1178172Simp/*- 2178172Simp * This file is in the public domain. 3178172Simp * 4178172Simp * from: src/sys/alpha/include/pmc_mdep.h,v 1.2 2005/06/09 19:45:06 jkoshy 5178172Simp * $FreeBSD$ 6178172Simp */ 7178172Simp 8178172Simp#ifndef _MACHINE_PMC_MDEP_H_ 9178172Simp#define _MACHINE_PMC_MDEP_H_ 10178172Simp 11233628Sfabient#define PMC_MDEP_CLASS_INDEX_MIPS 1 12204635Sgnn 13178172Simpunion pmc_md_op_pmcallocate { 14178172Simp uint64_t __pad[4]; 15178172Simp}; 16178172Simp 17178172Simp/* Logging */ 18233319Sgonzo#if defined(__mips_n64) 19233319Sgonzo#define PMCLOG_READADDR PMCLOG_READ64 20233319Sgonzo#define PMCLOG_EMITADDR PMCLOG_EMIT64 21233319Sgonzo#else 22204635Sgnn#define PMCLOG_READADDR PMCLOG_READ32 23204635Sgnn#define PMCLOG_EMITADDR PMCLOG_EMIT32 24233319Sgonzo#endif 25178172Simp 26178172Simp#if _KERNEL 27233319Sgonzo 28233319Sgonzo/* 29233319Sgonzo * MIPS event codes are encoded with a select bit. The 30233319Sgonzo * select bit is used when writing to CP0 so that we 31233319Sgonzo * can select either counter 0/2 or 1/3. The cycle 32233319Sgonzo * and instruction counters are special in that they 33233319Sgonzo * can be counted on either 0/2 or 1/3. 34233319Sgonzo */ 35233319Sgonzo 36233319Sgonzo#define MIPS_CTR_ALL 255 /* Count events in any counter. */ 37233319Sgonzo#define MIPS_CTR_0 0 /* Counter 0 Event */ 38233319Sgonzo#define MIPS_CTR_1 1 /* Counter 1 Event */ 39233319Sgonzo 40233319Sgonzostruct mips_event_code_map { 41233319Sgonzo uint32_t pe_ev; /* enum value */ 42233319Sgonzo uint8_t pe_counter; /* Which counter this can be counted in. */ 43233319Sgonzo uint8_t pe_code; /* numeric code */ 44233319Sgonzo}; 45233319Sgonzo 46233319Sgonzostruct mips_pmc_spec { 47233319Sgonzo uint32_t ps_cpuclass; 48233319Sgonzo uint32_t ps_cputype; 49233319Sgonzo uint32_t ps_capabilities; 50233319Sgonzo int ps_counter_width; 51233319Sgonzo}; 52233319Sgonzo 53178172Simpunion pmc_md_pmc { 54233319Sgonzo uint32_t pm_mips_evsel; 55178172Simp}; 56178172Simp 57204635Sgnn#define PMC_TRAPFRAME_TO_PC(TF) ((TF)->pc) 58204635Sgnn 59233319Sgonzoextern const struct mips_event_code_map mips_event_codes[]; 60233319Sgonzoextern const int mips_event_codes_size; 61233319Sgonzoextern int mips_npmcs; 62233319Sgonzoextern struct mips_pmc_spec mips_pmc_spec; 63233319Sgonzo 64204635Sgnn/* 65204635Sgnn * Prototypes 66204635Sgnn */ 67233319Sgonzostruct pmc_mdep *pmc_mips_initialize(void); 68233319Sgonzovoid pmc_mips_finalize(struct pmc_mdep *_md); 69233319Sgonzo 70233319Sgonzo/* 71233319Sgonzo * CPU-specific functions 72233319Sgonzo */ 73233319Sgonzo 74233319Sgonzouint32_t mips_get_perfctl(int cpu, int ri, uint32_t event, uint32_t caps); 75233319Sgonzouint64_t mips_pmcn_read(unsigned int pmc); 76233319Sgonzouint64_t mips_pmcn_write(unsigned int pmc, uint64_t v); 77233319Sgonzo 78204635Sgnn#endif /* _KERNEL */ 79204635Sgnn 80178172Simp#endif /* !_MACHINE_PMC_MDEP_H_ */ 81