1/* $OpenBSD: mips_opcode.h,v 1.2 1999/01/27 04:46:05 imp Exp $ */ 2 3/*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from: @(#)mips_opcode.h 8.1 (Berkeley) 6/10/93 35 * JNPR: mips_opcode.h,v 1.1 2006/08/07 05:38:57 katta 36 * $FreeBSD$ 37 */ 38 39#ifndef _MACHINE_MIPS_OPCODE_H_ 40#define _MACHINE_MIPS_OPCODE_H_ 41 42/* 43 * Define the instruction formats and opcode values for the 44 * MIPS instruction set. 45 */ 46#include <machine/endian.h> 47 48/* 49 * Define the instruction formats. 50 */ 51typedef union { 52 unsigned word; 53 54#if BYTE_ORDER == BIG_ENDIAN 55 struct { 56 unsigned op: 6; 57 unsigned rs: 5; 58 unsigned rt: 5; 59 unsigned imm: 16; 60 } IType; 61 62 struct { 63 unsigned op: 6; 64 unsigned target: 26; 65 } JType; 66 67 struct { 68 unsigned op: 6; 69 unsigned rs: 5; 70 unsigned rt: 5; 71 unsigned rd: 5; 72 unsigned shamt: 5; 73 unsigned func: 6; 74 } RType; 75 76 struct { 77 unsigned op: 6; /* always '0x11' */ 78 unsigned : 1; /* always '1' */ 79 unsigned fmt: 4; 80 unsigned ft: 5; 81 unsigned fs: 5; 82 unsigned fd: 5; 83 unsigned func: 6; 84 } FRType; 85#endif 86#if BYTE_ORDER == LITTLE_ENDIAN 87 struct { 88 unsigned imm: 16; 89 unsigned rt: 5; 90 unsigned rs: 5; 91 unsigned op: 6; 92 } IType; 93 94 struct { 95 unsigned target: 26; 96 unsigned op: 6; 97 } JType; 98 99 struct { 100 unsigned func: 6; 101 unsigned shamt: 5; 102 unsigned rd: 5; 103 unsigned rt: 5; 104 unsigned rs: 5; 105 unsigned op: 6; 106 } RType; 107 108 struct { 109 unsigned func: 6; 110 unsigned fd: 5; 111 unsigned fs: 5; 112 unsigned ft: 5; 113 unsigned fmt: 4; 114 unsigned : 1; /* always '1' */ 115 unsigned op: 6; /* always '0x11' */ 116 } FRType; 117#endif 118} InstFmt; 119 120/* instruction field decoding macros */ 121#define MIPS_INST_OPCODE(val) (val >> 26) 122#define MIPS_INST_RS(val) ((val & 0x03e00000) >> 21) 123#define MIPS_INST_RT(val) ((val & 0x001f0000) >> 16) 124#define MIPS_INST_IMM(val) ((val & 0x0000ffff)) 125 126#define MIPS_INST_RD(val) ((val & 0x0000f800) >> 11) 127#define MIPS_INST_SA(val) ((val & 0x000007c0) >> 6) 128#define MIPS_INST_FUNC(val) (val & 0x0000003f) 129 130#define MIPS_INST_INDEX(val) (val & 0x03ffffff) 131 132/* 133 * the mips opcode and function table use a 3bit row and 3bit col 134 * number we define the following macro for easy transcribing 135 */ 136 137#define MIPS_OPCODE(r, c) (((r & 0x07) << 3) | (c & 0x07)) 138 139 140/* 141 * Values for the 'op' field. 142 */ 143#define OP_SPECIAL 000 144#define OP_BCOND 001 145#define OP_J 002 146#define OP_JAL 003 147#define OP_BEQ 004 148#define OP_BNE 005 149#define OP_BLEZ 006 150#define OP_BGTZ 007 151 152#define OP_REGIMM OP_BCOND 153 154#define OP_ADDI 010 155#define OP_ADDIU 011 156#define OP_SLTI 012 157#define OP_SLTIU 013 158#define OP_ANDI 014 159#define OP_ORI 015 160#define OP_XORI 016 161#define OP_LUI 017 162 163#define OP_COP0 020 164#define OP_COP1 021 165#define OP_COP2 022 166#define OP_COP3 023 167#define OP_BEQL 024 168#define OP_BNEL 025 169#define OP_BLEZL 026 170#define OP_BGTZL 027 171 172#define OP_COP1X OP_COP3 173 174#define OP_DADDI 030 175#define OP_DADDIU 031 176#define OP_LDL 032 177#define OP_LDR 033 178 179#define OP_SPECIAL2 034 180#define OP_JALX 035 181 182#define OP_SPECIAL3 037 183 184#define OP_LB 040 185#define OP_LH 041 186#define OP_LWL 042 187#define OP_LW 043 188#define OP_LBU 044 189#define OP_LHU 045 190#define OP_LWR 046 191#define OP_LWU 047 192 193#define OP_SB 050 194#define OP_SH 051 195#define OP_SWL 052 196#define OP_SW 053 197#define OP_SDL 054 198#define OP_SDR 055 199#define OP_SWR 056 200#define OP_CACHE 057 201 202#define OP_LL 060 203#define OP_LWC1 061 204#define OP_LWC2 062 205#define OP_LWC3 063 206#define OP_LLD 064 207#define OP_LDC1 065 208#define OP_LDC2 066 209#define OP_LD 067 210 211#define OP_PREF OP_LWC3 212 213#define OP_SC 070 214#define OP_SWC1 071 215#define OP_SWC2 072 216#define OP_SWC3 073 217#define OP_SCD 074 218#define OP_SDC1 075 219#define OP_SDC2 076 220#define OP_SD 077 221 222/* 223 * Values for the 'func' field when 'op' == OP_SPECIAL. 224 */ 225#define OP_SLL 000 226#define OP_MOVCI 001 227#define OP_SRL 002 228#define OP_SRA 003 229#define OP_SLLV 004 230#define OP_SRLV 006 231#define OP_SRAV 007 232 233#define OP_F_SLL OP_SLL 234#define OP_F_MOVCI OP_MOVCI 235#define OP_F_SRL OP_SRL 236#define OP_F_SRA OP_SRA 237#define OP_F_SLLV OP_SLLV 238#define OP_F_SRLV OP_SRLV 239#define OP_F_SRAV OP_SRAV 240 241#define OP_JR 010 242#define OP_JALR 011 243#define OP_MOVZ 012 244#define OP_MOVN 013 245#define OP_SYSCALL 014 246#define OP_BREAK 015 247#define OP_SYNC 017 248 249#define OP_F_JR OP_JR 250#define OP_F_JALR OP_JALR 251#define OP_F_MOVZ OP_MOVZ 252#define OP_F_MOVN OP_MOVN 253#define OP_F_SYSCALL OP_SYSCALL 254#define OP_F_BREAK OP_BREAK 255#define OP_F_SYNC OP_SYNC 256 257#define OP_MFHI 020 258#define OP_MTHI 021 259#define OP_MFLO 022 260#define OP_MTLO 023 261#define OP_DSLLV 024 262#define OP_DSRLV 026 263#define OP_DSRAV 027 264 265#define OP_F_MFHI OP_MFHI 266#define OP_F_MTHI OP_MTHI 267#define OP_F_MFLO OP_MFLO 268#define OP_F_MTLO OP_MTLO 269#define OP_F_DSLLV OP_DSLLV 270#define OP_F_DSRLV OP_DSRLV 271#define OP_F_DSRAV OP_DSRAV 272 273#define OP_MULT 030 274#define OP_MULTU 031 275#define OP_DIV 032 276#define OP_DIVU 033 277#define OP_DMULT 034 278#define OP_DMULTU 035 279#define OP_DDIV 036 280#define OP_DDIVU 037 281 282#define OP_F_MULT OP_MULT 283#define OP_F_MULTU OP_MULTU 284#define OP_F_DIV OP_DIV 285#define OP_F_DIVU OP_DIVU 286#define OP_F_DMULT OP_DMULT 287#define OP_F_DMULTU OP_DMULTU 288#define OP_F_DDIV OP_DDIV 289#define OP_F_DDIVU OP_DDIVU 290 291#define OP_ADD 040 292#define OP_ADDU 041 293#define OP_SUB 042 294#define OP_SUBU 043 295#define OP_AND 044 296#define OP_OR 045 297#define OP_XOR 046 298#define OP_NOR 047 299 300#define OP_F_ADD OP_ADD 301#define OP_F_ADDU OP_ADDU 302#define OP_F_SUB OP_SUB 303#define OP_F_SUBU OP_SUBU 304#define OP_F_AND OP_AND 305#define OP_F_OR OP_OR 306#define OP_F_XOR OP_XOR 307#define OP_F_NOR OP_NOR 308 309#define OP_SLT 052 310#define OP_SLTU 053 311#define OP_DADD 054 312#define OP_DADDU 055 313#define OP_DSUB 056 314#define OP_DSUBU 057 315 316#define OP_F_SLT OP_SLT 317#define OP_F_SLTU OP_SLTU 318#define OP_F_DADD OP_DADD 319#define OP_F_DADDU OP_DADDU 320#define OP_F_DSUB OP_DSUB 321#define OP_F_DSUBU OP_DSUBU 322 323#define OP_TGE 060 324#define OP_TGEU 061 325#define OP_TLT 062 326#define OP_TLTU 063 327#define OP_TEQ 064 328#define OP_TNE 066 329 330#define OP_F_TGE OP_TGE 331#define OP_F_TGEU OP_TGEU 332#define OP_F_TLT OP_TLT 333#define OP_F_TLTU OP_TLTU 334#define OP_F_TEQ OP_TEQ 335#define OP_F_TNE OP_TNE 336 337#define OP_DSLL 070 338#define OP_DSRL 072 339#define OP_DSRA 073 340#define OP_DSLL32 074 341#define OP_DSRL32 076 342#define OP_DSRA32 077 343 344#define OP_F_DSLL OP_DSLL 345#define OP_F_DSRL OP_DSRL 346#define OP_F_DSRA OP_DSRA 347#define OP_F_DSLL32 OP_DSLL32 348#define OP_F_DSRL32 OP_DSRL32 349#define OP_F_DSRA32 OP_DSRA32 350 351/* 352 * The REGIMM - register immediate instructions are further 353 * decoded using this table that has 2bit row numbers, hence 354 * a need for a new helper macro. 355 */ 356 357#define MIPS_ROP(r, c) ((r & 0x03) << 3) | (c & 0x07) 358 359/* 360 * Values for the 'func' field when 'op' == OP_BCOND. 361 */ 362#define OP_BLTZ 000 363#define OP_BGEZ 001 364#define OP_BLTZL 002 365#define OP_BGEZL 003 366 367#define OP_R_BLTZ OP_BLTZ 368#define OP_R_BGEZ OP_BGEZ 369#define OP_R_BLTZL OP_BLTZL 370#define OP_R_BGEZL OP_BGEZL 371 372#define OP_TGEI 010 373#define OP_TGEIU 011 374#define OP_TLTI 012 375#define OP_TLTIU 013 376#define OP_TEQI 014 377#define OP_TNEI 016 378 379#define OP_R_TGEI OP_TGEI 380#define OP_R_TGEIU OP_TGEIU 381#define OP_R_TLTI OP_TLTI 382#define OP_R_TLTIU OP_TLTIU 383#define OP_R_TEQI OP_TEQI 384#define OP_R_TNEI OP_TNEI 385 386#define OP_BLTZAL 020 387#define OP_BGEZAL 021 388#define OP_BLTZALL 022 389#define OP_BGEZALL 023 390 391#define OP_R_BLTZAL OP_BLTZAL 392#define OP_R_BGEZAL OP_BGEZAL 393#define OP_R_BLTZALL OP_BLTZALL 394#define OP_R_BGEZALL OP_BGEZALL 395 396/* 397 * Values for the 'func' field when 'op' == OP_SPECIAL3. 398 */ 399#define OP_RDHWR 073 400 401/* 402 * Values for the 'rs' field when 'op' == OP_COPz. 403 */ 404#define OP_MF 000 405#define OP_DMF 001 406#define OP_MT 004 407#define OP_DMT 005 408#define OP_BCx 010 409#define OP_BCy 014 410#define OP_CF 002 411#define OP_CT 006 412 413/* 414 * Values for the 'rt' field when 'op' == OP_COPz. 415 */ 416#define COPz_BC_TF_MASK 0x01 417#define COPz_BC_TRUE 0x01 418#define COPz_BC_FALSE 0x00 419#define COPz_BCL_TF_MASK 0x02 420#define COPz_BCL_TRUE 0x02 421#define COPz_BCL_FALSE 0x00 422 423#endif /* !_MACHINE_MIPS_OPCODE_H_ */ 424