1285079Sadrian# The Archer C7 v2 is based on the AP135-020 board, with 2285079Sadrian# TP-Link specific bits (eg flash layout, MAC address, etc.) 3285079Sadrian 4285079Sadrian# $FreeBSD$ 5285079Sadrian 6285079Sadrian# QCA955X_ETH_CFG_RGMII_EN (1 << 0) 7285079Sadrianhint.qca955x_gmac.0.gmac_cfg=0x1 8285079Sadrian 9285079Sadrian# Use base mac address for wifi; +1 and +2 for arge0/arge1. 10285079Sadrianhint.ar71xx.0.eeprom_mac_addr=0x1f01fc00 11285079Sadrianhint.ar71xx.0.eeprom_mac_isascii=0 12285079Sadrian 13285079Sadrianhint.ar71xx_mac_map.0.devid=ath 14285079Sadrianhint.ar71xx_mac_map.0.unitid=0 15285079Sadrianhint.ar71xx_mac_map.0.offset=0 16285079Sadrianhint.ar71xx_mac_map.0.is_local=0 17285079Sadrian 18285079Sadrianhint.ar71xx_mac_map.1.devid=arge 19285079Sadrianhint.ar71xx_mac_map.1.unitid=0 20285079Sadrianhint.ar71xx_mac_map.1.offset=1 21285079Sadrianhint.ar71xx_mac_map.1.is_local=0 22285079Sadrian 23285079Sadrianhint.ar71xx_mac_map.2.devid=arge 24285079Sadrianhint.ar71xx_mac_map.2.unitid=1 25285079Sadrianhint.ar71xx_mac_map.2.offset=2 26285079Sadrianhint.ar71xx_mac_map.2.is_local=0 27285079Sadrian 28285079Sadrian# mdiobus0 on arge0 29285079Sadrianhint.argemdio.0.at="nexus0" 30285079Sadrianhint.argemdio.0.maddr=0x19000000 31285079Sadrianhint.argemdio.0.msize=0x1000 32285079Sadrianhint.argemdio.0.order=0 33285079Sadrian 34285079Sadrian# mdiobus1 on arge1 - required to bring up arge1? 35285079Sadrianhint.argemdio.1.at="nexus0" 36285079Sadrianhint.argemdio.1.maddr=0x1a000000 37285079Sadrianhint.argemdio.1.msize=0x1000 38285079Sadrianhint.argemdio.1.order=0 39285079Sadrian 40285079Sadrian# AR8327 - connected via mdiobus0 on arge0 41285079Sadrianhint.arswitch.0.at="mdio0" 42285079Sadrianhint.arswitch.0.is_7240=0 # definitely not the internal switch! 43285079Sadrianhint.arswitch.0.is_9340=0 # not the internal switch! 44285079Sadrianhint.arswitch.0.numphys=5 # all ports are PHYs 45285079Sadrianhint.arswitch.0.phy4cpu=0 46285079Sadrianhint.arswitch.0.is_rgmii=0 # not needed 47285079Sadrianhint.arswitch.0.is_gmii=0 # not needed 48285079Sadrian 49285079Sadrian# This is where it gets a bit odd. port 0 and port 6 are CPU ports. 50285079Sadrian# The current code only supports one CPU port. So hm, what should 51285079Sadrian# we do to hook PAD6 up to be RGMII but a PHY, not a MAC? 52285079Sadrian 53285079Sadrian# The other trick - how do we get arge1 (hooked up to GMAC0) to work? 54285079Sadrian# That's currently supposed to be hooked up to CPU port 0. 55285079Sadrian 56285079Sadrian# Other AR8327 configuration parameters 57285079Sadrian 58285079Sadrian# AP136-020 parameters 59285079Sadrian 60285079Sadrian# GMAC0 AR8327 -> GMAC1 (arge1) SoC, SGMII 61285079Sadrian 62285079Sadrian# AR8327_PAD_MAC_SGMII 63285079Sadrianhint.arswitch.0.pad.0.mode=3 64285079Sadrian#hint.arswitch.0.pad.0.rxclk_delay_sel=0 65285079Sadrianhint.arswitch.0.pad.0.sgmii_delay_en=1 66285079Sadrian 67285079Sadrian# GMAC6 AR8327 -> GMAC0 (arge0) SoC, RGMII 68285079Sadrian 69285079Sadrian# AR8327_PAD_MAC_RGMII 70285079Sadrian# XXX I think this hooks it up to the internal MAC6 71285079Sadrianhint.arswitch.0.pad.6.mode=6 72285079Sadrianhint.arswitch.0.pad.6.txclk_delay_en=1 73285079Sadrianhint.arswitch.0.pad.6.rxclk_delay_en=1 74285079Sadrian# AR8327_CLK_DELAY_SEL1 75285079Sadrianhint.arswitch.0.pad.6.txclk_delay_sel=1 76285079Sadrian# AR8327_CLK_DELAY_SEL2 77285079Sadrianhint.arswitch.0.pad.6.rxclk_delay_sel=2 78285079Sadrian 79285079Sadrian# XXX there's no LED management just yet! 80285079Sadrianhint.arswitch.0.led.ctrl0=0xc737c737 81285079Sadrianhint.arswitch.0.led.ctrl1=0x00000000 82285079Sadrianhint.arswitch.0.led.ctrl2=0x00000000 83285079Sadrianhint.arswitch.0.led.ctrl3=0x00c30c00 84285079Sadrianhint.arswitch.0.led.open_drain=0 85285079Sadrian 86285079Sadrian# force_link=1 is required for the rest of the parameters 87285079Sadrian# to be configured. 88285079Sadrianhint.arswitch.0.port.0.force_link=1 89285079Sadrianhint.arswitch.0.port.0.speed=1000 90285079Sadrianhint.arswitch.0.port.0.duplex=1 91285079Sadrianhint.arswitch.0.port.0.txpause=1 92285079Sadrianhint.arswitch.0.port.0.rxpause=1 93285079Sadrian 94285079Sadrian# force_link=1 is required for the rest of the parameters 95285079Sadrian# to be configured. 96285079Sadrianhint.arswitch.0.port.6.force_link=1 97285079Sadrianhint.arswitch.0.port.6.speed=1000 98285079Sadrianhint.arswitch.0.port.6.duplex=1 99285079Sadrianhint.arswitch.0.port.6.txpause=1 100285079Sadrianhint.arswitch.0.port.6.rxpause=1 101285079Sadrian 102285079Sadrian# arge0 - hooked up to AR8327 GMAC6, RGMII 103285079Sadrian# set at 1000/full to the switch. 104285079Sadrian# so, lock both sides of this connect up to 1000/full; 105285079Sadrian# if_arge thus wont change the PLL configuration 106285079Sadrian# upon a link status change. 107285079Sadrianhint.arge.0.phymask=0x0 108285079Sadrianhint.arge.0.miimode=3 # RGMII 109285079Sadrianhint.arge.0.media=1000 110285079Sadrianhint.arge.0.fduplex=1 111285079Sadrianhint.arge.0.pll_1000=0x56000000 112285079Sadrian 113285079Sadrian# MAC for arge0 is the first 6 bytes of the ART 114285079Sadrianhint.arge.0.eeprommac=0x1fff0000 115285079Sadrian 116285079Sadrian# arge1 - lock up to 1000/full 117285079Sadrianhint.arge.1.phymask=0x0 118285079Sadrianhint.arge.1.media=1000 119285079Sadrianhint.arge.1.fduplex=1 120285079Sadrianhint.arge.1.miimode=5 # SGMII 121285079Sadrianhint.arge.1.pll_1000=0x03000101 122285079Sadrian 123285079Sadrian# MAC for arge1 is the second 6 bytes of the ART 124285079Sadrianhint.arge.1.eeprommac=0x1fff0006 125285079Sadrian 126285079Sadrian# ath0: Where the ART is - last 64k in the flash 127285079Sadrianhint.ath.0.eepromaddr=0x1fff0000 128285079Sadrianhint.ath.0.eepromsize=16384 129285079Sadrian 130285079Sadrian# ath1: it's different; it's a PCIe attached device, so 131285079Sadrian# we instead need to teach the PCIe bridge code about it 132285079Sadrian# (ie, the 'early pci fixup' stuff that programs the PCIe 133285079Sadrian# host registers on the NIC) and then we teach ath where 134285079Sadrian# to find it. 135285079Sadrian 136285079Sadrian# ath1 hint - pcie slot 0 137285079Sadrian# hint.pcib.0.bus.0.0.0.ath_fixup_addr=0x1fff4000 138285079Sadrian# hint.pcib.0.bus.0.0.0.ath_fixup_size=16384 139285079Sadrian 140285079Sadrian# ath0 - eeprom comes from here 141285079Sadrian# hint.ath.1.eeprom_firmware="pcib.0.bus.0.0.0.eeprom_firmware" 142285079Sadrian 143285079Sadrian# Flash layout - the tplink layout differs to what's passed 144285079Sadrian# in via the kernel environment. What's passed in is based on 145285079Sadrian# the AP135, but.. well, TP-Link. 146285079Sadrian 147285079Sadrian# 128 KiB u-boot 148285079Sadrianhint.map.0.at="flash/spi0" 149285079Sadrianhint.map.0.start=0x00000000 150285079Sadrianhint.map.0.end=0x00020000 # 128k u-boot 151285079Sadrianhint.map.0.name="u-boot" 152285079Sadrianhint.map.0.readonly=1 153285079Sadrian 154285079Sadrian# Kernel 155285079Sadrianhint.map.1.at="flash/spi0" 156285079Sadrianhint.map.1.start=0x00020000 157285079Sadrianhint.map.1.end="search:0x00020000:0x10000:.!/bin/sh" 158285079Sadrianhint.map.1.name="kernel" 159285079Sadrianhint.map.1.readonly=1 160285079Sadrian 161285079Sadrian# Root 162285079Sadrianhint.map.2.at="flash/spi0" 163285079Sadrianhint.map.2.start="search:0x00020000:0x10000:.!/bin/sh" 164285079Sadrianhint.map.2.end=0x007d0000 165285079Sadrianhint.map.2.name="rootfs" 166285079Sadrianhint.map.2.readonly=1 167285079Sadrian 168285079Sadrian# 64KiB cfg 169285079Sadrianhint.map.4.at="flash/spi0" 170285079Sadrianhint.map.4.start=0x00fe0000 171285079Sadrianhint.map.4.end=0x00ff0000 172285079Sadrianhint.map.4.name="cfg" 173285079Sadrianhint.map.4.readonly=0 174285079Sadrian 175285079Sadrian# 64KiB ART 176285079Sadrianhint.map.6.at="flash/spi0" 177285079Sadrianhint.map.6.start=0x00ff0000 178285079Sadrianhint.map.6.end=0x01000000 # 64k ART 179285079Sadrianhint.map.6.name="ART" 180285079Sadrianhint.map.6.readonly=1 181285079Sadrian 182285079Sadrian# TODO: GPIO config 183285079Sadrian# These are the GPIO LEDs and buttons which can be software controlled. 184285079Sadrianhint.gpio.0.pinmask=0x00600000 185285079Sadrian 186285079Sadrian# Enable GPIO21, GPIO22 output and high - for USB power 187285079Sadrianhint.gpio.0.pinon=0x00600000 188285079Sadrian 189285079Sadrian# TODO: GPIO pin config: 190285079Sadrian# LED_WLAN2G 12 191285079Sadrian# BTN_RFKILL 13 192285079Sadrian# LED_SYSTEM 14 193285079Sadrian# LED_QSS 15 194285079Sadrian# BTN_RESET 16 195285079Sadrian# LED_WLAN5G 17 196285079Sadrian# LED_USB1 18 197285079Sadrian# LED_USB2 19 198285079Sadrian# USB2_POWER 21 199285079Sadrian# USB1_POWER 22 200285079Sadrian 201285079Sadrian# TODO: PCIe isn't showing link; maybe uboot isn't initialising 202