1# The Archer C7 v2 is based on the AP135-020 board, with 2# TP-Link specific bits (eg flash layout, MAC address, etc.) 3 4# $FreeBSD$ 5 6# QCA955X_ETH_CFG_RGMII_EN (1 << 0) 7hint.qca955x_gmac.0.gmac_cfg=0x1 8 9# Use base mac address for wifi; +1 and +2 for arge0/arge1. 10hint.ar71xx.0.eeprom_mac_addr=0x1f01fc00 11hint.ar71xx.0.eeprom_mac_isascii=0 12 13hint.ar71xx_mac_map.0.devid=ath 14hint.ar71xx_mac_map.0.unitid=0 15hint.ar71xx_mac_map.0.offset=0 16hint.ar71xx_mac_map.0.is_local=0 17 18hint.ar71xx_mac_map.1.devid=arge 19hint.ar71xx_mac_map.1.unitid=0 20hint.ar71xx_mac_map.1.offset=1 21hint.ar71xx_mac_map.1.is_local=0 22 23hint.ar71xx_mac_map.2.devid=arge 24hint.ar71xx_mac_map.2.unitid=1 25hint.ar71xx_mac_map.2.offset=2 26hint.ar71xx_mac_map.2.is_local=0 27 28# mdiobus0 on arge0 29hint.argemdio.0.at="nexus0" 30hint.argemdio.0.maddr=0x19000000 31hint.argemdio.0.msize=0x1000 32hint.argemdio.0.order=0 33 34# mdiobus1 on arge1 - required to bring up arge1? 35hint.argemdio.1.at="nexus0" 36hint.argemdio.1.maddr=0x1a000000 37hint.argemdio.1.msize=0x1000 38hint.argemdio.1.order=0 39 40# AR8327 - connected via mdiobus0 on arge0 41hint.arswitch.0.at="mdio0" 42hint.arswitch.0.is_7240=0 # definitely not the internal switch! 43hint.arswitch.0.is_9340=0 # not the internal switch! 44hint.arswitch.0.numphys=5 # all ports are PHYs 45hint.arswitch.0.phy4cpu=0 46hint.arswitch.0.is_rgmii=0 # not needed 47hint.arswitch.0.is_gmii=0 # not needed 48 49# This is where it gets a bit odd. port 0 and port 6 are CPU ports. 50# The current code only supports one CPU port. So hm, what should 51# we do to hook PAD6 up to be RGMII but a PHY, not a MAC? 52 53# The other trick - how do we get arge1 (hooked up to GMAC0) to work? 54# That's currently supposed to be hooked up to CPU port 0. 55 56# Other AR8327 configuration parameters 57 58# AP136-020 parameters 59 60# GMAC0 AR8327 -> GMAC1 (arge1) SoC, SGMII 61 62# AR8327_PAD_MAC_SGMII 63hint.arswitch.0.pad.0.mode=3 64#hint.arswitch.0.pad.0.rxclk_delay_sel=0 65hint.arswitch.0.pad.0.sgmii_delay_en=1 66 67# GMAC6 AR8327 -> GMAC0 (arge0) SoC, RGMII 68 69# AR8327_PAD_MAC_RGMII 70# XXX I think this hooks it up to the internal MAC6 71hint.arswitch.0.pad.6.mode=6 72hint.arswitch.0.pad.6.txclk_delay_en=1 73hint.arswitch.0.pad.6.rxclk_delay_en=1 74# AR8327_CLK_DELAY_SEL1 75hint.arswitch.0.pad.6.txclk_delay_sel=1 76# AR8327_CLK_DELAY_SEL2 77hint.arswitch.0.pad.6.rxclk_delay_sel=2 78 79# XXX there's no LED management just yet! 80hint.arswitch.0.led.ctrl0=0xc737c737 81hint.arswitch.0.led.ctrl1=0x00000000 82hint.arswitch.0.led.ctrl2=0x00000000 83hint.arswitch.0.led.ctrl3=0x00c30c00 84hint.arswitch.0.led.open_drain=0 85 86# force_link=1 is required for the rest of the parameters 87# to be configured. 88hint.arswitch.0.port.0.force_link=1 89hint.arswitch.0.port.0.speed=1000 90hint.arswitch.0.port.0.duplex=1 91hint.arswitch.0.port.0.txpause=1 92hint.arswitch.0.port.0.rxpause=1 93 94# force_link=1 is required for the rest of the parameters 95# to be configured. 96hint.arswitch.0.port.6.force_link=1 97hint.arswitch.0.port.6.speed=1000 98hint.arswitch.0.port.6.duplex=1 99hint.arswitch.0.port.6.txpause=1 100hint.arswitch.0.port.6.rxpause=1 101 102# arge0 - hooked up to AR8327 GMAC6, RGMII 103# set at 1000/full to the switch. 104# so, lock both sides of this connect up to 1000/full; 105# if_arge thus wont change the PLL configuration 106# upon a link status change. 107hint.arge.0.phymask=0x0 108hint.arge.0.miimode=3 # RGMII 109hint.arge.0.media=1000 110hint.arge.0.fduplex=1 111hint.arge.0.pll_1000=0x56000000 112 113# MAC for arge0 is the first 6 bytes of the ART 114hint.arge.0.eeprommac=0x1fff0000 115 116# arge1 - lock up to 1000/full 117hint.arge.1.phymask=0x0 118hint.arge.1.media=1000 119hint.arge.1.fduplex=1 120hint.arge.1.miimode=5 # SGMII 121hint.arge.1.pll_1000=0x03000101 122 123# MAC for arge1 is the second 6 bytes of the ART 124hint.arge.1.eeprommac=0x1fff0006 125 126# ath0: Where the ART is - last 64k in the flash 127hint.ath.0.eepromaddr=0x1fff0000 128hint.ath.0.eepromsize=16384 129 130# ath1: it's different; it's a PCIe attached device, so 131# we instead need to teach the PCIe bridge code about it 132# (ie, the 'early pci fixup' stuff that programs the PCIe 133# host registers on the NIC) and then we teach ath where 134# to find it. 135 136# ath1 hint - pcie slot 0 137# hint.pcib.0.bus.0.0.0.ath_fixup_addr=0x1fff4000 138# hint.pcib.0.bus.0.0.0.ath_fixup_size=16384 139 140# ath0 - eeprom comes from here 141# hint.ath.1.eeprom_firmware="pcib.0.bus.0.0.0.eeprom_firmware" 142 143# Flash layout - the tplink layout differs to what's passed 144# in via the kernel environment. What's passed in is based on 145# the AP135, but.. well, TP-Link. 146 147# 128 KiB u-boot 148hint.map.0.at="flash/spi0" 149hint.map.0.start=0x00000000 150hint.map.0.end=0x00020000 # 128k u-boot 151hint.map.0.name="u-boot" 152hint.map.0.readonly=1 153 154# Kernel 155hint.map.1.at="flash/spi0" 156hint.map.1.start=0x00020000 157hint.map.1.end="search:0x00020000:0x10000:.!/bin/sh" 158hint.map.1.name="kernel" 159hint.map.1.readonly=1 160 161# Root 162hint.map.2.at="flash/spi0" 163hint.map.2.start="search:0x00020000:0x10000:.!/bin/sh" 164hint.map.2.end=0x007d0000 165hint.map.2.name="rootfs" 166hint.map.2.readonly=1 167 168# 64KiB cfg 169hint.map.4.at="flash/spi0" 170hint.map.4.start=0x00fe0000 171hint.map.4.end=0x00ff0000 172hint.map.4.name="cfg" 173hint.map.4.readonly=0 174 175# 64KiB ART 176hint.map.6.at="flash/spi0" 177hint.map.6.start=0x00ff0000 178hint.map.6.end=0x01000000 # 64k ART 179hint.map.6.name="ART" 180hint.map.6.readonly=1 181 182# TODO: GPIO config 183# These are the GPIO LEDs and buttons which can be software controlled. 184hint.gpio.0.pinmask=0x00600000 185 186# Enable GPIO21, GPIO22 output and high - for USB power 187hint.gpio.0.pinon=0x00600000 188 189# TODO: GPIO pin config: 190# LED_WLAN2G 12 191# BTN_RFKILL 13 192# LED_SYSTEM 14 193# LED_QSS 15 194# BTN_RESET 16 195# LED_WLAN5G 17 196# LED_USB1 18 197# LED_USB2 19 198# USB2_POWER 21 199# USB1_POWER 22 200 201# TODO: PCIe isn't showing link; maybe uboot isn't initialising 202