1 2# I'm assuming this is an AP135-020. The AP136-010 in openwrt has 3# the ethernet ports wired up to the switch in the reverse way. 4 5# $FreeBSD$ 6 7# QCA955X_ETH_CFG_RGMII_EN (1 << 0) 8hint.qca955x_gmac.0.gmac_cfg=0x1 9 10# Use this to derive ath0 from arge0 MAC address. 11# 0x1ffe0004 is the arge0 MAC; but it's also the "unit MAC". 12# So make that the ath0 MAC, and make arge0 -1 from that. 13# ath0: offset 0 14# arge0: offset -1 15# arge1: use +1 from the arge0 MAC, even though 16# there's a secondary MAC address configured in EEPROM 17# at 0x1ffe0018. 18hint.ar71xx.0.eeprom_mac_addr=0x1ffe0004 19hint.ar71xx.0.eeprom_mac_isascii=1 20 21hint.ar71xx_mac_map.0.devid=ath 22hint.ar71xx_mac_map.0.unitid=0 23hint.ar71xx_mac_map.0.offset=0 24hint.ar71xx_mac_map.0.is_local=0 25 26hint.ar71xx_mac_map.1.devid=arge 27hint.ar71xx_mac_map.1.unitid=0 28hint.ar71xx_mac_map.1.offset=-1 29hint.ar71xx_mac_map.1.is_local=0 30 31hint.ar71xx_mac_map.2.devid=arge 32hint.ar71xx_mac_map.2.unitid=1 33hint.ar71xx_mac_map.2.offset=1 34hint.ar71xx_mac_map.2.is_local=0 35 36# mdiobus0 on arge0 37hint.argemdio.0.at="nexus0" 38hint.argemdio.0.maddr=0x19000000 39hint.argemdio.0.msize=0x1000 40hint.argemdio.0.order=0 41 42# mdiobus1 on arge1 - required to bring up arge1? 43hint.argemdio.1.at="nexus0" 44hint.argemdio.1.maddr=0x1a000000 45hint.argemdio.1.msize=0x1000 46hint.argemdio.1.order=0 47 48# AR8327 - connected via mdiobus0 on arge0 49hint.arswitch.0.at="mdio0" 50hint.arswitch.0.is_7240=0 # definitely not the internal switch! 51hint.arswitch.0.is_9340=0 # not the internal switch! 52hint.arswitch.0.numphys=5 # all ports are PHYs 53hint.arswitch.0.phy4cpu=0 54hint.arswitch.0.is_rgmii=0 # not needed 55hint.arswitch.0.is_gmii=0 # not needed 56 57# This is where it gets a bit odd. port 0 and port 6 are CPU ports. 58# The current code only supports one CPU port. So hm, what should 59# we do to hook PAD6 up to be RGMII but a PHY, not a MAC? 60 61# The other trick - how do we get arge1 (hooked up to GMAC0) to work? 62# That's currently supposed to be hooked up to CPU port 0. 63 64# Other AR8327 configuration parameters 65 66# AP136-020 parameters 67 68# GMAC0 AR8327 -> GMAC1 (arge1) SoC, SGMII 69 70# AR8327_PAD_MAC_SGMII 71hint.arswitch.0.pad.0.mode=3 72#hint.arswitch.0.pad.0.rxclk_delay_sel=0 73hint.arswitch.0.pad.0.sgmii_delay_en=1 74 75# GMAC6 AR8327 -> GMAC0 (arge0) SoC, RGMII 76 77# AR8327_PAD_MAC_RGMII 78# XXX I think this hooks it up to the internal MAC6 79hint.arswitch.0.pad.6.mode=6 80hint.arswitch.0.pad.6.txclk_delay_en=1 81hint.arswitch.0.pad.6.rxclk_delay_en=1 82# AR8327_CLK_DELAY_SEL1 83hint.arswitch.0.pad.6.txclk_delay_sel=1 84# AR8327_CLK_DELAY_SEL2 85hint.arswitch.0.pad.6.rxclk_delay_sel=2 86 87# XXX there's no LED management just yet! 88hint.arswitch.0.led.ctrl0=0x00000000 89hint.arswitch.0.led.ctrl1=0xc737c737 90hint.arswitch.0.led.ctrl2=0x00000000 91hint.arswitch.0.led.ctrl3=0x00c30c00 92hint.arswitch.0.led.open_drain=1 93 94# force_link=1 is required for the rest of the parameters 95# to be configured. 96hint.arswitch.0.port.0.force_link=1 97hint.arswitch.0.port.0.speed=1000 98hint.arswitch.0.port.0.duplex=1 99hint.arswitch.0.port.0.txpause=1 100hint.arswitch.0.port.0.rxpause=1 101 102# force_link=1 is required for the rest of the parameters 103# to be configured. 104hint.arswitch.0.port.6.force_link=1 105hint.arswitch.0.port.6.speed=1000 106hint.arswitch.0.port.6.duplex=1 107hint.arswitch.0.port.6.txpause=1 108hint.arswitch.0.port.6.rxpause=1 109 110# arge0 - hooked up to AR8327 GMAC6, RGMII 111# set at 1000/full to the switch. 112# so, lock both sides of this connect up to 1000/full; 113# if_arge thus wont change the PLL configuration 114# upon a link status change. 115hint.arge.0.phymask=0x0 116hint.arge.0.miimode=3 # RGMII 117hint.arge.0.media=1000 118hint.arge.0.fduplex=1 119hint.arge.0.pll_1000=0x56000000 120# hint.arge.0.eeprommac=0x1ffe0004 121# hint.arge.0.readascii=1 122 123# arge1 - lock up to 1000/full 124hint.arge.1.phymask=0x0 125hint.arge.1.media=1000 126hint.arge.1.fduplex=1 127hint.arge.1.miimode=5 # SGMII 128hint.arge.1.pll_1000=0x03000101 129#hint.arge.1.eeprommac=0x1ffe0018 130#hint.arge.1.readascii=1 131 132# ath0: Where the ART is - last 64k in the flash 133# Note: ath0 MAC is default (00:11:22:33:44:55) and thus 134# requires replacing via the board MAC address map. 135hint.ath.0.eepromaddr=0x1fff0000 136hint.ath.0.eepromsize=16384 137 138# 256KiB u-boot 139hint.map.0.at="flash/spi0" 140hint.map.0.start=0x00000000 141hint.map.0.end=0x00040000 # 256k u-boot 142hint.map.0.name="u-boot" 143hint.map.0.readonly=1 144 145# kernel 146hint.map.1.at="flash/spi0" 147hint.map.1.start=0x00040000 148hint.map.1.end="search:0x00040000:0x10000:.!/bin/sh" 149hint.map.1.name="kernel" 150hint.map.1.readonly=1 151 152# rootfs 153hint.map.2.at="flash/spi0" 154hint.map.2.start="search:0x00040000:0x10000:.!/bin/sh" 155hint.map.2.end=0x007d0000 156hint.map.2.name="rootfs" 157hint.map.2.readonly=1 158 159# 64KiB cfg 160hint.map.3.at="flash/spi0" 161hint.map.3.start=0x007d0000 162hint.map.3.end=0x007e0000 163hint.map.3.name="cfg" 164hint.map.3.readonly=0 165 166# 8256 KiB mib0 167hint.map.4.at="flash/spi0" 168hint.map.4.start=0x007e0000 169hint.map.4.end=0x00ff0000 # 64k mib0 170hint.map.4.name="mib0" 171hint.map.4.readonly=1 172 173# 64KiB ART 174# XXX TODO: is this really here? 175hint.map.5.at="flash/spi0" 176hint.map.5.start=0x00ff0000 177hint.map.5.end=0x01000000 # 64k ART 178hint.map.5.name="ART" 179hint.map.5.readonly=1 180