1# This is a placeholder until the hardware support is complete. 2 3# I'm assuming this is an AP135-020. The AP136-010 in openwrt has 4# the ethernet ports wired up to the switch in the reverse way. 5 6# $FreeBSD$ 7 8# QCA955X_ETH_CFG_RGMII_EN (1 << 0) 9hint.qca955x_gmac.0.gmac_cfg=0x1 10 11# mdiobus0 on arge0 12hint.argemdio.0.at="nexus0" 13hint.argemdio.0.maddr=0x19000000 14hint.argemdio.0.msize=0x1000 15hint.argemdio.0.order=0 16 17# mdiobus1 on arge1 - required to bring up arge1? 18hint.argemdio.1.at="nexus0" 19hint.argemdio.1.maddr=0x1a000000 20hint.argemdio.1.msize=0x1000 21hint.argemdio.1.order=0 22 23# AR8327 - connected via mdiobus0 on arge0 24hint.arswitch.0.at="mdio0" 25hint.arswitch.0.is_7240=0 # definitely not the internal switch! 26hint.arswitch.0.is_9340=0 # not the internal switch! 27hint.arswitch.0.numphys=5 # all ports are PHYs 28hint.arswitch.0.phy4cpu=0 29hint.arswitch.0.is_rgmii=0 # not needed 30hint.arswitch.0.is_gmii=0 # not needed 31 32# This is where it gets a bit odd. port 0 and port 6 are CPU ports. 33# The current code only supports one CPU port. So hm, what should 34# we do to hook PAD6 up to be RGMII but a PHY, not a MAC? 35 36# The other trick - how do we get arge1 (hooked up to GMAC0) to work? 37# That's currently supposed to be hooked up to CPU port 0. 38 39# Other AR8327 configuration parameters 40 41# AP136-020 parameters 42 43# GMAC0 AR8327 -> GMAC1 (arge1) SoC, SGMII 44 45# AR8327_PAD_MAC_SGMII 46hint.arswitch.0.pad.0.mode=3 47#hint.arswitch.0.pad.0.rxclk_delay_sel=0 48hint.arswitch.0.pad.0.sgmii_delay_en=1 49 50# GMAC6 AR8327 -> GMAC0 (arge0) SoC, RGMII 51 52# AR8327_PAD_MAC_RGMII 53# XXX I think this hooks it up to the internal MAC6 54hint.arswitch.0.pad.6.mode=6 55hint.arswitch.0.pad.6.txclk_delay_en=1 56hint.arswitch.0.pad.6.rxclk_delay_en=1 57# AR8327_CLK_DELAY_SEL1 58hint.arswitch.0.pad.6.txclk_delay_sel=1 59# AR8327_CLK_DELAY_SEL2 60hint.arswitch.0.pad.6.rxclk_delay_sel=2 61 62# XXX there's no LED management just yet! 63hint.arswitch.0.led.ctrl0=0x00000000 64hint.arswitch.0.led.ctrl1=0xc737c737 65hint.arswitch.0.led.ctrl2=0x00000000 66hint.arswitch.0.led.ctrl3=0x00c30c00 67hint.arswitch.0.led.open_drain=1 68 69# force_link=1 is required for the rest of the parameters 70# to be configured. 71hint.arswitch.0.port.0.force_link=1 72hint.arswitch.0.port.0.speed=1000 73hint.arswitch.0.port.0.duplex=1 74hint.arswitch.0.port.0.txpause=1 75hint.arswitch.0.port.0.rxpause=1 76 77# force_link=1 is required for the rest of the parameters 78# to be configured. 79hint.arswitch.0.port.6.force_link=1 80hint.arswitch.0.port.6.speed=1000 81hint.arswitch.0.port.6.duplex=1 82hint.arswitch.0.port.6.txpause=1 83hint.arswitch.0.port.6.rxpause=1 84 85# arge0 - hooked up to AR8327 GMAC6, RGMII 86# set at 1000/full to the switch. 87# so, lock both sides of this connect up to 1000/full; 88# if_arge thus wont change the PLL configuration 89# upon a link status change. 90hint.arge.0.phymask=0x0 91hint.arge.0.miimode=3 # RGMII 92hint.arge.0.media=1000 93hint.arge.0.fduplex=1 94hint.arge.0.pll_1000=0x56000000 95 96# MAC for arge0 is the first 6 bytes of the ART 97hint.arge.0.eeprommac=0x1fff0000 98 99# arge1 - lock up to 1000/full 100hint.arge.1.phymask=0x0 101hint.arge.1.media=1000 102hint.arge.1.fduplex=1 103hint.arge.1.miimode=5 # SGMII 104hint.arge.1.pll_1000=0x03000101 105 106# MAC for arge1 is the second 6 bytes of the ART 107hint.arge.1.eeprommac=0x1fff0006 108 109# ath0: Where the ART is - last 64k in the flash 110hint.ath.0.eepromaddr=0x1fff0000 111hint.ath.0.eepromsize=16384 112 113# ath1: it's different; it's a PCIe attached device, so 114# we instead need to teach the PCIe bridge code about it 115# (ie, the 'early pci fixup' stuff that programs the PCIe 116# host registers on the NIC) and then we teach ath where 117# to find it. 118 119# ath1 hint - pcie slot 0 120# hint.pcib.0.bus.0.0.0.ath_fixup_addr=0x1fff4000 121# hint.pcib.0.bus.0.0.0.ath_fixup_size=16384 122 123# ath0 - eeprom comes from here 124# hint.ath.1.eeprom_firmware="pcib.0.bus.0.0.0.eeprom_firmware" 125 126# flash layout: 127# 128# bootargs=console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k(uImage),8256k(mib0),64k(ART) 129 130# The default flash layout isn't enough to fit a freebsd kernel 131# now, so the layout has been shuffled around. 132# 133# By default it's set to: 134# 256KB uboot, 64KB uboot-env, 6336KB rootfs, 1344KB kernel, 64KB cfg, 8256MB mib0, 64KB ART 135# With 'bootcmd=bootm 0x9f680000' in the environment. 136# 137# Instead, now let's make it: 138# 256KB uboot, 64KB uboot-env, 2048MB kernel, 6144MB rootfs, 7644KB mib0, 64KB cfg, 64KB ART 139# .. and then you change the boot env to be: 140# 'bootcmd=bootm 0x9f050000' 141 142# 256KiB u-boot 143hint.map.0.at="flash/spi0" 144hint.map.0.start=0x00000000 145hint.map.0.end=0x00040000 # 256k u-boot 146hint.map.0.name="u-boot" 147hint.map.0.readonly=1 148 149# 64KiB u-boot-env 150hint.map.1.at="flash/spi0" 151hint.map.1.start=0x00040000 152hint.map.1.end=0x00050000 # 64k u-boot-env 153hint.map.1.name="u-boot-env" 154hint.map.1.readonly=1 155 156# 2048KiB kernel 157hint.map.2.at="flash/spi0" 158hint.map.2.start=0x00050000 159hint.map.2.end=0x00250000 # 2048k rootfs 160hint.map.2.name="kernel" 161hint.map.2.readonly=1 162 163# 6144KiB rootfs 164hint.map.3.at="flash/spi0" 165hint.map.3.start=0x00250000 166hint.map.3.end=0x00850000 167hint.map.3.name="rootfs" 168hint.map.3.readonly=1 169 170# 7644KiB mib0 171hint.map.4.at="flash/spi0" 172hint.map.4.start=0x00850000 173hint.map.4.end=0x00fe0000 174hint.map.4.name="mib0" 175hint.map.4.readonly=0 176 177# 64KiB cfg 178hint.map.5.at="flash/spi0" 179hint.map.5.start=0x00fe0000 180hint.map.5.end=0x00ff0000 181hint.map.5.name="cfg" 182hint.map.5.readonly=0 183 184# 64KiB ART 185hint.map.6.at="flash/spi0" 186hint.map.6.start=0x00ff0000 187hint.map.6.end=0x01000000 # 64k ART 188hint.map.6.name="ART" 189hint.map.6.readonly=1 190