1# 2# This file adds to the values in AR933X_BASE.hints 3# 4# $FreeBSD$ 5 6# mdiobus on arge1 7hint.argemdio.0.at="nexus0" 8hint.argemdio.0.maddr=0x1a000000 9hint.argemdio.0.msize=0x1000 10hint.argemdio.0.order=0 11 12# There's no need to set the ar933x GMAC configuration bits. 13# This just creates a switch instance and correctly uses it. 14 15# Embedded Atheros Switch 16hint.arswitch.0.at="mdio0" 17 18# XXX this should really say it's an AR933x switch, as there 19# are some vlan specific differences here! 20hint.arswitch.0.is_7240=1 21hint.arswitch.0.numphys=4 22hint.arswitch.0.phy4cpu=1 # phy 4 is a "CPU" separate PHY 23hint.arswitch.0.is_rgmii=0 24hint.arswitch.0.is_gmii=1 # arge1 <-> switch PHY is GMII 25 26# arge0 - MII, autoneg, phy(4) 27hint.arge.0.phymask=0x10 # PHY4 28hint.arge.0.mdio=mdioproxy1 # .. off of the switch mdiobus 29 30# arge1 - GMII, 1000/full 31hint.arge.1.phymask=0x0 # No directly mapped PHYs 32hint.arge.1.media=1000 33hint.arge.1.fduplex=1 34 35# Where the ART is - last 64k in the flash 36# 0x9fff1000 ? 37hint.ath.0.eepromaddr=0x1fff0000 38hint.ath.0.eepromsize=16384 39 40# The board 16MiB flash layout in uboot env: 41# 42# 256k (uboot), 64k (uboot-env), 14336k (rootfs), 1600k (kernel), 64k (NVRAM), 64k (ART) 43 44# However, it boots from 0x9f050000, which is the front of the flsah! 45# Thus the kernel/rootfs are switched around. 46 47# 256KB 48hint.map.0.at="flash/spi0" 49hint.map.0.start=0x00000000 50hint.map.0.end=0x000040000 51hint.map.0.name="uboot" 52hint.map.0.readonly=1 53 54# 64KB 55hint.map.1.at="flash/spi0" 56hint.map.1.start=0x00040000 57hint.map.1.end=0x00050000 58hint.map.1.name="uboot-env" 59hint.map.1.readonly=0 60 61# 1600KB 62hint.map.2.at="flash/spi0" 63hint.map.2.start=0x00050000 64hint.map.2.end=0x001e0000 65hint.map.2.name="kernel" 66hint.map.2.readonly=0 67 68# 14336KB 69hint.map.3.at="flash/spi0" 70hint.map.3.start=0x001e0000 71hint.map.3.end=0x00fe0000 72hint.map.3.name="rootfs" 73hint.map.3.readonly=0 74 75# NVRAM 76hint.map.4.at="flash/spi0" 77hint.map.4.start=0x00fe0000 78hint.map.4.end=0x00ff0000 79hint.map.4.name="cfg" 80hint.map.4.readonly=0 81 82# This is radio calibration section. It is (or should be!) unique 83# for each board, to take into account thermal and electrical differences 84# as well as the regulatory compliance data. 85# 86hint.map.5.at="flash/spi0" 87hint.map.5.start=0x00ff0000 88hint.map.5.end=0x01000000 89hint.map.5.name="art" 90hint.map.5.readonly=1 91 92# GPIO specific configuration block 93 94# Don't flip on anything that isn't already enabled. 95# This includes leaving the SPI CS1/CS2 pins as GPIO pins as they're 96# not used here. 97hint.gpio.0.function_set=0x00000000 98hint.gpio.0.function_clear=0x00000000 99 100# These are the GPIO LEDs and buttons which can be software controlled. 101#hint.gpio.0.pinmask=0x001c02ae 102#hint.gpio.0.pinmask=0x00001803 103 104# XXX TODO: the button and LEDs! 105 106