1/***********************license start************************************ 2 * Copyright (c) 2005-2007 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 * 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 * 23 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 24 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS 25 * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH 26 * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY 27 * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT 28 * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES 29 * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR 30 * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET 31 * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT 32 * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 33 * 34 * 35 * For any questions regarding licensing please contact marketing@caviumnetworks.com 36 * 37 ***********************license end**************************************/ 38/* $FreeBSD$ */ 39 40#ifndef _CAVIUM_OCTOPCIREG_H_ 41#define _CAVIUM_OCTOPCIREG_H_ 42 43/** 44 * This is the bit decoding used for the Octeon PCI controller addresses for config space 45 */ 46typedef union 47{ 48 uint64_t u64; 49 uint64_t * u64_ptr; 50 uint32_t * u32_ptr; 51 uint16_t * u16_ptr; 52 uint8_t * u8_ptr; 53 struct 54 { 55 uint64_t upper : 2; 56 uint64_t reserved : 13; 57 uint64_t io : 1; 58 uint64_t did : 5; 59 uint64_t subdid : 3; 60 uint64_t reserved2 : 4; 61 uint64_t endian_swap : 2; 62 uint64_t reserved3 : 10; 63 uint64_t bus : 8; 64 uint64_t dev : 5; 65 uint64_t func : 3; 66 uint64_t reg : 8; 67 } s; 68} octeon_pci_config_space_address_t; 69 70typedef union 71{ 72 uint64_t u64; 73 uint32_t * u32_ptr; 74 uint16_t * u16_ptr; 75 uint8_t * u8_ptr; 76 struct 77 { 78 uint64_t upper : 2; 79 uint64_t reserved : 13; 80 uint64_t io : 1; 81 uint64_t did : 5; 82 uint64_t subdid : 3; 83 uint64_t reserved2 : 4; 84 uint64_t endian_swap : 2; 85 uint64_t res1 : 1; 86 uint64_t port : 1; 87 uint64_t addr : 32; 88 } s; 89} octeon_pci_io_space_address_t; 90 91 92#define CVMX_OCT_SUBDID_PCI_CFG 1 93#define CVMX_OCT_SUBDID_PCI_IO 2 94#define CVMX_OCT_SUBDID_PCI_MEM1 3 95#define CVMX_OCT_SUBDID_PCI_MEM2 4 96#define CVMX_OCT_SUBDID_PCI_MEM3 5 97#define CVMX_OCT_SUBDID_PCI_MEM4 6 98 99#define CVMX_OCT_PCI_IO_BASE 0x00004000 100#define CVMX_OCT_PCI_IO_SIZE 0x08000000 101 102#define CVMX_OCT_PCI_MEM1_BASE 0xf0000000 103#define CVMX_OCT_PCI_MEM1_SIZE 0x0f000000 104 105#endif /* !_CAVIUM_OCTOPCIREG_H_ */ 106