qca955xreg.h revision 280314
1/*- 2 * Copyright (c) 2013 Adrian Chadd <adrian@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/mips/atheros/qca955xreg.h 280314 2015-03-21 06:00:46Z adrian $ 27 */ 28#ifndef __QCA955XREG_H__ 29#define __QCA955XREG_H__ 30 31#define BIT(x) (1 << (x)) 32 33/* Revision ID information */ 34#define REV_ID_MAJOR_QCA9556 0x0130 35#define REV_ID_MAJOR_QCA9558 0x1130 36#define QCA955X_REV_ID_REVISION_MASK 0xf 37 38/* Big enough to cover APB and SPI, and most peripherals */ 39/* 40 * it needs to cover SPI because right now the if_ath_ahb 41 * code uses rman to map in the SPI address into memory 42 * to read data instead of us squirreling it away at early 43 * boot-time and using the firmware interface. 44 * 45 * if_ath_ahb.c should use the same firmware interface 46 * that if_ath_pci.c uses. 47 */ 48#define QCA955X_APB_BASE 0x18000000 49#define QCA955X_APB_SIZE 0x08000000 50 51#define QCA955X_PCI_MEM_BASE0 0x10000000 52#define QCA955X_PCI_MEM_BASE1 0x12000000 53#define QCA955X_PCI_MEM_SIZE 0x02000000 54#define QCA955X_PCI_CFG_BASE0 0x14000000 55#define QCA955X_PCI_CFG_BASE1 0x16000000 56#define QCA955X_PCI_CFG_SIZE 0x1000 57#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) 58#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) 59#define QCA955X_PCI_CRP_SIZE 0x1000 60#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) 61#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) 62#define QCA955X_PCI_CTRL_SIZE 0x100 63 64#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) 65#define QCA955X_WMAC_SIZE 0x20000 66#define QCA955X_EHCI0_BASE 0x1b000000 67#define QCA955X_EHCI1_BASE 0x1b400000 68#define QCA955X_EHCI_SIZE 0x1000 69 70/* PLL block */ 71 72#define QCA955X_PLL_CPU_CONFIG_REG (AR71XX_PLL_CPU_BASE + 0x00) 73#define QCA955X_PLL_DDR_CONFIG_REG (AR71XX_PLL_CPU_BASE + 0x04) 74#define QCA955X_PLL_CLK_CTRL_REG (AR71XX_PLL_CPU_BASE + 0x08) 75 76#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 77#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f 78#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 79#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f 80#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 81#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 82#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 83#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 84 85#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 86#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff 87#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 88#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f 89#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 90#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f 91#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 92#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 93 94#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) 95#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) 96#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) 97#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 98#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f 99#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 100#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f 101#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 102#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f 103#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) 104#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) 105#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) 106 107#define QCA955X_PLL_ETH_XMII_CONTROL_REG (AR71XX_PLL_CPU_BASE + 0x28) 108#define QCA955X_PLL_ETH_SGMII_CONTROL_REG (AR71XX_PLL_CPU_BASE + 0x48) 109 110/* Reset block */ 111#define QCA955X_RESET_REG_RESET_MODULE (AR71XX_RST_BLOCK_BASE + 0x1c) 112#define QCA955X_RESET_REG_BOOTSTRAP (AR71XX_RST_BLOCK_BASE + 0xb0) 113#define QCA955X_RESET_REG_EXT_INT_STATUS (AR71XX_RST_BLOCK_BASE + 0xac) 114 115#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) 116 117#define QCA955X_EXT_INT_WMAC_MISC BIT(0) 118#define QCA955X_EXT_INT_WMAC_TX BIT(1) 119#define QCA955X_EXT_INT_WMAC_RXLP BIT(2) 120#define QCA955X_EXT_INT_WMAC_RXHP BIT(3) 121#define QCA955X_EXT_INT_PCIE_RC1 BIT(4) 122#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) 123#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) 124#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) 125#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) 126#define QCA955X_EXT_INT_PCIE_RC2 BIT(12) 127#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) 128#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) 129#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) 130#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) 131#define QCA955X_EXT_INT_USB1 BIT(24) 132#define QCA955X_EXT_INT_USB2 BIT(28) 133 134#define QCA955X_EXT_INT_WMAC_ALL \ 135 (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ 136 QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP) 137 138#define QCA955X_EXT_INT_PCIE_RC1_ALL \ 139 (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \ 140 QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \ 141 QCA955X_EXT_INT_PCIE_RC1_INT3) 142 143#define QCA955X_EXT_INT_PCIE_RC2_ALL \ 144 (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \ 145 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ 146 QCA955X_EXT_INT_PCIE_RC2_INT3) 147 148#define QCA955X_RESET_HOST BIT(31) 149#define QCA955X_RESET_SLIC BIT(30) 150#define QCA955X_RESET_HDMA BIT(29) 151#define QCA955X_RESET_EXTERNAL BIT(28) 152#define QCA955X_RESET_RTC BIT(27) 153#define QCA955X_RESET_PCIE_EP_INT BIT(26) 154#define QCA955X_RESET_CHKSUM_ACC BIT(25) 155#define QCA955X_RESET_FULL_CHIP BIT(24) 156#define QCA955X_RESET_GE1_MDIO BIT(23) 157#define QCA955X_RESET_GE0_MDIO BIT(22) 158#define QCA955X_RESET_CPU_NMI BIT(21) 159#define QCA955X_RESET_CPU_COLD BIT(20) 160#define QCA955X_RESET_HOST_RESET_INT BIT(19) 161#define QCA955X_RESET_PCIE_EP BIT(18) 162#define QCA955X_RESET_UART1 BIT(17) 163#define QCA955X_RESET_DDR BIT(16) 164#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) 165#define QCA955X_RESET_NANDF BIT(14) 166#define QCA955X_RESET_GE1_MAC BIT(13) 167#define QCA955X_RESET_SGMII_ANALOG BIT(12) 168#define QCA955X_RESET_USB_PHY_ANALOG BIT(11) 169#define QCA955X_RESET_HOST_DMA_INT BIT(10) 170#define QCA955X_RESET_GE0_MAC BIT(9) 171#define QCA955X_RESET_SGMII BIT(8) 172#define QCA955X_RESET_PCIE_PHY BIT(7) 173#define QCA955X_RESET_PCIE BIT(6) 174#define QCA955X_RESET_USB_HOST BIT(5) 175#define QCA955X_RESET_USB_PHY BIT(4) 176#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3) 177#define QCA955X_RESET_LUT BIT(2) 178#define QCA955X_RESET_MBOX BIT(1) 179#define QCA955X_RESET_I2S BIT(0) 180 181/* GPIO block */ 182#define QCA955X_GPIO_COUNT 24 183 184#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) 185#define QCA955X_GMAC_SIZE 0x40 186#define QCA955X_NFC_BASE 0x1b800200 187#define QCA955X_NFC_SIZE 0xb8 188 189 190/* GMAC Interface */ 191#define QCA955X_GMAC_REG_ETH_CFG (QCA955X_GMAC_BASE + 0x00) 192 193#define QCA955X_ETH_CFG_RGMII_EN BIT(0) 194#define QCA955X_ETH_CFG_GE0_SGMII BIT(6) 195 196/* XXX Same as AR934x values */ 197#define QCA955X_PLL_VAL_1000 0x16000000 198#define QCA955X_PLL_VAL_100 0x00000101 199#define QCA955X_PLL_VAL_10 0x00001616 200 201/* DDR block */ 202#define QCA955X_DDR_REG_FLUSH_GE0 (AR71XX_APB_BASE + 0x9c) 203#define QCA955X_DDR_REG_FLUSH_GE1 (AR71XX_APB_BASE + 0xa0) 204#define QCA955X_DDR_REG_FLUSH_USB (AR71XX_APB_BASE + 0xa4) 205#define QCA955X_DDR_REG_FLUSH_PCIE (AR71XX_APB_BASE + 0xa8) 206#define QCA955X_DDR_REG_FLUSH_WMAC (AR71XX_APB_BASE + 0xac) 207 208/* PCIe control block - relative to PCI_CTRL_BASE0/PCI_CTRL_BASE1 */ 209 210#define QCA955X_PCI_APP 0x0 211#define QCA955X_PCI_APP_LTSSM_ENABLE (1 << 0) 212#define QCA955X_PCI_RESET 0x18 213#define QCA955X_PCI_RESET_LINK_UP (1 << 0) 214#define QCA955X_PCI_INTR_STATUS 0x4c 215#define QCA955X_PCI_INTR_MASK 0x50 216#define QCA955X_PCI_INTR_DEV0 (1 << 14) 217 218#endif /* __QCA955XREG_H__ */ 219