qca955xreg.h revision 276739
1152219Simp/*- 2152219Simp * Copyright (c) 2013 Adrian Chadd <adrian@FreeBSD.org> 3152219Simp * All rights reserved. 4152219Simp * 5152219Simp * Redistribution and use in source and binary forms, with or without 6152219Simp * modification, are permitted provided that the following conditions 7152219Simp * are met: 8152219Simp * 1. Redistributions of source code must retain the above copyright 9152219Simp * notice, this list of conditions and the following disclaimer. 10152219Simp * 2. Redistributions in binary form must reproduce the above copyright 11152219Simp * notice, this list of conditions and the following disclaimer in the 12152219Simp * documentation and/or other materials provided with the distribution. 13152219Simp * 14152219Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15152219Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16152219Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17152219Simp * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18152219Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19152219Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20152219Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21152219Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22152219Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23152219Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24152219Simp * SUCH DAMAGE. 25152219Simp * 26152219Simp * $FreeBSD: head/sys/mips/atheros/qca955xreg.h 276739 2015-01-06 07:37:33Z adrian $ 27152219Simp */ 28152219Simp#ifndef __QCA955XREG_H__ 29152219Simp#define __QCA955XREG_H__ 30152219Simp 31152219Simp#define BIT(x) (1 << (x)) 32152219Simp 33152219Simp/* Revision ID information */ 34152219Simp#define REV_ID_MAJOR_QCA9556 0x0130 35152219Simp#define REV_ID_MAJOR_QCA9558 0x1130 36152219Simp#define QCA955X_REV_ID_REVISION_MASK 0xf 37152219Simp 38152219Simp/* Big enough to cover APB and SPI, and most peripherals */ 39152219Simp/* 40152219Simp * it needs to cover SPI because right now the if_ath_ahb 41152219Simp * code uses rman to map in the SPI address into memory 42152219Simp * to read data instead of us squirreling it away at early 43152219Simp * boot-time and using the firmware interface. 44152219Simp * 45152219Simp * if_ath_ahb.c should use the same firmware interface 46152219Simp * that if_ath_pci.c uses. 47152219Simp */ 48152219Simp#define QCA955X_APB_BASE 0x18000000 49152219Simp#define QCA955X_APB_SIZE 0x08000000 50152219Simp 51152219Simp#define QCA955X_PCI_MEM_BASE0 0x10000000 52152219Simp#define QCA955X_PCI_MEM_BASE1 0x12000000 53152219Simp#define QCA955X_PCI_MEM_SIZE 0x02000000 54152219Simp#define QCA955X_PCI_CFG_BASE0 0x14000000 55152219Simp#define QCA955X_PCI_CFG_BASE1 0x16000000 56152219Simp#define QCA955X_PCI_CFG_SIZE 0x1000 57152219Simp#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) 58152219Simp#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) 59152219Simp#define QCA955X_PCI_CRP_SIZE 0x1000 60152219Simp#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) 61152219Simp#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) 62152219Simp#define QCA955X_PCI_CTRL_SIZE 0x100 63152219Simp 64152219Simp#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) 65152219Simp#define QCA955X_WMAC_SIZE 0x20000 66152219Simp#define QCA955X_EHCI0_BASE 0x1b000000 67152219Simp#define QCA955X_EHCI1_BASE 0x1b400000 68152219Simp#define QCA955X_EHCI_SIZE 0x1000 69152219Simp 70152219Simp/* PLL block */ 71152219Simp 72152219Simp#define QCA955X_PLL_CPU_CONFIG_REG (AR71XX_PLL_CPU_BASE + 0x00) 73152219Simp#define QCA955X_PLL_DDR_CONFIG_REG (AR71XX_PLL_CPU_BASE + 0x04) 74152219Simp#define QCA955X_PLL_CLK_CTRL_REG (AR71XX_PLL_CPU_BASE + 0x08) 75152219Simp 76152219Simp#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 77152219Simp#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f 78152219Simp#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 79152219Simp#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f 80152219Simp#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 81152219Simp#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f 82152219Simp#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 83152219Simp#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 84152219Simp 85152219Simp#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 86152219Simp#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff 87152219Simp#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 88152219Simp#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f 89152219Simp#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 90152219Simp#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f 91152219Simp#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 92152219Simp#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 93152219Simp 94152219Simp#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) 95152219Simp#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) 96152219Simp#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) 97152219Simp#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 98152219Simp#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f 99152219Simp#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 100152219Simp#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f 101152219Simp#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 102152219Simp#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f 103152219Simp#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) 104152219Simp#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) 105152219Simp#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) 106152219Simp 107152219Simp#define QCA955X_PLL_ETH_XMII_CONTROL_REG (AR71XX_PLL_CPU_BASE + 0x28) 108152219Simp#define QCA955X_PLL_ETH_SGMII_CONTROL_REG (AR71XX_PLL_CPU_BASE + 0x48) 109152219Simp 110152219Simp/* Reset block */ 111152219Simp#define QCA955X_RESET_REG_RESET_MODULE (AR71XX_RST_BLOCK_BASE + 0x1c) 112152219Simp#define QCA955X_RESET_REG_BOOTSTRAP (AR71XX_RST_BLOCK_BASE + 0xb0) 113152219Simp#define QCA955X_RESET_REG_EXT_INT_STATUS (AR71XX_RST_BLOCK_BASE + 0xac) 114152219Simp 115152219Simp#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) 116152219Simp 117152219Simp#define QCA955X_EXT_INT_WMAC_MISC BIT(0) 118152219Simp#define QCA955X_EXT_INT_WMAC_TX BIT(1) 119152219Simp#define QCA955X_EXT_INT_WMAC_RXLP BIT(2) 120152219Simp#define QCA955X_EXT_INT_WMAC_RXHP BIT(3) 121152219Simp#define QCA955X_EXT_INT_PCIE_RC1 BIT(4) 122152219Simp#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) 123152219Simp#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) 124152219Simp#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) 125152219Simp#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) 126152219Simp#define QCA955X_EXT_INT_PCIE_RC2 BIT(12) 127152219Simp#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) 128152219Simp#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) 129152219Simp#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) 130152219Simp#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) 131152219Simp#define QCA955X_EXT_INT_USB1 BIT(24) 132152219Simp#define QCA955X_EXT_INT_USB2 BIT(28) 133152219Simp 134152219Simp#define QCA955X_EXT_INT_WMAC_ALL \ 135152219Simp (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ 136152219Simp QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP) 137152219Simp 138152219Simp#define QCA955X_EXT_INT_PCIE_RC1_ALL \ 139152219Simp (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \ 140152219Simp QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \ 141152219Simp QCA955X_EXT_INT_PCIE_RC1_INT3) 142152219Simp 143152219Simp#define QCA955X_EXT_INT_PCIE_RC2_ALL \ 144152219Simp (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \ 145152219Simp QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ 146152219Simp QCA955X_EXT_INT_PCIE_RC2_INT3) 147152219Simp 148152219Simp#define QCA955X_RESET_HOST BIT(31) 149152219Simp#define QCA955X_RESET_SLIC BIT(30) 150152219Simp#define QCA955X_RESET_HDMA BIT(29) 151152219Simp#define QCA955X_RESET_EXTERNAL BIT(28) 152152219Simp#define QCA955X_RESET_RTC BIT(27) 153152219Simp#define QCA955X_RESET_PCIE_EP_INT BIT(26) 154152219Simp#define QCA955X_RESET_CHKSUM_ACC BIT(25) 155152219Simp#define QCA955X_RESET_FULL_CHIP BIT(24) 156152219Simp#define QCA955X_RESET_GE1_MDIO BIT(23) 157152219Simp#define QCA955X_RESET_GE0_MDIO BIT(22) 158152219Simp#define QCA955X_RESET_CPU_NMI BIT(21) 159152219Simp#define QCA955X_RESET_CPU_COLD BIT(20) 160152219Simp#define QCA955X_RESET_HOST_RESET_INT BIT(19) 161152219Simp#define QCA955X_RESET_PCIE_EP BIT(18) 162152219Simp#define QCA955X_RESET_UART1 BIT(17) 163152219Simp#define QCA955X_RESET_DDR BIT(16) 164152219Simp#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) 165152219Simp#define QCA955X_RESET_NANDF BIT(14) 166152219Simp#define QCA955X_RESET_GE1_MAC BIT(13) 167152219Simp#define QCA955X_RESET_SGMII_ANALOG BIT(12) 168152219Simp#define QCA955X_RESET_USB_PHY_ANALOG BIT(11) 169152219Simp#define QCA955X_RESET_HOST_DMA_INT BIT(10) 170152219Simp#define QCA955X_RESET_GE0_MAC BIT(9) 171152219Simp#define QCA955X_RESET_SGMII BIT(8) 172152219Simp#define QCA955X_RESET_PCIE_PHY BIT(7) 173152219Simp#define QCA955X_RESET_PCIE BIT(6) 174152219Simp#define QCA955X_RESET_USB_HOST BIT(5) 175152219Simp#define QCA955X_RESET_USB_PHY BIT(4) 176152219Simp#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3) 177152219Simp#define QCA955X_RESET_LUT BIT(2) 178152219Simp#define QCA955X_RESET_MBOX BIT(1) 179152219Simp#define QCA955X_RESET_I2S BIT(0) 180152219Simp 181152219Simp/* GPIO block */ 182152219Simp#define QCA955X_GPIO_COUNT 24 183152219Simp 184152219Simp#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) 185152219Simp#define QCA955X_GMAC_SIZE 0x40 186152219Simp#define QCA955X_NFC_BASE 0x1b800200 187152219Simp#define QCA955X_NFC_SIZE 0xb8 188152219Simp 189152219Simp 190152219Simp/* GMAC Interface */ 191152219Simp#define QCA955X_GMAC_REG_ETH_CFG 0x00 /* XXX register base? */ 192152219Simp 193152219Simp#define QCA955X_ETH_CFG_RGMII_EN BIT(0) 194152219Simp#define QCA955X_ETH_CFG_GE0_SGMII BIT(6) 195152219Simp 196152219Simp#endif /* __QCA955XREG_H__ */ 197152219Simp