pmc_mdep.h revision 145256
1/*- 2 * Copyright (c) 2003, Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/i386/include/pmc_mdep.h 145256 2005-04-19 04:01:25Z jkoshy $ 27 */ 28 29/* Machine dependent interfaces */ 30 31#ifndef _MACHINE_PMC_MDEP_H 32#define _MACHINE_PMC_MDEP_H 1 33 34#include <sys/pmc.h> 35 36/* AMD K7 PMCs */ 37 38#define K7_NPMCS 5 /* 1 TSC + 4 PMCs */ 39 40#define K7_PMC_COUNTERMASK 0xFF000000 41#define K7_PMC_TO_COUNTER(x) (((x) << 24) & K7_PMC_COUNTERMASK) 42#define K7_PMC_INVERT (1 << 23) 43#define K7_PMC_ENABLE (1 << 22) 44#define K7_PMC_INT (1 << 20) 45#define K7_PMC_PC (1 << 19) 46#define K7_PMC_EDGE (1 << 18) 47#define K7_PMC_OS (1 << 17) 48#define K7_PMC_USR (1 << 16) 49 50#define K7_PMC_UNITMASK_M 0x10 51#define K7_PMC_UNITMASK_O 0x08 52#define K7_PMC_UNITMASK_E 0x04 53#define K7_PMC_UNITMASK_S 0x02 54#define K7_PMC_UNITMASK_I 0x01 55#define K7_PMC_UNITMASK_MOESI 0x1F 56 57#define K7_PMC_UNITMASK 0xFF00 58#define K7_PMC_EVENTMASK 0x00FF 59#define K7_PMC_TO_UNITMASK(x) (((x) << 8) & K7_PMC_UNITMASK) 60#define K7_PMC_TO_EVENTMASK(x) ((x) & 0xFF) 61#define K7_VALID_BITS (K7_PMC_COUNTERMASK | K7_PMC_INVERT | \ 62 K7_PMC_ENABLE | K7_PMC_INT | K7_PMC_PC | K7_PMC_EDGE | K7_PMC_OS | \ 63 K7_PMC_USR | K7_PMC_UNITMASK | K7_PMC_EVENTMASK) 64 65/* Intel P4 PMCs */ 66 67#define P4_NPMCS 19 /* 1 TSC + 18 PMCS */ 68#define P4_NESCR 45 69#define P4_INVALID_PMC_INDEX -1 70#define P4_MAX_ESCR_PER_EVENT 2 71#define P4_MAX_PMC_PER_ESCR 3 72 73#define P4_CCCR_OVF (1 << 31) 74#define P4_CCCR_CASCADE (1 << 30) 75#define P4_CCCR_OVF_PMI_T1 (1 << 27) 76#define P4_CCCR_OVF_PMI_T0 (1 << 26) 77#define P4_CCCR_FORCE_OVF (1 << 25) 78#define P4_CCCR_EDGE (1 << 24) 79#define P4_CCCR_THRESHOLD_SHIFT 20 80#define P4_CCCR_THRESHOLD_MASK 0x00F00000 81#define P4_CCCR_TO_THRESHOLD(C) (((C) << P4_CCCR_THRESHOLD_SHIFT) & \ 82 P4_CCCR_THRESHOLD_MASK) 83#define P4_CCCR_COMPLEMENT (1 << 19) 84#define P4_CCCR_COMPARE (1 << 18) 85#define P4_CCCR_ACTIVE_THREAD_SHIFT 16 86#define P4_CCCR_ACTIVE_THREAD_MASK 0x00030000 87#define P4_CCCR_TO_ACTIVE_THREAD(T) (((T) << P4_CCCR_ACTIVE_THREAD_SHIFT) & \ 88 P4_CCCR_ACTIVE_THREAD_MASK) 89#define P4_CCCR_ESCR_SELECT_SHIFT 13 90#define P4_CCCR_ESCR_SELECT_MASK 0x0000E000 91#define P4_CCCR_TO_ESCR_SELECT(E) (((E) << P4_CCCR_ESCR_SELECT_SHIFT) & \ 92 P4_CCCR_ESCR_SELECT_MASK) 93#define P4_CCCR_ENABLE (1 << 12) 94#define P4_CCCR_VALID_BITS (P4_CCCR_OVF | P4_CCCR_CASCADE | \ 95 P4_CCCR_OVF_PMI_T1 | P4_CCCR_OVF_PMI_T0 | P4_CCCR_FORCE_OVF | \ 96 P4_CCCR_EDGE | P4_CCCR_THRESHOLD_MASK | P4_CCCR_COMPLEMENT | \ 97 P4_CCCR_COMPARE | P4_CCCR_ESCR_SELECT_MASK | P4_CCCR_ENABLE) 98 99#define P4_ESCR_EVENT_SELECT_SHIFT 25 100#define P4_ESCR_EVENT_SELECT_MASK 0x7E000000 101#define P4_ESCR_TO_EVENT_SELECT(E) (((E) << P4_ESCR_EVENT_SELECT_SHIFT) & \ 102 P4_ESCR_EVENT_SELECT_MASK) 103#define P4_ESCR_EVENT_MASK_SHIFT 9 104#define P4_ESCR_EVENT_MASK_MASK 0x01FFFE00 105#define P4_ESCR_TO_EVENT_MASK(M) (((M) << P4_ESCR_EVENT_MASK_SHIFT) & \ 106 P4_ESCR_EVENT_MASK_MASK) 107#define P4_ESCR_TAG_VALUE_SHIFT 5 108#define P4_ESCR_TAG_VALUE_MASK 0x000001E0 109#define P4_ESCR_TO_TAG_VALUE(T) (((T) << P4_ESCR_TAG_VALUE_SHIFT) & \ 110 P4_ESCR_TAG_VALUE_MASK) 111#define P4_ESCR_TAG_ENABLE 0x00000010 112#define P4_ESCR_T0_OS 0x00000008 113#define P4_ESCR_T0_USR 0x00000004 114#define P4_ESCR_T1_OS 0x00000002 115#define P4_ESCR_T1_USR 0x00000001 116#define P4_ESCR_OS P4_ESCR_T0_OS 117#define P4_ESCR_USR P4_ESCR_T0_USR 118#define P4_ESCR_VALID_BITS (P4_ESCR_EVENT_SELECT_MASK | \ 119 P4_ESCR_EVENT_MASK_MASK | P4_ESCR_TAG_VALUE_MASK | \ 120 P4_ESCR_TAG_ENABLE | P4_ESCR_T0_OS | P4_ESCR_T0_USR | P4_ESCR_T1_OS \ 121 P4_ESCR_T1_USR) 122 123#define P4_PERFCTR_MASK 0xFFFFFFFFFFLL /* 40 bits */ 124 125/* Intel PPro, Celeron, P-II, P-III, Pentium-M PMCS */ 126 127#define P6_NPMCS 3 /* 1 TSC + 2 PMCs */ 128 129#define P6_EVSEL_CMASK_MASK 0xFF000000 130#define P6_EVSEL_TO_CMASK(C) (((C) & 0xFF) << 24) 131#define P6_EVSEL_INV (1 << 23) 132#define P6_EVSEL_EN (1 << 22) 133#define P6_EVSEL_INT (1 << 20) 134#define P6_EVSEL_PC (1 << 19) 135#define P6_EVSEL_E (1 << 18) 136#define P6_EVSEL_OS (1 << 17) 137#define P6_EVSEL_USR (1 << 16) 138#define P6_EVSEL_UMASK_MASK 0x0000FF00 139#define P6_EVSEL_TO_UMASK(U) (((U) & 0xFF) << 8) 140#define P6_EVSEL_EVENT_SELECT(ES) ((ES) & 0xFF) 141#define P6_EVSEL_RESERVED (1 << 21) 142 143#define P6_MSR_EVSEL0 0x0186 144#define P6_MSR_EVSEL1 0x0187 145#define P6_MSR_PERFCTR0 0x00C1 146#define P6_MSR_PERFCTR1 0x00C2 147 148#define P6_PERFCTR_MASK 0xFFFFFFFFFFLL /* 40 bits */ 149 150/* Intel Pentium PMCs */ 151 152#define PENTIUM_NPMCS 3 /* 1 TSC + 2 PMCs */ 153#define PENTIUM_CESR_PC1 (1 << 25) 154#define PENTIUM_CESR_CC1_MASK 0x01C00000 155#define PENTIUM_CESR_TO_CC1(C) (((C) & 0x07) << 22) 156#define PENTIUM_CESR_ES1_MASK 0x003F0000 157#define PENTIUM_CESR_TO_ES1(E) (((E) & 0x3F) << 16) 158#define PENTIUM_CESR_PC0 (1 << 9) 159#define PENTIUM_CESR_CC0_MASK 0x000001C0 160#define PENTIUM_CESR_TO_CC0(C) (((C) & 0x07) << 6) 161#define PENTIUM_CESR_ES0_MASK 0x0000003F 162#define PENTIUM_CESR_TO_ES0(E) ((E) & 0x3F) 163#define PENTIUM_CESR_RESERVED 0xFC00FC00 164 165#define PENTIUM_MSR_CESR 0x11 166#define PENTIUM_MSR_CTR0 0x12 167#define PENTIUM_MSR_CTR1 0x13 168 169#ifdef _KERNEL 170 171/* 172 * Prototypes 173 */ 174 175#if defined(__i386__) 176struct pmc_mdep *pmc_amd_initialize(void); /* AMD K7/K8 PMCs */ 177struct pmc_mdep *pmc_intel_initialize(void); /* Intel PMCs */ 178int pmc_initialize_p4(struct pmc_mdep *); /* Pentium IV PMCs */ 179int pmc_initialize_p5(struct pmc_mdep *); /* Pentium PMCs */ 180int pmc_initialize_p6(struct pmc_mdep *); /* Pentium Pro PMCs */ 181#endif /* defined(__i386__) */ 182 183#endif /* _KERNEL */ 184#endif /* _MACHINE_PMC_MDEP_H */ 185