if_xlreg.h revision 38363
138363Swpaul/* 238363Swpaul * Copyright (c) 1997, 1998 338363Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 438363Swpaul * 538363Swpaul * Redistribution and use in source and binary forms, with or without 638363Swpaul * modification, are permitted provided that the following conditions 738363Swpaul * are met: 838363Swpaul * 1. Redistributions of source code must retain the above copyright 938363Swpaul * notice, this list of conditions and the following disclaimer. 1038363Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1138363Swpaul * notice, this list of conditions and the following disclaimer in the 1238363Swpaul * documentation and/or other materials provided with the distribution. 1338363Swpaul * 3. All advertising materials mentioning features or use of this software 1438363Swpaul * must display the following acknowledgement: 1538363Swpaul * This product includes software developed by Bill Paul. 1638363Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1738363Swpaul * may be used to endorse or promote products derived from this software 1838363Swpaul * without specific prior written permission. 1938363Swpaul * 2038363Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2138363Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2238363Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2338363Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2438363Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2538363Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2638363Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2738363Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2838363Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2938363Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3038363Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3138363Swpaul * 3238363Swpaul * $Id: if_xlreg.h,v 1.12 1998/08/13 21:29:06 wpaul Exp $ 3338363Swpaul */ 3438363Swpaul 3538363Swpaul#define XL_EE_READ 0x0080 /* read, 5 bit address */ 3638363Swpaul#define XL_EE_WRITE 0x0040 /* write, 5 bit address */ 3738363Swpaul#define XL_EE_ERASE 0x00c0 /* erase, 5 bit address */ 3838363Swpaul#define XL_EE_EWEN 0x0030 /* erase, no data needed */ 3938363Swpaul#define XL_EE_BUSY 0x8000 4038363Swpaul 4138363Swpaul#define XL_EE_EADDR0 0x00 /* station address, first word */ 4238363Swpaul#define XL_EE_EADDR1 0x01 /* station address, next word, */ 4338363Swpaul#define XL_EE_EADDR2 0x02 /* station address, last word */ 4438363Swpaul#define XL_EE_PRODID 0x03 /* product ID code */ 4538363Swpaul#define XL_EE_MDATA_DATE 0x04 /* manufacturing data, date */ 4638363Swpaul#define XL_EE_MDATA_DIV 0x05 /* manufacturing data, division */ 4738363Swpaul#define XL_EE_MDATA_PCODE 0x06 /* manufacturing data, product code */ 4838363Swpaul#define XL_EE_MFG_ID 0x07 4938363Swpaul#define XL_EE_PCI_PARM 0x08 5038363Swpaul#define XL_EE_ROM_ONFO 0x09 5138363Swpaul#define XL_EE_OEM_ADR0 0x0A 5238363Swpaul#define XL_EE_OEM_ADR1 0x0B 5338363Swpaul#define XL_EE_OEM_ADR2 0x0C 5438363Swpaul#define XL_EE_SOFTINFO1 0x0D 5538363Swpaul#define XL_EE_COMPAT 0x0E 5638363Swpaul#define XL_EE_SOFTINFO2 0x0F 5738363Swpaul#define XL_EE_CAPS 0x10 /* capabilities word */ 5838363Swpaul#define XL_EE_RSVD0 0x11 5938363Swpaul#define XL_EE_ICFG_0 0x12 6038363Swpaul#define XL_EE_ICFG_1 0x13 6138363Swpaul#define XL_EE_RSVD1 0x14 6238363Swpaul#define XL_EE_SOFTINFO3 0x15 6338363Swpaul#define XL_EE_RSVD_2 0x16 6438363Swpaul 6538363Swpaul/* 6638363Swpaul * Bits in the capabilities word 6738363Swpaul */ 6838363Swpaul#define XL_CAPS_PNP 0x0001 6938363Swpaul#define XL_CAPS_FULL_DUPLEX 0x0002 7038363Swpaul#define XL_CAPS_LARGE_PKTS 0x0004 7138363Swpaul#define XL_CAPS_SLAVE_DMA 0x0008 7238363Swpaul#define XL_CAPS_SECOND_DMA 0x0010 7338363Swpaul#define XL_CAPS_FULL_BM 0x0020 7438363Swpaul#define XL_CAPS_FRAG_BM 0x0040 7538363Swpaul#define XL_CAPS_CRC_PASSTHRU 0x0080 7638363Swpaul#define XL_CAPS_TXDONE 0x0100 7738363Swpaul#define XL_CAPS_NO_TXLENGTH 0x0200 7838363Swpaul#define XL_CAPS_RX_REPEAT 0x0400 7938363Swpaul#define XL_CAPS_SNOOPING 0x0800 8038363Swpaul#define XL_CAPS_100MBPS 0x1000 8138363Swpaul#define XL_CAPS_PWRMGMT 0x2000 8238363Swpaul 8338363Swpaul#define XL_PACKET_SIZE 1536 8438363Swpaul 8538363Swpaul/* 8638363Swpaul * Register layouts. 8738363Swpaul */ 8838363Swpaul#define XL_COMMAND 0x0E 8938363Swpaul#define XL_STATUS 0x0E 9038363Swpaul 9138363Swpaul#define XL_TX_STATUS 0x1B 9238363Swpaul#define XL_TX_FREE 0x1C 9338363Swpaul#define XL_DMACTL 0x20 9438363Swpaul#define XL_DOWNLIST_PTR 0x24 9538363Swpaul#define XL_TX_FREETHRESH 0x2F 9638363Swpaul#define XL_UPLIST_PTR 0x38 9738363Swpaul#define XL_UPLIST_STATUS 0x30 9838363Swpaul 9938363Swpaul#define XL_PKTSTAT_UP_STALLED 0x00002000 10038363Swpaul#define XL_PKTSTAT_UP_ERROR 0x00004000 10138363Swpaul#define XL_PKTSTAT_UP_CMPLT 0x00008000 10238363Swpaul 10338363Swpaul#define XL_DMACTL_DN_CMPLT_REQ 0x00000002 10438363Swpaul#define XL_DMACTL_DOWN_STALLED 0x00000004 10538363Swpaul#define XL_DMACTL_UP_CMPLT 0x00000008 10638363Swpaul#define XL_DMACTL_DOWN_CMPLT 0x00000010 10738363Swpaul#define XL_DMACTL_UP_RX_EARLY 0x00000020 10838363Swpaul#define XL_DMACTL_ARM_COUNTDOWN 0x00000040 10938363Swpaul#define XL_DMACTL_DOWN_INPROG 0x00000080 11038363Swpaul#define XL_DMACTL_COUNTER_SPEED 0x00000100 11138363Swpaul#define XL_DMACTL_DOWNDOWN_MODE 0x00000200 11238363Swpaul#define XL_DMACTL_TARGET_ABORT 0x40000000 11338363Swpaul#define XL_DMACTL_MASTER_ABORT 0x80000000 11438363Swpaul 11538363Swpaul/* 11638363Swpaul * Command codes. Some command codes require that we wait for 11738363Swpaul * the CMD_BUSY flag to clear. Those codes are marked as 'mustwait.' 11838363Swpaul */ 11938363Swpaul#define XL_CMD_RESET 0x0000 /* mustwait */ 12038363Swpaul#define XL_CMD_WINSEL 0x0800 12138363Swpaul#define XL_CMD_COAX_START 0x1000 12238363Swpaul#define XL_CMD_RX_DISABLE 0x1800 12338363Swpaul#define XL_CMD_RX_ENABLE 0x2000 12438363Swpaul#define XL_CMD_RX_RESET 0x2800 /* mustwait */ 12538363Swpaul#define XL_CMD_UP_STALL 0x3000 /* mustwait */ 12638363Swpaul#define XL_CMD_UP_UNSTALL 0x3001 12738363Swpaul#define XL_CMD_DOWN_STALL 0x3002 /* mustwait */ 12838363Swpaul#define XL_CMD_DOWN_UNSTALL 0x3003 12938363Swpaul#define XL_CMD_RX_DISCARD 0x4000 13038363Swpaul#define XL_CMD_TX_ENABLE 0x4800 13138363Swpaul#define XL_CMD_TX_DISABLE 0x5000 13238363Swpaul#define XL_CMD_TX_RESET 0x5800 /* mustwait */ 13338363Swpaul#define XL_CMD_INTR_FAKE 0x6000 13438363Swpaul#define XL_CMD_INTR_ACK 0x6800 13538363Swpaul#define XL_CMD_INTR_ENB 0x7000 13638363Swpaul#define XL_CMD_STAT_ENB 0x7800 13738363Swpaul#define XL_CMD_RX_SET_FILT 0x8000 13838363Swpaul#define XL_CMD_RX_SET_THRESH 0x8800 13938363Swpaul#define XL_CMD_TX_SET_THRESH 0x9000 14038363Swpaul#define XL_CMD_TX_SET_START 0x9800 14138363Swpaul#define XL_CMD_DMA_UP 0xA000 14238363Swpaul#define XL_CMD_DMA_STOP 0xA001 14338363Swpaul#define XL_CMD_STATS_ENABLE 0xA800 14438363Swpaul#define XL_CMD_STATS_DISABLE 0xB000 14538363Swpaul#define XL_CMD_COAX_STOP 0xB800 14638363Swpaul 14738363Swpaul#define XL_CMD_SET_TX_RECLAIM 0xC000 /* 3c905B only */ 14838363Swpaul#define XL_CMD_RX_SET_HASH 0xC800 /* 3c905B only */ 14938363Swpaul 15038363Swpaul#define XL_HASH_SET 0x0400 15138363Swpaul#define XL_HASHFILT_SIZE 256 15238363Swpaul 15338363Swpaul/* 15438363Swpaul * status codes 15538363Swpaul * Note that bits 15 to 13 indicate the currently visible register window 15638363Swpaul * which may be anything from 0 to 7. 15738363Swpaul */ 15838363Swpaul#define XL_STAT_INTLATCH 0x0001 /* 0 */ 15938363Swpaul#define XL_STAT_ADFAIL 0x0002 /* 1 */ 16038363Swpaul#define XL_STAT_TX_COMPLETE 0x0004 /* 2 */ 16138363Swpaul#define XL_STAT_TX_AVAIL 0x0008 /* 3 first generation */ 16238363Swpaul#define XL_STAT_RX_COMPLETE 0x0010 /* 4 */ 16338363Swpaul#define XL_STAT_RX_EARLY 0x0020 /* 5 */ 16438363Swpaul#define XL_STAT_INTREQ 0x0040 /* 6 */ 16538363Swpaul#define XL_STAT_STATSOFLOW 0x0080 /* 7 */ 16638363Swpaul#define XL_STAT_DMADONE 0x0100 /* 8 first generation */ 16738363Swpaul#define XL_STAT_LINKSTAT 0x0100 /* 8 3c509B */ 16838363Swpaul#define XL_STAT_DOWN_COMPLETE 0x0200 /* 9 */ 16938363Swpaul#define XL_STAT_UP_COMPLETE 0x0400 /* 10 */ 17038363Swpaul#define XL_STAT_DMABUSY 0x0800 /* 11 first generation */ 17138363Swpaul#define XL_STAT_CMDBUSY 0x1000 /* 12 */ 17238363Swpaul 17338363Swpaul/* 17438363Swpaul * Window 0 registers 17538363Swpaul */ 17638363Swpaul#define XL_W0_EE_DATA 0x0C 17738363Swpaul#define XL_W0_EE_CMD 0x0A 17838363Swpaul#define XL_W0_RSRC_CFG 0x08 17938363Swpaul#define XL_W0_ADDR_CFG 0x06 18038363Swpaul#define XL_W0_CFG_CTRL 0x04 18138363Swpaul 18238363Swpaul#define XL_W0_PROD_ID 0x02 18338363Swpaul#define XL_W0_MFG_ID 0x00 18438363Swpaul 18538363Swpaul/* 18638363Swpaul * Window 1 18738363Swpaul */ 18838363Swpaul 18938363Swpaul#define XL_W1_TX_FIFO 0x10 19038363Swpaul 19138363Swpaul#define XL_W1_FREE_TX 0x0C 19238363Swpaul#define XL_W1_TX_STATUS 0x0B 19338363Swpaul#define XL_W1_TX_TIMER 0x0A 19438363Swpaul#define XL_W1_RX_STATUS 0x08 19538363Swpaul#define XL_W1_RX_FIFO 0x00 19638363Swpaul 19738363Swpaul/* 19838363Swpaul * RX status codes 19938363Swpaul */ 20038363Swpaul#define XL_RXSTATUS_OVERRUN 0x01 20138363Swpaul#define XL_RXSTATUS_RUNT 0x02 20238363Swpaul#define XL_RXSTATUS_ALIGN 0x04 20338363Swpaul#define XL_RXSTATUS_CRC 0x08 20438363Swpaul#define XL_RXSTATUS_OVERSIZE 0x10 20538363Swpaul#define XL_RXSTATUS_DRIBBLE 0x20 20638363Swpaul 20738363Swpaul/* 20838363Swpaul * TX status codes 20938363Swpaul */ 21038363Swpaul#define XL_TXSTATUS_RECLAIM 0x02 /* 3c905B only */ 21138363Swpaul#define XL_TXSTATUS_OVERFLOW 0x04 21238363Swpaul#define XL_TXSTATUS_MAXCOLS 0x08 21338363Swpaul#define XL_TXSTATUS_UNDERRUN 0x10 21438363Swpaul#define XL_TXSTATUS_JABBER 0x20 21538363Swpaul#define XL_TXSTATUS_INTREQ 0x40 21638363Swpaul#define XL_TXSTATUS_COMPLETE 0x80 21738363Swpaul 21838363Swpaul/* 21938363Swpaul * Window 2 22038363Swpaul */ 22138363Swpaul#define XL_W2_RESET_OPTIONS 0x0C /* 3c905B only */ 22238363Swpaul#define XL_W2_STATION_MASK_HI 0x0A 22338363Swpaul#define XL_W2_STATION_MASK_MID 0x08 22438363Swpaul#define XL_W2_STATION_MASK_LO 0x06 22538363Swpaul#define XL_W2_STATION_ADDR_HI 0x04 22638363Swpaul#define XL_W2_STATION_ADDR_MID 0x02 22738363Swpaul#define XL_W2_STATION_ADDR_LO 0x00 22838363Swpaul 22938363Swpaul#define XL_RESETOPT_FEATUREMASK 0x0001|0x0002|0x004 23038363Swpaul#define XL_RESETOPT_D3RESETDIS 0x0008 23138363Swpaul#define XL_RESETOPT_DISADVFD 0x0010 23238363Swpaul#define XL_RESETOPT_DISADV100 0x0020 23338363Swpaul#define XL_RESETOPT_DISAUTONEG 0x0040 23438363Swpaul#define XL_RESETOPT_DEBUGMODE 0x0080 23538363Swpaul#define XL_RESETOPT_FASTAUTO 0x0100 23638363Swpaul#define XL_RESETOPT_FASTEE 0x0200 23738363Swpaul#define XL_RESETOPT_FORCEDCONF 0x0400 23838363Swpaul#define XL_RESETOPT_TESTPDTPDR 0x0800 23938363Swpaul#define XL_RESETOPT_TEST100TX 0x1000 24038363Swpaul#define XL_RESETOPT_TEST100RX 0x2000 24138363Swpaul 24238363Swpaul/* 24338363Swpaul * Window 3 (fifo management) 24438363Swpaul */ 24538363Swpaul#define XL_W3_INTERNAL_CFG 0x00 24638363Swpaul#define XL_W3_RESET_OPT 0x08 24738363Swpaul#define XL_W3_FREE_TX 0x0C 24838363Swpaul#define XL_W3_FREE_RX 0x0A 24938363Swpaul#define XL_W3_MAC_CTRL 0x06 25038363Swpaul 25138363Swpaul#define XL_ICFG_CONNECTOR_MASK 0x00F00000 25238363Swpaul#define XL_ICFG_CONNECTOR_BITS 20 25338363Swpaul 25438363Swpaul#define XL_ICFG_RAMSIZE_MASK 0x00000007 25538363Swpaul#define XL_ICFG_RAMWIDTH 0x00000008 25638363Swpaul#define XL_ICFG_ROMSIZE_MASK (0x00000040|0x00000080) 25738363Swpaul#define XL_ICFG_DISABLE_BASSD 0x00000100 25838363Swpaul#define XL_ICFG_RAMLOC 0x00000200 25938363Swpaul#define XL_ICFG_RAMPART (0x00010000|0x00020000) 26038363Swpaul#define XL_ICFG_XCVRSEL (0x00100000|0x00200000|0x00400000) 26138363Swpaul#define XL_ICFG_AUTOSEL 0x01000000 26238363Swpaul 26338363Swpaul#define XL_XCVR_10BT 0x00 26438363Swpaul#define XL_XCVR_AUI 0x01 26538363Swpaul#define XL_XCVR_RSVD_0 0x02 26638363Swpaul#define XL_XCVR_COAX 0x03 26738363Swpaul#define XL_XCVR_100BTX 0x04 26838363Swpaul#define XL_XCVR_100BFX 0x05 26938363Swpaul#define XL_XCVR_MII 0x06 27038363Swpaul#define XL_XCVR_RSVD_1 0x07 27138363Swpaul#define XL_XCVR_AUTO 0x08 /* 3c905B only */ 27238363Swpaul 27338363Swpaul#define XL_MACCTRL_DEFER_EXT_END 0x0001 27438363Swpaul#define XL_MACCTRL_DEFER_0 0x0002 27538363Swpaul#define XL_MACCTRL_DEFER_1 0x0004 27638363Swpaul#define XL_MACCTRL_DEFER_2 0x0008 27738363Swpaul#define XL_MACCTRL_DEFER_3 0x0010 27838363Swpaul#define XL_MACCTRL_DUPLEX 0x0020 27938363Swpaul#define XL_MACCTRL_ALLOW_LARGE_PACK 0x0040 28038363Swpaul#define XL_MACCTRL_EXTEND_AFTER_COL 0x0080 (3c905B only) 28138363Swpaul#define XL_MACCTRL_FLOW_CONTROL_ENB 0x0100 (3c905B only) 28238363Swpaul#define XL_MACCTRL_VLT_END 0x0200 (3c905B only) 28338363Swpaul 28438363Swpaul/* 28538363Swpaul * The 'reset options' register contains power-on reset values 28638363Swpaul * loaded from the EEPROM. This includes the supported media 28738363Swpaul * types on the card. It is also known as the media options register. 28838363Swpaul */ 28938363Swpaul#define XL_W3_MEDIA_OPT 0x08 29038363Swpaul 29138363Swpaul#define XL_MEDIAOPT_BT4 0x0001 /* MII */ 29238363Swpaul#define XL_MEDIAOPT_BTX 0x0002 /* on-chip */ 29338363Swpaul#define XL_MEDIAOPT_BFX 0x0004 /* on-chip */ 29438363Swpaul#define XL_MEDIAOPT_BT 0x0008 /* on-chip */ 29538363Swpaul#define XL_MEDIAOPT_BNC 0x0010 /* on-chip */ 29638363Swpaul#define XL_MEDIAOPT_AUI 0x0020 /* on-chip */ 29738363Swpaul#define XL_MEDIAOPT_MII 0x0040 /* MII */ 29838363Swpaul#define XL_MEDIAOPT_VCO 0x0100 /* 1st gen chip only */ 29938363Swpaul 30038363Swpaul#define XL_MEDIAOPT_10FL 0x0100 /* 3x905B only, on-chip */ 30138363Swpaul#define XL_MEDIAOPT_MASK 0x01FF 30238363Swpaul 30338363Swpaul/* 30438363Swpaul * Window 4 (diagnostics) 30538363Swpaul */ 30638363Swpaul#define XL_W4_UPPERBYTESOK 0x0D 30738363Swpaul#define XL_W4_BADSSD 0x0C 30838363Swpaul#define XL_W4_MEDIA_STATUS 0x0A 30938363Swpaul#define XL_W4_PHY_MGMT 0x08 31038363Swpaul#define XL_W4_NET_DIAG 0x06 31138363Swpaul#define XL_W4_FIFO_DIAG 0x04 31238363Swpaul#define XL_W4_VCO_DIAG 0x02 31338363Swpaul 31438363Swpaul#define XL_W4_CTRLR_STAT 0x08 31538363Swpaul#define XL_W4_TX_DIAG 0x00 31638363Swpaul 31738363Swpaul#define XL_MII_CLK 0x01 31838363Swpaul#define XL_MII_DATA 0x02 31938363Swpaul#define XL_MII_DIR 0x04 32038363Swpaul 32138363Swpaul#define XL_MEDIA_SQE 0x0008 32238363Swpaul#define XL_MEDIA_10TP 0x00C0 32338363Swpaul#define XL_MEDIA_LNK 0x0080 32438363Swpaul#define XL_MEDIA_LNKBEAT 0x0800 32538363Swpaul 32638363Swpaul#define XL_MEDIASTAT_CRCSTRIP 0x0004 32738363Swpaul#define XL_MEDIASTAT_SQEENB 0x0008 32838363Swpaul#define XL_MEDIASTAT_COLDET 0x0010 32938363Swpaul#define XL_MEDIASTAT_CARRIER 0x0020 33038363Swpaul#define XL_MEDIASTAT_JABGUARD 0x0040 33138363Swpaul#define XL_MEDIASTAT_LINKBEAT 0x0080 33238363Swpaul#define XL_MEDIASTAT_JABDETECT 0x0200 33338363Swpaul#define XL_MEDIASTAT_POLREVERS 0x0400 33438363Swpaul#define XL_MEDIASTAT_LINKDETECT 0x0800 33538363Swpaul#define XL_MEDIASTAT_TXINPROG 0x1000 33638363Swpaul#define XL_MEDIASTAT_DCENB 0x4000 33738363Swpaul#define XL_MEDIASTAT_AUIDIS 0x8000 33838363Swpaul 33938363Swpaul#define XL_NETDIAG_TEST_LOWVOLT 0x0001 34038363Swpaul#define XL_NETDIAG_ASIC_REVMASK (0x0002|0x0004|0x0008|0x0010|0x0020) 34138363Swpaul#define XL_NETDIAG_UPPER_BYTES_ENABLE 0x0040 34238363Swpaul#define XL_NETDIAG_STATS_ENABLED 0x0080 34338363Swpaul#define XL_NETDIAG_TX_FATALERR 0x0100 34438363Swpaul#define XL_NETDIAG_TRANSMITTING 0x0200 34538363Swpaul#define XL_NETDIAG_RX_ENABLED 0x0400 34638363Swpaul#define XL_NETDIAG_TX_ENABLED 0x0800 34738363Swpaul#define XL_NETDIAG_FIFO_LOOPBACK 0x1000 34838363Swpaul#define XL_NETDIAG_MAC_LOOPBACK 0x2000 34938363Swpaul#define XL_NETDIAG_ENDEC_LOOPBACK 0x4000 35038363Swpaul#define XL_NETDIAG_EXTERNAL_LOOP 0x8000 35138363Swpaul 35238363Swpaul/* 35338363Swpaul * Window 5 35438363Swpaul */ 35538363Swpaul#define XL_W5_STAT_ENB 0x0C 35638363Swpaul#define XL_W5_INTR_ENB 0x0A 35738363Swpaul#define XL_W5_RX_FILTER 0x08 35838363Swpaul#define XL_W5_RX_EARLYTHRESH 0x06 35938363Swpaul#define XL_W5_TX_AVAILTHRESH 0x02 36038363Swpaul#define XL_W5_TX_STARTTHRESH 0x00 36138363Swpaul 36238363Swpaul/* 36338363Swpaul * RX filter bits 36438363Swpaul */ 36538363Swpaul#define XL_RXFILTER_INDIVIDUAL 0x01 36638363Swpaul#define XL_RXFILTER_ALLMULTI 0x02 36738363Swpaul#define XL_RXFILTER_BROADCAST 0x04 36838363Swpaul#define XL_RXFILTER_ALLFRAMES 0x08 36938363Swpaul#define XL_RXFILTER_MULTIHASH 0x10 /* 3c905B only */ 37038363Swpaul 37138363Swpaul/* 37238363Swpaul * Window 6 (stats) 37338363Swpaul */ 37438363Swpaul#define XL_W6_TX_BYTES_OK 0x0C 37538363Swpaul#define XL_W6_RX_BYTES_OK 0x0A 37638363Swpaul#define XL_W6_UPPER_FRAMES_OK 0x09 37738363Swpaul#define XL_W6_DEFERRED 0x08 37838363Swpaul#define XL_W6_RX_OK 0x07 37938363Swpaul#define XL_W6_TX_OK 0x06 38038363Swpaul#define XL_W6_RX_OVERRUN 0x05 38138363Swpaul#define XL_W6_COL_LATE 0x04 38238363Swpaul#define XL_W6_COL_SINGLE 0x03 38338363Swpaul#define XL_W6_COL_MULTIPLE 0x02 38438363Swpaul#define XL_W6_SQE_ERRORS 0x01 38538363Swpaul#define XL_W6_CARRIER_LOST 0x00 38638363Swpaul 38738363Swpaul/* 38838363Swpaul * Window 7 (bus master control) 38938363Swpaul */ 39038363Swpaul#define XL_W7_BM_ADDR 0x00 39138363Swpaul#define XL_W7_BM_LEN 0x06 39238363Swpaul#define XL_W7_BM_STATUS 0x0B 39338363Swpaul#define XL_W7_BM_TIMEr 0x0A 39438363Swpaul 39538363Swpaul/* 39638363Swpaul * bus master control registers 39738363Swpaul */ 39838363Swpaul#define XL_BM_PKTSTAT 0x20 39938363Swpaul#define XL_BM_DOWNLISTPTR 0x24 40038363Swpaul#define XL_BM_FRAGADDR 0x28 40138363Swpaul#define XL_BM_FRAGLEN 0x2C 40238363Swpaul#define XL_BM_TXFREETHRESH 0x2F 40338363Swpaul#define XL_BM_UPPKTSTAT 0x30 40438363Swpaul#define XL_BM_UPLISTPTR 0x38 40538363Swpaul 40638363Swpaul#define XL_LAST_FRAG 0x80000000 40738363Swpaul 40838363Swpaul/* 40938363Swpaul * Boomerang/Cyclone TX/RX list structure. 41038363Swpaul * For the TX lists, bits 0 to 12 of the status word indicate 41138363Swpaul * length. 41238363Swpaul * This looks suspiciously like the ThunderLAN, doesn't it. 41338363Swpaul */ 41438363Swpaulstruct xl_frag { 41538363Swpaul u_int32_t xl_addr; /* 63 addr/len pairs */ 41638363Swpaul u_int32_t xl_len; 41738363Swpaul}; 41838363Swpaul 41938363Swpaulstruct xl_list { 42038363Swpaul u_int32_t xl_next; /* final entry has 0 nextptr */ 42138363Swpaul u_int32_t xl_status; 42238363Swpaul struct xl_frag xl_frag[63]; 42338363Swpaul}; 42438363Swpaul 42538363Swpaulstruct xl_list_onefrag { 42638363Swpaul u_int32_t xl_next; /* final entry has 0 nextptr */ 42738363Swpaul u_int32_t xl_status; 42838363Swpaul struct xl_frag xl_frag; 42938363Swpaul}; 43038363Swpaul 43138363Swpaul#define XL_MAXFRAGS 63 43238363Swpaul#define XL_RX_LIST_CNT 4 43338363Swpaul#define XL_TX_LIST_CNT 10 43438363Swpaul#define XL_MIN_FRAMELEN 60 43538363Swpaul 43638363Swpaulstruct xl_list_data { 43738363Swpaul struct xl_list_onefrag xl_rx_list[XL_RX_LIST_CNT]; 43838363Swpaul struct xl_list xl_tx_list[XL_TX_LIST_CNT]; 43938363Swpaul unsigned char xl_pad[XL_MIN_FRAMELEN]; 44038363Swpaul}; 44138363Swpaul 44238363Swpaulstruct xl_chain { 44338363Swpaul struct xl_list *xl_ptr; 44438363Swpaul struct mbuf *xl_mbuf; 44538363Swpaul struct xl_chain *xl_next; 44638363Swpaul}; 44738363Swpaul 44838363Swpaulstruct xl_chain_onefrag { 44938363Swpaul struct xl_list_onefrag *xl_ptr; 45038363Swpaul struct mbuf *xl_mbuf; 45138363Swpaul struct xl_chain_onefrag *xl_next; 45238363Swpaul}; 45338363Swpaul 45438363Swpaulstruct xl_chain_data { 45538363Swpaul struct xl_chain_onefrag xl_rx_chain[XL_RX_LIST_CNT]; 45638363Swpaul struct xl_chain xl_tx_chain[XL_TX_LIST_CNT]; 45738363Swpaul 45838363Swpaul struct xl_chain_onefrag *xl_rx_head; 45938363Swpaul 46038363Swpaul struct xl_chain *xl_tx_head; 46138363Swpaul struct xl_chain *xl_tx_tail; 46238363Swpaul struct xl_chain *xl_tx_free; 46338363Swpaul}; 46438363Swpaul 46538363Swpaul#define XL_RXSTAT_LENMASK 0x00001FFF 46638363Swpaul#define XL_RXSTAT_UP_ERROR 0x00004000 46738363Swpaul#define XL_RXSTAT_UP_CMPLT 0x00008000 46838363Swpaul#define XL_RXSTAT_UP_OVERRUN 0x00010000 46938363Swpaul#define XL_RXSTAT_RUNT 0x00020000 47038363Swpaul#define XL_RXSTAT_ALIGN 0x00040000 47138363Swpaul#define XL_RXSTAT_CRC 0x00080000 47238363Swpaul#define XL_RXSTAT_OVERSIZE 0x00100000 47338363Swpaul#define XL_RXSTAT_DRIBBLE 0x00800000 47438363Swpaul#define XL_RXSTAT_UP_OFLOW 0x01000000 47538363Swpaul#define XL_RXSTAT_IPCKERR 0x02000000 /* 3c905B only */ 47638363Swpaul#define XL_RXSTAT_TCPCKERR 0x04000000 /* 3c905B only */ 47738363Swpaul#define XL_RXSTAT_UDPCKERR 0x08000000 /* 3c905B only */ 47838363Swpaul#define XL_RXSTAT_BUFEN 0x10000000 /* 3c905B only */ 47938363Swpaul#define XL_RXSTAT_IPCKOK 0x20000000 /* 3c905B only */ 48038363Swpaul#define XL_RXSTAT_TCPCOK 0x40000000 /* 3c905B only */ 48138363Swpaul#define XL_RXSTAT_UDPCKOK 0x80000000 /* 3c905B only */ 48238363Swpaul 48338363Swpaul#define XL_TXSTAT_LENMASK 0x00001FFF 48438363Swpaul#define XL_TXSTAT_CRCDIS 0x00002000 48538363Swpaul#define XL_TXSTAT_TX_INTR 0x00008000 48638363Swpaul#define XL_TXSTAT_DL_COMPLETE 0x00010000 48738363Swpaul#define XL_TXSTAT_IPCKSUM 0x02000000 /* 3c905B only */ 48838363Swpaul#define XL_TXSTAT_TCPCKSUM 0x04000000 /* 3c905B only */ 48938363Swpaul#define XL_TXSTAT_UDPCKSUM 0x08000000 /* 3c905B only */ 49038363Swpaul#define XL_TXSTAT_DL_INTR 0x80000000 49138363Swpaul 49238363Swpaul#define XL_CAPABILITY_BM 0x20 49338363Swpaul 49438363Swpaul 49538363Swpaulstruct xl_type { 49638363Swpaul u_int16_t xl_vid; 49738363Swpaul u_int16_t xl_did; 49838363Swpaul char *xl_name; 49938363Swpaul}; 50038363Swpaul 50138363Swpaulstruct xl_mii_frame { 50238363Swpaul u_int8_t mii_stdelim; 50338363Swpaul u_int8_t mii_opcode; 50438363Swpaul u_int8_t mii_phyaddr; 50538363Swpaul u_int8_t mii_regaddr; 50638363Swpaul u_int8_t mii_turnaround; 50738363Swpaul u_int16_t mii_data; 50838363Swpaul}; 50938363Swpaul 51038363Swpaul/* 51138363Swpaul * MII constants 51238363Swpaul */ 51338363Swpaul#define XL_MII_STARTDELIM 0x01 51438363Swpaul#define XL_MII_READOP 0x02 51538363Swpaul#define XL_MII_WRITEOP 0x01 51638363Swpaul#define XL_MII_TURNAROUND 0x02 51738363Swpaul 51838363Swpaul/* 51938363Swpaul * The 3C905B adapters implement a few features that we want to 52038363Swpaul * take advantage of, namely the multicast hash filter. With older 52138363Swpaul * chips, you only have the option of turning on reception of all 52238363Swpaul * multicast frames, which is kind of lame. 52338363Swpaul */ 52438363Swpaul#define XL_TYPE_905B 1 52538363Swpaul#define XL_TYPE_90X 2 52638363Swpaul 52738363Swpaul#define XL_FLAG_FORCEDELAY 1 52838363Swpaul#define XL_FLAG_SCHEDDELAY 2 52938363Swpaul#define XL_FLAG_DELAYTIMEO 3 53038363Swpaul 53138363Swpaulstruct xl_softc { 53238363Swpaul struct arpcom arpcom; /* interface info */ 53338363Swpaul struct ifmedia ifmedia; /* media info */ 53438363Swpaul u_int32_t iobase; /* pointer to PIO space */ 53538363Swpaul#ifndef XL_USEIOSPACE 53638363Swpaul volatile caddr_t csr; /* pointer to register map */ 53738363Swpaul#endif 53838363Swpaul struct xl_type *xl_info; /* 3Com adapter info */ 53938363Swpaul struct xl_type *xl_pinfo; /* phy info */ 54038363Swpaul u_int8_t xl_unit; /* interface number */ 54138363Swpaul u_int8_t xl_type; 54238363Swpaul u_int8_t xl_phy_addr; /* PHY address */ 54338363Swpaul u_int32_t xl_xcvr; 54438363Swpaul u_int16_t xl_media; 54538363Swpaul u_int16_t xl_caps; 54638363Swpaul u_int8_t xl_tx_pend; /* TX pending */ 54738363Swpaul u_int8_t xl_want_auto; 54838363Swpaul u_int8_t xl_autoneg; 54938363Swpaul u_int8_t xl_stats_no_timeout; 55038363Swpaul caddr_t xl_ldata_ptr; 55138363Swpaul struct xl_list_data *xl_ldata; 55238363Swpaul struct xl_chain_data xl_cdata; 55338363Swpaul struct callout_handle xl_stat_ch; 55438363Swpaul}; 55538363Swpaul 55638363Swpaul#define xl_rx_goodframes(x) \ 55738363Swpaul ((x.xl_upper_frames_ok & 0x03) << 8) | x.xl_rx_frames_ok 55838363Swpaul 55938363Swpaul#define xl_tx_goodframes(x) \ 56038363Swpaul ((x.xl_upper_frames_ok & 0x30) << 4) | x.xl_tx_frames_ok 56138363Swpaul 56238363Swpaulstruct xl_stats { 56338363Swpaul u_int8_t xl_carrier_lost; 56438363Swpaul u_int8_t xl_sqe_errs; 56538363Swpaul u_int8_t xl_tx_multi_collision; 56638363Swpaul u_int8_t xl_tx_single_collision; 56738363Swpaul u_int8_t xl_tx_late_collision; 56838363Swpaul u_int8_t xl_rx_overrun; 56938363Swpaul u_int8_t xl_tx_frames_ok; 57038363Swpaul u_int8_t xl_rx_frames_ok; 57138363Swpaul u_int8_t xl_tx_deferred; 57238363Swpaul u_int8_t xl_upper_frames_ok; 57338363Swpaul u_int16_t xl_rx_bytes_ok; 57438363Swpaul u_int16_t xl_tx_bytes_ok; 57538363Swpaul u_int16_t status; 57638363Swpaul}; 57738363Swpaul 57838363Swpaul/* 57938363Swpaul * register space access macros 58038363Swpaul */ 58138363Swpaul#ifdef XL_USEIOSPACE 58238363Swpaul#define CSR_WRITE_4(sc, reg, val) \ 58338363Swpaul outl(sc->iobase + (u_int32_t)(reg), val) 58438363Swpaul#define CSR_WRITE_2(sc, reg, val) \ 58538363Swpaul outw(sc->iobase + (u_int32_t)(reg), val) 58638363Swpaul#define CSR_WRITE_1(sc, reg, val) \ 58738363Swpaul outb(sc->iobase + (u_int32_t)(reg), val) 58838363Swpaul 58938363Swpaul#define CSR_READ_4(sc, reg) \ 59038363Swpaul inl(sc->iobase + (u_int32_t)(reg)) 59138363Swpaul#define CSR_READ_2(sc, reg) \ 59238363Swpaul inw(sc->iobase + (u_int32_t)(reg)) 59338363Swpaul#define CSR_READ_1(sc, reg) \ 59438363Swpaul inb(sc->iobase + (u_int32_t)(reg)) 59538363Swpaul#else 59638363Swpaul#define CSR_WRITE_4(sc, reg, val) \ 59738363Swpaul ((*(u_int32_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int32_t)(val)) 59838363Swpaul#define CSR_WRITE_2(sc, reg, val) \ 59938363Swpaul ((*(u_int16_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int16_t)(val)) 60038363Swpaul#define CSR_WRITE_1(sc, reg, val) \ 60138363Swpaul ((*(u_int8_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int8_t)(val)) 60238363Swpaul 60338363Swpaul#define CSR_READ_4(sc, reg) \ 60438363Swpaul (*(u_int32_t *)((sc)->csr + (u_int32_t)(reg))) 60538363Swpaul#define CSR_READ_2(sc, reg) \ 60638363Swpaul (*(u_int16_t *)((sc)->csr + (u_int32_t)(reg))) 60738363Swpaul#define CSR_READ_1(sc, reg) \ 60838363Swpaul (*(u_int8_t *)((sc)->csr + (u_int32_t)(reg))) 60938363Swpaul#endif 61038363Swpaul 61138363Swpaul#define XL_SEL_WIN(x) \ 61238363Swpaul CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x) 61338363Swpaul#define XL_TIMEOUT 1000 61438363Swpaul 61538363Swpaul/* 61638363Swpaul * General constants that are fun to know. 61738363Swpaul * 61838363Swpaul * 3Com PCI vendor ID 61938363Swpaul */ 62038363Swpaul#define TC_VENDORID 0x10B7 62138363Swpaul 62238363Swpaul/* 62338363Swpaul * 3Com chip device IDs. 62438363Swpaul */ 62538363Swpaul#define TC_DEVICEID_BOOMERANG_10BT 0x9000 62638363Swpaul#define TC_DEVICEID_BOOMERANG_10BT_COMBO 0x9001 62738363Swpaul#define TC_DEVICEID_BOOMERANG_10_100BT 0x9050 62838363Swpaul#define TC_DEVICEID_BOOMERANG_100BT4 0x9051 62938363Swpaul#define TC_DEVICEID_CYCLONE_10BT 0x9004 63038363Swpaul#define TC_DEVICEID_CYCLONE_10BT_COMBO 0x9005 63138363Swpaul#define TC_DEVICEID_CYCLONE_10_100BT 0x9055 63238363Swpaul#define TC_DEVICEID_CYCLONE_10_100BT4 0x9056 63338363Swpaul 63438363Swpaul 63538363Swpaul/* 63638363Swpaul * Texas Instruments PHY identifiers 63738363Swpaul * 63838363Swpaul * The ThunderLAN manual has a curious and confusing error in it. 63938363Swpaul * In chapter 7, which describes PHYs, it says that TI PHYs have 64038363Swpaul * the following ID codes, where xx denotes a revision: 64138363Swpaul * 64238363Swpaul * 0x4000501xx internal 10baseT PHY 64338363Swpaul * 0x4000502xx TNETE211 100VG-AnyLan PMI 64438363Swpaul * 64538363Swpaul * The problem here is that these are not valid 32-bit hex numbers: 64638363Swpaul * there's one digit too many. My guess is that they mean the internal 64738363Swpaul * 10baseT PHY is 0x4000501x and the TNETE211 is 0x4000502x since these 64838363Swpaul * are the only numbers that make sense. 64938363Swpaul */ 65038363Swpaul#define TI_PHY_VENDORID 0x4000 65138363Swpaul#define TI_PHY_10BT 0x501F 65238363Swpaul#define TI_PHY_100VGPMI 0x502F 65338363Swpaul 65438363Swpaul/* 65538363Swpaul * These ID values are for the NS DP83840A 10/100 PHY 65638363Swpaul */ 65738363Swpaul#define NS_PHY_VENDORID 0x2000 65838363Swpaul#define NS_PHY_83840A 0x5C0F 65938363Swpaul 66038363Swpaul/* 66138363Swpaul * Level 1 10/100 PHY 66238363Swpaul */ 66338363Swpaul#define LEVEL1_PHY_VENDORID 0x7810 66438363Swpaul#define LEVEL1_PHY_LXT970 0x000F 66538363Swpaul 66638363Swpaul/* 66738363Swpaul * Intel 82555 10/100 PHY 66838363Swpaul */ 66938363Swpaul#define INTEL_PHY_VENDORID 0x0A28 67038363Swpaul#define INTEL_PHY_82555 0x015F 67138363Swpaul 67238363Swpaul/* 67338363Swpaul * SEEQ 80220 10/100 PHY 67438363Swpaul */ 67538363Swpaul#define SEEQ_PHY_VENDORID 0x0016 67638363Swpaul#define SEEQ_PHY_80220 0xF83F 67738363Swpaul 67838363Swpaul 67938363Swpaul/* 68038363Swpaul * PCI low memory base and low I/O base register, and 68138363Swpaul * other PCI registers. Note: some are only available on 68238363Swpaul * the 3c905B, in particular those that related to power management. 68338363Swpaul */ 68438363Swpaul 68538363Swpaul#define XL_PCI_VENDOR_ID 0x00 68638363Swpaul#define XL_PCI_DEVICE_ID 0x02 68738363Swpaul#define XL_PCI_COMMAND 0x04 68838363Swpaul#define XL_PCI_STATUS 0x06 68938363Swpaul#define XL_PCI_CLASSCODE 0x09 69038363Swpaul#define XL_PCI_LATENCY_TIMER 0x0D 69138363Swpaul#define XL_PCI_HEADER_TYPE 0x0E 69238363Swpaul#define XL_PCI_LOIO 0x10 69338363Swpaul#define XL_PCI_LOMEM 0x14 69438363Swpaul#define XL_PCI_BIOSROM 0x30 69538363Swpaul#define XL_PCI_INTLINE 0x3C 69638363Swpaul#define XL_PCI_INTPIN 0x3D 69738363Swpaul#define XL_PCI_MINGNT 0x3E 69838363Swpaul#define XL_PCI_MINLAT 0x0F 69938363Swpaul#define XL_PCI_RESETOPT 0x48 70038363Swpaul#define XL_PCI_EEPROM_DATA 0x4C 70138363Swpaul 70238363Swpaul/* 3c905B-only registers */ 70338363Swpaul#define XL_PCI_CAPID 0xDC /* 8 bits */ 70438363Swpaul#define XL_PCI_NEXTPTR 0xDD /* 8 bits */ 70538363Swpaul#define XL_PCI_PWRMGMTCAP 0xDE /* 16 bits */ 70638363Swpaul#define XL_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ 70738363Swpaul 70838363Swpaul#define XL_PSTATE_MASK 0x0003 70938363Swpaul#define XL_PSTATE_D0 0x0000 71038363Swpaul#define XL_PSTATE_D1 0x0002 71138363Swpaul#define XL_PSTATE_D2 0x0002 71238363Swpaul#define XL_PSTATE_D3 0x0003 71338363Swpaul#define XL_PME_EN 0x0010 71438363Swpaul#define XL_PME_STATUS 0x8000 71538363Swpaul 71638363Swpaul#define PHY_UNKNOWN 6 71738363Swpaul 71838363Swpaul#define XL_PHYADDR_MIN 0x00 71938363Swpaul#define XL_PHYADDR_MAX 0x1F 72038363Swpaul 72138363Swpaul#define XL_PHY_GENCTL 0x00 72238363Swpaul#define XL_PHY_GENSTS 0x01 72338363Swpaul#define XL_PHY_VENID 0x02 72438363Swpaul#define XL_PHY_DEVID 0x03 72538363Swpaul#define XL_PHY_ANAR 0x04 72638363Swpaul#define XL_PHY_LPAR 0x05 72738363Swpaul#define XL_PHY_ANEXP 0x06 72838363Swpaul 72938363Swpaul#define PHY_ANAR_NEXTPAGE 0x8000 73038363Swpaul#define PHY_ANAR_RSVD0 0x4000 73138363Swpaul#define PHY_ANAR_TLRFLT 0x2000 73238363Swpaul#define PHY_ANAR_RSVD1 0x1000 73338363Swpaul#define PHY_ANAR_RSVD2 0x0800 73438363Swpaul#define PHY_ANAR_RSVD3 0x0400 73538363Swpaul#define PHY_ANAR_100BT4 0x0200 73638363Swpaul#define PHY_ANAR_100BTXFULL 0x0100 73738363Swpaul#define PHY_ANAR_100BTXHALF 0x0080 73838363Swpaul#define PHY_ANAR_10BTFULL 0x0040 73938363Swpaul#define PHY_ANAR_10BTHALF 0x0020 74038363Swpaul#define PHY_ANAR_PROTO4 0x0010 74138363Swpaul#define PHY_ANAR_PROTO3 0x0008 74238363Swpaul#define PHY_ANAR_PROTO2 0x0004 74338363Swpaul#define PHY_ANAR_PROTO1 0x0002 74438363Swpaul#define PHY_ANAR_PROTO0 0x0001 74538363Swpaul 74638363Swpaul/* 74738363Swpaul * These are the register definitions for the PHY (physical layer 74838363Swpaul * interface chip). 74938363Swpaul */ 75038363Swpaul/* 75138363Swpaul * PHY BMCR Basic Mode Control Register 75238363Swpaul */ 75338363Swpaul#define PHY_BMCR 0x00 75438363Swpaul#define PHY_BMCR_RESET 0x8000 75538363Swpaul#define PHY_BMCR_LOOPBK 0x4000 75638363Swpaul#define PHY_BMCR_SPEEDSEL 0x2000 75738363Swpaul#define PHY_BMCR_AUTONEGENBL 0x1000 75838363Swpaul#define PHY_BMCR_RSVD0 0x0800 /* write as zero */ 75938363Swpaul#define PHY_BMCR_ISOLATE 0x0400 76038363Swpaul#define PHY_BMCR_AUTONEGRSTR 0x0200 76138363Swpaul#define PHY_BMCR_DUPLEX 0x0100 76238363Swpaul#define PHY_BMCR_COLLTEST 0x0080 76338363Swpaul#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */ 76438363Swpaul#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */ 76538363Swpaul#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */ 76638363Swpaul#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */ 76738363Swpaul#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */ 76838363Swpaul#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */ 76938363Swpaul#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */ 77038363Swpaul/* 77138363Swpaul * RESET: 1 == software reset, 0 == normal operation 77238363Swpaul * Resets status and control registers to default values. 77338363Swpaul * Relatches all hardware config values. 77438363Swpaul * 77538363Swpaul * LOOPBK: 1 == loopback operation enabled, 0 == normal operation 77638363Swpaul * 77738363Swpaul * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s 77838363Swpaul * Link speed is selected byt his bit or if auto-negotiation if bit 77938363Swpaul * 12 (AUTONEGENBL) is set (in which case the value of this register 78038363Swpaul * is ignored). 78138363Swpaul * 78238363Swpaul * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled 78338363Swpaul * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13 78438363Swpaul * determine speed and mode. Should be cleared and then set if PHY configured 78538363Swpaul * for no autoneg on startup. 78638363Swpaul * 78738363Swpaul * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation 78838363Swpaul * 78938363Swpaul * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation 79038363Swpaul * 79138363Swpaul * DUPLEX: 1 == full duplex mode, 0 == half duplex mode 79238363Swpaul * 79338363Swpaul * COLLTEST: 1 == collision test enabled, 0 == normal operation 79438363Swpaul */ 79538363Swpaul 79638363Swpaul/* 79738363Swpaul * PHY, BMSR Basic Mode Status Register 79838363Swpaul */ 79938363Swpaul#define PHY_BMSR 0x01 80038363Swpaul#define PHY_BMSR_100BT4 0x8000 80138363Swpaul#define PHY_BMSR_100BTXFULL 0x4000 80238363Swpaul#define PHY_BMSR_100BTXHALF 0x2000 80338363Swpaul#define PHY_BMSR_10BTFULL 0x1000 80438363Swpaul#define PHY_BMSR_10BTHALF 0x0800 80538363Swpaul#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */ 80638363Swpaul#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */ 80738363Swpaul#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */ 80838363Swpaul#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */ 80938363Swpaul#define PHY_BMSR_MFPRESUP 0x0040 81038363Swpaul#define PHY_BMSR_AUTONEGCOMP 0x0020 81138363Swpaul#define PHY_BMSR_REMFAULT 0x0010 81238363Swpaul#define PHY_BMSR_CANAUTONEG 0x0008 81338363Swpaul#define PHY_BMSR_LINKSTAT 0x0004 81438363Swpaul#define PHY_BMSR_JABBER 0x0002 81538363Swpaul#define PHY_BMSR_EXTENDED 0x0001 816