if_xlreg.h revision 38363
1157016Sdes/* 2126274Sdes * Copyright (c) 1997, 1998 398937Sdes * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4157016Sdes * 598937Sdes * Redistribution and use in source and binary forms, with or without 6157016Sdes * modification, are permitted provided that the following conditions 7157016Sdes * are met: 8157016Sdes * 1. Redistributions of source code must retain the above copyright 998937Sdes * notice, this list of conditions and the following disclaimer. 10157016Sdes * 2. Redistributions in binary form must reproduce the above copyright 11157016Sdes * notice, this list of conditions and the following disclaimer in the 12157016Sdes * documentation and/or other materials provided with the distribution. 13157016Sdes * 3. All advertising materials mentioning features or use of this software 14157016Sdes * must display the following acknowledgement: 15157016Sdes * This product includes software developed by Bill Paul. 16157016Sdes * 4. Neither the name of the author nor the names of any co-contributors 17157016Sdes * may be used to endorse or promote products derived from this software 18157016Sdes * without specific prior written permission. 19157016Sdes * 20157016Sdes * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2198937Sdes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2298937Sdes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23157016Sdes * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24157016Sdes * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2598937Sdes * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2698937Sdes * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2798937Sdes * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2898937Sdes * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2998937Sdes * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3098937Sdes * THE POSSIBILITY OF SUCH DAMAGE. 3198937Sdes * 3298937Sdes * $Id: if_xlreg.h,v 1.12 1998/08/13 21:29:06 wpaul Exp $ 3398937Sdes */ 3498937Sdes 3598937Sdes#define XL_EE_READ 0x0080 /* read, 5 bit address */ 3698937Sdes#define XL_EE_WRITE 0x0040 /* write, 5 bit address */ 3798937Sdes#define XL_EE_ERASE 0x00c0 /* erase, 5 bit address */ 38106121Sdes#define XL_EE_EWEN 0x0030 /* erase, no data needed */ 3998937Sdes#define XL_EE_BUSY 0x8000 40106121Sdes 4198937Sdes#define XL_EE_EADDR0 0x00 /* station address, first word */ 4298937Sdes#define XL_EE_EADDR1 0x01 /* station address, next word, */ 4398937Sdes#define XL_EE_EADDR2 0x02 /* station address, last word */ 4498937Sdes#define XL_EE_PRODID 0x03 /* product ID code */ 45#define XL_EE_MDATA_DATE 0x04 /* manufacturing data, date */ 46#define XL_EE_MDATA_DIV 0x05 /* manufacturing data, division */ 47#define XL_EE_MDATA_PCODE 0x06 /* manufacturing data, product code */ 48#define XL_EE_MFG_ID 0x07 49#define XL_EE_PCI_PARM 0x08 50#define XL_EE_ROM_ONFO 0x09 51#define XL_EE_OEM_ADR0 0x0A 52#define XL_EE_OEM_ADR1 0x0B 53#define XL_EE_OEM_ADR2 0x0C 54#define XL_EE_SOFTINFO1 0x0D 55#define XL_EE_COMPAT 0x0E 56#define XL_EE_SOFTINFO2 0x0F 57#define XL_EE_CAPS 0x10 /* capabilities word */ 58#define XL_EE_RSVD0 0x11 59#define XL_EE_ICFG_0 0x12 60#define XL_EE_ICFG_1 0x13 61#define XL_EE_RSVD1 0x14 62#define XL_EE_SOFTINFO3 0x15 63#define XL_EE_RSVD_2 0x16 64 65/* 66 * Bits in the capabilities word 67 */ 68#define XL_CAPS_PNP 0x0001 69#define XL_CAPS_FULL_DUPLEX 0x0002 70#define XL_CAPS_LARGE_PKTS 0x0004 71#define XL_CAPS_SLAVE_DMA 0x0008 72#define XL_CAPS_SECOND_DMA 0x0010 73#define XL_CAPS_FULL_BM 0x0020 74#define XL_CAPS_FRAG_BM 0x0040 75#define XL_CAPS_CRC_PASSTHRU 0x0080 76#define XL_CAPS_TXDONE 0x0100 77#define XL_CAPS_NO_TXLENGTH 0x0200 78#define XL_CAPS_RX_REPEAT 0x0400 79#define XL_CAPS_SNOOPING 0x0800 80#define XL_CAPS_100MBPS 0x1000 81#define XL_CAPS_PWRMGMT 0x2000 82 83#define XL_PACKET_SIZE 1536 84 85/* 86 * Register layouts. 87 */ 88#define XL_COMMAND 0x0E 89#define XL_STATUS 0x0E 90 91#define XL_TX_STATUS 0x1B 92#define XL_TX_FREE 0x1C 93#define XL_DMACTL 0x20 94#define XL_DOWNLIST_PTR 0x24 95#define XL_TX_FREETHRESH 0x2F 96#define XL_UPLIST_PTR 0x38 97#define XL_UPLIST_STATUS 0x30 98 99#define XL_PKTSTAT_UP_STALLED 0x00002000 100#define XL_PKTSTAT_UP_ERROR 0x00004000 101#define XL_PKTSTAT_UP_CMPLT 0x00008000 102 103#define XL_DMACTL_DN_CMPLT_REQ 0x00000002 104#define XL_DMACTL_DOWN_STALLED 0x00000004 105#define XL_DMACTL_UP_CMPLT 0x00000008 106#define XL_DMACTL_DOWN_CMPLT 0x00000010 107#define XL_DMACTL_UP_RX_EARLY 0x00000020 108#define XL_DMACTL_ARM_COUNTDOWN 0x00000040 109#define XL_DMACTL_DOWN_INPROG 0x00000080 110#define XL_DMACTL_COUNTER_SPEED 0x00000100 111#define XL_DMACTL_DOWNDOWN_MODE 0x00000200 112#define XL_DMACTL_TARGET_ABORT 0x40000000 113#define XL_DMACTL_MASTER_ABORT 0x80000000 114 115/* 116 * Command codes. Some command codes require that we wait for 117 * the CMD_BUSY flag to clear. Those codes are marked as 'mustwait.' 118 */ 119#define XL_CMD_RESET 0x0000 /* mustwait */ 120#define XL_CMD_WINSEL 0x0800 121#define XL_CMD_COAX_START 0x1000 122#define XL_CMD_RX_DISABLE 0x1800 123#define XL_CMD_RX_ENABLE 0x2000 124#define XL_CMD_RX_RESET 0x2800 /* mustwait */ 125#define XL_CMD_UP_STALL 0x3000 /* mustwait */ 126#define XL_CMD_UP_UNSTALL 0x3001 127#define XL_CMD_DOWN_STALL 0x3002 /* mustwait */ 128#define XL_CMD_DOWN_UNSTALL 0x3003 129#define XL_CMD_RX_DISCARD 0x4000 130#define XL_CMD_TX_ENABLE 0x4800 131#define XL_CMD_TX_DISABLE 0x5000 132#define XL_CMD_TX_RESET 0x5800 /* mustwait */ 133#define XL_CMD_INTR_FAKE 0x6000 134#define XL_CMD_INTR_ACK 0x6800 135#define XL_CMD_INTR_ENB 0x7000 136#define XL_CMD_STAT_ENB 0x7800 137#define XL_CMD_RX_SET_FILT 0x8000 138#define XL_CMD_RX_SET_THRESH 0x8800 139#define XL_CMD_TX_SET_THRESH 0x9000 140#define XL_CMD_TX_SET_START 0x9800 141#define XL_CMD_DMA_UP 0xA000 142#define XL_CMD_DMA_STOP 0xA001 143#define XL_CMD_STATS_ENABLE 0xA800 144#define XL_CMD_STATS_DISABLE 0xB000 145#define XL_CMD_COAX_STOP 0xB800 146 147#define XL_CMD_SET_TX_RECLAIM 0xC000 /* 3c905B only */ 148#define XL_CMD_RX_SET_HASH 0xC800 /* 3c905B only */ 149 150#define XL_HASH_SET 0x0400 151#define XL_HASHFILT_SIZE 256 152 153/* 154 * status codes 155 * Note that bits 15 to 13 indicate the currently visible register window 156 * which may be anything from 0 to 7. 157 */ 158#define XL_STAT_INTLATCH 0x0001 /* 0 */ 159#define XL_STAT_ADFAIL 0x0002 /* 1 */ 160#define XL_STAT_TX_COMPLETE 0x0004 /* 2 */ 161#define XL_STAT_TX_AVAIL 0x0008 /* 3 first generation */ 162#define XL_STAT_RX_COMPLETE 0x0010 /* 4 */ 163#define XL_STAT_RX_EARLY 0x0020 /* 5 */ 164#define XL_STAT_INTREQ 0x0040 /* 6 */ 165#define XL_STAT_STATSOFLOW 0x0080 /* 7 */ 166#define XL_STAT_DMADONE 0x0100 /* 8 first generation */ 167#define XL_STAT_LINKSTAT 0x0100 /* 8 3c509B */ 168#define XL_STAT_DOWN_COMPLETE 0x0200 /* 9 */ 169#define XL_STAT_UP_COMPLETE 0x0400 /* 10 */ 170#define XL_STAT_DMABUSY 0x0800 /* 11 first generation */ 171#define XL_STAT_CMDBUSY 0x1000 /* 12 */ 172 173/* 174 * Window 0 registers 175 */ 176#define XL_W0_EE_DATA 0x0C 177#define XL_W0_EE_CMD 0x0A 178#define XL_W0_RSRC_CFG 0x08 179#define XL_W0_ADDR_CFG 0x06 180#define XL_W0_CFG_CTRL 0x04 181 182#define XL_W0_PROD_ID 0x02 183#define XL_W0_MFG_ID 0x00 184 185/* 186 * Window 1 187 */ 188 189#define XL_W1_TX_FIFO 0x10 190 191#define XL_W1_FREE_TX 0x0C 192#define XL_W1_TX_STATUS 0x0B 193#define XL_W1_TX_TIMER 0x0A 194#define XL_W1_RX_STATUS 0x08 195#define XL_W1_RX_FIFO 0x00 196 197/* 198 * RX status codes 199 */ 200#define XL_RXSTATUS_OVERRUN 0x01 201#define XL_RXSTATUS_RUNT 0x02 202#define XL_RXSTATUS_ALIGN 0x04 203#define XL_RXSTATUS_CRC 0x08 204#define XL_RXSTATUS_OVERSIZE 0x10 205#define XL_RXSTATUS_DRIBBLE 0x20 206 207/* 208 * TX status codes 209 */ 210#define XL_TXSTATUS_RECLAIM 0x02 /* 3c905B only */ 211#define XL_TXSTATUS_OVERFLOW 0x04 212#define XL_TXSTATUS_MAXCOLS 0x08 213#define XL_TXSTATUS_UNDERRUN 0x10 214#define XL_TXSTATUS_JABBER 0x20 215#define XL_TXSTATUS_INTREQ 0x40 216#define XL_TXSTATUS_COMPLETE 0x80 217 218/* 219 * Window 2 220 */ 221#define XL_W2_RESET_OPTIONS 0x0C /* 3c905B only */ 222#define XL_W2_STATION_MASK_HI 0x0A 223#define XL_W2_STATION_MASK_MID 0x08 224#define XL_W2_STATION_MASK_LO 0x06 225#define XL_W2_STATION_ADDR_HI 0x04 226#define XL_W2_STATION_ADDR_MID 0x02 227#define XL_W2_STATION_ADDR_LO 0x00 228 229#define XL_RESETOPT_FEATUREMASK 0x0001|0x0002|0x004 230#define XL_RESETOPT_D3RESETDIS 0x0008 231#define XL_RESETOPT_DISADVFD 0x0010 232#define XL_RESETOPT_DISADV100 0x0020 233#define XL_RESETOPT_DISAUTONEG 0x0040 234#define XL_RESETOPT_DEBUGMODE 0x0080 235#define XL_RESETOPT_FASTAUTO 0x0100 236#define XL_RESETOPT_FASTEE 0x0200 237#define XL_RESETOPT_FORCEDCONF 0x0400 238#define XL_RESETOPT_TESTPDTPDR 0x0800 239#define XL_RESETOPT_TEST100TX 0x1000 240#define XL_RESETOPT_TEST100RX 0x2000 241 242/* 243 * Window 3 (fifo management) 244 */ 245#define XL_W3_INTERNAL_CFG 0x00 246#define XL_W3_RESET_OPT 0x08 247#define XL_W3_FREE_TX 0x0C 248#define XL_W3_FREE_RX 0x0A 249#define XL_W3_MAC_CTRL 0x06 250 251#define XL_ICFG_CONNECTOR_MASK 0x00F00000 252#define XL_ICFG_CONNECTOR_BITS 20 253 254#define XL_ICFG_RAMSIZE_MASK 0x00000007 255#define XL_ICFG_RAMWIDTH 0x00000008 256#define XL_ICFG_ROMSIZE_MASK (0x00000040|0x00000080) 257#define XL_ICFG_DISABLE_BASSD 0x00000100 258#define XL_ICFG_RAMLOC 0x00000200 259#define XL_ICFG_RAMPART (0x00010000|0x00020000) 260#define XL_ICFG_XCVRSEL (0x00100000|0x00200000|0x00400000) 261#define XL_ICFG_AUTOSEL 0x01000000 262 263#define XL_XCVR_10BT 0x00 264#define XL_XCVR_AUI 0x01 265#define XL_XCVR_RSVD_0 0x02 266#define XL_XCVR_COAX 0x03 267#define XL_XCVR_100BTX 0x04 268#define XL_XCVR_100BFX 0x05 269#define XL_XCVR_MII 0x06 270#define XL_XCVR_RSVD_1 0x07 271#define XL_XCVR_AUTO 0x08 /* 3c905B only */ 272 273#define XL_MACCTRL_DEFER_EXT_END 0x0001 274#define XL_MACCTRL_DEFER_0 0x0002 275#define XL_MACCTRL_DEFER_1 0x0004 276#define XL_MACCTRL_DEFER_2 0x0008 277#define XL_MACCTRL_DEFER_3 0x0010 278#define XL_MACCTRL_DUPLEX 0x0020 279#define XL_MACCTRL_ALLOW_LARGE_PACK 0x0040 280#define XL_MACCTRL_EXTEND_AFTER_COL 0x0080 (3c905B only) 281#define XL_MACCTRL_FLOW_CONTROL_ENB 0x0100 (3c905B only) 282#define XL_MACCTRL_VLT_END 0x0200 (3c905B only) 283 284/* 285 * The 'reset options' register contains power-on reset values 286 * loaded from the EEPROM. This includes the supported media 287 * types on the card. It is also known as the media options register. 288 */ 289#define XL_W3_MEDIA_OPT 0x08 290 291#define XL_MEDIAOPT_BT4 0x0001 /* MII */ 292#define XL_MEDIAOPT_BTX 0x0002 /* on-chip */ 293#define XL_MEDIAOPT_BFX 0x0004 /* on-chip */ 294#define XL_MEDIAOPT_BT 0x0008 /* on-chip */ 295#define XL_MEDIAOPT_BNC 0x0010 /* on-chip */ 296#define XL_MEDIAOPT_AUI 0x0020 /* on-chip */ 297#define XL_MEDIAOPT_MII 0x0040 /* MII */ 298#define XL_MEDIAOPT_VCO 0x0100 /* 1st gen chip only */ 299 300#define XL_MEDIAOPT_10FL 0x0100 /* 3x905B only, on-chip */ 301#define XL_MEDIAOPT_MASK 0x01FF 302 303/* 304 * Window 4 (diagnostics) 305 */ 306#define XL_W4_UPPERBYTESOK 0x0D 307#define XL_W4_BADSSD 0x0C 308#define XL_W4_MEDIA_STATUS 0x0A 309#define XL_W4_PHY_MGMT 0x08 310#define XL_W4_NET_DIAG 0x06 311#define XL_W4_FIFO_DIAG 0x04 312#define XL_W4_VCO_DIAG 0x02 313 314#define XL_W4_CTRLR_STAT 0x08 315#define XL_W4_TX_DIAG 0x00 316 317#define XL_MII_CLK 0x01 318#define XL_MII_DATA 0x02 319#define XL_MII_DIR 0x04 320 321#define XL_MEDIA_SQE 0x0008 322#define XL_MEDIA_10TP 0x00C0 323#define XL_MEDIA_LNK 0x0080 324#define XL_MEDIA_LNKBEAT 0x0800 325 326#define XL_MEDIASTAT_CRCSTRIP 0x0004 327#define XL_MEDIASTAT_SQEENB 0x0008 328#define XL_MEDIASTAT_COLDET 0x0010 329#define XL_MEDIASTAT_CARRIER 0x0020 330#define XL_MEDIASTAT_JABGUARD 0x0040 331#define XL_MEDIASTAT_LINKBEAT 0x0080 332#define XL_MEDIASTAT_JABDETECT 0x0200 333#define XL_MEDIASTAT_POLREVERS 0x0400 334#define XL_MEDIASTAT_LINKDETECT 0x0800 335#define XL_MEDIASTAT_TXINPROG 0x1000 336#define XL_MEDIASTAT_DCENB 0x4000 337#define XL_MEDIASTAT_AUIDIS 0x8000 338 339#define XL_NETDIAG_TEST_LOWVOLT 0x0001 340#define XL_NETDIAG_ASIC_REVMASK (0x0002|0x0004|0x0008|0x0010|0x0020) 341#define XL_NETDIAG_UPPER_BYTES_ENABLE 0x0040 342#define XL_NETDIAG_STATS_ENABLED 0x0080 343#define XL_NETDIAG_TX_FATALERR 0x0100 344#define XL_NETDIAG_TRANSMITTING 0x0200 345#define XL_NETDIAG_RX_ENABLED 0x0400 346#define XL_NETDIAG_TX_ENABLED 0x0800 347#define XL_NETDIAG_FIFO_LOOPBACK 0x1000 348#define XL_NETDIAG_MAC_LOOPBACK 0x2000 349#define XL_NETDIAG_ENDEC_LOOPBACK 0x4000 350#define XL_NETDIAG_EXTERNAL_LOOP 0x8000 351 352/* 353 * Window 5 354 */ 355#define XL_W5_STAT_ENB 0x0C 356#define XL_W5_INTR_ENB 0x0A 357#define XL_W5_RX_FILTER 0x08 358#define XL_W5_RX_EARLYTHRESH 0x06 359#define XL_W5_TX_AVAILTHRESH 0x02 360#define XL_W5_TX_STARTTHRESH 0x00 361 362/* 363 * RX filter bits 364 */ 365#define XL_RXFILTER_INDIVIDUAL 0x01 366#define XL_RXFILTER_ALLMULTI 0x02 367#define XL_RXFILTER_BROADCAST 0x04 368#define XL_RXFILTER_ALLFRAMES 0x08 369#define XL_RXFILTER_MULTIHASH 0x10 /* 3c905B only */ 370 371/* 372 * Window 6 (stats) 373 */ 374#define XL_W6_TX_BYTES_OK 0x0C 375#define XL_W6_RX_BYTES_OK 0x0A 376#define XL_W6_UPPER_FRAMES_OK 0x09 377#define XL_W6_DEFERRED 0x08 378#define XL_W6_RX_OK 0x07 379#define XL_W6_TX_OK 0x06 380#define XL_W6_RX_OVERRUN 0x05 381#define XL_W6_COL_LATE 0x04 382#define XL_W6_COL_SINGLE 0x03 383#define XL_W6_COL_MULTIPLE 0x02 384#define XL_W6_SQE_ERRORS 0x01 385#define XL_W6_CARRIER_LOST 0x00 386 387/* 388 * Window 7 (bus master control) 389 */ 390#define XL_W7_BM_ADDR 0x00 391#define XL_W7_BM_LEN 0x06 392#define XL_W7_BM_STATUS 0x0B 393#define XL_W7_BM_TIMEr 0x0A 394 395/* 396 * bus master control registers 397 */ 398#define XL_BM_PKTSTAT 0x20 399#define XL_BM_DOWNLISTPTR 0x24 400#define XL_BM_FRAGADDR 0x28 401#define XL_BM_FRAGLEN 0x2C 402#define XL_BM_TXFREETHRESH 0x2F 403#define XL_BM_UPPKTSTAT 0x30 404#define XL_BM_UPLISTPTR 0x38 405 406#define XL_LAST_FRAG 0x80000000 407 408/* 409 * Boomerang/Cyclone TX/RX list structure. 410 * For the TX lists, bits 0 to 12 of the status word indicate 411 * length. 412 * This looks suspiciously like the ThunderLAN, doesn't it. 413 */ 414struct xl_frag { 415 u_int32_t xl_addr; /* 63 addr/len pairs */ 416 u_int32_t xl_len; 417}; 418 419struct xl_list { 420 u_int32_t xl_next; /* final entry has 0 nextptr */ 421 u_int32_t xl_status; 422 struct xl_frag xl_frag[63]; 423}; 424 425struct xl_list_onefrag { 426 u_int32_t xl_next; /* final entry has 0 nextptr */ 427 u_int32_t xl_status; 428 struct xl_frag xl_frag; 429}; 430 431#define XL_MAXFRAGS 63 432#define XL_RX_LIST_CNT 4 433#define XL_TX_LIST_CNT 10 434#define XL_MIN_FRAMELEN 60 435 436struct xl_list_data { 437 struct xl_list_onefrag xl_rx_list[XL_RX_LIST_CNT]; 438 struct xl_list xl_tx_list[XL_TX_LIST_CNT]; 439 unsigned char xl_pad[XL_MIN_FRAMELEN]; 440}; 441 442struct xl_chain { 443 struct xl_list *xl_ptr; 444 struct mbuf *xl_mbuf; 445 struct xl_chain *xl_next; 446}; 447 448struct xl_chain_onefrag { 449 struct xl_list_onefrag *xl_ptr; 450 struct mbuf *xl_mbuf; 451 struct xl_chain_onefrag *xl_next; 452}; 453 454struct xl_chain_data { 455 struct xl_chain_onefrag xl_rx_chain[XL_RX_LIST_CNT]; 456 struct xl_chain xl_tx_chain[XL_TX_LIST_CNT]; 457 458 struct xl_chain_onefrag *xl_rx_head; 459 460 struct xl_chain *xl_tx_head; 461 struct xl_chain *xl_tx_tail; 462 struct xl_chain *xl_tx_free; 463}; 464 465#define XL_RXSTAT_LENMASK 0x00001FFF 466#define XL_RXSTAT_UP_ERROR 0x00004000 467#define XL_RXSTAT_UP_CMPLT 0x00008000 468#define XL_RXSTAT_UP_OVERRUN 0x00010000 469#define XL_RXSTAT_RUNT 0x00020000 470#define XL_RXSTAT_ALIGN 0x00040000 471#define XL_RXSTAT_CRC 0x00080000 472#define XL_RXSTAT_OVERSIZE 0x00100000 473#define XL_RXSTAT_DRIBBLE 0x00800000 474#define XL_RXSTAT_UP_OFLOW 0x01000000 475#define XL_RXSTAT_IPCKERR 0x02000000 /* 3c905B only */ 476#define XL_RXSTAT_TCPCKERR 0x04000000 /* 3c905B only */ 477#define XL_RXSTAT_UDPCKERR 0x08000000 /* 3c905B only */ 478#define XL_RXSTAT_BUFEN 0x10000000 /* 3c905B only */ 479#define XL_RXSTAT_IPCKOK 0x20000000 /* 3c905B only */ 480#define XL_RXSTAT_TCPCOK 0x40000000 /* 3c905B only */ 481#define XL_RXSTAT_UDPCKOK 0x80000000 /* 3c905B only */ 482 483#define XL_TXSTAT_LENMASK 0x00001FFF 484#define XL_TXSTAT_CRCDIS 0x00002000 485#define XL_TXSTAT_TX_INTR 0x00008000 486#define XL_TXSTAT_DL_COMPLETE 0x00010000 487#define XL_TXSTAT_IPCKSUM 0x02000000 /* 3c905B only */ 488#define XL_TXSTAT_TCPCKSUM 0x04000000 /* 3c905B only */ 489#define XL_TXSTAT_UDPCKSUM 0x08000000 /* 3c905B only */ 490#define XL_TXSTAT_DL_INTR 0x80000000 491 492#define XL_CAPABILITY_BM 0x20 493 494 495struct xl_type { 496 u_int16_t xl_vid; 497 u_int16_t xl_did; 498 char *xl_name; 499}; 500 501struct xl_mii_frame { 502 u_int8_t mii_stdelim; 503 u_int8_t mii_opcode; 504 u_int8_t mii_phyaddr; 505 u_int8_t mii_regaddr; 506 u_int8_t mii_turnaround; 507 u_int16_t mii_data; 508}; 509 510/* 511 * MII constants 512 */ 513#define XL_MII_STARTDELIM 0x01 514#define XL_MII_READOP 0x02 515#define XL_MII_WRITEOP 0x01 516#define XL_MII_TURNAROUND 0x02 517 518/* 519 * The 3C905B adapters implement a few features that we want to 520 * take advantage of, namely the multicast hash filter. With older 521 * chips, you only have the option of turning on reception of all 522 * multicast frames, which is kind of lame. 523 */ 524#define XL_TYPE_905B 1 525#define XL_TYPE_90X 2 526 527#define XL_FLAG_FORCEDELAY 1 528#define XL_FLAG_SCHEDDELAY 2 529#define XL_FLAG_DELAYTIMEO 3 530 531struct xl_softc { 532 struct arpcom arpcom; /* interface info */ 533 struct ifmedia ifmedia; /* media info */ 534 u_int32_t iobase; /* pointer to PIO space */ 535#ifndef XL_USEIOSPACE 536 volatile caddr_t csr; /* pointer to register map */ 537#endif 538 struct xl_type *xl_info; /* 3Com adapter info */ 539 struct xl_type *xl_pinfo; /* phy info */ 540 u_int8_t xl_unit; /* interface number */ 541 u_int8_t xl_type; 542 u_int8_t xl_phy_addr; /* PHY address */ 543 u_int32_t xl_xcvr; 544 u_int16_t xl_media; 545 u_int16_t xl_caps; 546 u_int8_t xl_tx_pend; /* TX pending */ 547 u_int8_t xl_want_auto; 548 u_int8_t xl_autoneg; 549 u_int8_t xl_stats_no_timeout; 550 caddr_t xl_ldata_ptr; 551 struct xl_list_data *xl_ldata; 552 struct xl_chain_data xl_cdata; 553 struct callout_handle xl_stat_ch; 554}; 555 556#define xl_rx_goodframes(x) \ 557 ((x.xl_upper_frames_ok & 0x03) << 8) | x.xl_rx_frames_ok 558 559#define xl_tx_goodframes(x) \ 560 ((x.xl_upper_frames_ok & 0x30) << 4) | x.xl_tx_frames_ok 561 562struct xl_stats { 563 u_int8_t xl_carrier_lost; 564 u_int8_t xl_sqe_errs; 565 u_int8_t xl_tx_multi_collision; 566 u_int8_t xl_tx_single_collision; 567 u_int8_t xl_tx_late_collision; 568 u_int8_t xl_rx_overrun; 569 u_int8_t xl_tx_frames_ok; 570 u_int8_t xl_rx_frames_ok; 571 u_int8_t xl_tx_deferred; 572 u_int8_t xl_upper_frames_ok; 573 u_int16_t xl_rx_bytes_ok; 574 u_int16_t xl_tx_bytes_ok; 575 u_int16_t status; 576}; 577 578/* 579 * register space access macros 580 */ 581#ifdef XL_USEIOSPACE 582#define CSR_WRITE_4(sc, reg, val) \ 583 outl(sc->iobase + (u_int32_t)(reg), val) 584#define CSR_WRITE_2(sc, reg, val) \ 585 outw(sc->iobase + (u_int32_t)(reg), val) 586#define CSR_WRITE_1(sc, reg, val) \ 587 outb(sc->iobase + (u_int32_t)(reg), val) 588 589#define CSR_READ_4(sc, reg) \ 590 inl(sc->iobase + (u_int32_t)(reg)) 591#define CSR_READ_2(sc, reg) \ 592 inw(sc->iobase + (u_int32_t)(reg)) 593#define CSR_READ_1(sc, reg) \ 594 inb(sc->iobase + (u_int32_t)(reg)) 595#else 596#define CSR_WRITE_4(sc, reg, val) \ 597 ((*(u_int32_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int32_t)(val)) 598#define CSR_WRITE_2(sc, reg, val) \ 599 ((*(u_int16_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int16_t)(val)) 600#define CSR_WRITE_1(sc, reg, val) \ 601 ((*(u_int8_t*)((sc)->csr + (u_int32_t)(reg))) = (u_int8_t)(val)) 602 603#define CSR_READ_4(sc, reg) \ 604 (*(u_int32_t *)((sc)->csr + (u_int32_t)(reg))) 605#define CSR_READ_2(sc, reg) \ 606 (*(u_int16_t *)((sc)->csr + (u_int32_t)(reg))) 607#define CSR_READ_1(sc, reg) \ 608 (*(u_int8_t *)((sc)->csr + (u_int32_t)(reg))) 609#endif 610 611#define XL_SEL_WIN(x) \ 612 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x) 613#define XL_TIMEOUT 1000 614 615/* 616 * General constants that are fun to know. 617 * 618 * 3Com PCI vendor ID 619 */ 620#define TC_VENDORID 0x10B7 621 622/* 623 * 3Com chip device IDs. 624 */ 625#define TC_DEVICEID_BOOMERANG_10BT 0x9000 626#define TC_DEVICEID_BOOMERANG_10BT_COMBO 0x9001 627#define TC_DEVICEID_BOOMERANG_10_100BT 0x9050 628#define TC_DEVICEID_BOOMERANG_100BT4 0x9051 629#define TC_DEVICEID_CYCLONE_10BT 0x9004 630#define TC_DEVICEID_CYCLONE_10BT_COMBO 0x9005 631#define TC_DEVICEID_CYCLONE_10_100BT 0x9055 632#define TC_DEVICEID_CYCLONE_10_100BT4 0x9056 633 634 635/* 636 * Texas Instruments PHY identifiers 637 * 638 * The ThunderLAN manual has a curious and confusing error in it. 639 * In chapter 7, which describes PHYs, it says that TI PHYs have 640 * the following ID codes, where xx denotes a revision: 641 * 642 * 0x4000501xx internal 10baseT PHY 643 * 0x4000502xx TNETE211 100VG-AnyLan PMI 644 * 645 * The problem here is that these are not valid 32-bit hex numbers: 646 * there's one digit too many. My guess is that they mean the internal 647 * 10baseT PHY is 0x4000501x and the TNETE211 is 0x4000502x since these 648 * are the only numbers that make sense. 649 */ 650#define TI_PHY_VENDORID 0x4000 651#define TI_PHY_10BT 0x501F 652#define TI_PHY_100VGPMI 0x502F 653 654/* 655 * These ID values are for the NS DP83840A 10/100 PHY 656 */ 657#define NS_PHY_VENDORID 0x2000 658#define NS_PHY_83840A 0x5C0F 659 660/* 661 * Level 1 10/100 PHY 662 */ 663#define LEVEL1_PHY_VENDORID 0x7810 664#define LEVEL1_PHY_LXT970 0x000F 665 666/* 667 * Intel 82555 10/100 PHY 668 */ 669#define INTEL_PHY_VENDORID 0x0A28 670#define INTEL_PHY_82555 0x015F 671 672/* 673 * SEEQ 80220 10/100 PHY 674 */ 675#define SEEQ_PHY_VENDORID 0x0016 676#define SEEQ_PHY_80220 0xF83F 677 678 679/* 680 * PCI low memory base and low I/O base register, and 681 * other PCI registers. Note: some are only available on 682 * the 3c905B, in particular those that related to power management. 683 */ 684 685#define XL_PCI_VENDOR_ID 0x00 686#define XL_PCI_DEVICE_ID 0x02 687#define XL_PCI_COMMAND 0x04 688#define XL_PCI_STATUS 0x06 689#define XL_PCI_CLASSCODE 0x09 690#define XL_PCI_LATENCY_TIMER 0x0D 691#define XL_PCI_HEADER_TYPE 0x0E 692#define XL_PCI_LOIO 0x10 693#define XL_PCI_LOMEM 0x14 694#define XL_PCI_BIOSROM 0x30 695#define XL_PCI_INTLINE 0x3C 696#define XL_PCI_INTPIN 0x3D 697#define XL_PCI_MINGNT 0x3E 698#define XL_PCI_MINLAT 0x0F 699#define XL_PCI_RESETOPT 0x48 700#define XL_PCI_EEPROM_DATA 0x4C 701 702/* 3c905B-only registers */ 703#define XL_PCI_CAPID 0xDC /* 8 bits */ 704#define XL_PCI_NEXTPTR 0xDD /* 8 bits */ 705#define XL_PCI_PWRMGMTCAP 0xDE /* 16 bits */ 706#define XL_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ 707 708#define XL_PSTATE_MASK 0x0003 709#define XL_PSTATE_D0 0x0000 710#define XL_PSTATE_D1 0x0002 711#define XL_PSTATE_D2 0x0002 712#define XL_PSTATE_D3 0x0003 713#define XL_PME_EN 0x0010 714#define XL_PME_STATUS 0x8000 715 716#define PHY_UNKNOWN 6 717 718#define XL_PHYADDR_MIN 0x00 719#define XL_PHYADDR_MAX 0x1F 720 721#define XL_PHY_GENCTL 0x00 722#define XL_PHY_GENSTS 0x01 723#define XL_PHY_VENID 0x02 724#define XL_PHY_DEVID 0x03 725#define XL_PHY_ANAR 0x04 726#define XL_PHY_LPAR 0x05 727#define XL_PHY_ANEXP 0x06 728 729#define PHY_ANAR_NEXTPAGE 0x8000 730#define PHY_ANAR_RSVD0 0x4000 731#define PHY_ANAR_TLRFLT 0x2000 732#define PHY_ANAR_RSVD1 0x1000 733#define PHY_ANAR_RSVD2 0x0800 734#define PHY_ANAR_RSVD3 0x0400 735#define PHY_ANAR_100BT4 0x0200 736#define PHY_ANAR_100BTXFULL 0x0100 737#define PHY_ANAR_100BTXHALF 0x0080 738#define PHY_ANAR_10BTFULL 0x0040 739#define PHY_ANAR_10BTHALF 0x0020 740#define PHY_ANAR_PROTO4 0x0010 741#define PHY_ANAR_PROTO3 0x0008 742#define PHY_ANAR_PROTO2 0x0004 743#define PHY_ANAR_PROTO1 0x0002 744#define PHY_ANAR_PROTO0 0x0001 745 746/* 747 * These are the register definitions for the PHY (physical layer 748 * interface chip). 749 */ 750/* 751 * PHY BMCR Basic Mode Control Register 752 */ 753#define PHY_BMCR 0x00 754#define PHY_BMCR_RESET 0x8000 755#define PHY_BMCR_LOOPBK 0x4000 756#define PHY_BMCR_SPEEDSEL 0x2000 757#define PHY_BMCR_AUTONEGENBL 0x1000 758#define PHY_BMCR_RSVD0 0x0800 /* write as zero */ 759#define PHY_BMCR_ISOLATE 0x0400 760#define PHY_BMCR_AUTONEGRSTR 0x0200 761#define PHY_BMCR_DUPLEX 0x0100 762#define PHY_BMCR_COLLTEST 0x0080 763#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */ 764#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */ 765#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */ 766#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */ 767#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */ 768#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */ 769#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */ 770/* 771 * RESET: 1 == software reset, 0 == normal operation 772 * Resets status and control registers to default values. 773 * Relatches all hardware config values. 774 * 775 * LOOPBK: 1 == loopback operation enabled, 0 == normal operation 776 * 777 * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s 778 * Link speed is selected byt his bit or if auto-negotiation if bit 779 * 12 (AUTONEGENBL) is set (in which case the value of this register 780 * is ignored). 781 * 782 * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled 783 * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13 784 * determine speed and mode. Should be cleared and then set if PHY configured 785 * for no autoneg on startup. 786 * 787 * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation 788 * 789 * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation 790 * 791 * DUPLEX: 1 == full duplex mode, 0 == half duplex mode 792 * 793 * COLLTEST: 1 == collision test enabled, 0 == normal operation 794 */ 795 796/* 797 * PHY, BMSR Basic Mode Status Register 798 */ 799#define PHY_BMSR 0x01 800#define PHY_BMSR_100BT4 0x8000 801#define PHY_BMSR_100BTXFULL 0x4000 802#define PHY_BMSR_100BTXHALF 0x2000 803#define PHY_BMSR_10BTFULL 0x1000 804#define PHY_BMSR_10BTHALF 0x0800 805#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */ 806#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */ 807#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */ 808#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */ 809#define PHY_BMSR_MFPRESUP 0x0040 810#define PHY_BMSR_AUTONEGCOMP 0x0020 811#define PHY_BMSR_REMFAULT 0x0010 812#define PHY_BMSR_CANAUTONEG 0x0008 813#define PHY_BMSR_LINKSTAT 0x0004 814#define PHY_BMSR_JABBER 0x0002 815#define PHY_BMSR_EXTENDED 0x0001 816