if_wpireg.h revision 282383
1160079Smjacob/* $FreeBSD: head/sys/dev/wpi/if_wpireg.h 282383 2015-05-03 23:03:06Z adrian $ */ 2160079Smjacob 3160079Smjacob/*- 4160079Smjacob * Copyright (c) 2006,2007 5160079Smjacob * Damien Bergamini <damien.bergamini@free.fr> 6160079Smjacob * 7160079Smjacob * Permission to use, copy, modify, and distribute this software for any 8160079Smjacob * purpose with or without fee is hereby granted, provided that the above 9160079Smjacob * copyright notice and this permission notice appear in all copies. 10160079Smjacob * 11160079Smjacob * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12160079Smjacob * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13160079Smjacob * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14160079Smjacob * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15160079Smjacob * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16160079Smjacob * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17160079Smjacob * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18160079Smjacob */ 19160079Smjacob 20160079Smjacob#define WPI_TX_RING_COUNT 256 21160079Smjacob#define WPI_TX_RING_LOMARK 192 22160079Smjacob#define WPI_TX_RING_HIMARK 224 23160079Smjacob 24160079Smjacob#ifdef DIAGNOSTIC 25160079Smjacob#define WPI_RX_RING_COUNT_LOG 8 26160079Smjacob#else 27160079Smjacob#define WPI_RX_RING_COUNT_LOG 6 28160079Smjacob#endif 29160079Smjacob 30291543Smav#define WPI_RX_RING_COUNT (1 << WPI_RX_RING_COUNT_LOG) 31291543Smav 32291543Smav#define WPI_NTXQUEUES 8 33160079Smjacob#define WPI_DRV_NTXQUEUES 5 34160079Smjacob#define WPI_CMD_QUEUE_NUM 4 35160079Smjacob 36291543Smav#define WPI_NDMACHNLS 6 37160079Smjacob 38160079Smjacob/* Maximum scatter/gather. */ 39291543Smav#define WPI_MAX_SCATTER 4 40217034Smjacob 41160079Smjacob/* 42160079Smjacob * Rings must be aligned on a 16K boundary. 43160079Smjacob */ 44291543Smav#define WPI_RING_DMA_ALIGN 0x4000 45160079Smjacob 46160079Smjacob/* Maximum Rx buffer size. */ 47160079Smjacob#define WPI_RBUF_SIZE ( 3 * 1024 ) /* XXX 3000 but must be aligned */ 48160079Smjacob 49160079Smjacob/* 50160079Smjacob * Control and status registers. 51160079Smjacob */ 52160079Smjacob#define WPI_HW_IF_CONFIG 0x000 53291543Smav#define WPI_INT 0x008 54291543Smav#define WPI_INT_MASK 0x00c 55291543Smav#define WPI_FH_INT 0x010 56291543Smav#define WPI_GPIO_IN 0x018 57291543Smav#define WPI_RESET 0x020 58160079Smjacob#define WPI_GP_CNTRL 0x024 59160079Smjacob#define WPI_EEPROM 0x02c 60160079Smjacob#define WPI_EEPROM_GP 0x030 61160079Smjacob#define WPI_GIO 0x03c 62160079Smjacob#define WPI_UCODE_GP1 0x054 63217034Smjacob#define WPI_UCODE_GP1_SET 0x058 64217034Smjacob#define WPI_UCODE_GP1_CLR 0x05c 65217034Smjacob#define WPI_UCODE_GP2 0x060 66160079Smjacob#define WPI_GIO_CHICKEN 0x100 67217034Smjacob#define WPI_ANA_PLL 0x20c 68160079Smjacob#define WPI_DBG_HPET_MEM 0x240 69160079Smjacob#define WPI_MEM_RADDR 0x40c 70160079Smjacob#define WPI_MEM_WADDR 0x410 71291543Smav#define WPI_MEM_WDATA 0x418 72291543Smav#define WPI_MEM_RDATA 0x41c 73291543Smav#define WPI_PRPH_WADDR 0x444 74291543Smav#define WPI_PRPH_RADDR 0x448 75291543Smav#define WPI_PRPH_WDATA 0x44c 76217034Smjacob#define WPI_PRPH_RDATA 0x450 77217034Smjacob#define WPI_HBUS_TARG_WRPTR 0x460 78217034Smjacob 79291543Smav/* 80217034Smjacob * Flow-Handler registers. 81217034Smjacob */ 82217034Smjacob#define WPI_FH_CBBC_CTRL(qid) (0x940 + (qid) * 8) 83291543Smav#define WPI_FH_CBBC_BASE(qid) (0x944 + (qid) * 8) 84291543Smav#define WPI_FH_RX_CONFIG 0xc00 85291543Smav#define WPI_FH_RX_BASE 0xc04 86291543Smav#define WPI_FH_RX_WPTR 0xc20 87291543Smav#define WPI_FH_RX_RPTR_ADDR 0xc24 88291543Smav#define WPI_FH_RSSR_TBL 0xcc0 89291543Smav#define WPI_FH_RX_STATUS 0xcc4 90291543Smav#define WPI_FH_TX_CONFIG(qid) (0xd00 + (qid) * 32) 91291543Smav#define WPI_FH_TX_BASE 0xe80 92291543Smav#define WPI_FH_MSG_CONFIG 0xe88 93291543Smav#define WPI_FH_TX_STATUS 0xe90 94291543Smav 95291543Smav 96291543Smav/* 97291543Smav * NIC internal memory offsets. 98291543Smav */ 99291543Smav#define WPI_ALM_SCHED_MODE 0x2e00 100291543Smav#define WPI_ALM_SCHED_ARASTAT 0x2e04 101291543Smav#define WPI_ALM_SCHED_TXFACT 0x2e10 102291543Smav#define WPI_ALM_SCHED_TXF4MF 0x2e14 103291543Smav#define WPI_ALM_SCHED_TXF5MF 0x2e20 104291543Smav#define WPI_ALM_SCHED_SBYPASS_MODE1 0x2e2c 105291543Smav#define WPI_ALM_SCHED_SBYPASS_MODE2 0x2e30 106291543Smav#define WPI_APMG_CLK_CTRL 0x3000 107291543Smav#define WPI_APMG_CLK_EN 0x3004 108291543Smav#define WPI_APMG_CLK_DIS 0x3008 109291543Smav#define WPI_APMG_PS 0x300c 110291543Smav#define WPI_APMG_PCI_STT 0x3010 111291543Smav#define WPI_APMG_RFKILL 0x3014 112291543Smav#define WPI_BSM_WR_CTRL 0x3400 113291543Smav#define WPI_BSM_WR_MEM_SRC 0x3404 114291543Smav#define WPI_BSM_WR_MEM_DST 0x3408 115291543Smav#define WPI_BSM_WR_DWCOUNT 0x340c 116291543Smav#define WPI_BSM_DRAM_TEXT_ADDR 0x3490 117291543Smav#define WPI_BSM_DRAM_TEXT_SIZE 0x3494 118291543Smav#define WPI_BSM_DRAM_DATA_ADDR 0x3498 119291543Smav#define WPI_BSM_DRAM_DATA_SIZE 0x349c 120291543Smav#define WPI_BSM_SRAM_BASE 0x3800 121291543Smav 122291543Smav 123291543Smav/* Possible flags for register WPI_HW_IF_CONFIG. */ 124291543Smav#define WPI_HW_IF_CONFIG_ALM_MB (1 << 8) 125291543Smav#define WPI_HW_IF_CONFIG_ALM_MM (1 << 9) 126291543Smav#define WPI_HW_IF_CONFIG_SKU_MRC (1 << 10) 127291543Smav#define WPI_HW_IF_CONFIG_REV_D (1 << 11) 128291543Smav#define WPI_HW_IF_CONFIG_TYPE_B (1 << 12) 129291543Smav 130291543Smav/* Possible flags for registers WPI_PRPH_RADDR/WPI_PRPH_WADDR. */ 131291543Smav#define WPI_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 132291543Smav 133291543Smav/* Possible values for WPI_BSM_WR_MEM_DST. */ 134291543Smav#define WPI_FW_TEXT_BASE 0x00000000 135291543Smav#define WPI_FW_DATA_BASE 0x00800000 136291543Smav 137291543Smav/* Possible flags for WPI_GPIO_IN. */ 138291543Smav#define WPI_GPIO_IN_VMAIN (1 << 9) 139291543Smav 140291543Smav/* Possible flags for register WPI_RESET. */ 141291543Smav#define WPI_RESET_NEVO (1 << 0) 142291543Smav#define WPI_RESET_SW (1 << 7) 143291543Smav#define WPI_RESET_MASTER_DISABLED (1 << 8) 144291543Smav#define WPI_RESET_STOP_MASTER (1 << 9) 145291543Smav 146291543Smav/* Possible flags for register WPI_GP_CNTRL. */ 147291543Smav#define WPI_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 148291543Smav#define WPI_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 149291543Smav#define WPI_GP_CNTRL_INIT_DONE (1 << 2) 150291543Smav#define WPI_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 151291543Smav#define WPI_GP_CNTRL_SLEEP (1 << 4) 152291543Smav#define WPI_GP_CNTRL_PS_MASK (7 << 24) 153291543Smav#define WPI_GP_CNTRL_MAC_PS (4 << 24) 154291543Smav#define WPI_GP_CNTRL_RFKILL (1 << 27) 155291543Smav 156291543Smav/* Possible flags for register WPI_GIO_CHICKEN. */ 157291543Smav#define WPI_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 158291543Smav#define WPI_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 159291543Smav 160291543Smav/* Possible flags for register WPI_GIO. */ 161291543Smav#define WPI_GIO_L0S_ENA (1 << 1) 162291543Smav 163291543Smav/* Possible flags for register WPI_FH_RX_CONFIG. */ 164291543Smav#define WPI_FH_RX_CONFIG_DMA_ENA (1U << 31) 165291543Smav#define WPI_FH_RX_CONFIG_RDRBD_ENA (1 << 29) 166291543Smav#define WPI_FH_RX_CONFIG_WRSTATUS_ENA (1 << 27) 167291543Smav#define WPI_FH_RX_CONFIG_MAXFRAG (1 << 24) 168291543Smav#define WPI_FH_RX_CONFIG_NRBD(x) ((x) << 20) 169291543Smav#define WPI_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 170291543Smav#define WPI_FH_RX_CONFIG_IRQ_TIMEOUT(x) ((x) << 4) 171291543Smav 172291543Smav/* Possible flags for register WPI_ANA_PLL. */ 173291543Smav#define WPI_ANA_PLL_INIT (1 << 24) 174291543Smav 175291543Smav/* Possible flags for register WPI_UCODE_GP1*. */ 176291543Smav#define WPI_UCODE_GP1_MAC_SLEEP (1 << 0) 177291543Smav#define WPI_UCODE_GP1_RFKILL (1 << 1) 178291543Smav#define WPI_UCODE_GP1_CMD_BLOCKED (1 << 2) 179291543Smav 180291543Smav/* Possible flags for register WPI_FH_RX_STATUS. */ 181291543Smav#define WPI_FH_RX_STATUS_IDLE (1 << 24) 182291543Smav 183291543Smav/* Possible flags for register WPI_BSM_WR_CTRL. */ 184291543Smav#define WPI_BSM_WR_CTRL_START_EN (1 << 30) 185291543Smav#define WPI_BSM_WR_CTRL_START (1U << 31) 186291543Smav 187291543Smav/* Possible flags for register WPI_INT. */ 188291543Smav#define WPI_INT_ALIVE (1 << 0) 189291543Smav#define WPI_INT_WAKEUP (1 << 1) 190291543Smav#define WPI_INT_SW_RX (1 << 3) 191291543Smav#define WPI_INT_SW_ERR (1 << 25) 192291543Smav#define WPI_INT_FH_TX (1 << 27) 193291543Smav#define WPI_INT_HW_ERR (1 << 29) 194291543Smav#define WPI_INT_FH_RX (1U << 31) 195291543Smav 196291543Smav/* Shortcut. */ 197291543Smav#define WPI_INT_MASK_DEF \ 198291543Smav (WPI_INT_SW_ERR | WPI_INT_HW_ERR | WPI_INT_FH_TX | \ 199291543Smav WPI_INT_FH_RX | WPI_INT_ALIVE | WPI_INT_WAKEUP | \ 200291543Smav WPI_INT_SW_RX) 201291543Smav 202291543Smav/* Possible flags for register WPI_FH_INT. */ 203291543Smav#define WPI_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 204291543Smav#define WPI_FH_INT_HI_PRIOR (1 << 30) 205291543Smav/* Shortcuts for the above. */ 206291543Smav#define WPI_FH_INT_RX \ 207291543Smav (WPI_FH_INT_RX_CHNL(0) | \ 208291543Smav WPI_FH_INT_RX_CHNL(1) | \ 209291543Smav WPI_FH_INT_RX_CHNL(2) | \ 210291543Smav WPI_FH_INT_HI_PRIOR) 211291543Smav 212291543Smav/* Possible flags for register WPI_FH_TX_STATUS. */ 213291543Smav#define WPI_FH_TX_STATUS_IDLE(qid) \ 214291543Smav (1 << ((qid) + 24) | 1 << ((qid) + 16)) 215291543Smav 216291543Smav/* Possible flags for register WPI_EEPROM. */ 217291543Smav#define WPI_EEPROM_READ_VALID (1 << 0) 218291543Smav 219291543Smav/* Possible flags for register WPI_EEPROM_GP. */ 220291543Smav#define WPI_EEPROM_VERSION 0x00000007 221291543Smav#define WPI_EEPROM_GP_IF_OWNER 0x00000180 222291543Smav 223291543Smav/* Possible flags for register WPI_APMG_PS. */ 224291543Smav#define WPI_APMG_PS_PWR_SRC_MASK (3 << 24) 225291543Smav 226291543Smav/* Possible flags for registers WPI_APMG_CLK_*. */ 227291543Smav#define WPI_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 228291543Smav#define WPI_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 229291543Smav 230291543Smav/* Possible flags for register WPI_APMG_PCI_STT. */ 231291543Smav#define WPI_APMG_PCI_STT_L1A_DIS (1 << 11) 232291543Smav 233291543Smavstruct wpi_shared { 234291543Smav uint32_t txbase[WPI_NTXQUEUES]; 235291543Smav uint32_t next; 236291543Smav uint32_t reserved[2]; 237291543Smav} __packed; 238291543Smav 239291543Smav#define WPI_MAX_SEG_LEN 65520 240291543Smavstruct wpi_tx_desc { 241291543Smav uint8_t reserved1[3]; 242291543Smav uint8_t nsegs; 243291543Smav#define WPI_PAD32(x) (roundup2(x, 4) - (x)) 244291543Smav 245291543Smav struct { 246291543Smav uint32_t addr; 247291543Smav uint32_t len; 248291543Smav } __packed segs[WPI_MAX_SCATTER]; 249291543Smav uint8_t reserved2[28]; 250291543Smav} __packed; 251291543Smav 252291543Smavstruct wpi_tx_stat { 253291543Smav uint8_t rtsfailcnt; 254291543Smav uint8_t ackfailcnt; 255291543Smav uint8_t btkillcnt; 256291543Smav uint8_t rate; 257291543Smav uint32_t duration; 258291543Smav uint32_t status; 259291543Smav#define WPI_TX_STATUS_SUCCESS 0x01 260291543Smav#define WPI_TX_STATUS_DIRECT_DONE 0x02 261291543Smav#define WPI_TX_STATUS_FAIL 0x80 262291543Smav#define WPI_TX_STATUS_FAIL_SHORT_LIMIT 0x82 263291543Smav#define WPI_TX_STATUS_FAIL_LONG_LIMIT 0x83 264291543Smav#define WPI_TX_STATUS_FAIL_FIFO_UNDERRUN 0x84 265291543Smav#define WPI_TX_STATUS_FAIL_MGMNT_ABORT 0x85 266291543Smav#define WPI_TX_STATUS_FAIL_NEXT_FRAG 0x86 267291543Smav#define WPI_TX_STATUS_FAIL_LIFE_EXPIRE 0x87 268291543Smav#define WPI_TX_STATUS_FAIL_NODE_PS 0x88 269291543Smav#define WPI_TX_STATUS_FAIL_ABORTED 0x89 270291543Smav#define WPI_TX_STATUS_FAIL_BT_RETRY 0x8a 271291543Smav#define WPI_TX_STATUS_FAIL_NODE_INVALID 0x8b 272291543Smav#define WPI_TX_STATUS_FAIL_FRAG_DROPPED 0x8c 273291543Smav#define WPI_TX_STATUS_FAIL_TID_DISABLE 0x8d 274291543Smav#define WPI_TX_STATUS_FAIL_FRAME_FLUSHED 0x8e 275291543Smav#define WPI_TX_STATUS_FAIL_INSUFFICIENT_CF_POLL 0x8f 276291543Smav#define WPI_TX_STATUS_FAIL_TX_LOCKED 0x90 277291543Smav#define WPI_TX_STATUS_FAIL_NO_BEACON_ON_RADAR 0x91 278291543Smav 279291543Smav} __packed; 280291543Smav 281291543Smavstruct wpi_rx_desc { 282291543Smav uint32_t len; 283291543Smav uint8_t type; 284291543Smav#define WPI_UC_READY 1 285291543Smav#define WPI_RX_DONE 27 286291543Smav#define WPI_TX_DONE 28 287291543Smav#define WPI_START_SCAN 130 288291543Smav#define WPI_SCAN_RESULTS 131 289291543Smav#define WPI_STOP_SCAN 132 290291543Smav#define WPI_BEACON_SENT 144 291291543Smav#define WPI_RX_STATISTICS 156 292291543Smav#define WPI_BEACON_STATISTICS 157 293291543Smav#define WPI_STATE_CHANGED 161 294291543Smav#define WPI_BEACON_MISSED 162 295291543Smav 296291543Smav uint8_t flags; 297291543Smav uint8_t idx; 298291543Smav uint8_t qid; 299291543Smav} __packed; 300291543Smav 301291543Smav#define WPI_RX_DESC_QID_MSK 0x07 302291543Smav#define WPI_UNSOLICITED_RX_NOTIF 0x80 303291543Smav 304291543Smavstruct wpi_rx_stat { 305291543Smav uint8_t len; 306291543Smav#define WPI_STAT_MAXLEN 20 307291543Smav 308291543Smav uint8_t id; 309291543Smav uint8_t rssi; /* received signal strength */ 310291543Smav#define WPI_RSSI_OFFSET -95 311291543Smav 312291543Smav uint8_t agc; /* access gain control */ 313291543Smav uint16_t signal; 314291543Smav uint16_t noise; 315291543Smav} __packed; 316291543Smav 317291543Smavstruct wpi_rx_head { 318291543Smav uint16_t chan; 319291543Smav uint16_t flags; 320291543Smav#define WPI_STAT_FLAG_SHPREAMBLE (1 << 2) 321291543Smav 322291543Smav uint8_t reserved; 323291543Smav uint8_t plcp; 324291543Smav uint16_t len; 325291543Smav} __packed; 326291543Smav 327291543Smavstruct wpi_rx_tail { 328291543Smav uint32_t flags; 329291543Smav#define WPI_RX_NO_CRC_ERR (1 << 0) 330291543Smav#define WPI_RX_NO_OVFL_ERR (1 << 1) 331291543Smav/* shortcut for the above */ 332291543Smav#define WPI_RX_NOERROR (WPI_RX_NO_CRC_ERR | WPI_RX_NO_OVFL_ERR) 333291543Smav#define WPI_RX_CIPHER_MASK (7 << 8) 334291543Smav#define WPI_RX_CIPHER_CCMP (2 << 8) 335291543Smav#define WPI_RX_DECRYPT_MASK (3 << 11) 336291543Smav#define WPI_RX_DECRYPT_OK (3 << 11) 337291543Smav 338291543Smav uint64_t tstamp; 339291543Smav uint32_t tbeacon; 340291543Smav} __packed; 341291543Smav 342291543Smavstruct wpi_tx_cmd { 343291543Smav uint8_t code; 344291543Smav#define WPI_CMD_RXON 16 345291543Smav#define WPI_CMD_RXON_ASSOC 17 346291543Smav#define WPI_CMD_EDCA_PARAMS 19 347291543Smav#define WPI_CMD_TIMING 20 348291543Smav#define WPI_CMD_ADD_NODE 24 349291543Smav#define WPI_CMD_DEL_NODE 25 350291543Smav#define WPI_CMD_TX_DATA 28 351291543Smav#define WPI_CMD_MRR_SETUP 71 352291543Smav#define WPI_CMD_SET_LED 72 353291543Smav#define WPI_CMD_SET_POWER_MODE 119 354291543Smav#define WPI_CMD_SCAN 128 355291543Smav#define WPI_CMD_SET_BEACON 145 356291543Smav#define WPI_CMD_TXPOWER 151 357291543Smav#define WPI_CMD_BT_COEX 155 358291543Smav#define WPI_CMD_GET_STATISTICS 156 359291543Smav 360291543Smav uint8_t flags; 361291543Smav uint8_t idx; 362291543Smav uint8_t qid; 363291543Smav uint8_t data[124]; 364291543Smav} __packed; 365291543Smav 366291543Smav/* Structure for command WPI_CMD_RXON. */ 367291543Smavstruct wpi_rxon { 368291543Smav uint8_t myaddr[IEEE80211_ADDR_LEN]; 369291543Smav uint16_t reserved1; 370291543Smav uint8_t bssid[IEEE80211_ADDR_LEN]; 371291543Smav uint16_t reserved2; 372291543Smav uint8_t wlap[IEEE80211_ADDR_LEN]; 373291543Smav uint16_t reserved3; 374291543Smav uint8_t mode; 375291543Smav#define WPI_MODE_HOSTAP 1 376291543Smav#define WPI_MODE_STA 3 377291543Smav#define WPI_MODE_IBSS 4 378291543Smav#define WPI_MODE_MONITOR 6 379291543Smav 380291543Smav uint8_t air; 381291543Smav uint16_t reserved4; 382291543Smav uint8_t ofdm_mask; 383291543Smav uint8_t cck_mask; 384291543Smav uint16_t associd; 385291543Smav uint32_t flags; 386291543Smav#define WPI_RXON_24GHZ (1 << 0) 387291543Smav#define WPI_RXON_CCK (1 << 1) 388291543Smav#define WPI_RXON_AUTO (1 << 2) 389291543Smav#define WPI_RXON_SHSLOT (1 << 4) 390291543Smav#define WPI_RXON_SHPREAMBLE (1 << 5) 391291543Smav#define WPI_RXON_NODIVERSITY (1 << 7) 392291543Smav#define WPI_RXON_ANTENNA_A (1 << 8) 393291543Smav#define WPI_RXON_ANTENNA_B (1 << 9) 394291543Smav#define WPI_RXON_TSF (1 << 15) 395291543Smav#define WPI_RXON_CTS_TO_SELF (1 << 30) 396291543Smav 397291543Smav uint32_t filter; 398291543Smav#define WPI_FILTER_PROMISC (1 << 0) 399291543Smav#define WPI_FILTER_CTL (1 << 1) 400291543Smav#define WPI_FILTER_MULTICAST (1 << 2) 401291543Smav#define WPI_FILTER_NODECRYPT (1 << 3) 402291543Smav#define WPI_FILTER_BSS (1 << 5) 403291543Smav#define WPI_FILTER_BEACON (1 << 6) 404291543Smav#define WPI_FILTER_ASSOC (1 << 7) /* Accept associaton requests. */ 405291543Smav 406291543Smav uint8_t chan; 407291543Smav uint16_t reserved5; 408291543Smav} __packed; 409291543Smav 410291543Smav/* Structure for command WPI_CMD_RXON_ASSOC. */ 411291543Smavstruct wpi_assoc { 412291543Smav uint32_t flags; 413291543Smav uint32_t filter; 414291543Smav uint8_t ofdm_mask; 415291543Smav uint8_t cck_mask; 416291543Smav uint16_t reserved; 417291543Smav} __packed; 418291543Smav 419291543Smav/* Structure for command WPI_CMD_EDCA_PARAMS. */ 420291543Smavstruct wpi_edca_params { 421291543Smav uint32_t flags; 422291543Smav#define WPI_EDCA_UPDATE (1 << 0) 423291543Smav 424291543Smav struct { 425291543Smav uint16_t cwmin; 426291543Smav uint16_t cwmax; 427291543Smav uint8_t aifsn; 428291543Smav uint8_t reserved; 429291543Smav uint16_t txoplimit; 430291543Smav } __packed ac[WME_NUM_AC]; 431291543Smav} __packed; 432291543Smav 433291543Smav/* Structure for command WPI_CMD_TIMING. */ 434291543Smavstruct wpi_cmd_timing { 435291543Smav uint64_t tstamp; 436291543Smav uint16_t bintval; 437291543Smav uint16_t atim; 438291543Smav uint32_t binitval; 439291543Smav uint16_t lintval; 440291543Smav uint16_t reserved; 441291543Smav} __packed; 442291543Smav 443291543Smav/* Structure for command WPI_CMD_ADD_NODE. */ 444291543Smavstruct wpi_node_info { 445291543Smav uint8_t control; 446291543Smav#define WPI_NODE_UPDATE (1 << 0) 447291543Smav 448291543Smav uint8_t reserved1[3]; 449291543Smav uint8_t macaddr[IEEE80211_ADDR_LEN]; 450291543Smav uint16_t reserved2; 451291543Smav uint8_t id; 452291543Smav#define WPI_ID_BSS 0 453291543Smav#define WPI_ID_IBSS_MIN 2 454291543Smav#define WPI_ID_IBSS_MAX 23 455291543Smav#define WPI_ID_BROADCAST 24 456291543Smav#define WPI_ID_UNDEFINED (uint8_t)-1 457291543Smav 458291543Smav uint8_t flags; 459291543Smav#define WPI_FLAG_KEY_SET (1 << 0) 460291543Smav 461291543Smav uint16_t reserved3; 462291543Smav uint16_t kflags; 463291543Smav#define WPI_KFLAG_CCMP (1 << 1) 464291543Smav#define WPI_KFLAG_KID(kid) ((kid) << 8) 465291543Smav#define WPI_KFLAG_MULTICAST (1 << 14) 466291543Smav 467291543Smav uint8_t tsc2; 468291543Smav uint8_t reserved4; 469291543Smav uint16_t ttak[5]; 470291543Smav uint16_t reserved5; 471291543Smav uint8_t key[IEEE80211_KEYBUF_SIZE]; 472291543Smav uint32_t action; 473291543Smav#define WPI_ACTION_SET_RATE (1 << 2) 474291543Smav 475291543Smav uint32_t mask; 476291543Smav uint16_t tid; 477291543Smav uint8_t plcp; 478291543Smav uint8_t antenna; 479291543Smav#define WPI_ANTENNA_A (1 << 6) 480291543Smav#define WPI_ANTENNA_B (1 << 7) 481291543Smav#define WPI_ANTENNA_BOTH (WPI_ANTENNA_A | WPI_ANTENNA_B) 482291543Smav 483291543Smav uint8_t add_imm; 484291543Smav uint8_t del_imm; 485291543Smav uint16_t add_imm_start; 486291543Smav} __packed; 487291543Smav 488291543Smav/* Structure for command WPI_CMD_DEL_NODE. */ 489291543Smavstruct wpi_cmd_del_node { 490291543Smav uint8_t count; 491291543Smav uint8_t reserved1[3]; 492291543Smav uint8_t macaddr[IEEE80211_ADDR_LEN]; 493291543Smav uint16_t reserved2; 494291543Smav} __packed; 495291543Smav 496291543Smav/* Structure for command WPI_CMD_TX_DATA. */ 497291543Smavstruct wpi_cmd_data { 498291543Smav uint16_t len; 499291543Smav uint16_t lnext; 500291543Smav uint32_t flags; 501291543Smav#define WPI_TX_NEED_RTS (1 << 1) 502291543Smav#define WPI_TX_NEED_CTS (1 << 2) 503291543Smav#define WPI_TX_NEED_ACK (1 << 3) 504291543Smav#define WPI_TX_FULL_TXOP (1 << 7) 505291543Smav#define WPI_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 506291543Smav#define WPI_TX_AUTO_SEQ (1 << 13) 507291543Smav#define WPI_TX_MORE_FRAG (1 << 14) 508291543Smav#define WPI_TX_INSERT_TSTAMP (1 << 16) 509291543Smav 510291543Smav uint8_t plcp; 511291543Smav uint8_t id; 512291543Smav uint8_t tid; 513291543Smav uint8_t security; 514291543Smav#define WPI_CIPHER_WEP 1 515291543Smav#define WPI_CIPHER_CCMP 2 516291543Smav#define WPI_CIPHER_TKIP 3 517291543Smav#define WPI_CIPHER_WEP104 9 518291543Smav 519291543Smav uint8_t key[IEEE80211_KEYBUF_SIZE]; 520291543Smav uint8_t tkip[IEEE80211_WEP_MICLEN]; 521291543Smav uint32_t fnext; 522291543Smav uint32_t lifetime; 523291543Smav#define WPI_LIFETIME_INFINITE 0xffffffff 524291543Smav 525291543Smav uint8_t ofdm_mask; 526291543Smav uint8_t cck_mask; 527291543Smav uint8_t rts_ntries; 528291543Smav uint8_t data_ntries; 529291543Smav uint16_t timeout; 530291543Smav uint16_t txop; 531291543Smav} __packed; 532291543Smav 533291543Smav/* Structure for command WPI_CMD_SET_BEACON. */ 534291543Smavstruct wpi_cmd_beacon { 535291543Smav uint16_t len; 536291543Smav uint16_t reserved1; 537291543Smav uint32_t flags; /* same as wpi_cmd_data */ 538291543Smav uint8_t plcp; 539291543Smav uint8_t id; 540291543Smav uint8_t reserved2[30]; 541291543Smav uint32_t lifetime; 542291543Smav uint8_t ofdm_mask; 543291543Smav uint8_t cck_mask; 544291543Smav uint16_t reserved3[3]; 545291543Smav uint16_t tim; 546291543Smav uint8_t timsz; 547291543Smav uint8_t reserved4; 548291543Smav} __packed; 549291543Smav 550291543Smav/* Structure for notification WPI_BEACON_MISSED. */ 551291543Smavstruct wpi_beacon_missed { 552291543Smav uint32_t consecutive; 553291543Smav uint32_t total; 554291543Smav uint32_t expected; 555291543Smav uint32_t received; 556291543Smav} __packed; 557291543Smav 558291543Smav 559291543Smav/* Structure for command WPI_CMD_MRR_SETUP. */ 560291543Smav#define WPI_RIDX_MAX 11 561291543Smavstruct wpi_mrr_setup { 562291543Smav uint32_t which; 563291543Smav#define WPI_MRR_CTL 0 564291543Smav#define WPI_MRR_DATA 1 565291543Smav 566291543Smav struct { 567291543Smav uint8_t plcp; 568291543Smav uint8_t flags; 569291543Smav uint8_t ntries; 570291543Smav#define WPI_NTRIES_DEFAULT 2 571291543Smav 572291543Smav uint8_t next; 573291543Smav } __packed rates[WPI_RIDX_MAX + 1]; 574291543Smav} __packed; 575291543Smav 576291543Smav/* Structure for command WPI_CMD_SET_LED. */ 577291543Smavstruct wpi_cmd_led { 578291543Smav uint32_t unit; /* multiplier (in usecs) */ 579291543Smav uint8_t which; 580291543Smav#define WPI_LED_ACTIVITY 1 581291543Smav#define WPI_LED_LINK 2 582291543Smav 583291543Smav uint8_t off; 584291543Smav uint8_t on; 585291543Smav uint8_t reserved; 586291543Smav} __packed; 587291543Smav 588291543Smav/* Structure for command WPI_CMD_SET_POWER_MODE. */ 589291543Smavstruct wpi_pmgt_cmd { 590291543Smav uint16_t flags; 591291543Smav#define WPI_PS_ALLOW_SLEEP (1 << 0) 592291543Smav#define WPI_PS_NOTIFY (1 << 1) 593291543Smav#define WPI_PS_SLEEP_OVER_DTIM (1 << 2) 594291543Smav#define WPI_PS_PCI_PMGT (1 << 3) 595291543Smav 596291543Smav uint8_t reserved[2]; 597291543Smav uint32_t rxtimeout; 598291543Smav uint32_t txtimeout; 599291543Smav uint32_t intval[5]; 600291543Smav} __packed; 601291543Smav 602291543Smav/* Structures for command WPI_CMD_SCAN. */ 603291543Smav#define WPI_SCAN_MAX_ESSIDS 4 604291543Smavstruct wpi_scan_essid { 605291543Smav uint8_t id; 606291543Smav uint8_t len; 607291543Smav uint8_t data[IEEE80211_NWID_LEN]; 608291543Smav} __packed; 609291543Smav 610291543Smavstruct wpi_scan_hdr { 611291543Smav uint16_t len; 612291543Smav uint8_t reserved1; 613291543Smav uint8_t nchan; 614291543Smav uint16_t quiet_time; /* timeout in milliseconds */ 615291543Smav#define WPI_QUIET_TIME_DEFAULT 10 616291543Smav 617291543Smav uint16_t quiet_threshold; /* min # of packets */ 618291543Smav uint16_t crc_threshold; 619291543Smav uint16_t reserved2; 620291543Smav uint32_t max_svc; /* background scans */ 621291543Smav uint32_t pause_svc; /* background scans */ 622291543Smav#define WPI_PAUSE_MAX_TIME ((1 << 20) - 1) 623291543Smav#define WPI_PAUSE_SCAN(nbeacons, time) ((nbeacons << 24) | time) 624291543Smav 625291543Smav uint32_t flags; 626291543Smav uint32_t filter; 627291543Smav 628291543Smav /* Followed by a struct wpi_cmd_data. */ 629291543Smav /* Followed by an array of 4 structs wpi_scan_essid. */ 630291543Smav /* Followed by probe request body. */ 631291543Smav /* Followed by an array of ``nchan'' structs wpi_scan_chan. */ 632291543Smav} __packed; 633291543Smav 634291543Smavstruct wpi_scan_chan { 635291543Smav uint8_t flags; 636291543Smav#define WPI_CHAN_ACTIVE (1 << 0) 637291543Smav#define WPI_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 638291543Smav 639291543Smav uint8_t chan; 640291543Smav uint8_t rf_gain; 641291543Smav uint8_t dsp_gain; 642291543Smav uint16_t active; /* msecs */ 643291543Smav uint16_t passive; /* msecs */ 644291543Smav} __packed; 645291543Smav 646291543Smav#define WPI_SCAN_CRC_TH_DEFAULT htole16(1) 647291543Smav#define WPI_SCAN_CRC_TH_NEVER htole16(0xffff) 648291543Smav 649291543Smav/* Maximum size of a scan command. */ 650291543Smav#define WPI_SCAN_MAXSZ (MCLBYTES - 4) 651291543Smav 652291543Smav#define WPI_ACTIVE_DWELL_TIME_2GHZ (30) /* all times in msec */ 653291543Smav#define WPI_ACTIVE_DWELL_TIME_5GHZ (20) 654291543Smav#define WPI_ACTIVE_DWELL_FACTOR_2GHZ ( 3) 655291543Smav#define WPI_ACTIVE_DWELL_FACTOR_5GHZ ( 2) 656291543Smav 657217034Smjacob#define WPI_PASSIVE_DWELL_TIME_2GHZ ( 20) 658291543Smav#define WPI_PASSIVE_DWELL_TIME_5GHZ ( 10) 659217034Smjacob#define WPI_PASSIVE_DWELL_BASE (100) 660291543Smav#define WPI_CHANNEL_TUNE_TIME ( 6) 661217034Smjacob 662217034Smjacob/* Structure for command WPI_CMD_TXPOWER. */ 663217034Smjacobstruct wpi_cmd_txpower { 664291543Smav uint8_t band; 665291543Smav#define WPI_BAND_5GHZ 0 666291543Smav#define WPI_BAND_2GHZ 1 667291543Smav 668291543Smav uint8_t reserved; 669291543Smav uint16_t chan; 670217034Smjacob 671291543Smav struct { 672291543Smav uint8_t plcp; 673217034Smjacob uint8_t rf_gain; 674291543Smav uint8_t dsp_gain; 675217034Smjacob uint8_t reserved; 676291543Smav } __packed rates[WPI_RIDX_MAX + 1]; 677217034Smjacob 678291543Smav} __packed; 679291543Smav 680217034Smjacob/* Structure for command WPI_CMD_BT_COEX. */ 681217034Smjacobstruct wpi_bluetooth { 682291543Smav uint8_t flags; 683217034Smjacob#define WPI_BT_COEX_DISABLE 0 684217034Smjacob#define WPI_BT_COEX_MODE_2WIRE 1 685217034Smjacob#define WPI_BT_COEX_MODE_3WIRE 2 686217034Smjacob#define WPI_BT_COEX_MODE_4WIRE 3 687217034Smjacob 688291543Smav uint8_t lead_time; 689291543Smav#define WPI_BT_LEAD_TIME_DEF 30 690217034Smjacob 691291543Smav uint8_t max_kill; 692291543Smav#define WPI_BT_MAX_KILL_DEF 5 693217034Smjacob 694217034Smjacob uint8_t reserved; 695217034Smjacob uint32_t kill_ack; 696217034Smjacob uint32_t kill_cts; 697291543Smav} __packed; 698217034Smjacob 699217034Smjacob/* Structure for WPI_UC_READY notification. */ 700217034Smjacobstruct wpi_ucode_info { 701291543Smav uint8_t minor; 702217034Smjacob uint8_t major; 703217034Smjacob uint16_t reserved1; 704291543Smav uint8_t revision[8]; 705291543Smav uint8_t type; 706291543Smav uint8_t subtype; 707291543Smav uint16_t reserved2; 708291543Smav uint32_t logptr; 709217034Smjacob uint32_t errptr; 710291543Smav uint32_t tstamp; 711217034Smjacob uint32_t valid; 712217034Smjacob} __packed; 713217034Smjacob 714217034Smjacob/* Structure for WPI_START_SCAN notification. */ 715291543Smavstruct wpi_start_scan { 716217034Smjacob uint64_t tstamp; 717217034Smjacob uint32_t tbeacon; 718217034Smjacob uint8_t chan; 719291543Smav uint8_t band; 720217034Smjacob uint16_t reserved; 721291543Smav uint32_t status; 722291543Smav} __packed; 723291543Smav 724291543Smav/* Structure for WPI_STOP_SCAN notification. */ 725291543Smavstruct wpi_stop_scan { 726291543Smav uint8_t nchan; 727291543Smav uint8_t status; 728291543Smav uint8_t reserved; 729291543Smav uint8_t chan; 730291543Smav uint64_t tsf; 731291543Smav} __packed; 732291543Smav 733291543Smav/* Structures for WPI_{RX,BEACON}_STATISTICS notification. */ 734291543Smavstruct wpi_rx_phy_stats { 735291543Smav uint32_t ina; 736291543Smav uint32_t fina; 737291543Smav uint32_t bad_plcp; 738291543Smav uint32_t bad_crc32; 739291543Smav uint32_t overrun; 740291543Smav uint32_t eoverrun; 741217034Smjacob uint32_t good_crc32; 742217034Smjacob uint32_t fa; 743217034Smjacob uint32_t bad_fina_sync; 744217034Smjacob uint32_t sfd_timeout; 745217034Smjacob uint32_t fina_timeout; 746291543Smav uint32_t no_rts_ack; 747291543Smav uint32_t rxe_limit; 748217034Smjacob uint32_t ack; 749291543Smav uint32_t cts; 750217034Smjacob} __packed; 751291543Smav 752217034Smjacobstruct wpi_rx_general_stats { 753217034Smjacob uint32_t bad_cts; 754291543Smav uint32_t bad_ack; 755291543Smav uint32_t not_bss; 756291543Smav uint32_t filtered; 757217034Smjacob uint32_t bad_chan; 758291543Smav} __packed; 759217034Smjacob 760217034Smjacobstruct wpi_rx_stats { 761217034Smjacob struct wpi_rx_phy_stats ofdm; 762291543Smav struct wpi_rx_phy_stats cck; 763291543Smav struct wpi_rx_general_stats general; 764291543Smav} __packed; 765217034Smjacob 766217034Smjacobstruct wpi_tx_stats { 767291543Smav uint32_t preamble; 768217034Smjacob uint32_t rx_detected; 769217034Smjacob uint32_t bt_defer; 770217034Smjacob uint32_t bt_kill; 771291543Smav uint32_t short_len; 772217034Smjacob uint32_t cts_timeout; 773291543Smav uint32_t ack_timeout; 774291543Smav uint32_t exp_ack; 775291543Smav uint32_t ack; 776217034Smjacob} __packed; 777291543Smav 778291543Smavstruct wpi_general_stats { 779217034Smjacob uint32_t temp; 780291543Smav uint32_t burst_check; 781291543Smav uint32_t burst; 782217034Smjacob uint32_t reserved[4]; 783291543Smav uint32_t sleep; 784217034Smjacob uint32_t slot_out; 785217034Smjacob uint32_t slot_idle; 786291543Smav uint32_t ttl_tstamp; 787291543Smav uint32_t tx_ant_a; 788291543Smav uint32_t tx_ant_b; 789291543Smav uint32_t exec; 790291543Smav uint32_t probe; 791291543Smav} __packed; 792291543Smav 793291543Smavstruct wpi_stats { 794217034Smjacob uint32_t flags; 795291543Smav struct wpi_rx_stats rx; 796291543Smav struct wpi_tx_stats tx; 797291543Smav struct wpi_general_stats general; 798291543Smav} __packed; 799291543Smav 800291543Smav/* Possible flags for command WPI_CMD_GET_STATISTICS. */ 801291543Smav#define WPI_STATISTICS_BEACON_DISABLE (1 << 1) 802291543Smav 803291543Smav 804291543Smav/* Firmware error dump entry. */ 805291543Smavstruct wpi_fw_dump { 806291543Smav uint32_t desc; 807291543Smav uint32_t time; 808291543Smav uint32_t blink[2]; 809291543Smav uint32_t ilink[2]; 810291543Smav uint32_t data; 811291543Smav} __packed; 812217034Smjacob 813217034Smjacob/* Firmware image file header. */ 814291543Smavstruct wpi_firmware_hdr { 815291543Smav 816291543Smav#define WPI_FW_MINVERSION 2144 817291543Smav#define WPI_FW_NAME "wpifw" 818291543Smav 819217034Smjacob uint16_t driver; 820291543Smav uint8_t minor; 821291543Smav uint8_t major; 822291543Smav uint32_t rtextsz; 823291543Smav uint32_t rdatasz; 824291543Smav uint32_t itextsz; 825291543Smav uint32_t idatasz; 826291543Smav uint32_t btextsz; 827291543Smav} __packed; 828291543Smav 829291543Smav#define WPI_FW_TEXT_MAXSZ ( 80 * 1024 ) 830291543Smav#define WPI_FW_DATA_MAXSZ ( 32 * 1024 ) 831291543Smav#define WPI_FW_BOOT_TEXT_MAXSZ 1024 832291543Smav 833291543Smav#define WPI_FW_UPDATED (1U << 31 ) 834291543Smav 835291543Smav/* 836291543Smav * Offsets into EEPROM. 837291543Smav */ 838291543Smav#define WPI_EEPROM_MAC 0x015 839291543Smav#define WPI_EEPROM_REVISION 0x035 840291543Smav#define WPI_EEPROM_SKU_CAP 0x045 841291543Smav#define WPI_EEPROM_TYPE 0x04a 842291543Smav#define WPI_EEPROM_DOMAIN 0x060 843217034Smjacob#define WPI_EEPROM_BAND1 0x063 844291543Smav#define WPI_EEPROM_BAND2 0x072 845217034Smjacob#define WPI_EEPROM_BAND3 0x080 846291543Smav#define WPI_EEPROM_BAND4 0x08d 847291543Smav#define WPI_EEPROM_BAND5 0x099 848217034Smjacob#define WPI_EEPROM_POWER_GRP 0x100 849217034Smjacob 850217034Smjacobstruct wpi_eeprom_chan { 851217034Smjacob uint8_t flags; 852217034Smjacob#define WPI_EEPROM_CHAN_VALID (1 << 0) 853217034Smjacob#define WPI_EEPROM_CHAN_IBSS (1 << 1) 854217034Smjacob#define WPI_EEPROM_CHAN_ACTIVE (1 << 3) 855217034Smjacob#define WPI_EEPROM_CHAN_RADAR (1 << 4) 856291543Smav 857217034Smjacob int8_t maxpwr; 858217034Smjacob} __packed; 859217034Smjacob 860217034Smjacobstruct wpi_eeprom_sample { 861291543Smav uint8_t index; 862291543Smav int8_t power; 863291543Smav uint16_t volt; 864291543Smav} __packed; 865291543Smav 866291543Smav#define WPI_POWER_GROUPS_COUNT 5 867291543Smavstruct wpi_eeprom_group { 868291543Smav struct wpi_eeprom_sample samples[5]; 869291543Smav int32_t coef[5]; 870291543Smav int32_t corr[5]; 871291543Smav int8_t maxpwr; 872291543Smav uint8_t chan; 873291543Smav int16_t temp; 874217034Smjacob} __packed; 875291543Smav 876217034Smjacob#define WPI_CHAN_BANDS_COUNT 5 877217034Smjacob#define WPI_MAX_CHAN_PER_BAND 14 878217034Smjacobstatic const struct wpi_chan_band { 879217034Smjacob uint32_t addr; /* offset in EEPROM */ 880217034Smjacob uint8_t nchan; 881217034Smjacob uint8_t chan[WPI_MAX_CHAN_PER_BAND]; 882217034Smjacob} wpi_bands[] = { 883217034Smjacob /* 20MHz channels, 2GHz band. */ 884217034Smjacob { WPI_EEPROM_BAND1, 14, 885217034Smjacob { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 886217034Smjacob /* 20MHz channels, 5GHz band. */ 887217034Smjacob { WPI_EEPROM_BAND2, 13, 888217034Smjacob { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 889217034Smjacob { WPI_EEPROM_BAND3, 12, 890217034Smjacob { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 891217034Smjacob { WPI_EEPROM_BAND4, 11, 892217034Smjacob { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 893217034Smjacob { WPI_EEPROM_BAND5, 6, 894291543Smav { 145, 149, 153, 157, 161, 165 } } 895217034Smjacob}; 896217034Smjacob 897217034Smjacob/* HW rate indices. */ 898291543Smav#define WPI_RIDX_OFDM6 0 899217034Smjacob#define WPI_RIDX_OFDM36 5 900291543Smav#define WPI_RIDX_OFDM48 6 901291543Smav#define WPI_RIDX_OFDM54 7 902217034Smjacob#define WPI_RIDX_CCK1 8 903291543Smav#define WPI_RIDX_CCK2 9 904291543Smav#define WPI_RIDX_CCK11 11 905217034Smjacob 906217034Smjacobstatic const uint8_t wpi_ridx_to_plcp[] = { 907217034Smjacob /* OFDM: IEEE Std 802.11a-1999, pp. 14 Table 80 */ 908217034Smjacob /* R1-R4 (ral/ural is R4-R1) */ 909217034Smjacob 0xd, 0xf, 0x5, 0x7, 0x9, 0xb, 0x1, 0x3, 910291543Smav /* CCK: device-dependent */ 911217034Smjacob 10, 20, 55, 110 912217034Smjacob}; 913217034Smjacob 914217034Smjacob#define WPI_MAX_PWR_INDEX 77 915217034Smjacob 916217034Smjacob/* 917217034Smjacob * RF Tx gain values from highest to lowest power (values obtained from 918217034Smjacob * the reference driver.) 919217034Smjacob */ 920217034Smjacobstatic const uint8_t wpi_rf_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 921217034Smjacob 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xbb, 0xbb, 0xbb, 922291543Smav 0xbb, 0xf3, 0xf3, 0xf3, 0xf3, 0xf3, 0xd3, 0xd3, 0xb3, 0xb3, 0xb3, 923291543Smav 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x73, 0xeb, 0xeb, 0xeb, 924217034Smjacob 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xab, 0xab, 0xab, 0x8b, 925291543Smav 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xc3, 0xc3, 0xc3, 0xc3, 0xa3, 926291543Smav 0xa3, 0xa3, 0xa3, 0x83, 0x83, 0x83, 0x83, 0x63, 0x63, 0x63, 0x63, 927291543Smav 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 0x03, 0x03, 0x03, 928291543Smav 0x03 929291543Smav}; 930291543Smav 931217034Smjacobstatic const uint8_t wpi_rf_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 932291543Smav 0xfb, 0xfb, 0xfb, 0xdb, 0xdb, 0xbb, 0xbb, 0x9b, 0x9b, 0x7b, 0x7b, 933291543Smav 0x7b, 0x7b, 0x5b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x1b, 0x1b, 934291543Smav 0x1b, 0x73, 0x73, 0x73, 0x53, 0x53, 0x53, 0x53, 0x53, 0x33, 0x33, 935291543Smav 0x33, 0x33, 0x13, 0x13, 0x13, 0x13, 0x13, 0xab, 0xab, 0xab, 0x8b, 936217034Smjacob 0x8b, 0x8b, 0x8b, 0x6b, 0x6b, 0x6b, 0x6b, 0x4b, 0x4b, 0x4b, 0x4b, 937291543Smav 0x2b, 0x2b, 0x2b, 0x2b, 0x0b, 0x0b, 0x0b, 0x0b, 0x83, 0x83, 0x63, 938291543Smav 0x63, 0x63, 0x63, 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 939291543Smav 0x03 940291543Smav}; 941291543Smav 942291543Smav/* 943291543Smav * DSP pre-DAC gain values from highest to lowest power (values obtained 944291543Smav * from the reference driver.) 945291543Smav */ 946291543Smavstatic const uint8_t wpi_dsp_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 947291543Smav 0x7f, 0x7f, 0x7f, 0x7f, 0x7d, 0x6e, 0x69, 0x62, 0x7d, 0x73, 0x6c, 948217034Smjacob 0x63, 0x77, 0x6f, 0x69, 0x61, 0x5c, 0x6a, 0x64, 0x78, 0x71, 0x6b, 949291543Smav 0x7d, 0x77, 0x70, 0x6a, 0x65, 0x61, 0x5b, 0x6b, 0x79, 0x73, 0x6d, 950217034Smjacob 0x7f, 0x79, 0x73, 0x6c, 0x66, 0x60, 0x5c, 0x6e, 0x68, 0x62, 0x74, 951291543Smav 0x7d, 0x77, 0x71, 0x6b, 0x65, 0x60, 0x71, 0x6a, 0x66, 0x5f, 0x71, 952217034Smjacob 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 953291543Smav 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 954291543Smav 0x5f 955217034Smjacob}; 956291543Smav 957217034Smjacobstatic const uint8_t wpi_dsp_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 958291543Smav 0x7f, 0x78, 0x72, 0x77, 0x65, 0x71, 0x66, 0x72, 0x67, 0x75, 0x6b, 959291543Smav 0x63, 0x5c, 0x6c, 0x7d, 0x76, 0x6d, 0x66, 0x60, 0x5a, 0x68, 0x62, 960291543Smav 0x5c, 0x76, 0x6f, 0x68, 0x7e, 0x79, 0x71, 0x69, 0x63, 0x76, 0x6f, 961291543Smav 0x68, 0x62, 0x74, 0x6d, 0x66, 0x62, 0x5d, 0x71, 0x6b, 0x63, 0x78, 962291543Smav 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 963291543Smav 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x6b, 0x63, 0x78, 964217034Smjacob 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 965291543Smav 0x78 966291543Smav}; 967291543Smav 968291543Smav/* 969217034Smjacob * Power saving settings (values obtained from the reference driver.) 970291543Smav */ 971291543Smav#define WPI_NDTIMRANGES 2 972291543Smav#define WPI_NPOWERLEVELS 6 973291543Smavstatic const struct wpi_pmgt { 974217034Smjacob uint32_t rxtimeout; 975217034Smjacob uint32_t txtimeout; 976217034Smjacob uint32_t intval[5]; 977291543Smav int skip_dtim; 978291543Smav} wpi_pmgt[WPI_NDTIMRANGES][WPI_NPOWERLEVELS] = { 979291543Smav /* DTIM <= 10 */ 980291543Smav { 981291543Smav { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 982291543Smav { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 983291543Smav { 200, 300, { 2, 4, 6, 7, 7 }, 0 }, /* PS level 2 */ 984291543Smav { 50, 100, { 2, 6, 9, 9, 10 }, 0 }, /* PS level 3 */ 985291543Smav { 50, 25, { 2, 7, 9, 9, 10 }, 1 }, /* PS level 4 */ 986291543Smav { 25, 25, { 4, 7, 10, 10, 10 }, 1 } /* PS level 5 */ 987291543Smav }, 988291543Smav /* DTIM >= 11 */ 989291543Smav { 990291543Smav { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 991291543Smav { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 992291543Smav { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 993291543Smav { 50, 100, { 2, 6, 9, 9, -1 }, 0 }, /* PS level 3 */ 994291543Smav { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 995291543Smav { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 996291543Smav } 997291543Smav}; 998291543Smav 999291543Smav/* Firmware errors. */ 1000291543Smavstatic const char * const wpi_fw_errmsg[] = { 1001291543Smav "OK", 1002291543Smav "FAIL", 1003291543Smav "BAD_PARAM", 1004291543Smav "BAD_CHECKSUM", 1005291543Smav "NMI_INTERRUPT", 1006291543Smav "SYSASSERT", 1007291543Smav "FATAL_ERROR" 1008291543Smav}; 1009291543Smav 1010291543Smav#define WPI_READ(sc, reg) \ 1011291543Smav bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 1012291543Smav 1013291543Smav#define WPI_WRITE(sc, reg, val) \ 1014291543Smav bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1015291543Smav 1016291543Smav#define WPI_WRITE_REGION_4(sc, offset, datap, count) \ 1017291543Smav bus_space_write_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 1018291543Smav (datap), (count)) 1019291543Smav 1020291543Smav#define WPI_SETBITS(sc, reg, mask) \ 1021291543Smav WPI_WRITE(sc, reg, WPI_READ(sc, reg) | (mask)) 1022291543Smav 1023291543Smav#define WPI_CLRBITS(sc, reg, mask) \ 1024291543Smav WPI_WRITE(sc, reg, WPI_READ(sc, reg) & ~(mask)) 1025291543Smav 1026291543Smav#define WPI_BARRIER_WRITE(sc) \ 1027291543Smav bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1028291543Smav BUS_SPACE_BARRIER_WRITE) 1029291543Smav 1030291543Smav#define WPI_BARRIER_READ_WRITE(sc) \ 1031291543Smav bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1032291543Smav BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 1033291543Smav