if_wpireg.h revision 282378
1/* $FreeBSD: head/sys/dev/wpi/if_wpireg.h 282378 2015-05-03 22:49:47Z adrian $ */ 2 3/*- 4 * Copyright (c) 2006,2007 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#define WPI_TX_RING_COUNT 256 21#define WPI_TX_RING_LOMARK 192 22#define WPI_TX_RING_HIMARK 224 23 24#ifdef DIAGNOSTIC 25#define WPI_RX_RING_COUNT_LOG 8 26#else 27#define WPI_RX_RING_COUNT_LOG 6 28#endif 29 30#define WPI_RX_RING_COUNT (1 << WPI_RX_RING_COUNT_LOG) 31 32#define WPI_NTXQUEUES 8 33#define WPI_DRV_NTXQUEUES 5 34#define WPI_CMD_QUEUE_NUM 4 35 36#define WPI_NDMACHNLS 6 37 38/* Maximum scatter/gather. */ 39#define WPI_MAX_SCATTER 4 40 41/* 42 * Rings must be aligned on a 16K boundary. 43 */ 44#define WPI_RING_DMA_ALIGN 0x4000 45 46/* Maximum Rx buffer size. */ 47#define WPI_RBUF_SIZE ( 3 * 1024 ) /* XXX 3000 but must be aligned */ 48 49/* 50 * Control and status registers. 51 */ 52#define WPI_HW_IF_CONFIG 0x000 53#define WPI_INT 0x008 54#define WPI_INT_MASK 0x00c 55#define WPI_FH_INT 0x010 56#define WPI_GPIO_IN 0x018 57#define WPI_RESET 0x020 58#define WPI_GP_CNTRL 0x024 59#define WPI_EEPROM 0x02c 60#define WPI_EEPROM_GP 0x030 61#define WPI_GIO 0x03c 62#define WPI_UCODE_GP1 0x054 63#define WPI_UCODE_GP1_SET 0x058 64#define WPI_UCODE_GP1_CLR 0x05c 65#define WPI_UCODE_GP2 0x060 66#define WPI_GIO_CHICKEN 0x100 67#define WPI_ANA_PLL 0x20c 68#define WPI_DBG_HPET_MEM 0x240 69#define WPI_MEM_RADDR 0x40c 70#define WPI_MEM_WADDR 0x410 71#define WPI_MEM_WDATA 0x418 72#define WPI_MEM_RDATA 0x41c 73#define WPI_PRPH_WADDR 0x444 74#define WPI_PRPH_RADDR 0x448 75#define WPI_PRPH_WDATA 0x44c 76#define WPI_PRPH_RDATA 0x450 77#define WPI_HBUS_TARG_WRPTR 0x460 78 79/* 80 * Flow-Handler registers. 81 */ 82#define WPI_FH_CBBC_CTRL(qid) (0x940 + (qid) * 8) 83#define WPI_FH_CBBC_BASE(qid) (0x944 + (qid) * 8) 84#define WPI_FH_RX_CONFIG 0xc00 85#define WPI_FH_RX_BASE 0xc04 86#define WPI_FH_RX_WPTR 0xc20 87#define WPI_FH_RX_RPTR_ADDR 0xc24 88#define WPI_FH_RSSR_TBL 0xcc0 89#define WPI_FH_RX_STATUS 0xcc4 90#define WPI_FH_TX_CONFIG(qid) (0xd00 + (qid) * 32) 91#define WPI_FH_TX_BASE 0xe80 92#define WPI_FH_MSG_CONFIG 0xe88 93#define WPI_FH_TX_STATUS 0xe90 94 95 96/* 97 * NIC internal memory offsets. 98 */ 99#define WPI_ALM_SCHED_MODE 0x2e00 100#define WPI_ALM_SCHED_ARASTAT 0x2e04 101#define WPI_ALM_SCHED_TXFACT 0x2e10 102#define WPI_ALM_SCHED_TXF4MF 0x2e14 103#define WPI_ALM_SCHED_TXF5MF 0x2e20 104#define WPI_ALM_SCHED_SBYPASS_MODE1 0x2e2c 105#define WPI_ALM_SCHED_SBYPASS_MODE2 0x2e30 106#define WPI_APMG_CLK_CTRL 0x3000 107#define WPI_APMG_CLK_EN 0x3004 108#define WPI_APMG_CLK_DIS 0x3008 109#define WPI_APMG_PS 0x300c 110#define WPI_APMG_PCI_STT 0x3010 111#define WPI_APMG_RFKILL 0x3014 112#define WPI_BSM_WR_CTRL 0x3400 113#define WPI_BSM_WR_MEM_SRC 0x3404 114#define WPI_BSM_WR_MEM_DST 0x3408 115#define WPI_BSM_WR_DWCOUNT 0x340c 116#define WPI_BSM_DRAM_TEXT_ADDR 0x3490 117#define WPI_BSM_DRAM_TEXT_SIZE 0x3494 118#define WPI_BSM_DRAM_DATA_ADDR 0x3498 119#define WPI_BSM_DRAM_DATA_SIZE 0x349c 120#define WPI_BSM_SRAM_BASE 0x3800 121 122 123/* Possible flags for register WPI_HW_IF_CONFIG. */ 124#define WPI_HW_IF_CONFIG_ALM_MB (1 << 8) 125#define WPI_HW_IF_CONFIG_ALM_MM (1 << 9) 126#define WPI_HW_IF_CONFIG_SKU_MRC (1 << 10) 127#define WPI_HW_IF_CONFIG_REV_D (1 << 11) 128#define WPI_HW_IF_CONFIG_TYPE_B (1 << 12) 129 130/* Possible flags for registers WPI_PRPH_RADDR/WPI_PRPH_WADDR. */ 131#define WPI_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 132 133/* Possible values for WPI_BSM_WR_MEM_DST. */ 134#define WPI_FW_TEXT_BASE 0x00000000 135#define WPI_FW_DATA_BASE 0x00800000 136 137/* Possible flags for WPI_GPIO_IN. */ 138#define WPI_GPIO_IN_VMAIN (1 << 9) 139 140/* Possible flags for register WPI_RESET. */ 141#define WPI_RESET_NEVO (1 << 0) 142#define WPI_RESET_SW (1 << 7) 143#define WPI_RESET_MASTER_DISABLED (1 << 8) 144#define WPI_RESET_STOP_MASTER (1 << 9) 145 146/* Possible flags for register WPI_GP_CNTRL. */ 147#define WPI_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 148#define WPI_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 149#define WPI_GP_CNTRL_INIT_DONE (1 << 2) 150#define WPI_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 151#define WPI_GP_CNTRL_SLEEP (1 << 4) 152#define WPI_GP_CNTRL_PS_MASK (7 << 24) 153#define WPI_GP_CNTRL_MAC_PS (4 << 24) 154#define WPI_GP_CNTRL_RFKILL (1 << 27) 155 156/* Possible flags for register WPI_GIO_CHICKEN. */ 157#define WPI_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 158#define WPI_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 159 160/* Possible flags for register WPI_GIO. */ 161#define WPI_GIO_L0S_ENA (1 << 1) 162 163/* Possible flags for register WPI_FH_RX_CONFIG. */ 164#define WPI_FH_RX_CONFIG_DMA_ENA (1U << 31) 165#define WPI_FH_RX_CONFIG_RDRBD_ENA (1 << 29) 166#define WPI_FH_RX_CONFIG_WRSTATUS_ENA (1 << 27) 167#define WPI_FH_RX_CONFIG_MAXFRAG (1 << 24) 168#define WPI_FH_RX_CONFIG_NRBD(x) ((x) << 20) 169#define WPI_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 170#define WPI_FH_RX_CONFIG_IRQ_TIMEOUT(x) ((x) << 4) 171 172/* Possible flags for register WPI_ANA_PLL. */ 173#define WPI_ANA_PLL_INIT (1 << 24) 174 175/* Possible flags for register WPI_UCODE_GP1*. */ 176#define WPI_UCODE_GP1_MAC_SLEEP (1 << 0) 177#define WPI_UCODE_GP1_RFKILL (1 << 1) 178#define WPI_UCODE_GP1_CMD_BLOCKED (1 << 2) 179 180/* Possible flags for register WPI_FH_RX_STATUS. */ 181#define WPI_FH_RX_STATUS_IDLE (1 << 24) 182 183/* Possible flags for register WPI_BSM_WR_CTRL. */ 184#define WPI_BSM_WR_CTRL_START_EN (1 << 30) 185#define WPI_BSM_WR_CTRL_START (1U << 31) 186 187/* Possible flags for register WPI_INT. */ 188#define WPI_INT_ALIVE (1 << 0) 189#define WPI_INT_WAKEUP (1 << 1) 190#define WPI_INT_SW_RX (1 << 3) 191#define WPI_INT_SW_ERR (1 << 25) 192#define WPI_INT_FH_TX (1 << 27) 193#define WPI_INT_HW_ERR (1 << 29) 194#define WPI_INT_FH_RX (1U << 31) 195 196/* Shortcut. */ 197#define WPI_INT_MASK_DEF \ 198 (WPI_INT_SW_ERR | WPI_INT_HW_ERR | WPI_INT_FH_TX | \ 199 WPI_INT_FH_RX | WPI_INT_ALIVE | WPI_INT_WAKEUP | \ 200 WPI_INT_SW_RX) 201 202/* Possible flags for register WPI_FH_INT. */ 203#define WPI_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 204#define WPI_FH_INT_HI_PRIOR (1 << 30) 205/* Shortcuts for the above. */ 206#define WPI_FH_INT_RX \ 207 (WPI_FH_INT_RX_CHNL(0) | \ 208 WPI_FH_INT_RX_CHNL(1) | \ 209 WPI_FH_INT_RX_CHNL(2) | \ 210 WPI_FH_INT_HI_PRIOR) 211 212/* Possible flags for register WPI_FH_TX_STATUS. */ 213#define WPI_FH_TX_STATUS_IDLE(qid) \ 214 (1 << ((qid) + 24) | 1 << ((qid) + 16)) 215 216/* Possible flags for register WPI_EEPROM. */ 217#define WPI_EEPROM_READ_VALID (1 << 0) 218 219/* Possible flags for register WPI_EEPROM_GP. */ 220#define WPI_EEPROM_VERSION 0x00000007 221#define WPI_EEPROM_GP_IF_OWNER 0x00000180 222 223/* Possible flags for register WPI_APMG_PS. */ 224#define WPI_APMG_PS_PWR_SRC_MASK (3 << 24) 225 226/* Possible flags for registers WPI_APMG_CLK_*. */ 227#define WPI_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 228#define WPI_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 229 230/* Possible flags for register WPI_APMG_PCI_STT. */ 231#define WPI_APMG_PCI_STT_L1A_DIS (1 << 11) 232 233struct wpi_shared { 234 uint32_t txbase[WPI_NTXQUEUES]; 235 uint32_t next; 236 uint32_t reserved[2]; 237} __packed; 238 239#define WPI_MAX_SEG_LEN 65520 240struct wpi_tx_desc { 241 uint8_t reserved1[3]; 242 uint8_t nsegs; 243#define WPI_PAD32(x) (roundup2(x, 4) - (x)) 244 245 struct { 246 uint32_t addr; 247 uint32_t len; 248 } __packed segs[WPI_MAX_SCATTER]; 249 uint8_t reserved2[28]; 250} __packed; 251 252struct wpi_tx_stat { 253 uint8_t rtsfailcnt; 254 uint8_t ackfailcnt; 255 uint8_t btkillcnt; 256 uint8_t rate; 257 uint32_t duration; 258 uint32_t status; 259#define WPI_TX_STATUS_SUCCESS 0x01 260#define WPI_TX_STATUS_DIRECT_DONE 0x02 261#define WPI_TX_STATUS_FAIL 0x80 262#define WPI_TX_STATUS_FAIL_SHORT_LIMIT 0x82 263#define WPI_TX_STATUS_FAIL_LONG_LIMIT 0x83 264#define WPI_TX_STATUS_FAIL_FIFO_UNDERRUN 0x84 265#define WPI_TX_STATUS_FAIL_MGMNT_ABORT 0x85 266#define WPI_TX_STATUS_FAIL_NEXT_FRAG 0x86 267#define WPI_TX_STATUS_FAIL_LIFE_EXPIRE 0x87 268#define WPI_TX_STATUS_FAIL_NODE_PS 0x88 269#define WPI_TX_STATUS_FAIL_ABORTED 0x89 270#define WPI_TX_STATUS_FAIL_BT_RETRY 0x8a 271#define WPI_TX_STATUS_FAIL_NODE_INVALID 0x8b 272#define WPI_TX_STATUS_FAIL_FRAG_DROPPED 0x8c 273#define WPI_TX_STATUS_FAIL_TID_DISABLE 0x8d 274#define WPI_TX_STATUS_FAIL_FRAME_FLUSHED 0x8e 275#define WPI_TX_STATUS_FAIL_INSUFFICIENT_CF_POLL 0x8f 276#define WPI_TX_STATUS_FAIL_TX_LOCKED 0x90 277#define WPI_TX_STATUS_FAIL_NO_BEACON_ON_RADAR 0x91 278 279} __packed; 280 281struct wpi_rx_desc { 282 uint32_t len; 283 uint8_t type; 284#define WPI_UC_READY 1 285#define WPI_RX_DONE 27 286#define WPI_TX_DONE 28 287#define WPI_START_SCAN 130 288#define WPI_SCAN_RESULTS 131 289#define WPI_STOP_SCAN 132 290#define WPI_BEACON_SENT 144 291#define WPI_RX_STATISTICS 156 292#define WPI_BEACON_STATISTICS 157 293#define WPI_STATE_CHANGED 161 294#define WPI_BEACON_MISSED 162 295 296 uint8_t flags; 297 uint8_t idx; 298 uint8_t qid; 299} __packed; 300 301#define WPI_RX_DESC_QID_MSK 0x07 302#define WPI_UNSOLICITED_RX_NOTIF 0x80 303 304struct wpi_rx_stat { 305 uint8_t len; 306#define WPI_STAT_MAXLEN 20 307 308 uint8_t id; 309 uint8_t rssi; /* received signal strength */ 310#define WPI_RSSI_OFFSET -95 311 312 uint8_t agc; /* access gain control */ 313 uint16_t signal; 314 uint16_t noise; 315} __packed; 316 317struct wpi_rx_head { 318 uint16_t chan; 319 uint16_t flags; 320#define WPI_STAT_FLAG_SHPREAMBLE (1 << 2) 321 322 uint8_t reserved; 323 uint8_t plcp; 324 uint16_t len; 325} __packed; 326 327struct wpi_rx_tail { 328 uint32_t flags; 329#define WPI_RX_NO_CRC_ERR (1 << 0) 330#define WPI_RX_NO_OVFL_ERR (1 << 1) 331/* shortcut for the above */ 332#define WPI_RX_NOERROR (WPI_RX_NO_CRC_ERR | WPI_RX_NO_OVFL_ERR) 333#define WPI_RX_CIPHER_MASK (7 << 8) 334#define WPI_RX_CIPHER_CCMP (2 << 8) 335#define WPI_RX_DECRYPT_MASK (3 << 11) 336#define WPI_RX_DECRYPT_OK (3 << 11) 337 338 uint64_t tstamp; 339 uint32_t tbeacon; 340} __packed; 341 342struct wpi_tx_cmd { 343 uint8_t code; 344#define WPI_CMD_RXON 16 345#define WPI_CMD_RXON_ASSOC 17 346#define WPI_CMD_EDCA_PARAMS 19 347#define WPI_CMD_TIMING 20 348#define WPI_CMD_ADD_NODE 24 349#define WPI_CMD_DEL_NODE 25 350#define WPI_CMD_TX_DATA 28 351#define WPI_CMD_MRR_SETUP 71 352#define WPI_CMD_SET_LED 72 353#define WPI_CMD_SET_POWER_MODE 119 354#define WPI_CMD_SCAN 128 355#define WPI_CMD_SET_BEACON 145 356#define WPI_CMD_TXPOWER 151 357#define WPI_CMD_BT_COEX 155 358#define WPI_CMD_GET_STATISTICS 156 359 360 uint8_t flags; 361 uint8_t idx; 362 uint8_t qid; 363 uint8_t data[124]; 364} __packed; 365 366/* Structure for command WPI_CMD_RXON. */ 367struct wpi_rxon { 368 uint8_t myaddr[IEEE80211_ADDR_LEN]; 369 uint16_t reserved1; 370 uint8_t bssid[IEEE80211_ADDR_LEN]; 371 uint16_t reserved2; 372 uint8_t wlap[IEEE80211_ADDR_LEN]; 373 uint16_t reserved3; 374 uint8_t mode; 375#define WPI_MODE_HOSTAP 1 376#define WPI_MODE_STA 3 377#define WPI_MODE_IBSS 4 378#define WPI_MODE_MONITOR 6 379 380 uint8_t air; 381 uint16_t reserved4; 382 uint8_t ofdm_mask; 383 uint8_t cck_mask; 384 uint16_t associd; 385 uint32_t flags; 386#define WPI_RXON_24GHZ (1 << 0) 387#define WPI_RXON_CCK (1 << 1) 388#define WPI_RXON_AUTO (1 << 2) 389#define WPI_RXON_SHSLOT (1 << 4) 390#define WPI_RXON_SHPREAMBLE (1 << 5) 391#define WPI_RXON_NODIVERSITY (1 << 7) 392#define WPI_RXON_ANTENNA_A (1 << 8) 393#define WPI_RXON_ANTENNA_B (1 << 9) 394#define WPI_RXON_TSF (1 << 15) 395#define WPI_RXON_CTS_TO_SELF (1 << 30) 396 397 uint32_t filter; 398#define WPI_FILTER_PROMISC (1 << 0) 399#define WPI_FILTER_CTL (1 << 1) 400#define WPI_FILTER_MULTICAST (1 << 2) 401#define WPI_FILTER_NODECRYPT (1 << 3) 402#define WPI_FILTER_BSS (1 << 5) 403#define WPI_FILTER_BEACON (1 << 6) 404#define WPI_FILTER_ASSOC (1 << 7) /* Accept associaton requests. */ 405 406 uint8_t chan; 407 uint16_t reserved5; 408} __packed; 409 410/* Structure for command WPI_CMD_RXON_ASSOC. */ 411struct wpi_assoc { 412 uint32_t flags; 413 uint32_t filter; 414 uint8_t ofdm_mask; 415 uint8_t cck_mask; 416 uint16_t reserved; 417} __packed; 418 419/* Structure for command WPI_CMD_EDCA_PARAMS. */ 420struct wpi_edca_params { 421 uint32_t flags; 422#define WPI_EDCA_UPDATE (1 << 0) 423 424 struct { 425 uint16_t cwmin; 426 uint16_t cwmax; 427 uint8_t aifsn; 428 uint8_t reserved; 429 uint16_t txoplimit; 430 } __packed ac[WME_NUM_AC]; 431} __packed; 432 433/* Structure for command WPI_CMD_TIMING. */ 434struct wpi_cmd_timing { 435 uint64_t tstamp; 436 uint16_t bintval; 437 uint16_t atim; 438 uint32_t binitval; 439 uint16_t lintval; 440 uint16_t reserved; 441} __packed; 442 443/* Structure for command WPI_CMD_ADD_NODE. */ 444struct wpi_node_info { 445 uint8_t control; 446#define WPI_NODE_UPDATE (1 << 0) 447 448 uint8_t reserved1[3]; 449 uint8_t macaddr[IEEE80211_ADDR_LEN]; 450 uint16_t reserved2; 451 uint8_t id; 452#define WPI_ID_BSS 0 453#define WPI_ID_IBSS_MIN 2 454#define WPI_ID_IBSS_MAX 23 455#define WPI_ID_BROADCAST 24 456#define WPI_ID_UNDEFINED (uint8_t)-1 457 458 uint8_t flags; 459#define WPI_FLAG_KEY_SET (1 << 0) 460 461 uint16_t reserved3; 462 uint16_t kflags; 463#define WPI_KFLAG_CCMP (1 << 1) 464#define WPI_KFLAG_KID(kid) ((kid) << 8) 465#define WPI_KFLAG_MULTICAST (1 << 14) 466 467 uint8_t tsc2; 468 uint8_t reserved4; 469 uint16_t ttak[5]; 470 uint16_t reserved5; 471 uint8_t key[IEEE80211_KEYBUF_SIZE]; 472 uint32_t action; 473#define WPI_ACTION_SET_RATE (1 << 2) 474 475 uint32_t mask; 476 uint16_t tid; 477 uint8_t plcp; 478 uint8_t antenna; 479#define WPI_ANTENNA_A (1 << 6) 480#define WPI_ANTENNA_B (1 << 7) 481#define WPI_ANTENNA_BOTH (WPI_ANTENNA_A | WPI_ANTENNA_B) 482 483 uint8_t add_imm; 484 uint8_t del_imm; 485 uint16_t add_imm_start; 486} __packed; 487 488/* Structure for command WPI_CMD_DEL_NODE. */ 489struct wpi_cmd_del_node { 490 uint8_t count; 491 uint8_t reserved1[3]; 492 uint8_t macaddr[IEEE80211_ADDR_LEN]; 493 uint16_t reserved2; 494} __packed; 495 496/* Structure for command WPI_CMD_TX_DATA. */ 497struct wpi_cmd_data { 498 uint16_t len; 499 uint16_t lnext; 500 uint32_t flags; 501#define WPI_TX_NEED_RTS (1 << 1) 502#define WPI_TX_NEED_CTS (1 << 2) 503#define WPI_TX_NEED_ACK (1 << 3) 504#define WPI_TX_FULL_TXOP (1 << 7) 505#define WPI_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 506#define WPI_TX_AUTO_SEQ (1 << 13) 507#define WPI_TX_MORE_FRAG (1 << 14) 508#define WPI_TX_INSERT_TSTAMP (1 << 16) 509 510 uint8_t plcp; 511 uint8_t id; 512 uint8_t tid; 513 uint8_t security; 514#define WPI_CIPHER_WEP 1 515#define WPI_CIPHER_CCMP 2 516#define WPI_CIPHER_TKIP 3 517#define WPI_CIPHER_WEP104 9 518 519 uint8_t key[IEEE80211_KEYBUF_SIZE]; 520 uint8_t tkip[IEEE80211_WEP_MICLEN]; 521 uint32_t fnext; 522 uint32_t lifetime; 523#define WPI_LIFETIME_INFINITE 0xffffffff 524 525 uint8_t ofdm_mask; 526 uint8_t cck_mask; 527 uint8_t rts_ntries; 528 uint8_t data_ntries; 529 uint16_t timeout; 530 uint16_t txop; 531} __packed; 532 533/* Structure for command WPI_CMD_SET_BEACON. */ 534struct wpi_cmd_beacon { 535 uint16_t len; 536 uint16_t reserved1; 537 uint32_t flags; /* same as wpi_cmd_data */ 538 uint8_t plcp; 539 uint8_t id; 540 uint8_t reserved2[30]; 541 uint32_t lifetime; 542 uint8_t ofdm_mask; 543 uint8_t cck_mask; 544 uint16_t reserved3[3]; 545 uint16_t tim; 546 uint8_t timsz; 547 uint8_t reserved4; 548} __packed; 549 550/* Structure for notification WPI_BEACON_MISSED. */ 551struct wpi_beacon_missed { 552 uint32_t consecutive; 553 uint32_t total; 554 uint32_t expected; 555 uint32_t received; 556} __packed; 557 558 559/* Structure for command WPI_CMD_MRR_SETUP. */ 560#define WPI_RIDX_MAX 11 561struct wpi_mrr_setup { 562 uint32_t which; 563#define WPI_MRR_CTL 0 564#define WPI_MRR_DATA 1 565 566 struct { 567 uint8_t plcp; 568 uint8_t flags; 569 uint8_t ntries; 570#define WPI_NTRIES_DEFAULT 2 571 572 uint8_t next; 573 } __packed rates[WPI_RIDX_MAX + 1]; 574} __packed; 575 576/* Structure for command WPI_CMD_SET_LED. */ 577struct wpi_cmd_led { 578 uint32_t unit; /* multiplier (in usecs) */ 579 uint8_t which; 580#define WPI_LED_ACTIVITY 1 581#define WPI_LED_LINK 2 582 583 uint8_t off; 584 uint8_t on; 585 uint8_t reserved; 586} __packed; 587 588/* Structure for command WPI_CMD_SET_POWER_MODE. */ 589struct wpi_pmgt_cmd { 590 uint16_t flags; 591#define WPI_PS_ALLOW_SLEEP (1 << 0) 592#define WPI_PS_NOTIFY (1 << 1) 593#define WPI_PS_SLEEP_OVER_DTIM (1 << 2) 594#define WPI_PS_PCI_PMGT (1 << 3) 595 596 uint8_t reserved[2]; 597 uint32_t rxtimeout; 598 uint32_t txtimeout; 599 uint32_t intval[5]; 600} __packed; 601 602/* Structures for command WPI_CMD_SCAN. */ 603#define WPI_SCAN_MAX_ESSIDS 4 604struct wpi_scan_essid { 605 uint8_t id; 606 uint8_t len; 607 uint8_t data[IEEE80211_NWID_LEN]; 608} __packed; 609 610struct wpi_scan_hdr { 611 uint16_t len; 612 uint8_t reserved1; 613 uint8_t nchan; 614 uint16_t quiet_time; 615 uint16_t quiet_threshold; 616 uint16_t crc_threshold; 617 uint16_t reserved2; 618 uint32_t max_svc; /* background scans */ 619 uint32_t pause_svc; /* background scans */ 620 uint32_t flags; 621 uint32_t filter; 622 623 /* Followed by a struct wpi_cmd_data. */ 624 /* Followed by an array of 4 structs wpi_scan_essid. */ 625 /* Followed by probe request body. */ 626 /* Followed by an array of ``nchan'' structs wpi_scan_chan. */ 627} __packed; 628 629struct wpi_scan_chan { 630 uint8_t flags; 631#define WPI_CHAN_ACTIVE (1 << 0) 632#define WPI_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 633 634 uint8_t chan; 635 uint8_t rf_gain; 636 uint8_t dsp_gain; 637 uint16_t active; /* msecs */ 638 uint16_t passive; /* msecs */ 639} __packed; 640 641#define WPI_SCAN_CRC_TH_DEFAULT htole16(1) 642#define WPI_SCAN_CRC_TH_NEVER htole16(0xffff) 643 644/* Maximum size of a scan command. */ 645#define WPI_SCAN_MAXSZ (MCLBYTES - 4) 646 647#define WPI_ACTIVE_DWELL_TIME_2GHZ (30) /* all times in msec */ 648#define WPI_ACTIVE_DWELL_TIME_5GHZ (20) 649#define WPI_ACTIVE_DWELL_FACTOR_2GHZ ( 3) 650#define WPI_ACTIVE_DWELL_FACTOR_5GHZ ( 2) 651 652#define WPI_PASSIVE_DWELL_TIME_2GHZ ( 20) 653#define WPI_PASSIVE_DWELL_TIME_5GHZ ( 10) 654#define WPI_PASSIVE_DWELL_BASE (100) 655 656/* Structure for command WPI_CMD_TXPOWER. */ 657struct wpi_cmd_txpower { 658 uint8_t band; 659#define WPI_BAND_5GHZ 0 660#define WPI_BAND_2GHZ 1 661 662 uint8_t reserved; 663 uint16_t chan; 664 665 struct { 666 uint8_t plcp; 667 uint8_t rf_gain; 668 uint8_t dsp_gain; 669 uint8_t reserved; 670 } __packed rates[WPI_RIDX_MAX + 1]; 671 672} __packed; 673 674/* Structure for command WPI_CMD_BT_COEX. */ 675struct wpi_bluetooth { 676 uint8_t flags; 677#define WPI_BT_COEX_DISABLE 0 678#define WPI_BT_COEX_MODE_2WIRE 1 679#define WPI_BT_COEX_MODE_3WIRE 2 680#define WPI_BT_COEX_MODE_4WIRE 3 681 682 uint8_t lead_time; 683#define WPI_BT_LEAD_TIME_DEF 30 684 685 uint8_t max_kill; 686#define WPI_BT_MAX_KILL_DEF 5 687 688 uint8_t reserved; 689 uint32_t kill_ack; 690 uint32_t kill_cts; 691} __packed; 692 693/* Structure for WPI_UC_READY notification. */ 694struct wpi_ucode_info { 695 uint8_t minor; 696 uint8_t major; 697 uint16_t reserved1; 698 uint8_t revision[8]; 699 uint8_t type; 700 uint8_t subtype; 701 uint16_t reserved2; 702 uint32_t logptr; 703 uint32_t errptr; 704 uint32_t tstamp; 705 uint32_t valid; 706} __packed; 707 708/* Structure for WPI_START_SCAN notification. */ 709struct wpi_start_scan { 710 uint64_t tstamp; 711 uint32_t tbeacon; 712 uint8_t chan; 713 uint8_t band; 714 uint16_t reserved; 715 uint32_t status; 716} __packed; 717 718/* Structure for WPI_STOP_SCAN notification. */ 719struct wpi_stop_scan { 720 uint8_t nchan; 721 uint8_t status; 722 uint8_t reserved; 723 uint8_t chan; 724 uint64_t tsf; 725} __packed; 726 727/* Structures for WPI_{RX,BEACON}_STATISTICS notification. */ 728struct wpi_rx_phy_stats { 729 uint32_t ina; 730 uint32_t fina; 731 uint32_t bad_plcp; 732 uint32_t bad_crc32; 733 uint32_t overrun; 734 uint32_t eoverrun; 735 uint32_t good_crc32; 736 uint32_t fa; 737 uint32_t bad_fina_sync; 738 uint32_t sfd_timeout; 739 uint32_t fina_timeout; 740 uint32_t no_rts_ack; 741 uint32_t rxe_limit; 742 uint32_t ack; 743 uint32_t cts; 744} __packed; 745 746struct wpi_rx_general_stats { 747 uint32_t bad_cts; 748 uint32_t bad_ack; 749 uint32_t not_bss; 750 uint32_t filtered; 751 uint32_t bad_chan; 752} __packed; 753 754struct wpi_rx_stats { 755 struct wpi_rx_phy_stats ofdm; 756 struct wpi_rx_phy_stats cck; 757 struct wpi_rx_general_stats general; 758} __packed; 759 760struct wpi_tx_stats { 761 uint32_t preamble; 762 uint32_t rx_detected; 763 uint32_t bt_defer; 764 uint32_t bt_kill; 765 uint32_t short_len; 766 uint32_t cts_timeout; 767 uint32_t ack_timeout; 768 uint32_t exp_ack; 769 uint32_t ack; 770} __packed; 771 772struct wpi_general_stats { 773 uint32_t temp; 774 uint32_t burst_check; 775 uint32_t burst; 776 uint32_t reserved[4]; 777 uint32_t sleep; 778 uint32_t slot_out; 779 uint32_t slot_idle; 780 uint32_t ttl_tstamp; 781 uint32_t tx_ant_a; 782 uint32_t tx_ant_b; 783 uint32_t exec; 784 uint32_t probe; 785} __packed; 786 787struct wpi_stats { 788 uint32_t flags; 789 struct wpi_rx_stats rx; 790 struct wpi_tx_stats tx; 791 struct wpi_general_stats general; 792} __packed; 793 794/* Possible flags for command WPI_CMD_GET_STATISTICS. */ 795#define WPI_STATISTICS_BEACON_DISABLE (1 << 1) 796 797 798/* Firmware error dump entry. */ 799struct wpi_fw_dump { 800 uint32_t desc; 801 uint32_t time; 802 uint32_t blink[2]; 803 uint32_t ilink[2]; 804 uint32_t data; 805} __packed; 806 807/* Firmware image file header. */ 808struct wpi_firmware_hdr { 809 810#define WPI_FW_MINVERSION 2144 811#define WPI_FW_NAME "wpifw" 812 813 uint16_t driver; 814 uint8_t minor; 815 uint8_t major; 816 uint32_t rtextsz; 817 uint32_t rdatasz; 818 uint32_t itextsz; 819 uint32_t idatasz; 820 uint32_t btextsz; 821} __packed; 822 823#define WPI_FW_TEXT_MAXSZ ( 80 * 1024 ) 824#define WPI_FW_DATA_MAXSZ ( 32 * 1024 ) 825#define WPI_FW_BOOT_TEXT_MAXSZ 1024 826 827#define WPI_FW_UPDATED (1U << 31 ) 828 829/* 830 * Offsets into EEPROM. 831 */ 832#define WPI_EEPROM_MAC 0x015 833#define WPI_EEPROM_REVISION 0x035 834#define WPI_EEPROM_SKU_CAP 0x045 835#define WPI_EEPROM_TYPE 0x04a 836#define WPI_EEPROM_DOMAIN 0x060 837#define WPI_EEPROM_BAND1 0x063 838#define WPI_EEPROM_BAND2 0x072 839#define WPI_EEPROM_BAND3 0x080 840#define WPI_EEPROM_BAND4 0x08d 841#define WPI_EEPROM_BAND5 0x099 842#define WPI_EEPROM_POWER_GRP 0x100 843 844struct wpi_eeprom_chan { 845 uint8_t flags; 846#define WPI_EEPROM_CHAN_VALID (1 << 0) 847#define WPI_EEPROM_CHAN_IBSS (1 << 1) 848#define WPI_EEPROM_CHAN_ACTIVE (1 << 3) 849#define WPI_EEPROM_CHAN_RADAR (1 << 4) 850 851 int8_t maxpwr; 852} __packed; 853 854struct wpi_eeprom_sample { 855 uint8_t index; 856 int8_t power; 857 uint16_t volt; 858} __packed; 859 860#define WPI_POWER_GROUPS_COUNT 5 861struct wpi_eeprom_group { 862 struct wpi_eeprom_sample samples[5]; 863 int32_t coef[5]; 864 int32_t corr[5]; 865 int8_t maxpwr; 866 uint8_t chan; 867 int16_t temp; 868} __packed; 869 870#define WPI_CHAN_BANDS_COUNT 5 871#define WPI_MAX_CHAN_PER_BAND 14 872static const struct wpi_chan_band { 873 uint32_t addr; /* offset in EEPROM */ 874 uint8_t nchan; 875 uint8_t chan[WPI_MAX_CHAN_PER_BAND]; 876} wpi_bands[] = { 877 /* 20MHz channels, 2GHz band. */ 878 { WPI_EEPROM_BAND1, 14, 879 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 880 /* 20MHz channels, 5GHz band. */ 881 { WPI_EEPROM_BAND2, 13, 882 { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 883 { WPI_EEPROM_BAND3, 12, 884 { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 885 { WPI_EEPROM_BAND4, 11, 886 { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 887 { WPI_EEPROM_BAND5, 6, 888 { 145, 149, 153, 157, 161, 165 } } 889}; 890 891/* HW rate indices. */ 892#define WPI_RIDX_OFDM6 0 893#define WPI_RIDX_OFDM36 5 894#define WPI_RIDX_OFDM48 6 895#define WPI_RIDX_OFDM54 7 896#define WPI_RIDX_CCK1 8 897#define WPI_RIDX_CCK2 9 898#define WPI_RIDX_CCK11 11 899 900static const uint8_t wpi_ridx_to_plcp[] = { 901 /* OFDM: IEEE Std 802.11a-1999, pp. 14 Table 80 */ 902 /* R1-R4 (ral/ural is R4-R1) */ 903 0xd, 0xf, 0x5, 0x7, 0x9, 0xb, 0x1, 0x3, 904 /* CCK: device-dependent */ 905 10, 20, 55, 110 906}; 907 908#define WPI_MAX_PWR_INDEX 77 909 910/* 911 * RF Tx gain values from highest to lowest power (values obtained from 912 * the reference driver.) 913 */ 914static const uint8_t wpi_rf_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 915 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xbb, 0xbb, 0xbb, 916 0xbb, 0xf3, 0xf3, 0xf3, 0xf3, 0xf3, 0xd3, 0xd3, 0xb3, 0xb3, 0xb3, 917 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x73, 0xeb, 0xeb, 0xeb, 918 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xab, 0xab, 0xab, 0x8b, 919 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xc3, 0xc3, 0xc3, 0xc3, 0xa3, 920 0xa3, 0xa3, 0xa3, 0x83, 0x83, 0x83, 0x83, 0x63, 0x63, 0x63, 0x63, 921 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 0x03, 0x03, 0x03, 922 0x03 923}; 924 925static const uint8_t wpi_rf_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 926 0xfb, 0xfb, 0xfb, 0xdb, 0xdb, 0xbb, 0xbb, 0x9b, 0x9b, 0x7b, 0x7b, 927 0x7b, 0x7b, 0x5b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x1b, 0x1b, 928 0x1b, 0x73, 0x73, 0x73, 0x53, 0x53, 0x53, 0x53, 0x53, 0x33, 0x33, 929 0x33, 0x33, 0x13, 0x13, 0x13, 0x13, 0x13, 0xab, 0xab, 0xab, 0x8b, 930 0x8b, 0x8b, 0x8b, 0x6b, 0x6b, 0x6b, 0x6b, 0x4b, 0x4b, 0x4b, 0x4b, 931 0x2b, 0x2b, 0x2b, 0x2b, 0x0b, 0x0b, 0x0b, 0x0b, 0x83, 0x83, 0x63, 932 0x63, 0x63, 0x63, 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 933 0x03 934}; 935 936/* 937 * DSP pre-DAC gain values from highest to lowest power (values obtained 938 * from the reference driver.) 939 */ 940static const uint8_t wpi_dsp_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 941 0x7f, 0x7f, 0x7f, 0x7f, 0x7d, 0x6e, 0x69, 0x62, 0x7d, 0x73, 0x6c, 942 0x63, 0x77, 0x6f, 0x69, 0x61, 0x5c, 0x6a, 0x64, 0x78, 0x71, 0x6b, 943 0x7d, 0x77, 0x70, 0x6a, 0x65, 0x61, 0x5b, 0x6b, 0x79, 0x73, 0x6d, 944 0x7f, 0x79, 0x73, 0x6c, 0x66, 0x60, 0x5c, 0x6e, 0x68, 0x62, 0x74, 945 0x7d, 0x77, 0x71, 0x6b, 0x65, 0x60, 0x71, 0x6a, 0x66, 0x5f, 0x71, 946 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 947 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 948 0x5f 949}; 950 951static const uint8_t wpi_dsp_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 952 0x7f, 0x78, 0x72, 0x77, 0x65, 0x71, 0x66, 0x72, 0x67, 0x75, 0x6b, 953 0x63, 0x5c, 0x6c, 0x7d, 0x76, 0x6d, 0x66, 0x60, 0x5a, 0x68, 0x62, 954 0x5c, 0x76, 0x6f, 0x68, 0x7e, 0x79, 0x71, 0x69, 0x63, 0x76, 0x6f, 955 0x68, 0x62, 0x74, 0x6d, 0x66, 0x62, 0x5d, 0x71, 0x6b, 0x63, 0x78, 956 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 957 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x6b, 0x63, 0x78, 958 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 959 0x78 960}; 961 962/* 963 * Power saving settings (values obtained from the reference driver.) 964 */ 965#define WPI_NDTIMRANGES 2 966#define WPI_NPOWERLEVELS 6 967static const struct wpi_pmgt { 968 uint32_t rxtimeout; 969 uint32_t txtimeout; 970 uint32_t intval[5]; 971 int skip_dtim; 972} wpi_pmgt[WPI_NDTIMRANGES][WPI_NPOWERLEVELS] = { 973 /* DTIM <= 10 */ 974 { 975 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 976 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 977 { 200, 300, { 2, 4, 6, 7, 7 }, 0 }, /* PS level 2 */ 978 { 50, 100, { 2, 6, 9, 9, 10 }, 0 }, /* PS level 3 */ 979 { 50, 25, { 2, 7, 9, 9, 10 }, 1 }, /* PS level 4 */ 980 { 25, 25, { 4, 7, 10, 10, 10 }, 1 } /* PS level 5 */ 981 }, 982 /* DTIM >= 11 */ 983 { 984 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 985 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 986 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 987 { 50, 100, { 2, 6, 9, 9, -1 }, 0 }, /* PS level 3 */ 988 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 989 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 990 } 991}; 992 993/* Firmware errors. */ 994static const char * const wpi_fw_errmsg[] = { 995 "OK", 996 "FAIL", 997 "BAD_PARAM", 998 "BAD_CHECKSUM", 999 "NMI_INTERRUPT", 1000 "SYSASSERT", 1001 "FATAL_ERROR" 1002}; 1003 1004#define WPI_READ(sc, reg) \ 1005 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 1006 1007#define WPI_WRITE(sc, reg, val) \ 1008 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1009 1010#define WPI_WRITE_REGION_4(sc, offset, datap, count) \ 1011 bus_space_write_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 1012 (datap), (count)) 1013 1014#define WPI_SETBITS(sc, reg, mask) \ 1015 WPI_WRITE(sc, reg, WPI_READ(sc, reg) | (mask)) 1016 1017#define WPI_CLRBITS(sc, reg, mask) \ 1018 WPI_WRITE(sc, reg, WPI_READ(sc, reg) & ~(mask)) 1019 1020#define WPI_BARRIER_WRITE(sc) \ 1021 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1022 BUS_SPACE_BARRIER_WRITE) 1023 1024#define WPI_BARRIER_READ_WRITE(sc) \ 1025 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1026 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 1027