if_wpireg.h revision 280093
1/* $FreeBSD: head/sys/dev/wpi/if_wpireg.h 280093 2015-03-15 21:04:55Z adrian $ */ 2 3/*- 4 * Copyright (c) 2006,2007 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#define WPI_TX_RING_COUNT 256 21#define WPI_TX_RING_LOMARK 192 22#define WPI_TX_RING_HIMARK 224 23#define WPI_RX_RING_COUNT_LOG 6 24#define WPI_RX_RING_COUNT (1 << WPI_RX_RING_COUNT_LOG) 25 26#define WPI_NTXQUEUES 8 27#define WPI_DRV_NTXQUEUES 5 28#define WPI_CMD_QUEUE_NUM 4 29 30#define WPI_NDMACHNLS 6 31 32/* Maximum scatter/gather. */ 33#define WPI_MAX_SCATTER 4 34 35/* 36 * Rings must be aligned on a 16K boundary. 37 */ 38#define WPI_RING_DMA_ALIGN 0x4000 39 40/* Maximum Rx buffer size. */ 41#define WPI_RBUF_SIZE ( 3 * 1024 ) /* XXX 3000 but must be aligned */ 42 43/* 44 * Control and status registers. 45 */ 46#define WPI_HW_IF_CONFIG 0x000 47#define WPI_INT 0x008 48#define WPI_INT_MASK 0x00c 49#define WPI_FH_INT 0x010 50#define WPI_GPIO_IN 0x018 51#define WPI_RESET 0x020 52#define WPI_GP_CNTRL 0x024 53#define WPI_EEPROM 0x02c 54#define WPI_EEPROM_GP 0x030 55#define WPI_GIO 0x03c 56#define WPI_UCODE_GP1 0x054 57#define WPI_UCODE_GP1_SET 0x058 58#define WPI_UCODE_GP1_CLR 0x05c 59#define WPI_UCODE_GP2 0x060 60#define WPI_GIO_CHICKEN 0x100 61#define WPI_ANA_PLL 0x20c 62#define WPI_DBG_HPET_MEM 0x240 63#define WPI_MEM_RADDR 0x40c 64#define WPI_MEM_WADDR 0x410 65#define WPI_MEM_WDATA 0x418 66#define WPI_MEM_RDATA 0x41c 67#define WPI_PRPH_WADDR 0x444 68#define WPI_PRPH_RADDR 0x448 69#define WPI_PRPH_WDATA 0x44c 70#define WPI_PRPH_RDATA 0x450 71#define WPI_HBUS_TARG_WRPTR 0x460 72 73/* 74 * Flow-Handler registers. 75 */ 76#define WPI_FH_CBBC_CTRL(qid) (0x940 + (qid) * 8) 77#define WPI_FH_CBBC_BASE(qid) (0x944 + (qid) * 8) 78#define WPI_FH_RX_CONFIG 0xc00 79#define WPI_FH_RX_BASE 0xc04 80#define WPI_FH_RX_WPTR 0xc20 81#define WPI_FH_RX_RPTR_ADDR 0xc24 82#define WPI_FH_RSSR_TBL 0xcc0 83#define WPI_FH_RX_STATUS 0xcc4 84#define WPI_FH_TX_CONFIG(qid) (0xd00 + (qid) * 32) 85#define WPI_FH_TX_BASE 0xe80 86#define WPI_FH_MSG_CONFIG 0xe88 87#define WPI_FH_TX_STATUS 0xe90 88 89 90/* 91 * NIC internal memory offsets. 92 */ 93#define WPI_ALM_SCHED_MODE 0x2e00 94#define WPI_ALM_SCHED_ARASTAT 0x2e04 95#define WPI_ALM_SCHED_TXFACT 0x2e10 96#define WPI_ALM_SCHED_TXF4MF 0x2e14 97#define WPI_ALM_SCHED_TXF5MF 0x2e20 98#define WPI_ALM_SCHED_SBYPASS_MODE1 0x2e2c 99#define WPI_ALM_SCHED_SBYPASS_MODE2 0x2e30 100#define WPI_APMG_CLK_CTRL 0x3000 101#define WPI_APMG_CLK_EN 0x3004 102#define WPI_APMG_CLK_DIS 0x3008 103#define WPI_APMG_PS 0x300c 104#define WPI_APMG_PCI_STT 0x3010 105#define WPI_APMG_RFKILL 0x3014 106#define WPI_BSM_WR_CTRL 0x3400 107#define WPI_BSM_WR_MEM_SRC 0x3404 108#define WPI_BSM_WR_MEM_DST 0x3408 109#define WPI_BSM_WR_DWCOUNT 0x340c 110#define WPI_BSM_DRAM_TEXT_ADDR 0x3490 111#define WPI_BSM_DRAM_TEXT_SIZE 0x3494 112#define WPI_BSM_DRAM_DATA_ADDR 0x3498 113#define WPI_BSM_DRAM_DATA_SIZE 0x349c 114#define WPI_BSM_SRAM_BASE 0x3800 115 116 117/* Possible flags for register WPI_HW_IF_CONFIG. */ 118#define WPI_HW_IF_CONFIG_ALM_MB (1 << 8) 119#define WPI_HW_IF_CONFIG_ALM_MM (1 << 9) 120#define WPI_HW_IF_CONFIG_SKU_MRC (1 << 10) 121#define WPI_HW_IF_CONFIG_REV_D (1 << 11) 122#define WPI_HW_IF_CONFIG_TYPE_B (1 << 12) 123 124/* Possible flags for registers WPI_PRPH_RADDR/WPI_PRPH_WADDR. */ 125#define WPI_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 126 127/* Possible values for WPI_BSM_WR_MEM_DST. */ 128#define WPI_FW_TEXT_BASE 0x00000000 129#define WPI_FW_DATA_BASE 0x00800000 130 131/* Possible flags for WPI_GPIO_IN. */ 132#define WPI_GPIO_IN_VMAIN (1 << 9) 133 134/* Possible flags for register WPI_RESET. */ 135#define WPI_RESET_NEVO (1 << 0) 136#define WPI_RESET_SW (1 << 7) 137#define WPI_RESET_MASTER_DISABLED (1 << 8) 138#define WPI_RESET_STOP_MASTER (1 << 9) 139 140/* Possible flags for register WPI_GP_CNTRL. */ 141#define WPI_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 142#define WPI_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 143#define WPI_GP_CNTRL_INIT_DONE (1 << 2) 144#define WPI_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 145#define WPI_GP_CNTRL_SLEEP (1 << 4) 146#define WPI_GP_CNTRL_PS_MASK (7 << 24) 147#define WPI_GP_CNTRL_MAC_PS (4 << 24) 148#define WPI_GP_CNTRL_RFKILL (1 << 27) 149 150/* Possible flags for register WPI_GIO_CHICKEN. */ 151#define WPI_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 152#define WPI_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 153 154/* Possible flags for register WPI_GIO. */ 155#define WPI_GIO_L0S_ENA (1 << 1) 156 157/* Possible flags for register WPI_FH_RX_CONFIG. */ 158#define WPI_FH_RX_CONFIG_DMA_ENA (1U << 31) 159#define WPI_FH_RX_CONFIG_RDRBD_ENA (1 << 29) 160#define WPI_FH_RX_CONFIG_WRSTATUS_ENA (1 << 27) 161#define WPI_FH_RX_CONFIG_MAXFRAG (1 << 24) 162#define WPI_FH_RX_CONFIG_NRBD(x) ((x) << 20) 163#define WPI_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 164#define WPI_FH_RX_CONFIG_IRQ_TIMEOUT(x) ((x) << 4) 165 166/* Possible flags for register WPI_ANA_PLL. */ 167#define WPI_ANA_PLL_INIT (1 << 24) 168 169/* Possible flags for register WPI_UCODE_GP1*. */ 170#define WPI_UCODE_GP1_MAC_SLEEP (1 << 0) 171#define WPI_UCODE_GP1_RFKILL (1 << 1) 172#define WPI_UCODE_GP1_CMD_BLOCKED (1 << 2) 173 174/* Possible flags for register WPI_FH_RX_STATUS. */ 175#define WPI_FH_RX_STATUS_IDLE (1 << 24) 176 177/* Possible flags for register WPI_BSM_WR_CTRL. */ 178#define WPI_BSM_WR_CTRL_START_EN (1 << 30) 179#define WPI_BSM_WR_CTRL_START (1U << 31) 180 181/* Possible flags for register WPI_INT. */ 182#define WPI_INT_ALIVE (1 << 0) 183#define WPI_INT_WAKEUP (1 << 1) 184#define WPI_INT_SW_RX (1 << 3) 185#define WPI_INT_SW_ERR (1 << 25) 186#define WPI_INT_FH_TX (1 << 27) 187#define WPI_INT_HW_ERR (1 << 29) 188#define WPI_INT_FH_RX (1U << 31) 189 190/* Shortcut. */ 191#define WPI_INT_MASK_DEF \ 192 (WPI_INT_SW_ERR | WPI_INT_HW_ERR | WPI_INT_FH_TX | \ 193 WPI_INT_FH_RX | WPI_INT_ALIVE | WPI_INT_WAKEUP | \ 194 WPI_INT_SW_RX) 195 196/* Possible flags for register WPI_FH_INT. */ 197#define WPI_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 198#define WPI_FH_INT_HI_PRIOR (1 << 30) 199/* Shortcuts for the above. */ 200#define WPI_FH_INT_RX \ 201 (WPI_FH_INT_RX_CHNL(0) | \ 202 WPI_FH_INT_RX_CHNL(1) | \ 203 WPI_FH_INT_RX_CHNL(2) | \ 204 WPI_FH_INT_HI_PRIOR) 205 206/* Possible flags for register WPI_FH_TX_STATUS. */ 207#define WPI_FH_TX_STATUS_IDLE(qid) \ 208 (1 << ((qid) + 24) | 1 << ((qid) + 16)) 209 210/* Possible flags for register WPI_EEPROM. */ 211#define WPI_EEPROM_READ_VALID (1 << 0) 212 213/* Possible flags for register WPI_EEPROM_GP. */ 214#define WPI_EEPROM_VERSION 0x00000007 215#define WPI_EEPROM_GP_IF_OWNER 0x00000180 216 217/* Possible flags for register WPI_APMG_PS. */ 218#define WPI_APMG_PS_PWR_SRC_MASK (3 << 24) 219 220/* Possible flags for registers WPI_APMG_CLK_*. */ 221#define WPI_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 222#define WPI_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 223 224/* Possible flags for register WPI_APMG_PCI_STT. */ 225#define WPI_APMG_PCI_STT_L1A_DIS (1 << 11) 226 227struct wpi_shared { 228 uint32_t txbase[WPI_NTXQUEUES]; 229 uint32_t next; 230 uint32_t reserved[2]; 231} __packed; 232 233#define WPI_MAX_SEG_LEN 65520 234struct wpi_tx_desc { 235 uint8_t reserved1[3]; 236 uint8_t nsegs; 237#define WPI_PAD32(x) (roundup2(x, 4) - (x)) 238 239 struct { 240 uint32_t addr; 241 uint32_t len; 242 } __packed segs[WPI_MAX_SCATTER]; 243 uint8_t reserved2[28]; 244} __packed; 245 246struct wpi_tx_stat { 247 uint8_t rtsfailcnt; 248 uint8_t ackfailcnt; 249 uint8_t btkillcnt; 250 uint8_t rate; 251 uint32_t duration; 252 uint32_t status; 253} __packed; 254 255struct wpi_rx_desc { 256 uint32_t len; 257 uint8_t type; 258#define WPI_UC_READY 1 259#define WPI_RX_DONE 27 260#define WPI_TX_DONE 28 261#define WPI_START_SCAN 130 262#define WPI_SCAN_RESULTS 131 263#define WPI_STOP_SCAN 132 264#define WPI_BEACON_SENT 144 265#define WPI_RX_STATISTICS 156 266#define WPI_BEACON_STATISTICS 157 267#define WPI_STATE_CHANGED 161 268#define WPI_BEACON_MISSED 162 269 270 uint8_t flags; 271 uint8_t idx; 272 uint8_t qid; 273} __packed; 274 275#define WPI_RX_DESC_QID_MSK 0x07 276#define WPI_UNSOLICITED_RX_NOTIF 0x80 277 278struct wpi_rx_stat { 279 uint8_t len; 280#define WPI_STAT_MAXLEN 20 281 282 uint8_t id; 283 uint8_t rssi; /* received signal strength */ 284#define WPI_RSSI_OFFSET -95 285 286 uint8_t agc; /* access gain control */ 287 uint16_t signal; 288 uint16_t noise; 289} __packed; 290 291struct wpi_rx_head { 292 uint16_t chan; 293 uint16_t flags; 294#define WPI_STAT_FLAG_SHPREAMBLE (1 << 2) 295 296 uint8_t reserved; 297 uint8_t plcp; 298 uint16_t len; 299} __packed; 300 301struct wpi_rx_tail { 302 uint32_t flags; 303#define WPI_RX_NO_CRC_ERR (1 << 0) 304#define WPI_RX_NO_OVFL_ERR (1 << 1) 305/* shortcut for the above */ 306#define WPI_RX_NOERROR (WPI_RX_NO_CRC_ERR | WPI_RX_NO_OVFL_ERR) 307#define WPI_RX_CIPHER_MASK (7 << 8) 308#define WPI_RX_CIPHER_CCMP (2 << 8) 309#define WPI_RX_DECRYPT_MASK (3 << 11) 310#define WPI_RX_DECRYPT_OK (3 << 11) 311 312 uint64_t tstamp; 313 uint32_t tbeacon; 314} __packed; 315 316struct wpi_tx_cmd { 317 uint8_t code; 318#define WPI_CMD_RXON 16 319#define WPI_CMD_RXON_ASSOC 17 320#define WPI_CMD_EDCA_PARAMS 19 321#define WPI_CMD_TIMING 20 322#define WPI_CMD_ADD_NODE 24 323#define WPI_CMD_DEL_NODE 25 324#define WPI_CMD_TX_DATA 28 325#define WPI_CMD_MRR_SETUP 71 326#define WPI_CMD_SET_LED 72 327#define WPI_CMD_SET_POWER_MODE 119 328#define WPI_CMD_SCAN 128 329#define WPI_CMD_SET_BEACON 145 330#define WPI_CMD_TXPOWER 151 331#define WPI_CMD_BT_COEX 155 332#define WPI_CMD_GET_STATISTICS 156 333 334 uint8_t flags; 335 uint8_t idx; 336 uint8_t qid; 337 uint8_t data[124]; 338} __packed; 339 340/* Structure for command WPI_CMD_RXON. */ 341struct wpi_rxon { 342 uint8_t myaddr[IEEE80211_ADDR_LEN]; 343 uint16_t reserved1; 344 uint8_t bssid[IEEE80211_ADDR_LEN]; 345 uint16_t reserved2; 346 uint8_t wlap[IEEE80211_ADDR_LEN]; 347 uint16_t reserved3; 348 uint8_t mode; 349#define WPI_MODE_HOSTAP 1 350#define WPI_MODE_STA 3 351#define WPI_MODE_IBSS 4 352#define WPI_MODE_MONITOR 6 353 354 uint8_t air; 355 uint16_t reserved4; 356 uint8_t ofdm_mask; 357 uint8_t cck_mask; 358 uint16_t associd; 359 uint32_t flags; 360#define WPI_RXON_24GHZ (1 << 0) 361#define WPI_RXON_CCK (1 << 1) 362#define WPI_RXON_AUTO (1 << 2) 363#define WPI_RXON_SHSLOT (1 << 4) 364#define WPI_RXON_SHPREAMBLE (1 << 5) 365#define WPI_RXON_NODIVERSITY (1 << 7) 366#define WPI_RXON_ANTENNA_A (1 << 8) 367#define WPI_RXON_ANTENNA_B (1 << 9) 368#define WPI_RXON_TSF (1 << 15) 369#define WPI_RXON_CTS_TO_SELF (1 << 30) 370 371 uint32_t filter; 372#define WPI_FILTER_PROMISC (1 << 0) 373#define WPI_FILTER_CTL (1 << 1) 374#define WPI_FILTER_MULTICAST (1 << 2) 375#define WPI_FILTER_NODECRYPT (1 << 3) 376#define WPI_FILTER_BSS (1 << 5) 377#define WPI_FILTER_BEACON (1 << 6) 378 379 uint8_t chan; 380 uint16_t reserved5; 381} __packed; 382 383/* Structure for command WPI_CMD_RXON_ASSOC. */ 384struct wpi_assoc { 385 uint32_t flags; 386 uint32_t filter; 387 uint8_t ofdm_mask; 388 uint8_t cck_mask; 389 uint16_t reserved; 390} __packed; 391 392/* Structure for command WPI_CMD_EDCA_PARAMS. */ 393struct wpi_edca_params { 394 uint32_t flags; 395#define WPI_EDCA_UPDATE (1 << 0) 396 397 struct { 398 uint16_t cwmin; 399 uint16_t cwmax; 400 uint8_t aifsn; 401 uint8_t reserved; 402 uint16_t txoplimit; 403 } __packed ac[WME_NUM_AC]; 404} __packed; 405 406/* Structure for command WPI_CMD_TIMING. */ 407struct wpi_cmd_timing { 408 uint64_t tstamp; 409 uint16_t bintval; 410 uint16_t atim; 411 uint32_t binitval; 412 uint16_t lintval; 413 uint16_t reserved; 414} __packed; 415 416/* Structure for command WPI_CMD_ADD_NODE. */ 417struct wpi_node_info { 418 uint8_t control; 419#define WPI_NODE_UPDATE (1 << 0) 420 421 uint8_t reserved1[3]; 422 uint8_t macaddr[IEEE80211_ADDR_LEN]; 423 uint16_t reserved2; 424 uint8_t id; 425#define WPI_ID_BSS 0 426#define WPI_ID_IBSS_MIN 2 427#define WPI_ID_IBSS_MAX 23 428#define WPI_ID_BROADCAST 24 429#define WPI_ID_UNDEFINED (uint8_t)-1 430 431 uint8_t flags; 432#define WPI_FLAG_KEY_SET (1 << 0) 433 434 uint16_t reserved3; 435 uint16_t kflags; 436#define WPI_KFLAG_CCMP (1 << 1) 437#define WPI_KFLAG_KID(kid) ((kid) << 8) 438#define WPI_KFLAG_MULTICAST (1 << 14) 439 440 uint8_t tsc2; 441 uint8_t reserved4; 442 uint16_t ttak[5]; 443 uint16_t reserved5; 444 uint8_t key[IEEE80211_KEYBUF_SIZE]; 445 uint32_t action; 446#define WPI_ACTION_SET_RATE (1 << 2) 447 448 uint32_t mask; 449 uint16_t tid; 450 uint8_t plcp; 451 uint8_t antenna; 452#define WPI_ANTENNA_A (1 << 6) 453#define WPI_ANTENNA_B (1 << 7) 454#define WPI_ANTENNA_BOTH (WPI_ANTENNA_A | WPI_ANTENNA_B) 455 456 uint8_t add_imm; 457 uint8_t del_imm; 458 uint16_t add_imm_start; 459} __packed; 460 461/* Structure for command WPI_CMD_DEL_NODE. */ 462struct wpi_cmd_del_node { 463 uint8_t count; 464 uint8_t reserved1[3]; 465 uint8_t macaddr[IEEE80211_ADDR_LEN]; 466 uint16_t reserved2; 467} __packed; 468 469/* Structure for command WPI_CMD_TX_DATA. */ 470struct wpi_cmd_data { 471 uint16_t len; 472 uint16_t lnext; 473 uint32_t flags; 474#define WPI_TX_NEED_RTS (1 << 1) 475#define WPI_TX_NEED_CTS (1 << 2) 476#define WPI_TX_NEED_ACK (1 << 3) 477#define WPI_TX_FULL_TXOP (1 << 7) 478#define WPI_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 479#define WPI_TX_AUTO_SEQ (1 << 13) 480#define WPI_TX_MORE_FRAG (1 << 14) 481#define WPI_TX_INSERT_TSTAMP (1 << 16) 482 483 uint8_t plcp; 484 uint8_t id; 485 uint8_t tid; 486 uint8_t security; 487#define WPI_CIPHER_WEP 1 488#define WPI_CIPHER_CCMP 2 489#define WPI_CIPHER_TKIP 3 490#define WPI_CIPHER_WEP104 9 491 492 uint8_t key[IEEE80211_KEYBUF_SIZE]; 493 uint8_t tkip[IEEE80211_WEP_MICLEN]; 494 uint32_t fnext; 495 uint32_t lifetime; 496#define WPI_LIFETIME_INFINITE 0xffffffff 497 498 uint8_t ofdm_mask; 499 uint8_t cck_mask; 500 uint8_t rts_ntries; 501 uint8_t data_ntries; 502 uint16_t timeout; 503 uint16_t txop; 504} __packed; 505 506/* Structure for command WPI_CMD_SET_BEACON. */ 507struct wpi_cmd_beacon { 508 uint16_t len; 509 uint16_t reserved1; 510 uint32_t flags; /* same as wpi_cmd_data */ 511 uint8_t plcp; 512 uint8_t id; 513 uint8_t reserved2[30]; 514 uint32_t lifetime; 515 uint8_t ofdm_mask; 516 uint8_t cck_mask; 517 uint16_t reserved3[3]; 518 uint16_t tim; 519 uint8_t timsz; 520 uint8_t reserved4; 521} __packed; 522 523/* Structure for notification WPI_BEACON_MISSED. */ 524struct wpi_beacon_missed { 525 uint32_t consecutive; 526 uint32_t total; 527 uint32_t expected; 528 uint32_t received; 529} __packed; 530 531 532/* Structure for command WPI_CMD_MRR_SETUP. */ 533#define WPI_RIDX_MAX 11 534struct wpi_mrr_setup { 535 uint32_t which; 536#define WPI_MRR_CTL 0 537#define WPI_MRR_DATA 1 538 539 struct { 540 uint8_t plcp; 541 uint8_t flags; 542 uint8_t ntries; 543 uint8_t next; 544 } __packed rates[WPI_RIDX_MAX + 1]; 545} __packed; 546 547/* Structure for command WPI_CMD_SET_LED. */ 548struct wpi_cmd_led { 549 uint32_t unit; /* multiplier (in usecs) */ 550 uint8_t which; 551#define WPI_LED_ACTIVITY 1 552#define WPI_LED_LINK 2 553 554 uint8_t off; 555 uint8_t on; 556 uint8_t reserved; 557} __packed; 558 559/* Structure for command WPI_CMD_SET_POWER_MODE. */ 560struct wpi_pmgt_cmd { 561 uint16_t flags; 562#define WPI_PS_ALLOW_SLEEP (1 << 0) 563#define WPI_PS_NOTIFY (1 << 1) 564#define WPI_PS_SLEEP_OVER_DTIM (1 << 2) 565#define WPI_PS_PCI_PMGT (1 << 3) 566 567 uint8_t reserved[2]; 568 uint32_t rxtimeout; 569 uint32_t txtimeout; 570 uint32_t intval[5]; 571} __packed; 572 573/* Structures for command WPI_CMD_SCAN. */ 574#define WPI_SCAN_MAX_ESSIDS 4 575struct wpi_scan_essid { 576 uint8_t id; 577 uint8_t len; 578 uint8_t data[IEEE80211_NWID_LEN]; 579} __packed; 580 581struct wpi_scan_hdr { 582 uint16_t len; 583 uint8_t reserved1; 584 uint8_t nchan; 585 uint16_t quiet_time; 586 uint16_t quiet_threshold; 587 uint16_t crc_threshold; 588 uint16_t reserved2; 589 uint32_t max_svc; /* background scans */ 590 uint32_t pause_svc; /* background scans */ 591 uint32_t flags; 592 uint32_t filter; 593 594 /* Followed by a struct wpi_cmd_data. */ 595 /* Followed by an array of 4 structs wpi_scan_essid. */ 596 /* Followed by probe request body. */ 597 /* Followed by an array of ``nchan'' structs wpi_scan_chan. */ 598} __packed; 599 600struct wpi_scan_chan { 601 uint8_t flags; 602#define WPI_CHAN_ACTIVE (1 << 0) 603#define WPI_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 604 605 uint8_t chan; 606 uint8_t rf_gain; 607 uint8_t dsp_gain; 608 uint16_t active; /* msecs */ 609 uint16_t passive; /* msecs */ 610} __packed; 611 612#define WPI_SCAN_CRC_TH_DEFAULT htole16(1) 613#define WPI_SCAN_CRC_TH_NEVER htole16(0xffff) 614 615/* Maximum size of a scan command. */ 616#define WPI_SCAN_MAXSZ (MCLBYTES - 4) 617 618#define WPI_ACTIVE_DWELL_TIME_2GHZ (30) /* all times in msec */ 619#define WPI_ACTIVE_DWELL_TIME_5GHZ (20) 620#define WPI_ACTIVE_DWELL_FACTOR_2GHZ ( 3) 621#define WPI_ACTIVE_DWELL_FACTOR_5GHZ ( 2) 622 623#define WPI_PASSIVE_DWELL_TIME_2GHZ ( 20) 624#define WPI_PASSIVE_DWELL_TIME_5GHZ ( 10) 625#define WPI_PASSIVE_DWELL_BASE (100) 626 627/* Structure for command WPI_CMD_TXPOWER. */ 628struct wpi_cmd_txpower { 629 uint8_t band; 630#define WPI_BAND_5GHZ 0 631#define WPI_BAND_2GHZ 1 632 633 uint8_t reserved; 634 uint16_t chan; 635 636 struct { 637 uint8_t plcp; 638 uint8_t rf_gain; 639 uint8_t dsp_gain; 640 uint8_t reserved; 641 } __packed rates[WPI_RIDX_MAX + 1]; 642 643} __packed; 644 645/* Structure for command WPI_CMD_BT_COEX. */ 646struct wpi_bluetooth { 647 uint8_t flags; 648#define WPI_BT_COEX_DISABLE 0 649#define WPI_BT_COEX_MODE_2WIRE 1 650#define WPI_BT_COEX_MODE_3WIRE 2 651#define WPI_BT_COEX_MODE_4WIRE 3 652 653 uint8_t lead_time; 654#define WPI_BT_LEAD_TIME_DEF 30 655 656 uint8_t max_kill; 657#define WPI_BT_MAX_KILL_DEF 5 658 659 uint8_t reserved; 660 uint32_t kill_ack; 661 uint32_t kill_cts; 662} __packed; 663 664/* Structure for WPI_UC_READY notification. */ 665struct wpi_ucode_info { 666 uint8_t minor; 667 uint8_t major; 668 uint16_t reserved1; 669 uint8_t revision[8]; 670 uint8_t type; 671 uint8_t subtype; 672 uint16_t reserved2; 673 uint32_t logptr; 674 uint32_t errptr; 675 uint32_t tstamp; 676 uint32_t valid; 677} __packed; 678 679/* Structure for WPI_START_SCAN notification. */ 680struct wpi_start_scan { 681 uint64_t tstamp; 682 uint32_t tbeacon; 683 uint8_t chan; 684 uint8_t band; 685 uint16_t reserved; 686 uint32_t status; 687} __packed; 688 689/* Structure for WPI_STOP_SCAN notification. */ 690struct wpi_stop_scan { 691 uint8_t nchan; 692 uint8_t status; 693 uint8_t reserved; 694 uint8_t chan; 695 uint64_t tsf; 696} __packed; 697 698/* Structures for WPI_{RX,BEACON}_STATISTICS notification. */ 699struct wpi_rx_phy_stats { 700 uint32_t ina; 701 uint32_t fina; 702 uint32_t bad_plcp; 703 uint32_t bad_crc32; 704 uint32_t overrun; 705 uint32_t eoverrun; 706 uint32_t good_crc32; 707 uint32_t fa; 708 uint32_t bad_fina_sync; 709 uint32_t sfd_timeout; 710 uint32_t fina_timeout; 711 uint32_t no_rts_ack; 712 uint32_t rxe_limit; 713 uint32_t ack; 714 uint32_t cts; 715} __packed; 716 717struct wpi_rx_general_stats { 718 uint32_t bad_cts; 719 uint32_t bad_ack; 720 uint32_t not_bss; 721 uint32_t filtered; 722 uint32_t bad_chan; 723} __packed; 724 725struct wpi_rx_stats { 726 struct wpi_rx_phy_stats ofdm; 727 struct wpi_rx_phy_stats cck; 728 struct wpi_rx_general_stats general; 729} __packed; 730 731struct wpi_tx_stats { 732 uint32_t preamble; 733 uint32_t rx_detected; 734 uint32_t bt_defer; 735 uint32_t bt_kill; 736 uint32_t short_len; 737 uint32_t cts_timeout; 738 uint32_t ack_timeout; 739 uint32_t exp_ack; 740 uint32_t ack; 741} __packed; 742 743struct wpi_general_stats { 744 uint32_t temp; 745 uint32_t burst_check; 746 uint32_t burst; 747 uint32_t reserved[4]; 748 uint32_t sleep; 749 uint32_t slot_out; 750 uint32_t slot_idle; 751 uint32_t ttl_tstamp; 752 uint32_t tx_ant_a; 753 uint32_t tx_ant_b; 754 uint32_t exec; 755 uint32_t probe; 756} __packed; 757 758struct wpi_stats { 759 uint32_t flags; 760 struct wpi_rx_stats rx; 761 struct wpi_tx_stats tx; 762 struct wpi_general_stats general; 763} __packed; 764 765/* Possible flags for command WPI_CMD_GET_STATISTICS. */ 766#define WPI_STATISTICS_BEACON_DISABLE (1 << 1) 767 768 769/* Firmware error dump entry. */ 770struct wpi_fw_dump { 771 uint32_t desc; 772 uint32_t time; 773 uint32_t blink[2]; 774 uint32_t ilink[2]; 775 uint32_t data; 776} __packed; 777 778/* Firmware image file header. */ 779struct wpi_firmware_hdr { 780 781#define WPI_FW_MINVERSION 2144 782#define WPI_FW_NAME "wpifw" 783 784 uint16_t driver; 785 uint8_t minor; 786 uint8_t major; 787 uint32_t rtextsz; 788 uint32_t rdatasz; 789 uint32_t itextsz; 790 uint32_t idatasz; 791 uint32_t btextsz; 792} __packed; 793 794#define WPI_FW_TEXT_MAXSZ ( 80 * 1024 ) 795#define WPI_FW_DATA_MAXSZ ( 32 * 1024 ) 796#define WPI_FW_BOOT_TEXT_MAXSZ 1024 797 798#define WPI_FW_UPDATED (1U << 31 ) 799 800/* 801 * Offsets into EEPROM. 802 */ 803#define WPI_EEPROM_MAC 0x015 804#define WPI_EEPROM_REVISION 0x035 805#define WPI_EEPROM_SKU_CAP 0x045 806#define WPI_EEPROM_TYPE 0x04a 807#define WPI_EEPROM_DOMAIN 0x060 808#define WPI_EEPROM_BAND1 0x063 809#define WPI_EEPROM_BAND2 0x072 810#define WPI_EEPROM_BAND3 0x080 811#define WPI_EEPROM_BAND4 0x08d 812#define WPI_EEPROM_BAND5 0x099 813#define WPI_EEPROM_POWER_GRP 0x100 814 815struct wpi_eeprom_chan { 816 uint8_t flags; 817#define WPI_EEPROM_CHAN_VALID (1 << 0) 818#define WPI_EEPROM_CHAN_IBSS (1 << 1) 819#define WPI_EEPROM_CHAN_ACTIVE (1 << 3) 820#define WPI_EEPROM_CHAN_RADAR (1 << 4) 821 822 int8_t maxpwr; 823} __packed; 824 825struct wpi_eeprom_sample { 826 uint8_t index; 827 int8_t power; 828 uint16_t volt; 829} __packed; 830 831#define WPI_POWER_GROUPS_COUNT 5 832struct wpi_eeprom_group { 833 struct wpi_eeprom_sample samples[5]; 834 int32_t coef[5]; 835 int32_t corr[5]; 836 int8_t maxpwr; 837 uint8_t chan; 838 int16_t temp; 839} __packed; 840 841#define WPI_CHAN_BANDS_COUNT 5 842#define WPI_MAX_CHAN_PER_BAND 14 843static const struct wpi_chan_band { 844 uint32_t addr; /* offset in EEPROM */ 845 uint8_t nchan; 846 uint8_t chan[WPI_MAX_CHAN_PER_BAND]; 847} wpi_bands[] = { 848 /* 20MHz channels, 2GHz band. */ 849 { WPI_EEPROM_BAND1, 14, 850 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 851 /* 20MHz channels, 5GHz band. */ 852 { WPI_EEPROM_BAND2, 13, 853 { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 854 { WPI_EEPROM_BAND3, 12, 855 { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 856 { WPI_EEPROM_BAND4, 11, 857 { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 858 { WPI_EEPROM_BAND5, 6, 859 { 145, 149, 153, 157, 161, 165 } } 860}; 861 862/* HW rate indices. */ 863#define WPI_RIDX_OFDM6 0 864#define WPI_RIDX_OFDM36 5 865#define WPI_RIDX_OFDM48 6 866#define WPI_RIDX_OFDM54 7 867#define WPI_RIDX_CCK1 8 868#define WPI_RIDX_CCK2 9 869#define WPI_RIDX_CCK11 11 870 871static const uint8_t wpi_ridx_to_plcp[] = { 872 /* OFDM: IEEE Std 802.11a-1999, pp. 14 Table 80 */ 873 /* R1-R4 (ral/ural is R4-R1) */ 874 0xd, 0xf, 0x5, 0x7, 0x9, 0xb, 0x1, 0x3, 875 /* CCK: device-dependent */ 876 10, 20, 55, 110 877}; 878 879#define WPI_MAX_PWR_INDEX 77 880 881/* 882 * RF Tx gain values from highest to lowest power (values obtained from 883 * the reference driver.) 884 */ 885static const uint8_t wpi_rf_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 886 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xbb, 0xbb, 0xbb, 887 0xbb, 0xf3, 0xf3, 0xf3, 0xf3, 0xf3, 0xd3, 0xd3, 0xb3, 0xb3, 0xb3, 888 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x73, 0xeb, 0xeb, 0xeb, 889 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xab, 0xab, 0xab, 0x8b, 890 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xc3, 0xc3, 0xc3, 0xc3, 0xa3, 891 0xa3, 0xa3, 0xa3, 0x83, 0x83, 0x83, 0x83, 0x63, 0x63, 0x63, 0x63, 892 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 0x03, 0x03, 0x03, 893 0x03 894}; 895 896static const uint8_t wpi_rf_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 897 0xfb, 0xfb, 0xfb, 0xdb, 0xdb, 0xbb, 0xbb, 0x9b, 0x9b, 0x7b, 0x7b, 898 0x7b, 0x7b, 0x5b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x1b, 0x1b, 899 0x1b, 0x73, 0x73, 0x73, 0x53, 0x53, 0x53, 0x53, 0x53, 0x33, 0x33, 900 0x33, 0x33, 0x13, 0x13, 0x13, 0x13, 0x13, 0xab, 0xab, 0xab, 0x8b, 901 0x8b, 0x8b, 0x8b, 0x6b, 0x6b, 0x6b, 0x6b, 0x4b, 0x4b, 0x4b, 0x4b, 902 0x2b, 0x2b, 0x2b, 0x2b, 0x0b, 0x0b, 0x0b, 0x0b, 0x83, 0x83, 0x63, 903 0x63, 0x63, 0x63, 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 904 0x03 905}; 906 907/* 908 * DSP pre-DAC gain values from highest to lowest power (values obtained 909 * from the reference driver.) 910 */ 911static const uint8_t wpi_dsp_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 912 0x7f, 0x7f, 0x7f, 0x7f, 0x7d, 0x6e, 0x69, 0x62, 0x7d, 0x73, 0x6c, 913 0x63, 0x77, 0x6f, 0x69, 0x61, 0x5c, 0x6a, 0x64, 0x78, 0x71, 0x6b, 914 0x7d, 0x77, 0x70, 0x6a, 0x65, 0x61, 0x5b, 0x6b, 0x79, 0x73, 0x6d, 915 0x7f, 0x79, 0x73, 0x6c, 0x66, 0x60, 0x5c, 0x6e, 0x68, 0x62, 0x74, 916 0x7d, 0x77, 0x71, 0x6b, 0x65, 0x60, 0x71, 0x6a, 0x66, 0x5f, 0x71, 917 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 918 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 919 0x5f 920}; 921 922static const uint8_t wpi_dsp_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 923 0x7f, 0x78, 0x72, 0x77, 0x65, 0x71, 0x66, 0x72, 0x67, 0x75, 0x6b, 924 0x63, 0x5c, 0x6c, 0x7d, 0x76, 0x6d, 0x66, 0x60, 0x5a, 0x68, 0x62, 925 0x5c, 0x76, 0x6f, 0x68, 0x7e, 0x79, 0x71, 0x69, 0x63, 0x76, 0x6f, 926 0x68, 0x62, 0x74, 0x6d, 0x66, 0x62, 0x5d, 0x71, 0x6b, 0x63, 0x78, 927 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 928 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x6b, 0x63, 0x78, 929 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 930 0x78 931}; 932 933/* 934 * Power saving settings (values obtained from the reference driver.) 935 */ 936#define WPI_NDTIMRANGES 2 937#define WPI_NPOWERLEVELS 6 938static const struct wpi_pmgt { 939 uint32_t rxtimeout; 940 uint32_t txtimeout; 941 uint32_t intval[5]; 942 int skip_dtim; 943} wpi_pmgt[WPI_NDTIMRANGES][WPI_NPOWERLEVELS] = { 944 /* DTIM <= 10 */ 945 { 946 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 947 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 948 { 200, 300, { 2, 4, 6, 7, 7 }, 0 }, /* PS level 2 */ 949 { 50, 100, { 2, 6, 9, 9, 10 }, 0 }, /* PS level 3 */ 950 { 50, 25, { 2, 7, 9, 9, 10 }, 1 }, /* PS level 4 */ 951 { 25, 25, { 4, 7, 10, 10, 10 }, 1 } /* PS level 5 */ 952 }, 953 /* DTIM >= 11 */ 954 { 955 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 956 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 957 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 958 { 50, 100, { 2, 6, 9, 9, -1 }, 0 }, /* PS level 3 */ 959 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 960 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 961 } 962}; 963 964/* Firmware errors. */ 965static const char * const wpi_fw_errmsg[] = { 966 "OK", 967 "FAIL", 968 "BAD_PARAM", 969 "BAD_CHECKSUM", 970 "NMI_INTERRUPT", 971 "SYSASSERT", 972 "FATAL_ERROR" 973}; 974 975#define WPI_READ(sc, reg) \ 976 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 977 978#define WPI_WRITE(sc, reg, val) \ 979 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 980 981#define WPI_WRITE_REGION_4(sc, offset, datap, count) \ 982 bus_space_write_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 983 (datap), (count)) 984 985#define WPI_SETBITS(sc, reg, mask) \ 986 WPI_WRITE(sc, reg, WPI_READ(sc, reg) | (mask)) 987 988#define WPI_CLRBITS(sc, reg, mask) \ 989 WPI_WRITE(sc, reg, WPI_READ(sc, reg) & ~(mask)) 990 991#define WPI_BARRIER_WRITE(sc) \ 992 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 993 BUS_SPACE_BARRIER_WRITE) 994 995#define WPI_BARRIER_READ_WRITE(sc) \ 996 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 997 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 998