if_wpireg.h revision 282392
1173362Sbenjsc/* $FreeBSD: head/sys/dev/wpi/if_wpireg.h 282392 2015-05-03 23:28:54Z adrian $ */ 2173362Sbenjsc 3173362Sbenjsc/*- 4173362Sbenjsc * Copyright (c) 2006,2007 5173362Sbenjsc * Damien Bergamini <damien.bergamini@free.fr> 6173362Sbenjsc * 7173362Sbenjsc * Permission to use, copy, modify, and distribute this software for any 8173362Sbenjsc * purpose with or without fee is hereby granted, provided that the above 9173362Sbenjsc * copyright notice and this permission notice appear in all copies. 10173362Sbenjsc * 11173362Sbenjsc * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12173362Sbenjsc * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13173362Sbenjsc * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14173362Sbenjsc * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15173362Sbenjsc * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16173362Sbenjsc * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17173362Sbenjsc * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18173362Sbenjsc */ 19173362Sbenjsc 20173362Sbenjsc#define WPI_TX_RING_COUNT 256 21278366Sadrian#define WPI_TX_RING_LOMARK 192 22278366Sadrian#define WPI_TX_RING_HIMARK 224 23280119Sadrian 24280119Sadrian#ifdef DIAGNOSTIC 25280119Sadrian#define WPI_RX_RING_COUNT_LOG 8 26280119Sadrian#else 27278366Sadrian#define WPI_RX_RING_COUNT_LOG 6 28280119Sadrian#endif 29280119Sadrian 30278366Sadrian#define WPI_RX_RING_COUNT (1 << WPI_RX_RING_COUNT_LOG) 31173362Sbenjsc 32278366Sadrian#define WPI_NTXQUEUES 8 33280058Sadrian#define WPI_DRV_NTXQUEUES 5 34280064Sadrian#define WPI_CMD_QUEUE_NUM 4 35280064Sadrian 36278366Sadrian#define WPI_NDMACHNLS 6 37278366Sadrian 38278366Sadrian/* Maximum scatter/gather. */ 39280059Sadrian#define WPI_MAX_SCATTER 4 40278366Sadrian 41173362Sbenjsc/* 42173362Sbenjsc * Rings must be aligned on a 16K boundary. 43173362Sbenjsc */ 44173362Sbenjsc#define WPI_RING_DMA_ALIGN 0x4000 45173362Sbenjsc 46278366Sadrian/* Maximum Rx buffer size. */ 47173362Sbenjsc#define WPI_RBUF_SIZE ( 3 * 1024 ) /* XXX 3000 but must be aligned */ 48173362Sbenjsc 49173362Sbenjsc/* 50173362Sbenjsc * Control and status registers. 51173362Sbenjsc */ 52278366Sadrian#define WPI_HW_IF_CONFIG 0x000 53278366Sadrian#define WPI_INT 0x008 54278366Sadrian#define WPI_INT_MASK 0x00c 55278366Sadrian#define WPI_FH_INT 0x010 56278366Sadrian#define WPI_GPIO_IN 0x018 57173362Sbenjsc#define WPI_RESET 0x020 58278366Sadrian#define WPI_GP_CNTRL 0x024 59278366Sadrian#define WPI_EEPROM 0x02c 60278366Sadrian#define WPI_EEPROM_GP 0x030 61278366Sadrian#define WPI_GIO 0x03c 62278366Sadrian#define WPI_UCODE_GP1 0x054 63278366Sadrian#define WPI_UCODE_GP1_SET 0x058 64278366Sadrian#define WPI_UCODE_GP1_CLR 0x05c 65278366Sadrian#define WPI_UCODE_GP2 0x060 66278366Sadrian#define WPI_GIO_CHICKEN 0x100 67278366Sadrian#define WPI_ANA_PLL 0x20c 68278366Sadrian#define WPI_DBG_HPET_MEM 0x240 69278366Sadrian#define WPI_MEM_RADDR 0x40c 70278366Sadrian#define WPI_MEM_WADDR 0x410 71278366Sadrian#define WPI_MEM_WDATA 0x418 72278366Sadrian#define WPI_MEM_RDATA 0x41c 73278366Sadrian#define WPI_PRPH_WADDR 0x444 74278366Sadrian#define WPI_PRPH_RADDR 0x448 75278366Sadrian#define WPI_PRPH_WDATA 0x44c 76278366Sadrian#define WPI_PRPH_RDATA 0x450 77278366Sadrian#define WPI_HBUS_TARG_WRPTR 0x460 78173362Sbenjsc 79278366Sadrian/* 80278366Sadrian * Flow-Handler registers. 81278366Sadrian */ 82278366Sadrian#define WPI_FH_CBBC_CTRL(qid) (0x940 + (qid) * 8) 83278366Sadrian#define WPI_FH_CBBC_BASE(qid) (0x944 + (qid) * 8) 84278366Sadrian#define WPI_FH_RX_CONFIG 0xc00 85278366Sadrian#define WPI_FH_RX_BASE 0xc04 86278366Sadrian#define WPI_FH_RX_WPTR 0xc20 87278366Sadrian#define WPI_FH_RX_RPTR_ADDR 0xc24 88278366Sadrian#define WPI_FH_RSSR_TBL 0xcc0 89278366Sadrian#define WPI_FH_RX_STATUS 0xcc4 90278366Sadrian#define WPI_FH_TX_CONFIG(qid) (0xd00 + (qid) * 32) 91278366Sadrian#define WPI_FH_TX_BASE 0xe80 92278366Sadrian#define WPI_FH_MSG_CONFIG 0xe88 93278366Sadrian#define WPI_FH_TX_STATUS 0xe90 94173362Sbenjsc 95278366Sadrian 96173362Sbenjsc/* 97173362Sbenjsc * NIC internal memory offsets. 98173362Sbenjsc */ 99278366Sadrian#define WPI_ALM_SCHED_MODE 0x2e00 100278366Sadrian#define WPI_ALM_SCHED_ARASTAT 0x2e04 101278366Sadrian#define WPI_ALM_SCHED_TXFACT 0x2e10 102278366Sadrian#define WPI_ALM_SCHED_TXF4MF 0x2e14 103278366Sadrian#define WPI_ALM_SCHED_TXF5MF 0x2e20 104278366Sadrian#define WPI_ALM_SCHED_SBYPASS_MODE1 0x2e2c 105278366Sadrian#define WPI_ALM_SCHED_SBYPASS_MODE2 0x2e30 106280093Sadrian#define WPI_APMG_CLK_CTRL 0x3000 107278366Sadrian#define WPI_APMG_CLK_EN 0x3004 108278366Sadrian#define WPI_APMG_CLK_DIS 0x3008 109278366Sadrian#define WPI_APMG_PS 0x300c 110278366Sadrian#define WPI_APMG_PCI_STT 0x3010 111278366Sadrian#define WPI_APMG_RFKILL 0x3014 112278366Sadrian#define WPI_BSM_WR_CTRL 0x3400 113278366Sadrian#define WPI_BSM_WR_MEM_SRC 0x3404 114278366Sadrian#define WPI_BSM_WR_MEM_DST 0x3408 115278366Sadrian#define WPI_BSM_WR_DWCOUNT 0x340c 116278366Sadrian#define WPI_BSM_DRAM_TEXT_ADDR 0x3490 117278366Sadrian#define WPI_BSM_DRAM_TEXT_SIZE 0x3494 118278366Sadrian#define WPI_BSM_DRAM_DATA_ADDR 0x3498 119278366Sadrian#define WPI_BSM_DRAM_DATA_SIZE 0x349c 120278366Sadrian#define WPI_BSM_SRAM_BASE 0x3800 121173362Sbenjsc 122173362Sbenjsc 123278366Sadrian/* Possible flags for register WPI_HW_IF_CONFIG. */ 124278366Sadrian#define WPI_HW_IF_CONFIG_ALM_MB (1 << 8) 125278366Sadrian#define WPI_HW_IF_CONFIG_ALM_MM (1 << 9) 126278366Sadrian#define WPI_HW_IF_CONFIG_SKU_MRC (1 << 10) 127278366Sadrian#define WPI_HW_IF_CONFIG_REV_D (1 << 11) 128278366Sadrian#define WPI_HW_IF_CONFIG_TYPE_B (1 << 12) 129173362Sbenjsc 130278366Sadrian/* Possible flags for registers WPI_PRPH_RADDR/WPI_PRPH_WADDR. */ 131278366Sadrian#define WPI_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 132173362Sbenjsc 133278366Sadrian/* Possible values for WPI_BSM_WR_MEM_DST. */ 134278366Sadrian#define WPI_FW_TEXT_BASE 0x00000000 135278366Sadrian#define WPI_FW_DATA_BASE 0x00800000 136173362Sbenjsc 137278366Sadrian/* Possible flags for WPI_GPIO_IN. */ 138278366Sadrian#define WPI_GPIO_IN_VMAIN (1 << 9) 139173362Sbenjsc 140278366Sadrian/* Possible flags for register WPI_RESET. */ 141278366Sadrian#define WPI_RESET_NEVO (1 << 0) 142278366Sadrian#define WPI_RESET_SW (1 << 7) 143278366Sadrian#define WPI_RESET_MASTER_DISABLED (1 << 8) 144278366Sadrian#define WPI_RESET_STOP_MASTER (1 << 9) 145173362Sbenjsc 146278366Sadrian/* Possible flags for register WPI_GP_CNTRL. */ 147278366Sadrian#define WPI_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 148278366Sadrian#define WPI_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 149278366Sadrian#define WPI_GP_CNTRL_INIT_DONE (1 << 2) 150278366Sadrian#define WPI_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 151278366Sadrian#define WPI_GP_CNTRL_SLEEP (1 << 4) 152278366Sadrian#define WPI_GP_CNTRL_PS_MASK (7 << 24) 153278366Sadrian#define WPI_GP_CNTRL_MAC_PS (4 << 24) 154278366Sadrian#define WPI_GP_CNTRL_RFKILL (1 << 27) 155173362Sbenjsc 156278366Sadrian/* Possible flags for register WPI_GIO_CHICKEN. */ 157278366Sadrian#define WPI_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 158278366Sadrian#define WPI_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 159173362Sbenjsc 160278366Sadrian/* Possible flags for register WPI_GIO. */ 161278366Sadrian#define WPI_GIO_L0S_ENA (1 << 1) 162173362Sbenjsc 163278366Sadrian/* Possible flags for register WPI_FH_RX_CONFIG. */ 164278366Sadrian#define WPI_FH_RX_CONFIG_DMA_ENA (1U << 31) 165278366Sadrian#define WPI_FH_RX_CONFIG_RDRBD_ENA (1 << 29) 166278366Sadrian#define WPI_FH_RX_CONFIG_WRSTATUS_ENA (1 << 27) 167278366Sadrian#define WPI_FH_RX_CONFIG_MAXFRAG (1 << 24) 168278366Sadrian#define WPI_FH_RX_CONFIG_NRBD(x) ((x) << 20) 169278366Sadrian#define WPI_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 170278366Sadrian#define WPI_FH_RX_CONFIG_IRQ_TIMEOUT(x) ((x) << 4) 171173362Sbenjsc 172278366Sadrian/* Possible flags for register WPI_ANA_PLL. */ 173278366Sadrian#define WPI_ANA_PLL_INIT (1 << 24) 174173362Sbenjsc 175278366Sadrian/* Possible flags for register WPI_UCODE_GP1*. */ 176278366Sadrian#define WPI_UCODE_GP1_MAC_SLEEP (1 << 0) 177278366Sadrian#define WPI_UCODE_GP1_RFKILL (1 << 1) 178278366Sadrian#define WPI_UCODE_GP1_CMD_BLOCKED (1 << 2) 179173362Sbenjsc 180278366Sadrian/* Possible flags for register WPI_FH_RX_STATUS. */ 181278366Sadrian#define WPI_FH_RX_STATUS_IDLE (1 << 24) 182173362Sbenjsc 183278366Sadrian/* Possible flags for register WPI_BSM_WR_CTRL. */ 184278366Sadrian#define WPI_BSM_WR_CTRL_START_EN (1 << 30) 185278366Sadrian#define WPI_BSM_WR_CTRL_START (1U << 31) 186173362Sbenjsc 187278366Sadrian/* Possible flags for register WPI_INT. */ 188278366Sadrian#define WPI_INT_ALIVE (1 << 0) 189278366Sadrian#define WPI_INT_WAKEUP (1 << 1) 190278366Sadrian#define WPI_INT_SW_RX (1 << 3) 191278366Sadrian#define WPI_INT_SW_ERR (1 << 25) 192278366Sadrian#define WPI_INT_FH_TX (1 << 27) 193278366Sadrian#define WPI_INT_HW_ERR (1 << 29) 194278366Sadrian#define WPI_INT_FH_RX (1U << 31) 195173362Sbenjsc 196278366Sadrian/* Shortcut. */ 197278366Sadrian#define WPI_INT_MASK_DEF \ 198278366Sadrian (WPI_INT_SW_ERR | WPI_INT_HW_ERR | WPI_INT_FH_TX | \ 199278366Sadrian WPI_INT_FH_RX | WPI_INT_ALIVE | WPI_INT_WAKEUP | \ 200278366Sadrian WPI_INT_SW_RX) 201173362Sbenjsc 202278366Sadrian/* Possible flags for register WPI_FH_INT. */ 203278366Sadrian#define WPI_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 204278366Sadrian#define WPI_FH_INT_HI_PRIOR (1 << 30) 205278366Sadrian/* Shortcuts for the above. */ 206278366Sadrian#define WPI_FH_INT_RX \ 207278366Sadrian (WPI_FH_INT_RX_CHNL(0) | \ 208278366Sadrian WPI_FH_INT_RX_CHNL(1) | \ 209278366Sadrian WPI_FH_INT_RX_CHNL(2) | \ 210278366Sadrian WPI_FH_INT_HI_PRIOR) 211173362Sbenjsc 212278366Sadrian/* Possible flags for register WPI_FH_TX_STATUS. */ 213278366Sadrian#define WPI_FH_TX_STATUS_IDLE(qid) \ 214278366Sadrian (1 << ((qid) + 24) | 1 << ((qid) + 16)) 215278366Sadrian 216278366Sadrian/* Possible flags for register WPI_EEPROM. */ 217278366Sadrian#define WPI_EEPROM_READ_VALID (1 << 0) 218278366Sadrian 219278366Sadrian/* Possible flags for register WPI_EEPROM_GP. */ 220173362Sbenjsc#define WPI_EEPROM_VERSION 0x00000007 221278366Sadrian#define WPI_EEPROM_GP_IF_OWNER 0x00000180 222173362Sbenjsc 223278366Sadrian/* Possible flags for register WPI_APMG_PS. */ 224278366Sadrian#define WPI_APMG_PS_PWR_SRC_MASK (3 << 24) 225173362Sbenjsc 226278366Sadrian/* Possible flags for registers WPI_APMG_CLK_*. */ 227278366Sadrian#define WPI_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 228278366Sadrian#define WPI_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 229278366Sadrian 230278366Sadrian/* Possible flags for register WPI_APMG_PCI_STT. */ 231278366Sadrian#define WPI_APMG_PCI_STT_L1A_DIS (1 << 11) 232278366Sadrian 233173362Sbenjscstruct wpi_shared { 234280064Sadrian uint32_t txbase[WPI_NTXQUEUES]; 235173362Sbenjsc uint32_t next; 236173362Sbenjsc uint32_t reserved[2]; 237173362Sbenjsc} __packed; 238173362Sbenjsc 239173362Sbenjsc#define WPI_MAX_SEG_LEN 65520 240173362Sbenjscstruct wpi_tx_desc { 241278366Sadrian uint8_t reserved1[3]; 242278366Sadrian uint8_t nsegs; 243173362Sbenjsc#define WPI_PAD32(x) (roundup2(x, 4) - (x)) 244173362Sbenjsc 245173362Sbenjsc struct { 246173362Sbenjsc uint32_t addr; 247173362Sbenjsc uint32_t len; 248278366Sadrian } __packed segs[WPI_MAX_SCATTER]; 249278366Sadrian uint8_t reserved2[28]; 250173362Sbenjsc} __packed; 251173362Sbenjsc 252173362Sbenjscstruct wpi_tx_stat { 253278366Sadrian uint8_t rtsfailcnt; 254278366Sadrian uint8_t ackfailcnt; 255278366Sadrian uint8_t btkillcnt; 256173362Sbenjsc uint8_t rate; 257173362Sbenjsc uint32_t duration; 258173362Sbenjsc uint32_t status; 259282378Sadrian#define WPI_TX_STATUS_SUCCESS 0x01 260282378Sadrian#define WPI_TX_STATUS_DIRECT_DONE 0x02 261282378Sadrian#define WPI_TX_STATUS_FAIL 0x80 262282378Sadrian#define WPI_TX_STATUS_FAIL_SHORT_LIMIT 0x82 263282378Sadrian#define WPI_TX_STATUS_FAIL_LONG_LIMIT 0x83 264282378Sadrian#define WPI_TX_STATUS_FAIL_FIFO_UNDERRUN 0x84 265282378Sadrian#define WPI_TX_STATUS_FAIL_MGMNT_ABORT 0x85 266282378Sadrian#define WPI_TX_STATUS_FAIL_NEXT_FRAG 0x86 267282378Sadrian#define WPI_TX_STATUS_FAIL_LIFE_EXPIRE 0x87 268282378Sadrian#define WPI_TX_STATUS_FAIL_NODE_PS 0x88 269282378Sadrian#define WPI_TX_STATUS_FAIL_ABORTED 0x89 270282378Sadrian#define WPI_TX_STATUS_FAIL_BT_RETRY 0x8a 271282378Sadrian#define WPI_TX_STATUS_FAIL_NODE_INVALID 0x8b 272282378Sadrian#define WPI_TX_STATUS_FAIL_FRAG_DROPPED 0x8c 273282378Sadrian#define WPI_TX_STATUS_FAIL_TID_DISABLE 0x8d 274282378Sadrian#define WPI_TX_STATUS_FAIL_FRAME_FLUSHED 0x8e 275282378Sadrian#define WPI_TX_STATUS_FAIL_INSUFFICIENT_CF_POLL 0x8f 276282378Sadrian#define WPI_TX_STATUS_FAIL_TX_LOCKED 0x90 277282378Sadrian#define WPI_TX_STATUS_FAIL_NO_BEACON_ON_RADAR 0x91 278282378Sadrian 279173362Sbenjsc} __packed; 280173362Sbenjsc 281173362Sbenjscstruct wpi_rx_desc { 282173362Sbenjsc uint32_t len; 283173362Sbenjsc uint8_t type; 284173362Sbenjsc#define WPI_UC_READY 1 285173362Sbenjsc#define WPI_RX_DONE 27 286173362Sbenjsc#define WPI_TX_DONE 28 287173362Sbenjsc#define WPI_START_SCAN 130 288177043Sthompsa#define WPI_SCAN_RESULTS 131 289173362Sbenjsc#define WPI_STOP_SCAN 132 290278366Sadrian#define WPI_BEACON_SENT 144 291278366Sadrian#define WPI_RX_STATISTICS 156 292278366Sadrian#define WPI_BEACON_STATISTICS 157 293173362Sbenjsc#define WPI_STATE_CHANGED 161 294278366Sadrian#define WPI_BEACON_MISSED 162 295173362Sbenjsc 296173362Sbenjsc uint8_t flags; 297173362Sbenjsc uint8_t idx; 298173362Sbenjsc uint8_t qid; 299173362Sbenjsc} __packed; 300173362Sbenjsc 301280064Sadrian#define WPI_RX_DESC_QID_MSK 0x07 302280064Sadrian#define WPI_UNSOLICITED_RX_NOTIF 0x80 303280064Sadrian 304173362Sbenjscstruct wpi_rx_stat { 305173362Sbenjsc uint8_t len; 306173362Sbenjsc#define WPI_STAT_MAXLEN 20 307173362Sbenjsc 308173362Sbenjsc uint8_t id; 309173362Sbenjsc uint8_t rssi; /* received signal strength */ 310280064Sadrian#define WPI_RSSI_OFFSET -95 311173362Sbenjsc 312173362Sbenjsc uint8_t agc; /* access gain control */ 313173362Sbenjsc uint16_t signal; 314173362Sbenjsc uint16_t noise; 315173362Sbenjsc} __packed; 316173362Sbenjsc 317173362Sbenjscstruct wpi_rx_head { 318173362Sbenjsc uint16_t chan; 319173362Sbenjsc uint16_t flags; 320278366Sadrian#define WPI_STAT_FLAG_SHPREAMBLE (1 << 2) 321278366Sadrian 322173362Sbenjsc uint8_t reserved; 323278366Sadrian uint8_t plcp; 324173362Sbenjsc uint16_t len; 325173362Sbenjsc} __packed; 326173362Sbenjsc 327173362Sbenjscstruct wpi_rx_tail { 328173362Sbenjsc uint32_t flags; 329173362Sbenjsc#define WPI_RX_NO_CRC_ERR (1 << 0) 330173362Sbenjsc#define WPI_RX_NO_OVFL_ERR (1 << 1) 331173362Sbenjsc/* shortcut for the above */ 332173362Sbenjsc#define WPI_RX_NOERROR (WPI_RX_NO_CRC_ERR | WPI_RX_NO_OVFL_ERR) 333278366Sadrian#define WPI_RX_CIPHER_MASK (7 << 8) 334278366Sadrian#define WPI_RX_CIPHER_CCMP (2 << 8) 335278366Sadrian#define WPI_RX_DECRYPT_MASK (3 << 11) 336278366Sadrian#define WPI_RX_DECRYPT_OK (3 << 11) 337278366Sadrian 338173362Sbenjsc uint64_t tstamp; 339173362Sbenjsc uint32_t tbeacon; 340173362Sbenjsc} __packed; 341173362Sbenjsc 342173362Sbenjscstruct wpi_tx_cmd { 343173362Sbenjsc uint8_t code; 344278366Sadrian#define WPI_CMD_RXON 16 345278366Sadrian#define WPI_CMD_RXON_ASSOC 17 346278366Sadrian#define WPI_CMD_EDCA_PARAMS 19 347278366Sadrian#define WPI_CMD_TIMING 20 348173362Sbenjsc#define WPI_CMD_ADD_NODE 24 349278366Sadrian#define WPI_CMD_DEL_NODE 25 350173362Sbenjsc#define WPI_CMD_TX_DATA 28 351173362Sbenjsc#define WPI_CMD_MRR_SETUP 71 352173362Sbenjsc#define WPI_CMD_SET_LED 72 353173362Sbenjsc#define WPI_CMD_SET_POWER_MODE 119 354173362Sbenjsc#define WPI_CMD_SCAN 128 355282392Sadrian#define WPI_CMD_SCAN_ABORT 129 356173362Sbenjsc#define WPI_CMD_SET_BEACON 145 357173362Sbenjsc#define WPI_CMD_TXPOWER 151 358278366Sadrian#define WPI_CMD_BT_COEX 155 359278366Sadrian#define WPI_CMD_GET_STATISTICS 156 360173362Sbenjsc 361173362Sbenjsc uint8_t flags; 362173362Sbenjsc uint8_t idx; 363173362Sbenjsc uint8_t qid; 364278366Sadrian uint8_t data[124]; 365173362Sbenjsc} __packed; 366173362Sbenjsc 367278366Sadrian/* Structure for command WPI_CMD_RXON. */ 368278366Sadrianstruct wpi_rxon { 369173362Sbenjsc uint8_t myaddr[IEEE80211_ADDR_LEN]; 370173362Sbenjsc uint16_t reserved1; 371173362Sbenjsc uint8_t bssid[IEEE80211_ADDR_LEN]; 372173362Sbenjsc uint16_t reserved2; 373278366Sadrian uint8_t wlap[IEEE80211_ADDR_LEN]; 374173362Sbenjsc uint16_t reserved3; 375173362Sbenjsc uint8_t mode; 376173362Sbenjsc#define WPI_MODE_HOSTAP 1 377173362Sbenjsc#define WPI_MODE_STA 3 378173362Sbenjsc#define WPI_MODE_IBSS 4 379173362Sbenjsc#define WPI_MODE_MONITOR 6 380173362Sbenjsc 381278366Sadrian uint8_t air; 382173362Sbenjsc uint16_t reserved4; 383173362Sbenjsc uint8_t ofdm_mask; 384173362Sbenjsc uint8_t cck_mask; 385173362Sbenjsc uint16_t associd; 386173362Sbenjsc uint32_t flags; 387278366Sadrian#define WPI_RXON_24GHZ (1 << 0) 388278366Sadrian#define WPI_RXON_CCK (1 << 1) 389278366Sadrian#define WPI_RXON_AUTO (1 << 2) 390278366Sadrian#define WPI_RXON_SHSLOT (1 << 4) 391278366Sadrian#define WPI_RXON_SHPREAMBLE (1 << 5) 392278366Sadrian#define WPI_RXON_NODIVERSITY (1 << 7) 393278366Sadrian#define WPI_RXON_ANTENNA_A (1 << 8) 394278366Sadrian#define WPI_RXON_ANTENNA_B (1 << 9) 395278366Sadrian#define WPI_RXON_TSF (1 << 15) 396278366Sadrian#define WPI_RXON_CTS_TO_SELF (1 << 30) 397173362Sbenjsc 398173362Sbenjsc uint32_t filter; 399173362Sbenjsc#define WPI_FILTER_PROMISC (1 << 0) 400173362Sbenjsc#define WPI_FILTER_CTL (1 << 1) 401173362Sbenjsc#define WPI_FILTER_MULTICAST (1 << 2) 402173362Sbenjsc#define WPI_FILTER_NODECRYPT (1 << 3) 403173362Sbenjsc#define WPI_FILTER_BSS (1 << 5) 404173362Sbenjsc#define WPI_FILTER_BEACON (1 << 6) 405280105Sadrian#define WPI_FILTER_ASSOC (1 << 7) /* Accept associaton requests. */ 406173362Sbenjsc 407173362Sbenjsc uint8_t chan; 408278366Sadrian uint16_t reserved5; 409173362Sbenjsc} __packed; 410173362Sbenjsc 411278366Sadrian/* Structure for command WPI_CMD_RXON_ASSOC. */ 412173362Sbenjscstruct wpi_assoc { 413173362Sbenjsc uint32_t flags; 414173362Sbenjsc uint32_t filter; 415173362Sbenjsc uint8_t ofdm_mask; 416173362Sbenjsc uint8_t cck_mask; 417173362Sbenjsc uint16_t reserved; 418173362Sbenjsc} __packed; 419173362Sbenjsc 420278366Sadrian/* Structure for command WPI_CMD_EDCA_PARAMS. */ 421278366Sadrianstruct wpi_edca_params { 422173362Sbenjsc uint32_t flags; 423278366Sadrian#define WPI_EDCA_UPDATE (1 << 0) 424278366Sadrian 425173362Sbenjsc struct { 426173362Sbenjsc uint16_t cwmin; 427173362Sbenjsc uint16_t cwmax; 428173362Sbenjsc uint8_t aifsn; 429173362Sbenjsc uint8_t reserved; 430278366Sadrian uint16_t txoplimit; 431173362Sbenjsc } __packed ac[WME_NUM_AC]; 432173362Sbenjsc} __packed; 433173362Sbenjsc 434278366Sadrian/* Structure for command WPI_CMD_TIMING. */ 435278366Sadrianstruct wpi_cmd_timing { 436173362Sbenjsc uint64_t tstamp; 437173362Sbenjsc uint16_t bintval; 438173362Sbenjsc uint16_t atim; 439173362Sbenjsc uint32_t binitval; 440173362Sbenjsc uint16_t lintval; 441173362Sbenjsc uint16_t reserved; 442173362Sbenjsc} __packed; 443173362Sbenjsc 444278366Sadrian/* Structure for command WPI_CMD_ADD_NODE. */ 445173362Sbenjscstruct wpi_node_info { 446173362Sbenjsc uint8_t control; 447278366Sadrian#define WPI_NODE_UPDATE (1 << 0) 448173362Sbenjsc 449173362Sbenjsc uint8_t reserved1[3]; 450278366Sadrian uint8_t macaddr[IEEE80211_ADDR_LEN]; 451173362Sbenjsc uint16_t reserved2; 452173362Sbenjsc uint8_t id; 453173362Sbenjsc#define WPI_ID_BSS 0 454278366Sadrian#define WPI_ID_IBSS_MIN 2 455278366Sadrian#define WPI_ID_IBSS_MAX 23 456173362Sbenjsc#define WPI_ID_BROADCAST 24 457278366Sadrian#define WPI_ID_UNDEFINED (uint8_t)-1 458173362Sbenjsc 459173362Sbenjsc uint8_t flags; 460278366Sadrian#define WPI_FLAG_KEY_SET (1 << 0) 461278366Sadrian 462173362Sbenjsc uint16_t reserved3; 463278366Sadrian uint16_t kflags; 464278366Sadrian#define WPI_KFLAG_CCMP (1 << 1) 465278366Sadrian#define WPI_KFLAG_KID(kid) ((kid) << 8) 466278366Sadrian#define WPI_KFLAG_MULTICAST (1 << 14) 467278366Sadrian 468278366Sadrian uint8_t tsc2; 469173362Sbenjsc uint8_t reserved4; 470173362Sbenjsc uint16_t ttak[5]; 471173362Sbenjsc uint16_t reserved5; 472173362Sbenjsc uint8_t key[IEEE80211_KEYBUF_SIZE]; 473173362Sbenjsc uint32_t action; 474278366Sadrian#define WPI_ACTION_SET_RATE (1 << 2) 475278366Sadrian 476173362Sbenjsc uint32_t mask; 477173362Sbenjsc uint16_t tid; 478278366Sadrian uint8_t plcp; 479173362Sbenjsc uint8_t antenna; 480278366Sadrian#define WPI_ANTENNA_A (1 << 6) 481278366Sadrian#define WPI_ANTENNA_B (1 << 7) 482278366Sadrian#define WPI_ANTENNA_BOTH (WPI_ANTENNA_A | WPI_ANTENNA_B) 483278366Sadrian 484173362Sbenjsc uint8_t add_imm; 485173362Sbenjsc uint8_t del_imm; 486173362Sbenjsc uint16_t add_imm_start; 487173362Sbenjsc} __packed; 488173362Sbenjsc 489278366Sadrian/* Structure for command WPI_CMD_DEL_NODE. */ 490278366Sadrianstruct wpi_cmd_del_node { 491278366Sadrian uint8_t count; 492278366Sadrian uint8_t reserved1[3]; 493278366Sadrian uint8_t macaddr[IEEE80211_ADDR_LEN]; 494278366Sadrian uint16_t reserved2; 495278366Sadrian} __packed; 496278366Sadrian 497278366Sadrian/* Structure for command WPI_CMD_TX_DATA. */ 498173362Sbenjscstruct wpi_cmd_data { 499173362Sbenjsc uint16_t len; 500173362Sbenjsc uint16_t lnext; 501173362Sbenjsc uint32_t flags; 502173362Sbenjsc#define WPI_TX_NEED_RTS (1 << 1) 503280059Sadrian#define WPI_TX_NEED_CTS (1 << 2) 504173362Sbenjsc#define WPI_TX_NEED_ACK (1 << 3) 505173362Sbenjsc#define WPI_TX_FULL_TXOP (1 << 7) 506278366Sadrian#define WPI_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 507173362Sbenjsc#define WPI_TX_AUTO_SEQ (1 << 13) 508278764Sadrian#define WPI_TX_MORE_FRAG (1 << 14) 509173362Sbenjsc#define WPI_TX_INSERT_TSTAMP (1 << 16) 510173362Sbenjsc 511278366Sadrian uint8_t plcp; 512173362Sbenjsc uint8_t id; 513173362Sbenjsc uint8_t tid; 514173362Sbenjsc uint8_t security; 515278366Sadrian#define WPI_CIPHER_WEP 1 516278366Sadrian#define WPI_CIPHER_CCMP 2 517278366Sadrian#define WPI_CIPHER_TKIP 3 518278366Sadrian#define WPI_CIPHER_WEP104 9 519278366Sadrian 520173362Sbenjsc uint8_t key[IEEE80211_KEYBUF_SIZE]; 521173362Sbenjsc uint8_t tkip[IEEE80211_WEP_MICLEN]; 522173362Sbenjsc uint32_t fnext; 523173362Sbenjsc uint32_t lifetime; 524173362Sbenjsc#define WPI_LIFETIME_INFINITE 0xffffffff 525278366Sadrian 526173362Sbenjsc uint8_t ofdm_mask; 527173362Sbenjsc uint8_t cck_mask; 528173362Sbenjsc uint8_t rts_ntries; 529173362Sbenjsc uint8_t data_ntries; 530173362Sbenjsc uint16_t timeout; 531173362Sbenjsc uint16_t txop; 532173362Sbenjsc} __packed; 533173362Sbenjsc 534278366Sadrian/* Structure for command WPI_CMD_SET_BEACON. */ 535173362Sbenjscstruct wpi_cmd_beacon { 536173362Sbenjsc uint16_t len; 537173362Sbenjsc uint16_t reserved1; 538173362Sbenjsc uint32_t flags; /* same as wpi_cmd_data */ 539278366Sadrian uint8_t plcp; 540173362Sbenjsc uint8_t id; 541173362Sbenjsc uint8_t reserved2[30]; 542173362Sbenjsc uint32_t lifetime; 543173362Sbenjsc uint8_t ofdm_mask; 544173362Sbenjsc uint8_t cck_mask; 545173362Sbenjsc uint16_t reserved3[3]; 546173362Sbenjsc uint16_t tim; 547173362Sbenjsc uint8_t timsz; 548173362Sbenjsc uint8_t reserved4; 549173362Sbenjsc} __packed; 550173362Sbenjsc 551278366Sadrian/* Structure for notification WPI_BEACON_MISSED. */ 552278366Sadrianstruct wpi_beacon_missed { 553280059Sadrian uint32_t consecutive; 554280059Sadrian uint32_t total; 555280059Sadrian uint32_t expected; 556280059Sadrian uint32_t received; 557173976Sbenjsc} __packed; 558173976Sbenjsc 559173976Sbenjsc 560278366Sadrian/* Structure for command WPI_CMD_MRR_SETUP. */ 561278366Sadrian#define WPI_RIDX_MAX 11 562173362Sbenjscstruct wpi_mrr_setup { 563278366Sadrian uint32_t which; 564173362Sbenjsc#define WPI_MRR_CTL 0 565173362Sbenjsc#define WPI_MRR_DATA 1 566173362Sbenjsc 567173362Sbenjsc struct { 568278366Sadrian uint8_t plcp; 569173362Sbenjsc uint8_t flags; 570173362Sbenjsc uint8_t ntries; 571282369Sadrian#define WPI_NTRIES_DEFAULT 2 572282369Sadrian 573173362Sbenjsc uint8_t next; 574278366Sadrian } __packed rates[WPI_RIDX_MAX + 1]; 575173362Sbenjsc} __packed; 576173362Sbenjsc 577278366Sadrian/* Structure for command WPI_CMD_SET_LED. */ 578173362Sbenjscstruct wpi_cmd_led { 579173362Sbenjsc uint32_t unit; /* multiplier (in usecs) */ 580173362Sbenjsc uint8_t which; 581173362Sbenjsc#define WPI_LED_ACTIVITY 1 582173362Sbenjsc#define WPI_LED_LINK 2 583173362Sbenjsc 584173362Sbenjsc uint8_t off; 585173362Sbenjsc uint8_t on; 586173362Sbenjsc uint8_t reserved; 587173362Sbenjsc} __packed; 588173362Sbenjsc 589278366Sadrian/* Structure for command WPI_CMD_SET_POWER_MODE. */ 590278366Sadrianstruct wpi_pmgt_cmd { 591278366Sadrian uint16_t flags; 592278366Sadrian#define WPI_PS_ALLOW_SLEEP (1 << 0) 593278366Sadrian#define WPI_PS_NOTIFY (1 << 1) 594278366Sadrian#define WPI_PS_SLEEP_OVER_DTIM (1 << 2) 595278366Sadrian#define WPI_PS_PCI_PMGT (1 << 3) 596278366Sadrian 597278366Sadrian uint8_t reserved[2]; 598278366Sadrian uint32_t rxtimeout; 599278366Sadrian uint32_t txtimeout; 600278366Sadrian uint32_t intval[5]; 601173362Sbenjsc} __packed; 602173362Sbenjsc 603278366Sadrian/* Structures for command WPI_CMD_SCAN. */ 604278366Sadrian#define WPI_SCAN_MAX_ESSIDS 4 605278366Sadrianstruct wpi_scan_essid { 606278366Sadrian uint8_t id; 607278366Sadrian uint8_t len; 608278366Sadrian uint8_t data[IEEE80211_NWID_LEN]; 609278366Sadrian} __packed; 610278366Sadrian 611173362Sbenjscstruct wpi_scan_hdr { 612173362Sbenjsc uint16_t len; 613173362Sbenjsc uint8_t reserved1; 614173362Sbenjsc uint8_t nchan; 615282382Sadrian uint16_t quiet_time; /* timeout in milliseconds */ 616282382Sadrian#define WPI_QUIET_TIME_DEFAULT 10 617282382Sadrian 618282382Sadrian uint16_t quiet_threshold; /* min # of packets */ 619278366Sadrian uint16_t crc_threshold; 620173362Sbenjsc uint16_t reserved2; 621278366Sadrian uint32_t max_svc; /* background scans */ 622278366Sadrian uint32_t pause_svc; /* background scans */ 623282383Sadrian#define WPI_PAUSE_MAX_TIME ((1 << 20) - 1) 624282383Sadrian#define WPI_PAUSE_SCAN(nbeacons, time) ((nbeacons << 24) | time) 625282383Sadrian 626173362Sbenjsc uint32_t flags; 627173362Sbenjsc uint32_t filter; 628173362Sbenjsc 629278366Sadrian /* Followed by a struct wpi_cmd_data. */ 630278366Sadrian /* Followed by an array of 4 structs wpi_scan_essid. */ 631278366Sadrian /* Followed by probe request body. */ 632278366Sadrian /* Followed by an array of ``nchan'' structs wpi_scan_chan. */ 633173362Sbenjsc} __packed; 634173362Sbenjsc 635173362Sbenjscstruct wpi_scan_chan { 636173362Sbenjsc uint8_t flags; 637278366Sadrian#define WPI_CHAN_ACTIVE (1 << 0) 638278366Sadrian#define WPI_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 639278366Sadrian 640173362Sbenjsc uint8_t chan; 641278366Sadrian uint8_t rf_gain; 642278366Sadrian uint8_t dsp_gain; 643173362Sbenjsc uint16_t active; /* msecs */ 644173362Sbenjsc uint16_t passive; /* msecs */ 645173362Sbenjsc} __packed; 646173362Sbenjsc 647278366Sadrian#define WPI_SCAN_CRC_TH_DEFAULT htole16(1) 648278366Sadrian#define WPI_SCAN_CRC_TH_NEVER htole16(0xffff) 649173362Sbenjsc 650278366Sadrian/* Maximum size of a scan command. */ 651278366Sadrian#define WPI_SCAN_MAXSZ (MCLBYTES - 4) 652278366Sadrian 653278366Sadrian#define WPI_ACTIVE_DWELL_TIME_2GHZ (30) /* all times in msec */ 654278366Sadrian#define WPI_ACTIVE_DWELL_TIME_5GHZ (20) 655278366Sadrian#define WPI_ACTIVE_DWELL_FACTOR_2GHZ ( 3) 656278366Sadrian#define WPI_ACTIVE_DWELL_FACTOR_5GHZ ( 2) 657278366Sadrian 658278366Sadrian#define WPI_PASSIVE_DWELL_TIME_2GHZ ( 20) 659278366Sadrian#define WPI_PASSIVE_DWELL_TIME_5GHZ ( 10) 660278366Sadrian#define WPI_PASSIVE_DWELL_BASE (100) 661282382Sadrian#define WPI_CHANNEL_TUNE_TIME ( 6) 662278366Sadrian 663278366Sadrian/* Structure for command WPI_CMD_TXPOWER. */ 664173362Sbenjscstruct wpi_cmd_txpower { 665278366Sadrian uint8_t band; 666278366Sadrian#define WPI_BAND_5GHZ 0 667278366Sadrian#define WPI_BAND_2GHZ 1 668173362Sbenjsc 669173362Sbenjsc uint8_t reserved; 670278366Sadrian uint16_t chan; 671173362Sbenjsc 672173362Sbenjsc struct { 673278366Sadrian uint8_t plcp; 674278366Sadrian uint8_t rf_gain; 675278366Sadrian uint8_t dsp_gain; 676278366Sadrian uint8_t reserved; 677278366Sadrian } __packed rates[WPI_RIDX_MAX + 1]; 678173362Sbenjsc 679173362Sbenjsc} __packed; 680173362Sbenjsc 681278366Sadrian/* Structure for command WPI_CMD_BT_COEX. */ 682278366Sadrianstruct wpi_bluetooth { 683278366Sadrian uint8_t flags; 684278366Sadrian#define WPI_BT_COEX_DISABLE 0 685278366Sadrian#define WPI_BT_COEX_MODE_2WIRE 1 686278366Sadrian#define WPI_BT_COEX_MODE_3WIRE 2 687278366Sadrian#define WPI_BT_COEX_MODE_4WIRE 3 688173362Sbenjsc 689278366Sadrian uint8_t lead_time; 690278366Sadrian#define WPI_BT_LEAD_TIME_DEF 30 691173362Sbenjsc 692278366Sadrian uint8_t max_kill; 693278366Sadrian#define WPI_BT_MAX_KILL_DEF 5 694173362Sbenjsc 695278366Sadrian uint8_t reserved; 696278366Sadrian uint32_t kill_ack; 697278366Sadrian uint32_t kill_cts; 698173362Sbenjsc} __packed; 699173362Sbenjsc 700278366Sadrian/* Structure for WPI_UC_READY notification. */ 701173362Sbenjscstruct wpi_ucode_info { 702278366Sadrian uint8_t minor; 703278366Sadrian uint8_t major; 704278366Sadrian uint16_t reserved1; 705173362Sbenjsc uint8_t revision[8]; 706173362Sbenjsc uint8_t type; 707173362Sbenjsc uint8_t subtype; 708278366Sadrian uint16_t reserved2; 709173362Sbenjsc uint32_t logptr; 710278366Sadrian uint32_t errptr; 711278366Sadrian uint32_t tstamp; 712173362Sbenjsc uint32_t valid; 713173362Sbenjsc} __packed; 714173362Sbenjsc 715278366Sadrian/* Structure for WPI_START_SCAN notification. */ 716173362Sbenjscstruct wpi_start_scan { 717173362Sbenjsc uint64_t tstamp; 718173362Sbenjsc uint32_t tbeacon; 719173362Sbenjsc uint8_t chan; 720173362Sbenjsc uint8_t band; 721173362Sbenjsc uint16_t reserved; 722173362Sbenjsc uint32_t status; 723173362Sbenjsc} __packed; 724173362Sbenjsc 725278366Sadrian/* Structure for WPI_STOP_SCAN notification. */ 726173362Sbenjscstruct wpi_stop_scan { 727173362Sbenjsc uint8_t nchan; 728173362Sbenjsc uint8_t status; 729282392Sadrian#define WPI_SCAN_COMPLETED 1 730282392Sadrian#define WPI_SCAN_ABORTED 2 731282392Sadrian 732173362Sbenjsc uint8_t reserved; 733173362Sbenjsc uint8_t chan; 734173362Sbenjsc uint64_t tsf; 735173362Sbenjsc} __packed; 736173362Sbenjsc 737278366Sadrian/* Structures for WPI_{RX,BEACON}_STATISTICS notification. */ 738278366Sadrianstruct wpi_rx_phy_stats { 739278366Sadrian uint32_t ina; 740278366Sadrian uint32_t fina; 741278366Sadrian uint32_t bad_plcp; 742278366Sadrian uint32_t bad_crc32; 743278366Sadrian uint32_t overrun; 744278366Sadrian uint32_t eoverrun; 745278366Sadrian uint32_t good_crc32; 746278366Sadrian uint32_t fa; 747278366Sadrian uint32_t bad_fina_sync; 748278366Sadrian uint32_t sfd_timeout; 749278366Sadrian uint32_t fina_timeout; 750278366Sadrian uint32_t no_rts_ack; 751278366Sadrian uint32_t rxe_limit; 752278366Sadrian uint32_t ack; 753278366Sadrian uint32_t cts; 754278366Sadrian} __packed; 755278366Sadrian 756278366Sadrianstruct wpi_rx_general_stats { 757278366Sadrian uint32_t bad_cts; 758278366Sadrian uint32_t bad_ack; 759278366Sadrian uint32_t not_bss; 760278366Sadrian uint32_t filtered; 761278366Sadrian uint32_t bad_chan; 762278366Sadrian} __packed; 763278366Sadrian 764278366Sadrianstruct wpi_rx_stats { 765278366Sadrian struct wpi_rx_phy_stats ofdm; 766278366Sadrian struct wpi_rx_phy_stats cck; 767278366Sadrian struct wpi_rx_general_stats general; 768278366Sadrian} __packed; 769278366Sadrian 770278366Sadrianstruct wpi_tx_stats { 771278366Sadrian uint32_t preamble; 772278366Sadrian uint32_t rx_detected; 773278366Sadrian uint32_t bt_defer; 774278366Sadrian uint32_t bt_kill; 775278366Sadrian uint32_t short_len; 776278366Sadrian uint32_t cts_timeout; 777278366Sadrian uint32_t ack_timeout; 778278366Sadrian uint32_t exp_ack; 779278366Sadrian uint32_t ack; 780278366Sadrian} __packed; 781278366Sadrian 782278366Sadrianstruct wpi_general_stats { 783278366Sadrian uint32_t temp; 784278366Sadrian uint32_t burst_check; 785278366Sadrian uint32_t burst; 786278366Sadrian uint32_t reserved[4]; 787278366Sadrian uint32_t sleep; 788278366Sadrian uint32_t slot_out; 789278366Sadrian uint32_t slot_idle; 790278366Sadrian uint32_t ttl_tstamp; 791278366Sadrian uint32_t tx_ant_a; 792278366Sadrian uint32_t tx_ant_b; 793278366Sadrian uint32_t exec; 794278366Sadrian uint32_t probe; 795278366Sadrian} __packed; 796278366Sadrian 797278366Sadrianstruct wpi_stats { 798278366Sadrian uint32_t flags; 799278366Sadrian struct wpi_rx_stats rx; 800278366Sadrian struct wpi_tx_stats tx; 801278366Sadrian struct wpi_general_stats general; 802278366Sadrian} __packed; 803278366Sadrian 804278366Sadrian/* Possible flags for command WPI_CMD_GET_STATISTICS. */ 805278366Sadrian#define WPI_STATISTICS_BEACON_DISABLE (1 << 1) 806278366Sadrian 807278366Sadrian 808278366Sadrian/* Firmware error dump entry. */ 809278366Sadrianstruct wpi_fw_dump { 810278366Sadrian uint32_t desc; 811278366Sadrian uint32_t time; 812278366Sadrian uint32_t blink[2]; 813278366Sadrian uint32_t ilink[2]; 814278366Sadrian uint32_t data; 815278366Sadrian} __packed; 816278366Sadrian 817278366Sadrian/* Firmware image file header. */ 818278366Sadrianstruct wpi_firmware_hdr { 819278366Sadrian 820278366Sadrian#define WPI_FW_MINVERSION 2144 821278366Sadrian#define WPI_FW_NAME "wpifw" 822278366Sadrian 823278366Sadrian uint16_t driver; 824278366Sadrian uint8_t minor; 825278366Sadrian uint8_t major; 826278366Sadrian uint32_t rtextsz; 827278366Sadrian uint32_t rdatasz; 828278366Sadrian uint32_t itextsz; 829278366Sadrian uint32_t idatasz; 830278366Sadrian uint32_t btextsz; 831278366Sadrian} __packed; 832278366Sadrian 833278366Sadrian#define WPI_FW_TEXT_MAXSZ ( 80 * 1024 ) 834278366Sadrian#define WPI_FW_DATA_MAXSZ ( 32 * 1024 ) 835278366Sadrian#define WPI_FW_BOOT_TEXT_MAXSZ 1024 836278366Sadrian 837278366Sadrian#define WPI_FW_UPDATED (1U << 31 ) 838278366Sadrian 839278366Sadrian/* 840278366Sadrian * Offsets into EEPROM. 841278366Sadrian */ 842173362Sbenjsc#define WPI_EEPROM_MAC 0x015 843173362Sbenjsc#define WPI_EEPROM_REVISION 0x035 844278366Sadrian#define WPI_EEPROM_SKU_CAP 0x045 845173362Sbenjsc#define WPI_EEPROM_TYPE 0x04a 846173362Sbenjsc#define WPI_EEPROM_DOMAIN 0x060 847173362Sbenjsc#define WPI_EEPROM_BAND1 0x063 848173362Sbenjsc#define WPI_EEPROM_BAND2 0x072 849173362Sbenjsc#define WPI_EEPROM_BAND3 0x080 850173362Sbenjsc#define WPI_EEPROM_BAND4 0x08d 851173362Sbenjsc#define WPI_EEPROM_BAND5 0x099 852173362Sbenjsc#define WPI_EEPROM_POWER_GRP 0x100 853173362Sbenjsc 854173362Sbenjscstruct wpi_eeprom_chan { 855173362Sbenjsc uint8_t flags; 856278366Sadrian#define WPI_EEPROM_CHAN_VALID (1 << 0) 857278366Sadrian#define WPI_EEPROM_CHAN_IBSS (1 << 1) 858278366Sadrian#define WPI_EEPROM_CHAN_ACTIVE (1 << 3) 859278366Sadrian#define WPI_EEPROM_CHAN_RADAR (1 << 4) 860173362Sbenjsc 861173362Sbenjsc int8_t maxpwr; 862173362Sbenjsc} __packed; 863173362Sbenjsc 864173362Sbenjscstruct wpi_eeprom_sample { 865278366Sadrian uint8_t index; 866278366Sadrian int8_t power; 867278366Sadrian uint16_t volt; 868278366Sadrian} __packed; 869173362Sbenjsc 870173362Sbenjsc#define WPI_POWER_GROUPS_COUNT 5 871173362Sbenjscstruct wpi_eeprom_group { 872278366Sadrian struct wpi_eeprom_sample samples[5]; 873278366Sadrian int32_t coef[5]; 874278366Sadrian int32_t corr[5]; 875278366Sadrian int8_t maxpwr; 876278366Sadrian uint8_t chan; 877278366Sadrian int16_t temp; 878173362Sbenjsc} __packed; 879173362Sbenjsc 880278366Sadrian#define WPI_CHAN_BANDS_COUNT 5 881173362Sbenjsc#define WPI_MAX_CHAN_PER_BAND 14 882173362Sbenjscstatic const struct wpi_chan_band { 883278366Sadrian uint32_t addr; /* offset in EEPROM */ 884278366Sadrian uint8_t nchan; 885278366Sadrian uint8_t chan[WPI_MAX_CHAN_PER_BAND]; 886278366Sadrian} wpi_bands[] = { 887278366Sadrian /* 20MHz channels, 2GHz band. */ 888278366Sadrian { WPI_EEPROM_BAND1, 14, 889278366Sadrian { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 890278366Sadrian /* 20MHz channels, 5GHz band. */ 891278366Sadrian { WPI_EEPROM_BAND2, 13, 892278366Sadrian { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 893278366Sadrian { WPI_EEPROM_BAND3, 12, 894278366Sadrian { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 895278366Sadrian { WPI_EEPROM_BAND4, 11, 896278366Sadrian { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 897278366Sadrian { WPI_EEPROM_BAND5, 6, 898278366Sadrian { 145, 149, 153, 157, 161, 165 } } 899173362Sbenjsc}; 900173362Sbenjsc 901278366Sadrian/* HW rate indices. */ 902278366Sadrian#define WPI_RIDX_OFDM6 0 903278366Sadrian#define WPI_RIDX_OFDM36 5 904278366Sadrian#define WPI_RIDX_OFDM48 6 905278366Sadrian#define WPI_RIDX_OFDM54 7 906278366Sadrian#define WPI_RIDX_CCK1 8 907278366Sadrian#define WPI_RIDX_CCK2 9 908278366Sadrian#define WPI_RIDX_CCK11 11 909278366Sadrian 910278366Sadrianstatic const uint8_t wpi_ridx_to_plcp[] = { 911278366Sadrian /* OFDM: IEEE Std 802.11a-1999, pp. 14 Table 80 */ 912278366Sadrian /* R1-R4 (ral/ural is R4-R1) */ 913278366Sadrian 0xd, 0xf, 0x5, 0x7, 0x9, 0xb, 0x1, 0x3, 914278366Sadrian /* CCK: device-dependent */ 915278366Sadrian 10, 20, 55, 110 916278366Sadrian}; 917278366Sadrian 918173362Sbenjsc#define WPI_MAX_PWR_INDEX 77 919173362Sbenjsc 920173362Sbenjsc/* 921173362Sbenjsc * RF Tx gain values from highest to lowest power (values obtained from 922173362Sbenjsc * the reference driver.) 923173362Sbenjsc */ 924173362Sbenjscstatic const uint8_t wpi_rf_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 925278366Sadrian 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xbb, 0xbb, 0xbb, 926278366Sadrian 0xbb, 0xf3, 0xf3, 0xf3, 0xf3, 0xf3, 0xd3, 0xd3, 0xb3, 0xb3, 0xb3, 927278366Sadrian 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x73, 0xeb, 0xeb, 0xeb, 928278366Sadrian 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xab, 0xab, 0xab, 0x8b, 929278366Sadrian 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xc3, 0xc3, 0xc3, 0xc3, 0xa3, 930278366Sadrian 0xa3, 0xa3, 0xa3, 0x83, 0x83, 0x83, 0x83, 0x63, 0x63, 0x63, 0x63, 931278366Sadrian 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 0x03, 0x03, 0x03, 932278366Sadrian 0x03 933173362Sbenjsc}; 934173362Sbenjsc 935173362Sbenjscstatic const uint8_t wpi_rf_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 936278366Sadrian 0xfb, 0xfb, 0xfb, 0xdb, 0xdb, 0xbb, 0xbb, 0x9b, 0x9b, 0x7b, 0x7b, 937278366Sadrian 0x7b, 0x7b, 0x5b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x1b, 0x1b, 938278366Sadrian 0x1b, 0x73, 0x73, 0x73, 0x53, 0x53, 0x53, 0x53, 0x53, 0x33, 0x33, 939278366Sadrian 0x33, 0x33, 0x13, 0x13, 0x13, 0x13, 0x13, 0xab, 0xab, 0xab, 0x8b, 940278366Sadrian 0x8b, 0x8b, 0x8b, 0x6b, 0x6b, 0x6b, 0x6b, 0x4b, 0x4b, 0x4b, 0x4b, 941278366Sadrian 0x2b, 0x2b, 0x2b, 0x2b, 0x0b, 0x0b, 0x0b, 0x0b, 0x83, 0x83, 0x63, 942278366Sadrian 0x63, 0x63, 0x63, 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 943278366Sadrian 0x03 944173362Sbenjsc}; 945173362Sbenjsc 946173362Sbenjsc/* 947173362Sbenjsc * DSP pre-DAC gain values from highest to lowest power (values obtained 948173362Sbenjsc * from the reference driver.) 949173362Sbenjsc */ 950173362Sbenjscstatic const uint8_t wpi_dsp_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 951278366Sadrian 0x7f, 0x7f, 0x7f, 0x7f, 0x7d, 0x6e, 0x69, 0x62, 0x7d, 0x73, 0x6c, 952278366Sadrian 0x63, 0x77, 0x6f, 0x69, 0x61, 0x5c, 0x6a, 0x64, 0x78, 0x71, 0x6b, 953278366Sadrian 0x7d, 0x77, 0x70, 0x6a, 0x65, 0x61, 0x5b, 0x6b, 0x79, 0x73, 0x6d, 954278366Sadrian 0x7f, 0x79, 0x73, 0x6c, 0x66, 0x60, 0x5c, 0x6e, 0x68, 0x62, 0x74, 955278366Sadrian 0x7d, 0x77, 0x71, 0x6b, 0x65, 0x60, 0x71, 0x6a, 0x66, 0x5f, 0x71, 956278366Sadrian 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 957278366Sadrian 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 958278366Sadrian 0x5f 959173362Sbenjsc}; 960173362Sbenjsc 961173362Sbenjscstatic const uint8_t wpi_dsp_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 962278366Sadrian 0x7f, 0x78, 0x72, 0x77, 0x65, 0x71, 0x66, 0x72, 0x67, 0x75, 0x6b, 963278366Sadrian 0x63, 0x5c, 0x6c, 0x7d, 0x76, 0x6d, 0x66, 0x60, 0x5a, 0x68, 0x62, 964278366Sadrian 0x5c, 0x76, 0x6f, 0x68, 0x7e, 0x79, 0x71, 0x69, 0x63, 0x76, 0x6f, 965278366Sadrian 0x68, 0x62, 0x74, 0x6d, 0x66, 0x62, 0x5d, 0x71, 0x6b, 0x63, 0x78, 966278366Sadrian 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 967278366Sadrian 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x6b, 0x63, 0x78, 968278366Sadrian 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 969278366Sadrian 0x78 970173362Sbenjsc}; 971173362Sbenjsc 972278366Sadrian/* 973278366Sadrian * Power saving settings (values obtained from the reference driver.) 974278366Sadrian */ 975278366Sadrian#define WPI_NDTIMRANGES 2 976278366Sadrian#define WPI_NPOWERLEVELS 6 977278366Sadrianstatic const struct wpi_pmgt { 978278366Sadrian uint32_t rxtimeout; 979278366Sadrian uint32_t txtimeout; 980278366Sadrian uint32_t intval[5]; 981278366Sadrian int skip_dtim; 982278366Sadrian} wpi_pmgt[WPI_NDTIMRANGES][WPI_NPOWERLEVELS] = { 983278366Sadrian /* DTIM <= 10 */ 984278366Sadrian { 985278366Sadrian { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 986278366Sadrian { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 987278366Sadrian { 200, 300, { 2, 4, 6, 7, 7 }, 0 }, /* PS level 2 */ 988278366Sadrian { 50, 100, { 2, 6, 9, 9, 10 }, 0 }, /* PS level 3 */ 989278366Sadrian { 50, 25, { 2, 7, 9, 9, 10 }, 1 }, /* PS level 4 */ 990278366Sadrian { 25, 25, { 4, 7, 10, 10, 10 }, 1 } /* PS level 5 */ 991278366Sadrian }, 992278366Sadrian /* DTIM >= 11 */ 993278366Sadrian { 994278366Sadrian { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 995278366Sadrian { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 996278366Sadrian { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 997278366Sadrian { 50, 100, { 2, 6, 9, 9, -1 }, 0 }, /* PS level 3 */ 998278366Sadrian { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 999278366Sadrian { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 1000278366Sadrian } 1001278366Sadrian}; 1002173362Sbenjsc 1003278366Sadrian/* Firmware errors. */ 1004278366Sadrianstatic const char * const wpi_fw_errmsg[] = { 1005278366Sadrian "OK", 1006278366Sadrian "FAIL", 1007278366Sadrian "BAD_PARAM", 1008278366Sadrian "BAD_CHECKSUM", 1009278366Sadrian "NMI_INTERRUPT", 1010278366Sadrian "SYSASSERT", 1011278366Sadrian "FATAL_ERROR" 1012278366Sadrian}; 1013278366Sadrian 1014173362Sbenjsc#define WPI_READ(sc, reg) \ 1015278366Sadrian bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 1016173362Sbenjsc 1017173362Sbenjsc#define WPI_WRITE(sc, reg, val) \ 1018278366Sadrian bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1019173362Sbenjsc 1020173362Sbenjsc#define WPI_WRITE_REGION_4(sc, offset, datap, count) \ 1021278366Sadrian bus_space_write_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 1022278366Sadrian (datap), (count)) 1023278366Sadrian 1024278366Sadrian#define WPI_SETBITS(sc, reg, mask) \ 1025278366Sadrian WPI_WRITE(sc, reg, WPI_READ(sc, reg) | (mask)) 1026278366Sadrian 1027278366Sadrian#define WPI_CLRBITS(sc, reg, mask) \ 1028278366Sadrian WPI_WRITE(sc, reg, WPI_READ(sc, reg) & ~(mask)) 1029278366Sadrian 1030278366Sadrian#define WPI_BARRIER_WRITE(sc) \ 1031278366Sadrian bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1032278366Sadrian BUS_SPACE_BARRIER_WRITE) 1033278366Sadrian 1034278366Sadrian#define WPI_BARRIER_READ_WRITE(sc) \ 1035278366Sadrian bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1036278366Sadrian BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 1037