if_wpireg.h revision 282382
1173362Sbenjsc/* $FreeBSD: head/sys/dev/wpi/if_wpireg.h 282382 2015-05-03 22:56:36Z adrian $ */ 2173362Sbenjsc 3173362Sbenjsc/*- 4173362Sbenjsc * Copyright (c) 2006,2007 5173362Sbenjsc * Damien Bergamini <damien.bergamini@free.fr> 6173362Sbenjsc * 7173362Sbenjsc * Permission to use, copy, modify, and distribute this software for any 8173362Sbenjsc * purpose with or without fee is hereby granted, provided that the above 9173362Sbenjsc * copyright notice and this permission notice appear in all copies. 10173362Sbenjsc * 11173362Sbenjsc * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12173362Sbenjsc * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13173362Sbenjsc * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14173362Sbenjsc * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15173362Sbenjsc * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16173362Sbenjsc * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17173362Sbenjsc * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18173362Sbenjsc */ 19173362Sbenjsc 20173362Sbenjsc#define WPI_TX_RING_COUNT 256 21278366Sadrian#define WPI_TX_RING_LOMARK 192 22278366Sadrian#define WPI_TX_RING_HIMARK 224 23280119Sadrian 24280119Sadrian#ifdef DIAGNOSTIC 25280119Sadrian#define WPI_RX_RING_COUNT_LOG 8 26280119Sadrian#else 27278366Sadrian#define WPI_RX_RING_COUNT_LOG 6 28280119Sadrian#endif 29280119Sadrian 30278366Sadrian#define WPI_RX_RING_COUNT (1 << WPI_RX_RING_COUNT_LOG) 31173362Sbenjsc 32278366Sadrian#define WPI_NTXQUEUES 8 33280058Sadrian#define WPI_DRV_NTXQUEUES 5 34280064Sadrian#define WPI_CMD_QUEUE_NUM 4 35280064Sadrian 36278366Sadrian#define WPI_NDMACHNLS 6 37278366Sadrian 38278366Sadrian/* Maximum scatter/gather. */ 39280059Sadrian#define WPI_MAX_SCATTER 4 40278366Sadrian 41173362Sbenjsc/* 42173362Sbenjsc * Rings must be aligned on a 16K boundary. 43173362Sbenjsc */ 44173362Sbenjsc#define WPI_RING_DMA_ALIGN 0x4000 45173362Sbenjsc 46278366Sadrian/* Maximum Rx buffer size. */ 47173362Sbenjsc#define WPI_RBUF_SIZE ( 3 * 1024 ) /* XXX 3000 but must be aligned */ 48173362Sbenjsc 49173362Sbenjsc/* 50173362Sbenjsc * Control and status registers. 51173362Sbenjsc */ 52278366Sadrian#define WPI_HW_IF_CONFIG 0x000 53278366Sadrian#define WPI_INT 0x008 54278366Sadrian#define WPI_INT_MASK 0x00c 55278366Sadrian#define WPI_FH_INT 0x010 56278366Sadrian#define WPI_GPIO_IN 0x018 57173362Sbenjsc#define WPI_RESET 0x020 58278366Sadrian#define WPI_GP_CNTRL 0x024 59278366Sadrian#define WPI_EEPROM 0x02c 60278366Sadrian#define WPI_EEPROM_GP 0x030 61278366Sadrian#define WPI_GIO 0x03c 62278366Sadrian#define WPI_UCODE_GP1 0x054 63278366Sadrian#define WPI_UCODE_GP1_SET 0x058 64278366Sadrian#define WPI_UCODE_GP1_CLR 0x05c 65278366Sadrian#define WPI_UCODE_GP2 0x060 66278366Sadrian#define WPI_GIO_CHICKEN 0x100 67278366Sadrian#define WPI_ANA_PLL 0x20c 68278366Sadrian#define WPI_DBG_HPET_MEM 0x240 69278366Sadrian#define WPI_MEM_RADDR 0x40c 70278366Sadrian#define WPI_MEM_WADDR 0x410 71278366Sadrian#define WPI_MEM_WDATA 0x418 72278366Sadrian#define WPI_MEM_RDATA 0x41c 73278366Sadrian#define WPI_PRPH_WADDR 0x444 74278366Sadrian#define WPI_PRPH_RADDR 0x448 75278366Sadrian#define WPI_PRPH_WDATA 0x44c 76278366Sadrian#define WPI_PRPH_RDATA 0x450 77278366Sadrian#define WPI_HBUS_TARG_WRPTR 0x460 78173362Sbenjsc 79278366Sadrian/* 80278366Sadrian * Flow-Handler registers. 81278366Sadrian */ 82278366Sadrian#define WPI_FH_CBBC_CTRL(qid) (0x940 + (qid) * 8) 83278366Sadrian#define WPI_FH_CBBC_BASE(qid) (0x944 + (qid) * 8) 84278366Sadrian#define WPI_FH_RX_CONFIG 0xc00 85278366Sadrian#define WPI_FH_RX_BASE 0xc04 86278366Sadrian#define WPI_FH_RX_WPTR 0xc20 87278366Sadrian#define WPI_FH_RX_RPTR_ADDR 0xc24 88278366Sadrian#define WPI_FH_RSSR_TBL 0xcc0 89278366Sadrian#define WPI_FH_RX_STATUS 0xcc4 90278366Sadrian#define WPI_FH_TX_CONFIG(qid) (0xd00 + (qid) * 32) 91278366Sadrian#define WPI_FH_TX_BASE 0xe80 92278366Sadrian#define WPI_FH_MSG_CONFIG 0xe88 93278366Sadrian#define WPI_FH_TX_STATUS 0xe90 94173362Sbenjsc 95278366Sadrian 96173362Sbenjsc/* 97173362Sbenjsc * NIC internal memory offsets. 98173362Sbenjsc */ 99278366Sadrian#define WPI_ALM_SCHED_MODE 0x2e00 100278366Sadrian#define WPI_ALM_SCHED_ARASTAT 0x2e04 101278366Sadrian#define WPI_ALM_SCHED_TXFACT 0x2e10 102278366Sadrian#define WPI_ALM_SCHED_TXF4MF 0x2e14 103278366Sadrian#define WPI_ALM_SCHED_TXF5MF 0x2e20 104278366Sadrian#define WPI_ALM_SCHED_SBYPASS_MODE1 0x2e2c 105278366Sadrian#define WPI_ALM_SCHED_SBYPASS_MODE2 0x2e30 106280093Sadrian#define WPI_APMG_CLK_CTRL 0x3000 107278366Sadrian#define WPI_APMG_CLK_EN 0x3004 108278366Sadrian#define WPI_APMG_CLK_DIS 0x3008 109278366Sadrian#define WPI_APMG_PS 0x300c 110278366Sadrian#define WPI_APMG_PCI_STT 0x3010 111278366Sadrian#define WPI_APMG_RFKILL 0x3014 112278366Sadrian#define WPI_BSM_WR_CTRL 0x3400 113278366Sadrian#define WPI_BSM_WR_MEM_SRC 0x3404 114278366Sadrian#define WPI_BSM_WR_MEM_DST 0x3408 115278366Sadrian#define WPI_BSM_WR_DWCOUNT 0x340c 116278366Sadrian#define WPI_BSM_DRAM_TEXT_ADDR 0x3490 117278366Sadrian#define WPI_BSM_DRAM_TEXT_SIZE 0x3494 118278366Sadrian#define WPI_BSM_DRAM_DATA_ADDR 0x3498 119278366Sadrian#define WPI_BSM_DRAM_DATA_SIZE 0x349c 120278366Sadrian#define WPI_BSM_SRAM_BASE 0x3800 121173362Sbenjsc 122173362Sbenjsc 123278366Sadrian/* Possible flags for register WPI_HW_IF_CONFIG. */ 124278366Sadrian#define WPI_HW_IF_CONFIG_ALM_MB (1 << 8) 125278366Sadrian#define WPI_HW_IF_CONFIG_ALM_MM (1 << 9) 126278366Sadrian#define WPI_HW_IF_CONFIG_SKU_MRC (1 << 10) 127278366Sadrian#define WPI_HW_IF_CONFIG_REV_D (1 << 11) 128278366Sadrian#define WPI_HW_IF_CONFIG_TYPE_B (1 << 12) 129173362Sbenjsc 130278366Sadrian/* Possible flags for registers WPI_PRPH_RADDR/WPI_PRPH_WADDR. */ 131278366Sadrian#define WPI_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24) 132173362Sbenjsc 133278366Sadrian/* Possible values for WPI_BSM_WR_MEM_DST. */ 134278366Sadrian#define WPI_FW_TEXT_BASE 0x00000000 135278366Sadrian#define WPI_FW_DATA_BASE 0x00800000 136173362Sbenjsc 137278366Sadrian/* Possible flags for WPI_GPIO_IN. */ 138278366Sadrian#define WPI_GPIO_IN_VMAIN (1 << 9) 139173362Sbenjsc 140278366Sadrian/* Possible flags for register WPI_RESET. */ 141278366Sadrian#define WPI_RESET_NEVO (1 << 0) 142278366Sadrian#define WPI_RESET_SW (1 << 7) 143278366Sadrian#define WPI_RESET_MASTER_DISABLED (1 << 8) 144278366Sadrian#define WPI_RESET_STOP_MASTER (1 << 9) 145173362Sbenjsc 146278366Sadrian/* Possible flags for register WPI_GP_CNTRL. */ 147278366Sadrian#define WPI_GP_CNTRL_MAC_ACCESS_ENA (1 << 0) 148278366Sadrian#define WPI_GP_CNTRL_MAC_CLOCK_READY (1 << 0) 149278366Sadrian#define WPI_GP_CNTRL_INIT_DONE (1 << 2) 150278366Sadrian#define WPI_GP_CNTRL_MAC_ACCESS_REQ (1 << 3) 151278366Sadrian#define WPI_GP_CNTRL_SLEEP (1 << 4) 152278366Sadrian#define WPI_GP_CNTRL_PS_MASK (7 << 24) 153278366Sadrian#define WPI_GP_CNTRL_MAC_PS (4 << 24) 154278366Sadrian#define WPI_GP_CNTRL_RFKILL (1 << 27) 155173362Sbenjsc 156278366Sadrian/* Possible flags for register WPI_GIO_CHICKEN. */ 157278366Sadrian#define WPI_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23) 158278366Sadrian#define WPI_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29) 159173362Sbenjsc 160278366Sadrian/* Possible flags for register WPI_GIO. */ 161278366Sadrian#define WPI_GIO_L0S_ENA (1 << 1) 162173362Sbenjsc 163278366Sadrian/* Possible flags for register WPI_FH_RX_CONFIG. */ 164278366Sadrian#define WPI_FH_RX_CONFIG_DMA_ENA (1U << 31) 165278366Sadrian#define WPI_FH_RX_CONFIG_RDRBD_ENA (1 << 29) 166278366Sadrian#define WPI_FH_RX_CONFIG_WRSTATUS_ENA (1 << 27) 167278366Sadrian#define WPI_FH_RX_CONFIG_MAXFRAG (1 << 24) 168278366Sadrian#define WPI_FH_RX_CONFIG_NRBD(x) ((x) << 20) 169278366Sadrian#define WPI_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12) 170278366Sadrian#define WPI_FH_RX_CONFIG_IRQ_TIMEOUT(x) ((x) << 4) 171173362Sbenjsc 172278366Sadrian/* Possible flags for register WPI_ANA_PLL. */ 173278366Sadrian#define WPI_ANA_PLL_INIT (1 << 24) 174173362Sbenjsc 175278366Sadrian/* Possible flags for register WPI_UCODE_GP1*. */ 176278366Sadrian#define WPI_UCODE_GP1_MAC_SLEEP (1 << 0) 177278366Sadrian#define WPI_UCODE_GP1_RFKILL (1 << 1) 178278366Sadrian#define WPI_UCODE_GP1_CMD_BLOCKED (1 << 2) 179173362Sbenjsc 180278366Sadrian/* Possible flags for register WPI_FH_RX_STATUS. */ 181278366Sadrian#define WPI_FH_RX_STATUS_IDLE (1 << 24) 182173362Sbenjsc 183278366Sadrian/* Possible flags for register WPI_BSM_WR_CTRL. */ 184278366Sadrian#define WPI_BSM_WR_CTRL_START_EN (1 << 30) 185278366Sadrian#define WPI_BSM_WR_CTRL_START (1U << 31) 186173362Sbenjsc 187278366Sadrian/* Possible flags for register WPI_INT. */ 188278366Sadrian#define WPI_INT_ALIVE (1 << 0) 189278366Sadrian#define WPI_INT_WAKEUP (1 << 1) 190278366Sadrian#define WPI_INT_SW_RX (1 << 3) 191278366Sadrian#define WPI_INT_SW_ERR (1 << 25) 192278366Sadrian#define WPI_INT_FH_TX (1 << 27) 193278366Sadrian#define WPI_INT_HW_ERR (1 << 29) 194278366Sadrian#define WPI_INT_FH_RX (1U << 31) 195173362Sbenjsc 196278366Sadrian/* Shortcut. */ 197278366Sadrian#define WPI_INT_MASK_DEF \ 198278366Sadrian (WPI_INT_SW_ERR | WPI_INT_HW_ERR | WPI_INT_FH_TX | \ 199278366Sadrian WPI_INT_FH_RX | WPI_INT_ALIVE | WPI_INT_WAKEUP | \ 200278366Sadrian WPI_INT_SW_RX) 201173362Sbenjsc 202278366Sadrian/* Possible flags for register WPI_FH_INT. */ 203278366Sadrian#define WPI_FH_INT_RX_CHNL(x) (1 << ((x) + 16)) 204278366Sadrian#define WPI_FH_INT_HI_PRIOR (1 << 30) 205278366Sadrian/* Shortcuts for the above. */ 206278366Sadrian#define WPI_FH_INT_RX \ 207278366Sadrian (WPI_FH_INT_RX_CHNL(0) | \ 208278366Sadrian WPI_FH_INT_RX_CHNL(1) | \ 209278366Sadrian WPI_FH_INT_RX_CHNL(2) | \ 210278366Sadrian WPI_FH_INT_HI_PRIOR) 211173362Sbenjsc 212278366Sadrian/* Possible flags for register WPI_FH_TX_STATUS. */ 213278366Sadrian#define WPI_FH_TX_STATUS_IDLE(qid) \ 214278366Sadrian (1 << ((qid) + 24) | 1 << ((qid) + 16)) 215278366Sadrian 216278366Sadrian/* Possible flags for register WPI_EEPROM. */ 217278366Sadrian#define WPI_EEPROM_READ_VALID (1 << 0) 218278366Sadrian 219278366Sadrian/* Possible flags for register WPI_EEPROM_GP. */ 220173362Sbenjsc#define WPI_EEPROM_VERSION 0x00000007 221278366Sadrian#define WPI_EEPROM_GP_IF_OWNER 0x00000180 222173362Sbenjsc 223278366Sadrian/* Possible flags for register WPI_APMG_PS. */ 224278366Sadrian#define WPI_APMG_PS_PWR_SRC_MASK (3 << 24) 225173362Sbenjsc 226278366Sadrian/* Possible flags for registers WPI_APMG_CLK_*. */ 227278366Sadrian#define WPI_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9) 228278366Sadrian#define WPI_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11) 229278366Sadrian 230278366Sadrian/* Possible flags for register WPI_APMG_PCI_STT. */ 231278366Sadrian#define WPI_APMG_PCI_STT_L1A_DIS (1 << 11) 232278366Sadrian 233173362Sbenjscstruct wpi_shared { 234280064Sadrian uint32_t txbase[WPI_NTXQUEUES]; 235173362Sbenjsc uint32_t next; 236173362Sbenjsc uint32_t reserved[2]; 237173362Sbenjsc} __packed; 238173362Sbenjsc 239173362Sbenjsc#define WPI_MAX_SEG_LEN 65520 240173362Sbenjscstruct wpi_tx_desc { 241278366Sadrian uint8_t reserved1[3]; 242278366Sadrian uint8_t nsegs; 243173362Sbenjsc#define WPI_PAD32(x) (roundup2(x, 4) - (x)) 244173362Sbenjsc 245173362Sbenjsc struct { 246173362Sbenjsc uint32_t addr; 247173362Sbenjsc uint32_t len; 248278366Sadrian } __packed segs[WPI_MAX_SCATTER]; 249278366Sadrian uint8_t reserved2[28]; 250173362Sbenjsc} __packed; 251173362Sbenjsc 252173362Sbenjscstruct wpi_tx_stat { 253278366Sadrian uint8_t rtsfailcnt; 254278366Sadrian uint8_t ackfailcnt; 255278366Sadrian uint8_t btkillcnt; 256173362Sbenjsc uint8_t rate; 257173362Sbenjsc uint32_t duration; 258173362Sbenjsc uint32_t status; 259282378Sadrian#define WPI_TX_STATUS_SUCCESS 0x01 260282378Sadrian#define WPI_TX_STATUS_DIRECT_DONE 0x02 261282378Sadrian#define WPI_TX_STATUS_FAIL 0x80 262282378Sadrian#define WPI_TX_STATUS_FAIL_SHORT_LIMIT 0x82 263282378Sadrian#define WPI_TX_STATUS_FAIL_LONG_LIMIT 0x83 264282378Sadrian#define WPI_TX_STATUS_FAIL_FIFO_UNDERRUN 0x84 265282378Sadrian#define WPI_TX_STATUS_FAIL_MGMNT_ABORT 0x85 266282378Sadrian#define WPI_TX_STATUS_FAIL_NEXT_FRAG 0x86 267282378Sadrian#define WPI_TX_STATUS_FAIL_LIFE_EXPIRE 0x87 268282378Sadrian#define WPI_TX_STATUS_FAIL_NODE_PS 0x88 269282378Sadrian#define WPI_TX_STATUS_FAIL_ABORTED 0x89 270282378Sadrian#define WPI_TX_STATUS_FAIL_BT_RETRY 0x8a 271282378Sadrian#define WPI_TX_STATUS_FAIL_NODE_INVALID 0x8b 272282378Sadrian#define WPI_TX_STATUS_FAIL_FRAG_DROPPED 0x8c 273282378Sadrian#define WPI_TX_STATUS_FAIL_TID_DISABLE 0x8d 274282378Sadrian#define WPI_TX_STATUS_FAIL_FRAME_FLUSHED 0x8e 275282378Sadrian#define WPI_TX_STATUS_FAIL_INSUFFICIENT_CF_POLL 0x8f 276282378Sadrian#define WPI_TX_STATUS_FAIL_TX_LOCKED 0x90 277282378Sadrian#define WPI_TX_STATUS_FAIL_NO_BEACON_ON_RADAR 0x91 278282378Sadrian 279173362Sbenjsc} __packed; 280173362Sbenjsc 281173362Sbenjscstruct wpi_rx_desc { 282173362Sbenjsc uint32_t len; 283173362Sbenjsc uint8_t type; 284173362Sbenjsc#define WPI_UC_READY 1 285173362Sbenjsc#define WPI_RX_DONE 27 286173362Sbenjsc#define WPI_TX_DONE 28 287173362Sbenjsc#define WPI_START_SCAN 130 288177043Sthompsa#define WPI_SCAN_RESULTS 131 289173362Sbenjsc#define WPI_STOP_SCAN 132 290278366Sadrian#define WPI_BEACON_SENT 144 291278366Sadrian#define WPI_RX_STATISTICS 156 292278366Sadrian#define WPI_BEACON_STATISTICS 157 293173362Sbenjsc#define WPI_STATE_CHANGED 161 294278366Sadrian#define WPI_BEACON_MISSED 162 295173362Sbenjsc 296173362Sbenjsc uint8_t flags; 297173362Sbenjsc uint8_t idx; 298173362Sbenjsc uint8_t qid; 299173362Sbenjsc} __packed; 300173362Sbenjsc 301280064Sadrian#define WPI_RX_DESC_QID_MSK 0x07 302280064Sadrian#define WPI_UNSOLICITED_RX_NOTIF 0x80 303280064Sadrian 304173362Sbenjscstruct wpi_rx_stat { 305173362Sbenjsc uint8_t len; 306173362Sbenjsc#define WPI_STAT_MAXLEN 20 307173362Sbenjsc 308173362Sbenjsc uint8_t id; 309173362Sbenjsc uint8_t rssi; /* received signal strength */ 310280064Sadrian#define WPI_RSSI_OFFSET -95 311173362Sbenjsc 312173362Sbenjsc uint8_t agc; /* access gain control */ 313173362Sbenjsc uint16_t signal; 314173362Sbenjsc uint16_t noise; 315173362Sbenjsc} __packed; 316173362Sbenjsc 317173362Sbenjscstruct wpi_rx_head { 318173362Sbenjsc uint16_t chan; 319173362Sbenjsc uint16_t flags; 320278366Sadrian#define WPI_STAT_FLAG_SHPREAMBLE (1 << 2) 321278366Sadrian 322173362Sbenjsc uint8_t reserved; 323278366Sadrian uint8_t plcp; 324173362Sbenjsc uint16_t len; 325173362Sbenjsc} __packed; 326173362Sbenjsc 327173362Sbenjscstruct wpi_rx_tail { 328173362Sbenjsc uint32_t flags; 329173362Sbenjsc#define WPI_RX_NO_CRC_ERR (1 << 0) 330173362Sbenjsc#define WPI_RX_NO_OVFL_ERR (1 << 1) 331173362Sbenjsc/* shortcut for the above */ 332173362Sbenjsc#define WPI_RX_NOERROR (WPI_RX_NO_CRC_ERR | WPI_RX_NO_OVFL_ERR) 333278366Sadrian#define WPI_RX_CIPHER_MASK (7 << 8) 334278366Sadrian#define WPI_RX_CIPHER_CCMP (2 << 8) 335278366Sadrian#define WPI_RX_DECRYPT_MASK (3 << 11) 336278366Sadrian#define WPI_RX_DECRYPT_OK (3 << 11) 337278366Sadrian 338173362Sbenjsc uint64_t tstamp; 339173362Sbenjsc uint32_t tbeacon; 340173362Sbenjsc} __packed; 341173362Sbenjsc 342173362Sbenjscstruct wpi_tx_cmd { 343173362Sbenjsc uint8_t code; 344278366Sadrian#define WPI_CMD_RXON 16 345278366Sadrian#define WPI_CMD_RXON_ASSOC 17 346278366Sadrian#define WPI_CMD_EDCA_PARAMS 19 347278366Sadrian#define WPI_CMD_TIMING 20 348173362Sbenjsc#define WPI_CMD_ADD_NODE 24 349278366Sadrian#define WPI_CMD_DEL_NODE 25 350173362Sbenjsc#define WPI_CMD_TX_DATA 28 351173362Sbenjsc#define WPI_CMD_MRR_SETUP 71 352173362Sbenjsc#define WPI_CMD_SET_LED 72 353173362Sbenjsc#define WPI_CMD_SET_POWER_MODE 119 354173362Sbenjsc#define WPI_CMD_SCAN 128 355173362Sbenjsc#define WPI_CMD_SET_BEACON 145 356173362Sbenjsc#define WPI_CMD_TXPOWER 151 357278366Sadrian#define WPI_CMD_BT_COEX 155 358278366Sadrian#define WPI_CMD_GET_STATISTICS 156 359173362Sbenjsc 360173362Sbenjsc uint8_t flags; 361173362Sbenjsc uint8_t idx; 362173362Sbenjsc uint8_t qid; 363278366Sadrian uint8_t data[124]; 364173362Sbenjsc} __packed; 365173362Sbenjsc 366278366Sadrian/* Structure for command WPI_CMD_RXON. */ 367278366Sadrianstruct wpi_rxon { 368173362Sbenjsc uint8_t myaddr[IEEE80211_ADDR_LEN]; 369173362Sbenjsc uint16_t reserved1; 370173362Sbenjsc uint8_t bssid[IEEE80211_ADDR_LEN]; 371173362Sbenjsc uint16_t reserved2; 372278366Sadrian uint8_t wlap[IEEE80211_ADDR_LEN]; 373173362Sbenjsc uint16_t reserved3; 374173362Sbenjsc uint8_t mode; 375173362Sbenjsc#define WPI_MODE_HOSTAP 1 376173362Sbenjsc#define WPI_MODE_STA 3 377173362Sbenjsc#define WPI_MODE_IBSS 4 378173362Sbenjsc#define WPI_MODE_MONITOR 6 379173362Sbenjsc 380278366Sadrian uint8_t air; 381173362Sbenjsc uint16_t reserved4; 382173362Sbenjsc uint8_t ofdm_mask; 383173362Sbenjsc uint8_t cck_mask; 384173362Sbenjsc uint16_t associd; 385173362Sbenjsc uint32_t flags; 386278366Sadrian#define WPI_RXON_24GHZ (1 << 0) 387278366Sadrian#define WPI_RXON_CCK (1 << 1) 388278366Sadrian#define WPI_RXON_AUTO (1 << 2) 389278366Sadrian#define WPI_RXON_SHSLOT (1 << 4) 390278366Sadrian#define WPI_RXON_SHPREAMBLE (1 << 5) 391278366Sadrian#define WPI_RXON_NODIVERSITY (1 << 7) 392278366Sadrian#define WPI_RXON_ANTENNA_A (1 << 8) 393278366Sadrian#define WPI_RXON_ANTENNA_B (1 << 9) 394278366Sadrian#define WPI_RXON_TSF (1 << 15) 395278366Sadrian#define WPI_RXON_CTS_TO_SELF (1 << 30) 396173362Sbenjsc 397173362Sbenjsc uint32_t filter; 398173362Sbenjsc#define WPI_FILTER_PROMISC (1 << 0) 399173362Sbenjsc#define WPI_FILTER_CTL (1 << 1) 400173362Sbenjsc#define WPI_FILTER_MULTICAST (1 << 2) 401173362Sbenjsc#define WPI_FILTER_NODECRYPT (1 << 3) 402173362Sbenjsc#define WPI_FILTER_BSS (1 << 5) 403173362Sbenjsc#define WPI_FILTER_BEACON (1 << 6) 404280105Sadrian#define WPI_FILTER_ASSOC (1 << 7) /* Accept associaton requests. */ 405173362Sbenjsc 406173362Sbenjsc uint8_t chan; 407278366Sadrian uint16_t reserved5; 408173362Sbenjsc} __packed; 409173362Sbenjsc 410278366Sadrian/* Structure for command WPI_CMD_RXON_ASSOC. */ 411173362Sbenjscstruct wpi_assoc { 412173362Sbenjsc uint32_t flags; 413173362Sbenjsc uint32_t filter; 414173362Sbenjsc uint8_t ofdm_mask; 415173362Sbenjsc uint8_t cck_mask; 416173362Sbenjsc uint16_t reserved; 417173362Sbenjsc} __packed; 418173362Sbenjsc 419278366Sadrian/* Structure for command WPI_CMD_EDCA_PARAMS. */ 420278366Sadrianstruct wpi_edca_params { 421173362Sbenjsc uint32_t flags; 422278366Sadrian#define WPI_EDCA_UPDATE (1 << 0) 423278366Sadrian 424173362Sbenjsc struct { 425173362Sbenjsc uint16_t cwmin; 426173362Sbenjsc uint16_t cwmax; 427173362Sbenjsc uint8_t aifsn; 428173362Sbenjsc uint8_t reserved; 429278366Sadrian uint16_t txoplimit; 430173362Sbenjsc } __packed ac[WME_NUM_AC]; 431173362Sbenjsc} __packed; 432173362Sbenjsc 433278366Sadrian/* Structure for command WPI_CMD_TIMING. */ 434278366Sadrianstruct wpi_cmd_timing { 435173362Sbenjsc uint64_t tstamp; 436173362Sbenjsc uint16_t bintval; 437173362Sbenjsc uint16_t atim; 438173362Sbenjsc uint32_t binitval; 439173362Sbenjsc uint16_t lintval; 440173362Sbenjsc uint16_t reserved; 441173362Sbenjsc} __packed; 442173362Sbenjsc 443278366Sadrian/* Structure for command WPI_CMD_ADD_NODE. */ 444173362Sbenjscstruct wpi_node_info { 445173362Sbenjsc uint8_t control; 446278366Sadrian#define WPI_NODE_UPDATE (1 << 0) 447173362Sbenjsc 448173362Sbenjsc uint8_t reserved1[3]; 449278366Sadrian uint8_t macaddr[IEEE80211_ADDR_LEN]; 450173362Sbenjsc uint16_t reserved2; 451173362Sbenjsc uint8_t id; 452173362Sbenjsc#define WPI_ID_BSS 0 453278366Sadrian#define WPI_ID_IBSS_MIN 2 454278366Sadrian#define WPI_ID_IBSS_MAX 23 455173362Sbenjsc#define WPI_ID_BROADCAST 24 456278366Sadrian#define WPI_ID_UNDEFINED (uint8_t)-1 457173362Sbenjsc 458173362Sbenjsc uint8_t flags; 459278366Sadrian#define WPI_FLAG_KEY_SET (1 << 0) 460278366Sadrian 461173362Sbenjsc uint16_t reserved3; 462278366Sadrian uint16_t kflags; 463278366Sadrian#define WPI_KFLAG_CCMP (1 << 1) 464278366Sadrian#define WPI_KFLAG_KID(kid) ((kid) << 8) 465278366Sadrian#define WPI_KFLAG_MULTICAST (1 << 14) 466278366Sadrian 467278366Sadrian uint8_t tsc2; 468173362Sbenjsc uint8_t reserved4; 469173362Sbenjsc uint16_t ttak[5]; 470173362Sbenjsc uint16_t reserved5; 471173362Sbenjsc uint8_t key[IEEE80211_KEYBUF_SIZE]; 472173362Sbenjsc uint32_t action; 473278366Sadrian#define WPI_ACTION_SET_RATE (1 << 2) 474278366Sadrian 475173362Sbenjsc uint32_t mask; 476173362Sbenjsc uint16_t tid; 477278366Sadrian uint8_t plcp; 478173362Sbenjsc uint8_t antenna; 479278366Sadrian#define WPI_ANTENNA_A (1 << 6) 480278366Sadrian#define WPI_ANTENNA_B (1 << 7) 481278366Sadrian#define WPI_ANTENNA_BOTH (WPI_ANTENNA_A | WPI_ANTENNA_B) 482278366Sadrian 483173362Sbenjsc uint8_t add_imm; 484173362Sbenjsc uint8_t del_imm; 485173362Sbenjsc uint16_t add_imm_start; 486173362Sbenjsc} __packed; 487173362Sbenjsc 488278366Sadrian/* Structure for command WPI_CMD_DEL_NODE. */ 489278366Sadrianstruct wpi_cmd_del_node { 490278366Sadrian uint8_t count; 491278366Sadrian uint8_t reserved1[3]; 492278366Sadrian uint8_t macaddr[IEEE80211_ADDR_LEN]; 493278366Sadrian uint16_t reserved2; 494278366Sadrian} __packed; 495278366Sadrian 496278366Sadrian/* Structure for command WPI_CMD_TX_DATA. */ 497173362Sbenjscstruct wpi_cmd_data { 498173362Sbenjsc uint16_t len; 499173362Sbenjsc uint16_t lnext; 500173362Sbenjsc uint32_t flags; 501173362Sbenjsc#define WPI_TX_NEED_RTS (1 << 1) 502280059Sadrian#define WPI_TX_NEED_CTS (1 << 2) 503173362Sbenjsc#define WPI_TX_NEED_ACK (1 << 3) 504173362Sbenjsc#define WPI_TX_FULL_TXOP (1 << 7) 505278366Sadrian#define WPI_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 506173362Sbenjsc#define WPI_TX_AUTO_SEQ (1 << 13) 507278764Sadrian#define WPI_TX_MORE_FRAG (1 << 14) 508173362Sbenjsc#define WPI_TX_INSERT_TSTAMP (1 << 16) 509173362Sbenjsc 510278366Sadrian uint8_t plcp; 511173362Sbenjsc uint8_t id; 512173362Sbenjsc uint8_t tid; 513173362Sbenjsc uint8_t security; 514278366Sadrian#define WPI_CIPHER_WEP 1 515278366Sadrian#define WPI_CIPHER_CCMP 2 516278366Sadrian#define WPI_CIPHER_TKIP 3 517278366Sadrian#define WPI_CIPHER_WEP104 9 518278366Sadrian 519173362Sbenjsc uint8_t key[IEEE80211_KEYBUF_SIZE]; 520173362Sbenjsc uint8_t tkip[IEEE80211_WEP_MICLEN]; 521173362Sbenjsc uint32_t fnext; 522173362Sbenjsc uint32_t lifetime; 523173362Sbenjsc#define WPI_LIFETIME_INFINITE 0xffffffff 524278366Sadrian 525173362Sbenjsc uint8_t ofdm_mask; 526173362Sbenjsc uint8_t cck_mask; 527173362Sbenjsc uint8_t rts_ntries; 528173362Sbenjsc uint8_t data_ntries; 529173362Sbenjsc uint16_t timeout; 530173362Sbenjsc uint16_t txop; 531173362Sbenjsc} __packed; 532173362Sbenjsc 533278366Sadrian/* Structure for command WPI_CMD_SET_BEACON. */ 534173362Sbenjscstruct wpi_cmd_beacon { 535173362Sbenjsc uint16_t len; 536173362Sbenjsc uint16_t reserved1; 537173362Sbenjsc uint32_t flags; /* same as wpi_cmd_data */ 538278366Sadrian uint8_t plcp; 539173362Sbenjsc uint8_t id; 540173362Sbenjsc uint8_t reserved2[30]; 541173362Sbenjsc uint32_t lifetime; 542173362Sbenjsc uint8_t ofdm_mask; 543173362Sbenjsc uint8_t cck_mask; 544173362Sbenjsc uint16_t reserved3[3]; 545173362Sbenjsc uint16_t tim; 546173362Sbenjsc uint8_t timsz; 547173362Sbenjsc uint8_t reserved4; 548173362Sbenjsc} __packed; 549173362Sbenjsc 550278366Sadrian/* Structure for notification WPI_BEACON_MISSED. */ 551278366Sadrianstruct wpi_beacon_missed { 552280059Sadrian uint32_t consecutive; 553280059Sadrian uint32_t total; 554280059Sadrian uint32_t expected; 555280059Sadrian uint32_t received; 556173976Sbenjsc} __packed; 557173976Sbenjsc 558173976Sbenjsc 559278366Sadrian/* Structure for command WPI_CMD_MRR_SETUP. */ 560278366Sadrian#define WPI_RIDX_MAX 11 561173362Sbenjscstruct wpi_mrr_setup { 562278366Sadrian uint32_t which; 563173362Sbenjsc#define WPI_MRR_CTL 0 564173362Sbenjsc#define WPI_MRR_DATA 1 565173362Sbenjsc 566173362Sbenjsc struct { 567278366Sadrian uint8_t plcp; 568173362Sbenjsc uint8_t flags; 569173362Sbenjsc uint8_t ntries; 570282369Sadrian#define WPI_NTRIES_DEFAULT 2 571282369Sadrian 572173362Sbenjsc uint8_t next; 573278366Sadrian } __packed rates[WPI_RIDX_MAX + 1]; 574173362Sbenjsc} __packed; 575173362Sbenjsc 576278366Sadrian/* Structure for command WPI_CMD_SET_LED. */ 577173362Sbenjscstruct wpi_cmd_led { 578173362Sbenjsc uint32_t unit; /* multiplier (in usecs) */ 579173362Sbenjsc uint8_t which; 580173362Sbenjsc#define WPI_LED_ACTIVITY 1 581173362Sbenjsc#define WPI_LED_LINK 2 582173362Sbenjsc 583173362Sbenjsc uint8_t off; 584173362Sbenjsc uint8_t on; 585173362Sbenjsc uint8_t reserved; 586173362Sbenjsc} __packed; 587173362Sbenjsc 588278366Sadrian/* Structure for command WPI_CMD_SET_POWER_MODE. */ 589278366Sadrianstruct wpi_pmgt_cmd { 590278366Sadrian uint16_t flags; 591278366Sadrian#define WPI_PS_ALLOW_SLEEP (1 << 0) 592278366Sadrian#define WPI_PS_NOTIFY (1 << 1) 593278366Sadrian#define WPI_PS_SLEEP_OVER_DTIM (1 << 2) 594278366Sadrian#define WPI_PS_PCI_PMGT (1 << 3) 595278366Sadrian 596278366Sadrian uint8_t reserved[2]; 597278366Sadrian uint32_t rxtimeout; 598278366Sadrian uint32_t txtimeout; 599278366Sadrian uint32_t intval[5]; 600173362Sbenjsc} __packed; 601173362Sbenjsc 602278366Sadrian/* Structures for command WPI_CMD_SCAN. */ 603278366Sadrian#define WPI_SCAN_MAX_ESSIDS 4 604278366Sadrianstruct wpi_scan_essid { 605278366Sadrian uint8_t id; 606278366Sadrian uint8_t len; 607278366Sadrian uint8_t data[IEEE80211_NWID_LEN]; 608278366Sadrian} __packed; 609278366Sadrian 610173362Sbenjscstruct wpi_scan_hdr { 611173362Sbenjsc uint16_t len; 612173362Sbenjsc uint8_t reserved1; 613173362Sbenjsc uint8_t nchan; 614282382Sadrian uint16_t quiet_time; /* timeout in milliseconds */ 615282382Sadrian#define WPI_QUIET_TIME_DEFAULT 10 616282382Sadrian 617282382Sadrian uint16_t quiet_threshold; /* min # of packets */ 618278366Sadrian uint16_t crc_threshold; 619173362Sbenjsc uint16_t reserved2; 620278366Sadrian uint32_t max_svc; /* background scans */ 621278366Sadrian uint32_t pause_svc; /* background scans */ 622173362Sbenjsc uint32_t flags; 623173362Sbenjsc uint32_t filter; 624173362Sbenjsc 625278366Sadrian /* Followed by a struct wpi_cmd_data. */ 626278366Sadrian /* Followed by an array of 4 structs wpi_scan_essid. */ 627278366Sadrian /* Followed by probe request body. */ 628278366Sadrian /* Followed by an array of ``nchan'' structs wpi_scan_chan. */ 629173362Sbenjsc} __packed; 630173362Sbenjsc 631173362Sbenjscstruct wpi_scan_chan { 632173362Sbenjsc uint8_t flags; 633278366Sadrian#define WPI_CHAN_ACTIVE (1 << 0) 634278366Sadrian#define WPI_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1) 635278366Sadrian 636173362Sbenjsc uint8_t chan; 637278366Sadrian uint8_t rf_gain; 638278366Sadrian uint8_t dsp_gain; 639173362Sbenjsc uint16_t active; /* msecs */ 640173362Sbenjsc uint16_t passive; /* msecs */ 641173362Sbenjsc} __packed; 642173362Sbenjsc 643278366Sadrian#define WPI_SCAN_CRC_TH_DEFAULT htole16(1) 644278366Sadrian#define WPI_SCAN_CRC_TH_NEVER htole16(0xffff) 645173362Sbenjsc 646278366Sadrian/* Maximum size of a scan command. */ 647278366Sadrian#define WPI_SCAN_MAXSZ (MCLBYTES - 4) 648278366Sadrian 649278366Sadrian#define WPI_ACTIVE_DWELL_TIME_2GHZ (30) /* all times in msec */ 650278366Sadrian#define WPI_ACTIVE_DWELL_TIME_5GHZ (20) 651278366Sadrian#define WPI_ACTIVE_DWELL_FACTOR_2GHZ ( 3) 652278366Sadrian#define WPI_ACTIVE_DWELL_FACTOR_5GHZ ( 2) 653278366Sadrian 654278366Sadrian#define WPI_PASSIVE_DWELL_TIME_2GHZ ( 20) 655278366Sadrian#define WPI_PASSIVE_DWELL_TIME_5GHZ ( 10) 656278366Sadrian#define WPI_PASSIVE_DWELL_BASE (100) 657282382Sadrian#define WPI_CHANNEL_TUNE_TIME ( 6) 658278366Sadrian 659278366Sadrian/* Structure for command WPI_CMD_TXPOWER. */ 660173362Sbenjscstruct wpi_cmd_txpower { 661278366Sadrian uint8_t band; 662278366Sadrian#define WPI_BAND_5GHZ 0 663278366Sadrian#define WPI_BAND_2GHZ 1 664173362Sbenjsc 665173362Sbenjsc uint8_t reserved; 666278366Sadrian uint16_t chan; 667173362Sbenjsc 668173362Sbenjsc struct { 669278366Sadrian uint8_t plcp; 670278366Sadrian uint8_t rf_gain; 671278366Sadrian uint8_t dsp_gain; 672278366Sadrian uint8_t reserved; 673278366Sadrian } __packed rates[WPI_RIDX_MAX + 1]; 674173362Sbenjsc 675173362Sbenjsc} __packed; 676173362Sbenjsc 677278366Sadrian/* Structure for command WPI_CMD_BT_COEX. */ 678278366Sadrianstruct wpi_bluetooth { 679278366Sadrian uint8_t flags; 680278366Sadrian#define WPI_BT_COEX_DISABLE 0 681278366Sadrian#define WPI_BT_COEX_MODE_2WIRE 1 682278366Sadrian#define WPI_BT_COEX_MODE_3WIRE 2 683278366Sadrian#define WPI_BT_COEX_MODE_4WIRE 3 684173362Sbenjsc 685278366Sadrian uint8_t lead_time; 686278366Sadrian#define WPI_BT_LEAD_TIME_DEF 30 687173362Sbenjsc 688278366Sadrian uint8_t max_kill; 689278366Sadrian#define WPI_BT_MAX_KILL_DEF 5 690173362Sbenjsc 691278366Sadrian uint8_t reserved; 692278366Sadrian uint32_t kill_ack; 693278366Sadrian uint32_t kill_cts; 694173362Sbenjsc} __packed; 695173362Sbenjsc 696278366Sadrian/* Structure for WPI_UC_READY notification. */ 697173362Sbenjscstruct wpi_ucode_info { 698278366Sadrian uint8_t minor; 699278366Sadrian uint8_t major; 700278366Sadrian uint16_t reserved1; 701173362Sbenjsc uint8_t revision[8]; 702173362Sbenjsc uint8_t type; 703173362Sbenjsc uint8_t subtype; 704278366Sadrian uint16_t reserved2; 705173362Sbenjsc uint32_t logptr; 706278366Sadrian uint32_t errptr; 707278366Sadrian uint32_t tstamp; 708173362Sbenjsc uint32_t valid; 709173362Sbenjsc} __packed; 710173362Sbenjsc 711278366Sadrian/* Structure for WPI_START_SCAN notification. */ 712173362Sbenjscstruct wpi_start_scan { 713173362Sbenjsc uint64_t tstamp; 714173362Sbenjsc uint32_t tbeacon; 715173362Sbenjsc uint8_t chan; 716173362Sbenjsc uint8_t band; 717173362Sbenjsc uint16_t reserved; 718173362Sbenjsc uint32_t status; 719173362Sbenjsc} __packed; 720173362Sbenjsc 721278366Sadrian/* Structure for WPI_STOP_SCAN notification. */ 722173362Sbenjscstruct wpi_stop_scan { 723173362Sbenjsc uint8_t nchan; 724173362Sbenjsc uint8_t status; 725173362Sbenjsc uint8_t reserved; 726173362Sbenjsc uint8_t chan; 727173362Sbenjsc uint64_t tsf; 728173362Sbenjsc} __packed; 729173362Sbenjsc 730278366Sadrian/* Structures for WPI_{RX,BEACON}_STATISTICS notification. */ 731278366Sadrianstruct wpi_rx_phy_stats { 732278366Sadrian uint32_t ina; 733278366Sadrian uint32_t fina; 734278366Sadrian uint32_t bad_plcp; 735278366Sadrian uint32_t bad_crc32; 736278366Sadrian uint32_t overrun; 737278366Sadrian uint32_t eoverrun; 738278366Sadrian uint32_t good_crc32; 739278366Sadrian uint32_t fa; 740278366Sadrian uint32_t bad_fina_sync; 741278366Sadrian uint32_t sfd_timeout; 742278366Sadrian uint32_t fina_timeout; 743278366Sadrian uint32_t no_rts_ack; 744278366Sadrian uint32_t rxe_limit; 745278366Sadrian uint32_t ack; 746278366Sadrian uint32_t cts; 747278366Sadrian} __packed; 748278366Sadrian 749278366Sadrianstruct wpi_rx_general_stats { 750278366Sadrian uint32_t bad_cts; 751278366Sadrian uint32_t bad_ack; 752278366Sadrian uint32_t not_bss; 753278366Sadrian uint32_t filtered; 754278366Sadrian uint32_t bad_chan; 755278366Sadrian} __packed; 756278366Sadrian 757278366Sadrianstruct wpi_rx_stats { 758278366Sadrian struct wpi_rx_phy_stats ofdm; 759278366Sadrian struct wpi_rx_phy_stats cck; 760278366Sadrian struct wpi_rx_general_stats general; 761278366Sadrian} __packed; 762278366Sadrian 763278366Sadrianstruct wpi_tx_stats { 764278366Sadrian uint32_t preamble; 765278366Sadrian uint32_t rx_detected; 766278366Sadrian uint32_t bt_defer; 767278366Sadrian uint32_t bt_kill; 768278366Sadrian uint32_t short_len; 769278366Sadrian uint32_t cts_timeout; 770278366Sadrian uint32_t ack_timeout; 771278366Sadrian uint32_t exp_ack; 772278366Sadrian uint32_t ack; 773278366Sadrian} __packed; 774278366Sadrian 775278366Sadrianstruct wpi_general_stats { 776278366Sadrian uint32_t temp; 777278366Sadrian uint32_t burst_check; 778278366Sadrian uint32_t burst; 779278366Sadrian uint32_t reserved[4]; 780278366Sadrian uint32_t sleep; 781278366Sadrian uint32_t slot_out; 782278366Sadrian uint32_t slot_idle; 783278366Sadrian uint32_t ttl_tstamp; 784278366Sadrian uint32_t tx_ant_a; 785278366Sadrian uint32_t tx_ant_b; 786278366Sadrian uint32_t exec; 787278366Sadrian uint32_t probe; 788278366Sadrian} __packed; 789278366Sadrian 790278366Sadrianstruct wpi_stats { 791278366Sadrian uint32_t flags; 792278366Sadrian struct wpi_rx_stats rx; 793278366Sadrian struct wpi_tx_stats tx; 794278366Sadrian struct wpi_general_stats general; 795278366Sadrian} __packed; 796278366Sadrian 797278366Sadrian/* Possible flags for command WPI_CMD_GET_STATISTICS. */ 798278366Sadrian#define WPI_STATISTICS_BEACON_DISABLE (1 << 1) 799278366Sadrian 800278366Sadrian 801278366Sadrian/* Firmware error dump entry. */ 802278366Sadrianstruct wpi_fw_dump { 803278366Sadrian uint32_t desc; 804278366Sadrian uint32_t time; 805278366Sadrian uint32_t blink[2]; 806278366Sadrian uint32_t ilink[2]; 807278366Sadrian uint32_t data; 808278366Sadrian} __packed; 809278366Sadrian 810278366Sadrian/* Firmware image file header. */ 811278366Sadrianstruct wpi_firmware_hdr { 812278366Sadrian 813278366Sadrian#define WPI_FW_MINVERSION 2144 814278366Sadrian#define WPI_FW_NAME "wpifw" 815278366Sadrian 816278366Sadrian uint16_t driver; 817278366Sadrian uint8_t minor; 818278366Sadrian uint8_t major; 819278366Sadrian uint32_t rtextsz; 820278366Sadrian uint32_t rdatasz; 821278366Sadrian uint32_t itextsz; 822278366Sadrian uint32_t idatasz; 823278366Sadrian uint32_t btextsz; 824278366Sadrian} __packed; 825278366Sadrian 826278366Sadrian#define WPI_FW_TEXT_MAXSZ ( 80 * 1024 ) 827278366Sadrian#define WPI_FW_DATA_MAXSZ ( 32 * 1024 ) 828278366Sadrian#define WPI_FW_BOOT_TEXT_MAXSZ 1024 829278366Sadrian 830278366Sadrian#define WPI_FW_UPDATED (1U << 31 ) 831278366Sadrian 832278366Sadrian/* 833278366Sadrian * Offsets into EEPROM. 834278366Sadrian */ 835173362Sbenjsc#define WPI_EEPROM_MAC 0x015 836173362Sbenjsc#define WPI_EEPROM_REVISION 0x035 837278366Sadrian#define WPI_EEPROM_SKU_CAP 0x045 838173362Sbenjsc#define WPI_EEPROM_TYPE 0x04a 839173362Sbenjsc#define WPI_EEPROM_DOMAIN 0x060 840173362Sbenjsc#define WPI_EEPROM_BAND1 0x063 841173362Sbenjsc#define WPI_EEPROM_BAND2 0x072 842173362Sbenjsc#define WPI_EEPROM_BAND3 0x080 843173362Sbenjsc#define WPI_EEPROM_BAND4 0x08d 844173362Sbenjsc#define WPI_EEPROM_BAND5 0x099 845173362Sbenjsc#define WPI_EEPROM_POWER_GRP 0x100 846173362Sbenjsc 847173362Sbenjscstruct wpi_eeprom_chan { 848173362Sbenjsc uint8_t flags; 849278366Sadrian#define WPI_EEPROM_CHAN_VALID (1 << 0) 850278366Sadrian#define WPI_EEPROM_CHAN_IBSS (1 << 1) 851278366Sadrian#define WPI_EEPROM_CHAN_ACTIVE (1 << 3) 852278366Sadrian#define WPI_EEPROM_CHAN_RADAR (1 << 4) 853173362Sbenjsc 854173362Sbenjsc int8_t maxpwr; 855173362Sbenjsc} __packed; 856173362Sbenjsc 857173362Sbenjscstruct wpi_eeprom_sample { 858278366Sadrian uint8_t index; 859278366Sadrian int8_t power; 860278366Sadrian uint16_t volt; 861278366Sadrian} __packed; 862173362Sbenjsc 863173362Sbenjsc#define WPI_POWER_GROUPS_COUNT 5 864173362Sbenjscstruct wpi_eeprom_group { 865278366Sadrian struct wpi_eeprom_sample samples[5]; 866278366Sadrian int32_t coef[5]; 867278366Sadrian int32_t corr[5]; 868278366Sadrian int8_t maxpwr; 869278366Sadrian uint8_t chan; 870278366Sadrian int16_t temp; 871173362Sbenjsc} __packed; 872173362Sbenjsc 873278366Sadrian#define WPI_CHAN_BANDS_COUNT 5 874173362Sbenjsc#define WPI_MAX_CHAN_PER_BAND 14 875173362Sbenjscstatic const struct wpi_chan_band { 876278366Sadrian uint32_t addr; /* offset in EEPROM */ 877278366Sadrian uint8_t nchan; 878278366Sadrian uint8_t chan[WPI_MAX_CHAN_PER_BAND]; 879278366Sadrian} wpi_bands[] = { 880278366Sadrian /* 20MHz channels, 2GHz band. */ 881278366Sadrian { WPI_EEPROM_BAND1, 14, 882278366Sadrian { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 883278366Sadrian /* 20MHz channels, 5GHz band. */ 884278366Sadrian { WPI_EEPROM_BAND2, 13, 885278366Sadrian { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 886278366Sadrian { WPI_EEPROM_BAND3, 12, 887278366Sadrian { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 888278366Sadrian { WPI_EEPROM_BAND4, 11, 889278366Sadrian { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 890278366Sadrian { WPI_EEPROM_BAND5, 6, 891278366Sadrian { 145, 149, 153, 157, 161, 165 } } 892173362Sbenjsc}; 893173362Sbenjsc 894278366Sadrian/* HW rate indices. */ 895278366Sadrian#define WPI_RIDX_OFDM6 0 896278366Sadrian#define WPI_RIDX_OFDM36 5 897278366Sadrian#define WPI_RIDX_OFDM48 6 898278366Sadrian#define WPI_RIDX_OFDM54 7 899278366Sadrian#define WPI_RIDX_CCK1 8 900278366Sadrian#define WPI_RIDX_CCK2 9 901278366Sadrian#define WPI_RIDX_CCK11 11 902278366Sadrian 903278366Sadrianstatic const uint8_t wpi_ridx_to_plcp[] = { 904278366Sadrian /* OFDM: IEEE Std 802.11a-1999, pp. 14 Table 80 */ 905278366Sadrian /* R1-R4 (ral/ural is R4-R1) */ 906278366Sadrian 0xd, 0xf, 0x5, 0x7, 0x9, 0xb, 0x1, 0x3, 907278366Sadrian /* CCK: device-dependent */ 908278366Sadrian 10, 20, 55, 110 909278366Sadrian}; 910278366Sadrian 911173362Sbenjsc#define WPI_MAX_PWR_INDEX 77 912173362Sbenjsc 913173362Sbenjsc/* 914173362Sbenjsc * RF Tx gain values from highest to lowest power (values obtained from 915173362Sbenjsc * the reference driver.) 916173362Sbenjsc */ 917173362Sbenjscstatic const uint8_t wpi_rf_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 918278366Sadrian 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xbb, 0xbb, 0xbb, 919278366Sadrian 0xbb, 0xf3, 0xf3, 0xf3, 0xf3, 0xf3, 0xd3, 0xd3, 0xb3, 0xb3, 0xb3, 920278366Sadrian 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x73, 0xeb, 0xeb, 0xeb, 921278366Sadrian 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xab, 0xab, 0xab, 0x8b, 922278366Sadrian 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xc3, 0xc3, 0xc3, 0xc3, 0xa3, 923278366Sadrian 0xa3, 0xa3, 0xa3, 0x83, 0x83, 0x83, 0x83, 0x63, 0x63, 0x63, 0x63, 924278366Sadrian 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 0x03, 0x03, 0x03, 925278366Sadrian 0x03 926173362Sbenjsc}; 927173362Sbenjsc 928173362Sbenjscstatic const uint8_t wpi_rf_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 929278366Sadrian 0xfb, 0xfb, 0xfb, 0xdb, 0xdb, 0xbb, 0xbb, 0x9b, 0x9b, 0x7b, 0x7b, 930278366Sadrian 0x7b, 0x7b, 0x5b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x1b, 0x1b, 931278366Sadrian 0x1b, 0x73, 0x73, 0x73, 0x53, 0x53, 0x53, 0x53, 0x53, 0x33, 0x33, 932278366Sadrian 0x33, 0x33, 0x13, 0x13, 0x13, 0x13, 0x13, 0xab, 0xab, 0xab, 0x8b, 933278366Sadrian 0x8b, 0x8b, 0x8b, 0x6b, 0x6b, 0x6b, 0x6b, 0x4b, 0x4b, 0x4b, 0x4b, 934278366Sadrian 0x2b, 0x2b, 0x2b, 0x2b, 0x0b, 0x0b, 0x0b, 0x0b, 0x83, 0x83, 0x63, 935278366Sadrian 0x63, 0x63, 0x63, 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 936278366Sadrian 0x03 937173362Sbenjsc}; 938173362Sbenjsc 939173362Sbenjsc/* 940173362Sbenjsc * DSP pre-DAC gain values from highest to lowest power (values obtained 941173362Sbenjsc * from the reference driver.) 942173362Sbenjsc */ 943173362Sbenjscstatic const uint8_t wpi_dsp_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 944278366Sadrian 0x7f, 0x7f, 0x7f, 0x7f, 0x7d, 0x6e, 0x69, 0x62, 0x7d, 0x73, 0x6c, 945278366Sadrian 0x63, 0x77, 0x6f, 0x69, 0x61, 0x5c, 0x6a, 0x64, 0x78, 0x71, 0x6b, 946278366Sadrian 0x7d, 0x77, 0x70, 0x6a, 0x65, 0x61, 0x5b, 0x6b, 0x79, 0x73, 0x6d, 947278366Sadrian 0x7f, 0x79, 0x73, 0x6c, 0x66, 0x60, 0x5c, 0x6e, 0x68, 0x62, 0x74, 948278366Sadrian 0x7d, 0x77, 0x71, 0x6b, 0x65, 0x60, 0x71, 0x6a, 0x66, 0x5f, 0x71, 949278366Sadrian 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 950278366Sadrian 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 951278366Sadrian 0x5f 952173362Sbenjsc}; 953173362Sbenjsc 954173362Sbenjscstatic const uint8_t wpi_dsp_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 955278366Sadrian 0x7f, 0x78, 0x72, 0x77, 0x65, 0x71, 0x66, 0x72, 0x67, 0x75, 0x6b, 956278366Sadrian 0x63, 0x5c, 0x6c, 0x7d, 0x76, 0x6d, 0x66, 0x60, 0x5a, 0x68, 0x62, 957278366Sadrian 0x5c, 0x76, 0x6f, 0x68, 0x7e, 0x79, 0x71, 0x69, 0x63, 0x76, 0x6f, 958278366Sadrian 0x68, 0x62, 0x74, 0x6d, 0x66, 0x62, 0x5d, 0x71, 0x6b, 0x63, 0x78, 959278366Sadrian 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 960278366Sadrian 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x6b, 0x63, 0x78, 961278366Sadrian 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 962278366Sadrian 0x78 963173362Sbenjsc}; 964173362Sbenjsc 965278366Sadrian/* 966278366Sadrian * Power saving settings (values obtained from the reference driver.) 967278366Sadrian */ 968278366Sadrian#define WPI_NDTIMRANGES 2 969278366Sadrian#define WPI_NPOWERLEVELS 6 970278366Sadrianstatic const struct wpi_pmgt { 971278366Sadrian uint32_t rxtimeout; 972278366Sadrian uint32_t txtimeout; 973278366Sadrian uint32_t intval[5]; 974278366Sadrian int skip_dtim; 975278366Sadrian} wpi_pmgt[WPI_NDTIMRANGES][WPI_NPOWERLEVELS] = { 976278366Sadrian /* DTIM <= 10 */ 977278366Sadrian { 978278366Sadrian { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 979278366Sadrian { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */ 980278366Sadrian { 200, 300, { 2, 4, 6, 7, 7 }, 0 }, /* PS level 2 */ 981278366Sadrian { 50, 100, { 2, 6, 9, 9, 10 }, 0 }, /* PS level 3 */ 982278366Sadrian { 50, 25, { 2, 7, 9, 9, 10 }, 1 }, /* PS level 4 */ 983278366Sadrian { 25, 25, { 4, 7, 10, 10, 10 }, 1 } /* PS level 5 */ 984278366Sadrian }, 985278366Sadrian /* DTIM >= 11 */ 986278366Sadrian { 987278366Sadrian { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */ 988278366Sadrian { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */ 989278366Sadrian { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */ 990278366Sadrian { 50, 100, { 2, 6, 9, 9, -1 }, 0 }, /* PS level 3 */ 991278366Sadrian { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */ 992278366Sadrian { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */ 993278366Sadrian } 994278366Sadrian}; 995173362Sbenjsc 996278366Sadrian/* Firmware errors. */ 997278366Sadrianstatic const char * const wpi_fw_errmsg[] = { 998278366Sadrian "OK", 999278366Sadrian "FAIL", 1000278366Sadrian "BAD_PARAM", 1001278366Sadrian "BAD_CHECKSUM", 1002278366Sadrian "NMI_INTERRUPT", 1003278366Sadrian "SYSASSERT", 1004278366Sadrian "FATAL_ERROR" 1005278366Sadrian}; 1006278366Sadrian 1007173362Sbenjsc#define WPI_READ(sc, reg) \ 1008278366Sadrian bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 1009173362Sbenjsc 1010173362Sbenjsc#define WPI_WRITE(sc, reg, val) \ 1011278366Sadrian bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1012173362Sbenjsc 1013173362Sbenjsc#define WPI_WRITE_REGION_4(sc, offset, datap, count) \ 1014278366Sadrian bus_space_write_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 1015278366Sadrian (datap), (count)) 1016278366Sadrian 1017278366Sadrian#define WPI_SETBITS(sc, reg, mask) \ 1018278366Sadrian WPI_WRITE(sc, reg, WPI_READ(sc, reg) | (mask)) 1019278366Sadrian 1020278366Sadrian#define WPI_CLRBITS(sc, reg, mask) \ 1021278366Sadrian WPI_WRITE(sc, reg, WPI_READ(sc, reg) & ~(mask)) 1022278366Sadrian 1023278366Sadrian#define WPI_BARRIER_WRITE(sc) \ 1024278366Sadrian bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1025278366Sadrian BUS_SPACE_BARRIER_WRITE) 1026278366Sadrian 1027278366Sadrian#define WPI_BARRIER_READ_WRITE(sc) \ 1028278366Sadrian bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 1029278366Sadrian BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 1030