if_wpireg.h revision 173362
159243Sobrien/* $FreeBSD: head/sys/dev/wpi/if_wpireg.h 173362 2007-11-05 11:47:19Z benjsc $ */ 259243Sobrien 359243Sobrien/*- 459243Sobrien * Copyright (c) 2006,2007 559243Sobrien * Damien Bergamini <damien.bergamini@free.fr> 659243Sobrien * 759243Sobrien * Permission to use, copy, modify, and distribute this software for any 859243Sobrien * purpose with or without fee is hereby granted, provided that the above 959243Sobrien * copyright notice and this permission notice appear in all copies. 1059243Sobrien * 1159243Sobrien * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 1259243Sobrien * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 1359243Sobrien * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 1459243Sobrien * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 1559243Sobrien * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 1659243Sobrien * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 1759243Sobrien * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 1859243Sobrien */ 1959243Sobrien 2059243Sobrien#define WPI_TX_RING_COUNT 256 2159243Sobrien#define WPI_CMD_RING_COUNT 256 2259243Sobrien#define WPI_RX_RING_COUNT 64 2359243Sobrien 2459243Sobrien/* 2559243Sobrien * Rings must be aligned on a 16K boundary. 2659243Sobrien */ 2759243Sobrien#define WPI_RING_DMA_ALIGN 0x4000 2859243Sobrien 2959243Sobrien/* maximum scatter/gather */ 3059243Sobrien#define WPI_MAX_SCATTER 4 3159243Sobrien 3259243Sobrien/* maximum Rx buffer size */ 3359243Sobrien#define WPI_RBUF_SIZE ( 3 * 1024 ) /* XXX 3000 but must be aligned */ 3459243Sobrien 3559243Sobrien/* 3659243Sobrien * Control and status registers. 3759243Sobrien */ 3859243Sobrien#define WPI_HWCONFIG 0x000 3959243Sobrien#define WPI_INTR 0x008 4059243Sobrien#define WPI_MASK 0x00c 4159243Sobrien#define WPI_INTR_STATUS 0x010 4259243Sobrien#define WPI_GPIO_STATUS 0x018 4359243Sobrien#define WPI_RESET 0x020 4459243Sobrien#define WPI_GPIO_CTL 0x024 4559243Sobrien#define WPI_EEPROM_CTL 0x02c 4659243Sobrien#define WPI_EEPROM_STATUS 0x030 4759243Sobrien#define WPI_UCODE_CLR 0x05c 4859243Sobrien#define WPI_TEMPERATURE 0x060 4959243Sobrien#define WPI_CHICKEN 0x100 5059243Sobrien#define WPI_PLL_CTL 0x20c 5159243Sobrien#define WPI_WRITE_MEM_ADDR 0x444 5259243Sobrien#define WPI_READ_MEM_ADDR 0x448 5359243Sobrien#define WPI_WRITE_MEM_DATA 0x44c 5459243Sobrien#define WPI_READ_MEM_DATA 0x450 5559243Sobrien#define WPI_TX_WIDX 0x460 5659243Sobrien#define WPI_TX_CTL(qid) (0x940 + (qid) * 8) 5759243Sobrien#define WPI_TX_BASE(qid) (0x944 + (qid) * 8) 5859243Sobrien#define WPI_TX_DESC(qid) (0x980 + (qid) * 80) 5959243Sobrien#define WPI_RX_CONFIG 0xc00 6059243Sobrien#define WPI_RX_BASE 0xc04 6159243Sobrien#define WPI_RX_WIDX 0xc20 6259243Sobrien#define WPI_RX_RIDX_PTR 0xc24 6359243Sobrien#define WPI_RX_CTL 0xcc0 6459243Sobrien#define WPI_RX_STATUS 0xcc4 6559243Sobrien#define WPI_TX_CONFIG(qid) (0xd00 + (qid) * 32) 6659243Sobrien#define WPI_TX_CREDIT(qid) (0xd04 + (qid) * 32) 6759243Sobrien#define WPI_TX_STATE(qid) (0xd08 + (qid) * 32) 6859243Sobrien#define WPI_TX_BASE_PTR 0xe80 6959243Sobrien#define WPI_MSG_CONFIG 0xe88 7059243Sobrien#define WPI_TX_STATUS 0xe90 7159243Sobrien 7259243Sobrien 7359243Sobrien/* 7459243Sobrien * NIC internal memory offsets. 7559243Sobrien */ 7659243Sobrien#define WPI_MEM_MODE 0x2e00 7759243Sobrien#define WPI_MEM_RA 0x2e04 7859243Sobrien#define WPI_MEM_TXCFG 0x2e10 7959243Sobrien#define WPI_MEM_MAGIC4 0x2e14 8059243Sobrien#define WPI_MEM_MAGIC5 0x2e20 8159243Sobrien#define WPI_MEM_BYPASS1 0x2e2c 8259243Sobrien#define WPI_MEM_BYPASS2 0x2e30 8359243Sobrien#define WPI_MEM_CLOCK1 0x3004 8459243Sobrien#define WPI_MEM_CLOCK2 0x3008 8559243Sobrien#define WPI_MEM_POWER 0x300c 8659243Sobrien#define WPI_MEM_PCIDEV 0x3010 8759243Sobrien#define WPI_MEM_HW_RADIO_OFF 0x3014 8859243Sobrien#define WPI_MEM_UCODE_CTL 0x3400 8959243Sobrien#define WPI_MEM_UCODE_SRC 0x3404 9059243Sobrien#define WPI_MEM_UCODE_DST 0x3408 9159243Sobrien#define WPI_MEM_UCODE_SIZE 0x340c 9259243Sobrien#define WPI_MEM_UCODE_BASE 0x3800 9359243Sobrien 9459243Sobrien#define WPI_MEM_TEXT_BASE 0x3490 9559243Sobrien#define WPI_MEM_TEXT_SIZE 0x3494 9659243Sobrien#define WPI_MEM_DATA_BASE 0x3498 9759243Sobrien#define WPI_MEM_DATA_SIZE 0x349c 9859243Sobrien 9959243Sobrien 10059243Sobrien/* possible flags for register WPI_HWCONFIG */ 10159243Sobrien#define WPI_HW_ALM_MB (1 << 8) 10259243Sobrien#define WPI_HW_ALM_MM (1 << 9) 10359243Sobrien#define WPI_HW_SKU_MRC (1 << 10) 10459243Sobrien#define WPI_HW_REV_D (1 << 11) 10559243Sobrien#define WPI_HW_TYPE_B (1 << 12) 10659243Sobrien 10759243Sobrien/* possible flags for registers WPI_READ_MEM_ADDR/WPI_WRITE_MEM_ADDR */ 10859243Sobrien#define WPI_MEM_4 ((sizeof (uint32_t) - 1) << 24) 10959243Sobrien 11059243Sobrien/* possible values for WPI_MEM_UCODE_DST */ 11159243Sobrien#define WPI_FW_TEXT 0x00000000 11259243Sobrien 11359243Sobrien/* possible flags for WPI_GPIO_STATUS */ 11459243Sobrien#define WPI_POWERED (1 << 9) 11559243Sobrien 11659243Sobrien/* possible flags for register WPI_RESET */ 11759243Sobrien#define WPI_NEVO_RESET (1 << 0) 11859243Sobrien#define WPI_SW_RESET (1 << 7) 11959243Sobrien#define WPI_MASTER_DISABLED (1 << 8) 12059243Sobrien#define WPI_STOP_MASTER (1 << 9) 12159243Sobrien 12259243Sobrien/* possible flags for register WPI_GPIO_CTL */ 12359243Sobrien#define WPI_GPIO_CLOCK (1 << 0) 12459243Sobrien#define WPI_GPIO_INIT (1 << 2) 12559243Sobrien#define WPI_GPIO_MAC (1 << 3) 12659243Sobrien#define WPI_GPIO_SLEEP (1 << 4) 12759243Sobrien#define WPI_GPIO_PWR_STATUS 0x07000000 12859243Sobrien#define WPI_GPIO_PWR_SLEEP (4 << 24) 12959243Sobrien 13059243Sobrien/* possible flags for register WPI_CHICKEN */ 13159243Sobrien#define WPI_CHICKEN_RXNOLOS (1 << 23) 13259243Sobrien 13359243Sobrien/* possible flags for register WPI_PLL_CTL */ 13459243Sobrien#define WPI_PLL_INIT (1 << 24) 13559243Sobrien 13659243Sobrien/* possible flags for register WPI_UCODE_CLR */ 13759243Sobrien#define WPI_RADIO_OFF (1 << 1) 13859243Sobrien#define WPI_DISABLE_CMD (1 << 2) 13959243Sobrien 14059243Sobrien/* possible flags for WPI_RX_STATUS */ 14159243Sobrien#define WPI_RX_IDLE (1 << 24) 14259243Sobrien 14359243Sobrien/* possible flags for register WPI_UC_CTL */ 14459243Sobrien#define WPI_UC_ENABLE (1 << 30) 14559243Sobrien#define WPI_UC_RUN (1 << 31) 14659243Sobrien 14759243Sobrien/* possible flags for register WPI_INTR_CSR */ 14859243Sobrien#define WPI_ALIVE_INTR (1 << 0) 14959243Sobrien#define WPI_WAKEUP_INTR (1 << 1) 15059243Sobrien#define WPI_SW_ERROR (1 << 25) 15159243Sobrien#define WPI_TX_INTR (1 << 27) 15259243Sobrien#define WPI_HW_ERROR (1 << 29) 15359243Sobrien#define WPI_RX_INTR (1 << 31) 15459243Sobrien 15559243Sobrien#define WPI_INTR_MASK \ 15659243Sobrien (WPI_SW_ERROR | WPI_HW_ERROR | WPI_TX_INTR | WPI_RX_INTR | \ 15759243Sobrien WPI_ALIVE_INTR | WPI_WAKEUP_INTR) 15859243Sobrien 15959243Sobrien/* possible flags for register WPI_TX_STATUS */ 16059243Sobrien#define WPI_TX_IDLE(qid) (1 << ((qid) + 24) | 1 << ((qid) + 16)) 16159243Sobrien 16259243Sobrien/* possible flags for register WPI_EEPROM_CTL */ 16359243Sobrien#define WPI_EEPROM_READY (1 << 0) 16459243Sobrien 16559243Sobrien/* possible flags for register WPI_EEPROM_STATUS */ 16659243Sobrien#define WPI_EEPROM_VERSION 0x00000007 16759243Sobrien#define WPI_EEPROM_LOCKED 0x00000180 16859243Sobrien 16959243Sobrien 17059243Sobrienstruct wpi_shared { 17159243Sobrien uint32_t txbase[8]; 17259243Sobrien uint32_t next; 17359243Sobrien uint32_t reserved[2]; 17459243Sobrien} __packed; 17559243Sobrien 17659243Sobrien#define WPI_MAX_SEG_LEN 65520 17759243Sobrienstruct wpi_tx_desc { 17859243Sobrien uint32_t flags; 17959243Sobrien#define WPI_PAD32(x) (roundup2(x, 4) - (x)) 18059243Sobrien 18159243Sobrien struct { 18259243Sobrien uint32_t addr; 18359243Sobrien uint32_t len; 18459243Sobrien } __attribute__((__packed__)) segs[WPI_MAX_SCATTER]; 18559243Sobrien uint8_t reserved[28]; 18659243Sobrien} __packed; 18759243Sobrien 18859243Sobrienstruct wpi_tx_stat { 18959243Sobrien uint8_t nrts; 19059243Sobrien uint8_t ntries; 19159243Sobrien uint8_t nkill; 19259243Sobrien uint8_t rate; 19359243Sobrien uint32_t duration; 19459243Sobrien uint32_t status; 19559243Sobrien} __packed; 19659243Sobrien 19759243Sobrienstruct wpi_rx_desc { 19859243Sobrien uint32_t len; 19959243Sobrien uint8_t type; 20059243Sobrien#define WPI_UC_READY 1 20159243Sobrien#define WPI_RX_DONE 27 20259243Sobrien#define WPI_TX_DONE 28 20359243Sobrien#define WPI_START_SCAN 130 20459243Sobrien#define WPI_STOP_SCAN 132 20559243Sobrien#define WPI_STATE_CHANGED 161 20659243Sobrien 20759243Sobrien uint8_t flags; 20859243Sobrien uint8_t idx; 20959243Sobrien uint8_t qid; 21059243Sobrien} __packed; 21159243Sobrien 21259243Sobrienstruct wpi_rx_stat { 21359243Sobrien uint8_t len; 21459243Sobrien#define WPI_STAT_MAXLEN 20 21559243Sobrien 21659243Sobrien uint8_t id; 21759243Sobrien uint8_t rssi; /* received signal strength */ 21859243Sobrien#define WPI_RSSI_OFFSET 95 21959243Sobrien 22059243Sobrien uint8_t agc; /* access gain control */ 22159243Sobrien uint16_t signal; 22259243Sobrien uint16_t noise; 22359243Sobrien} __packed; 22459243Sobrien 22559243Sobrienstruct wpi_rx_head { 22659243Sobrien uint16_t chan; 227 uint16_t flags; 228 uint8_t reserved; 229 uint8_t rate; 230 uint16_t len; 231} __packed; 232 233struct wpi_rx_tail { 234 uint32_t flags; 235#if 0 236#define WPI_RX_NO_CRC_ERR (1 << 0) 237#define WPI_RX_NO_OVFL_ERR (1 << 1) 238/* shortcut for the above */ 239#define WPI_RX_NOERROR (WPI_RX_NO_CRC_ERR | WPI_RX_NO_OVFL_ERR) 240#endif 241 uint64_t tstamp; 242 uint32_t tbeacon; 243} __packed; 244 245struct wpi_tx_cmd { 246 uint8_t code; 247#define WPI_CMD_CONFIGURE 16 248#define WPI_CMD_ASSOCIATE 17 249#define WPI_CMD_SET_WME 19 250#define WPI_CMD_TSF 20 251#define WPI_CMD_ADD_NODE 24 252#define WPI_CMD_TX_DATA 28 253#define WPI_CMD_MRR_SETUP 71 254#define WPI_CMD_SET_LED 72 255#define WPI_CMD_SET_POWER_MODE 119 256#define WPI_CMD_SCAN 128 257#define WPI_CMD_SET_BEACON 145 258#define WPI_CMD_TXPOWER 151 259#define WPI_CMD_BLUETOOTH 155 260 261 uint8_t flags; 262 uint8_t idx; 263 uint8_t qid; 264 uint8_t data[360]; 265} __packed; 266 267/* structure for WPI_CMD_CONFIGURE */ 268struct wpi_config { 269 uint8_t myaddr[IEEE80211_ADDR_LEN]; 270 uint16_t reserved1; 271 uint8_t bssid[IEEE80211_ADDR_LEN]; 272 uint16_t reserved2; 273 uint8_t wlap_bssid_addr[6]; 274 uint16_t reserved3; 275 uint8_t mode; 276#define WPI_MODE_HOSTAP 1 277#define WPI_MODE_STA 3 278#define WPI_MODE_IBSS 4 279#define WPI_MODE_MONITOR 6 280 281 uint8_t air_propogation; 282 uint16_t reserved4; 283 uint8_t ofdm_mask; 284 uint8_t cck_mask; 285 uint16_t associd; 286 uint32_t flags; 287#define WPI_CONFIG_24GHZ (1 << 0) 288#define WPI_CONFIG_CCK (1 << 1) 289#define WPI_CONFIG_AUTO (1 << 2) 290#define WPI_CONFIG_SHSLOT (1 << 4) 291#define WPI_CONFIG_SHPREAMBLE (1 << 5) 292#define WPI_CONFIG_NODIVERSITY (1 << 7) 293#define WPI_CONFIG_ANTENNA_A (1 << 8) 294#define WPI_CONFIG_ANTENNA_B (1 << 9) 295#define WPI_CONFIG_TSF (1 << 15) 296 297 uint32_t filter; 298#define WPI_FILTER_PROMISC (1 << 0) 299#define WPI_FILTER_CTL (1 << 1) 300#define WPI_FILTER_MULTICAST (1 << 2) 301#define WPI_FILTER_NODECRYPT (1 << 3) 302#define WPI_FILTER_BSS (1 << 5) 303#define WPI_FILTER_BEACON (1 << 6) 304 305 uint8_t chan; 306 uint16_t reserved6; 307} __packed; 308 309/* structure for command WPI_CMD_ASSOCIATE */ 310struct wpi_assoc { 311 uint32_t flags; 312 uint32_t filter; 313 uint8_t ofdm_mask; 314 uint8_t cck_mask; 315 uint16_t reserved; 316} __packed; 317 318/* structure for command WPI_CMD_SET_WME */ 319struct wpi_wme_setup { 320 uint32_t flags; 321 struct { 322 uint16_t cwmin; 323 uint16_t cwmax; 324 uint8_t aifsn; 325 uint8_t reserved; 326 uint16_t txop; 327 } __packed ac[WME_NUM_AC]; 328} __packed; 329 330/* structure for command WPI_CMD_TSF */ 331struct wpi_cmd_tsf { 332 uint64_t tstamp; 333 uint16_t bintval; 334 uint16_t atim; 335 uint32_t binitval; 336 uint16_t lintval; 337 uint16_t reserved; 338} __packed; 339 340/* structure for WPI_CMD_ADD_NODE */ 341struct wpi_node_info { 342 uint8_t control; 343#define WPI_NODE_UPDATE (1 << 0) 344 345 uint8_t reserved1[3]; 346 uint8_t bssid[IEEE80211_ADDR_LEN]; 347 uint16_t reserved2; 348 uint8_t id; 349#define WPI_ID_BSS 0 350#define WPI_ID_BROADCAST 24 351 352 uint8_t flags; 353 uint16_t reserved3; 354 uint16_t key_flags; 355 uint8_t tkip; 356 uint8_t reserved4; 357 uint16_t ttak[5]; 358 uint16_t reserved5; 359 uint8_t key[IEEE80211_KEYBUF_SIZE]; 360 uint32_t action; 361#define WPI_ACTION_SET_RATE 4 362 uint32_t mask; 363 uint16_t tid; 364 uint8_t rate; 365 uint8_t antenna; 366#define WPI_ANTENNA_A (1<<6) 367#define WPI_ANTENNA_B (1<<7) 368#define WPI_ANTENNA_BOTH (WPI_ANTENNA_A|WPI_ANTENNA_B) 369 uint8_t add_imm; 370 uint8_t del_imm; 371 uint16_t add_imm_start; 372} __packed; 373 374/* structure for command WPI_CMD_TX_DATA */ 375struct wpi_cmd_data { 376 uint16_t len; 377 uint16_t lnext; 378 uint32_t flags; 379#define WPI_TX_NEED_RTS (1 << 1) 380#define WPI_TX_NEED_CTS (1 << 2) 381#define WPI_TX_NEED_ACK (1 << 3) 382#define WPI_TX_FULL_TXOP (1 << 7) 383#define WPI_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 384#define WPI_TX_AUTO_SEQ (1 << 13) 385#define WPI_TX_INSERT_TSTAMP (1 << 16) 386 387 uint8_t rate; 388 uint8_t id; 389 uint8_t tid; 390 uint8_t security; 391 uint8_t key[IEEE80211_KEYBUF_SIZE]; 392 uint8_t tkip[IEEE80211_WEP_MICLEN]; 393 uint32_t fnext; 394 uint32_t lifetime; 395#define WPI_LIFETIME_INFINITE 0xffffffff 396 uint8_t ofdm_mask; 397 uint8_t cck_mask; 398 uint8_t rts_ntries; 399 uint8_t data_ntries; 400 uint16_t timeout; 401 uint16_t txop; 402 struct ieee80211_frame wh; 403} __packed; 404 405/* structure for command WPI_CMD_SET_BEACON */ 406struct wpi_cmd_beacon { 407 uint16_t len; 408 uint16_t reserved1; 409 uint32_t flags; /* same as wpi_cmd_data */ 410 uint8_t rate; 411 uint8_t id; 412 uint8_t reserved2[30]; 413 uint32_t lifetime; 414 uint8_t ofdm_mask; 415 uint8_t cck_mask; 416 uint16_t reserved3[3]; 417 uint16_t tim; 418 uint8_t timsz; 419 uint8_t reserved4; 420 struct ieee80211_frame wh; 421} __packed; 422 423/* structure for WPI_CMD_MRR_SETUP */ 424struct wpi_mrr_setup { 425 uint8_t which; 426#define WPI_MRR_CTL 0 427#define WPI_MRR_DATA 1 428 429 uint8_t reserved[3]; 430 431 struct { 432 uint8_t signal; 433 uint8_t flags; 434 uint8_t ntries; 435 uint8_t next; 436#define WPI_OFDM6 0 437#define WPI_OFDM54 7 438#define WPI_CCK1 8 439#define WPI_CCK2 9 440#define WPI_CCK11 11 441 442 } __attribute__((__packed__)) rates[WPI_CCK11 + 1]; 443} __packed; 444 445/* structure for WPI_CMD_SET_LED */ 446struct wpi_cmd_led { 447 uint32_t unit; /* multiplier (in usecs) */ 448 uint8_t which; 449#define WPI_LED_ACTIVITY 1 450#define WPI_LED_LINK 2 451 452 uint8_t off; 453 uint8_t on; 454 uint8_t reserved; 455} __packed; 456 457/* structure for WPI_CMD_SET_POWER_MODE */ 458struct wpi_power { 459 uint32_t flags; 460#define WPI_POWER_CAM 0 /* constantly awake mode */ 461 uint32_t rx_timeout; 462 uint32_t tx_timeout; 463 uint32_t sleep[5]; 464} __packed; 465 466/* structure for command WPI_CMD_SCAN */ 467struct wpi_scan_hdr { 468 uint16_t len; 469 uint8_t reserved1; 470 uint8_t nchan; 471 uint16_t quiet; 472 uint16_t threshold; 473 uint16_t promotion; 474 uint16_t reserved2; 475 uint32_t maxtimeout; 476 uint32_t suspend; 477 uint32_t flags; 478 uint32_t filter; 479 480struct { 481 uint16_t len; 482 uint16_t lnext; 483 uint32_t flags; 484 uint8_t rate; 485 uint8_t id; 486 uint8_t tid; 487 uint8_t security; 488 uint8_t key[IEEE80211_KEYBUF_SIZE]; 489 uint8_t tkip[IEEE80211_WEP_MICLEN]; 490 uint32_t fnext; 491 uint32_t lifetime; 492 uint8_t ofdm_mask; 493 uint8_t cck_mask; 494 uint8_t rts_ntries; 495 uint8_t data_ntries; 496 uint16_t timeout; 497 uint16_t txop; 498} tx __attribute__((__packed__)); 499 500#define WPI_SCAN_MAX_ESSIDS 4 501 struct { 502 uint8_t id; 503 uint8_t esslen; 504 uint8_t essid[32]; 505 }scan_essids[WPI_SCAN_MAX_ESSIDS]; 506 /* followed by probe request body */ 507 /* followed by nchan x wpi_scan_chan */ 508} __packed; 509 510struct wpi_scan_chan { 511 uint8_t flags; 512 uint8_t chan; 513#define WPI_CHAN_ACTIVE (1 << 0) 514#define WPI_CHAN_DIRECT (1 << 1) 515 uint8_t gain_radio; 516 uint8_t gain_dsp; 517 uint16_t active; /* msecs */ 518 uint16_t passive; /* msecs */ 519} __packed; 520 521/* structure for WPI_CMD_BLUETOOTH */ 522struct wpi_bluetooth { 523 uint8_t flags; 524 uint8_t lead; 525 uint8_t kill; 526 uint8_t reserved; 527 uint32_t ack; 528 uint32_t cts; 529} __packed; 530 531/* structure for command WPI_CMD_TXPOWER */ 532struct wpi_cmd_txpower { 533 534 uint8_t band; 535#define WPI_RATE_5GHZ 0 536#define WPI_RATE_2GHZ 1 537 uint8_t reserved; 538 uint16_t channel; 539 540#define WPI_RATE_MAPPING_COUNT 12 541 struct { 542 uint8_t rate; 543 uint8_t gain_radio; 544 uint8_t gain_dsp; 545 uint8_t reserved; 546 } __packed rates [WPI_RATE_MAPPING_COUNT]; 547 548} __packed; 549 550 551 552#define WPI_FW_MAIN_TEXT_MAXSZ (80 * 1024 ) 553#define WPI_FW_MAIN_DATA_MAXSZ (32 * 1024 ) 554#define WPI_FW_INIT_TEXT_MAXSZ (80 * 1024 ) 555#define WPI_FW_INIT_DATA_MAXSZ (32 * 1024 ) 556#define WPI_FW_BOOT_TEXT_MAXSZ 1024 557 558#define WPI_FW_UPDATED (1 << 31 ) 559 560/* firmware image header */ 561struct wpi_firmware_hdr { 562 563#define WPI_FW_MINVERSION 2144 564 565 uint32_t version; 566 uint32_t rtextsz; 567 uint32_t rdatasz; 568 uint32_t itextsz; 569 uint32_t idatasz; 570 uint32_t btextsz; 571} __packed; 572 573/* structure for WPI_UC_READY notification */ 574struct wpi_ucode_info { 575 uint32_t version; 576 uint8_t revision[8]; 577 uint8_t type; 578 uint8_t subtype; 579 uint16_t reserved; 580 uint32_t logptr; 581 uint32_t errorptr; 582 uint32_t timestamp; 583 uint32_t valid; 584} __packed; 585 586/* structure for WPI_START_SCAN notification */ 587struct wpi_start_scan { 588 uint64_t tstamp; 589 uint32_t tbeacon; 590 uint8_t chan; 591 uint8_t band; 592 uint16_t reserved; 593 uint32_t status; 594} __packed; 595 596/* structure for WPI_STOP_SCAN notification */ 597struct wpi_stop_scan { 598 uint8_t nchan; 599 uint8_t status; 600 uint8_t reserved; 601 uint8_t chan; 602 uint64_t tsf; 603} __packed; 604 605#define WPI_EEPROM_MAC 0x015 606#define WPI_EEPROM_REVISION 0x035 607#define WPI_EEPROM_CAPABILITIES 0x045 608#define WPI_EEPROM_TYPE 0x04a 609#define WPI_EEPROM_DOMAIN 0x060 610#define WPI_EEPROM_BAND1 0x063 611#define WPI_EEPROM_BAND2 0x072 612#define WPI_EEPROM_BAND3 0x080 613#define WPI_EEPROM_BAND4 0x08d 614#define WPI_EEPROM_BAND5 0x099 615#define WPI_EEPROM_POWER_GRP 0x100 616 617struct wpi_eeprom_chan { 618 uint8_t flags; 619#define WPI_EEPROM_CHAN_VALID (1<<0) 620#define WPI_EEPROM_CHAN_IBSS (1<<1) 621#define WPI_EEPROM_CHAN_ACTIVE (1<<3) 622#define WPI_EEPROM_CHAN_RADAR (1<<4) 623 624 int8_t maxpwr; 625} __packed; 626 627struct wpi_eeprom_sample { 628 uint8_t index; 629 int8_t power; 630 uint16_t volt; 631}; 632 633#define WPI_POWER_GROUPS_COUNT 5 634 635struct wpi_eeprom_group { 636 struct wpi_eeprom_sample samples[5]; 637 int32_t coef[5]; 638 int32_t corr[5]; 639 int8_t maxpwr; 640 uint8_t chan; 641 int16_t temp; 642} __packed; 643 644#define WPI_CHAN_BANDS_COUNT 5 645#define WPI_MAX_CHAN_PER_BAND 14 646 647static const struct wpi_chan_band { 648 uint32_t addr; /* offset in EEPROM */ 649 uint8_t nchan; 650 uint8_t chan[WPI_MAX_CHAN_PER_BAND]; 651} wpi_bands[5] = { 652 { WPI_EEPROM_BAND1, 14, 653 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 }}, 654 { WPI_EEPROM_BAND2, 13, 655 { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 }}, 656 { WPI_EEPROM_BAND3, 12, 657 { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 }}, 658 { WPI_EEPROM_BAND4, 11, 659 { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 }}, 660 { WPI_EEPROM_BAND5, 6, 661 { 145, 149, 153, 157, 161, 165 }} 662}; 663 664#define WPI_MAX_PWR_INDEX 77 665 666/* 667 * RF Tx gain values from highest to lowest power (values obtained from 668 * the reference driver.) 669 */ 670static const uint8_t wpi_rf_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 671 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xbb, 0xbb, 0xbb, 672 0xbb, 0xf3, 0xf3, 0xf3, 0xf3, 0xf3, 0xd3, 0xd3, 0xb3, 0xb3, 0xb3, 673 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x73, 0xeb, 0xeb, 0xeb, 674 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xab, 0xab, 0xab, 0x8b, 675 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xc3, 0xc3, 0xc3, 0xc3, 0xa3, 676 0xa3, 0xa3, 0xa3, 0x83, 0x83, 0x83, 0x83, 0x63, 0x63, 0x63, 0x63, 677 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 0x03, 0x03, 0x03, 678 0x03 679}; 680 681static const uint8_t wpi_rf_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 682 0xfb, 0xfb, 0xfb, 0xdb, 0xdb, 0xbb, 0xbb, 0x9b, 0x9b, 0x7b, 0x7b, 683 0x7b, 0x7b, 0x5b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x1b, 0x1b, 684 0x1b, 0x73, 0x73, 0x73, 0x53, 0x53, 0x53, 0x53, 0x53, 0x33, 0x33, 685 0x33, 0x33, 0x13, 0x13, 0x13, 0x13, 0x13, 0xab, 0xab, 0xab, 0x8b, 686 0x8b, 0x8b, 0x8b, 0x6b, 0x6b, 0x6b, 0x6b, 0x4b, 0x4b, 0x4b, 0x4b, 687 0x2b, 0x2b, 0x2b, 0x2b, 0x0b, 0x0b, 0x0b, 0x0b, 0x83, 0x83, 0x63, 688 0x63, 0x63, 0x63, 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 689 0x03 690}; 691 692/* 693 * DSP pre-DAC gain values from highest to lowest power (values obtained 694 * from the reference driver.) 695 */ 696static const uint8_t wpi_dsp_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 697 0x7f, 0x7f, 0x7f, 0x7f, 0x7d, 0x6e, 0x69, 0x62, 0x7d, 0x73, 0x6c, 698 0x63, 0x77, 0x6f, 0x69, 0x61, 0x5c, 0x6a, 0x64, 0x78, 0x71, 0x6b, 699 0x7d, 0x77, 0x70, 0x6a, 0x65, 0x61, 0x5b, 0x6b, 0x79, 0x73, 0x6d, 700 0x7f, 0x79, 0x73, 0x6c, 0x66, 0x60, 0x5c, 0x6e, 0x68, 0x62, 0x74, 701 0x7d, 0x77, 0x71, 0x6b, 0x65, 0x60, 0x71, 0x6a, 0x66, 0x5f, 0x71, 702 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 703 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 704 0x5f 705}; 706 707static const uint8_t wpi_dsp_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 708 0x7f, 0x78, 0x72, 0x77, 0x65, 0x71, 0x66, 0x72, 0x67, 0x75, 0x6b, 709 0x63, 0x5c, 0x6c, 0x7d, 0x76, 0x6d, 0x66, 0x60, 0x5a, 0x68, 0x62, 710 0x5c, 0x76, 0x6f, 0x68, 0x7e, 0x79, 0x71, 0x69, 0x63, 0x76, 0x6f, 711 0x68, 0x62, 0x74, 0x6d, 0x66, 0x62, 0x5d, 0x71, 0x6b, 0x63, 0x78, 712 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 713 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x6b, 0x63, 0x78, 714 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 715 0x78 716}; 717 718 719#define WPI_READ(sc, reg) \ 720 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 721 722#define WPI_WRITE(sc, reg, val) \ 723 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 724 725#define WPI_WRITE_REGION_4(sc, offset, datap, count) \ 726 bus_space_write_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 727 (datap), (count)) 728