1/*- 2 * Copyright(c) 2002-2011 Exar Corp. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification are permitted provided the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Exar Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31/*$FreeBSD$*/ 32 33#include <dev/vxge/vxgehal/vxgehal.h> 34 35/* 36 * vxge_hal_mrpcim_serial_number_get - Returns the serial number 37 * @devh: HAL device handle. 38 * 39 * Return the serial number 40 */ 41const u8 * 42vxge_hal_mrpcim_serial_number_get(vxge_hal_device_h devh) 43{ 44 __hal_device_t *hldev = (__hal_device_t *) devh; 45 46 vxge_assert(devh); 47 48 vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 49 __FILE__, __func__, __LINE__); 50 51 vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT, 52 (ptr_t) devh); 53 54 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 55 vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 56 __FILE__, __func__, __LINE__, 57 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 58 59 return (NULL); 60 } 61 62 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0", 63 __FILE__, __func__, __LINE__); 64 65 return (hldev->mrpcim->vpd_data.serial_num); 66} 67 68/* 69 * vxge_hal_mrpcim_vpath_map_get - Returns the assigned vpaths map 70 * @pdev: PCI device object. 71 * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev 72 * (Linux and the rest.) 73 * @bar0: Address of BAR0 in PCI config 74 * @func: Function Number 75 * 76 * Returns the assigned vpaths map 77 */ 78u64 79vxge_hal_mrpcim_vpath_map_get( 80 pci_dev_h pdev, 81 pci_reg_h regh0, 82 u8 *bar0, 83 u32 func) 84{ 85 u64 val64; 86 vxge_hal_legacy_reg_t *legacy_reg; 87 vxge_hal_toc_reg_t *toc_reg; 88 vxge_hal_vpath_reg_t *vpath_reg; 89 90 vxge_assert(bar0 != NULL); 91 92 vxge_hal_trace_log_driver("==> %s:%s:%d", 93 __FILE__, __func__, __LINE__); 94 95 vxge_hal_trace_log_driver( 96 "pdev = 0x"VXGE_OS_STXFMT", regh0 = 0x"VXGE_OS_STXFMT", " 97 "bar0 = 0x"VXGE_OS_STXFMT", func = %d", 98 (ptr_t) pdev, (ptr_t) regh0, (ptr_t) bar0, func); 99 100 legacy_reg = (vxge_hal_legacy_reg_t *) 101 vxge_hal_device_get_legacy_reg(pdev, regh0, bar0); 102 103 val64 = vxge_os_pio_mem_read64(pdev, regh0, 104 &legacy_reg->toc_first_pointer); 105 106 toc_reg = (vxge_hal_toc_reg_t *) ((void *)(bar0 + val64)); 107 108 val64 = vxge_os_pio_mem_read64(pdev, regh0, 109 &toc_reg->toc_vpath_pointer[0]); 110 111 vpath_reg = (vxge_hal_vpath_reg_t *) ((void *)(bar0 + val64)); 112 113 val64 = __hal_vpath_vpath_map_get(pdev, regh0, 0, 0, func, vpath_reg); 114 115 vxge_hal_trace_log_driver("<== %s:%s:%d Result = 0", 116 __FILE__, __func__, __LINE__); 117 118 return (val64); 119} 120 121/* 122 * vxge_hal_mrpcim_pcie_func_mode_set - Set PCI-E function mode 123 * @devh: Device Handle. 124 * @func_mode: PCI-E func mode. Please see vxge_hal_pcie_function_mode_e{} 125 * 126 * Set PCI-E function mode. 127 * 128 */ 129vxge_hal_status_e 130vxge_hal_mrpcim_pcie_func_mode_set( 131 vxge_hal_device_h devh, 132 vxge_hal_pcie_function_mode_e func_mode) 133{ 134 __hal_device_t *hldev = (__hal_device_t *) devh; 135 u32 fmode; 136 vxge_hal_status_e status; 137 138 vxge_assert(hldev != NULL); 139 140 vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 141 __FILE__, __func__, __LINE__); 142 143 vxge_hal_trace_log_driver("devh = 0x"VXGE_OS_STXFMT 144 ",func_mode = %d", (ptr_t) devh, func_mode); 145 146 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 147 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 148 __FILE__, __func__, __LINE__, 149 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 150 151 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 152 } 153 154 switch (func_mode) { 155 case VXGE_HAL_PCIE_FUNC_MODE_SF1_VP17: 156 fmode = 157 VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_SF1_VP17; 158 break; 159 case VXGE_HAL_PCIE_FUNC_MODE_MF8_VP2: 160 fmode = 161 VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF8_VP2; 162 break; 163 case VXGE_HAL_PCIE_FUNC_MODE_SR17_VP1: 164 fmode = 165 VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_SR17_VP1; 166 break; 167 case VXGE_HAL_PCIE_FUNC_MODE_MR17_VP1: 168 fmode = 169 VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MR17_VP1; 170 break; 171 case VXGE_HAL_PCIE_FUNC_MODE_MR8_VP2: 172 fmode = 173 VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MR8_VP2; 174 break; 175 case VXGE_HAL_PCIE_FUNC_MODE_MF17_VP1: 176 fmode = 177 VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF17_VP1; 178 break; 179 case VXGE_HAL_PCIE_FUNC_MODE_SR8_VP2: 180 fmode = 181 VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_SR8_VP2; 182 break; 183 case VXGE_HAL_PCIE_FUNC_MODE_SR4_VP4: 184 fmode = 185 VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_SR4_VP4; 186 break; 187 case VXGE_HAL_PCIE_FUNC_MODE_MF2_VP8: 188 fmode = 189 VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF2_VP8; 190 break; 191 case VXGE_HAL_PCIE_FUNC_MODE_MF4_VP4: 192 fmode = 193 VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF4_VP4; 194 break; 195 case VXGE_HAL_PCIE_FUNC_MODE_MR4_VP4: 196 fmode = 197 VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MR4_VP4; 198 break; 199 case VXGE_HAL_PCIE_FUNC_MODE_MF8P_VP2: 200 fmode = 201 VXGE_HAL_RTS_ACCESS_STEER_DATA0_FUNC_MODE_MF8P_VP2; 202 break; 203 default: 204 vxge_hal_trace_log_driver("<== %s:%s:%d Result = %d", 205 __FILE__, __func__, __LINE__, 206 VXGE_HAL_ERR_INVALID_TYPE); 207 208 return (VXGE_HAL_ERR_INVALID_TYPE); 209 } 210 211 status = __hal_vpath_pcie_func_mode_set(hldev, hldev->first_vp_id, fmode); 212 213 vxge_hal_trace_log_driver("<== %s:%s:%d Result = 0", 214 __FILE__, __func__, __LINE__); 215 216 return (status); 217 218} 219 220/* 221 * vxge_hal_mrpcim_fw_upgrade - Upgrade firmware 222 * @pdev: PCI device object. 223 * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev 224 * (Linux and the rest.) 225 * @bar0: Address of BAR0 in PCI config 226 * @buffer: Buffer containing F/W image 227 * @length: F/W image length 228 * 229 * Upgrade firmware 230 */ 231vxge_hal_status_e 232vxge_hal_mrpcim_fw_upgrade( 233 pci_dev_h pdev, 234 pci_reg_h regh0, 235 u8 *bar0, 236 u8 *buffer, 237 u32 length) 238{ 239 u64 val64, vpath_mask; 240 u32 host_type, func_id, i; 241 vxge_hal_legacy_reg_t *legacy_reg; 242 vxge_hal_toc_reg_t *toc_reg; 243 vxge_hal_mrpcim_reg_t *mrpcim_reg; 244 vxge_hal_common_reg_t *common_reg; 245 vxge_hal_vpmgmt_reg_t *vpmgmt_reg; 246 vxge_hal_vpath_reg_t *vpath_reg; 247 vxge_hal_status_e status = VXGE_HAL_OK; 248 249 vxge_assert((bar0 != NULL) && (buffer != NULL)); 250 251 vxge_hal_trace_log_driver("==> %s:%s:%d", 252 __FILE__, __func__, __LINE__); 253 254 vxge_hal_trace_log_driver( 255 "pdev = 0x"VXGE_OS_STXFMT", regh0 = 0x"VXGE_OS_STXFMT", " 256 "bar0 = 0x"VXGE_OS_STXFMT", buffer = 0x"VXGE_OS_STXFMT", " 257 "length = %d", (ptr_t) pdev, (ptr_t) regh0, (ptr_t) bar0, 258 (ptr_t) buffer, length); 259 260 legacy_reg = (vxge_hal_legacy_reg_t *) 261 vxge_hal_device_get_legacy_reg(pdev, regh0, bar0); 262 263 val64 = vxge_os_pio_mem_read64(pdev, regh0, 264 &legacy_reg->toc_first_pointer); 265 266 toc_reg = (vxge_hal_toc_reg_t *) ((void *)(bar0 + val64)); 267 268 val64 = 269 vxge_os_pio_mem_read64(pdev, regh0, &toc_reg->toc_common_pointer); 270 271 common_reg = (vxge_hal_common_reg_t *) ((void *)(bar0 + val64)); 272 273 vpath_mask = vxge_os_pio_mem_read64(pdev, regh0, 274 &common_reg->vpath_assignments); 275 276 val64 = vxge_os_pio_mem_read64(pdev, regh0, 277 &common_reg->host_type_assignments); 278 279 host_type = (u32) 280 VXGE_HAL_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64); 281 282 for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) { 283 284 if (!((vpath_mask) & mBIT(i))) 285 continue; 286 287 val64 = vxge_os_pio_mem_read64(pdev, regh0, 288 &toc_reg->toc_vpmgmt_pointer[i]); 289 290 vpmgmt_reg = (vxge_hal_vpmgmt_reg_t *) ((void *)(bar0 + val64)); 291 292 val64 = vxge_os_pio_mem_read64(pdev, regh0, 293 &vpmgmt_reg->vpath_to_func_map_cfg1); 294 295 func_id = (u32) VXGE_HAL_VPATH_TO_FUNC_MAP_CFG1_GET_CFG1(val64); 296 297 if (!(__hal_device_access_rights_get(host_type, func_id) & 298 VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 299 300 vxge_hal_trace_log_driver("<== %s:%s:%d Result = %d", 301 __FILE__, __func__, __LINE__, 302 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 303 304 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 305 } 306 307 val64 = vxge_os_pio_mem_read64(pdev, regh0, 308 &toc_reg->toc_vpath_pointer[i]); 309 310 vpath_reg = (vxge_hal_vpath_reg_t *) ((void *)(bar0 + val64)); 311 312 status = __hal_vpath_fw_upgrade(pdev, regh0, 313 i, vpath_reg, buffer, length); 314 315 break; 316 } 317 318 if (status == VXGE_HAL_OK) { 319 val64 = vxge_os_pio_mem_read64(pdev, regh0, 320 &toc_reg->toc_mrpcim_pointer); 321 322 mrpcim_reg = (vxge_hal_mrpcim_reg_t *) ((void *)(bar0 + val64)); 323 324 val64 = vxge_os_pio_mem_read64(pdev, regh0, 325 &mrpcim_reg->sw_reset_cfg1); 326 327 val64 |= VXGE_HAL_SW_RESET_CFG1_TYPE; 328 329 vxge_os_pio_mem_write64(pdev, regh0, 330 val64, 331 &mrpcim_reg->sw_reset_cfg1); 332 333 vxge_os_pio_mem_write64(pdev, regh0, 334 VXGE_HAL_PF_SW_RESET_PF_SW_RESET( 335 VXGE_HAL_PF_SW_RESET_COMMAND), 336 &mrpcim_reg->bf_sw_reset); 337 338 vxge_os_mdelay(100); 339 } 340 341 vxge_hal_trace_log_driver("<== %s:%s:%d Result = %d", 342 __FILE__, __func__, __LINE__, status); 343 344 return (status); 345} 346 347/* 348 * vxge_hal_mrpcim_vpath_qos_set - Set the priority, Guaranteed and maximum 349 * bandwidth for a vpath. 350 * @devh: HAL device handle. 351 * @vp_id: Vpath Id. 352 * @priority: Priority 353 * @min_bandwidth: Minimum Bandwidth 354 * @max_bandwidth: Maximum Bandwidth 355 * 356 * Set the Guaranteed and maximum bandwidth for a given vpath 357 * 358 */ 359vxge_hal_status_e 360vxge_hal_mrpcim_vpath_qos_set( 361 vxge_hal_device_h devh, 362 u32 vp_id, 363 u32 priority, 364 u32 min_bandwidth, 365 u32 max_bandwidth) 366{ 367 vxge_hal_status_e status = VXGE_HAL_OK; 368 vxge_hal_vpath_qos_config_t config; 369 __hal_device_t *hldev = (__hal_device_t *) devh; 370 371 vxge_assert(devh != NULL); 372 373 vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 374 __FILE__, __func__, __LINE__); 375 376 vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT", vp_id = %d, " 377 "priority = %d, min_bandwidth = %d, max_bandwidth = %d", 378 (ptr_t) devh, vp_id, priority, min_bandwidth, max_bandwidth); 379 380 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 381 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 382 __FILE__, __func__, __LINE__, 383 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 384 385 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 386 } 387 388 if (vp_id >= VXGE_HAL_MAX_VIRTUAL_PATHS) { 389 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 390 __FILE__, __func__, __LINE__, 391 VXGE_HAL_ERR_VPATH_NOT_AVAILABLE); 392 393 return (VXGE_HAL_ERR_VPATH_NOT_AVAILABLE); 394 } 395 396 config.priority = priority; 397 config.min_bandwidth = min_bandwidth; 398 config.max_bandwidth = max_bandwidth; 399 400 if ((status = __hal_vpath_qos_config_check(&config)) != VXGE_HAL_OK) { 401 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 402 __FILE__, __func__, __LINE__, status); 403 return (status); 404 } 405 406 if (status == VXGE_HAL_OK) { 407 hldev->header.config.mrpcim_config.vp_qos[vp_id].priority = 408 priority; 409 hldev->header.config.mrpcim_config.vp_qos[vp_id].min_bandwidth = 410 min_bandwidth; 411 hldev->header.config.mrpcim_config.vp_qos[vp_id].max_bandwidth = 412 max_bandwidth; 413 } 414 415 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 416 __FILE__, __func__, __LINE__, status); 417 return (status); 418} 419 420/* 421 * vxge_hal_mrpcim_vpath_qos_get - Get the priority, Guaranteed and maximum 422 * bandwidth for a vpath. 423 * @devh: HAL device handle. 424 * @vp_id: Vpath Id. 425 * @priority: Buffer to return Priority 426 * @min_bandwidth: Buffer to return Minimum Bandwidth 427 * @max_bandwidth: Buffer to return Maximum Bandwidth 428 * 429 * Get the Guaranteed and maximum bandwidth for a given vpath 430 * 431 */ 432vxge_hal_status_e 433vxge_hal_mrpcim_vpath_qos_get( 434 vxge_hal_device_h devh, 435 u32 vp_id, 436 u32 *priority, 437 u32 *min_bandwidth, 438 u32 *max_bandwidth) 439{ 440 vxge_hal_status_e status = VXGE_HAL_OK; 441 __hal_device_t *hldev = (__hal_device_t *) devh; 442 443 vxge_assert(devh != NULL); 444 445 vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 446 __FILE__, __func__, __LINE__); 447 448 vxge_hal_trace_log_mrpcim( 449 "devh = 0x"VXGE_OS_STXFMT", vp_id = %d, " 450 "priority = 0x"VXGE_OS_STXFMT", " 451 "min_bandwidth = 0x"VXGE_OS_STXFMT", " 452 "max_bandwidth = 0x"VXGE_OS_STXFMT, 453 (ptr_t) devh, vp_id, (ptr_t) priority, 454 (ptr_t) min_bandwidth, (ptr_t) max_bandwidth); 455 456 if (vp_id >= VXGE_HAL_MAX_VIRTUAL_PATHS) { 457 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 458 __FILE__, __func__, __LINE__, 459 VXGE_HAL_ERR_VPATH_NOT_AVAILABLE); 460 461 return (VXGE_HAL_ERR_VPATH_NOT_AVAILABLE); 462 } 463 464 *priority = 465 hldev->header.config.mrpcim_config.vp_qos[vp_id].min_bandwidth; 466 467 *min_bandwidth = 468 hldev->header.config.mrpcim_config.vp_qos[vp_id].min_bandwidth; 469 470 *max_bandwidth = 471 hldev->header.config.mrpcim_config.vp_qos[vp_id].max_bandwidth; 472 473 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 474 __FILE__, __func__, __LINE__, status); 475 return (status); 476} 477 478/* 479 * __hal_mrpcim_mdio_access - Access the MDIO device 480 * @devh: HAL Device handle. 481 * @port: Port id 482 * @operation: Type of operation 483 * @device: MMD device address 484 * @addr: MMD address 485 * @data: MMD data 486 * 487 * Access the data from a MDIO Device. 488 * 489 */ 490vxge_hal_status_e 491__hal_mrpcim_mdio_access( 492 vxge_hal_device_h devh, 493 u32 port, 494 u32 operation, 495 u32 device, 496 u16 addr, 497 u16 *data) 498{ 499 u64 val64; 500 u32 prtad; 501 vxge_hal_status_e status = VXGE_HAL_OK; 502 __hal_device_t *hldev = (__hal_device_t *) devh; 503 504 vxge_assert((devh != NULL) && (data != NULL)); 505 506 vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 507 __FILE__, __func__, __LINE__); 508 509 vxge_hal_trace_log_mrpcim( 510 "devh = 0x"VXGE_OS_STXFMT", operation = %d, " 511 "device = %d, addr = %d, data = 0x"VXGE_OS_STXFMT, 512 (ptr_t) devh, operation, device, addr, (ptr_t) data); 513 514 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 515 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 516 __FILE__, __func__, __LINE__, 517 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 518 519 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 520 } 521 522 if (device == VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_DTE_XS) { 523 if (port == 0) 524 prtad = hldev->mrpcim->mdio_dte_prtad0; 525 else 526 prtad = hldev->mrpcim->mdio_dte_prtad1; 527 } else { 528 if (port == 0) 529 prtad = hldev->mrpcim->mdio_phy_prtad0; 530 else 531 prtad = hldev->mrpcim->mdio_phy_prtad1; 532 } 533 534 val64 = VXGE_HAL_MDIO_MGR_ACCESS_PORT_STROBE_ONE | 535 VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE(operation) | 536 VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD(device) | 537 VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR(addr) | 538 VXGE_HAL_MDIO_MGR_ACCESS_PORT_DATA(*data) | 539 VXGE_HAL_MDIO_MGR_ACCESS_PORT_ST_PATTERN(0) | 540 VXGE_HAL_MDIO_MGR_ACCESS_PORT_PREAMBLE | 541 VXGE_HAL_MDIO_MGR_ACCESS_PORT_PRTAD(prtad) | 542 VXGE_HAL_MDIO_MGR_ACCESS_PORT_STROBE_TWO; 543 544 vxge_os_pio_mem_write64(hldev->header.pdev, 545 hldev->header.regh0, 546 val64, 547 &hldev->mrpcim_reg->mdio_mgr_access_port[port]); 548 549 vxge_os_wmb(); 550 551 status = vxge_hal_device_register_poll(hldev->header.pdev, 552 hldev->header.regh0, 553 &hldev->mrpcim_reg->mdio_mgr_access_port[port], 554 0, 555 VXGE_HAL_MDIO_MGR_ACCESS_PORT_STROBE_ONE | 556 VXGE_HAL_MDIO_MGR_ACCESS_PORT_STROBE_TWO, 557 hldev->header.config.device_poll_millis); 558 559 if ((status == VXGE_HAL_OK) && 560 ((operation == VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_READ_INCR) || 561 (operation == VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_READ) || 562 (operation == 563 VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ_INCR) || 564 (operation == VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ))) { 565 566 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 567 hldev->header.regh0, 568 &hldev->mrpcim_reg->mdio_mgr_access_port[port]); 569 570 *data = (u16) VXGE_HAL_MDIO_MGR_ACCESS_GET_PORT_DATA(val64); 571 572 } else { 573 *data = 0; 574 } 575 576 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 577 __FILE__, __func__, __LINE__, status); 578 579 return (VXGE_HAL_OK); 580} 581 582/* 583 * vxge_hal_mrpcim_intr_enable - Enable the interrupts on mrpcim. 584 * @devh: HAL device handle. 585 * 586 * Enable mrpcim interrupts 587 * 588 * See also: vxge_hal_mrpcim_intr_disable(). 589 */ 590vxge_hal_status_e 591vxge_hal_mrpcim_intr_enable(vxge_hal_device_h devh) 592{ 593 u32 i; 594 u64 val64; 595 vxge_hal_status_e status = VXGE_HAL_OK; 596 vxge_hal_mrpcim_reg_t *mrpcim_reg; 597 __hal_device_t *hldev = (__hal_device_t *) devh; 598 599 vxge_assert(devh); 600 601 vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 602 __FILE__, __func__, __LINE__); 603 604 vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT, 605 (ptr_t) devh); 606 607 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 608 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 609 __FILE__, __func__, __LINE__, 610 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 611 612 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 613 614 } 615 616 mrpcim_reg = hldev->mrpcim_reg; 617 618 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->ini_errors_reg); 619 620 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->dma_errors_reg); 621 622 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->tgt_errors_reg); 623 624 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->config_errors_reg); 625 626 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->crdt_errors_reg); 627 628 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->mrpcim_general_errors_reg); 629 630 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->pll_errors_reg); 631 632 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->mrpcim_ppif_int_status); 633 634 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->dbecc_err_reg); 635 636 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->general_err_reg); 637 638 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->pcipif_int_status); 639 640 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->pda_alarm_reg); 641 642 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->pcc_error_reg); 643 644 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->lso_error_reg); 645 646 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->sm_error_reg); 647 648 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rtdma_int_status); 649 650 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rc_alarm_reg); 651 652 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rxdrm_sm_err_reg); 653 654 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rxdcm_sm_err_reg); 655 656 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rxdwm_sm_err_reg); 657 658 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rda_err_reg); 659 660 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rda_ecc_db_reg); 661 662 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rqa_err_reg); 663 664 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->frf_alarm_reg); 665 666 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rocrc_alarm_reg); 667 668 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->wde0_alarm_reg); 669 670 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->wde1_alarm_reg); 671 672 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->wde2_alarm_reg); 673 674 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->wde3_alarm_reg); 675 676 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->wrdma_int_status); 677 678 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3cmct_err_reg); 679 680 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3cmct_int_status); 681 682 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->gsscc_err_reg); 683 684 for (i = 0; i < 3; i++) { 685 686 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->gssc_err0_reg[i]); 687 688 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->gssc_err1_reg[i]); 689 690 } 691 692 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->gcmg1_int_status); 693 694 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->gxtmc_err_reg); 695 696 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->gcp_err_reg); 697 698 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->cmc_err_reg); 699 700 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->gcmg2_int_status); 701 702 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3ifcmd_cml_err_reg); 703 704 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3ifcmd_cml_int_status); 705 706 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3ifcmd_cmu_err_reg); 707 708 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3ifcmd_cmu_int_status); 709 710 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->psscc_err_reg); 711 712 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->pcmg1_int_status); 713 714 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->pxtmc_err_reg); 715 716 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->cp_exc_reg); 717 718 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->cp_err_reg); 719 720 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->pcmg2_int_status); 721 722 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->dam_err_reg); 723 724 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->pcmg3_int_status); 725 726 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->xmac_gen_err_reg); 727 728 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->xgxs_gen_err_reg); 729 730 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->asic_ntwk_err_reg); 731 732 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->xgmac_int_status); 733 734 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rxmac_ecc_err_reg); 735 736 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rxmac_various_err_reg); 737 738 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->rxmac_int_status); 739 740 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->txmac_gen_err_reg); 741 742 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->txmac_ecc_err_reg); 743 744 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->tmac_int_status); 745 746 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3ifcmd_fb_err_reg); 747 748 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3ifcmd_fb_int_status); 749 750 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->mc_err_reg); 751 752 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->grocrc_alarm_reg); 753 754 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->fau_ecc_err_reg); 755 756 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->mc_int_status); 757 758 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3fbct_err_reg); 759 760 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->g3fbct_int_status); 761 762 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->orp_err_reg); 763 764 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->ptm_alarm_reg); 765 766 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->tpa_error_reg); 767 768 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->tpa_int_status); 769 770 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->kdfc_err_reg); 771 772 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->doorbell_int_status); 773 774 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->tim_err_reg); 775 776 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->msg_exc_reg); 777 778 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->msg_err_reg); 779 780 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->msg_err2_reg); 781 782 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->msg_err3_reg); 783 784 VXGE_HAL_MRPCIM_ERROR_REG_CLEAR(&mrpcim_reg->msg_int_status); 785 786 vxge_os_pio_mem_read64(hldev->header.pdev, 787 hldev->header.regh0, 788 &mrpcim_reg->mrpcim_general_int_status); 789 790 /* unmask interrupts */ 791 val64 = VXGE_HAL_INI_ERRORS_REG_DCPL_FSM_ERR | 792 VXGE_HAL_INI_ERRORS_REG_INI_BUF_DB_ERR | 793 VXGE_HAL_INI_ERRORS_REG_INI_DATA_OVERFLOW | 794 VXGE_HAL_INI_ERRORS_REG_INI_HDR_OVERFLOW; 795 796 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->ini_errors_mask); 797 798 val64 = VXGE_HAL_DMA_ERRORS_REG_RDARB_FSM_ERR | 799 VXGE_HAL_DMA_ERRORS_REG_WRARB_FSM_ERR | 800 VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_WR_HDR_OVERFLOW | 801 VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_WR_HDR_UNDERFLOW | 802 VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_WR_DATA_OVERFLOW | 803 VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_WR_DATA_UNDERFLOW | 804 VXGE_HAL_DMA_ERRORS_REG_DMA_MSG_WR_HDR_OVERFLOW | 805 VXGE_HAL_DMA_ERRORS_REG_DMA_MSG_WR_HDR_UNDERFLOW | 806 VXGE_HAL_DMA_ERRORS_REG_DMA_MSG_WR_DATA_OVERFLOW | 807 VXGE_HAL_DMA_ERRORS_REG_DMA_MSG_WR_DATA_UNDERFLOW | 808 VXGE_HAL_DMA_ERRORS_REG_DMA_STATS_WR_HDR_OVERFLOW | 809 VXGE_HAL_DMA_ERRORS_REG_DMA_STATS_WR_HDR_UNDERFLOW | 810 VXGE_HAL_DMA_ERRORS_REG_DMA_STATS_WR_DATA_OVERFLOW | 811 VXGE_HAL_DMA_ERRORS_REG_DMA_STATS_WR_DATA_UNDERFLOW | 812 VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_WR_HDR_OVERFLOW | 813 VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_WR_HDR_UNDERFLOW | 814 VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_WR_DATA_OVERFLOW | 815 VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_WR_DATA_UNDERFLOW | 816 VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_RD_HDR_OVERFLOW | 817 VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_RD_HDR_UNDERFLOW | 818 VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_RD_HDR_OVERFLOW | 819 VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_RD_HDR_UNDERFLOW | 820 VXGE_HAL_DMA_ERRORS_REG_DBLGEN_FSM_ERR | 821 VXGE_HAL_DMA_ERRORS_REG_DBLGEN_CREDIT_FSM_ERR | 822 VXGE_HAL_DMA_ERRORS_REG_DBLGEN_DMA_WRR_SM_ERR; 823 824 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->dma_errors_mask); 825 826 val64 = VXGE_HAL_TGT_ERRORS_REG_TGT_REQ_FSM_ERR | 827 VXGE_HAL_TGT_ERRORS_REG_TGT_CPL_FSM_ERR; 828 829 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->tgt_errors_mask); 830 831 val64 = VXGE_HAL_CONFIG_ERRORS_REG_I2C_MAIN_FSM_ERR | 832 VXGE_HAL_CONFIG_ERRORS_REG_I2C_REG_FSM_ERR | 833 VXGE_HAL_CONFIG_ERRORS_REG_CFGM_I2C_TIMEOUT | 834 VXGE_HAL_CONFIG_ERRORS_REG_RIC_I2C_TIMEOUT | 835 VXGE_HAL_CONFIG_ERRORS_REG_CFGM_FSM_ERR | 836 VXGE_HAL_CONFIG_ERRORS_REG_RIC_FSM_ERR | 837 VXGE_HAL_CONFIG_ERRORS_REG_PIFM_TIMEOUT | 838 VXGE_HAL_CONFIG_ERRORS_REG_PIFM_FSM_ERR | 839 VXGE_HAL_CONFIG_ERRORS_REG_PIFM_TO_FSM_ERR | 840 VXGE_HAL_CONFIG_ERRORS_REG_RIC_RIC_RD_TIMEOUT; 841 842 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 843 &mrpcim_reg->config_errors_mask); 844 845 val64 = VXGE_HAL_CRDT_ERRORS_REG_WRCRDTARB_FSM_ERR | 846 VXGE_HAL_CRDT_ERRORS_REG_WRCRDTARB_INTCTL_ILLEGAL_CRD_DEAL | 847 VXGE_HAL_CRDT_ERRORS_REG_WRCRDTARB_PDA_ILLEGAL_CRD_DEAL | 848 VXGE_HAL_CRDT_ERRORS_REG_WRCRDTARB_PCI_MSG_ILLEGAL_CRD_DEAL | 849 VXGE_HAL_CRDT_ERRORS_REG_RDCRDTARB_FSM_ERR | 850 VXGE_HAL_CRDT_ERRORS_REG_RDCRDTARB_RDA_ILLEGAL_CRD_DEAL | 851 VXGE_HAL_CRDT_ERRORS_REG_RDCRDTARB_PDA_ILLEGAL_CRD_DEAL | 852 VXGE_HAL_CRDT_ERRORS_REG_RDCRDTARB_DBLGEN_ILLEGAL_CRD_DEAL; 853 854 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->crdt_errors_mask); 855 856 val64 = VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_STATSB_FSM_ERR | 857 VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_XGEN_FSM_ERR | 858 VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_XMEM_FSM_ERR | 859 VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_KDFCCTL_FSM_ERR | 860 VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_MRIOVCTL_FSM_ERR | 861 VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_SPI_FLSH_ERR | 862 VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_SPI_IIC_ACK_ERR | 863 VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_SPI_IIC_CHKSUM_ERR | 864 VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_INI_SERR_DET | 865 VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_INTCTL_MSIX_FSM_ERR | 866 VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_INTCTL_MSI_OVERFLOW | 867 VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_PPIF_PCI_NOT_FLUSH_SW_RESET | 868 VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_PPIF_SW_RESET_FSM_ERR; 869 870 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 871 &mrpcim_reg->mrpcim_general_errors_mask); 872 873 val64 = VXGE_HAL_PLL_ERRORS_REG_CORE_CMG_PLL_OOL | 874 VXGE_HAL_PLL_ERRORS_REG_CORE_FB_PLL_OOL | 875 VXGE_HAL_PLL_ERRORS_REG_CORE_X_PLL_OOL; 876 877 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pll_errors_mask); 878 879 val64 = VXGE_HAL_MRPCIM_PPIF_INT_STATUS_INI_ERRORS_INI_INT | 880 VXGE_HAL_MRPCIM_PPIF_INT_STATUS_DMA_ERRORS_DMA_INT | 881 VXGE_HAL_MRPCIM_PPIF_INT_STATUS_TGT_ERRORS_TGT_INT | 882 VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CONFIG_ERRORS_CONFIG_INT | 883 VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_CRDT_INT | 884 VXGE_HAL_MRPCIM_PPIF_INT_STATUS_MRPCIM_GENERAL_ERRORS_GENERAL_INT | 885 VXGE_HAL_MRPCIM_PPIF_INT_STATUS_PLL_ERRORS_PLL_INT; 886 887 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 888 &mrpcim_reg->mrpcim_ppif_int_mask); 889 890 val64 = VXGE_HAL_DBECC_ERR_REG_PCI_RETRY_BUF_DB_ERR | 891 VXGE_HAL_DBECC_ERR_REG_PCI_RETRY_SOT_DB_ERR | 892 VXGE_HAL_DBECC_ERR_REG_PCI_P_HDR_DB_ERR | 893 VXGE_HAL_DBECC_ERR_REG_PCI_P_DATA_DB_ERR | 894 VXGE_HAL_DBECC_ERR_REG_PCI_NP_HDR_DB_ERR | 895 VXGE_HAL_DBECC_ERR_REG_PCI_NP_DATA_DB_ERR; 896 897 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->dbecc_err_mask); 898 899 val64 = VXGE_HAL_GENERAL_ERR_REG_PCI_LINK_RST_FSM_ERR; 900 901 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->general_err_mask); 902 903 val64 = VXGE_HAL_PCIPIF_INT_STATUS_DBECC_ERR_DBECC_ERR_INT | 904 VXGE_HAL_PCIPIF_INT_STATUS_GENERAL_ERR_GENERAL_ERR_INT; 905 906 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pcipif_int_mask); 907 908 val64 = VXGE_HAL_PDA_ALARM_REG_PDA_SM_ERR; 909 910 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pda_alarm_mask); 911 912 val64 = 0; 913 914 for (i = 0; i < 8; i++) { 915 val64 |= VXGE_HAL_PCC_ERROR_REG_PCC_PCC_FRM_BUF_DBE(i) | 916 VXGE_HAL_PCC_ERROR_REG_PCC_PCC_TXDO_DBE(i) | 917 VXGE_HAL_PCC_ERROR_REG_PCC_PCC_FSM_ERR_ALARM(i) | 918 VXGE_HAL_PCC_ERROR_REG_PCC_PCC_SERR(i); 919 } 920 921 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pcc_error_mask); 922 923 val64 = 0; 924 925 for (i = 0; i < 8; i++) { 926 val64 |= VXGE_HAL_LSO_ERROR_REG_PCC_LSO_FSM_ERR_ALARM(i); 927 } 928 929 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->lso_error_mask); 930 931 val64 = VXGE_HAL_SM_ERROR_REG_SM_FSM_ERR_ALARM; 932 933 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->sm_error_mask); 934 935 val64 = VXGE_HAL_RTDMA_INT_STATUS_PDA_ALARM_PDA_INT | 936 VXGE_HAL_RTDMA_INT_STATUS_PCC_ERROR_PCC_INT | 937 VXGE_HAL_RTDMA_INT_STATUS_LSO_ERROR_LSO_INT | 938 VXGE_HAL_RTDMA_INT_STATUS_SM_ERROR_SM_INT; 939 940 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rtdma_int_mask); 941 942 val64 = VXGE_HAL_RC_ALARM_REG_FTC_SM_ERR | 943 VXGE_HAL_RC_ALARM_REG_FTC_SM_PHASE_ERR | 944 VXGE_HAL_RC_ALARM_REG_BTDWM_SM_ERR | 945 VXGE_HAL_RC_ALARM_REG_BTC_SM_ERR | 946 VXGE_HAL_RC_ALARM_REG_BTDCM_SM_ERR | 947 VXGE_HAL_RC_ALARM_REG_BTDRM_SM_ERR | 948 VXGE_HAL_RC_ALARM_REG_RMM_RXD_RC_ECC_DB_ERR | 949 VXGE_HAL_RC_ALARM_REG_RHS_RXD_RHS_ECC_DB_ERR | 950 VXGE_HAL_RC_ALARM_REG_RMM_SM_ERR | 951 VXGE_HAL_RC_ALARM_REG_BTC_VPATH_MISMATCH_ERR; 952 953 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rc_alarm_mask); 954 955 val64 = 0; 956 957 for (i = 0; i < 17; i++) { 958 val64 |= VXGE_HAL_RXDRM_SM_ERR_REG_PRC_VP(i); 959 } 960 961 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rxdrm_sm_err_mask); 962 963 val64 = 0; 964 965 for (i = 0; i < 17; i++) { 966 val64 |= VXGE_HAL_RXDCM_SM_ERR_REG_PRC_VP(i); 967 } 968 969 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rxdcm_sm_err_mask); 970 971 val64 = 0; 972 973 for (i = 0; i < 17; i++) { 974 val64 |= VXGE_HAL_RXDWM_SM_ERR_REG_PRC_VP(i); 975 } 976 977 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rxdwm_sm_err_mask); 978 979 val64 = VXGE_HAL_RDA_ERR_REG_RDA_SM0_ERR_ALARM | 980 VXGE_HAL_RDA_ERR_REG_RDA_RXD_ECC_DB_ERR | 981 VXGE_HAL_RDA_ERR_REG_RDA_FRM_ECC_DB_ERR | 982 VXGE_HAL_RDA_ERR_REG_RDA_UQM_ECC_DB_ERR | 983 VXGE_HAL_RDA_ERR_REG_RDA_IMM_ECC_DB_ERR | 984 VXGE_HAL_RDA_ERR_REG_RDA_TIM_ECC_DB_ERR; 985 986 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rda_err_mask); 987 988 val64 = 0; 989 990 for (i = 0; i < 17; i++) { 991 val64 |= VXGE_HAL_RDA_ECC_DB_REG_RDA_RXD_ERR(i); 992 } 993 994 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rda_ecc_db_mask); 995 996 val64 = VXGE_HAL_RQA_ERR_REG_RQA_SM_ERR_ALARM; 997 998 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rqa_err_mask); 999 1000 val64 = 0; 1001 1002 for (i = 0; i < 17; i++) { 1003 val64 |= VXGE_HAL_FRF_ALARM_REG_PRC_VP_FRF_SM_ERR(i); 1004 } 1005 1006 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->frf_alarm_mask); 1007 1008 val64 = VXGE_HAL_ROCRC_ALARM_REG_QCQ_QCC_BYP_ECC_DB | 1009 VXGE_HAL_ROCRC_ALARM_REG_NOA_NMA_SM_ERR | 1010 VXGE_HAL_ROCRC_ALARM_REG_NOA_IMMM_ECC_DB | 1011 VXGE_HAL_ROCRC_ALARM_REG_UDQ_UMQM_ECC_DB | 1012 VXGE_HAL_ROCRC_ALARM_REG_NOA_RCBM_ECC_DB | 1013 VXGE_HAL_ROCRC_ALARM_REG_NOA_WCT_CMD_FIFO_ERR; 1014 1015 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rocrc_alarm_mask); 1016 1017 val64 = VXGE_HAL_WDE0_ALARM_REG_WDE0_DCC_SM_ERR | 1018 VXGE_HAL_WDE0_ALARM_REG_WDE0_PRM_SM_ERR | 1019 VXGE_HAL_WDE0_ALARM_REG_WDE0_CP_SM_ERR | 1020 VXGE_HAL_WDE0_ALARM_REG_WDE0_CP_CMD_ERR | 1021 VXGE_HAL_WDE0_ALARM_REG_WDE0_PCR_SM_ERR; 1022 1023 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->wde0_alarm_mask); 1024 1025 val64 = VXGE_HAL_WDE1_ALARM_REG_WDE1_DCC_SM_ERR | 1026 VXGE_HAL_WDE1_ALARM_REG_WDE1_PRM_SM_ERR | 1027 VXGE_HAL_WDE1_ALARM_REG_WDE1_CP_SM_ERR | 1028 VXGE_HAL_WDE1_ALARM_REG_WDE1_CP_CMD_ERR | 1029 VXGE_HAL_WDE1_ALARM_REG_WDE1_PCR_SM_ERR; 1030 1031 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->wde1_alarm_mask); 1032 1033 val64 = VXGE_HAL_WDE2_ALARM_REG_WDE2_DCC_SM_ERR | 1034 VXGE_HAL_WDE2_ALARM_REG_WDE2_PRM_SM_ERR | 1035 VXGE_HAL_WDE2_ALARM_REG_WDE2_CP_SM_ERR | 1036 VXGE_HAL_WDE2_ALARM_REG_WDE2_CP_CMD_ERR | 1037 VXGE_HAL_WDE2_ALARM_REG_WDE2_PCR_SM_ERR; 1038 1039 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->wde2_alarm_mask); 1040 1041 val64 = VXGE_HAL_WDE3_ALARM_REG_WDE3_DCC_SM_ERR | 1042 VXGE_HAL_WDE3_ALARM_REG_WDE3_PRM_SM_ERR | 1043 VXGE_HAL_WDE3_ALARM_REG_WDE3_CP_SM_ERR | 1044 VXGE_HAL_WDE3_ALARM_REG_WDE3_CP_CMD_ERR | 1045 VXGE_HAL_WDE3_ALARM_REG_WDE3_PCR_SM_ERR; 1046 1047 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->wde3_alarm_mask); 1048 1049 val64 = VXGE_HAL_WRDMA_INT_STATUS_RC_ALARM_RC_INT | 1050 VXGE_HAL_WRDMA_INT_STATUS_RXDRM_SM_ERR_RXDRM_INT | 1051 VXGE_HAL_WRDMA_INT_STATUS_RXDCM_SM_ERR_RXDCM_SM_INT | 1052 VXGE_HAL_WRDMA_INT_STATUS_RXDWM_SM_ERR_RXDWM_INT | 1053 VXGE_HAL_WRDMA_INT_STATUS_RDA_ERR_RDA_INT | 1054 VXGE_HAL_WRDMA_INT_STATUS_RDA_ECC_DB_RDA_ECC_DB_INT | 1055 VXGE_HAL_WRDMA_INT_STATUS_FRF_ALARM_FRF_INT | 1056 VXGE_HAL_WRDMA_INT_STATUS_ROCRC_ALARM_ROCRC_INT | 1057 VXGE_HAL_WRDMA_INT_STATUS_WDE0_ALARM_WDE0_INT | 1058 VXGE_HAL_WRDMA_INT_STATUS_WDE1_ALARM_WDE1_INT | 1059 VXGE_HAL_WRDMA_INT_STATUS_WDE2_ALARM_WDE2_INT | 1060 VXGE_HAL_WRDMA_INT_STATUS_WDE3_ALARM_WDE3_INT; 1061 1062 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->wrdma_int_mask); 1063 1064 val64 = VXGE_HAL_G3CMCT_ERR_REG_G3IF_SM_ERR | 1065 VXGE_HAL_G3CMCT_ERR_REG_G3IF_GDDR3_DECC | 1066 VXGE_HAL_G3CMCT_ERR_REG_G3IF_GDDR3_U_DECC | 1067 VXGE_HAL_G3CMCT_ERR_REG_G3IF_CTRL_FIFO_DECC; 1068 1069 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->g3cmct_err_mask); 1070 1071 val64 = VXGE_HAL_G3CMCT_INT_STATUS_ERR_G3IF_INT; 1072 1073 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->g3cmct_int_mask); 1074 1075 val64 = VXGE_HAL_GSSCC_ERR_REG_SSCC_SSR_DB_ERR(0x3) | 1076 VXGE_HAL_GSSCC_ERR_REG_SSCC_TSR_DB_ERR(0x3f) | 1077 VXGE_HAL_GSSCC_ERR_REG_SSCC_CP2STE_UFLOW_ERR | 1078 VXGE_HAL_GSSCC_ERR_REG_SSCC_CP2TTE_UFLOW_ERR; 1079 1080 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->gsscc_err_mask); 1081 1082 for (i = 0; i < 3; i++) { 1083 1084 val64 = VXGE_HAL_GSSC_ERR0_REG_SSCC_STATE_DB_ERR(0xff) | 1085 VXGE_HAL_GSSC_ERR0_REG_SSCC_CM_RESP_DB_ERR(0xf) | 1086 VXGE_HAL_GSSC_ERR0_REG_SSCC_SSR_RESP_DB_ERR(0x3) | 1087 VXGE_HAL_GSSC_ERR0_REG_SSCC_TSR_RESP_DB_ERR(0x3f); 1088 1089 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1090 &mrpcim_reg->gssc_err0_mask[i]); 1091 1092 val64 = VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_RESP_DB_ERR | 1093 VXGE_HAL_GSSC_ERR1_REG_SSCC_SCREQ_ERR | 1094 VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_RESP_OFLOW_ERR | 1095 VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_RESP_R_WN_ERR | 1096 VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_RESP_UFLOW_ERR | 1097 VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_REQ_OFLOW_ERR | 1098 VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_REQ_UFLOW_ERR | 1099 VXGE_HAL_GSSC_ERR1_REG_SSCC_FSM_OFLOW_ERR | 1100 VXGE_HAL_GSSC_ERR1_REG_SSCC_FSM_UFLOW_ERR | 1101 VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_REQ_OFLOW_ERR | 1102 VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_REQ_UFLOW_ERR | 1103 VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_RESP_OFLOW_ERR | 1104 VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_RESP_R_WN_ERR | 1105 VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_RESP_UFLOW_ERR | 1106 VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_REQ_OFLOW_ERR | 1107 VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_REQ_UFLOW_ERR | 1108 VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_RESP_OFLOW_ERR | 1109 VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_RESP_R_WN_ERR | 1110 VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_RESP_UFLOW_ERR | 1111 VXGE_HAL_GSSC_ERR1_REG_SSCC_SCRESP_ERR; 1112 1113 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1114 &mrpcim_reg->gssc_err1_mask[i]); 1115 1116 } 1117 1118 val64 = VXGE_HAL_GCMG1_INT_STATUS_GSSCC_ERR_GSSCC_INT | 1119 VXGE_HAL_GCMG1_INT_STATUS_GSSC0_ERR0_GSSC0_0_INT | 1120 VXGE_HAL_GCMG1_INT_STATUS_GSSC0_ERR1_GSSC0_1_INT | 1121 VXGE_HAL_GCMG1_INT_STATUS_GSSC1_ERR0_GSSC1_0_INT | 1122 VXGE_HAL_GCMG1_INT_STATUS_GSSC1_ERR1_GSSC1_1_INT | 1123 VXGE_HAL_GCMG1_INT_STATUS_GSSC2_ERR0_GSSC2_0_INT | 1124 VXGE_HAL_GCMG1_INT_STATUS_GSSC2_ERR1_GSSC2_1_INT; 1125 1126 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->gcmg1_int_mask); 1127 1128 val64 = VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_MEM_DB_ERR(0xf) | 1129 VXGE_HAL_GXTMC_ERR_REG_XTMC_CMC_RD_DATA_DB_ERR | 1130 VXGE_HAL_GXTMC_ERR_REG_XTMC_REQ_FIFO_ERR | 1131 VXGE_HAL_GXTMC_ERR_REG_XTMC_REQ_DATA_FIFO_ERR | 1132 VXGE_HAL_GXTMC_ERR_REG_XTMC_WR_RSP_FIFO_ERR | 1133 VXGE_HAL_GXTMC_ERR_REG_XTMC_RD_RSP_FIFO_ERR | 1134 VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_WRP_FIFO_ERR | 1135 VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_WRP_ERR | 1136 VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_RRP_FIFO_ERR | 1137 VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_RRP_ERR | 1138 VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_DATA_SM_ERR | 1139 VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_CMC0_IF_ERR | 1140 VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_CFC_SM_ERR | 1141 VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_CREDIT_OVERFLOW | 1142 VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_CREDIT_UNDERFLOW | 1143 VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_SM_ERR | 1144 VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_CREDIT_OVERFLOW | 1145 VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_CREDIT_UNDERFLOW | 1146 VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_SM_ERR | 1147 VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_WCOMPL_SM_ERR | 1148 VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_WCOMPL_TAG_ERR | 1149 VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_WREQ_SM_ERR | 1150 VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_WREQ_FIFO_ERR | 1151 VXGE_HAL_GXTMC_ERR_REG_XTMC_CP2BDT_RFIFO_POP_ERR | 1152 VXGE_HAL_GXTMC_ERR_REG_XTMC_XTMC_BDT_CMI_OP_ERR | 1153 VXGE_HAL_GXTMC_ERR_REG_XTMC_XTMC_BDT_DFETCH_OP_ERR | 1154 VXGE_HAL_GXTMC_ERR_REG_XTMC_XTMC_BDT_DFIFO_ERR | 1155 VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_ARB_SM_ERR; 1156 1157 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->gxtmc_err_mask); 1158 1159 val64 = VXGE_HAL_GCP_ERR_REG_CP_H2L2CP_FIFO_ERR | 1160 VXGE_HAL_GCP_ERR_REG_CP_STC2CP_FIFO_ERR | 1161 VXGE_HAL_GCP_ERR_REG_CP_STE2CP_FIFO_ERR | 1162 VXGE_HAL_GCP_ERR_REG_CP_TTE2CP_FIFO_ERR; 1163 1164 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->gcp_err_mask); 1165 1166 val64 = VXGE_HAL_CMC_ERR_REG_CMC_CMC_SM_ERR; 1167 1168 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->cmc_err_mask); 1169 1170 val64 = VXGE_HAL_GCMG2_INT_STATUS_GXTMC_ERR_GXTMC_INT | 1171 VXGE_HAL_GCMG2_INT_STATUS_GCP_ERR_GCP_INT | 1172 VXGE_HAL_GCMG2_INT_STATUS_CMC_ERR_CMC_INT; 1173 1174 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->gcmg2_int_mask); 1175 1176 val64 = VXGE_HAL_G3IFCMD_CML_ERR_REG_G3IF_SM_ERR; 1177 1178 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1179 &mrpcim_reg->g3ifcmd_cml_err_mask); 1180 1181 val64 = VXGE_HAL_G3IFCMD_CML_INT_STATUS_ERR_G3IF_INT; 1182 1183 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1184 &mrpcim_reg->g3ifcmd_cml_int_mask); 1185 1186 val64 = VXGE_HAL_G3IFCMD_CMU_ERR_REG_G3IF_SM_ERR; 1187 1188 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1189 &mrpcim_reg->g3ifcmd_cmu_err_mask); 1190 1191 val64 = VXGE_HAL_G3IFCMD_CMU_INT_STATUS_ERR_G3IF_INT; 1192 1193 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1194 &mrpcim_reg->g3ifcmd_cmu_int_mask); 1195 1196 val64 = VXGE_HAL_PSSCC_ERR_REG_SSCC_CP2STE_OFLOW_ERR | 1197 VXGE_HAL_PSSCC_ERR_REG_SSCC_CP2TTE_OFLOW_ERR; 1198 1199 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1200 &mrpcim_reg->psscc_err_mask); 1201 1202 val64 = VXGE_HAL_PCMG1_INT_STATUS_PSSCC_ERR_PSSCC_INT; 1203 1204 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1205 &mrpcim_reg->pcmg1_int_mask); 1206 1207 val64 = VXGE_HAL_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_DB_ERR(0x3) | 1208 VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_REQ_FIFO_ERR | 1209 VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_PRSP_FIFO_ERR | 1210 VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_WRSP_FIFO_ERR | 1211 VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_REQ_FIFO_ERR | 1212 VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_PRSP_FIFO_ERR | 1213 VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_WRSP_FIFO_ERR | 1214 VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_REQ_FIFO_ERR | 1215 VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_PRSP_FIFO_ERR | 1216 VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_WRSP_FIFO_ERR | 1217 VXGE_HAL_PXTMC_ERR_REG_XTMC_REQ_FIFO_ERR | 1218 VXGE_HAL_PXTMC_ERR_REG_XTMC_REQ_DATA_FIFO_ERR | 1219 VXGE_HAL_PXTMC_ERR_REG_XTMC_WR_RSP_FIFO_ERR | 1220 VXGE_HAL_PXTMC_ERR_REG_XTMC_RD_RSP_FIFO_ERR | 1221 VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_REQ_SHADOW_ERR | 1222 VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_RSP_SHADOW_ERR | 1223 VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_REQ_SHADOW_ERR | 1224 VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_RSP_SHADOW_ERR | 1225 VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_REQ_SHADOW_ERR | 1226 VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_RSP_SHADOW_ERR | 1227 VXGE_HAL_PXTMC_ERR_REG_XTMC_XIL_SHADOW_ERR | 1228 VXGE_HAL_PXTMC_ERR_REG_XTMC_ARB_SHADOW_ERR | 1229 VXGE_HAL_PXTMC_ERR_REG_XTMC_RAM_SHADOW_ERR | 1230 VXGE_HAL_PXTMC_ERR_REG_XTMC_CMW_SHADOW_ERR | 1231 VXGE_HAL_PXTMC_ERR_REG_XTMC_CMR_SHADOW_ERR | 1232 VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_REQ_FSM_ERR | 1233 VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_RSP_FSM_ERR | 1234 VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_REQ_FSM_ERR | 1235 VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_RSP_FSM_ERR | 1236 VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_REQ_FSM_ERR | 1237 VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_RSP_FSM_ERR | 1238 VXGE_HAL_PXTMC_ERR_REG_XTMC_XIL_FSM_ERR | 1239 VXGE_HAL_PXTMC_ERR_REG_XTMC_ARB_FSM_ERR | 1240 VXGE_HAL_PXTMC_ERR_REG_XTMC_CMW_FSM_ERR | 1241 VXGE_HAL_PXTMC_ERR_REG_XTMC_CMR_FSM_ERR | 1242 VXGE_HAL_PXTMC_ERR_REG_XTMC_MXP_RD_PROT_ERR | 1243 VXGE_HAL_PXTMC_ERR_REG_XTMC_UXP_RD_PROT_ERR | 1244 VXGE_HAL_PXTMC_ERR_REG_XTMC_CXP_RD_PROT_ERR | 1245 VXGE_HAL_PXTMC_ERR_REG_XTMC_MXP_WR_PROT_ERR | 1246 VXGE_HAL_PXTMC_ERR_REG_XTMC_UXP_WR_PROT_ERR | 1247 VXGE_HAL_PXTMC_ERR_REG_XTMC_CXP_WR_PROT_ERR | 1248 VXGE_HAL_PXTMC_ERR_REG_XTMC_MXP_INV_ADDR_ERR | 1249 VXGE_HAL_PXTMC_ERR_REG_XTMC_UXP_INV_ADDR_ERR | 1250 VXGE_HAL_PXTMC_ERR_REG_XTMC_CXP_INV_ADDR_ERR | 1251 VXGE_HAL_PXTMC_ERR_REG_XTMC_CP2BDT_DFIFO_PUSH_ERR | 1252 VXGE_HAL_PXTMC_ERR_REG_XTMC_CP2BDT_RFIFO_PUSH_ERR; 1253 1254 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pxtmc_err_mask); 1255 1256 val64 = VXGE_HAL_CP_EXC_REG_CP_CP_CAUSE_CRIT_INT | 1257 VXGE_HAL_CP_EXC_REG_CP_CP_SERR; 1258 1259 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->cp_exc_mask); 1260 1261 val64 = VXGE_HAL_CP_ERR_REG_CP_CP_DCACHE_DB_ERR(0xff) | 1262 VXGE_HAL_CP_ERR_REG_CP_CP_ICACHE_DB_ERR(0x3) | 1263 VXGE_HAL_CP_ERR_REG_CP_CP_DTAG_DB_ERR | 1264 VXGE_HAL_CP_ERR_REG_CP_CP_ITAG_DB_ERR | 1265 VXGE_HAL_CP_ERR_REG_CP_CP_TRACE_DB_ERR | 1266 VXGE_HAL_CP_ERR_REG_CP_DMA2CP_DB_ERR | 1267 VXGE_HAL_CP_ERR_REG_CP_MP2CP_DB_ERR | 1268 VXGE_HAL_CP_ERR_REG_CP_QCC2CP_DB_ERR | 1269 VXGE_HAL_CP_ERR_REG_CP_STC2CP_DB_ERR(0x3) | 1270 VXGE_HAL_CP_ERR_REG_CP_H2L2CP_FIFO_ERR | 1271 VXGE_HAL_CP_ERR_REG_CP_STC2CP_FIFO_ERR | 1272 VXGE_HAL_CP_ERR_REG_CP_STE2CP_FIFO_ERR | 1273 VXGE_HAL_CP_ERR_REG_CP_TTE2CP_FIFO_ERR | 1274 VXGE_HAL_CP_ERR_REG_CP_SWIF2CP_FIFO_ERR | 1275 VXGE_HAL_CP_ERR_REG_CP_CP2DMA_FIFO_ERR | 1276 VXGE_HAL_CP_ERR_REG_CP_DAM2CP_FIFO_ERR | 1277 VXGE_HAL_CP_ERR_REG_CP_MP2CP_FIFO_ERR | 1278 VXGE_HAL_CP_ERR_REG_CP_QCC2CP_FIFO_ERR | 1279 VXGE_HAL_CP_ERR_REG_CP_DMA2CP_FIFO_ERR | 1280 VXGE_HAL_CP_ERR_REG_CP_CP_WAKE_FSM_INTEGRITY_ERR | 1281 VXGE_HAL_CP_ERR_REG_CP_CP_PMON_FSM_INTEGRITY_ERR | 1282 VXGE_HAL_CP_ERR_REG_CP_DMA_RD_SHADOW_ERR | 1283 VXGE_HAL_CP_ERR_REG_CP_PIFT_CREDIT_ERR; 1284 1285 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->cp_err_mask); 1286 1287 val64 = VXGE_HAL_PCMG2_INT_STATUS_PXTMC_ERR_PXTMC_INT | 1288 VXGE_HAL_PCMG2_INT_STATUS_CP_EXC_CP_XT_EXC_INT | 1289 VXGE_HAL_PCMG2_INT_STATUS_CP_ERR_CP_ERR_INT; 1290 1291 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pcmg2_int_mask); 1292 1293 val64 = VXGE_HAL_DAM_ERR_REG_DAM_RDSB_ECC_DB_ERR | 1294 VXGE_HAL_DAM_ERR_REG_DAM_WRSB_ECC_DB_ERR | 1295 VXGE_HAL_DAM_ERR_REG_DAM_HPPEDAT_ECC_DB_ERR | 1296 VXGE_HAL_DAM_ERR_REG_DAM_LPPEDAT_ECC_DB_ERR | 1297 VXGE_HAL_DAM_ERR_REG_DAM_WRRESP_ECC_DB_ERR | 1298 VXGE_HAL_DAM_ERR_REG_DAM_HPRD_ERR | 1299 VXGE_HAL_DAM_ERR_REG_DAM_LPRD_0_ERR | 1300 VXGE_HAL_DAM_ERR_REG_DAM_LPRD_1_ERR | 1301 VXGE_HAL_DAM_ERR_REG_DAM_HPPEDAT_OVERFLOW_ERR | 1302 VXGE_HAL_DAM_ERR_REG_DAM_LPPEDAT_OVERFLOW_ERR | 1303 VXGE_HAL_DAM_ERR_REG_DAM_WRRESP_OVERFLOW_ERR | 1304 VXGE_HAL_DAM_ERR_REG_DAM_SM_ERR; 1305 1306 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->dam_err_mask); 1307 1308 val64 = VXGE_HAL_PCMG3_INT_STATUS_DAM_ERR_DAM_INT; 1309 1310 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->pcmg3_int_mask); 1311 1312 val64 = VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_DB_ERR(0x3) | 1313 VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE1_DB_ERR(0x3) | 1314 VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE2_DB_ERR(0x3) | 1315 VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE3_DB_ERR(0x3) | 1316 VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE4_DB_ERR(0x3) | 1317 VXGE_HAL_XMAC_GEN_ERR_REG_XMACJ_XMAC_FSM_ERR; 1318 1319 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->xmac_gen_err_mask); 1320 1321 val64 = VXGE_HAL_XGXS_GEN_ERR_REG_XGXS_XGXS_FSM_ERR; 1322 1323 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->xgxs_gen_err_mask); 1324 1325 val64 = VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_DOWN | 1326 VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_UP | 1327 VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_WENT_DOWN | 1328 VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_WENT_UP | 1329 VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT | 1330 VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK; 1331 1332 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1333 &mrpcim_reg->asic_ntwk_err_mask); 1334 1335 val64 = VXGE_HAL_XGMAC_INT_STATUS_XMAC_GEN_ERR_XMAC_GEN_INT | 1336 VXGE_HAL_XGMAC_INT_STATUS_XGXS_GEN_ERR_XGXS_GEN_INT | 1337 VXGE_HAL_XGMAC_INT_STATUS_ASIC_NTWK_ERR_ASIC_NTWK_INT; 1338 1339 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->xgmac_int_mask); 1340 1341 val64 = 1342 VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_DB_ERR(0xf) | 1343 VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT1_RMAC_RTS_PART_DB_ERR(0xf) | 1344 VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT2_RMAC_RTS_PART_DB_ERR(0xf) | 1345 VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT0_DB_ERR(0x3) | 1346 VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT1_DB_ERR(0x3) | 1347 VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_VID_LKP_DB_ERR | 1348 VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT0_DB_ERR | 1349 VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT1_DB_ERR | 1350 VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT2_DB_ERR | 1351 VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_DB_ERR(0x3f) | 1352 VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_DB_ERR(0x7) | 1353 VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DS_LKP_DB_ERR; 1354 1355 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1356 &mrpcim_reg->rxmac_ecc_err_mask); 1357 1358 val64 = VXGE_HAL_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT0_FSM_ERR | 1359 VXGE_HAL_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT1_FSM_ERR | 1360 VXGE_HAL_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT2_FSM_ERR | 1361 VXGE_HAL_RXMAC_VARIOUS_ERR_REG_RMACJ_RMACJ_FSM_ERR; 1362 1363 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1364 &mrpcim_reg->rxmac_various_err_mask); 1365 1366 val64 = VXGE_HAL_RXMAC_INT_STATUS_RXMAC_ECC_ERR_RXMAC_ECC_INT | 1367 VXGE_HAL_RXMAC_INT_STATUS_RXMAC_VARIOUS_ERR_RXMAC_VARIOUS_INT; 1368 1369 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->rxmac_int_mask); 1370 1371 val64 = VXGE_HAL_TXMAC_GEN_ERR_REG_TMACJ_PERMANENT_STOP; 1372 1373 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1374 &mrpcim_reg->txmac_gen_err_mask); 1375 1376 val64 = VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2MAC_DB_ERR | 1377 VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_SB_DB_ERR | 1378 VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_DA_DB_ERR | 1379 VXGE_HAL_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT0_FSM_ERR | 1380 VXGE_HAL_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT1_FSM_ERR | 1381 VXGE_HAL_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT2_FSM_ERR | 1382 VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMACJ_FSM_ERR; 1383 1384 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1385 &mrpcim_reg->txmac_ecc_err_mask); 1386 1387 val64 = VXGE_HAL_TMAC_INT_STATUS_TXMAC_GEN_ERR_TXMAC_GEN_INT | 1388 VXGE_HAL_TMAC_INT_STATUS_TXMAC_ECC_ERR_TXMAC_ECC_INT; 1389 1390 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->tmac_int_mask); 1391 1392 val64 = VXGE_HAL_G3IFCMD_FB_ERR_REG_G3IF_SM_ERR; 1393 1394 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1395 &mrpcim_reg->g3ifcmd_fb_err_mask); 1396 1397 val64 = VXGE_HAL_G3IFCMD_FB_INT_STATUS_ERR_G3IF_INT; 1398 1399 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, 1400 &mrpcim_reg->g3ifcmd_fb_int_mask); 1401 1402 val64 = VXGE_HAL_MC_ERR_REG_MC_XFMD_MEM_ECC_DB_ERR_A | 1403 VXGE_HAL_MC_ERR_REG_MC_XFMD_MEM_ECC_DB_ERR_B | 1404 VXGE_HAL_MC_ERR_REG_MC_G3IF_RD_FIFO_ECC_DB_ERR | 1405 VXGE_HAL_MC_ERR_REG_MC_MIRI_ECC_DB_ERR_0 | 1406 VXGE_HAL_MC_ERR_REG_MC_MIRI_ECC_DB_ERR_1 | 1407 VXGE_HAL_MC_ERR_REG_MC_SM_ERR; 1408 1409 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->mc_err_mask); 1410 1411 val64 = VXGE_HAL_GROCRC_ALARM_REG_XFMD_WR_FIFO_ERR | 1412 VXGE_HAL_GROCRC_ALARM_REG_WDE2MSR_RD_FIFO_ERR; 1413 1414 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->grocrc_alarm_mask); 1415 1416 val64 = VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_N_DB_ERR | 1417 VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_W_DB_ERR(0x3) | 1418 VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_N_DB_ERR | 1419 VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_W_DB_ERR(0x3) | 1420 VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_N_DB_ERR | 1421 VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_W_DB_ERR(0x3) | 1422 VXGE_HAL_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_DB_ERR(0x3) | 1423 VXGE_HAL_FAU_ECC_ERR_REG_FAUJ_FAU_FSM_ERR; 1424 1425 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->fau_ecc_err_mask); 1426 1427 val64 = VXGE_HAL_MC_INT_STATUS_MC_ERR_MC_INT | 1428 VXGE_HAL_MC_INT_STATUS_GROCRC_ALARM_ROCRC_INT | 1429 VXGE_HAL_MC_INT_STATUS_FAU_ECC_ERR_FAU_ECC_INT; 1430 1431 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->mc_int_mask); 1432 1433 val64 = VXGE_HAL_G3FBCT_ERR_REG_G3IF_SM_ERR | 1434 VXGE_HAL_G3FBCT_ERR_REG_G3IF_GDDR3_DECC | 1435 VXGE_HAL_G3FBCT_ERR_REG_G3IF_GDDR3_U_DECC | 1436 VXGE_HAL_G3FBCT_ERR_REG_G3IF_CTRL_FIFO_DECC; 1437 1438 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->g3fbct_err_mask); 1439 1440 val64 = VXGE_HAL_G3FBCT_INT_STATUS_ERR_G3IF_INT; 1441 1442 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->g3fbct_int_mask); 1443 1444 val64 = VXGE_HAL_ORP_ERR_REG_ORP_FIFO_DB_ERR | 1445 VXGE_HAL_ORP_ERR_REG_ORP_XFMD_FIFO_UFLOW_ERR | 1446 VXGE_HAL_ORP_ERR_REG_ORP_FRM_FIFO_UFLOW_ERR | 1447 VXGE_HAL_ORP_ERR_REG_ORP_XFMD_RCV_FSM_ERR | 1448 VXGE_HAL_ORP_ERR_REG_ORP_OUTREAD_FSM_ERR | 1449 VXGE_HAL_ORP_ERR_REG_ORP_OUTQEM_FSM_ERR | 1450 VXGE_HAL_ORP_ERR_REG_ORP_XFMD_RCV_SHADOW_ERR | 1451 VXGE_HAL_ORP_ERR_REG_ORP_OUTREAD_SHADOW_ERR | 1452 VXGE_HAL_ORP_ERR_REG_ORP_OUTQEM_SHADOW_ERR | 1453 VXGE_HAL_ORP_ERR_REG_ORP_OUTFRM_SHADOW_ERR | 1454 VXGE_HAL_ORP_ERR_REG_ORP_OPTPRS_SHADOW_ERR; 1455 1456 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->orp_err_mask); 1457 1458 val64 = VXGE_HAL_PTM_ALARM_REG_PTM_RDCTRL_SYNC_ERR | 1459 VXGE_HAL_PTM_ALARM_REG_PTM_RDCTRL_FIFO_ERR | 1460 VXGE_HAL_PTM_ALARM_REG_XFMD_RD_FIFO_ERR | 1461 VXGE_HAL_PTM_ALARM_REG_WDE2MSR_WR_FIFO_ERR | 1462 VXGE_HAL_PTM_ALARM_REG_PTM_FRMM_ECC_DB_ERR(0x3); 1463 1464 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->ptm_alarm_mask); 1465 1466 val64 = VXGE_HAL_TPA_ERROR_REG_TPA_FSM_ERR_ALARM | 1467 VXGE_HAL_TPA_ERROR_REG_TPA_TPA_DA_LKUP_PRT0_DB_ERR; 1468 1469 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->tpa_error_mask); 1470 1471 val64 = VXGE_HAL_TPA_INT_STATUS_ORP_ERR_ORP_INT | 1472 VXGE_HAL_TPA_INT_STATUS_PTM_ALARM_PTM_INT | 1473 VXGE_HAL_TPA_INT_STATUS_TPA_ERROR_TPA_INT; 1474 1475 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->tpa_int_mask); 1476 1477 val64 = VXGE_HAL_KDFC_ERR_REG_KDFC_KDFC_ECC_DB_ERR | 1478 VXGE_HAL_KDFC_ERR_REG_KDFC_KDFC_SM_ERR_ALARM; 1479 1480 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->kdfc_err_mask); 1481 1482 val64 = VXGE_HAL_DOORBELL_INT_STATUS_KDFC_ERR_REG_TXDMA_KDFC_INT; 1483 1484 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->doorbell_int_mask); 1485 1486 val64 = VXGE_HAL_TIM_ERR_REG_TIM_VBLS_DB_ERR | 1487 VXGE_HAL_TIM_ERR_REG_TIM_BMAP_PA_DB_ERR | 1488 VXGE_HAL_TIM_ERR_REG_TIM_BMAP_PB_DB_ERR | 1489 VXGE_HAL_TIM_ERR_REG_TIM_BMAP_MSG_DB_ERR | 1490 VXGE_HAL_TIM_ERR_REG_TIM_BMAP_MEM_CNTRL_SM_ERR | 1491 VXGE_HAL_TIM_ERR_REG_TIM_BMAP_MSG_MEM_CNTRL_SM_ERR | 1492 VXGE_HAL_TIM_ERR_REG_TIM_MPIF_PCIWR_ERR | 1493 VXGE_HAL_TIM_ERR_REG_TIM_ROCRC_BMAP_UPDT_FIFO_ERR | 1494 VXGE_HAL_TIM_ERR_REG_TIM_CREATE_BMAPMSG_FIFO_ERR; 1495 1496 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->tim_err_mask); 1497 1498 val64 = VXGE_HAL_MSG_EXC_REG_MP_MXP_CAUSE_CRIT_INT | 1499 VXGE_HAL_MSG_EXC_REG_UP_UXP_CAUSE_CRIT_INT | 1500 VXGE_HAL_MSG_EXC_REG_MP_MXP_SERR | 1501 VXGE_HAL_MSG_EXC_REG_UP_UXP_SERR; 1502 1503 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->msg_exc_mask); 1504 1505 val64 = VXGE_HAL_MSG_ERR_REG_UP_UXP_WAKE_FSM_INTEGRITY_ERR | 1506 VXGE_HAL_MSG_ERR_REG_MP_MXP_WAKE_FSM_INTEGRITY_ERR | 1507 VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMQ_DMA_READ_CMD_FSM_INTEGRITY_ERR | 1508 VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMQ_DMA_RESP_FSM_INTEGRITY_ERR | 1509 VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMQ_OWN_FSM_INTEGRITY_ERR | 1510 VXGE_HAL_MSG_ERR_REG_MSG_QUE_PDA_ACC_FSM_INTEGRITY_ERR | 1511 VXGE_HAL_MSG_ERR_REG_MP_MXP_PMON_FSM_INTEGRITY_ERR | 1512 VXGE_HAL_MSG_ERR_REG_UP_UXP_PMON_FSM_INTEGRITY_ERR | 1513 VXGE_HAL_MSG_ERR_REG_MSG_XFMDQRY_FSM_INTEGRITY_ERR | 1514 VXGE_HAL_MSG_ERR_REG_MSG_FRMQRY_FSM_INTEGRITY_ERR | 1515 VXGE_HAL_MSG_ERR_REG_MSG_QUE_UMQ_WRITE_FSM_INTEGRITY_ERR | 1516 VXGE_HAL_MSG_ERR_REG_MSG_QUE_UMQ_BWR_PF_FSM_INTEGRITY_ERR | 1517 VXGE_HAL_MSG_ERR_REG_MSG_QUE_REG_RESP_FIFO_ERR | 1518 VXGE_HAL_MSG_ERR_REG_UP_UXP_DTAG_DB_ERR | 1519 VXGE_HAL_MSG_ERR_REG_UP_UXP_ITAG_DB_ERR | 1520 VXGE_HAL_MSG_ERR_REG_MP_MXP_DTAG_DB_ERR | 1521 VXGE_HAL_MSG_ERR_REG_MP_MXP_ITAG_DB_ERR | 1522 VXGE_HAL_MSG_ERR_REG_UP_UXP_TRACE_DB_ERR | 1523 VXGE_HAL_MSG_ERR_REG_MP_MXP_TRACE_DB_ERR | 1524 VXGE_HAL_MSG_ERR_REG_MSG_QUE_CMG2MSG_DB_ERR | 1525 VXGE_HAL_MSG_ERR_REG_MSG_QUE_TXPE2MSG_DB_ERR | 1526 VXGE_HAL_MSG_ERR_REG_MSG_QUE_RXPE2MSG_DB_ERR | 1527 VXGE_HAL_MSG_ERR_REG_MSG_QUE_RPE2MSG_DB_ERR | 1528 VXGE_HAL_MSG_ERR_REG_MSG_QUE_REG_READ_FIFO_ERR | 1529 VXGE_HAL_MSG_ERR_REG_MSG_QUE_MXP2UXP_FIFO_ERR | 1530 VXGE_HAL_MSG_ERR_REG_MSG_QUE_KDFC_SIF_FIFO_ERR | 1531 VXGE_HAL_MSG_ERR_REG_MSG_QUE_CXP2SWIF_FIFO_ERR | 1532 VXGE_HAL_MSG_ERR_REG_MSG_QUE_UMQ_DB_ERR | 1533 VXGE_HAL_MSG_ERR_REG_MSG_QUE_BWR_PF_DB_ERR | 1534 VXGE_HAL_MSG_ERR_REG_MSG_QUE_BWR_SIF_FIFO_ERR | 1535 VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMQ_ECC_DB_ERR | 1536 VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMA_READ_FIFO_ERR | 1537 VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMA_RESP_ECC_DB_ERR | 1538 VXGE_HAL_MSG_ERR_REG_MSG_QUE_UXP2MXP_FIFO_ERR; 1539 1540 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->msg_err_mask); 1541 1542 val64 = 1543 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_CMG2MSG_DISPATCH_FSM_INTEGRITY_ERR | 1544 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_DMQ_DISPATCH_FSM_INTEGRITY_ERR | 1545 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_SWIF_DISPATCH_FSM_INTEGRITY_ERR | 1546 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_PIC_WRITE_FSM_INTEGRITY_ERR | 1547 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_SWIFREG_FSM_INTEGRITY_ERR | 1548 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_TIM_WRITE_FSM_INTEGRITY_ERR | 1549 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_UMQ_TA_FSM_INTEGRITY_ERR | 1550 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_TXPE_TA_FSM_INTEGRITY_ERR | 1551 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_RXPE_TA_FSM_INTEGRITY_ERR | 1552 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_SWIF_TA_FSM_INTEGRITY_ERR | 1553 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_DMA_TA_FSM_INTEGRITY_ERR | 1554 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_CP_TA_FSM_INTEGRITY_ERR | 1555 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA16_FSM_INTEGRITY_ERR | 1556 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA15_FSM_INTEGRITY_ERR | 1557 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA14_FSM_INTEGRITY_ERR | 1558 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA13_FSM_INTEGRITY_ERR | 1559 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA12_FSM_INTEGRITY_ERR | 1560 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA11_FSM_INTEGRITY_ERR | 1561 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA10_FSM_INTEGRITY_ERR | 1562 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA9_FSM_INTEGRITY_ERR | 1563 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA8_FSM_INTEGRITY_ERR | 1564 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA7_FSM_INTEGRITY_ERR | 1565 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA6_FSM_INTEGRITY_ERR | 1566 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA5_FSM_INTEGRITY_ERR | 1567 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA4_FSM_INTEGRITY_ERR | 1568 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA3_FSM_INTEGRITY_ERR | 1569 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA2_FSM_INTEGRITY_ERR | 1570 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA1_FSM_INTEGRITY_ERR | 1571 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA0_FSM_INTEGRITY_ERR | 1572 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_FBMC_OWN_FSM_INTEGRITY_ERR | 1573 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_TXPE2MSG_DISPATCH_FSM_INTEGRITY_ERR | 1574 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_RXPE2MSG_DISPATCH_FSM_INTEGRITY_ERR | 1575 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_RPE2MSG_DISPATCH_FSM_INTEGRITY_ERR | 1576 VXGE_HAL_MSG_ERR2_REG_MP_MP_PIFT_IF_CREDIT_CNT_ERR | 1577 VXGE_HAL_MSG_ERR2_REG_UP_UP_PIFT_IF_CREDIT_CNT_ERR | 1578 VXGE_HAL_MSG_ERR2_REG_MSG_QUE_UMQ2PIC_CMD_FIFO_ERR | 1579 VXGE_HAL_MSG_ERR2_REG_TIM_TIM2MSG_CMD_FIFO_ERR; 1580 1581 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->msg_err2_mask); 1582 1583 val64 = VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR0 | 1584 VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR1 | 1585 VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR2 | 1586 VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR3 | 1587 VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR4 | 1588 VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR5 | 1589 VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR6 | 1590 VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR7 | 1591 VXGE_HAL_MSG_ERR3_REG_UP_UXP_ICACHE_DB_ERR0 | 1592 VXGE_HAL_MSG_ERR3_REG_UP_UXP_ICACHE_DB_ERR1 | 1593 VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR0 | 1594 VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR1 | 1595 VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR2 | 1596 VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR3 | 1597 VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR4 | 1598 VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR5 | 1599 VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR6 | 1600 VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR7 | 1601 VXGE_HAL_MSG_ERR3_REG_MP_MXP_ICACHE_DB_ERR0 | 1602 VXGE_HAL_MSG_ERR3_REG_MP_MXP_ICACHE_DB_ERR1; 1603 1604 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->msg_err3_mask); 1605 1606 val64 = VXGE_HAL_MSG_INT_STATUS_TIM_ERR_TIM_INT | 1607 VXGE_HAL_MSG_INT_STATUS_MSG_EXC_MSG_XT_EXC_INT | 1608 VXGE_HAL_MSG_INT_STATUS_MSG_ERR3_MSG_ERR3_INT | 1609 VXGE_HAL_MSG_INT_STATUS_MSG_ERR2_MSG_ERR2_INT | 1610 VXGE_HAL_MSG_INT_STATUS_MSG_ERR_MSG_ERR_INT; 1611 1612 VXGE_HAL_MRPCIM_ERROR_REG_UNMASK(val64, &mrpcim_reg->msg_int_mask); 1613 1614 val64 = VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PIC_INT | 1615 VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PCI_INT | 1616 VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_RTDMA_INT | 1617 VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_WRDMA_INT | 1618 VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3CMCT_INT | 1619 VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_GCMG1_INT | 1620 VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_GCMG2_INT | 1621 VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3CMIFL_INT | 1622 VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3CMIFU_INT | 1623 VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PCMG1_INT | 1624 VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PCMG2_INT | 1625 VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PCMG3_INT | 1626 VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_XMAC_INT | 1627 VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_RXMAC_INT | 1628 VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_TMAC_INT | 1629 VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3FBIF_INT | 1630 VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_FBMC_INT | 1631 VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3FBCT_INT | 1632 VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_TPA_INT | 1633 VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_DRBELL_INT | 1634 VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_MSG_INT; 1635 1636 vxge_hal_pio_mem_write32_upper( 1637 hldev->header.pdev, 1638 hldev->header.regh0, 1639 (u32) bVAL32(~val64, 0), 1640 &mrpcim_reg->mrpcim_general_int_mask); 1641 1642 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 1643 __FILE__, __func__, __LINE__, status); 1644 1645 return (status); 1646} 1647 1648/* 1649 * vxge_hal_mrpcim_intr_disable - Disable the interrupts on mrpcim. 1650 * @devh: HAL device handle. 1651 * 1652 * Disable mrpcim interrupts 1653 * 1654 * See also: vxge_hal_mrpcim_intr_enable(). 1655 */ 1656vxge_hal_status_e 1657vxge_hal_mrpcim_intr_disable(vxge_hal_device_h devh) 1658{ 1659 u32 i; 1660 vxge_hal_status_e status = VXGE_HAL_OK; 1661 vxge_hal_mrpcim_reg_t *mrpcim_reg; 1662 __hal_device_t *hldev = (__hal_device_t *) devh; 1663 1664 vxge_assert(devh); 1665 1666 vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 1667 __FILE__, __func__, __LINE__); 1668 1669 vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT, 1670 (ptr_t) devh); 1671 1672 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 1673 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 1674 __FILE__, __func__, __LINE__, 1675 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 1676 1677 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 1678 1679 } 1680 1681 mrpcim_reg = hldev->mrpcim_reg; 1682 1683 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->ini_errors_mask); 1684 1685 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->dma_errors_mask); 1686 1687 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->tgt_errors_mask); 1688 1689 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->config_errors_mask); 1690 1691 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->crdt_errors_mask); 1692 1693 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->mrpcim_general_errors_mask); 1694 1695 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->pll_errors_mask); 1696 1697 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->mrpcim_ppif_int_mask); 1698 1699 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->dbecc_err_mask); 1700 1701 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->general_err_mask); 1702 1703 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->pcipif_int_mask); 1704 1705 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->pda_alarm_mask); 1706 1707 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->pcc_error_mask); 1708 1709 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->lso_error_mask); 1710 1711 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->sm_error_mask); 1712 1713 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rtdma_int_mask); 1714 1715 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rc_alarm_mask); 1716 1717 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rxdrm_sm_err_mask); 1718 1719 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rxdcm_sm_err_mask); 1720 1721 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rxdwm_sm_err_mask); 1722 1723 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rda_err_mask); 1724 1725 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rda_ecc_db_mask); 1726 1727 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rqa_err_mask); 1728 1729 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->frf_alarm_mask); 1730 1731 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rocrc_alarm_mask); 1732 1733 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->wde0_alarm_mask); 1734 1735 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->wde1_alarm_mask); 1736 1737 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->wde2_alarm_mask); 1738 1739 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->wde3_alarm_mask); 1740 1741 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->wrdma_int_mask); 1742 1743 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3cmct_err_mask); 1744 1745 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3cmct_int_mask); 1746 1747 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->gsscc_err_mask); 1748 1749 for (i = 0; i < 3; i++) { 1750 1751 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->gssc_err0_mask[i]); 1752 1753 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->gssc_err1_mask[i]); 1754 1755 } 1756 1757 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->gcmg1_int_mask); 1758 1759 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->gxtmc_err_mask); 1760 1761 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->gcp_err_mask); 1762 1763 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->cmc_err_mask); 1764 1765 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->gcmg2_int_mask); 1766 1767 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3ifcmd_cml_err_mask); 1768 1769 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3ifcmd_cml_int_mask); 1770 1771 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3ifcmd_cmu_err_mask); 1772 1773 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3ifcmd_cmu_int_mask); 1774 1775 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->psscc_err_mask); 1776 1777 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->pcmg1_int_mask); 1778 1779 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->pxtmc_err_mask); 1780 1781 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->cp_exc_mask); 1782 1783 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->cp_err_mask); 1784 1785 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->pcmg2_int_mask); 1786 1787 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->dam_err_mask); 1788 1789 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->pcmg3_int_mask); 1790 1791 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->xmac_gen_err_mask); 1792 1793 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->xgxs_gen_err_mask); 1794 1795 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->asic_ntwk_err_mask); 1796 1797 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->xgmac_int_mask); 1798 1799 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rxmac_ecc_err_mask); 1800 1801 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rxmac_various_err_mask); 1802 1803 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->rxmac_int_mask); 1804 1805 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->txmac_gen_err_mask); 1806 1807 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->txmac_ecc_err_mask); 1808 1809 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->tmac_int_mask); 1810 1811 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3ifcmd_fb_err_mask); 1812 1813 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3ifcmd_fb_int_mask); 1814 1815 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->mc_err_mask); 1816 1817 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->grocrc_alarm_mask); 1818 1819 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->fau_ecc_err_mask); 1820 1821 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->mc_int_mask); 1822 1823 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3fbct_err_mask); 1824 1825 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->g3fbct_int_mask); 1826 1827 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->orp_err_mask); 1828 1829 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->ptm_alarm_mask); 1830 1831 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->tpa_error_mask); 1832 1833 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->tpa_int_mask); 1834 1835 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->kdfc_err_mask); 1836 1837 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->doorbell_int_mask); 1838 1839 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->tim_err_mask); 1840 1841 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->msg_exc_mask); 1842 1843 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->msg_err_mask); 1844 1845 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->msg_err2_mask); 1846 1847 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->msg_err3_mask); 1848 1849 VXGE_HAL_MRPCIM_ERROR_REG_MASK(&mrpcim_reg->msg_int_mask); 1850 1851 vxge_hal_pio_mem_write32_upper( 1852 hldev->header.pdev, 1853 hldev->header.regh0, 1854 (u32) VXGE_HAL_INTR_MASK_ALL, 1855 &mrpcim_reg->mrpcim_general_int_mask); 1856 1857 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 1858 __FILE__, __func__, __LINE__, status); 1859 1860 return (status); 1861} 1862 1863/* 1864 * vxge_hal_mrpcim_reset - Reset the entire device. 1865 * @devh: HAL device handle. 1866 * 1867 * Soft-reset the device, reset the device stats except reset_cnt. 1868 * 1869 * 1870 * Returns: VXGE_HAL_OK - success. 1871 * VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED - Device is not initialized. 1872 * VXGE_HAL_ERR_RESET_FAILED - Reset failed. 1873 * 1874 * See also: vxge_hal_status_e {}. 1875 */ 1876vxge_hal_status_e 1877vxge_hal_mrpcim_reset(vxge_hal_device_h devh) 1878{ 1879 u64 val64; 1880 __hal_device_t *hldev = (__hal_device_t *) devh; 1881 1882 vxge_assert(devh); 1883 1884 vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 1885 __FILE__, __func__, __LINE__); 1886 1887 vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT, 1888 (ptr_t) devh); 1889 1890 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 1891 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 1892 __FILE__, __func__, __LINE__, 1893 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 1894 1895 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 1896 1897 } 1898 1899 if (!hldev->header.is_initialized) 1900 return (VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED); 1901 1902 if (hldev->device_resetting == 1) { 1903 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 1904 __FILE__, __func__, __LINE__, 1905 VXGE_HAL_ERR_RESET_IN_PROGRESS); 1906 1907 return (VXGE_HAL_ERR_RESET_IN_PROGRESS); 1908 } 1909 1910 (void) __hal_ifmsg_wmsg_post(hldev, 1911 hldev->first_vp_id, 1912 VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_BROADCAST, 1913 VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_DEVICE_RESET_BEGIN, 1914 0); 1915 1916 vxge_os_mdelay(100); 1917 1918 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 1919 hldev->header.regh0, 1920 &hldev->mrpcim_reg->sw_reset_cfg1); 1921 1922 val64 |= VXGE_HAL_SW_RESET_CFG1_TYPE; 1923 1924 vxge_os_pio_mem_write64(hldev->header.pdev, 1925 hldev->header.regh0, 1926 val64, 1927 &hldev->mrpcim_reg->sw_reset_cfg1); 1928 1929 vxge_os_pio_mem_write64(hldev->header.pdev, 1930 hldev->header.regh0, 1931 VXGE_HAL_PF_SW_RESET_PF_SW_RESET( 1932 VXGE_HAL_PF_SW_RESET_COMMAND), 1933 &hldev->mrpcim_reg->bf_sw_reset); 1934 1935 hldev->stats.sw_dev_info_stats.soft_reset_cnt++; 1936 1937 hldev->device_resetting = 1; 1938 1939 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 1940 __FILE__, __func__, __LINE__, VXGE_HAL_PENDING); 1941 1942 return (VXGE_HAL_PENDING); 1943} 1944 1945/* 1946 * vxge_hal_mrpcim_reset_poll - Poll the device for reset complete. 1947 * @devh: HAL device handle. 1948 * 1949 * Soft-reset the device, reset the device stats except reset_cnt. 1950 * 1951 * After reset is done, will try to re-initialize HW. 1952 * 1953 * Returns: VXGE_HAL_OK - success. 1954 * VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED - Device is not initialized. 1955 * VXGE_HAL_ERR_RESET_FAILED - Reset failed. 1956 * 1957 * See also: vxge_hal_status_e {}. 1958 */ 1959vxge_hal_status_e 1960vxge_hal_mrpcim_reset_poll(vxge_hal_device_h devh) 1961{ 1962 u64 val64; 1963 vxge_hal_status_e status = VXGE_HAL_OK; 1964 __hal_device_t *hldev = (__hal_device_t *) devh; 1965 1966 vxge_assert(devh); 1967 1968 vxge_hal_trace_log_mrpcim("==> %s:%s:%d", __FILE__, __func__, __LINE__); 1969 1970 vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT, 1971 (ptr_t) devh); 1972 1973 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 1974 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 1975 __FILE__, __func__, __LINE__, 1976 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 1977 1978 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 1979 1980 } 1981 1982 if (!hldev->header.is_initialized) { 1983 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 1984 __FILE__, __func__, __LINE__, 1985 VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED); 1986 return (VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED); 1987 } 1988 1989 if ((status = __hal_device_reg_addr_get(hldev)) != VXGE_HAL_OK) { 1990 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 1991 __FILE__, __func__, __LINE__, status); 1992 hldev->device_resetting = 0; 1993 return (status); 1994 } 1995 1996 __hal_device_id_get(hldev); 1997 1998 __hal_device_host_info_get(hldev); 1999 2000 hldev->hw_is_initialized = 0; 2001 2002 hldev->device_resetting = 0; 2003 2004 vxge_os_memzero(hldev->mrpcim->mrpcim_stats, 2005 sizeof(vxge_hal_mrpcim_stats_hw_info_t)); 2006 2007 vxge_os_memzero(&hldev->mrpcim->mrpcim_stats_sav, 2008 sizeof(vxge_hal_mrpcim_stats_hw_info_t)); 2009 2010 status = __hal_mrpcim_mac_configure(hldev); 2011 2012 if (status != VXGE_HAL_OK) { 2013 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 2014 __FILE__, __func__, __LINE__, status); 2015 return (status); 2016 } 2017 2018 status = __hal_mrpcim_lag_configure(hldev); 2019 2020 if (status != VXGE_HAL_OK) { 2021 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 2022 __FILE__, __func__, __LINE__, status); 2023 return (status); 2024 } 2025 2026 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 2027 hldev->header.regh0, 2028 &hldev->mrpcim_reg->mdio_gen_cfg_port[0]); 2029 2030 hldev->mrpcim->mdio_phy_prtad0 = 2031 (u32) VXGE_HAL_MDIO_GEN_CFG_PORT_GET_MDIO_PHY_PRTAD(val64); 2032 2033 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 2034 hldev->header.regh0, 2035 &hldev->mrpcim_reg->mdio_gen_cfg_port[1]); 2036 2037 hldev->mrpcim->mdio_phy_prtad1 = 2038 (u32) VXGE_HAL_MDIO_GEN_CFG_PORT_GET_MDIO_PHY_PRTAD(val64); 2039 2040 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 2041 hldev->header.regh0, 2042 &hldev->mrpcim_reg->xgxs_static_cfg_port[0]); 2043 2044 hldev->mrpcim->mdio_dte_prtad0 = 2045 (u32) VXGE_HAL_XGXS_STATIC_CFG_PORT_GET_MDIO_DTE_PRTAD(val64); 2046 2047 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 2048 hldev->header.regh0, 2049 &hldev->mrpcim_reg->xgxs_static_cfg_port[1]); 2050 2051 hldev->mrpcim->mdio_dte_prtad1 = 2052 (u32) VXGE_HAL_XGXS_STATIC_CFG_PORT_GET_MDIO_DTE_PRTAD(val64); 2053 2054 vxge_os_pio_mem_write64(hldev->header.pdev, 2055 hldev->header.regh0, 2056 hldev->mrpcim->mrpcim_stats_block->dma_addr, 2057 &hldev->mrpcim_reg->mrpcim_stats_start_host_addr); 2058 2059 vxge_os_pio_mem_write64(hldev->header.pdev, 2060 hldev->header.regh0, 2061 hldev->vpath_assignments, 2062 &hldev->mrpcim_reg->rxmac_authorize_all_addr); 2063 2064 vxge_os_pio_mem_write64(hldev->header.pdev, 2065 hldev->header.regh0, 2066 hldev->vpath_assignments, 2067 &hldev->mrpcim_reg->rxmac_authorize_all_vid); 2068 2069 (void) __hal_ifmsg_wmsg_post(hldev, 2070 hldev->first_vp_id, 2071 VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_BROADCAST, 2072 VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_DEVICE_RESET_END, 2073 0); 2074 2075 (void) vxge_hal_device_reset_poll(devh); 2076 2077 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 2078 __FILE__, __func__, __LINE__, status); 2079 2080 return (status); 2081} 2082 2083/* 2084 * __hal_mrpcim_xpak_counter_check - check the Xpak error count and log the msg 2085 * @hldev: pointer to __hal_device_t structure 2086 * @port: Port number 2087 * @type: xpak stats error type 2088 * @value: xpak stats value 2089 * 2090 * It is used to log the error message based on the xpak stats value 2091 * Return value: 2092 * None 2093 */ 2094void 2095__hal_mrpcim_xpak_counter_check(__hal_device_t *hldev, 2096 u32 port, u32 type, u32 value) 2097{ 2098 vxge_assert(hldev != NULL); 2099 2100 vxge_hal_trace_log_stats("==> %s:%s:%d", 2101 __FILE__, __func__, __LINE__); 2102 2103 vxge_hal_trace_log_stats( 2104 "hldev = 0x"VXGE_OS_STXFMT", port = %d, type = %d, value = %d", 2105 (ptr_t) hldev, port, type, value); 2106 2107 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 2108 2109 vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d", 2110 __FILE__, __func__, 2111 __LINE__, VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2112 return; 2113 2114 } 2115 2116 /* 2117 * If the value is high for three consecutive cylce, 2118 * log a error message 2119 */ 2120 if (value == 3) { 2121 switch (type) { 2122 case VXGE_HAL_XPAK_ALARM_EXCESS_TEMP: 2123 hldev->mrpcim->xpak_stats[port].excess_temp = 0; 2124 2125 /* 2126 * Notify the ULD on Excess Xpak temperature alarm msg 2127 */ 2128 if (g_vxge_hal_driver->uld_callbacks.xpak_alarm_log) { 2129 g_vxge_hal_driver->uld_callbacks.xpak_alarm_log( 2130 hldev->header.upper_layer_data, 2131 port, 2132 VXGE_HAL_XPAK_ALARM_EXCESS_TEMP); 2133 } 2134 break; 2135 case VXGE_HAL_XPAK_ALARM_EXCESS_BIAS_CURRENT: 2136 hldev->mrpcim->xpak_stats[port].excess_bias_current = 0; 2137 2138 /* 2139 * Notify the ULD on Excess xpak bias current alarm msg 2140 */ 2141 if (g_vxge_hal_driver->uld_callbacks.xpak_alarm_log) { 2142 g_vxge_hal_driver->uld_callbacks.xpak_alarm_log( 2143 hldev->header.upper_layer_data, 2144 port, 2145 VXGE_HAL_XPAK_ALARM_EXCESS_BIAS_CURRENT); 2146 } 2147 break; 2148 case VXGE_HAL_XPAK_ALARM_EXCESS_LASER_OUTPUT: 2149 hldev->mrpcim->xpak_stats[port].excess_laser_output = 0; 2150 2151 /* 2152 * Notify the ULD on Excess Xpak Laser o/p power 2153 * alarm msg 2154 */ 2155 if (g_vxge_hal_driver->uld_callbacks.xpak_alarm_log) { 2156 g_vxge_hal_driver->uld_callbacks.xpak_alarm_log( 2157 hldev->header.upper_layer_data, 2158 port, 2159 VXGE_HAL_XPAK_ALARM_EXCESS_LASER_OUTPUT); 2160 } 2161 break; 2162 default: 2163 vxge_hal_info_log_stats("%s", 2164 "Incorrect XPAK Alarm type"); 2165 } 2166 } 2167 2168 vxge_hal_trace_log_stats("<== %s:%s:%d Result = 0", 2169 __FILE__, __func__, __LINE__); 2170} 2171 2172/* 2173 * vxge_hal_mrpcim_xpak_stats_poll - Poll and update the Xpak error count. 2174 * @devh: HAL device handle 2175 * @port: Port number 2176 * 2177 * It is used to update the xpak stats value 2178 */ 2179vxge_hal_status_e 2180vxge_hal_mrpcim_xpak_stats_poll( 2181 vxge_hal_device_h devh, u32 port) 2182{ 2183 u16 val; 2184 vxge_hal_status_e status = VXGE_HAL_OK; 2185 __hal_device_t *hldev = (__hal_device_t *) devh; 2186 2187 vxge_assert(hldev != NULL); 2188 2189 vxge_hal_trace_log_stats("==> %s:%s:%d", 2190 __FILE__, __func__, __LINE__); 2191 2192 vxge_hal_trace_log_stats("hldev = 0x"VXGE_OS_STXFMT", port = %d", 2193 (ptr_t) hldev, port); 2194 2195 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 2196 2197 vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d", 2198 __FILE__, __func__, __LINE__, 2199 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2200 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2201 2202 } 2203 2204 /* Loading the DOM register to MDIO register */ 2205 2206 val = 0; 2207 2208 status = __hal_mrpcim_mdio_access(devh, port, 2209 VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_WRITE, 2210 VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PMA_PMD, 2211 VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT, 2212 &val); 2213 2214 if (status != VXGE_HAL_OK) { 2215 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 2216 __FILE__, __func__, __LINE__, status); 2217 return (status); 2218 } 2219 2220 status = __hal_mrpcim_mdio_access(devh, port, 2221 VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ, 2222 VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PMA_PMD, 2223 VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_CMD_STAT, 2224 &val); 2225 2226 if (status != VXGE_HAL_OK) { 2227 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 2228 __FILE__, __func__, __LINE__, status); 2229 return (status); 2230 } 2231 2232 /* 2233 * Reading the Alarm flags 2234 */ 2235 status = __hal_mrpcim_mdio_access(devh, port, 2236 VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ, 2237 VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PMA_PMD, 2238 VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG, 2239 &val); 2240 2241 if (status != VXGE_HAL_OK) { 2242 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 2243 __FILE__, __func__, __LINE__, status); 2244 return (status); 2245 } 2246 2247 if (val & 2248 VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_TEMP_HIGH) { 2249 hldev->mrpcim->xpak_stats[port].alarm_transceiver_temp_high++; 2250 hldev->mrpcim->xpak_stats[port].excess_temp++; 2251 __hal_mrpcim_xpak_counter_check(hldev, port, 2252 VXGE_HAL_XPAK_ALARM_EXCESS_TEMP, 2253 hldev->mrpcim->xpak_stats[port].excess_temp); 2254 } else { 2255 hldev->mrpcim->xpak_stats[port].excess_temp = 0; 2256 } 2257 2258 if (val & 2259 VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_TEMP_LOW) { 2260 hldev->mrpcim->xpak_stats[port].alarm_transceiver_temp_low++; 2261 } 2262 2263 if (val & 2264 VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_CUR_HIGH) { 2265 hldev->mrpcim->xpak_stats[port].alarm_laser_bias_current_high++; 2266 hldev->mrpcim->xpak_stats[port].excess_bias_current++; 2267 __hal_mrpcim_xpak_counter_check(hldev, port, 2268 VXGE_HAL_XPAK_ALARM_EXCESS_BIAS_CURRENT, 2269 hldev->mrpcim->xpak_stats[port].excess_bias_current); 2270 } else { 2271 hldev->mrpcim->xpak_stats[port].excess_bias_current = 0; 2272 } 2273 2274 if (val & 2275 VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_CUR_LOW) { 2276 hldev->mrpcim->xpak_stats[port].alarm_laser_bias_current_low++; 2277 } 2278 2279 if (val & 2280 VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_PWR_HIGH) { 2281 hldev->mrpcim->xpak_stats[port].alarm_laser_output_power_high++; 2282 hldev->mrpcim->xpak_stats[port].excess_laser_output++; 2283 __hal_mrpcim_xpak_counter_check(hldev, port, 2284 VXGE_HAL_XPAK_ALARM_EXCESS_LASER_OUTPUT, 2285 hldev->mrpcim->xpak_stats[port].excess_laser_output); 2286 } else { 2287 hldev->mrpcim->xpak_stats[port].excess_laser_output = 0; 2288 } 2289 2290 if (val & 2291 VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_ALARM_FLAG_PWR_LOW) { 2292 hldev->mrpcim->xpak_stats[port].alarm_laser_output_power_low++; 2293 } 2294 2295 /* 2296 * Reading the warning flags 2297 */ 2298 status = __hal_mrpcim_mdio_access(devh, port, 2299 VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE_ADDR_READ, 2300 VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD_PMA_PMD, 2301 VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG, 2302 &val); 2303 2304 if (status != VXGE_HAL_OK) { 2305 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 2306 __FILE__, __func__, __LINE__, status); 2307 return (status); 2308 } 2309 2310 if (val & VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_TEMP_HIGH) 2311 hldev->mrpcim->xpak_stats[port].warn_transceiver_temp_high++; 2312 if (val & VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_TEMP_LOW) 2313 hldev->mrpcim->xpak_stats[port].warn_transceiver_temp_low++; 2314 if (val & VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_CUR_HIGH) 2315 hldev->mrpcim->xpak_stats[port].warn_laser_bias_current_high++; 2316 if (val & VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_CUR_LOW) 2317 hldev->mrpcim->xpak_stats[port].warn_laser_bias_current_low++; 2318 if (val & VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_PWR_HIGH) 2319 hldev->mrpcim->xpak_stats[port].warn_laser_output_power_high++; 2320 if (val & VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR_DOM_TX_WARN_FLAG_PWR_LOW) 2321 hldev->mrpcim->xpak_stats[port].warn_laser_output_power_low++; 2322 2323 vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 2324 __FILE__, __func__, __LINE__, status); 2325 return (status); 2326} 2327 2328/* 2329 * vxge_hal_mrpcim_stats_enable - Enable mrpcim statistics. 2330 * @devh: HAL Device. 2331 * 2332 * Enable the DMA mrpcim statistics for the device. The function is to be called 2333 * to re-enable the adapter to update stats into the host memory 2334 * 2335 * See also: vxge_hal_mrpcim_stats_disable() 2336 */ 2337vxge_hal_status_e 2338vxge_hal_mrpcim_stats_enable(vxge_hal_device_h devh) 2339{ 2340 u64 val64; 2341 vxge_hal_status_e status = VXGE_HAL_OK; 2342 __hal_device_t *hldev = (__hal_device_t *) devh; 2343 2344 vxge_assert(devh != NULL); 2345 2346 vxge_hal_trace_log_stats("==> %s:%s:%d", 2347 __FILE__, __func__, __LINE__); 2348 2349 vxge_hal_trace_log_stats("devh = 0x"VXGE_OS_STXFMT, 2350 (ptr_t) devh); 2351 2352 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 2353 2354 vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d", 2355 __FILE__, __func__, __LINE__, 2356 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2357 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2358 2359 } 2360 2361 vxge_os_memcpy(&hldev->mrpcim->mrpcim_stats_sav, 2362 hldev->mrpcim->mrpcim_stats, 2363 sizeof(vxge_hal_mrpcim_stats_hw_info_t)); 2364 2365 if (hldev->header.config.stats_read_method == 2366 VXGE_HAL_STATS_READ_METHOD_DMA) { 2367 2368 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 2369 hldev->header.regh0, 2370 &hldev->mrpcim_reg->mrpcim_general_cfg2); 2371 2372 val64 |= VXGE_HAL_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_ENABLE; 2373 2374 vxge_os_pio_mem_write64(hldev->header.pdev, 2375 hldev->header.regh0, 2376 val64, 2377 &hldev->mrpcim_reg->mrpcim_general_cfg2); 2378 2379 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 2380 hldev->header.regh0, 2381 &hldev->common_reg->stats_cfg0); 2382 2383 val64 |= VXGE_HAL_STATS_CFG0_STATS_ENABLE( 2384 (1 << (16 - hldev->first_vp_id))); 2385 2386 vxge_hal_pio_mem_write32_upper(hldev->header.pdev, 2387 hldev->header.regh0, 2388 (u32) bVAL32(val64, 0), 2389 &hldev->common_reg->stats_cfg0); 2390 } else { 2391 status = __hal_mrpcim_stats_get( 2392 hldev, 2393 hldev->mrpcim->mrpcim_stats); 2394 } 2395 2396 vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 2397 __FILE__, __func__, __LINE__, status); 2398 return (status); 2399} 2400 2401/* 2402 * vxge_hal_mrpcim_stats_disable - Disable mrpcim statistics. 2403 * @devh: HAL Device. 2404 * 2405 * Enable the DMA mrpcim statistics for the device. The function is to be called 2406 * to disable the adapter to update stats into the host memory. This function 2407 * is not needed to be called, normally. 2408 * 2409 * See also: vxge_hal_mrpcim_stats_enable() 2410 */ 2411vxge_hal_status_e 2412vxge_hal_mrpcim_stats_disable(vxge_hal_device_h devh) 2413{ 2414 u64 val64; 2415 vxge_hal_status_e status = VXGE_HAL_OK; 2416 __hal_device_t *hldev = (__hal_device_t *) devh; 2417 2418 vxge_assert(devh != NULL); 2419 2420 vxge_hal_trace_log_stats("==> %s:%s:%d", 2421 __FILE__, __func__, __LINE__); 2422 2423 vxge_hal_trace_log_stats("devh = 0x"VXGE_OS_STXFMT, 2424 (ptr_t) devh); 2425 2426 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 2427 2428 vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d", 2429 __FILE__, __func__, __LINE__, 2430 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2431 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2432 2433 } 2434 2435 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 2436 hldev->header.regh0, 2437 &hldev->mrpcim_reg->mrpcim_general_cfg2); 2438 2439 val64 &= ~VXGE_HAL_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_ENABLE; 2440 2441 vxge_os_pio_mem_write64(hldev->header.pdev, 2442 hldev->header.regh0, 2443 val64, 2444 &hldev->mrpcim_reg->mrpcim_general_cfg2); 2445 2446 vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 2447 __FILE__, __func__, __LINE__, status); 2448 return (status); 2449} 2450 2451/* 2452 * vxge_hal_mrpcim_stats_get - Get the device mrpcim statistics. 2453 * @devh: HAL Device. 2454 * @stats: mrpcim stats 2455 * 2456 * Returns the device mrpcim stats for the device. 2457 * 2458 * See also: vxge_hal_device_stats_get() 2459 */ 2460vxge_hal_status_e 2461vxge_hal_mrpcim_stats_get( 2462 vxge_hal_device_h devh, 2463 vxge_hal_mrpcim_stats_hw_info_t *stats) 2464{ 2465 u64 val64; 2466 vxge_hal_status_e status = VXGE_HAL_OK; 2467 __hal_device_t *hldev = (__hal_device_t *) devh; 2468 2469 vxge_assert((hldev != NULL) && (stats != NULL)); 2470 2471 vxge_hal_trace_log_stats("==> %s:%s:%d", 2472 __FILE__, __func__, __LINE__); 2473 2474 vxge_hal_trace_log_stats( 2475 "devh = 0x"VXGE_OS_STXFMT", stats = 0x"VXGE_OS_STXFMT, 2476 (ptr_t) devh, (ptr_t) stats); 2477 2478 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 2479 2480 vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d", 2481 __FILE__, __func__, __LINE__, 2482 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2483 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2484 2485 } 2486 2487 if (hldev->header.config.stats_read_method == 2488 VXGE_HAL_STATS_READ_METHOD_DMA) { 2489 2490 status = vxge_hal_device_register_poll(hldev->header.pdev, 2491 hldev->header.regh0, 2492 &hldev->common_reg->stats_cfg0, 2493 0, 2494 VXGE_HAL_STATS_CFG0_STATS_ENABLE( 2495 (1 << (16 - hldev->first_vp_id))), 2496 hldev->header.config.device_poll_millis); 2497 2498 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 2499 hldev->header.regh0, 2500 &hldev->mrpcim_reg->mrpcim_general_cfg2); 2501 2502 val64 &= ~VXGE_HAL_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_ENABLE; 2503 2504 vxge_os_pio_mem_write64(hldev->header.pdev, 2505 hldev->header.regh0, 2506 val64, 2507 &hldev->mrpcim_reg->mrpcim_general_cfg2); 2508 } 2509 2510 if (status == VXGE_HAL_OK) { 2511 vxge_os_memcpy(stats, 2512 hldev->mrpcim->mrpcim_stats, 2513 sizeof(vxge_hal_mrpcim_stats_hw_info_t)); 2514 } 2515 2516 vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 2517 __FILE__, __func__, __LINE__, status); 2518 return (status); 2519} 2520 2521/* 2522 * vxge_hal_mrpcim_stats_access - Access the statistics from the given location 2523 * and offset and perform an operation 2524 * @devh: HAL Device handle. 2525 * @operation: Operation to be performed 2526 * @location: Location (one of vpath id, aggregate or port) 2527 * @offset: Offset with in the location 2528 * @stat: Pointer to a buffer to return the value 2529 * 2530 * Get the statistics from the given location and offset. 2531 * 2532 */ 2533vxge_hal_status_e 2534vxge_hal_mrpcim_stats_access( 2535 vxge_hal_device_h devh, 2536 u32 operation, 2537 u32 location, 2538 u32 offset, 2539 u64 *stat) 2540{ 2541 u64 val64; 2542 vxge_hal_status_e status = VXGE_HAL_OK; 2543 __hal_device_t *hldev = (__hal_device_t *) devh; 2544 2545 vxge_assert((devh != NULL) && (stat != NULL)); 2546 2547 vxge_hal_trace_log_stats("==> %s:%s:%d", 2548 __FILE__, __func__, __LINE__); 2549 2550 vxge_hal_trace_log_stats("devh = 0x"VXGE_OS_STXFMT", operation = %d, " 2551 "location = %d, offset = %d, stat = 0x"VXGE_OS_STXFMT, 2552 (ptr_t) devh, operation, location, offset, (ptr_t) stat); 2553 2554 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 2555 vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 2556 __FILE__, __func__, __LINE__, 2557 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2558 2559 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2560 } 2561 2562 val64 = VXGE_HAL_XMAC_STATS_SYS_CMD_OP(operation) | 2563 VXGE_HAL_XMAC_STATS_SYS_CMD_STROBE | 2564 VXGE_HAL_XMAC_STATS_SYS_CMD_LOC_SEL(location) | 2565 VXGE_HAL_XMAC_STATS_SYS_CMD_OFFSET_SEL(offset); 2566 2567 2568 vxge_hal_pio_mem_write32_lower(hldev->header.pdev, 2569 hldev->header.regh0, 2570 (u32) bVAL32(val64, 32), 2571 &hldev->mrpcim_reg->xmac_stats_sys_cmd); 2572 2573 vxge_os_wmb(); 2574 2575 vxge_hal_pio_mem_write32_upper(hldev->header.pdev, 2576 hldev->header.regh0, 2577 (u32) bVAL32(val64, 0), 2578 &hldev->mrpcim_reg->xmac_stats_sys_cmd); 2579 2580 vxge_os_wmb(); 2581 2582 status = vxge_hal_device_register_poll(hldev->header.pdev, 2583 hldev->header.regh0, 2584 &hldev->mrpcim_reg->xmac_stats_sys_cmd, 2585 0, 2586 VXGE_HAL_XMAC_STATS_SYS_CMD_STROBE, 2587 hldev->header.config.device_poll_millis); 2588 2589 if ((status == VXGE_HAL_OK) && (operation == VXGE_HAL_STATS_OP_READ)) { 2590 2591 *stat = vxge_os_pio_mem_read64(hldev->header.pdev, 2592 hldev->header.regh0, 2593 &hldev->mrpcim_reg->xmac_stats_sys_data); 2594 2595 } else { 2596 *stat = 0; 2597 } 2598 2599 vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 2600 __FILE__, __func__, __LINE__, status); 2601 return (VXGE_HAL_OK); 2602} 2603 2604/* 2605 * vxge_hal_mrpcim_xmac_aggr_stats_get - Get the Statistics on aggregate port 2606 * @devh: HAL device handle. 2607 * @port: Number of the port (0 or 1) 2608 * @aggr_stats: Buffer to return Statistics on aggregate port. 2609 * 2610 * Get the Statistics on aggregate port 2611 * 2612 */ 2613vxge_hal_status_e 2614vxge_hal_mrpcim_xmac_aggr_stats_get(vxge_hal_device_h devh, 2615 u32 port, 2616 vxge_hal_xmac_aggr_stats_t *aggr_stats) 2617{ 2618 u64 val64; 2619 vxge_hal_status_e status = VXGE_HAL_OK; 2620 __hal_device_t *hldev = (__hal_device_t *) devh; 2621 2622 vxge_assert((devh != NULL) && (aggr_stats != NULL)); 2623 2624 vxge_hal_trace_log_stats("==> %s:%s:%d", 2625 __FILE__, __func__, __LINE__); 2626 2627 vxge_hal_trace_log_stats("devh = 0x"VXGE_OS_STXFMT", port = %d, " 2628 "aggr_stats = 0x"VXGE_OS_STXFMT, 2629 (ptr_t) devh, port, (ptr_t) aggr_stats); 2630 2631 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 2632 vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 2633 __FILE__, __func__, __LINE__, 2634 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2635 2636 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2637 } 2638 2639 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 2640 VXGE_HAL_STATS_AGGRn_TX_FRMS_OFFSET(port)); 2641 2642 aggr_stats->tx_frms = 2643 VXGE_HAL_STATS_GET_AGGRn_TX_FRMS(val64); 2644 2645 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 2646 VXGE_HAL_STATS_AGGRn_TX_DATA_OCTETS_OFFSET(port)); 2647 2648 aggr_stats->tx_data_octets = 2649 VXGE_HAL_STATS_GET_AGGRn_TX_DATA_OCTETS(val64); 2650 2651 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 2652 VXGE_HAL_STATS_AGGRn_TX_MCAST_FRMS_OFFSET(port)); 2653 2654 aggr_stats->tx_mcast_frms = 2655 VXGE_HAL_STATS_GET_AGGRn_TX_MCAST_FRMS(val64); 2656 2657 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 2658 VXGE_HAL_STATS_AGGRn_TX_BCAST_FRMS_OFFSET(port)); 2659 2660 aggr_stats->tx_bcast_frms = 2661 VXGE_HAL_STATS_GET_AGGRn_TX_BCAST_FRMS(val64); 2662 2663 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 2664 VXGE_HAL_STATS_AGGRn_TX_DISCARDED_FRMS_OFFSET(port)); 2665 2666 aggr_stats->tx_discarded_frms = 2667 VXGE_HAL_STATS_GET_AGGRn_TX_DISCARDED_FRMS(val64); 2668 2669 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 2670 VXGE_HAL_STATS_AGGRn_TX_ERRORED_FRMS_OFFSET(port)); 2671 2672 aggr_stats->tx_errored_frms = 2673 VXGE_HAL_STATS_GET_AGGRn_TX_ERRORED_FRMS(val64); 2674 2675 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 2676 VXGE_HAL_STATS_AGGRn_RX_FRMS_OFFSET(port)); 2677 2678 aggr_stats->rx_frms = 2679 VXGE_HAL_STATS_GET_AGGRn_RX_FRMS(val64); 2680 2681 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 2682 VXGE_HAL_STATS_AGGRn_RX_DATA_OCTETS_OFFSET(port)); 2683 2684 aggr_stats->rx_data_octets = 2685 VXGE_HAL_STATS_GET_AGGRn_RX_DATA_OCTETS(val64); 2686 2687 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 2688 VXGE_HAL_STATS_AGGRn_RX_MCAST_FRMS_OFFSET(port)); 2689 2690 aggr_stats->rx_mcast_frms = 2691 VXGE_HAL_STATS_GET_AGGRn_RX_MCAST_FRMS(val64); 2692 2693 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 2694 VXGE_HAL_STATS_AGGRn_RX_BCAST_FRMS_OFFSET(port)); 2695 2696 aggr_stats->rx_bcast_frms = 2697 VXGE_HAL_STATS_GET_AGGRn_RX_BCAST_FRMS(val64); 2698 2699 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 2700 VXGE_HAL_STATS_AGGRn_RX_DISCARDED_FRMS_OFFSET(port)); 2701 2702 aggr_stats->rx_discarded_frms = 2703 VXGE_HAL_STATS_GET_AGGRn_RX_DISCARDED_FRMS(val64); 2704 2705 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 2706 VXGE_HAL_STATS_AGGRn_RX_ERRORED_FRMS_OFFSET(port)); 2707 2708 aggr_stats->rx_errored_frms = 2709 VXGE_HAL_STATS_GET_AGGRn_RX_ERRORED_FRMS(val64); 2710 2711 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 2712 VXGE_HAL_STATS_AGGRn_RX_U_SLOW_PROTO_FRMS_OFFSET(port)); 2713 2714 aggr_stats->rx_unknown_slow_proto_frms = 2715 VXGE_HAL_STATS_GET_AGGRn_RX_U_SLOW_PROTO_FRMS(val64); 2716 2717 vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 2718 __FILE__, __func__, __LINE__, status); 2719 return (VXGE_HAL_OK); 2720} 2721 2722 2723/* 2724 * vxge_hal_mrpcim_xmac_port_stats_get - Get the Statistics on a port 2725 * @devh: HAL device handle. 2726 * @port: Number of the port (wire 0, wire 1 or LAG) 2727 * @port_stats: Buffer to return Statistics on a port. 2728 * 2729 * Get the Statistics on port 2730 * 2731 */ 2732vxge_hal_status_e 2733vxge_hal_mrpcim_xmac_port_stats_get(vxge_hal_device_h devh, 2734 u32 port, 2735 vxge_hal_xmac_port_stats_t *port_stats) 2736{ 2737 u64 val64; 2738 vxge_hal_status_e status = VXGE_HAL_OK; 2739 __hal_device_t *hldev = (__hal_device_t *) devh; 2740 2741 vxge_assert((devh != NULL) && (port_stats != NULL)); 2742 2743 vxge_hal_trace_log_stats("==> %s:%s:%d", 2744 __FILE__, __func__, __LINE__); 2745 2746 vxge_hal_trace_log_stats("devh = 0x"VXGE_OS_STXFMT", port = %d, " 2747 "port_stats = 0x"VXGE_OS_STXFMT, 2748 (ptr_t) devh, port, (ptr_t) port_stats); 2749 2750 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 2751 vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 2752 __FILE__, __func__, __LINE__, 2753 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2754 2755 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 2756 } 2757 2758 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2759 VXGE_HAL_STATS_PORTn_TX_TTL_FRMS_OFFSET(port)); 2760 2761 port_stats->tx_ttl_frms = 2762 VXGE_HAL_STATS_GET_PORTn_TX_TTL_FRMS(val64); 2763 2764 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2765 VXGE_HAL_STATS_PORTn_TX_TTL_FRMS_OFFSET(port)); 2766 2767 port_stats->tx_ttl_octets = 2768 VXGE_HAL_STATS_GET_PORTn_TX_TTL_OCTETS(val64); 2769 2770 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2771 VXGE_HAL_STATS_PORTn_TX_DATA_OCTETS_OFFSET(port)); 2772 2773 port_stats->tx_data_octets = 2774 VXGE_HAL_STATS_GET_PORTn_TX_DATA_OCTETS(val64); 2775 2776 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2777 VXGE_HAL_STATS_PORTn_TX_MCAST_FRMS_OFFSET(port)); 2778 2779 port_stats->tx_mcast_frms = 2780 VXGE_HAL_STATS_GET_PORTn_TX_MCAST_FRMS(val64); 2781 2782 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2783 VXGE_HAL_STATS_PORTn_TX_BCAST_FRMS_OFFSET(port)); 2784 2785 port_stats->tx_bcast_frms = 2786 VXGE_HAL_STATS_GET_PORTn_TX_BCAST_FRMS(val64); 2787 2788 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2789 VXGE_HAL_STATS_PORTn_TX_UCAST_FRMS_OFFSET(port)); 2790 2791 port_stats->tx_ucast_frms = 2792 VXGE_HAL_STATS_GET_PORTn_TX_UCAST_FRMS(val64); 2793 2794 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2795 VXGE_HAL_STATS_PORTn_TX_TAGGED_FRMS_OFFSET(port)); 2796 2797 port_stats->tx_tagged_frms = 2798 VXGE_HAL_STATS_GET_PORTn_TX_TAGGED_FRMS(val64); 2799 2800 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2801 VXGE_HAL_STATS_PORTn_TX_VLD_IP_OFFSET(port)); 2802 2803 port_stats->tx_vld_ip = 2804 VXGE_HAL_STATS_GET_PORTn_TX_VLD_IP(val64); 2805 2806 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2807 VXGE_HAL_STATS_PORTn_TX_VLD_IP_OCTETS_OFFSET(port)); 2808 2809 port_stats->tx_vld_ip_octets = 2810 VXGE_HAL_STATS_GET_PORTn_TX_VLD_IP_OCTETS(val64); 2811 2812 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2813 VXGE_HAL_STATS_PORTn_TX_ICMP_OFFSET(port)); 2814 2815 port_stats->tx_icmp = 2816 VXGE_HAL_STATS_GET_PORTn_TX_ICMP(val64); 2817 2818 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2819 VXGE_HAL_STATS_PORTn_TX_TCP_OFFSET(port)); 2820 2821 port_stats->tx_tcp = 2822 VXGE_HAL_STATS_GET_PORTn_TX_TCP(val64); 2823 2824 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2825 VXGE_HAL_STATS_PORTn_TX_RST_TCP_OFFSET(port)); 2826 2827 port_stats->tx_rst_tcp = 2828 VXGE_HAL_STATS_GET_PORTn_TX_RST_TCP(val64); 2829 2830 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2831 VXGE_HAL_STATS_PORTn_TX_UDP_OFFSET(port)); 2832 2833 port_stats->tx_udp = 2834 VXGE_HAL_STATS_GET_PORTn_TX_UDP(val64); 2835 2836 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2837 VXGE_HAL_STATS_PORTn_TX_UNKNOWN_PROTOCOL_OFFSET(port)); 2838 2839 port_stats->tx_unknown_protocol = 2840 (u32) VXGE_HAL_STATS_GET_PORTn_TX_UNKNOWN_PROTOCOL(val64); 2841 2842 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2843 VXGE_HAL_STATS_PORTn_TX_PARSE_ERROR_OFFSET(port)); 2844 2845 port_stats->tx_parse_error = 2846 (u32) VXGE_HAL_STATS_GET_PORTn_TX_PARSE_ERROR(val64); 2847 2848 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2849 VXGE_HAL_STATS_PORTn_TX_PAUSE_CTRL_FRMS_OFFSET(port)); 2850 2851 port_stats->tx_pause_ctrl_frms = 2852 VXGE_HAL_STATS_GET_PORTn_TX_PAUSE_CTRL_FRMS(val64); 2853 2854 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2855 VXGE_HAL_STATS_PORTn_TX_LACPDU_FRMS_OFFSET(port)); 2856 2857 port_stats->tx_lacpdu_frms = 2858 (u32) VXGE_HAL_STATS_GET_PORTn_TX_LACPDU_FRMS(val64); 2859 2860 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2861 VXGE_HAL_STATS_PORTn_TX_MRKR_PDU_FRMS_OFFSET(port)); 2862 2863 port_stats->tx_marker_pdu_frms = 2864 (u32) VXGE_HAL_STATS_GET_PORTn_TX_MRKR_PDU_FRMS(val64); 2865 2866 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2867 VXGE_HAL_STATS_PORTn_TX_MRKR_RESP_PDU_FRMS_OFFSET(port)); 2868 2869 port_stats->tx_marker_resp_pdu_frms = 2870 (u32) VXGE_HAL_STATS_GET_PORTn_TX_MRKR_RESP_PDU_FRMS(val64); 2871 2872 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2873 VXGE_HAL_STATS_PORTn_TX_DROP_IP_OFFSET(port)); 2874 2875 port_stats->tx_drop_ip = 2876 (u32) VXGE_HAL_STATS_GET_PORTn_TX_DROP_IP(val64); 2877 2878 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2879 VXGE_HAL_STATS_PORTn_TX_XGMII_CHAR1_MATCH_OFFSET(port)); 2880 2881 port_stats->tx_xgmii_char1_match = 2882 (u32) VXGE_HAL_STATS_GET_PORTn_TX_XGMII_CHAR1_MATCH(val64); 2883 2884 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2885 VXGE_HAL_STATS_PORTn_TX_XGMII_CHAR2_MATCH_OFFSET(port)); 2886 2887 port_stats->tx_xgmii_char2_match = 2888 (u32) VXGE_HAL_STATS_GET_PORTn_TX_XGMII_CHAR2_MATCH(val64); 2889 2890 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2891 VXGE_HAL_STATS_PORTn_TX_XGMII_COL1_MATCH_OFFSET(port)); 2892 2893 port_stats->tx_xgmii_column1_match = 2894 (u32) VXGE_HAL_STATS_GET_PORTn_TX_XGMII_COL1_MATCH(val64); 2895 2896 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2897 VXGE_HAL_STATS_PORTn_TX_XGMII_COL2_MATCH_OFFSET(port)); 2898 2899 port_stats->tx_xgmii_column2_match = 2900 (u32) VXGE_HAL_STATS_GET_PORTn_TX_XGMII_COL2_MATCH(val64); 2901 2902 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2903 VXGE_HAL_STATS_PORTn_TX_DROP_FRMS_OFFSET(port)); 2904 2905 port_stats->tx_drop_frms = 2906 (u16) VXGE_HAL_STATS_GET_PORTn_TX_DROP_FRMS(val64); 2907 2908 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2909 VXGE_HAL_STATS_PORTn_TX_ANY_ERR_FRMS_OFFSET(port)); 2910 2911 port_stats->tx_any_err_frms = 2912 (u16) VXGE_HAL_STATS_GET_PORTn_TX_ANY_ERR_FRMS(val64); 2913 2914 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2915 VXGE_HAL_STATS_PORTn_RX_TTL_FRMS_OFFSET(port)); 2916 2917 port_stats->rx_ttl_frms = 2918 VXGE_HAL_STATS_GET_PORTn_RX_TTL_FRMS(val64); 2919 2920 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2921 VXGE_HAL_STATS_PORTn_RX_VLD_FRMS_OFFSET(port)); 2922 2923 port_stats->rx_vld_frms = 2924 VXGE_HAL_STATS_GET_PORTn_RX_VLD_FRMS(val64); 2925 2926 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2927 VXGE_HAL_STATS_PORTn_RX_OFFLOAD_FRMS_OFFSET(port)); 2928 2929 port_stats->rx_offload_frms = 2930 VXGE_HAL_STATS_GET_PORTn_RX_OFFLOAD_FRMS(val64); 2931 2932 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2933 VXGE_HAL_STATS_PORTn_RX_TTL_OCTETS_OFFSET(port)); 2934 2935 port_stats->rx_ttl_octets = 2936 VXGE_HAL_STATS_GET_PORTn_RX_TTL_OCTETS(val64); 2937 2938 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2939 VXGE_HAL_STATS_PORTn_RX_DATA_OCTETS_OFFSET(port)); 2940 2941 port_stats->rx_data_octets = 2942 VXGE_HAL_STATS_GET_PORTn_RX_DATA_OCTETS(val64); 2943 2944 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2945 VXGE_HAL_STATS_PORTn_RX_OFFLOAD_OCTETS_OFFSET(port)); 2946 2947 port_stats->rx_offload_octets = 2948 VXGE_HAL_STATS_GET_PORTn_RX_OFFLOAD_OCTETS(val64); 2949 2950 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2951 VXGE_HAL_STATS_PORTn_RX_VLD_MCAST_FRMS_OFFSET(port)); 2952 2953 port_stats->rx_vld_mcast_frms = 2954 VXGE_HAL_STATS_GET_PORTn_RX_VLD_MCAST_FRMS(val64); 2955 2956 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2957 VXGE_HAL_STATS_PORTn_RX_VLD_BCAST_FRMS_OFFSET(port)); 2958 2959 port_stats->rx_vld_bcast_frms = 2960 VXGE_HAL_STATS_GET_PORTn_RX_VLD_BCAST_FRMS(val64); 2961 2962 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2963 VXGE_HAL_STATS_PORTn_RX_ACC_UCAST_FRMS_OFFSET(port)); 2964 2965 port_stats->rx_accepted_ucast_frms = 2966 VXGE_HAL_STATS_GET_PORTn_RX_ACC_UCAST_FRMS(val64); 2967 2968 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2969 VXGE_HAL_STATS_PORTn_RX_ACC_NUCAST_FRMS_OFFSET(port)); 2970 2971 port_stats->rx_accepted_nucast_frms = 2972 VXGE_HAL_STATS_GET_PORTn_RX_ACC_NUCAST_FRMS(val64); 2973 2974 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2975 VXGE_HAL_STATS_PORTn_RX_TAGGED_FRMS_OFFSET(port)); 2976 2977 port_stats->rx_tagged_frms = 2978 VXGE_HAL_STATS_GET_PORTn_RX_TAGGED_FRMS(val64); 2979 2980 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2981 VXGE_HAL_STATS_PORTn_RX_LONG_FRMS_OFFSET(port)); 2982 2983 port_stats->rx_long_frms = 2984 VXGE_HAL_STATS_GET_PORTn_RX_LONG_FRMS(val64); 2985 2986 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2987 VXGE_HAL_STATS_PORTn_RX_USIZED_FRMS_OFFSET(port)); 2988 2989 port_stats->rx_usized_frms = 2990 VXGE_HAL_STATS_GET_PORTn_RX_USIZED_FRMS(val64); 2991 2992 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2993 VXGE_HAL_STATS_PORTn_RX_OSIZED_FRMS_OFFSET(port)); 2994 2995 port_stats->rx_osized_frms = 2996 VXGE_HAL_STATS_GET_PORTn_RX_OSIZED_FRMS(val64); 2997 2998 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 2999 VXGE_HAL_STATS_PORTn_RX_FRAG_FRMS_OFFSET(port)); 3000 3001 port_stats->rx_frag_frms = 3002 VXGE_HAL_STATS_GET_PORTn_RX_FRAG_FRMS(val64); 3003 3004 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3005 VXGE_HAL_STATS_PORTn_RX_JABBER_FRMS_OFFSET(port)); 3006 3007 port_stats->rx_jabber_frms = 3008 VXGE_HAL_STATS_GET_PORTn_RX_JABBER_FRMS(val64); 3009 3010 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3011 VXGE_HAL_STATS_PORTn_RX_TTL_64_FRMS_OFFSET(port)); 3012 3013 port_stats->rx_ttl_64_frms = 3014 VXGE_HAL_STATS_GET_PORTn_RX_TTL_64_FRMS(val64); 3015 3016 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3017 VXGE_HAL_STATS_PORTn_RX_TTL_65_127_FRMS_OFFSET(port)); 3018 3019 port_stats->rx_ttl_65_127_frms = 3020 VXGE_HAL_STATS_GET_PORTn_RX_TTL_65_127_FRMS(val64); 3021 3022 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3023 VXGE_HAL_STATS_PORTn_RX_TTL_128_255_FRMS_OFFSET(port)); 3024 3025 port_stats->rx_ttl_128_255_frms = 3026 VXGE_HAL_STATS_GET_PORTn_RX_TTL_128_255_FRMS(val64); 3027 3028 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3029 VXGE_HAL_STATS_PORTn_RX_TTL_256_511_FRMS_OFFSET(port)); 3030 3031 port_stats->rx_ttl_256_511_frms = 3032 VXGE_HAL_STATS_GET_PORTn_RX_TTL_256_511_FRMS(val64); 3033 3034 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3035 VXGE_HAL_STATS_PORTn_RX_TTL_512_1023_FRMS_OFFSET(port)); 3036 3037 port_stats->rx_ttl_512_1023_frms = 3038 VXGE_HAL_STATS_GET_PORTn_RX_TTL_512_1023_FRMS(val64); 3039 3040 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3041 VXGE_HAL_STATS_PORTn_RX_TTL_1024_1518_FRMS_OFFSET(port)); 3042 3043 port_stats->rx_ttl_1024_1518_frms = 3044 VXGE_HAL_STATS_GET_PORTn_RX_TTL_1024_1518_FRMS(val64); 3045 3046 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3047 VXGE_HAL_STATS_PORTn_RX_TTL_1519_4095_FRMS_OFFSET(port)); 3048 3049 port_stats->rx_ttl_1519_4095_frms = 3050 VXGE_HAL_STATS_GET_PORTn_RX_TTL_1519_4095_FRMS(val64); 3051 3052 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3053 VXGE_HAL_STATS_PORTn_RX_TTL_4096_81915_FRMS_OFFSET(port)); 3054 3055 port_stats->rx_ttl_4096_8191_frms = 3056 VXGE_HAL_STATS_GET_PORTn_RX_TTL_4096_8191_FRMS(val64); 3057 3058 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3059 VXGE_HAL_STATS_PORTn_RX_TTL_8192_MAX_FRMS_OFFSET(port)); 3060 3061 port_stats->rx_ttl_8192_max_frms = 3062 VXGE_HAL_STATS_GET_PORTn_RX_TTL_8192_MAX_FRMS(val64); 3063 3064 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3065 VXGE_HAL_STATS_PORTn_RX_TTL_GT_MAX_FRMS_OFFSET(port)); 3066 3067 port_stats->rx_ttl_gt_max_frms = 3068 VXGE_HAL_STATS_GET_PORTn_RX_TTL_GT_MAX_FRMS(val64); 3069 3070 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3071 VXGE_HAL_STATS_PORTn_RX_IP_OFFSET(port)); 3072 3073 port_stats->rx_ip = VXGE_HAL_STATS_GET_PORTn_RX_IP(val64); 3074 3075 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3076 VXGE_HAL_STATS_PORTn_RX_ACC_IP_OFFSET(port)); 3077 3078 port_stats->rx_accepted_ip = 3079 VXGE_HAL_STATS_GET_PORTn_RX_ACC_IP(val64); 3080 3081 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3082 VXGE_HAL_STATS_PORTn_RX_IP_OCTETS_OFFSET(port)); 3083 3084 port_stats->rx_ip_octets = 3085 VXGE_HAL_STATS_GET_PORTn_RX_IP_OCTETS(val64); 3086 3087 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3088 VXGE_HAL_STATS_PORTn_RX_ERR_IP_OFFSET(port)); 3089 3090 port_stats->rx_err_ip = 3091 VXGE_HAL_STATS_GET_PORTn_RX_ERR_IP(val64); 3092 3093 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3094 VXGE_HAL_STATS_PORTn_RX_ICMP_OFFSET(port)); 3095 3096 port_stats->rx_icmp = VXGE_HAL_STATS_GET_PORTn_RX_ICMP(val64); 3097 3098 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3099 VXGE_HAL_STATS_PORTn_RX_TCP_OFFSET(port)); 3100 3101 port_stats->rx_tcp = VXGE_HAL_STATS_GET_PORTn_RX_TCP(val64); 3102 3103 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3104 VXGE_HAL_STATS_PORTn_RX_UDP_OFFSET(port)); 3105 3106 port_stats->rx_udp = VXGE_HAL_STATS_GET_PORTn_RX_UDP(val64); 3107 3108 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3109 VXGE_HAL_STATS_PORTn_RX_ERR_TCP_OFFSET(port)); 3110 3111 port_stats->rx_err_tcp = VXGE_HAL_STATS_GET_PORTn_RX_ERR_TCP(val64); 3112 3113 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3114 VXGE_HAL_STATS_PORTn_RX_PAUSE_CNT_OFFSET(port)); 3115 3116 port_stats->rx_pause_count = 3117 VXGE_HAL_STATS_GET_PORTn_RX_PAUSE_CNT(val64); 3118 3119 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3120 VXGE_HAL_STATS_PORTn_RX_PAUSE_CTRL_FRMS_OFFSET(port)); 3121 3122 port_stats->rx_pause_ctrl_frms = 3123 VXGE_HAL_STATS_GET_PORTn_RX_PAUSE_CTRL_FRMS(val64); 3124 3125 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3126 VXGE_HAL_STATS_PORTn_RX_UNSUP_CTRL_FRMS_OFFSET(port)); 3127 3128 port_stats->rx_unsup_ctrl_frms = 3129 VXGE_HAL_STATS_GET_PORTn_RX_UNSUP_CTRL_FRMS(val64); 3130 3131 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3132 VXGE_HAL_STATS_PORTn_RX_FCS_ERR_FRMS_OFFSET(port)); 3133 3134 port_stats->rx_fcs_err_frms = 3135 VXGE_HAL_STATS_GET_PORTn_RX_FCS_ERR_FRMS(val64); 3136 3137 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3138 VXGE_HAL_STATS_PORTn_RX_IN_RNG_LEN_ERR_FRMS_OFFSET(port)); 3139 3140 port_stats->rx_in_rng_len_err_frms = 3141 VXGE_HAL_STATS_GET_PORTn_RX_IN_RNG_LEN_ERR_FRMS(val64); 3142 3143 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3144 VXGE_HAL_STATS_PORTn_RX_OUT_RNG_LEN_ERR_FRMS_OFFSET(port)); 3145 3146 port_stats->rx_out_rng_len_err_frms = 3147 VXGE_HAL_STATS_GET_PORTn_RX_OUT_RNG_LEN_ERR_FRMS(val64); 3148 3149 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3150 VXGE_HAL_STATS_PORTn_RX_DROP_FRMS_OFFSET(port)); 3151 3152 port_stats->rx_drop_frms = 3153 VXGE_HAL_STATS_GET_PORTn_RX_DROP_FRMS(val64); 3154 3155 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3156 VXGE_HAL_STATS_PORTn_RX_DISCARDED_FRMS_OFFSET(port)); 3157 3158 port_stats->rx_discarded_frms = 3159 VXGE_HAL_STATS_GET_PORTn_RX_DISCARDED_FRMS(val64); 3160 3161 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3162 VXGE_HAL_STATS_PORTn_RX_DROP_IP_OFFSET(port)); 3163 3164 port_stats->rx_drop_ip = 3165 VXGE_HAL_STATS_GET_PORTn_RX_DROP_IP(val64); 3166 3167 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3168 VXGE_HAL_STATS_PORTn_RX_DRP_UDP_OFFSET(port)); 3169 3170 port_stats->rx_drop_udp = 3171 VXGE_HAL_STATS_GET_PORTn_RX_DRP_UDP(val64); 3172 3173 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3174 VXGE_HAL_STATS_PORTn_RX_LACPDU_FRMS_OFFSET(port)); 3175 3176 port_stats->rx_lacpdu_frms = 3177 (u32) VXGE_HAL_STATS_GET_PORTn_RX_LACPDU_FRMS(val64); 3178 3179 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3180 VXGE_HAL_STATS_PORTn_RX_MRKR_PDU_FRMS_OFFSET(port)); 3181 3182 port_stats->rx_marker_pdu_frms = 3183 (u32) VXGE_HAL_STATS_GET_PORTn_RX_MRKR_PDU_FRMS(val64); 3184 3185 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3186 VXGE_HAL_STATS_PORTn_RX_MRKR_RESP_PDU_FRMS_OFFSET(port)); 3187 3188 port_stats->rx_marker_resp_pdu_frms = 3189 (u32) VXGE_HAL_STATS_GET_PORTn_RX_MRKR_RESP_PDU_FRMS(val64); 3190 3191 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3192 VXGE_HAL_STATS_PORTn_RX_UNKNOWN_PDU_FRMS_OFFSET(port)); 3193 3194 port_stats->rx_unknown_pdu_frms = 3195 (u32) VXGE_HAL_STATS_GET_PORTn_RX_UNKNOWN_PDU_FRMS(val64); 3196 3197 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3198 VXGE_HAL_STATS_PORTn_RX_ILLEGAL_PDU_FRMS_OFFSET(port)); 3199 3200 port_stats->rx_illegal_pdu_frms = 3201 (u32) VXGE_HAL_STATS_GET_PORTn_RX_ILLEGAL_PDU_FRMS(val64); 3202 3203 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3204 VXGE_HAL_STATS_PORTn_RX_FCS_DISCARD_OFFSET(port)); 3205 3206 port_stats->rx_fcs_discard = 3207 (u32) VXGE_HAL_STATS_GET_PORTn_RX_FCS_DISCARD(val64); 3208 3209 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3210 VXGE_HAL_STATS_PORTn_RX_LEN_DISCARD_OFFSET(port)); 3211 3212 port_stats->rx_len_discard = 3213 (u32) VXGE_HAL_STATS_GET_PORTn_RX_LEN_DISCARD(val64); 3214 3215 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3216 VXGE_HAL_STATS_PORTn_RX_SWITCH_DISCARD_OFFSET(port)); 3217 3218 port_stats->rx_switch_discard = 3219 (u32) VXGE_HAL_STATS_GET_PORTn_RX_SWITCH_DISCARD(val64); 3220 3221 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3222 VXGE_HAL_STATS_PORTn_RX_L2_MGMT_DISCARD_OFFSET(port)); 3223 3224 port_stats->rx_l2_mgmt_discard = 3225 (u32) VXGE_HAL_STATS_GET_PORTn_RX_L2_MGMT_DISCARD(val64); 3226 3227 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3228 VXGE_HAL_STATS_PORTn_RX_RPA_DISCARD_OFFSET(port)); 3229 3230 port_stats->rx_rpa_discard = 3231 (u32) VXGE_HAL_STATS_GET_PORTn_RX_RPA_DISCARD(val64); 3232 3233 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3234 VXGE_HAL_STATS_PORTn_RX_TRASH_DISCARD_OFFSET(port)); 3235 3236 port_stats->rx_trash_discard = 3237 (u32) VXGE_HAL_STATS_GET_PORTn_RX_TRASH_DISCARD(val64); 3238 3239 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3240 VXGE_HAL_STATS_PORTn_RX_RTS_DISCARD_OFFSET(port)); 3241 3242 port_stats->rx_rts_discard = 3243 (u32) VXGE_HAL_STATS_GET_PORTn_RX_RTS_DISCARD(val64); 3244 3245 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3246 VXGE_HAL_STATS_PORTn_RX_RED_DISCARD_OFFSET(port)); 3247 3248 port_stats->rx_red_discard = 3249 (u32) VXGE_HAL_STATS_GET_PORTn_RX_RED_DISCARD(val64); 3250 3251 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3252 VXGE_HAL_STATS_PORTn_RX_BUFF_FULL_DISCARD_OFFSET(port)); 3253 3254 port_stats->rx_buff_full_discard = 3255 (u32) VXGE_HAL_STATS_GET_PORTn_RX_BUFF_FULL_DISCARD(val64); 3256 3257 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3258 VXGE_HAL_STATS_PORTn_RX_XGMII_DATA_ERR_CNT_OFFSET(port)); 3259 3260 port_stats->rx_xgmii_data_err_cnt = 3261 (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_DATA_ERR_CNT(val64); 3262 3263 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3264 VXGE_HAL_STATS_PORTn_RX_XGMII_CTRL_ERR_CNT_OFFSET(port)); 3265 3266 port_stats->rx_xgmii_ctrl_err_cnt = 3267 (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_CTRL_ERR_CNT(val64); 3268 3269 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3270 VXGE_HAL_STATS_PORTn_RX_XGMII_ERR_SYM_OFFSET(port)); 3271 3272 port_stats->rx_xgmii_err_sym = 3273 (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_ERR_SYM(val64); 3274 3275 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3276 VXGE_HAL_STATS_PORTn_RX_XGMII_CHAR1_MATCH_OFFSET(port)); 3277 3278 port_stats->rx_xgmii_char1_match = 3279 (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_CHAR1_MATCH(val64); 3280 3281 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3282 VXGE_HAL_STATS_PORTn_RX_XGMII_CHAR2_MATCH_OFFSET(port)); 3283 3284 port_stats->rx_xgmii_char2_match = 3285 (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_CHAR2_MATCH(val64); 3286 3287 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3288 VXGE_HAL_STATS_PORTn_RX_XGMII_COL1_MATCH_OFFSET(port)); 3289 3290 port_stats->rx_xgmii_column1_match = 3291 (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_COL1_MATCH(val64); 3292 3293 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3294 VXGE_HAL_STATS_PORTn_RX_XGMII_COL2_MATCH_OFFSET(port)); 3295 3296 port_stats->rx_xgmii_column2_match = 3297 (u32) VXGE_HAL_STATS_GET_PORTn_RX_XGMII_COL2_MATCH(val64); 3298 3299 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3300 VXGE_HAL_STATS_PORTn_RX_LOCAL_FAULT_OFFSET(port)); 3301 3302 port_stats->rx_local_fault = 3303 (u32) VXGE_HAL_STATS_GET_PORTn_RX_LOCAL_FAULT(val64); 3304 3305 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3306 VXGE_HAL_STATS_PORTn_RX_REMOTE_FAULT_OFFSET(port)); 3307 3308 port_stats->rx_remote_fault = 3309 (u32) VXGE_HAL_STATS_GET_PORTn_RX_REMOTE_FAULT(val64); 3310 3311 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_PORT, 3312 VXGE_HAL_STATS_PORTn_RX_JETTISON_OFFSET(port)); 3313 3314 port_stats->rx_jettison = 3315 (u32) VXGE_HAL_STATS_GET_PORTn_RX_JETTISON(val64); 3316 3317 3318 vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 3319 __FILE__, __func__, __LINE__, status); 3320 return (VXGE_HAL_OK); 3321} 3322 3323 3324/* 3325 * vxge_hal_mrpcim_xmac_stats_get - Get the XMAC Statistics 3326 * @devh: HAL device handle. 3327 * @xmac_stats: Buffer to return XMAC Statistics. 3328 * 3329 * Get the XMAC Statistics 3330 * 3331 */ 3332vxge_hal_status_e 3333vxge_hal_mrpcim_xmac_stats_get(vxge_hal_device_h devh, 3334 vxge_hal_mrpcim_xmac_stats_t *xmac_stats) 3335{ 3336 u32 i; 3337 __hal_device_t *hldev = (__hal_device_t *) devh; 3338 vxge_hal_status_e status = VXGE_HAL_OK; 3339 3340 vxge_assert((devh != NULL) && (xmac_stats != NULL)); 3341 3342 vxge_hal_trace_log_stats("==> %s:%s:%d", 3343 __FILE__, __func__, __LINE__); 3344 3345 vxge_hal_trace_log_stats( 3346 "hldev = 0x"VXGE_OS_STXFMT", mrpcim_stats = 0x"VXGE_OS_STXFMT, 3347 (ptr_t) devh, (ptr_t) xmac_stats); 3348 3349 3350 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 3351 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 3352 __FILE__, __func__, __LINE__, 3353 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 3354 3355 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 3356 } 3357 3358 status = vxge_hal_mrpcim_xmac_aggr_stats_get(devh, 3359 0, 3360 &xmac_stats->aggr_stats[0]); 3361 3362 if (status != VXGE_HAL_OK) { 3363 vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 3364 __FILE__, __func__, __LINE__, status); 3365 return (status); 3366 } 3367 3368 status = vxge_hal_mrpcim_xmac_aggr_stats_get(devh, 3369 1, 3370 &xmac_stats->aggr_stats[1]); 3371 3372 if (status != VXGE_HAL_OK) { 3373 vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 3374 __FILE__, __func__, __LINE__, status); 3375 return (status); 3376 } 3377 3378 for (i = 0; i < VXGE_HAL_MAC_MAX_PORTS; i++) { 3379 3380 status = vxge_hal_mrpcim_xmac_port_stats_get(devh, 3381 i, 3382 &xmac_stats->port_stats[i]); 3383 3384 if (status != VXGE_HAL_OK) { 3385 vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 3386 __FILE__, __func__, __LINE__, status); 3387 return (status); 3388 } 3389 3390 } 3391 3392 vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 3393 __FILE__, __func__, __LINE__, status); 3394 return (status); 3395} 3396 3397/* 3398 * _hal_mrpcim_stats_get - Get the mrpcim statistics using PIO 3399 * @hldev: hal device. 3400 * @mrpcim_stats: MRPCIM stats 3401 * 3402 * Returns the mrpcim stats. 3403 * 3404 * See also: vxge_hal_mrpcim_stats_enable(), vxge_hal_mrpcim_stats_disable() 3405 */ 3406vxge_hal_status_e 3407__hal_mrpcim_stats_get( 3408 __hal_device_t *hldev, 3409 vxge_hal_mrpcim_stats_hw_info_t *mrpcim_stats) 3410{ 3411 u32 i; 3412 u64 val64; 3413 vxge_hal_device_h devh = (vxge_hal_device_h) hldev; 3414 vxge_hal_status_e status = VXGE_HAL_OK; 3415 3416 vxge_assert((hldev != NULL) && (mrpcim_stats != NULL)); 3417 3418 vxge_hal_trace_log_stats("==> %s:%s:%d", 3419 __FILE__, __func__, __LINE__); 3420 3421 vxge_hal_trace_log_stats( 3422 "hldev = 0x"VXGE_OS_STXFMT", mrpcim_stats = 0x"VXGE_OS_STXFMT, 3423 (ptr_t) hldev, (ptr_t) mrpcim_stats); 3424 3425 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3426 hldev->header.regh0, 3427 &hldev->mrpcim_reg->mrpcim_debug_stats0); 3428 3429 mrpcim_stats->pic_ini_rd_drop = 3430 (u32) VXGE_HAL_MRPCIM_DEBUG_STATS0_GET_INI_RD_DROP(val64); 3431 3432 mrpcim_stats->pic_ini_wr_drop = 3433 (u32) VXGE_HAL_MRPCIM_DEBUG_STATS0_GET_INI_WR_DROP(val64); 3434 3435 for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) { 3436 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3437 hldev->header.regh0, 3438 &hldev->mrpcim_reg->mrpcim_debug_stats1_vplane[i]); 3439 3440 mrpcim_stats->pic_wrcrdtarb_ph_crdt_depleted_vplane[i]. 3441 pic_wrcrdtarb_ph_crdt_depleted = (u32) 3442 VXGE_HAL_MRPCIM_DEBUG_STATS1_GET_VPLANE_WRCRDTARB_PH_CRDT_DEPLETED( 3443 val64); 3444 3445 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3446 hldev->header.regh0, 3447 &hldev->mrpcim_reg->mrpcim_debug_stats2_vplane[i]); 3448 3449 mrpcim_stats->pic_wrcrdtarb_pd_crdt_depleted_vplane[i]. 3450 pic_wrcrdtarb_pd_crdt_depleted = (u32) 3451 VXGE_HAL_MRPCIM_DEBUG_STATS2_GET_VPLANE_WRCRDTARB_PD_CRDT_DEPLETED( 3452 val64); 3453 3454 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3455 hldev->header.regh0, 3456 &hldev->mrpcim_reg->mrpcim_debug_stats3_vplane[i]); 3457 3458 mrpcim_stats->pic_rdcrdtarb_nph_crdt_depleted_vplane[i]. 3459 pic_rdcrdtarb_nph_crdt_depleted = (u32) 3460 VXGE_HAL_MRPCIM_DEBUG_STATS3_GET_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED( 3461 val64); 3462 } 3463 3464 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3465 hldev->header.regh0, 3466 &hldev->mrpcim_reg->mrpcim_debug_stats4); 3467 3468 mrpcim_stats->pic_ini_rd_vpin_drop = 3469 (u32) VXGE_HAL_MRPCIM_DEBUG_STATS4_GET_INI_RD_VPIN_DROP(val64); 3470 3471 mrpcim_stats->pic_ini_wr_vpin_drop = 3472 (u32) VXGE_HAL_MRPCIM_DEBUG_STATS4_GET_INI_WR_VPIN_DROP(val64); 3473 3474 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3475 hldev->header.regh0, 3476 &hldev->mrpcim_reg->genstats_count01); 3477 3478 mrpcim_stats->pic_genstats_count0 = 3479 (u32) VXGE_HAL_GENSTATS_COUNT01_GET_GENSTATS_COUNT0(val64); 3480 3481 mrpcim_stats->pic_genstats_count1 = 3482 (u32) VXGE_HAL_GENSTATS_COUNT01_GET_GENSTATS_COUNT1(val64); 3483 3484 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3485 hldev->header.regh0, 3486 &hldev->mrpcim_reg->genstats_count23); 3487 3488 mrpcim_stats->pic_genstats_count2 = 3489 (u32) VXGE_HAL_GENSTATS_COUNT23_GET_GENSTATS_COUNT2(val64); 3490 3491 mrpcim_stats->pic_genstats_count3 = 3492 (u32) VXGE_HAL_GENSTATS_COUNT23_GET_GENSTATS_COUNT3(val64); 3493 3494 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3495 hldev->header.regh0, 3496 &hldev->mrpcim_reg->genstats_count4); 3497 3498 mrpcim_stats->pic_genstats_count4 = 3499 (u32) VXGE_HAL_GENSTATS_COUNT4_GET_GENSTATS_COUNT4(val64); 3500 3501 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3502 hldev->header.regh0, 3503 &hldev->mrpcim_reg->genstats_count5); 3504 3505 mrpcim_stats->pic_genstats_count5 = 3506 (u32) VXGE_HAL_GENSTATS_COUNT5_GET_GENSTATS_COUNT5(val64); 3507 3508 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3509 hldev->header.regh0, 3510 &hldev->mrpcim_reg->debug_stats0); 3511 3512 mrpcim_stats->pci_rstdrop_cpl = 3513 (u32) VXGE_HAL_DEBUG_STATS0_GET_RSTDROP_CPL(val64); 3514 3515 mrpcim_stats->pci_rstdrop_msg = 3516 (u32) VXGE_HAL_DEBUG_STATS0_GET_RSTDROP_MSG(val64); 3517 3518 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3519 hldev->header.regh0, 3520 &hldev->mrpcim_reg->debug_stats1); 3521 3522 mrpcim_stats->pci_rstdrop_client0 = 3523 (u32) VXGE_HAL_DEBUG_STATS1_GET_RSTDROP_CLIENT0(val64); 3524 3525 mrpcim_stats->pci_rstdrop_client1 = 3526 (u32) VXGE_HAL_DEBUG_STATS1_GET_RSTDROP_CLIENT1(val64); 3527 3528 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3529 hldev->header.regh0, 3530 &hldev->mrpcim_reg->debug_stats2); 3531 3532 mrpcim_stats->pci_rstdrop_client2 = 3533 (u32) VXGE_HAL_DEBUG_STATS2_GET_RSTDROP_CLIENT2(val64); 3534 3535 for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) { 3536 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3537 hldev->header.regh0, 3538 &hldev->mrpcim_reg->debug_stats3_vplane); 3539 3540 mrpcim_stats->pci_depl_h_vplane[i].pci_depl_cplh = 3541 (u16) VXGE_HAL_DEBUG_STATS3_GET_VPLANE_DEPL_CPLH(val64); 3542 3543 mrpcim_stats->pci_depl_h_vplane[i].pci_depl_nph = 3544 (u16) VXGE_HAL_DEBUG_STATS3_GET_VPLANE_DEPL_NPH(val64); 3545 3546 mrpcim_stats->pci_depl_h_vplane[i].pci_depl_ph = 3547 (u16) VXGE_HAL_DEBUG_STATS3_GET_VPLANE_DEPL_PH(val64); 3548 3549 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3550 hldev->header.regh0, 3551 &hldev->mrpcim_reg->debug_stats4_vplane); 3552 3553 mrpcim_stats->pci_depl_d_vplane[i].pci_depl_cpld = 3554 (u16) VXGE_HAL_DEBUG_STATS4_GET_VPLANE_DEPL_CPLD(val64); 3555 3556 mrpcim_stats->pci_depl_d_vplane[i].pci_depl_npd = 3557 (u16) VXGE_HAL_DEBUG_STATS4_GET_VPLANE_DEPL_NPD(val64); 3558 3559 mrpcim_stats->pci_depl_d_vplane[i].pci_depl_pd = 3560 (u16) VXGE_HAL_DEBUG_STATS4_GET_VPLANE_DEPL_PD(val64); 3561 } 3562 3563 status = vxge_hal_mrpcim_xmac_aggr_stats_get(hldev, 3564 0, 3565 &mrpcim_stats->xgmac_aggr[0]); 3566 3567 if (status != VXGE_HAL_OK) { 3568 vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 3569 __FILE__, __func__, __LINE__, status); 3570 return (status); 3571 } 3572 3573 status = vxge_hal_mrpcim_xmac_aggr_stats_get(hldev, 3574 1, 3575 &mrpcim_stats->xgmac_aggr[1]); 3576 3577 if (status != VXGE_HAL_OK) { 3578 vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 3579 __FILE__, __func__, __LINE__, status); 3580 return (status); 3581 } 3582 3583 for (i = 0; i < VXGE_HAL_MAC_MAX_PORTS; i++) { 3584 3585 status = vxge_hal_mrpcim_xmac_port_stats_get(hldev, 3586 i, 3587 &mrpcim_stats->xgmac_port[i]); 3588 3589 if (status != VXGE_HAL_OK) { 3590 vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 3591 __FILE__, __func__, __LINE__, status); 3592 return (status); 3593 } 3594 3595 } 3596 3597 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 3598 VXGE_HAL_STATS_GLOBAL_PROG_EVENT_GNUM0_OFFSET); 3599 3600 mrpcim_stats->xgmac_global_prog_event_gnum0 = 3601 VXGE_HAL_STATS_GET_GLOBAL_PROG_EVENT_GNUM0(val64); 3602 3603 VXGE_HAL_MRPCIM_STATS_PIO_READ(VXGE_HAL_STATS_LOC_AGGR, 3604 VXGE_HAL_STATS_GLOBAL_PROG_EVENT_GNUM1_OFFSET); 3605 3606 mrpcim_stats->xgmac_global_prog_event_gnum1 = 3607 VXGE_HAL_STATS_GET_GLOBAL_PROG_EVENT_GNUM1(val64); 3608 3609 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3610 hldev->header.regh0, 3611 &hldev->mrpcim_reg->orp_lro_events); 3612 3613 mrpcim_stats->xgmac_orp_lro_events = 3614 VXGE_HAL_ORP_LRO_EVENTS_GET_ORP_LRO_EVENTS(val64); 3615 3616 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3617 hldev->header.regh0, 3618 &hldev->mrpcim_reg->orp_bs_events); 3619 3620 mrpcim_stats->xgmac_orp_bs_events = 3621 VXGE_HAL_ORP_BS_EVENTS_GET_ORP_BS_EVENTS(val64); 3622 3623 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3624 hldev->header.regh0, 3625 &hldev->mrpcim_reg->orp_iwarp_events); 3626 3627 mrpcim_stats->xgmac_orp_iwarp_events = 3628 VXGE_HAL_ORP_IWARP_EVENTS_GET_ORP_IWARP_EVENTS(val64); 3629 3630 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3631 hldev->header.regh0, 3632 &hldev->mrpcim_reg->dbg_stats_tpa_tx_path); 3633 3634 mrpcim_stats->xgmac_tx_permitted_frms = 3635 (u32) VXGE_HAL_DBG_STATS_TPA_TX_PATH_GET_TX_PERMITTED_FRMS(val64); 3636 3637 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3638 hldev->header.regh0, 3639 &hldev->mrpcim_reg->dbg_stat_tx_any_frms); 3640 3641 mrpcim_stats->xgmac_port0_tx_any_frms = 3642 (u8) VXGE_HAL_DBG_STAT_TX_ANY_FRMS_GET_PORT0_TX_ANY_FRMS(val64); 3643 3644 mrpcim_stats->xgmac_port1_tx_any_frms = 3645 (u8) VXGE_HAL_DBG_STAT_TX_ANY_FRMS_GET_PORT1_TX_ANY_FRMS(val64); 3646 3647 mrpcim_stats->xgmac_port2_tx_any_frms = 3648 (u8) VXGE_HAL_DBG_STAT_TX_ANY_FRMS_GET_PORT2_TX_ANY_FRMS(val64); 3649 3650 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3651 hldev->header.regh0, 3652 &hldev->mrpcim_reg->dbg_stat_rx_any_frms); 3653 3654 mrpcim_stats->xgmac_port0_rx_any_frms = 3655 (u8) VXGE_HAL_DBG_STAT_RX_ANY_FRMS_GET_PORT0_RX_ANY_FRMS(val64); 3656 3657 mrpcim_stats->xgmac_port1_rx_any_frms = 3658 (u8) VXGE_HAL_DBG_STAT_RX_ANY_FRMS_GET_PORT1_RX_ANY_FRMS(val64); 3659 3660 mrpcim_stats->xgmac_port2_rx_any_frms = 3661 (u8) VXGE_HAL_DBG_STAT_RX_ANY_FRMS_GET_PORT2_RX_ANY_FRMS(val64); 3662 3663 vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 3664 __FILE__, __func__, __LINE__, status); 3665 return (status); 3666} 3667 3668/* 3669 * vxge_hal_mrpcim_stats_clear - Clear the statistics of the device 3670 * @devh: HAL Device handle. 3671 * 3672 * Clear the statistics of the given Device. 3673 * 3674 */ 3675vxge_hal_status_e 3676vxge_hal_mrpcim_stats_clear(vxge_hal_device_h devh) 3677{ 3678 u32 i; 3679 u64 stat; 3680 vxge_hal_status_e status; 3681 __hal_device_t *hldev = (__hal_device_t *) devh; 3682 3683 vxge_assert(hldev != NULL); 3684 3685 vxge_hal_trace_log_stats("==> %s:%s:%d", 3686 __FILE__, __func__, __LINE__); 3687 3688 vxge_hal_trace_log_stats("devh = 0x"VXGE_OS_STXFMT, 3689 (ptr_t) devh); 3690 3691 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 3692 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 3693 __FILE__, __func__, __LINE__, 3694 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 3695 3696 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 3697 } 3698 3699 vxge_os_memcpy(&hldev->mrpcim->mrpcim_stats_sav, 3700 hldev->mrpcim->mrpcim_stats, 3701 sizeof(vxge_hal_mrpcim_stats_hw_info_t)); 3702 3703 vxge_os_memzero(hldev->mrpcim->mrpcim_stats, 3704 sizeof(vxge_hal_mrpcim_stats_hw_info_t)); 3705 3706 vxge_os_memzero(&hldev->stats.sw_dev_err_stats, 3707 sizeof(vxge_hal_device_stats_sw_err_t)); 3708 3709 hldev->stats.sw_dev_info_stats.soft_reset_cnt = 0; 3710 3711 for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) { 3712 3713 if (!(hldev->vpaths_deployed & mBIT(i))) 3714 continue; 3715 3716 (void) vxge_hal_vpath_stats_clear( 3717 VXGE_HAL_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i])); 3718 3719 } 3720 3721 status = vxge_hal_mrpcim_stats_access( 3722 devh, 3723 VXGE_HAL_STATS_OP_CLEAR_ALL_STATS, 3724 0, 3725 0, 3726 &stat); 3727 3728 vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 3729 __FILE__, __func__, __LINE__, status); 3730 3731 return (status); 3732} 3733 3734/* 3735 * vxge_hal_mrpcim_udp_rth_enable - Enable UDP/RTH. 3736 * @devh: HAL device handle. 3737 * 3738 * enable udp rth 3739 * 3740 */ 3741vxge_hal_status_e 3742vxge_hal_mrpcim_udp_rth_enable( 3743 vxge_hal_device_h devh) 3744{ 3745 vxge_hal_status_e status = VXGE_HAL_OK; 3746 __hal_device_t *hldev = (__hal_device_t *) devh; 3747 3748 vxge_assert(devh != NULL); 3749 3750 vxge_hal_trace_log_stats("==> %s:%s:%d", 3751 __FILE__, __func__, __LINE__); 3752 3753 vxge_hal_trace_log_stats("devh = 0x"VXGE_OS_STXFMT, 3754 (ptr_t) devh); 3755 3756 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 3757 3758 vxge_hal_trace_log_stats("<== %s:%s:%d Result: %d", 3759 __FILE__, __func__, __LINE__, 3760 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 3761 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 3762 3763 } 3764 3765 status = __hal_vpath_udp_rth_set(hldev, 3766 hldev->first_vp_id, 3767 TRUE); 3768 3769 vxge_hal_trace_log_stats("<== %s:%s:%d Result = %d", 3770 __FILE__, __func__, __LINE__, status); 3771 return (status); 3772} 3773 3774/* 3775 * __hal_mrpcim_mac_configure - Initialize mac 3776 * @hldev: hal device. 3777 * 3778 * Initializes mac 3779 * 3780 */ 3781vxge_hal_status_e 3782__hal_mrpcim_mac_configure(__hal_device_t *hldev) 3783{ 3784 u64 val64; 3785 u32 i, port_id; 3786 vxge_hal_status_e status = VXGE_HAL_OK; 3787 vxge_hal_mac_config_t *mac_config = 3788 &hldev->header.config.mrpcim_config.mac_config; 3789 3790 vxge_assert(hldev != NULL); 3791 3792 vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 3793 __FILE__, __func__, __LINE__); 3794 3795 vxge_hal_trace_log_mrpcim("hldev = 0x"VXGE_OS_STXFMT, 3796 (ptr_t) hldev); 3797 3798 for (i = 0; i < VXGE_HAL_MAC_MAX_WIRE_PORTS; i++) { 3799 3800 port_id = mac_config->wire_port_config[i].port_id; 3801 3802 if (mac_config->wire_port_config[i].tmac_en == 3803 VXGE_HAL_WIRE_PORT_TMAC_DEFAULT) { 3804 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3805 hldev->header.regh0, 3806 &hldev->mrpcim_reg->txmac_cfg0_port[port_id]); 3807 3808 if (val64 & VXGE_HAL_TXMAC_CFG0_PORT_TMAC_EN) { 3809 mac_config->wire_port_config[i].tmac_en = 3810 VXGE_HAL_WIRE_PORT_TMAC_ENABLE; 3811 } else { 3812 mac_config->wire_port_config[i].tmac_en = 3813 VXGE_HAL_WIRE_PORT_TMAC_DISABLE; 3814 } 3815 3816 } 3817 3818 if (mac_config->wire_port_config[i].rmac_en == 3819 VXGE_HAL_WIRE_PORT_RMAC_DEFAULT) { 3820 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3821 hldev->header.regh0, 3822 &hldev->mrpcim_reg->rxmac_cfg0_port[port_id]); 3823 3824 if (val64 & VXGE_HAL_RXMAC_CFG0_PORT_RMAC_EN) { 3825 mac_config->wire_port_config[i].rmac_en = 3826 VXGE_HAL_WIRE_PORT_RMAC_ENABLE; 3827 } else { 3828 mac_config->wire_port_config[i].rmac_en = 3829 VXGE_HAL_WIRE_PORT_RMAC_DISABLE; 3830 } 3831 3832 } 3833 3834 if ((!(mac_config->wire_port_config[i].rmac_en)) && 3835 (!(mac_config->wire_port_config[i].tmac_en))) 3836 val64 = 0; 3837 else 3838 val64 = VXGE_HAL_XGMAC_MAIN_CFG_PORT_PORT_EN; 3839 3840 vxge_os_pio_mem_write64(hldev->header.pdev, 3841 hldev->header.regh0, 3842 val64, 3843 &hldev->mrpcim_reg->xgmac_main_cfg_port[port_id]); 3844 3845 if (!val64) 3846 continue; 3847 3848 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3849 hldev->header.regh0, 3850 &hldev->mrpcim_reg->rxmac_cfg0_port[port_id]); 3851 3852 if (mac_config->wire_port_config[i].rmac_en) 3853 val64 |= VXGE_HAL_RXMAC_CFG0_PORT_RMAC_EN; 3854 else 3855 val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_RMAC_EN; 3856 3857 if (mac_config->wire_port_config[i].rmac_strip_fcs != 3858 VXGE_HAL_WIRE_PORT_RMAC_STRIP_FCS_DEFAULT) { 3859 if (mac_config->wire_port_config[i].rmac_strip_fcs) 3860 val64 |= VXGE_HAL_RXMAC_CFG0_PORT_STRIP_FCS; 3861 else 3862 val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_STRIP_FCS; 3863 } 3864 3865 if (mac_config->wire_port_config[i].rmac_discard_pfrm != 3866 VXGE_HAL_WIRE_PORT_RMAC_DISCARD_PFRM_DEFAULT) { 3867 if (mac_config->wire_port_config[i].rmac_discard_pfrm) 3868 val64 |= VXGE_HAL_RXMAC_CFG0_PORT_DISCARD_PFRM; 3869 else 3870 val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_DISCARD_PFRM; 3871 } 3872 3873 if (mac_config->wire_port_config[i].mtu != 3874 VXGE_HAL_WIRE_PORT_DEF_INITIAL_MTU) { 3875 3876 val64 &= 3877 ~VXGE_HAL_RXMAC_CFG0_PORT_MAX_PYLD_LEN(0x3fff); 3878 3879 val64 |= VXGE_HAL_RXMAC_CFG0_PORT_MAX_PYLD_LEN( 3880 mac_config->wire_port_config[i].mtu); 3881 3882 } 3883 3884 vxge_os_pio_mem_write64(hldev->header.pdev, 3885 hldev->header.regh0, 3886 val64, 3887 &hldev->mrpcim_reg->rxmac_cfg0_port[port_id]); 3888 3889 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3890 hldev->header.regh0, 3891 &hldev->mrpcim_reg->rxmac_cfg2_port[port_id]); 3892 3893 if (mac_config->wire_port_config[i].rmac_prom_en != 3894 VXGE_HAL_WIRE_PORT_RMAC_PROM_EN_DEFAULT) { 3895 if (mac_config->wire_port_config[i].rmac_prom_en) 3896 val64 |= VXGE_HAL_RXMAC_CFG2_PORT_PROM_EN; 3897 else 3898 val64 &= ~VXGE_HAL_RXMAC_CFG2_PORT_PROM_EN; 3899 } 3900 3901 vxge_os_pio_mem_write64(hldev->header.pdev, 3902 hldev->header.regh0, 3903 val64, 3904 &hldev->mrpcim_reg->rxmac_cfg2_port[port_id]); 3905 3906 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3907 hldev->header.regh0, 3908 &hldev->mrpcim_reg->rxmac_pause_cfg_port[port_id]); 3909 3910 if (mac_config->wire_port_config[i].rmac_pause_gen_en != 3911 VXGE_HAL_WIRE_PORT_RMAC_PAUSE_GEN_EN_DEFAULT) { 3912 if (mac_config->wire_port_config[i].rmac_pause_gen_en) 3913 val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN; 3914 else 3915 val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN; 3916 3917 } 3918 3919 if (mac_config->wire_port_config[i].rmac_pause_rcv_en != 3920 VXGE_HAL_WIRE_PORT_RMAC_PAUSE_RCV_EN_DEFAULT) { 3921 if (mac_config->wire_port_config[i].rmac_pause_rcv_en) 3922 val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN; 3923 else 3924 val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN; 3925 3926 } 3927 3928 if (mac_config->wire_port_config[i].rmac_pause_time != 3929 VXGE_HAL_WIRE_PORT_DEF_RMAC_HIGH_PTIME) { 3930 val64 &= 3931 ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_HIGH_PTIME(0xffff); 3932 3933 val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_HIGH_PTIME( 3934 mac_config->wire_port_config[i].rmac_pause_time); 3935 3936 } 3937 3938 if (mac_config->wire_port_config[i].rmac_pause_time != 3939 VXGE_HAL_WIRE_PORT_RMAC_PAUSE_LIMITER_DEFAULT) { 3940 if (mac_config->wire_port_config[i].limiter_en) 3941 val64 |= 3942 VXGE_HAL_RXMAC_PAUSE_CFG_PORT_LIMITER_EN; 3943 else 3944 val64 &= 3945 ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_LIMITER_EN; 3946 3947 } 3948 3949 if (mac_config->wire_port_config[i].max_limit != 3950 VXGE_HAL_WIRE_PORT_DEF_RMAC_MAX_LIMIT) { 3951 val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT(0xff); 3952 3953 val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT( 3954 mac_config->wire_port_config[i].max_limit); 3955 3956 } 3957 3958 vxge_os_pio_mem_write64(hldev->header.pdev, 3959 hldev->header.regh0, 3960 val64, 3961 &hldev->mrpcim_reg->rxmac_pause_cfg_port[port_id]); 3962 3963 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3964 hldev->header.regh0, 3965 &hldev->mrpcim_reg->rxmac_link_util_port[port_id]); 3966 3967 if (mac_config->wire_port_config[i].rmac_util_period != 3968 VXGE_HAL_WIRE_PORT_DEF_TMAC_UTIL_PERIOD) { 3969 val64 &= 3970 ~VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_UTIL_CFG(0xf); 3971 3972 val64 |= VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_UTIL_CFG( 3973 mac_config->wire_port_config[i].rmac_util_period); 3974 } 3975 3976 vxge_os_pio_mem_write64(hldev->header.pdev, 3977 hldev->header.regh0, 3978 val64, 3979 &hldev->mrpcim_reg->rxmac_link_util_port[port_id]); 3980 3981 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 3982 hldev->header.regh0, 3983 &hldev->mrpcim_reg->xgmac_debounce_port[port_id]); 3984 3985 if (mac_config->wire_port_config[i].link_stability_period != 3986 VXGE_HAL_WIRE_PORT_DEF_LINK_STABILITY_PERIOD) { 3987 val64 &= 3988 ~(VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_LINK_UP(0xf) | 3989 VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_LINK_DOWN(0xf)); 3990 3991 val64 |= VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_LINK_UP( 3992 mac_config->wire_port_config[i].link_stability_period) | 3993 VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_LINK_DOWN( 3994 mac_config->wire_port_config[i].link_stability_period); 3995 } 3996 3997 if (mac_config->wire_port_config[i].port_stability_period != 3998 VXGE_HAL_WIRE_PORT_DEF_PORT_STABILITY_PERIOD) { 3999 val64 &= 4000 ~(VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_PORT_UP(0xf) | 4001 VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_PORT_DOWN(0xf)); 4002 4003 val64 |= VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_PORT_UP( 4004 mac_config->wire_port_config[i].port_stability_period) | 4005 VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_PORT_DOWN( 4006 mac_config->wire_port_config[i].port_stability_period); 4007 } 4008 4009 vxge_os_pio_mem_write64(hldev->header.pdev, 4010 hldev->header.regh0, 4011 val64, 4012 &hldev->mrpcim_reg->xgmac_debounce_port[port_id]); 4013 4014 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4015 hldev->header.regh0, 4016 &hldev->mrpcim_reg->txmac_cfg0_port[port_id]); 4017 4018 if (mac_config->wire_port_config[i].tmac_en) 4019 val64 |= VXGE_HAL_TXMAC_CFG0_PORT_TMAC_EN; 4020 else 4021 val64 &= ~VXGE_HAL_TXMAC_CFG0_PORT_TMAC_EN; 4022 4023 if (mac_config->wire_port_config[i].tmac_pad != 4024 VXGE_HAL_WIRE_PORT_TMAC_PAD_DEFAULT) { 4025 if (mac_config->wire_port_config[i].tmac_pad) 4026 val64 |= VXGE_HAL_TXMAC_CFG0_PORT_APPEND_PAD; 4027 else 4028 val64 &= ~VXGE_HAL_TXMAC_CFG0_PORT_APPEND_PAD; 4029 } 4030 4031 if (mac_config->wire_port_config[i].tmac_pad_byte != 4032 VXGE_HAL_WIRE_PORT_TMAC_PAD_DEFAULT) { 4033 val64 &= ~VXGE_HAL_TXMAC_CFG0_PORT_PAD_BYTE(0xff); 4034 4035 val64 |= VXGE_HAL_TXMAC_CFG0_PORT_PAD_BYTE( 4036 mac_config->wire_port_config[i].tmac_pad_byte); 4037 } 4038 4039 vxge_os_pio_mem_write64(hldev->header.pdev, 4040 hldev->header.regh0, 4041 val64, 4042 &hldev->mrpcim_reg->txmac_cfg0_port[port_id]); 4043 4044 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4045 hldev->header.regh0, 4046 &hldev->mrpcim_reg->txmac_link_util_port); 4047 4048 if (mac_config->wire_port_config[i].tmac_util_period != 4049 VXGE_HAL_WIRE_PORT_DEF_TMAC_UTIL_PERIOD) { 4050 val64 &= 4051 ~VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_UTIL_CFG(0xf); 4052 4053 val64 |= VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_UTIL_CFG( 4054 mac_config->wire_port_config[i].tmac_util_period); 4055 } 4056 4057 vxge_os_pio_mem_write64(hldev->header.pdev, 4058 hldev->header.regh0, 4059 val64, 4060 &hldev->mrpcim_reg->txmac_link_util_port[port_id]); 4061 4062 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4063 hldev->header.regh0, 4064 &hldev->mrpcim_reg->ratemgmt_cfg_port); 4065 4066 if (mac_config->wire_port_config[i].autoneg_mode != 4067 VXGE_HAL_WIRE_PORT_AUTONEG_MODE_DEFAULT) { 4068 4069 val64 &= ~VXGE_HAL_RATEMGMT_CFG_PORT_MODE(0x3); 4070 4071 val64 |= VXGE_HAL_RATEMGMT_CFG_PORT_MODE( 4072 mac_config->wire_port_config[i].autoneg_mode); 4073 } 4074 4075 if (mac_config->wire_port_config[i].autoneg_rate != 4076 VXGE_HAL_WIRE_PORT_AUTONEG_RATE_DEFAULT) { 4077 4078 if (mac_config->wire_port_config[i].autoneg_rate) 4079 val64 |= VXGE_HAL_RATEMGMT_CFG_PORT_RATE; 4080 else 4081 val64 &= ~VXGE_HAL_RATEMGMT_CFG_PORT_RATE; 4082 4083 } 4084 4085 if (mac_config->wire_port_config[i].fixed_use_fsm != 4086 VXGE_HAL_WIRE_PORT_FIXED_USE_FSM_DEFAULT) { 4087 4088 if (mac_config->wire_port_config[i].fixed_use_fsm) 4089 val64 |= 4090 VXGE_HAL_RATEMGMT_CFG_PORT_FIXED_USE_FSM; 4091 else 4092 val64 &= 4093 ~VXGE_HAL_RATEMGMT_CFG_PORT_FIXED_USE_FSM; 4094 4095 } 4096 4097 if (mac_config->wire_port_config[i].antp_use_fsm != 4098 VXGE_HAL_WIRE_PORT_ANTP_USE_FSM_DEFAULT) { 4099 4100 if (mac_config->wire_port_config[i].antp_use_fsm) 4101 val64 |= 4102 VXGE_HAL_RATEMGMT_CFG_PORT_ANTP_USE_FSM; 4103 else 4104 val64 &= 4105 ~VXGE_HAL_RATEMGMT_CFG_PORT_ANTP_USE_FSM; 4106 4107 } 4108 4109 if (mac_config->wire_port_config[i].anbe_use_fsm != 4110 VXGE_HAL_WIRE_PORT_ANBE_USE_FSM_DEFAULT) { 4111 4112 if (mac_config->wire_port_config[i].anbe_use_fsm) 4113 val64 |= 4114 VXGE_HAL_RATEMGMT_CFG_PORT_ANBE_USE_FSM; 4115 else 4116 val64 &= 4117 ~VXGE_HAL_RATEMGMT_CFG_PORT_ANBE_USE_FSM; 4118 4119 } 4120 4121 vxge_os_pio_mem_write64(hldev->header.pdev, 4122 hldev->header.regh0, 4123 val64, 4124 &hldev->mrpcim_reg->ratemgmt_cfg_port[port_id]); 4125 4126 } 4127 4128 if (mac_config->switch_port_config.tmac_en == 4129 VXGE_HAL_SWITCH_PORT_TMAC_DEFAULT) { 4130 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4131 hldev->header.regh0, 4132 &hldev->mrpcim_reg->txmac_cfg0_port[ 4133 VXGE_HAL_MAC_SWITCH_PORT]); 4134 4135 if (val64 & VXGE_HAL_TXMAC_CFG0_PORT_TMAC_EN) { 4136 mac_config->switch_port_config.tmac_en = 4137 VXGE_HAL_SWITCH_PORT_TMAC_ENABLE; 4138 } else { 4139 mac_config->switch_port_config.tmac_en = 4140 VXGE_HAL_SWITCH_PORT_TMAC_DISABLE; 4141 } 4142 4143 } 4144 4145 if (mac_config->switch_port_config.rmac_en == 4146 VXGE_HAL_SWITCH_PORT_RMAC_DEFAULT) { 4147 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4148 hldev->header.regh0, 4149 &hldev->mrpcim_reg->rxmac_cfg0_port[ 4150 VXGE_HAL_MAC_SWITCH_PORT]); 4151 4152 if (val64 & VXGE_HAL_RXMAC_CFG0_PORT_RMAC_EN) { 4153 mac_config->switch_port_config.rmac_en = 4154 VXGE_HAL_SWITCH_PORT_RMAC_ENABLE; 4155 } else { 4156 mac_config->switch_port_config.rmac_en = 4157 VXGE_HAL_SWITCH_PORT_RMAC_DISABLE; 4158 } 4159 4160 } 4161 4162 if (mac_config->switch_port_config.rmac_en || 4163 mac_config->switch_port_config.tmac_en) { 4164 4165 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4166 hldev->header.regh0, 4167 &hldev->mrpcim_reg->rxmac_cfg0_port[ 4168 VXGE_HAL_MAC_SWITCH_PORT]); 4169 4170 if (mac_config->switch_port_config.rmac_en) 4171 val64 |= VXGE_HAL_RXMAC_CFG0_PORT_RMAC_EN; 4172 else 4173 val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_RMAC_EN; 4174 4175 if (mac_config->switch_port_config.rmac_strip_fcs != 4176 VXGE_HAL_SWITCH_PORT_RMAC_STRIP_FCS_DEFAULT) { 4177 if (mac_config->switch_port_config.rmac_strip_fcs) 4178 val64 |= VXGE_HAL_RXMAC_CFG0_PORT_STRIP_FCS; 4179 else 4180 val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_STRIP_FCS; 4181 } 4182 4183 if (mac_config->switch_port_config.rmac_discard_pfrm != 4184 VXGE_HAL_SWITCH_PORT_RMAC_DISCARD_PFRM_DEFAULT) { 4185 if (mac_config->switch_port_config.rmac_discard_pfrm) 4186 val64 |= VXGE_HAL_RXMAC_CFG0_PORT_DISCARD_PFRM; 4187 else 4188 val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_DISCARD_PFRM; 4189 } 4190 4191 if (mac_config->switch_port_config.mtu != 4192 VXGE_HAL_SWITCH_PORT_DEF_INITIAL_MTU) { 4193 4194 val64 &= ~VXGE_HAL_RXMAC_CFG0_PORT_MAX_PYLD_LEN(0x3fff); 4195 4196 val64 |= VXGE_HAL_RXMAC_CFG0_PORT_MAX_PYLD_LEN( 4197 mac_config->switch_port_config.mtu); 4198 4199 } 4200 4201 vxge_os_pio_mem_write64(hldev->header.pdev, 4202 hldev->header.regh0, 4203 val64, 4204 &hldev->mrpcim_reg->rxmac_cfg0_port[ 4205 VXGE_HAL_MAC_SWITCH_PORT]); 4206 4207 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4208 hldev->header.regh0, 4209 &hldev->mrpcim_reg->rxmac_cfg2_port[ 4210 VXGE_HAL_MAC_SWITCH_PORT]); 4211 4212 if (mac_config->switch_port_config.rmac_prom_en != 4213 VXGE_HAL_SWITCH_PORT_RMAC_PROM_EN_DEFAULT) { 4214 if (mac_config->switch_port_config.rmac_prom_en) 4215 val64 |= VXGE_HAL_RXMAC_CFG2_PORT_PROM_EN; 4216 else 4217 val64 &= ~VXGE_HAL_RXMAC_CFG2_PORT_PROM_EN; 4218 } 4219 4220 vxge_os_pio_mem_write64(hldev->header.pdev, 4221 hldev->header.regh0, 4222 val64, 4223 &hldev->mrpcim_reg->rxmac_cfg2_port[ 4224 VXGE_HAL_MAC_SWITCH_PORT]); 4225 4226 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4227 hldev->header.regh0, 4228 &hldev->mrpcim_reg->rxmac_pause_cfg_port[ 4229 VXGE_HAL_MAC_SWITCH_PORT]); 4230 4231 if (mac_config->switch_port_config.rmac_pause_gen_en != 4232 VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_GEN_EN_DEFAULT) { 4233 if (mac_config->switch_port_config.rmac_pause_gen_en) 4234 val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN; 4235 else 4236 val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN; 4237 4238 } 4239 4240 if (mac_config->switch_port_config.rmac_pause_rcv_en != 4241 VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_RCV_EN_DEFAULT) { 4242 if (mac_config->switch_port_config.rmac_pause_rcv_en) 4243 val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN; 4244 else 4245 val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN; 4246 4247 } 4248 4249 if (mac_config->switch_port_config.rmac_pause_time != 4250 VXGE_HAL_SWITCH_PORT_DEF_RMAC_HIGH_PTIME) { 4251 val64 &= 4252 ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_HIGH_PTIME(0xffff); 4253 4254 val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_HIGH_PTIME( 4255 mac_config->switch_port_config.rmac_pause_time); 4256 4257 } 4258 4259 if (mac_config->switch_port_config.rmac_pause_time != 4260 VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_LIMITER_DEFAULT) { 4261 if (mac_config->switch_port_config.limiter_en) 4262 val64 |= 4263 VXGE_HAL_RXMAC_PAUSE_CFG_PORT_LIMITER_EN; 4264 else 4265 val64 &= 4266 ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_LIMITER_EN; 4267 4268 } 4269 4270 if (mac_config->switch_port_config.max_limit != 4271 VXGE_HAL_SWITCH_PORT_DEF_RMAC_MAX_LIMIT) { 4272 val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT(0xff); 4273 4274 val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT( 4275 mac_config->switch_port_config.max_limit); 4276 4277 } 4278 4279 vxge_os_pio_mem_write64(hldev->header.pdev, 4280 hldev->header.regh0, 4281 val64, 4282 &hldev->mrpcim_reg->rxmac_pause_cfg_port[ 4283 VXGE_HAL_MAC_SWITCH_PORT]); 4284 4285 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4286 hldev->header.regh0, 4287 &hldev->mrpcim_reg->rxmac_link_util_port[ 4288 VXGE_HAL_MAC_SWITCH_PORT]); 4289 4290 if (mac_config->switch_port_config.rmac_util_period != 4291 VXGE_HAL_SWITCH_PORT_DEF_TMAC_UTIL_PERIOD) { 4292 val64 &= 4293 ~VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_UTIL_CFG(0xf); 4294 4295 val64 |= VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_UTIL_CFG( 4296 mac_config->switch_port_config.rmac_util_period); 4297 } 4298 4299 vxge_os_pio_mem_write64(hldev->header.pdev, 4300 hldev->header.regh0, 4301 val64, 4302 &hldev->mrpcim_reg->rxmac_link_util_port[ 4303 VXGE_HAL_MAC_SWITCH_PORT]); 4304 4305 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4306 hldev->header.regh0, 4307 &hldev->mrpcim_reg->txmac_cfg0_port[ 4308 VXGE_HAL_MAC_SWITCH_PORT]); 4309 4310 if (mac_config->switch_port_config.tmac_en) 4311 val64 |= VXGE_HAL_TXMAC_CFG0_PORT_TMAC_EN; 4312 else 4313 val64 &= ~VXGE_HAL_TXMAC_CFG0_PORT_TMAC_EN; 4314 4315 if (mac_config->switch_port_config.tmac_pad != 4316 VXGE_HAL_SWITCH_PORT_TMAC_PAD_DEFAULT) { 4317 if (mac_config->switch_port_config.tmac_pad) 4318 val64 |= VXGE_HAL_TXMAC_CFG0_PORT_APPEND_PAD; 4319 else 4320 val64 &= ~VXGE_HAL_TXMAC_CFG0_PORT_APPEND_PAD; 4321 } 4322 4323 if (mac_config->switch_port_config.tmac_pad_byte != 4324 VXGE_HAL_SWITCH_PORT_TMAC_PAD_DEFAULT) { 4325 val64 &= ~VXGE_HAL_TXMAC_CFG0_PORT_PAD_BYTE(0xff); 4326 4327 val64 |= VXGE_HAL_TXMAC_CFG0_PORT_PAD_BYTE( 4328 mac_config->switch_port_config.tmac_pad_byte); 4329 } 4330 4331 vxge_os_pio_mem_write64(hldev->header.pdev, 4332 hldev->header.regh0, 4333 val64, 4334 &hldev->mrpcim_reg->txmac_cfg0_port[ 4335 VXGE_HAL_MAC_SWITCH_PORT]); 4336 4337 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4338 hldev->header.regh0, 4339 &hldev->mrpcim_reg->txmac_link_util_port); 4340 4341 if (mac_config->switch_port_config.tmac_util_period != 4342 VXGE_HAL_SWITCH_PORT_DEF_TMAC_UTIL_PERIOD) { 4343 val64 &= 4344 ~VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_UTIL_CFG(0xf); 4345 4346 val64 |= VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_UTIL_CFG( 4347 mac_config->switch_port_config.tmac_util_period); 4348 } 4349 4350 vxge_os_pio_mem_write64(hldev->header.pdev, 4351 hldev->header.regh0, 4352 val64, 4353 &hldev->mrpcim_reg->txmac_link_util_port[ 4354 VXGE_HAL_MAC_SWITCH_PORT]); 4355 4356 } 4357 4358 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4359 hldev->header.regh0, 4360 &hldev->mrpcim_reg->txmac_gen_cfg1); 4361 4362 if (mac_config->tmac_perma_stop_en != 4363 VXGE_HAL_MAC_TMAC_PERMA_STOP_DEFAULT) { 4364 4365 if (mac_config->tmac_perma_stop_en) 4366 val64 |= VXGE_HAL_TXMAC_GEN_CFG1_TMAC_PERMA_STOP_EN; 4367 else 4368 val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_TMAC_PERMA_STOP_EN; 4369 4370 } 4371 4372 if (mac_config->tmac_tx_switch_dis != 4373 VXGE_HAL_MAC_TMAC_TX_SWITCH_DEFAULT) { 4374 4375 if (mac_config->tmac_tx_switch_dis) 4376 val64 |= VXGE_HAL_TXMAC_GEN_CFG1_TX_SWITCH_DISABLE; 4377 else 4378 val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_TX_SWITCH_DISABLE; 4379 4380 } 4381 4382 if (mac_config->tmac_lossy_switch_en != 4383 VXGE_HAL_MAC_TMAC_LOSSY_SWITCH_DEFAULT) { 4384 4385 if (mac_config->tmac_lossy_switch_en) 4386 val64 |= VXGE_HAL_TXMAC_GEN_CFG1_LOSSY_SWITCH; 4387 else 4388 val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_LOSSY_SWITCH; 4389 4390 } 4391 4392 if (mac_config->tmac_lossy_switch_en != 4393 VXGE_HAL_MAC_TMAC_LOSSY_WIRE_DEFAULT) { 4394 4395 if (mac_config->tmac_lossy_wire_en) 4396 val64 |= VXGE_HAL_TXMAC_GEN_CFG1_LOSSY_WIRE; 4397 else 4398 val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_LOSSY_WIRE; 4399 4400 } 4401 4402 if (mac_config->tmac_bcast_to_wire_dis != 4403 VXGE_HAL_MAC_TMAC_BCAST_TO_WIRE_DEFAULT) { 4404 4405 if (mac_config->tmac_bcast_to_wire_dis) 4406 val64 |= VXGE_HAL_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_WIRE; 4407 else 4408 val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_WIRE; 4409 4410 } 4411 4412 if (mac_config->tmac_bcast_to_wire_dis != 4413 VXGE_HAL_MAC_TMAC_BCAST_TO_SWITCH_DEFAULT) { 4414 4415 if (mac_config->tmac_bcast_to_switch_dis) 4416 val64 |= VXGE_HAL_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_SWITCH; 4417 else 4418 val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_SWITCH; 4419 4420 } 4421 4422 if (mac_config->tmac_host_append_fcs_en != 4423 VXGE_HAL_MAC_TMAC_HOST_APPEND_FCS_DEFAULT) { 4424 4425 if (mac_config->tmac_host_append_fcs_en) 4426 val64 |= VXGE_HAL_TXMAC_GEN_CFG1_HOST_APPEND_FCS; 4427 else 4428 val64 &= ~VXGE_HAL_TXMAC_GEN_CFG1_HOST_APPEND_FCS; 4429 4430 } 4431 4432 vxge_os_pio_mem_write64(hldev->header.pdev, 4433 hldev->header.regh0, 4434 val64, 4435 &hldev->mrpcim_reg->txmac_gen_cfg1); 4436 4437 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4438 hldev->header.regh0, 4439 &hldev->mrpcim_reg->rxmac_rx_pa_cfg0); 4440 4441 if (mac_config->rpa_ignore_frame_err != 4442 VXGE_HAL_MAC_RPA_IGNORE_FRAME_ERR_DEFAULT) { 4443 4444 if (mac_config->rpa_ignore_frame_err) 4445 val64 |= VXGE_HAL_RXMAC_RX_PA_CFG0_IGNORE_FRAME_ERR; 4446 else 4447 val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG0_IGNORE_FRAME_ERR; 4448 4449 } 4450 4451 if (mac_config->rpa_support_snap_ab_n != 4452 VXGE_HAL_MAC_RPA_SUPPORT_SNAP_AB_N_DEFAULT) { 4453 4454 if (mac_config->rpa_support_snap_ab_n) 4455 val64 |= VXGE_HAL_RXMAC_RX_PA_CFG0_SUPPORT_SNAP_AB_N; 4456 else 4457 val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG0_SUPPORT_SNAP_AB_N; 4458 4459 } 4460 4461 if (mac_config->rpa_search_for_hao != 4462 VXGE_HAL_MAC_RPA_SEARCH_FOR_HAO_DEFAULT) { 4463 4464 if (mac_config->rpa_search_for_hao) 4465 val64 |= VXGE_HAL_RXMAC_RX_PA_CFG0_SEARCH_FOR_HAO; 4466 else 4467 val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG0_SEARCH_FOR_HAO; 4468 4469 } 4470 4471 if (mac_config->rpa_support_ipv6_mobile_hdrs != 4472 VXGE_HAL_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS_DEFAULT) { 4473 4474 if (mac_config->rpa_support_ipv6_mobile_hdrs) 4475 val64 |= 4476 VXGE_HAL_RXMAC_RX_PA_CFG0_SUPPORT_MOBILE_IPV6_HDRS; 4477 else 4478 val64 &= 4479 ~VXGE_HAL_RXMAC_RX_PA_CFG0_SUPPORT_MOBILE_IPV6_HDRS; 4480 4481 } 4482 4483 if (mac_config->rpa_ipv6_stop_searching != 4484 VXGE_HAL_MAC_RPA_IPV6_STOP_SEARCHING_DEFAULT) { 4485 4486 if (mac_config->rpa_ipv6_stop_searching) 4487 val64 |= VXGE_HAL_RXMAC_RX_PA_CFG0_IPV6_STOP_SEARCHING; 4488 else 4489 val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG0_IPV6_STOP_SEARCHING; 4490 4491 } 4492 4493 if (mac_config->rpa_no_ps_if_unknown != 4494 VXGE_HAL_MAC_RPA_NO_PS_IF_UNKNOWN_DEFAULT) { 4495 4496 if (mac_config->rpa_no_ps_if_unknown) 4497 val64 |= VXGE_HAL_RXMAC_RX_PA_CFG0_NO_PS_IF_UNKNOWN; 4498 else 4499 val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG0_NO_PS_IF_UNKNOWN; 4500 4501 } 4502 4503 if (mac_config->rpa_search_for_etype != 4504 VXGE_HAL_MAC_RPA_SEARCH_FOR_ETYPE_DEFAULT) { 4505 4506 if (mac_config->rpa_search_for_etype) 4507 val64 |= VXGE_HAL_RXMAC_RX_PA_CFG0_SEARCH_FOR_ETYPE; 4508 else 4509 val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG0_SEARCH_FOR_ETYPE; 4510 4511 } 4512 4513 vxge_os_pio_mem_write64(hldev->header.pdev, 4514 hldev->header.regh0, 4515 val64, 4516 &hldev->mrpcim_reg->rxmac_rx_pa_cfg0); 4517 4518 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4519 hldev->header.regh0, 4520 &hldev->mrpcim_reg->fau_pa_cfg); 4521 4522 if (mac_config->rpa_repl_l4_comp_csum != 4523 VXGE_HAL_MAC_RPA_REPL_l4_COMP_CSUM_DEFAULT) { 4524 4525 if (mac_config->rpa_repl_l4_comp_csum) 4526 val64 |= VXGE_HAL_FAU_PA_CFG_REPL_L4_COMP_CSUM; 4527 else 4528 val64 &= ~VXGE_HAL_FAU_PA_CFG_REPL_L4_COMP_CSUM; 4529 4530 } 4531 4532 if (mac_config->rpa_repl_l3_incl_cf != 4533 VXGE_HAL_MAC_RPA_REPL_L3_INCL_CF_DEFAULT) { 4534 4535 if (mac_config->rpa_repl_l3_incl_cf) 4536 val64 |= VXGE_HAL_FAU_PA_CFG_REPL_L3_INCL_CF; 4537 else 4538 val64 &= ~VXGE_HAL_FAU_PA_CFG_REPL_L3_INCL_CF; 4539 4540 } 4541 4542 if (mac_config->rpa_repl_l3_comp_csum != 4543 VXGE_HAL_MAC_RPA_REPL_l3_COMP_CSUM_DEFAULT) { 4544 4545 if (mac_config->rpa_repl_l3_comp_csum) 4546 val64 |= VXGE_HAL_FAU_PA_CFG_REPL_L3_COMP_CSUM; 4547 else 4548 val64 &= ~VXGE_HAL_FAU_PA_CFG_REPL_L3_COMP_CSUM; 4549 4550 } 4551 4552 vxge_os_pio_mem_write64(hldev->header.pdev, 4553 hldev->header.regh0, 4554 val64, 4555 &hldev->mrpcim_reg->fau_pa_cfg); 4556 4557 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4558 hldev->header.regh0, 4559 &hldev->mrpcim_reg->rxmac_rx_pa_cfg1); 4560 4561 if (mac_config->rpa_repl_ipv4_tcp_incl_ph != 4562 VXGE_HAL_MAC_RPA_REPL_IPV4_TCP_INCL_PH_DEFAULT) { 4563 4564 if (mac_config->rpa_repl_ipv4_tcp_incl_ph) 4565 val64 |= 4566 VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV4_TCP_INCL_PH; 4567 else 4568 val64 &= 4569 ~VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV4_TCP_INCL_PH; 4570 4571 } 4572 4573 if (mac_config->rpa_repl_ipv6_tcp_incl_ph != 4574 VXGE_HAL_MAC_RPA_REPL_IPV6_TCP_INCL_PH_DEFAULT) { 4575 4576 if (mac_config->rpa_repl_ipv6_tcp_incl_ph) 4577 val64 |= 4578 VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV6_TCP_INCL_PH; 4579 else 4580 val64 &= 4581 ~VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV6_TCP_INCL_PH; 4582 4583 } 4584 4585 if (mac_config->rpa_repl_ipv4_udp_incl_ph != 4586 VXGE_HAL_MAC_RPA_REPL_IPV4_UDP_INCL_PH_DEFAULT) { 4587 4588 if (mac_config->rpa_repl_ipv4_udp_incl_ph) 4589 val64 |= 4590 VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV4_UDP_INCL_PH; 4591 else 4592 val64 &= 4593 ~VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV4_UDP_INCL_PH; 4594 4595 } 4596 4597 if (mac_config->rpa_repl_ipv6_udp_incl_ph != 4598 VXGE_HAL_MAC_RPA_REPL_IPV6_UDP_INCL_PH_DEFAULT) { 4599 4600 if (mac_config->rpa_repl_ipv6_udp_incl_ph) 4601 val64 |= 4602 VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV6_UDP_INCL_PH; 4603 else 4604 val64 &= 4605 ~VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV6_UDP_INCL_PH; 4606 4607 } 4608 4609 if (mac_config->rpa_repl_l4_incl_cf != 4610 VXGE_HAL_MAC_RPA_REPL_L4_INCL_CF_DEFAULT) { 4611 4612 if (mac_config->rpa_repl_l4_incl_cf) 4613 val64 |= VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_L4_INCL_CF; 4614 else 4615 val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_L4_INCL_CF; 4616 4617 } 4618 4619 if (mac_config->rpa_repl_strip_vlan_tag != 4620 VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_DEFAULT) { 4621 4622 if (mac_config->rpa_repl_strip_vlan_tag) 4623 val64 |= VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_STRIP_VLAN_TAG; 4624 else 4625 val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_STRIP_VLAN_TAG; 4626 4627 4628 } 4629 4630 vxge_os_pio_mem_write64(hldev->header.pdev, 4631 hldev->header.regh0, 4632 val64, 4633 &hldev->mrpcim_reg->rxmac_rx_pa_cfg1); 4634 4635 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4636 hldev->header.regh0, 4637 &hldev->mrpcim_reg->xmac_gen_cfg); 4638 4639 if (mac_config->network_stability_period != 4640 VXGE_HAL_MAC_DEF_NETWORK_STABILITY_PERIOD) { 4641 4642 val64 &= ~(VXGE_HAL_XMAC_GEN_CFG_PERIOD_NTWK_DOWN(0xf) | 4643 VXGE_HAL_XMAC_GEN_CFG_PERIOD_NTWK_UP(0xf)); 4644 4645 val64 |= VXGE_HAL_XMAC_GEN_CFG_PERIOD_NTWK_DOWN( 4646 mac_config->network_stability_period) | 4647 VXGE_HAL_XMAC_GEN_CFG_PERIOD_NTWK_UP( 4648 mac_config->network_stability_period); 4649 4650 } 4651 4652 vxge_os_pio_mem_write64(hldev->header.pdev, 4653 hldev->header.regh0, 4654 val64, 4655 &hldev->mrpcim_reg->xmac_gen_cfg); 4656 4657 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4658 hldev->header.regh0, 4659 &hldev->mrpcim_reg->tpa_global_cfg); 4660 4661 if (mac_config->tpa_support_snap_ab_n != 4662 VXGE_HAL_MAC_TPA_SUPPORT_SNAP_AB_N_DEFAULT) { 4663 4664 if (mac_config->tpa_support_snap_ab_n) 4665 val64 |= VXGE_HAL_TPA_GLOBAL_CFG_SUPPORT_SNAP_AB_N; 4666 else 4667 val64 &= ~VXGE_HAL_TPA_GLOBAL_CFG_SUPPORT_SNAP_AB_N; 4668 4669 } 4670 4671 if (mac_config->tpa_ecc_enable_n != 4672 VXGE_HAL_MAC_TPA_ECC_ENABLE_N_DEFAULT) { 4673 4674 if (mac_config->tpa_ecc_enable_n) 4675 val64 |= VXGE_HAL_TPA_GLOBAL_CFG_ECC_ENABLE_N; 4676 else 4677 val64 &= ~VXGE_HAL_TPA_GLOBAL_CFG_ECC_ENABLE_N; 4678 4679 } 4680 4681 vxge_os_pio_mem_write64(hldev->header.pdev, 4682 hldev->header.regh0, 4683 val64, 4684 &hldev->mrpcim_reg->tpa_global_cfg); 4685 4686 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 4687 __FILE__, __func__, __LINE__, status); 4688 return (status); 4689 4690} 4691 4692/* 4693 * __hal_mrpcim_lag_configure - Initialize LAG registers 4694 * @hldev: hal device. 4695 * 4696 * Initializes LAG registers 4697 * 4698 */ 4699vxge_hal_status_e 4700__hal_mrpcim_lag_configure(__hal_device_t *hldev) 4701{ 4702 u64 val64; 4703 u64 mac_addr; 4704 u32 i, j; 4705 vxge_hal_status_e status = VXGE_HAL_OK; 4706 vxge_hal_lag_config_t *lag_config = 4707 &hldev->header.config.mrpcim_config.lag_config; 4708 4709 vxge_assert(hldev != NULL); 4710 4711 vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 4712 __FILE__, __func__, __LINE__); 4713 4714 vxge_hal_trace_log_mrpcim("hldev = 0x"VXGE_OS_STXFMT, 4715 (ptr_t) hldev); 4716 4717 4718 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4719 hldev->header.regh0, 4720 &hldev->mrpcim_reg->lag_cfg); 4721 4722 if (lag_config->lag_en == VXGE_HAL_LAG_LAG_EN_DEFAULT) { 4723 4724 if (val64 & VXGE_HAL_LAG_CFG_EN) 4725 lag_config->lag_en = VXGE_HAL_LAG_LAG_EN_ENABLE; 4726 else 4727 lag_config->lag_en = VXGE_HAL_LAG_LAG_EN_DISABLE; 4728 4729 } 4730 4731 if (lag_config->lag_en == VXGE_HAL_LAG_LAG_EN_DISABLE) { 4732 4733 if (val64 & VXGE_HAL_LAG_CFG_EN) { 4734 val64 &= ~VXGE_HAL_LAG_CFG_EN; 4735 vxge_os_pio_mem_write64(hldev->header.pdev, 4736 hldev->header.regh0, 4737 val64, 4738 &hldev->mrpcim_reg->lag_cfg); 4739 } 4740 4741 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0", 4742 __FILE__, __func__, __LINE__); 4743 4744 return (VXGE_HAL_OK); 4745 4746 } 4747 4748 if (lag_config->lag_mode != VXGE_HAL_LAG_LAG_MODE_DEFAULT) { 4749 val64 &= ~VXGE_HAL_LAG_CFG_MODE(0x3); 4750 val64 |= VXGE_HAL_LAG_CFG_MODE(lag_config->lag_mode); 4751 } else { 4752 lag_config->lag_mode = (u32) VXGE_HAL_LAG_CFG_GET_MODE(val64); 4753 } 4754 4755 if (lag_config->la_mode_config.tx_discard != 4756 VXGE_HAL_LAG_TX_DISCARD_DEFAULT) { 4757 if (lag_config->la_mode_config.tx_discard == 4758 VXGE_HAL_LAG_TX_DISCARD_ENABLE) 4759 val64 |= VXGE_HAL_LAG_CFG_TX_DISCARD_BEHAV; 4760 else 4761 val64 &= ~VXGE_HAL_LAG_CFG_TX_DISCARD_BEHAV; 4762 } 4763 4764 if (lag_config->la_mode_config.rx_discard != 4765 VXGE_HAL_LAG_RX_DISCARD_DEFAULT) { 4766 if (lag_config->la_mode_config.rx_discard == 4767 VXGE_HAL_LAG_RX_DISCARD_ENABLE) 4768 val64 |= VXGE_HAL_LAG_CFG_RX_DISCARD_BEHAV; 4769 else 4770 val64 &= ~VXGE_HAL_LAG_CFG_RX_DISCARD_BEHAV; 4771 } 4772 4773 if (lag_config->sl_mode_config.pref_indiv_port != 4774 VXGE_HAL_LAG_PREF_INDIV_PORT_DEFAULT) { 4775 if (lag_config->sl_mode_config.pref_indiv_port == 4776 VXGE_HAL_LAG_RX_DISCARD_ENABLE) 4777 val64 |= VXGE_HAL_LAG_CFG_PREF_INDIV_PORT_NUM; 4778 else 4779 val64 &= ~VXGE_HAL_LAG_CFG_PREF_INDIV_PORT_NUM; 4780 } 4781 4782 vxge_os_pio_mem_write64(hldev->header.pdev, 4783 hldev->header.regh0, 4784 val64, 4785 &hldev->mrpcim_reg->lag_cfg); 4786 4787 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4788 hldev->header.regh0, 4789 &hldev->mrpcim_reg->lag_tx_cfg); 4790 4791 if (lag_config->incr_tx_aggr_stats != 4792 VXGE_HAL_LAG_INCR_TX_AGGR_STATS_DEFAULT) { 4793 if (lag_config->incr_tx_aggr_stats == 4794 VXGE_HAL_LAG_INCR_TX_AGGR_STATS_ENABLE) 4795 val64 |= VXGE_HAL_LAG_TX_CFG_INCR_TX_AGGR_STATS; 4796 else 4797 val64 &= ~VXGE_HAL_LAG_TX_CFG_INCR_TX_AGGR_STATS; 4798 } 4799 4800 if (lag_config->la_mode_config.distrib_alg_sel != 4801 VXGE_HAL_LAG_DISTRIB_ALG_SEL_DEFAULT) { 4802 val64 &= ~VXGE_HAL_LAG_TX_CFG_DISTRIB_ALG_SEL(0x3); 4803 val64 |= VXGE_HAL_LAG_TX_CFG_DISTRIB_ALG_SEL( 4804 lag_config->la_mode_config.distrib_alg_sel); 4805 vxge_os_pio_mem_write64(hldev->header.pdev, 4806 hldev->header.regh0, 4807 lag_config->la_mode_config.distrib_dest, 4808 &hldev->mrpcim_reg->lag_distrib_dest); 4809 } else { 4810 lag_config->la_mode_config.distrib_alg_sel = 4811 (u32) VXGE_HAL_LAG_TX_CFG_GET_DISTRIB_ALG_SEL(val64); 4812 lag_config->la_mode_config.distrib_dest = 4813 vxge_os_pio_mem_read64(hldev->header.pdev, 4814 hldev->header.regh0, 4815 &hldev->mrpcim_reg->lag_distrib_dest); 4816 } 4817 4818 if (lag_config->la_mode_config.distrib_remap_if_fail != 4819 VXGE_HAL_LAG_DISTRIB_REMAP_IF_FAIL_DEFAULT) { 4820 if (lag_config->la_mode_config.distrib_remap_if_fail == 4821 VXGE_HAL_LAG_DISTRIB_REMAP_IF_FAIL_ENABLE) 4822 val64 |= VXGE_HAL_LAG_TX_CFG_DISTRIB_REMAP_IF_FAIL; 4823 else 4824 val64 &= ~VXGE_HAL_LAG_TX_CFG_DISTRIB_REMAP_IF_FAIL; 4825 } 4826 4827 if (lag_config->la_mode_config.coll_max_delay != 4828 VXGE_HAL_LAG_DEF_COLL_MAX_DELAY) { 4829 val64 &= ~VXGE_HAL_LAG_TX_CFG_COLL_MAX_DELAY(0xffff); 4830 val64 |= VXGE_HAL_LAG_TX_CFG_DISTRIB_ALG_SEL( 4831 lag_config->la_mode_config.coll_max_delay); 4832 } 4833 4834 vxge_os_pio_mem_write64(hldev->header.pdev, 4835 hldev->header.regh0, 4836 val64, 4837 &hldev->mrpcim_reg->lag_tx_cfg); 4838 4839 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4840 hldev->header.regh0, 4841 &hldev->mrpcim_reg->lag_active_passive_cfg); 4842 4843 if (lag_config->ap_mode_config.hot_standby != 4844 VXGE_HAL_LAG_HOT_STANDBY_DEFAULT) { 4845 if (lag_config->ap_mode_config.hot_standby == 4846 VXGE_HAL_LAG_HOT_STANDBY_KEEP_UP_PORT) 4847 val64 |= VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_HOT_STANDBY; 4848 else 4849 val64 &= ~VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_HOT_STANDBY; 4850 } 4851 4852 if (lag_config->ap_mode_config.lacp_decides != 4853 VXGE_HAL_LAG_LACP_DECIDES_DEFAULT) { 4854 if (lag_config->ap_mode_config.lacp_decides == 4855 VXGE_HAL_LAG_LACP_DECIDES_ENBALE) 4856 val64 |= VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_LACP_DECIDES; 4857 else 4858 val64 &= ~VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_LACP_DECIDES; 4859 } 4860 4861 if (lag_config->ap_mode_config.pref_active_port != 4862 VXGE_HAL_LAG_PREF_ACTIVE_PORT_DEFAULT) { 4863 if (lag_config->ap_mode_config.pref_active_port == 4864 VXGE_HAL_LAG_PREF_ACTIVE_PORT_1) 4865 val64 |= 4866 VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_PREF_ACTIVE_PORT_NUM; 4867 else 4868 val64 &= 4869 ~VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_PREF_ACTIVE_PORT_NUM; 4870 } 4871 4872 if (lag_config->ap_mode_config.auto_failback != 4873 VXGE_HAL_LAG_AUTO_FAILBACK_DEFAULT) { 4874 if (lag_config->ap_mode_config.auto_failback == 4875 VXGE_HAL_LAG_AUTO_FAILBACK_ENBALE) 4876 val64 |= VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_AUTO_FAILBACK; 4877 else 4878 val64 &= ~VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_AUTO_FAILBACK; 4879 } 4880 4881 if (lag_config->ap_mode_config.failback_en != 4882 VXGE_HAL_LAG_FAILBACK_EN_DEFAULT) { 4883 if (lag_config->ap_mode_config.failback_en == 4884 VXGE_HAL_LAG_FAILBACK_EN_ENBALE) 4885 val64 |= VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_FAILBACK_EN; 4886 else 4887 val64 &= ~VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_FAILBACK_EN; 4888 } 4889 4890 if (lag_config->ap_mode_config.cold_failover_timeout != 4891 VXGE_HAL_LAG_DEF_COLD_FAILOVER_TIMEOUT) { 4892 val64 &= ~VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_COLD_FAILOVER_TIMEOUT( 4893 0xffff); 4894 val64 |= VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_COLD_FAILOVER_TIMEOUT( 4895 lag_config->ap_mode_config.cold_failover_timeout); 4896 } 4897 4898 vxge_os_pio_mem_write64(hldev->header.pdev, 4899 hldev->header.regh0, 4900 val64, 4901 &hldev->mrpcim_reg->lag_active_passive_cfg); 4902 4903 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4904 hldev->header.regh0, 4905 &hldev->mrpcim_reg->lag_lacp_cfg); 4906 4907 if (lag_config->lacp_config.lacp_en != 4908 VXGE_HAL_LAG_LACP_EN_DEFAULT) { 4909 if (lag_config->lacp_config.lacp_en == 4910 VXGE_HAL_LAG_LACP_EN_ENABLE) 4911 val64 |= VXGE_HAL_LAG_LACP_CFG_EN; 4912 else 4913 val64 &= ~VXGE_HAL_LAG_LACP_CFG_EN; 4914 } 4915 4916 if (lag_config->lacp_config.lacp_begin != 4917 VXGE_HAL_LAG_LACP_BEGIN_DEFAULT) { 4918 if (lag_config->lacp_config.lacp_begin == 4919 VXGE_HAL_LAG_LACP_BEGIN_RESET) 4920 val64 |= VXGE_HAL_LAG_LACP_CFG_LACP_BEGIN; 4921 else 4922 val64 &= ~VXGE_HAL_LAG_LACP_CFG_LACP_BEGIN; 4923 } 4924 4925 if (lag_config->lacp_config.discard_lacp != 4926 VXGE_HAL_LAG_DISCARD_LACP_DEFAULT) { 4927 if (lag_config->lacp_config.discard_lacp == 4928 VXGE_HAL_LAG_DISCARD_LACP_ENABLE) 4929 val64 |= VXGE_HAL_LAG_LACP_CFG_DISCARD_LACP; 4930 else 4931 val64 &= ~VXGE_HAL_LAG_LACP_CFG_DISCARD_LACP; 4932 } 4933 4934 if (lag_config->lacp_config.liberal_len_chk != 4935 VXGE_HAL_LAG_LIBERAL_LEN_CHK_DEFAULT) { 4936 if (lag_config->lacp_config.liberal_len_chk == 4937 VXGE_HAL_LAG_LIBERAL_LEN_CHK_ENABLE) 4938 val64 |= VXGE_HAL_LAG_LACP_CFG_LIBERAL_LEN_CHK; 4939 else 4940 val64 &= ~VXGE_HAL_LAG_LACP_CFG_LIBERAL_LEN_CHK; 4941 } 4942 4943 vxge_os_pio_mem_write64(hldev->header.pdev, 4944 hldev->header.regh0, 4945 val64, 4946 &hldev->mrpcim_reg->lag_lacp_cfg); 4947 4948 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 4949 hldev->header.regh0, 4950 &hldev->mrpcim_reg->lag_marker_cfg); 4951 4952 if (lag_config->lacp_config.marker_gen_recv_en != 4953 VXGE_HAL_LAG_MARKER_GEN_RECV_EN_DEFAULT) { 4954 if (lag_config->lacp_config.marker_gen_recv_en == 4955 VXGE_HAL_LAG_MARKER_GEN_RECV_EN_ENABLE) 4956 val64 |= VXGE_HAL_LAG_MARKER_CFG_GEN_RCVR_EN; 4957 else 4958 val64 &= ~VXGE_HAL_LAG_MARKER_CFG_GEN_RCVR_EN; 4959 } 4960 4961 if (lag_config->lacp_config.marker_resp_en != 4962 VXGE_HAL_LAG_MARKER_RESP_EN_DEFAULT) { 4963 if (lag_config->lacp_config.marker_resp_en == 4964 VXGE_HAL_LAG_MARKER_RESP_EN_ENABLE) 4965 val64 |= VXGE_HAL_LAG_MARKER_CFG_RESP_EN; 4966 else 4967 val64 &= ~VXGE_HAL_LAG_MARKER_CFG_RESP_EN; 4968 } 4969 4970 if (lag_config->lacp_config.marker_resp_timeout != 4971 VXGE_HAL_LAG_DEF_MARKER_RESP_TIMEOUT) { 4972 val64 &= ~VXGE_HAL_LAG_MARKER_CFG_RESP_TIMEOUT(0xffff); 4973 val64 |= VXGE_HAL_LAG_MARKER_CFG_RESP_TIMEOUT( 4974 lag_config->lacp_config.marker_resp_timeout); 4975 } 4976 4977 if (lag_config->lacp_config.slow_proto_mrkr_min_interval != 4978 VXGE_HAL_LAG_DEF_SLOW_PROTO_MRKR_MIN_INTERVAL) { 4979 val64 &= ~VXGE_HAL_LAG_MARKER_CFG_SLOW_PROTO_MRKR_MIN_INTERVAL( 4980 0xffff); 4981 val64 |= VXGE_HAL_LAG_MARKER_CFG_SLOW_PROTO_MRKR_MIN_INTERVAL( 4982 lag_config->lacp_config.slow_proto_mrkr_min_interval); 4983 } 4984 4985 if (lag_config->lacp_config.throttle_mrkr_resp != 4986 VXGE_HAL_LAG_THROTTLE_MRKR_RESP_DEFAULT) { 4987 if (lag_config->lacp_config.throttle_mrkr_resp == 4988 VXGE_HAL_LAG_THROTTLE_MRKR_RESP_ENABLE) 4989 val64 |= VXGE_HAL_LAG_MARKER_CFG_THROTTLE_MRKR_RESP; 4990 else 4991 val64 &= ~VXGE_HAL_LAG_MARKER_CFG_THROTTLE_MRKR_RESP; 4992 } 4993 4994 vxge_os_pio_mem_write64(hldev->header.pdev, 4995 hldev->header.regh0, 4996 val64, 4997 &hldev->mrpcim_reg->lag_marker_cfg); 4998 4999 for (i = 0; i < VXGE_HAL_LAG_PORT_MAX_PORTS; i++) { 5000 5001 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5002 hldev->header.regh0, 5003 &hldev->mrpcim_reg->lag_port_cfg[i]); 5004 5005 if (lag_config->port_config[i].lag_en != 5006 VXGE_HAL_LAG_PORT_LAG_EN_DEFAULT) { 5007 if (lag_config->port_config[i].lag_en == 5008 VXGE_HAL_LAG_PORT_LAG_EN_ENABLE) 5009 val64 |= VXGE_HAL_LAG_PORT_CFG_EN; 5010 else 5011 val64 &= ~VXGE_HAL_LAG_PORT_CFG_EN; 5012 } 5013 5014 if (lag_config->port_config[i].discard_slow_proto != 5015 VXGE_HAL_LAG_PORT_DISCARD_SLOW_PROTO_DEFAULT) { 5016 if (lag_config->port_config[i].discard_slow_proto == 5017 VXGE_HAL_LAG_PORT_DISCARD_SLOW_PROTO_ENABLE) 5018 val64 |= 5019 VXGE_HAL_LAG_PORT_CFG_DISCARD_SLOW_PROTO; 5020 else 5021 val64 &= 5022 ~VXGE_HAL_LAG_PORT_CFG_DISCARD_SLOW_PROTO; 5023 } 5024 5025 if (lag_config->port_config[i].host_chosen_aggr != 5026 VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_DEFAULT) { 5027 if (lag_config->port_config[i].host_chosen_aggr == 5028 VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_1) 5029 val64 |= 5030 VXGE_HAL_LAG_PORT_CFG_HOST_CHOSEN_AGGR; 5031 else 5032 val64 &= 5033 ~VXGE_HAL_LAG_PORT_CFG_HOST_CHOSEN_AGGR; 5034 } 5035 5036 if (lag_config->port_config[i].discard_unknown_slow_proto != 5037 VXGE_HAL_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO_DEFAULT) { 5038 if (lag_config->port_config[i].discard_unknown_slow_proto == 5039 VXGE_HAL_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO_ENABLE) 5040 val64 |= 5041 VXGE_HAL_LAG_PORT_CFG_DISCARD_UNKNOWN_SLOW_PROTO; 5042 else 5043 val64 &= 5044 ~VXGE_HAL_LAG_PORT_CFG_DISCARD_UNKNOWN_SLOW_PROTO; 5045 } 5046 5047 vxge_os_pio_mem_write64(hldev->header.pdev, 5048 hldev->header.regh0, 5049 val64, 5050 &hldev->mrpcim_reg->lag_port_cfg[i]); 5051 5052 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5053 hldev->header.regh0, 5054 &hldev->mrpcim_reg->lag_port_actor_admin_cfg[i]); 5055 5056 if (lag_config->port_config[i].actor_port_num != 5057 VXGE_HAL_LAG_PORT_DEF_ACTOR_PORT_NUM) { 5058 val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_PORT_NUM( 5059 0xffff); 5060 val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_PORT_NUM( 5061 lag_config->port_config[i].actor_port_num); 5062 } 5063 5064 if (lag_config->port_config[i].actor_port_priority != 5065 VXGE_HAL_LAG_PORT_DEF_ACTOR_PORT_PRIORITY) { 5066 val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_PORT_PRI( 5067 0xffff); 5068 val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_PORT_PRI( 5069 lag_config->port_config[i].actor_port_priority); 5070 } 5071 5072 if (lag_config->port_config[i].actor_key_10g != 5073 VXGE_HAL_LAG_PORT_DEF_ACTOR_KEY_10G) { 5074 val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_KEY_10G( 5075 0xffff); 5076 val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_KEY_10G( 5077 lag_config->port_config[i].actor_key_10g); 5078 } 5079 5080 if (lag_config->port_config[i].actor_key_1g != 5081 VXGE_HAL_LAG_PORT_DEF_ACTOR_KEY_1G) { 5082 val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_KEY_1G( 5083 0xffff); 5084 val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_KEY_1G( 5085 lag_config->port_config[i].actor_key_1g); 5086 } 5087 5088 vxge_os_pio_mem_write64(hldev->header.pdev, 5089 hldev->header.regh0, 5090 val64, 5091 &hldev->mrpcim_reg->lag_port_actor_admin_cfg[i]); 5092 5093 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5094 hldev->header.regh0, 5095 &hldev->mrpcim_reg->lag_port_actor_admin_state[i]); 5096 5097 if (lag_config->port_config[i].actor_lacp_activity != 5098 VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_DEFAULT) { 5099 if (lag_config->port_config[i].actor_lacp_activity == 5100 VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_ACTIVE) 5101 val64 |= 5102 VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_LACP_ACTIVITY; 5103 else 5104 val64 &= 5105 ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_LACP_ACTIVITY; 5106 } 5107 5108 if (lag_config->port_config[i].actor_lacp_timeout != 5109 VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_DEFAULT) { 5110 if (lag_config->port_config[i].actor_lacp_timeout == 5111 VXGE_HAL_LAG_PORT_ACTOR_LACP_TIMEOUT_SHORT) 5112 val64 |= 5113 VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_LACP_TIMEOUT; 5114 else 5115 val64 &= 5116 ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_LACP_TIMEOUT; 5117 } 5118 5119 if (lag_config->port_config[i].actor_aggregation != 5120 VXGE_HAL_LAG_PORT_ACTOR_AGGREGATION_DEFAULT) { 5121 if (lag_config->port_config[i].actor_aggregation == 5122 VXGE_HAL_LAG_PORT_ACTOR_AGGREGATION_AGGREGATEABLE) 5123 val64 |= 5124 VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_AGGREGATION; 5125 else 5126 val64 &= 5127 ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_AGGREGATION; 5128 } 5129 5130 if (lag_config->port_config[i].actor_synchronization != 5131 VXGE_HAL_LAG_PORT_ACTOR_SYNCHRONIZATION_DEFAULT) { 5132 if (lag_config->port_config[i].actor_aggregation == 5133 VXGE_HAL_LAG_PORT_ACTOR_SYNCHRONIZATION_IN_SYNC) 5134 val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_SYNCHRONIZATION; 5135 else 5136 val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_SYNCHRONIZATION; 5137 } 5138 5139 if (lag_config->port_config[i].actor_collecting != 5140 VXGE_HAL_LAG_PORT_ACTOR_COLLECTING_DEFAULT) { 5141 if (lag_config->port_config[i].actor_collecting == 5142 VXGE_HAL_LAG_PORT_ACTOR_COLLECTING_ENABLE) 5143 val64 |= 5144 VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_COLLECTING; 5145 else 5146 val64 &= 5147 ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_COLLECTING; 5148 } 5149 5150 if (lag_config->port_config[i].actor_distributing != 5151 VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_DEFAULT) { 5152 if (lag_config->port_config[i].actor_distributing == 5153 VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_ENABLE) 5154 val64 |= 5155 VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_DISTRIBUTING; 5156 else 5157 val64 &= 5158 ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_DISTRIBUTING; 5159 } 5160 5161 if (lag_config->port_config[i].actor_defaulted != 5162 VXGE_HAL_LAG_PORT_ACTOR_DEFAULTED_DEFAULT) { 5163 if (lag_config->port_config[i].actor_defaulted == 5164 VXGE_HAL_LAG_PORT_ACTOR_NOT_DEFAULTED) 5165 val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_DEFAULTED; 5166 else 5167 val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_DEFAULTED; 5168 } 5169 5170 if (lag_config->port_config[i].actor_expired != 5171 VXGE_HAL_LAG_PORT_ACTOR_EXPIRED_DEFAULT) { 5172 if (lag_config->port_config[i].actor_expired == 5173 VXGE_HAL_LAG_PORT_ACTOR_NOT_EXPIRED) 5174 val64 |= VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_EXPIRED; 5175 else 5176 val64 &= ~VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_EXPIRED; 5177 } 5178 5179 vxge_os_pio_mem_write64(hldev->header.pdev, 5180 hldev->header.regh0, 5181 val64, 5182 &hldev->mrpcim_reg->lag_port_actor_admin_state[i]); 5183 5184 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5185 hldev->header.regh0, 5186 &hldev->mrpcim_reg->lag_port_partner_admin_cfg[i]); 5187 5188 if (lag_config->port_config[i].partner_sys_pri != 5189 VXGE_HAL_LAG_PORT_DEF_PARTNER_SYS_PRI) { 5190 val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_SYS_PRI( 5191 0xffff); 5192 val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_SYS_PRI( 5193 lag_config->port_config[i].partner_sys_pri); 5194 } 5195 5196 if (lag_config->port_config[i].partner_key != 5197 VXGE_HAL_LAG_PORT_DEF_PARTNER_KEY) { 5198 val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_KEY( 5199 0xffff); 5200 val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_KEY( 5201 lag_config->port_config[i].partner_key); 5202 } 5203 5204 if (lag_config->port_config[i].partner_port_num != 5205 VXGE_HAL_LAG_PORT_DEF_PARTNER_PORT_NUM) { 5206 val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_PORT_NUM( 5207 0xffff); 5208 val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_PORT_NUM( 5209 lag_config->port_config[i].partner_port_num); 5210 } 5211 5212 if (lag_config->port_config[i].partner_port_priority != 5213 VXGE_HAL_LAG_PORT_DEF_PARTNER_PORT_PRIORITY) { 5214 val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_PORT_PRI( 5215 0xffff); 5216 val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_PORT_PRI( 5217 lag_config->port_config[i].actor_port_priority); 5218 } 5219 5220 vxge_os_pio_mem_write64(hldev->header.pdev, 5221 hldev->header.regh0, 5222 val64, 5223 &hldev->mrpcim_reg->lag_port_partner_admin_cfg[i]); 5224 5225 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5226 hldev->header.regh0, 5227 &hldev->mrpcim_reg->lag_port_partner_admin_state[i]); 5228 5229 if (lag_config->port_config[i].partner_lacp_activity != 5230 VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_DEFAULT) { 5231 if (lag_config->port_config[i].partner_lacp_activity == 5232 VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_ACTIVE) 5233 val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_LACP_ACTIVITY; 5234 else 5235 val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_LACP_ACTIVITY; 5236 } 5237 5238 if (lag_config->port_config[i].partner_lacp_timeout != 5239 VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_DEFAULT) { 5240 if (lag_config->port_config[i].partner_lacp_timeout == 5241 VXGE_HAL_LAG_PORT_PARTNER_LACP_TIMEOUT_SHORT) 5242 val64 |= 5243 VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_LACP_TIMEOUT; 5244 else 5245 val64 &= 5246 ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_LACP_TIMEOUT; 5247 } 5248 5249 if (lag_config->port_config[i].partner_aggregation != 5250 VXGE_HAL_LAG_PORT_PARTNER_AGGREGATION_DEFAULT) { 5251 if (lag_config->port_config[i].partner_aggregation == 5252 VXGE_HAL_LAG_PORT_PARTNER_AGGREGATION_AGGREGATEABLE) 5253 val64 |= 5254 VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_AGGREGATION; 5255 else 5256 val64 &= 5257 ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_AGGREGATION; 5258 } 5259 5260 if (lag_config->port_config[i].partner_synchronization != 5261 VXGE_HAL_LAG_PORT_PARTNER_SYNCHRONIZATION_DEFAULT) { 5262 if (lag_config->port_config[i].partner_aggregation == 5263 VXGE_HAL_LAG_PORT_PARTNER_SYNCHRONIZATION_IN_SYNC) 5264 val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_SYNCHRONIZATION; 5265 else 5266 val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_SYNCHRONIZATION; 5267 } 5268 5269 if (lag_config->port_config[i].partner_collecting != 5270 VXGE_HAL_LAG_PORT_PARTNER_COLLECTING_DEFAULT) { 5271 if (lag_config->port_config[i].partner_collecting == 5272 VXGE_HAL_LAG_PORT_PARTNER_COLLECTING_ENABLE) 5273 val64 |= 5274 VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_COLLECTING; 5275 else 5276 val64 &= 5277 ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_COLLECTING; 5278 } 5279 5280 if (lag_config->port_config[i].partner_distributing != 5281 VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_DEFAULT) { 5282 if (lag_config->port_config[i].partner_distributing == 5283 VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_ENABLE) 5284 val64 |= 5285 VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_DISTRIBUTING; 5286 else 5287 val64 &= 5288 ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_DISTRIBUTING; 5289 } 5290 5291 if (lag_config->port_config[i].partner_defaulted != 5292 VXGE_HAL_LAG_PORT_PARTNER_DEFAULTED_DEFAULT) { 5293 if (lag_config->port_config[i].partner_defaulted == 5294 VXGE_HAL_LAG_PORT_PARTNER_NOT_DEFAULTED) 5295 val64 |= 5296 VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_DEFAULTED; 5297 else 5298 val64 &= 5299 ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_DEFAULTED; 5300 } 5301 5302 if (lag_config->port_config[i].partner_expired != 5303 VXGE_HAL_LAG_PORT_PARTNER_EXPIRED_DEFAULT) { 5304 if (lag_config->port_config[i].partner_expired == 5305 VXGE_HAL_LAG_PORT_PARTNER_NOT_EXPIRED) 5306 val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_EXPIRED; 5307 else 5308 val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_EXPIRED; 5309 } 5310 5311 vxge_os_pio_mem_write64(hldev->header.pdev, 5312 hldev->header.regh0, 5313 val64, 5314 &hldev->mrpcim_reg->lag_port_partner_admin_state[i]); 5315 5316 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5317 hldev->header.regh0, 5318 &hldev->mrpcim_reg->lag_port_partner_admin_sys_id[i]); 5319 5320 mac_addr = 0; 5321 5322 for (j = 0; j < VXGE_HAL_ETH_ALEN; j++) { 5323 mac_addr <<= 8; 5324 mac_addr |= 5325 (u8) lag_config->port_config[i].partner_mac_addr[j]; 5326 } 5327 5328 if (mac_addr != 0xffffffffffffULL) { 5329 val64 &= ~VXGE_HAL_LAG_PORT_PARTNER_ADMIN_SYS_ID_ADDR( 5330 0xffffffffffffULL); 5331 val64 |= VXGE_HAL_LAG_PORT_PARTNER_ADMIN_SYS_ID_ADDR( 5332 mac_addr); 5333 } 5334 5335 vxge_os_pio_mem_write64(hldev->header.pdev, 5336 hldev->header.regh0, 5337 val64, 5338 &hldev->mrpcim_reg->lag_port_partner_admin_sys_id[i]); 5339 5340 } 5341 5342 for (i = 0; i < VXGE_HAL_LAG_AGGR_MAX_PORTS; i++) { 5343 5344 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5345 hldev->header.regh0, 5346 &hldev->mrpcim_reg->lag_aggr_id_cfg[i]); 5347 5348 val64 &= ~VXGE_HAL_LAG_AGGR_ID_CFG_ID(0xffff); 5349 val64 |= VXGE_HAL_LAG_AGGR_ID_CFG_ID( 5350 lag_config->aggr_config[i].aggr_id); 5351 5352 vxge_os_pio_mem_write64(hldev->header.pdev, 5353 hldev->header.regh0, 5354 val64, 5355 &hldev->mrpcim_reg->lag_aggr_id_cfg[i]); 5356 5357 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5358 hldev->header.regh0, 5359 &hldev->mrpcim_reg->lag_aggr_addr_cfg[i]); 5360 5361 mac_addr = 0; 5362 5363 for (j = 0; j < VXGE_HAL_ETH_ALEN; j++) { 5364 mac_addr <<= 8; 5365 mac_addr |= (u8) lag_config->aggr_config[i].mac_addr[j]; 5366 } 5367 5368 if (mac_addr != 0xffffffffffffULL) { 5369 val64 &= 5370 ~VXGE_HAL_LAG_AGGR_ADDR_CFG_ADDR(0xffffffffffffULL); 5371 val64 |= VXGE_HAL_LAG_AGGR_ADDR_CFG_ADDR(mac_addr); 5372 } 5373 5374 if (lag_config->aggr_config[i].use_port_mac_addr != 5375 VXGE_HAL_LAG_AGGR_USE_PORT_MAC_ADDR_DEFAULT) { 5376 if (lag_config->aggr_config[i].use_port_mac_addr == 5377 VXGE_HAL_LAG_AGGR_USE_PORT_MAC_ADDR_ENABLE) 5378 val64 |= 5379 VXGE_HAL_LAG_AGGR_ADDR_CFG_USE_PORT_ADDR; 5380 else 5381 val64 &= 5382 ~VXGE_HAL_LAG_AGGR_ADDR_CFG_USE_PORT_ADDR; 5383 } 5384 5385 if (lag_config->aggr_config[i].mac_addr_sel != 5386 VXGE_HAL_LAG_AGGR_MAC_ADDR_SEL_DEFAULT) { 5387 if (lag_config->aggr_config[i].mac_addr_sel == 5388 VXGE_HAL_LAG_AGGR_MAC_ADDR_SEL_PORT_1) 5389 val64 |= VXGE_HAL_LAG_AGGR_ADDR_CFG_ADDR_SEL; 5390 else 5391 val64 &= ~VXGE_HAL_LAG_AGGR_ADDR_CFG_ADDR_SEL; 5392 } 5393 5394 vxge_os_pio_mem_write64(hldev->header.pdev, 5395 hldev->header.regh0, 5396 val64, 5397 &hldev->mrpcim_reg->lag_aggr_addr_cfg[i]); 5398 5399 if (lag_config->aggr_config[i].admin_key == 5400 VXGE_HAL_LAG_AGGR_DEF_ADMIN_KEY) { 5401 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5402 hldev->header.regh0, 5403 &hldev->mrpcim_reg->lag_aggr_admin_key[i]); 5404 5405 val64 &= ~VXGE_HAL_LAG_AGGR_ADMIN_KEY_KEY(0xffff); 5406 val64 |= VXGE_HAL_LAG_AGGR_ADMIN_KEY_KEY( 5407 lag_config->aggr_config[i].admin_key); 5408 5409 vxge_os_pio_mem_write64(hldev->header.pdev, 5410 hldev->header.regh0, 5411 val64, 5412 &hldev->mrpcim_reg->lag_aggr_admin_key[i]); 5413 } 5414 } 5415 5416 if (lag_config->sys_pri != VXGE_HAL_LAG_DEF_SYS_PRI) { 5417 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5418 hldev->header.regh0, 5419 &hldev->mrpcim_reg->lag_sys_cfg); 5420 5421 val64 &= ~VXGE_HAL_LAG_SYS_CFG_SYS_PRI(0xffff); 5422 val64 |= VXGE_HAL_LAG_SYS_CFG_SYS_PRI( 5423 lag_config->sys_pri); 5424 5425 vxge_os_pio_mem_write64(hldev->header.pdev, 5426 hldev->header.regh0, 5427 val64, 5428 &hldev->mrpcim_reg->lag_sys_cfg); 5429 } 5430 5431 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5432 hldev->header.regh0, 5433 &hldev->mrpcim_reg->lag_sys_id); 5434 5435 mac_addr = 0; 5436 5437 for (j = 0; j < VXGE_HAL_ETH_ALEN; j++) { 5438 mac_addr <<= 8; 5439 mac_addr |= (u8) lag_config->mac_addr[j]; 5440 } 5441 5442 if (mac_addr != 0xffffffffffffULL) { 5443 val64 &= ~VXGE_HAL_LAG_SYS_ID_ADDR(0xffffffffffffULL); 5444 val64 |= VXGE_HAL_LAG_SYS_ID_ADDR(mac_addr); 5445 } 5446 5447 if (lag_config->use_port_mac_addr != 5448 VXGE_HAL_LAG_USE_PORT_MAC_ADDR_DEFAULT) { 5449 if (lag_config->use_port_mac_addr == 5450 VXGE_HAL_LAG_USE_PORT_MAC_ADDR_ENABLE) 5451 val64 |= VXGE_HAL_LAG_SYS_ID_USE_PORT_ADDR; 5452 else 5453 val64 &= ~VXGE_HAL_LAG_SYS_ID_USE_PORT_ADDR; 5454 } 5455 5456 if (lag_config->mac_addr_sel != VXGE_HAL_LAG_MAC_ADDR_SEL_DEFAULT) { 5457 if (lag_config->mac_addr_sel == 5458 VXGE_HAL_LAG_MAC_ADDR_SEL_PORT_1) 5459 val64 |= VXGE_HAL_LAG_SYS_ID_ADDR_SEL; 5460 else 5461 val64 &= ~VXGE_HAL_LAG_SYS_ID_ADDR_SEL; 5462 } 5463 5464 vxge_os_pio_mem_write64(hldev->header.pdev, 5465 hldev->header.regh0, 5466 val64, 5467 &hldev->mrpcim_reg->lag_sys_id); 5468 5469 5470 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5471 hldev->header.regh0, 5472 &hldev->mrpcim_reg->lag_aggr_alt_admin_key); 5473 5474 if (lag_config->ap_mode_config.alt_admin_key != 5475 VXGE_HAL_LAG_DEF_ALT_ADMIN_KEY) { 5476 val64 &= ~VXGE_HAL_LAG_AGGR_ALT_ADMIN_KEY_KEY(0xffff); 5477 val64 |= VXGE_HAL_LAG_AGGR_ALT_ADMIN_KEY_KEY( 5478 lag_config->ap_mode_config.alt_admin_key); 5479 } 5480 5481 if (lag_config->ap_mode_config.alt_aggr != 5482 VXGE_HAL_LAG_ALT_AGGR_DEFAULT) { 5483 if (lag_config->ap_mode_config.alt_aggr == 5484 VXGE_HAL_LAG_ALT_AGGR_1) 5485 val64 |= VXGE_HAL_LAG_AGGR_ALT_ADMIN_KEY_ALT_AGGR; 5486 else 5487 val64 &= ~VXGE_HAL_LAG_AGGR_ALT_ADMIN_KEY_ALT_AGGR; 5488 } 5489 5490 vxge_os_pio_mem_write64(hldev->header.pdev, 5491 hldev->header.regh0, 5492 val64, 5493 &hldev->mrpcim_reg->lag_aggr_alt_admin_key); 5494 5495 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5496 hldev->header.regh0, 5497 &hldev->mrpcim_reg->lag_timer_cfg_1); 5498 5499 if (lag_config->fast_per_time != VXGE_HAL_LAG_DEF_FAST_PER_TIME) { 5500 val64 &= ~VXGE_HAL_LAG_TIMER_CFG_1_FAST_PER(0xffff); 5501 val64 |= VXGE_HAL_LAG_TIMER_CFG_1_FAST_PER( 5502 lag_config->fast_per_time); 5503 } 5504 5505 if (lag_config->slow_per_time != VXGE_HAL_LAG_DEF_SLOW_PER_TIME) { 5506 val64 &= ~VXGE_HAL_LAG_TIMER_CFG_1_SLOW_PER(0xffff); 5507 val64 |= VXGE_HAL_LAG_TIMER_CFG_1_SLOW_PER( 5508 lag_config->slow_per_time); 5509 } 5510 5511 if (lag_config->short_timeout != VXGE_HAL_LAG_DEF_SHORT_TIMEOUT) { 5512 val64 &= ~VXGE_HAL_LAG_TIMER_CFG_1_SHORT_TIMEOUT(0xffff); 5513 val64 |= VXGE_HAL_LAG_TIMER_CFG_1_SHORT_TIMEOUT( 5514 lag_config->short_timeout); 5515 } 5516 5517 if (lag_config->long_timeout != VXGE_HAL_LAG_DEF_LONG_TIMEOUT) { 5518 val64 &= ~VXGE_HAL_LAG_TIMER_CFG_1_LONG_TIMEOUT(0xffff); 5519 val64 |= VXGE_HAL_LAG_TIMER_CFG_1_LONG_TIMEOUT( 5520 lag_config->short_timeout); 5521 } 5522 5523 vxge_os_pio_mem_write64(hldev->header.pdev, 5524 hldev->header.regh0, 5525 val64, 5526 &hldev->mrpcim_reg->lag_timer_cfg_1); 5527 5528 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 5529 hldev->header.regh0, 5530 &hldev->mrpcim_reg->lag_timer_cfg_2); 5531 5532 if (lag_config->churn_det_time != VXGE_HAL_LAG_DEF_CHURN_DET_TIME) { 5533 val64 &= ~VXGE_HAL_LAG_TIMER_CFG_2_CHURN_DET(0xffff); 5534 val64 |= VXGE_HAL_LAG_TIMER_CFG_2_CHURN_DET( 5535 lag_config->churn_det_time); 5536 } 5537 5538 if (lag_config->aggr_wait_time != VXGE_HAL_LAG_DEF_AGGR_WAIT_TIME) { 5539 val64 &= ~VXGE_HAL_LAG_TIMER_CFG_2_AGGR_WAIT(0xffff); 5540 val64 |= VXGE_HAL_LAG_TIMER_CFG_2_AGGR_WAIT( 5541 lag_config->slow_per_time); 5542 } 5543 5544 if (lag_config->short_timer_scale != 5545 VXGE_HAL_LAG_SHORT_TIMER_SCALE_DEFAULT) { 5546 val64 &= ~VXGE_HAL_LAG_TIMER_CFG_2_SHORT_TIMER_SCALE(0xffff); 5547 val64 |= VXGE_HAL_LAG_TIMER_CFG_2_SHORT_TIMER_SCALE( 5548 lag_config->short_timer_scale); 5549 } 5550 5551 if (lag_config->long_timer_scale != 5552 VXGE_HAL_LAG_LONG_TIMER_SCALE_DEFAULT) { 5553 val64 &= ~VXGE_HAL_LAG_TIMER_CFG_2_LONG_TIMER_SCALE(0xffff); 5554 val64 |= VXGE_HAL_LAG_TIMER_CFG_2_LONG_TIMER_SCALE( 5555 lag_config->long_timer_scale); 5556 } 5557 5558 vxge_os_pio_mem_write64(hldev->header.pdev, 5559 hldev->header.regh0, 5560 val64, 5561 &hldev->mrpcim_reg->lag_timer_cfg_2); 5562 5563 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 5564 __FILE__, __func__, __LINE__, status); 5565 return (status); 5566 5567} 5568 5569/* 5570 * __hal_mrpcim_get_vpd_data - Getting vpd_data. 5571 * 5572 * @hldev: HAL device handle. 5573 * 5574 * Getting product name and serial number from vpd capabilites structure 5575 * 5576 */ 5577void 5578__hal_mrpcim_get_vpd_data(__hal_device_t *hldev) 5579{ 5580 u8 *vpd_data; 5581 u16 data; 5582 u32 data32; 5583 u32 i, j, count, fail = 0; 5584 u32 addr_offset, data_offset; 5585 u32 max_count = hldev->header.config.device_poll_millis * 10; 5586 5587 vxge_assert(hldev); 5588 5589 vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 5590 __FILE__, __func__, __LINE__); 5591 5592 vxge_hal_trace_log_mrpcim("hldev = 0x"VXGE_OS_STXFMT, 5593 (ptr_t) hldev); 5594 5595 addr_offset = hldev->pci_caps.vpd_cap_offset + 5596 vxge_offsetof(vxge_hal_vpid_capability_le_t, vpd_address); 5597 5598 data_offset = hldev->pci_caps.vpd_cap_offset + 5599 vxge_offsetof(vxge_hal_vpid_capability_le_t, vpd_data); 5600 5601 vxge_os_strlcpy((char *) hldev->mrpcim->vpd_data.product_name, 5602 "10 Gigabit Ethernet Adapter", 5603 sizeof(hldev->mrpcim->vpd_data.product_name)); 5604 vxge_os_strlcpy((char *) hldev->mrpcim->vpd_data.serial_num, 5605 "not available", 5606 sizeof(hldev->mrpcim->vpd_data.serial_num)); 5607 5608 if (hldev->func_id != 0) { 5609 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 5610 __FILE__, __func__, __LINE__, 5611 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 5612 return; 5613 } 5614 vpd_data = (u8 *) vxge_os_malloc(hldev->header.pdev, 5615 VXGE_HAL_VPD_BUFFER_SIZE + 16); 5616 if (vpd_data == NULL) 5617 return; 5618 5619 for (i = 0; i < VXGE_HAL_VPD_BUFFER_SIZE; i += 4) { 5620 vxge_os_pci_write16(hldev->header.pdev, 5621 hldev->header.cfgh, 5622 addr_offset, (u16) i); 5623 for (count = 0; count < max_count; count++) { 5624 vxge_os_udelay(100); 5625 (void) __hal_vpath_pci_read(hldev, 5626 hldev->first_vp_id, 5627 addr_offset, 2, &data); 5628 if (data & VXGE_HAL_PCI_VPID_COMPL_FALG) 5629 break; 5630 } 5631 5632 if (count >= max_count) { 5633 vxge_hal_info_log_device("%s:ERR, \ 5634 Reading VPD data failed", __func__); 5635 fail = 1; 5636 break; 5637 } 5638 (void) __hal_vpath_pci_read(hldev, 5639 hldev->first_vp_id, 5640 data_offset, 5641 4, 5642 &data32); 5643 5644 for (j = 0; j < 4; j++) { 5645 vpd_data[i + j] = (u8) (data32 & 0xff); 5646 data32 >>= 8; 5647 } 5648 } 5649 5650 if (!fail) { 5651 5652 /* read serial number of adapter */ 5653 for (count = 0; count < VXGE_HAL_VPD_BUFFER_SIZE; count++) { 5654 if ((vpd_data[count] == 'S') && 5655 (vpd_data[count + 1] == 'N') && 5656 (vpd_data[count + 2] < VXGE_HAL_VPD_LENGTH)) { 5657 (void) vxge_os_memzero( 5658 hldev->mrpcim->vpd_data.serial_num, 5659 VXGE_HAL_VPD_LENGTH); 5660 (void) vxge_os_memcpy( 5661 hldev->mrpcim->vpd_data.serial_num, 5662 &vpd_data[count + 3], 5663 vpd_data[count + 2]); 5664 break; 5665 } 5666 } 5667 5668 if (vpd_data[1] < VXGE_HAL_VPD_LENGTH) { 5669 (void) vxge_os_memzero( 5670 hldev->mrpcim->vpd_data.product_name, vpd_data[1]); 5671 (void) vxge_os_memcpy(hldev->mrpcim->vpd_data.product_name, 5672 &vpd_data[3], vpd_data[1]); 5673 } 5674 } 5675 5676 vxge_os_free(hldev->header.pdev, 5677 vpd_data, 5678 VXGE_HAL_VPD_BUFFER_SIZE + 16); 5679 5680 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 5681 __FILE__, __func__, __LINE__, fail); 5682} 5683 5684/* 5685 * __hal_mrpcim_rts_table_access - Get/Set the entries from RTS access tables 5686 * @devh: Device handle. 5687 * @action: Write Enable. 0 - Read Operation; 1 - Write Operation 5688 * @rts_table: Data structure select. Identifies the RTS data structure 5689 * (i.e. lookup table) to access. 5690 * 0; DA; Destination Address 5691 * 1; VID; VLAN ID 5692 * 2; ETYPE; Ethertype 5693 * 3; PN; Layer 4 Port Number 5694 * 4; RANGE_PN; Range of Layer 4 Port Numbers 5695 * 5; RTH_GEN_CFG; Receive-Traffic Hashing General Configuration 5696 * 6; RTH_SOLO_IT; Receive-Traffic Hashing Indirection Table 5697 * (Single Bucket Programming) 5698 * 7; RTH_JHASH_CFG; Receive-Traffic Hashing Jenkins Hash Config 5699 * 8; RTH_MASK; Receive-Traffic Hashing Mask 5700 * 9; RTH_KEY; Receive-Traffic Hashing Key 5701 * 10; QOS; VLAN Quality of Service 5702 * 11; DS; IP Differentiated Services 5703 * @offset: Offset (into the data structure) to execute the command on. 5704 * @data1: Pointer to the data 1 to be read from the table 5705 * @data2: Pointer to the data 2 to be read from the table 5706 * @vpath_vector: Identifies the candidate VPATH(s) for the given entry. 5707 * These VPATH(s) determine the set of target destinations for 5708 * a frame that matches this steering entry. Any or all bits 5709 * can be set, which handles 16+1 virtual paths in an 'n-hot' 5710 * basis. VPATH 0 is the MSbit. 5711 * 5712 * Read from the RTS table 5713 * 5714 */ 5715vxge_hal_status_e 5716__hal_mrpcim_rts_table_access( 5717 vxge_hal_device_h devh, 5718 u32 action, 5719 u32 rts_table, 5720 u32 offset, 5721 u64 *data1, 5722 u64 *data2, 5723 u64 *vpath_vector) 5724{ 5725 u64 val64; 5726 __hal_device_t *hldev; 5727 vxge_hal_status_e status = VXGE_HAL_OK; 5728 5729 vxge_assert((devh != NULL) && (data1 != NULL) && 5730 (data2 != NULL) && (vpath_vector != NULL)); 5731 5732 hldev = (__hal_device_t *) devh; 5733 5734 vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 5735 __FILE__, __func__, __LINE__); 5736 5737 vxge_hal_trace_log_mrpcim( 5738 "devh = 0x"VXGE_OS_STXFMT", action = %d, rts_table = %d, " 5739 "offset = %d, data1 = 0x"VXGE_OS_STXFMT", " 5740 "data2 = 0x"VXGE_OS_STXFMT", vpath_vector = 0x"VXGE_OS_STXFMT, 5741 (ptr_t) devh, action, rts_table, offset, (ptr_t) data1, 5742 (ptr_t) data2, (ptr_t) vpath_vector); 5743 5744 val64 = VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL(rts_table) | 5745 VXGE_HAL_RTS_MGR_STEER_CTRL_STROBE | 5746 VXGE_HAL_RTS_MGR_STEER_CTRL_OFFSET(offset); 5747 5748 if (action == VXGE_HAL_RTS_MGR_STEER_CTRL_WE_WRITE) 5749 val64 = VXGE_HAL_RTS_MGR_STEER_CTRL_WE; 5750 5751 if ((rts_table == 5752 VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT) || 5753 (rts_table == 5754 VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT) || 5755 (rts_table == 5756 VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK) || 5757 (rts_table == 5758 VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY)) { 5759 val64 |= VXGE_HAL_RTS_MGR_STEER_CTRL_TABLE_SEL; 5760 } 5761 5762 vxge_hal_pio_mem_write32_lower(hldev->header.pdev, 5763 hldev->header.regh0, 5764 (u32) bVAL32(val64, 32), 5765 &hldev->mrpcim_reg->rts_mgr_steer_ctrl); 5766 5767 vxge_os_wmb(); 5768 5769 vxge_hal_pio_mem_write32_upper(hldev->header.pdev, 5770 hldev->header.regh0, 5771 (u32) bVAL32(val64, 0), 5772 &hldev->mrpcim_reg->rts_mgr_steer_ctrl); 5773 5774 vxge_os_wmb(); 5775 5776 status = vxge_hal_device_register_poll( 5777 hldev->header.pdev, 5778 hldev->header.regh0, 5779 &hldev->mrpcim_reg->rts_mgr_steer_ctrl, 0, 5780 VXGE_HAL_RTS_MGR_STEER_CTRL_STROBE, 5781 WAIT_FACTOR * hldev->header.config.device_poll_millis); 5782 5783 if (status != VXGE_HAL_OK) { 5784 5785 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 5786 __FILE__, __func__, __LINE__, status); 5787 return (status); 5788 } 5789 5790 val64 = vxge_os_pio_mem_read64( 5791 hldev->header.pdev, 5792 hldev->header.regh0, 5793 &hldev->mrpcim_reg->rts_mgr_steer_ctrl); 5794 5795 if ((val64 & VXGE_HAL_RTS_MGR_STEER_CTRL_RMACJ_STATUS) && 5796 (action == VXGE_HAL_RTS_MGR_STEER_CTRL_WE_READ)) { 5797 5798 *data1 = vxge_os_pio_mem_read64( 5799 hldev->header.pdev, 5800 hldev->header.regh0, 5801 &hldev->mrpcim_reg->rts_mgr_steer_data0); 5802 5803 *data2 = vxge_os_pio_mem_read64( 5804 hldev->header.pdev, 5805 hldev->header.regh0, 5806 &hldev->mrpcim_reg->rts_mgr_steer_data1); 5807 5808 *vpath_vector = vxge_os_pio_mem_read64( 5809 hldev->header.pdev, 5810 hldev->header.regh0, 5811 &hldev->mrpcim_reg->rts_mgr_steer_vpath_vector); 5812 5813 status = VXGE_HAL_OK; 5814 5815 } else { 5816 status = VXGE_HAL_FAIL; 5817 } 5818 5819 5820 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 5821 __FILE__, __func__, __LINE__, 5822 status); 5823 return (status); 5824} 5825 5826/* 5827 * vxge_hal_mrpcim_mac_addr_add - Add the mac address entry 5828 * into MAC address table. 5829 * @devh: Device handle. 5830 * @offset: Index into the DA table to add the mac address. 5831 * @macaddr: MAC address to be added for this vpath into the list 5832 * @macaddr_mask: MAC address mask for macaddr 5833 * @vpath_vector: Bit mask specifying the vpaths to which 5834 * the mac address applies 5835 * @duplicate_mode: Duplicate MAC address add mode. Please see 5836 * vxge_hal_vpath_mac_addr_add_mode_e {} 5837 * 5838 * Adds the given mac address, mac address mask and vpath vector into the list 5839 * 5840 * see also: vxge_hal_mrpcim_mac_addr_get 5841 * 5842 */ 5843vxge_hal_status_e 5844vxge_hal_mrpcim_mac_addr_add( 5845 vxge_hal_device_h devh, 5846 u32 offset, 5847 macaddr_t macaddr, 5848 macaddr_t macaddr_mask, 5849 u64 vpath_vector, 5850 u32 duplicate_mode) 5851{ 5852 u32 i; 5853 u64 data1 = 0ULL; 5854 u64 data2 = 0ULL; 5855 __hal_device_t *hldev; 5856 vxge_hal_status_e status = VXGE_HAL_OK; 5857 5858 vxge_assert(devh != NULL); 5859 5860 hldev = (__hal_device_t *) devh; 5861 5862 vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 5863 __FILE__, __func__, __LINE__); 5864 5865 vxge_hal_trace_log_mrpcim( 5866 "devh = 0x"VXGE_OS_STXFMT", offset = %d, " 5867 "macaddr = %02x-%02x-%02x-%02x-%02x-%02x, " 5868 "macaddr_mask = %02x-%02x-%02x-%02x-%02x-%02x, " 5869 "vpath_vector = 0x"VXGE_OS_LLXFMT, 5870 (ptr_t) devh, offset, macaddr[0], macaddr[1], macaddr[2], 5871 macaddr[3], macaddr[4], macaddr[5], macaddr_mask[0], 5872 macaddr_mask[1], macaddr_mask[2], macaddr_mask[3], 5873 macaddr_mask[4], macaddr_mask[5], vpath_vector); 5874 5875 for (i = 0; i < VXGE_HAL_ETH_ALEN; i++) { 5876 data1 <<= 8; 5877 data1 |= (u8) macaddr[i]; 5878 } 5879 5880 data1 = VXGE_HAL_RTS_MGR_STEER_DATA0_DA_MAC_ADDR(data1); 5881 5882 for (i = 0; i < VXGE_HAL_ETH_ALEN; i++) { 5883 data2 <<= 8; 5884 data2 |= (u8) macaddr_mask[i]; 5885 } 5886 5887 switch (duplicate_mode) { 5888 case VXGE_HAL_VPATH_MAC_ADDR_ADD_DUPLICATE: 5889 i = 0; 5890 break; 5891 case VXGE_HAL_VPATH_MAC_ADDR_DISCARD_DUPLICATE: 5892 i = 1; 5893 break; 5894 case VXGE_HAL_VPATH_MAC_ADDR_REPLACE_DUPLICATE: 5895 i = 2; 5896 break; 5897 default: 5898 i = 0; 5899 break; 5900 } 5901 5902 data2 = VXGE_HAL_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MASK(data2) | 5903 VXGE_HAL_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MODE(i); 5904 5905 status = __hal_mrpcim_rts_table_access(devh, 5906 VXGE_HAL_RTS_MGR_STEER_CTRL_WE_WRITE, 5907 VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_DA, 5908 offset, 5909 &data1, 5910 &data2, 5911 &vpath_vector); 5912 5913 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 5914 __FILE__, __func__, __LINE__, status); 5915 5916 return (status); 5917} 5918 5919/* 5920 * vxge_hal_mrpcim_mac_addr_get - Read the mac address entry into 5921 * MAC address table. 5922 * @devh: Device handle. 5923 * @offset: Index into the DA table to execute the command on. 5924 * @macaddr: Buffer to return MAC address to be added for this vpath 5925 * into the list 5926 * @macaddr_mask: Buffer to return MAC address mask for macaddr 5927 * @vpath_vector: Buffer to return Bit mask specifying the vpaths 5928 * to which the mac address applies 5929 * 5930 * Reads the mac address, mac address mask and vpath vector from 5931 * the given offset 5932 * 5933 * see also: vxge_hal_mrpcim_mac_addr_add 5934 * 5935 */ 5936vxge_hal_status_e 5937vxge_hal_mrpcim_mac_addr_get( 5938 vxge_hal_device_h devh, 5939 u32 offset, 5940 macaddr_t macaddr, 5941 macaddr_t macaddr_mask, 5942 u64 *vpath_vector) 5943{ 5944 u32 i; 5945 u64 data1 = 0ULL; 5946 u64 data2 = 0ULL; 5947 __hal_device_t *hldev; 5948 vxge_hal_status_e status = VXGE_HAL_OK; 5949 5950 vxge_assert(devh != NULL); 5951 5952 hldev = (__hal_device_t *) devh; 5953 5954 vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 5955 __FILE__, __func__, __LINE__); 5956 5957 vxge_hal_trace_log_mrpcim("hldev = 0x"VXGE_OS_STXFMT, 5958 (ptr_t) hldev); 5959 5960 status = __hal_mrpcim_rts_table_access(devh, 5961 VXGE_HAL_RTS_MGR_STEER_CTRL_WE_WRITE, 5962 VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_DA, 5963 offset, 5964 &data1, 5965 &data2, 5966 vpath_vector); 5967 5968 if (status != VXGE_HAL_OK) { 5969 5970 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 5971 __FILE__, __func__, __LINE__, status); 5972 return (status); 5973 } 5974 5975 data1 = VXGE_HAL_RTS_MGR_STEER_DATA0_GET_DA_MAC_ADDR(data1); 5976 5977 data2 = VXGE_HAL_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_MASK(data2); 5978 5979 for (i = VXGE_HAL_ETH_ALEN; i > 0; i--) { 5980 macaddr[i - 1] = (u8) (data1 & 0xFF); 5981 data1 >>= 8; 5982 } 5983 5984 for (i = VXGE_HAL_ETH_ALEN; i > 0; i--) { 5985 macaddr_mask[i - 1] = (u8) (data2 & 0xFF); 5986 data2 >>= 8; 5987 } 5988 5989 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 5990 __FILE__, __func__, __LINE__, status); 5991 5992 return (status); 5993} 5994 5995/* 5996 * vxge_hal_mrpcim_strip_repl_vlan_tag_enable - Enable strip Repl vlan tag. 5997 * @devh: Device handle. 5998 * 5999 * Enable X3100 strip Repl vlan tag. 6000 * Returns: VXGE_HAL_OK on success. 6001 * 6002 */ 6003vxge_hal_status_e 6004vxge_hal_mrpcim_strip_repl_vlan_tag_enable( 6005 vxge_hal_device_h devh) 6006{ 6007 u64 val64; 6008 __hal_device_t *hldev = (__hal_device_t *) devh; 6009 6010 vxge_assert(hldev != NULL); 6011 6012 vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 6013 __FILE__, __func__, __LINE__); 6014 6015 vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT, 6016 (ptr_t) devh); 6017 6018 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 6019 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6020 __FILE__, __func__, __LINE__, 6021 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6022 6023 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6024 } 6025 6026 if (hldev->header.config.mrpcim_config.mac_config. 6027 rpa_repl_strip_vlan_tag == 6028 VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_ENABLE) { 6029 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0", 6030 __FILE__, __func__, __LINE__); 6031 return (VXGE_HAL_OK); 6032 } 6033 6034 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 6035 hldev->header.regh0, 6036 &hldev->mrpcim_reg->rxmac_rx_pa_cfg1); 6037 6038 val64 |= VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_STRIP_VLAN_TAG; 6039 6040 vxge_os_pio_mem_write64(hldev->header.pdev, 6041 hldev->header.regh0, 6042 val64, 6043 &hldev->mrpcim_reg->rxmac_rx_pa_cfg1); 6044 6045 hldev->header.config.mrpcim_config.mac_config.rpa_repl_strip_vlan_tag = 6046 VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_ENABLE; 6047 6048 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0", 6049 __FILE__, __func__, __LINE__); 6050 6051 return (VXGE_HAL_OK); 6052} 6053 6054/* 6055 * vxge_hal_mrpcim_strip_repl_vlan_tag_disable - Disable strip Repl vlan tag. 6056 * @devh: Device handle. 6057 * 6058 * Disable X3100 strip Repl vlan tag. 6059 * Returns: VXGE_HAL_OK on success. 6060 * 6061 */ 6062vxge_hal_status_e 6063vxge_hal_mrpcim_strip_repl_vlan_tag_disable( 6064 vxge_hal_device_h devh) 6065{ 6066 u64 val64; 6067 __hal_device_t *hldev = (__hal_device_t *) devh; 6068 6069 vxge_assert(hldev != NULL); 6070 6071 vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 6072 __FILE__, __func__, __LINE__); 6073 6074 vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT, 6075 (ptr_t) devh); 6076 6077 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 6078 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6079 __FILE__, __func__, __LINE__, 6080 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6081 6082 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6083 } 6084 6085 if (hldev->header.config.mrpcim_config.mac_config. 6086 rpa_repl_strip_vlan_tag == 6087 VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_DISABLE) { 6088 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0", 6089 __FILE__, __func__, __LINE__); 6090 return (VXGE_HAL_OK); 6091 } 6092 6093 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 6094 hldev->header.regh0, 6095 &hldev->mrpcim_reg->rxmac_rx_pa_cfg1); 6096 6097 val64 &= ~VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_STRIP_VLAN_TAG; 6098 6099 vxge_os_pio_mem_write64(hldev->header.pdev, 6100 hldev->header.regh0, 6101 val64, 6102 &hldev->mrpcim_reg->rxmac_rx_pa_cfg1); 6103 6104 hldev->header.config.mrpcim_config.mac_config.rpa_repl_strip_vlan_tag = 6105 VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_DISABLE; 6106 6107 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0", 6108 __FILE__, __func__, __LINE__); 6109 6110 return (VXGE_HAL_OK); 6111} 6112 6113/* 6114 * vxge_hal_mrpcim_lag_config_get - Get the LAG config. 6115 * @devh: Device handle. 6116 * @lconfig: LAG Configuration 6117 * 6118 * Returns the current LAG configuration. 6119 * Returns: VXGE_HAL_OK on success. 6120 * 6121 */ 6122vxge_hal_status_e 6123vxge_hal_mrpcim_lag_config_get( 6124 vxge_hal_device_h devh, 6125 vxge_hal_lag_config_t *lconfig) 6126{ 6127 __hal_device_t *hldev = (__hal_device_t *) devh; 6128 6129 vxge_assert(hldev != NULL); 6130 6131 vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 6132 __FILE__, __func__, __LINE__); 6133 6134 vxge_hal_trace_log_mrpcim( 6135 "devh = 0x"VXGE_OS_STXFMT", lconfig = 0x"VXGE_OS_STXFMT, 6136 (ptr_t) devh, (ptr_t) lconfig); 6137 6138 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 6139 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6140 __FILE__, __func__, __LINE__, 6141 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6142 6143 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6144 } 6145 6146 vxge_os_memcpy(lconfig, 6147 &hldev->header.config.mrpcim_config.lag_config, 6148 sizeof(vxge_hal_lag_config_t)); 6149 6150 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0", 6151 __FILE__, __func__, __LINE__); 6152 6153 return (VXGE_HAL_OK); 6154} 6155 6156/* 6157 * vxge_hal_mrpcim_lag_config_set - Set the LAG config. 6158 * @devh: Device handle. 6159 * @lconfig: LAG Configuration 6160 * 6161 * Sets the LAG configuration. 6162 * Returns: VXGE_HAL_OK on success. 6163 * 6164 */ 6165vxge_hal_status_e 6166vxge_hal_mrpcim_lag_config_set( 6167 vxge_hal_device_h devh, 6168 vxge_hal_lag_config_t *lconfig) 6169{ 6170 vxge_hal_status_e status; 6171 __hal_device_t *hldev = (__hal_device_t *) devh; 6172 6173 vxge_assert(hldev != NULL); 6174 6175 vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 6176 __FILE__, __func__, __LINE__); 6177 6178 vxge_hal_trace_log_mrpcim( 6179 "devh = 0x"VXGE_OS_STXFMT", lconfig = 0x"VXGE_OS_STXFMT, 6180 (ptr_t) devh, (ptr_t) lconfig); 6181 6182 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 6183 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6184 __FILE__, __func__, __LINE__, 6185 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6186 6187 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6188 } 6189 6190 status = __hal_device_lag_config_check(lconfig); 6191 6192 if (status != VXGE_HAL_OK) { 6193 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6194 __FILE__, __func__, __LINE__, status); 6195 return (status); 6196 } 6197 6198 vxge_os_memcpy(&hldev->header.config.mrpcim_config.lag_config, 6199 lconfig, 6200 sizeof(vxge_hal_lag_config_t)); 6201 6202 status = __hal_mrpcim_lag_configure(hldev); 6203 6204 if (status != VXGE_HAL_OK) { 6205 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6206 __FILE__, __func__, __LINE__, status); 6207 return (status); 6208 } 6209 6210 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = 0", 6211 __FILE__, __func__, __LINE__); 6212 6213 return (VXGE_HAL_OK); 6214} 6215 6216/* 6217 * vxge_hal_mrpcim_getpause_data -Pause frame frame generation and reception. 6218 * @devh: HAL device handle. 6219 * @port : Port number 0, 1, or 2 6220 * @tx : A field to return the pause generation capability of the NIC. 6221 * @rx : A field to return the pause reception capability of the NIC. 6222 * 6223 * Returns the Pause frame generation and reception capability of the NIC. 6224 * Return value: 6225 * status 6226 */ 6227vxge_hal_status_e 6228vxge_hal_mrpcim_getpause_data( 6229 vxge_hal_device_h devh, 6230 u32 port, 6231 u32 *tx, 6232 u32 *rx) 6233{ 6234 u64 val64; 6235 __hal_device_t *hldev = (__hal_device_t *) devh; 6236 6237 vxge_assert(devh != NULL); 6238 6239 vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 6240 __FILE__, __func__, __LINE__); 6241 6242 vxge_hal_trace_log_mrpcim( 6243 "devh = 0x"VXGE_OS_STXFMT", port = %d, tx = 0x"VXGE_OS_STXFMT", " 6244 "rx = 0x"VXGE_OS_STXFMT, (ptr_t) devh, port, (ptr_t) tx, 6245 (ptr_t) rx); 6246 6247 if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) { 6248 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 6249 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_DEVICE); 6250 return (VXGE_HAL_ERR_INVALID_DEVICE); 6251 } 6252 6253 if (port >= VXGE_HAL_MAC_MAX_PORTS) { 6254 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 6255 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_PORT); 6256 return (VXGE_HAL_ERR_INVALID_PORT); 6257 } 6258 6259 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 6260 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 6261 __FILE__, __func__, __LINE__, 6262 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6263 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6264 } 6265 6266 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, hldev->header.regh0, 6267 &hldev->mrpcim_reg->rxmac_pause_cfg_port[port]); 6268 6269 if (val64 & VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN) 6270 *tx = 1; 6271 6272 if (val64 & VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN) 6273 *rx = 1; 6274 6275 6276 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: 0", 6277 __FILE__, __func__, __LINE__); 6278 6279 return (VXGE_HAL_OK); 6280} 6281 6282/* 6283 * vxge_hal_mrpcim_setpause_data - set/reset pause frame generation. 6284 * @devh: HAL device handle. 6285 * @port : Port number 0, 1, or 2 6286 * @tx: A field that indicates the pause generation capability to be 6287 * set on the NIC. 6288 * @rx: A field that indicates the pause reception capability to be 6289 * set on the NIC. 6290 * 6291 * It can be used to set or reset Pause frame generation or reception 6292 * support of the NIC. 6293 * Return value: 6294 * int, returns 0 on Success 6295 */ 6296 6297vxge_hal_status_e 6298vxge_hal_mrpcim_setpause_data( 6299 vxge_hal_device_h devh, 6300 u32 port, 6301 u32 tx, 6302 u32 rx) 6303{ 6304 u64 val64; 6305 __hal_device_t *hldev = (__hal_device_t *) devh; 6306 6307 vxge_assert(devh != NULL); 6308 6309 vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 6310 __FILE__, __func__, __LINE__); 6311 6312 vxge_hal_trace_log_mrpcim( 6313 "devh = 0x"VXGE_OS_STXFMT", port = %d, tx = %d, rx = %d", 6314 (ptr_t) devh, port, tx, rx); 6315 6316 if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) { 6317 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 6318 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_DEVICE); 6319 return (VXGE_HAL_ERR_INVALID_DEVICE); 6320 } 6321 6322 if (port >= VXGE_HAL_MAC_MAX_PORTS) { 6323 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 6324 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_PORT); 6325 return (VXGE_HAL_ERR_INVALID_PORT); 6326 } 6327 6328 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 6329 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 6330 __FILE__, __func__, __LINE__, 6331 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6332 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6333 } 6334 6335 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, hldev->header.regh0, 6336 &hldev->mrpcim_reg->rxmac_pause_cfg_port[port]); 6337 if (tx) 6338 val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN; 6339 else 6340 val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN; 6341 if (rx) 6342 val64 |= VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN; 6343 else 6344 val64 &= ~VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN; 6345 6346 vxge_os_pio_mem_write64(hldev->header.pdev, hldev->header.regh0, 6347 val64, &hldev->mrpcim_reg->rxmac_pause_cfg_port[port]); 6348 6349 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: 0", 6350 __FILE__, __func__, __LINE__); 6351 return (VXGE_HAL_OK); 6352} 6353 6354/* 6355 * vxge_hal_mrpcim_bist_test - invokes the MemBist test of the card . 6356 * @devh: HAL device handle. 6357 * vxge_nic structure. 6358 * @data:variable that returns the result of each of the test conducted by 6359 * the driver. 6360 * 6361 * This invokes the MemBist test of the card. We give around 6362 * 2 secs time for the Test to complete. If it's still not complete 6363 * within this peiod, we consider that the test failed. 6364 * Return value: 6365 * 0 on success and -1 on failure. 6366 */ 6367vxge_hal_status_e 6368vxge_hal_mrpcim_bist_test(vxge_hal_device_h devh, u64 *data) 6369{ 6370 __hal_device_t *hldev = (__hal_device_t *) devh; 6371 u8 bist = 0; 6372 int retry = 0; 6373 vxge_hal_status_e status = VXGE_HAL_FAIL; 6374 6375 vxge_assert(devh != NULL); 6376 6377 vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 6378 __FILE__, __func__, __LINE__); 6379 6380 vxge_hal_trace_log_mrpcim("devh = 0x"VXGE_OS_STXFMT, 6381 (ptr_t)devh); 6382 6383 if (hldev->header.magic != VXGE_HAL_DEVICE_MAGIC) { 6384 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 6385 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_INVALID_DEVICE); 6386 return (VXGE_HAL_ERR_INVALID_DEVICE); 6387 } 6388 6389 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 6390 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 6391 __FILE__, __func__, __LINE__, 6392 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6393 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6394 } 6395 6396 (void) __hal_vpath_pci_read(hldev, 6397 hldev->first_vp_id, 6398 vxge_offsetof(vxge_hal_pci_config_le_t, bist), 6399 1, 6400 &bist); 6401 bist |= 0x40; 6402 vxge_os_pci_write8(hldev->header.pdev, hldev->header.cfgh, 6403 vxge_offsetof(vxge_hal_pci_config_le_t, bist), bist); 6404 6405 while (retry < 20) { 6406 (void) __hal_vpath_pci_read(hldev, 6407 hldev->first_vp_id, 6408 vxge_offsetof(vxge_hal_pci_config_le_t, bist), 6409 1, 6410 &bist); 6411 if (!(bist & 0x40)) { 6412 *data = (bist & 0x0f); 6413 status = VXGE_HAL_OK; 6414 break; 6415 } 6416 vxge_os_mdelay(100); 6417 retry++; 6418 } 6419 6420 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result: %d", 6421 __FILE__, __func__, __LINE__, status); 6422 return (status); 6423} 6424 6425/* 6426 * __hal_mrpcim_initialize - Initialize mrpcim 6427 * @hldev: hal device. 6428 * 6429 * Initializes mrpcim 6430 * 6431 * See also: __hal_mrpcim_terminate() 6432 */ 6433vxge_hal_status_e 6434__hal_mrpcim_initialize(__hal_device_t *hldev) 6435{ 6436 u64 val64; 6437 vxge_hal_status_e status = VXGE_HAL_OK; 6438 6439 vxge_assert(hldev != NULL); 6440 6441 vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 6442 __FILE__, __func__, __LINE__); 6443 6444 vxge_hal_trace_log_mrpcim("hldev = 0x"VXGE_OS_STXFMT, 6445 (ptr_t)hldev); 6446 6447 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM)) { 6448 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6449 __FILE__, __func__, __LINE__, 6450 VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6451 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION); 6452 } 6453 6454 hldev->mrpcim = (__hal_mrpcim_t *) 6455 vxge_os_malloc(hldev->header.pdev, sizeof(__hal_mrpcim_t)); 6456 6457 if (hldev->mrpcim == NULL) { 6458 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6459 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY); 6460 return (VXGE_HAL_ERR_OUT_OF_MEMORY); 6461 } 6462 6463 vxge_os_memzero(hldev->mrpcim, sizeof(__hal_mrpcim_t)); 6464 6465 __hal_mrpcim_get_vpd_data(hldev); 6466 6467 hldev->mrpcim->mrpcim_stats_block = 6468 __hal_blockpool_block_allocate(hldev, VXGE_OS_HOST_PAGE_SIZE); 6469 6470 if (hldev->mrpcim->mrpcim_stats_block == NULL) { 6471 6472 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6473 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY); 6474 6475 return (VXGE_HAL_ERR_OUT_OF_MEMORY); 6476 6477 } 6478 6479 hldev->mrpcim->mrpcim_stats = (vxge_hal_mrpcim_stats_hw_info_t *) 6480 hldev->mrpcim->mrpcim_stats_block->memblock; 6481 6482 vxge_os_memzero(hldev->mrpcim->mrpcim_stats, 6483 sizeof(vxge_hal_mrpcim_stats_hw_info_t)); 6484 6485 vxge_os_memzero(&hldev->mrpcim->mrpcim_stats_sav, 6486 sizeof(vxge_hal_mrpcim_stats_hw_info_t)); 6487 6488 status = __hal_mrpcim_mac_configure(hldev); 6489 6490 if (status != VXGE_HAL_OK) { 6491 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6492 __FILE__, __func__, __LINE__, status); 6493 return (status); 6494 } 6495 6496 status = __hal_mrpcim_lag_configure(hldev); 6497 6498 if (status != VXGE_HAL_OK) { 6499 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6500 __FILE__, __func__, __LINE__, status); 6501 return (status); 6502 } 6503 6504 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 6505 hldev->header.regh0, 6506 &hldev->mrpcim_reg->mdio_gen_cfg_port[0]); 6507 6508 hldev->mrpcim->mdio_phy_prtad0 = 6509 (u32) VXGE_HAL_MDIO_GEN_CFG_PORT_GET_MDIO_PHY_PRTAD(val64); 6510 6511 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 6512 hldev->header.regh0, 6513 &hldev->mrpcim_reg->mdio_gen_cfg_port[1]); 6514 6515 hldev->mrpcim->mdio_phy_prtad1 = 6516 (u32) VXGE_HAL_MDIO_GEN_CFG_PORT_GET_MDIO_PHY_PRTAD(val64); 6517 6518 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 6519 hldev->header.regh0, 6520 &hldev->mrpcim_reg->xgxs_static_cfg_port[0]); 6521 6522 hldev->mrpcim->mdio_dte_prtad0 = 6523 (u32) VXGE_HAL_XGXS_STATIC_CFG_PORT_GET_MDIO_DTE_PRTAD(val64); 6524 6525 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 6526 hldev->header.regh0, 6527 &hldev->mrpcim_reg->xgxs_static_cfg_port[1]); 6528 6529 hldev->mrpcim->mdio_dte_prtad1 = 6530 (u32) VXGE_HAL_XGXS_STATIC_CFG_PORT_GET_MDIO_DTE_PRTAD(val64); 6531 6532 vxge_os_pio_mem_write64(hldev->header.pdev, 6533 hldev->header.regh0, 6534 hldev->mrpcim->mrpcim_stats_block->dma_addr, 6535 &hldev->mrpcim_reg->mrpcim_stats_start_host_addr); 6536 6537 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 6538 hldev->header.regh0, 6539 &hldev->mrpcim_reg->mrpcim_general_cfg2); 6540 6541 val64 &= ~VXGE_HAL_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_MAP_TO_VPATH(0x1f); 6542 val64 |= VXGE_HAL_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_MAP_TO_VPATH( 6543 hldev->first_vp_id); 6544 6545 vxge_os_pio_mem_write64(hldev->header.pdev, 6546 hldev->header.regh0, 6547 val64, 6548 &hldev->mrpcim_reg->mrpcim_general_cfg2); 6549 6550 vxge_os_pio_mem_write64(hldev->header.pdev, 6551 hldev->header.regh0, 6552 vBIT(0xFFFFFFFFFFFFFFFFULL, 0, VXGE_HAL_MAX_VIRTUAL_PATHS), 6553 &hldev->mrpcim_reg->rxmac_authorize_all_addr); 6554 6555 vxge_os_pio_mem_write64(hldev->header.pdev, 6556 hldev->header.regh0, 6557 vBIT(0xFFFFFFFFFFFFFFFFULL, 0, VXGE_HAL_MAX_VIRTUAL_PATHS), 6558 &hldev->mrpcim_reg->rxmac_authorize_all_vid); 6559 6560 if (hldev->header.config.intr_mode == 6561 VXGE_HAL_INTR_MODE_EMULATED_INTA) { 6562 6563 val64 = vxge_os_pio_mem_read64(hldev->header.pdev, 6564 hldev->header.regh0, 6565 &hldev->mrpcim_reg->rdcrdtarb_cfg0); 6566 6567 /* Set MOST to 8 for HP-ISS platform */ 6568 val64 &= ~VXGE_HAL_RDCRDTARB_CFG0_MAX_OUTSTANDING_RDS(0x3f); 6569 6570 val64 |= VXGE_HAL_RDCRDTARB_CFG0_MAX_OUTSTANDING_RDS(8); 6571 6572 vxge_os_pio_mem_write64(hldev->header.pdev, 6573 hldev->header.regh0, 6574 val64, 6575 &hldev->mrpcim_reg->rdcrdtarb_cfg0); 6576 } 6577 6578 (void) __hal_ifmsg_wmsg_post(hldev, 6579 hldev->first_vp_id, 6580 VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_BROADCAST, 6581 VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_PRIV_DRIVER_UP, 6582 0); 6583 6584 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6585 __FILE__, __func__, __LINE__, status); 6586 return (status); 6587 6588} 6589 6590/* 6591 * __hal_mrpcim_terminate - Terminates mrpcim 6592 * @hldev: hal device. 6593 * 6594 * Terminates mrpcim. 6595 * 6596 * See also: __hal_mrpcim_initialize() 6597 */ 6598vxge_hal_status_e 6599__hal_mrpcim_terminate(__hal_device_t *hldev) 6600{ 6601 vxge_hal_device_h devh = (vxge_hal_device_h) hldev; 6602 vxge_hal_status_e status = VXGE_HAL_OK; 6603 6604 vxge_assert((hldev != NULL) && (hldev->mrpcim != NULL)); 6605 6606 vxge_hal_trace_log_mrpcim("==> %s:%s:%d", 6607 __FILE__, __func__, __LINE__); 6608 6609 vxge_hal_trace_log_mrpcim("hldev = 0x"VXGE_OS_STXFMT, 6610 (ptr_t) hldev); 6611 6612 if (hldev->mrpcim == NULL) { 6613 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6614 __FILE__, __func__, __LINE__, status); 6615 return (status); 6616 } 6617 6618 (void) __hal_ifmsg_wmsg_post(hldev, 6619 hldev->first_vp_id, 6620 VXGE_HAL_RTS_ACCESS_STEER_MSG_DEST_BROADCAST, 6621 VXGE_HAL_RTS_ACCESS_STEER_DATA0_MSG_TYPE_PRIV_DRIVER_DOWN, 6622 0); 6623 6624 if (hldev->mrpcim->mrpcim_stats_block != NULL) { 6625 __hal_blockpool_block_free(devh, 6626 hldev->mrpcim->mrpcim_stats_block); 6627 hldev->mrpcim->mrpcim_stats_block = NULL; 6628 } 6629 6630 vxge_os_free(hldev->header.pdev, 6631 hldev->mrpcim, sizeof(__hal_mrpcim_t)); 6632 6633 hldev->mrpcim = NULL; 6634 6635 vxge_hal_trace_log_mrpcim("<== %s:%s:%d Result = %d", 6636 __FILE__, __func__, __LINE__, status); 6637 return (status); 6638} 6639