1/*- 2 * Copyright(c) 2002-2011 Exar Corp. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification are permitted provided the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Exar Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31/*$FreeBSD$*/ 32 33#ifndef VXGE_HAL_MRPCIM_REGS_H 34#define VXGE_HAL_MRPCIM_REGS_H 35 36__EXTERN_BEGIN_DECLS 37 38typedef struct vxge_hal_mrpcim_reg_t { 39 40/* 0x00000 */ u64 g3fbct_int_status; 41#define VXGE_HAL_G3FBCT_INT_STATUS_ERR_G3IF_INT mBIT(0) 42/* 0x00008 */ u64 g3fbct_int_mask; 43/* 0x00010 */ u64 g3fbct_err_reg; 44#define VXGE_HAL_G3FBCT_ERR_REG_G3IF_SM_ERR mBIT(4) 45#define VXGE_HAL_G3FBCT_ERR_REG_G3IF_GDDR3_DECC mBIT(5) 46#define VXGE_HAL_G3FBCT_ERR_REG_G3IF_GDDR3_U_DECC mBIT(6) 47#define VXGE_HAL_G3FBCT_ERR_REG_G3IF_CTRL_FIFO_DECC mBIT(7) 48#define VXGE_HAL_G3FBCT_ERR_REG_G3IF_GDDR3_SECC mBIT(29) 49#define VXGE_HAL_G3FBCT_ERR_REG_G3IF_GDDR3_U_SECC mBIT(30) 50#define VXGE_HAL_G3FBCT_ERR_REG_G3IF_CTRL_FIFO_SECC mBIT(31) 51/* 0x00018 */ u64 g3fbct_err_mask; 52/* 0x00020 */ u64 g3fbct_err_alarm; 53/* 0x00028 */ u64 g3fbct_config0; 54#define VXGE_HAL_G3FBCT_CONFIG0_RD_CMD_LATENCY_RPATH(val) vBIT(val, 5, 3) 55#define VXGE_HAL_G3FBCT_CONFIG0_RD_CMD_LATENCY(val) vBIT(val, 13, 3) 56#define VXGE_HAL_G3FBCT_CONFIG0_REFRESH_PER(val) vBIT(val, 16, 16) 57#define VXGE_HAL_G3FBCT_CONFIG0_TRC(val) vBIT(val, 35, 5) 58#define VXGE_HAL_G3FBCT_CONFIG0_TRRD(val) vBIT(val, 44, 4) 59#define VXGE_HAL_G3FBCT_CONFIG0_TFAW(val) vBIT(val, 50, 6) 60#define VXGE_HAL_G3FBCT_CONFIG0_RD_FIFO_THR(val) vBIT(val, 58, 6) 61/* 0x00030 */ u64 g3fbct_config1; 62#define VXGE_HAL_G3FBCT_CONFIG1_BIC_THR(val) vBIT(val, 3, 5) 63#define VXGE_HAL_G3FBCT_CONFIG1_BIC_OFF mBIT(15) 64#define VXGE_HAL_G3FBCT_CONFIG1_IGNORE_BEM mBIT(23) 65#define VXGE_HAL_G3FBCT_CONFIG1_RD_SAMPLING(val) vBIT(val, 29, 3) 66#define VXGE_HAL_G3FBCT_CONFIG1_CMD_START_PHASE mBIT(39) 67#define VXGE_HAL_G3FBCT_CONFIG1_BIC_HI_THR(val) vBIT(val, 43, 5) 68#define VXGE_HAL_G3FBCT_CONFIG1_BIC_MODE(val) vBIT(val, 54, 2) 69#define VXGE_HAL_G3FBCT_CONFIG1_ECC_ENABLE(val) vBIT(val, 57, 7) 70/* 0x00038 */ u64 g3fbct_config2; 71#define VXGE_HAL_G3FBCT_CONFIG2_DEV_USE_ENABLE(val) vBIT(val, 6, 2) 72#define VXGE_HAL_G3FBCT_CONFIG2_DEV_USE_VALUE(val) vBIT(val, 9, 7) 73#define VXGE_HAL_G3FBCT_CONFIG2_ARBITER_CTRL(val) vBIT(val, 22, 2) 74#define VXGE_HAL_G3FBCT_CONFIG2_DEFINE_CAD mBIT(31) 75#define VXGE_HAL_G3FBCT_CONFIG2_DEFINE_NOP_AD mBIT(39) 76#define VXGE_HAL_G3FBCT_CONFIG2_LAST_CADD(val) vBIT(val, 43, 13) 77/* 0x00040 */ u64 g3fbct_init0; 78#define VXGE_HAL_G3FBCT_INIT0_MRS_BAD(val) vBIT(val, 5, 3) 79#define VXGE_HAL_G3FBCT_INIT0_MRS_WL(val) vBIT(val, 13, 3) 80#define VXGE_HAL_G3FBCT_INIT0_MRS_DLL mBIT(23) 81#define VXGE_HAL_G3FBCT_INIT0_MRS_TM mBIT(39) 82#define VXGE_HAL_G3FBCT_INIT0_MRS_CL(val) vBIT(val, 44, 4) 83#define VXGE_HAL_G3FBCT_INIT0_MRS_BT mBIT(55) 84#define VXGE_HAL_G3FBCT_INIT0_MRS_BL(val) vBIT(val, 62, 2) 85/* 0x00048 */ u64 g3fbct_init1; 86#define VXGE_HAL_G3FBCT_INIT1_EMRS_BAD(val) vBIT(val, 5, 3) 87#define VXGE_HAL_G3FBCT_INIT1_EMRS_AD_TER mBIT(15) 88#define VXGE_HAL_G3FBCT_INIT1_EMRS_ID mBIT(23) 89#define VXGE_HAL_G3FBCT_INIT1_EMRS_RON mBIT(39) 90#define VXGE_HAL_G3FBCT_INIT1_EMRS_AL mBIT(47) 91#define VXGE_HAL_G3FBCT_INIT1_EMRS_TWR(val) vBIT(val, 53, 3) 92#define VXGE_HAL_G3FBCT_INIT1_EMRS_DQ_TER(val) vBIT(val, 62, 2) 93/* 0x00050 */ u64 g3fbct_init2; 94#define VXGE_HAL_G3FBCT_INIT2_EMRS_DR_STR(val) vBIT(val, 6, 2) 95#define VXGE_HAL_G3FBCT_INIT2_START_INI mBIT(15) 96#define VXGE_HAL_G3FBCT_INIT2_POWER_UP_DELAY(val) vBIT(val, 16, 24) 97#define VXGE_HAL_G3FBCT_INIT2_ACTIVE_CMD_DELAY(val) vBIT(val, 40, 24) 98/* 0x00058 */ u64 g3fbct_init3; 99#define VXGE_HAL_G3FBCT_INIT3_TRP_DELAY(val) vBIT(val, 0, 8) 100#define VXGE_HAL_G3FBCT_INIT3_TMRD_DELAY(val) vBIT(val, 8, 8) 101#define VXGE_HAL_G3FBCT_INIT3_TWR2PRE_DELAY(val) vBIT(val, 16, 8) 102#define VXGE_HAL_G3FBCT_INIT3_TRD2PRE_DELAY(val) vBIT(val, 24, 8) 103#define VXGE_HAL_G3FBCT_INIT3_TRCDR_DELAY(val) vBIT(val, 32, 8) 104#define VXGE_HAL_G3FBCT_INIT3_TRCDW_DELAY(val) vBIT(val, 40, 8) 105#define VXGE_HAL_G3FBCT_INIT3_TWR2RD_DELAY(val) vBIT(val, 48, 8) 106#define VXGE_HAL_G3FBCT_INIT3_TRD2WR_DELAY(val) vBIT(val, 56, 8) 107/* 0x00060 */ u64 g3fbct_init4; 108#define VXGE_HAL_G3FBCT_INIT4_TRFC_DELAY(val) vBIT(val, 0, 8) 109#define VXGE_HAL_G3FBCT_INIT4_REFRESH_BURSTS(val) vBIT(val, 12, 4) 110#define VXGE_HAL_G3FBCT_INIT4_CKE_INIT_VAL mBIT(31) 111#define VXGE_HAL_G3FBCT_INIT4_VENDOR_ID(val) vBIT(val, 32, 8) 112#define VXGE_HAL_G3FBCT_INIT4_OOO_DEPTH(val) vBIT(val, 42, 6) 113#define VXGE_HAL_G3FBCT_INIT4_ICTRL_INIT_DONE mBIT(55) 114#define VXGE_HAL_G3FBCT_INIT4_IOCAL_WAIT_DISABLE mBIT(63) 115/* 0x00068 */ u64 g3fbct_init5; 116#define VXGE_HAL_G3FBCT_INIT5_TRAS_DELAY(val) vBIT(val, 3, 5) 117#define VXGE_HAL_G3FBCT_INIT5_TVID_DELAY(val) vBIT(val, 8, 8) 118#define VXGE_HAL_G3FBCT_INIT5_TWR_APRE2CMD(val) vBIT(val, 16, 8) 119#define VXGE_HAL_G3FBCT_INIT5_TRD_APRE2CMD(val) vBIT(val, 24, 8) 120#define VXGE_HAL_G3FBCT_INIT5_TWR_APRE2CMD_CON(val) vBIT(val, 32, 8) 121#define VXGE_HAL_G3FBCT_INIT5_GDDR3_DLL_DELAY(val) vBIT(val, 40, 24) 122/* 0x00070 */ u64 g3fbct_dll_training1; 123#define VXGE_HAL_G3FBCT_DLL_TRAINING1_DLL_TRA_DATA00(val) vBIT(val, 0, 64) 124/* 0x00078 */ u64 g3fbct_dll_training2; 125#define VXGE_HAL_G3FBCT_DLL_TRAINING2_DLL_TRA_DATA01(val) vBIT(val, 0, 64) 126/* 0x00080 */ u64 g3fbct_dll_training3; 127#define VXGE_HAL_G3FBCT_DLL_TRAINING3_DLL_TRA_DATA10(val) vBIT(val, 0, 64) 128/* 0x00088 */ u64 g3fbct_dll_training4; 129#define VXGE_HAL_G3FBCT_DLL_TRAINING4_DLL_TRA_DATA11(val) vBIT(val, 0, 64) 130/* 0x00090 */ u64 g3fbct_dll_training6; 131#define VXGE_HAL_G3FBCT_DLL_TRAINING6_DLL_TRA_DATA20(val) vBIT(val, 0, 64) 132/* 0x00098 */ u64 g3fbct_dll_training7; 133#define VXGE_HAL_G3FBCT_DLL_TRAINING7_DLL_TRA_DATA21(val) vBIT(val, 0, 64) 134/* 0x000a0 */ u64 g3fbct_dll_training8; 135#define VXGE_HAL_G3FBCT_DLL_TRAINING8_DLL_TRA_DATA30(val) vBIT(val, 0, 64) 136/* 0x000a8 */ u64 g3fbct_dll_training9; 137#define VXGE_HAL_G3FBCT_DLL_TRAINING9_DLL_TRA_DATA31(val) vBIT(val, 0, 64) 138/* 0x000b0 */ u64 g3fbct_dll_training5; 139#define VXGE_HAL_G3FBCT_DLL_TRAINING5_DLL_TRA_RADD(val) vBIT(val, 2, 14) 140#define VXGE_HAL_G3FBCT_DLL_TRAINING5_DLL_TRA_CADD0(val) vBIT(val, 21, 11) 141#define VXGE_HAL_G3FBCT_DLL_TRAINING5_DLL_TRA_CADD1(val) vBIT(val, 37, 11) 142/* 0x000b8 */ u64 g3fbct_dll_training10; 143#define VXGE_HAL_G3FBCT_DLL_TRAINING10_DLL_TP_READS(val) vBIT(val, 4, 4) 144#define VXGE_HAL_G3FBCT_DLL_TRAINING10_DLL_SAMPLES(val) vBIT(val, 8, 8) 145#define VXGE_HAL_G3FBCT_DLL_TRAINING10_TRA_LOOPS(val) vBIT(val, 18, 14) 146#define VXGE_HAL_G3FBCT_DLL_TRAINING10_TRA_PASS_CNT(val) vBIT(val, 33, 7) 147#define VXGE_HAL_G3FBCT_DLL_TRAINING10_TRA_STEP(val) vBIT(val, 41, 7) 148/* 0x000c0 */ u64 g3fbct_dll_training11; 149#define VXGE_HAL_G3FBCT_DLL_TRAINING11_ICTRL_DLL_TRA_CNT(val) vBIT(val, 0, 48) 150#define VXGE_HAL_G3FBCT_DLL_TRAINING11_ICTRL_DLL_TRA_DIS(val) vBIT(val, 54, 2) 151/* 0x000c8 */ u64 g3fbct_init6; 152#define VXGE_HAL_G3FBCT_INIT6_TWR_APRE2RD_DELAY(val) vBIT(val, 4, 4) 153#define VXGE_HAL_G3FBCT_INIT6_TWR_APRE2WR_DELAY(val) vBIT(val, 12, 4) 154#define VXGE_HAL_G3FBCT_INIT6_TWR_APRE2PRE_DELAY(val) vBIT(val, 20, 4) 155#define VXGE_HAL_G3FBCT_INIT6_TWR_APRE2ACT_DELAY(val) vBIT(val, 28, 4) 156#define VXGE_HAL_G3FBCT_INIT6_TRD_APRE2RD_DELAY(val) vBIT(val, 36, 4) 157#define VXGE_HAL_G3FBCT_INIT6_TRD_APRE2WR_DELAY(val) vBIT(val, 44, 4) 158#define VXGE_HAL_G3FBCT_INIT6_TRD_APRE2PRE_DELAY(val) vBIT(val, 52, 4) 159#define VXGE_HAL_G3FBCT_INIT6_TRD_APRE2ACT_DELAY(val) vBIT(val, 60, 4) 160/* 0x000d0 */ u64 g3fbct_test0; 161#define VXGE_HAL_G3FBCT_TEST0_TEST_START_RADD(val) vBIT(val, 2, 14) 162#define VXGE_HAL_G3FBCT_TEST0_TEST_END_RADD(val) vBIT(val, 18, 14) 163#define VXGE_HAL_G3FBCT_TEST0_TEST_START_CADD(val) vBIT(val, 37, 11) 164#define VXGE_HAL_G3FBCT_TEST0_TEST_END_CADD(val) vBIT(val, 53, 11) 165/* 0x000d8 */ u64 g3fbct_test01; 166#define VXGE_HAL_G3FBCT_TEST01_TEST_BANK(val) vBIT(val, 0, 8) 167#define VXGE_HAL_G3FBCT_TEST01_TEST_CTRL(val) vBIT(val, 12, 4) 168#define VXGE_HAL_G3FBCT_TEST01_TEST_MODE mBIT(23) 169#define VXGE_HAL_G3FBCT_TEST01_TEST_GO mBIT(31) 170#define VXGE_HAL_G3FBCT_TEST01_TEST_DONE mBIT(39) 171#define VXGE_HAL_G3FBCT_TEST01_ECC_DEC_TEST_FAIL_CNTR(val) vBIT(val, 40, 16) 172#define VXGE_HAL_G3FBCT_TEST01_TEST_DATA_ADDR mBIT(63) 173/* 0x000e0 */ u64 g3fbct_test1; 174#define VXGE_HAL_G3FBCT_TEST1_TX_TEST_DATA(val) vBIT(val, 0, 64) 175/* 0x000e8 */ u64 g3fbct_test2; 176#define VXGE_HAL_G3FBCT_TEST2_TX_TEST_DATA(val) vBIT(val, 0, 64) 177/* 0x000f0 */ u64 g3fbct_test11; 178#define VXGE_HAL_G3FBCT_TEST11_TX_TEST_DATA1(val) vBIT(val, 0, 64) 179/* 0x000f8 */ u64 g3fbct_test21; 180#define VXGE_HAL_G3FBCT_TEST21_TX_TEST_DATA1(val) vBIT(val, 0, 64) 181/* 0x00100 */ u64 g3fbct_test3; 182#define VXGE_HAL_G3FBCT_TEST3_ECC_DEC_RX_TEST_DATA(val) vBIT(val, 0, 64) 183/* 0x00108 */ u64 g3fbct_test4; 184#define VXGE_HAL_G3FBCT_TEST4_ECC_DEC_RX_TEST_DATA(val) vBIT(val, 0, 64) 185/* 0x00110 */ u64 g3fbct_test31; 186#define VXGE_HAL_G3FBCT_TEST31_ECC_DEC_RX_TEST_DATA1(val) vBIT(val, 0, 64) 187/* 0x00118 */ u64 g3fbct_test41; 188#define VXGE_HAL_G3FBCT_TEST41_ECC_DEC_RX_TEST_DATA1(val) vBIT(val, 0, 64) 189/* 0x00120 */ u64 g3fbct_test5; 190#define VXGE_HAL_G3FBCT_TEST5_ECC_DEC_RX_FAILED_TEST_DATA(val) vBIT(val, 0, 64) 191/* 0x00128 */ u64 g3fbct_test6; 192#define VXGE_HAL_G3FBCT_TEST6_ECC_DEC_RX_FAILED_TEST_DATA(val) vBIT(val, 0, 64) 193/* 0x00130 */ u64 g3fbct_test51; 194#define VXGE_HAL_G3FBCT_TEST51_ECC_DEC_RX_FAILED_TEST_DATA1(val)\ 195 vBIT(val, 0, 64) 196/* 0x00138 */ u64 g3fbct_test61; 197#define VXGE_HAL_G3FBCT_TEST61_ECC_DEC_RX_FAILED_TEST_DATA1(val)\ 198 vBIT(val, 0, 64) 199/* 0x00140 */ u64 g3fbct_test7; 200#define VXGE_HAL_G3FBCT_TEST7_ECC_DEC_TEST_FAILED_RADD(val) vBIT(val, 0, 14) 201#define VXGE_HAL_G3FBCT_TEST7_ECC_DEC_TEST_FAILED_CADD(val) vBIT(val, 19, 11) 202#define VXGE_HAL_G3FBCT_TEST7_ECC_DEC_TEST_FAILED_BANK(val) vBIT(val, 32, 8) 203/* 0x00148 */ u64 g3fbct_test71; 204#define VXGE_HAL_G3FBCT_TEST71_ECC_DEC_TEST_FAILED_RADD1(val) vBIT(val, 0, 14) 205#define VXGE_HAL_G3FBCT_TEST71_ECC_DEC_TEST_FAILED_CADD1(val) vBIT(val, 19, 11) 206#define VXGE_HAL_G3FBCT_TEST71_ECC_DEC_TEST_FAILED_BANK1(val) vBIT(val, 32, 8) 207 u8 unused001b0[0x001b0 - 0x00150]; 208 209/* 0x001b0 */ u64 g3fbct_loop_back; 210#define VXGE_HAL_G3FBCT_LOOP_BACK_TDATA(val) vBIT(val, 0, 32) 211#define VXGE_HAL_G3FBCT_LOOP_BACK_MODE mBIT(39) 212#define VXGE_HAL_G3FBCT_LOOP_BACK_GO mBIT(47) 213#define VXGE_HAL_G3FBCT_LOOP_BACK_DONE mBIT(55) 214#define VXGE_HAL_G3FBCT_LOOP_BACK_RDLL_IDLE_VAL(val) vBIT(val, 56, 8) 215/* 0x001b8 */ u64 g3fbct_loop_back1; 216#define VXGE_HAL_G3FBCT_LOOP_BACK1_RDLL_START_VAL(val) vBIT(val, 1, 7) 217#define VXGE_HAL_G3FBCT_LOOP_BACK1_RDLL_END_VAL(val) vBIT(val, 9, 7) 218#define VXGE_HAL_G3FBCT_LOOP_BACK1_WDLL_IDLE_VAL(val) vBIT(val, 16, 8) 219#define VXGE_HAL_G3FBCT_LOOP_BACK1_WDLL_START_VAL(val) vBIT(val, 25, 7) 220#define VXGE_HAL_G3FBCT_LOOP_BACK1_WDLL_END_VAL(val) vBIT(val, 33, 7) 221#define VXGE_HAL_G3FBCT_LOOP_BACK1_STEPS(val) vBIT(val, 45, 3) 222#define VXGE_HAL_G3FBCT_LOOP_BACK1_RDLL_MIN_FILTER(val) vBIT(val, 49, 7) 223#define VXGE_HAL_G3FBCT_LOOP_BACK1_RDLL_MAX_FILTER(val) vBIT(val, 57, 7) 224/* 0x001c0 */ u64 g3fbct_loop_back2; 225#define VXGE_HAL_G3FBCT_LOOP_BACK2_WDLL_MIN_FILTER(val) vBIT(val, 1, 7) 226#define VXGE_HAL_G3FBCT_LOOP_BACK2_WDLL_MAX_FILTER(val) vBIT(val, 9, 7) 227/* 0x001c8 */ u64 g3fbct_loop_back3; 228#define VXGE_HAL_G3FBCT_LOOP_BACK3_LBCTRL_CM_RDLL_RESULT(val) vBIT(val, 0, 8) 229#define VXGE_HAL_G3FBCT_LOOP_BACK3_LBCTRL_CM_WDLL_RESULT(val) vBIT(val, 8, 8) 230#define VXGE_HAL_G3FBCT_LOOP_BACK3_LBCTRL_CM_RDLL_MON_RESULT(val)\ 231 vBIT(val, 16, 8) 232/* 0x001d0 */ u64 g3fbct_loop_back4; 233#define VXGE_HAL_G3FBCT_LOOP_BACK4_LBCTRL_IO_PASS_FAILN(val) vBIT(val, 0, 32) 234/* 0x001d8 */ u64 g3fbct_loop_back5; 235#define VXGE_HAL_G3FBCT_LOOP_BACK5_RDLL_START_IO_VAL(val) vBIT(val, 1, 7) 236#define VXGE_HAL_G3FBCT_LOOP_BACK5_RDLL_END_IO_VAL(val) vBIT(val, 9, 7) 237 u8 unused00200[0x00200 - 0x001e0]; 238 239/* 0x00200 */ u64 g3fbct_loop_back_rdll[4]; 240#define VXGE_HAL_G3FBCT_LOOP_BACK_RDLL_LBCTRL_MIN_VAL(val) vBIT(val, 1, 7) 241#define VXGE_HAL_G3FBCT_LOOP_BACK_RDLL_LBCTRL_MAX_VAL(val) vBIT(val, 9, 7) 242#define VXGE_HAL_G3FBCT_LOOP_BACK_RDLL_LBCTRL_MON_MIN_VAL(val) vBIT(val, 17, 7) 243#define VXGE_HAL_G3FBCT_LOOP_BACK_RDLL_LBCTRL_MON_MAX_VAL(val) vBIT(val, 25, 7) 244/* 0x00220 */ u64 g3fbct_loop_back_wdll[4]; 245#define VXGE_HAL_G3FBCT_LOOP_BACK_WDLL_LBCTRL_MIN_VAL(val) vBIT(val, 1, 7) 246#define VXGE_HAL_G3FBCT_LOOP_BACK_WDLL_LBCTRL_MAX_VAL(val) vBIT(val, 9, 7) 247/* 0x00240 */ u64 g3fbct_tran_wrd_cnt; 248#define VXGE_HAL_G3FBCT_TRAN_WRD_CNT_CTRL_PIPE_WR(val) vBIT(val, 0, 32) 249#define VXGE_HAL_G3FBCT_TRAN_WRD_CNT_CTRL_PIPE_RD(val) vBIT(val, 32, 32) 250/* 0x00248 */ u64 g3fbct_tran_ap_cnt; 251#define VXGE_HAL_G3FBCT_TRAN_AP_CNT_CTRL_PIPE_ACT(val) vBIT(val, 0, 16) 252#define VXGE_HAL_G3FBCT_TRAN_AP_CNT_CTRL_PIPE_PRE(val) vBIT(val, 16, 16) 253#define VXGE_HAL_G3FBCT_TRAN_AP_CNT_UPDATE mBIT(39) 254/* 0x00250 */ u64 g3fbct_g3bist; 255#define VXGE_HAL_G3FBCT_G3BIST_DISABLE_MAIN mBIT(7) 256#define VXGE_HAL_G3FBCT_G3BIST_DISABLE_ICTRL mBIT(15) 257#define VXGE_HAL_G3FBCT_G3BIST_BTCTRL_STATUS_MAIN(val) vBIT(val, 21, 3) 258#define VXGE_HAL_G3FBCT_G3BIST_BTCTRL_STATUS_ICTRL(val) vBIT(val, 29, 3) 259 u8 unused00a00[0x00a00 - 0x00258]; 260 261/* 0x00a00 */ u64 wrdma_int_status; 262#define VXGE_HAL_WRDMA_INT_STATUS_RC_ALARM_RC_INT mBIT(0) 263#define VXGE_HAL_WRDMA_INT_STATUS_RXDRM_SM_ERR_RXDRM_INT mBIT(1) 264#define VXGE_HAL_WRDMA_INT_STATUS_RXDCM_SM_ERR_RXDCM_SM_INT mBIT(2) 265#define VXGE_HAL_WRDMA_INT_STATUS_RXDWM_SM_ERR_RXDWM_INT mBIT(3) 266#define VXGE_HAL_WRDMA_INT_STATUS_RDA_ERR_RDA_INT mBIT(6) 267#define VXGE_HAL_WRDMA_INT_STATUS_RDA_ECC_DB_RDA_ECC_DB_INT mBIT(8) 268#define VXGE_HAL_WRDMA_INT_STATUS_RDA_ECC_SG_RDA_ECC_SG_INT mBIT(9) 269#define VXGE_HAL_WRDMA_INT_STATUS_FRF_ALARM_FRF_INT mBIT(12) 270#define VXGE_HAL_WRDMA_INT_STATUS_ROCRC_ALARM_ROCRC_INT mBIT(13) 271#define VXGE_HAL_WRDMA_INT_STATUS_WDE0_ALARM_WDE0_INT mBIT(14) 272#define VXGE_HAL_WRDMA_INT_STATUS_WDE1_ALARM_WDE1_INT mBIT(15) 273#define VXGE_HAL_WRDMA_INT_STATUS_WDE2_ALARM_WDE2_INT mBIT(16) 274#define VXGE_HAL_WRDMA_INT_STATUS_WDE3_ALARM_WDE3_INT mBIT(17) 275/* 0x00a08 */ u64 wrdma_int_mask; 276/* 0x00a10 */ u64 rc_alarm_reg; 277#define VXGE_HAL_RC_ALARM_REG_FTC_SM_ERR mBIT(0) 278#define VXGE_HAL_RC_ALARM_REG_FTC_SM_PHASE_ERR mBIT(1) 279#define VXGE_HAL_RC_ALARM_REG_BTDWM_SM_ERR mBIT(2) 280#define VXGE_HAL_RC_ALARM_REG_BTC_SM_ERR mBIT(3) 281#define VXGE_HAL_RC_ALARM_REG_BTDCM_SM_ERR mBIT(4) 282#define VXGE_HAL_RC_ALARM_REG_BTDRM_SM_ERR mBIT(5) 283#define VXGE_HAL_RC_ALARM_REG_RMM_RXD_RC_ECC_DB_ERR mBIT(6) 284#define VXGE_HAL_RC_ALARM_REG_RMM_RXD_RC_ECC_SG_ERR mBIT(7) 285#define VXGE_HAL_RC_ALARM_REG_RHS_RXD_RHS_ECC_DB_ERR mBIT(8) 286#define VXGE_HAL_RC_ALARM_REG_RHS_RXD_RHS_ECC_SG_ERR mBIT(9) 287#define VXGE_HAL_RC_ALARM_REG_RMM_SM_ERR mBIT(10) 288#define VXGE_HAL_RC_ALARM_REG_BTC_VPATH_MISMATCH_ERR mBIT(12) 289/* 0x00a18 */ u64 rc_alarm_mask; 290/* 0x00a20 */ u64 rc_alarm_alarm; 291/* 0x00a28 */ u64 rxdrm_sm_err_reg; 292#define VXGE_HAL_RXDRM_SM_ERR_REG_PRC_VP(n) mBIT(n) 293/* 0x00a30 */ u64 rxdrm_sm_err_mask; 294/* 0x00a38 */ u64 rxdrm_sm_err_alarm; 295/* 0x00a40 */ u64 rxdcm_sm_err_reg; 296#define VXGE_HAL_RXDCM_SM_ERR_REG_PRC_VP(n) mBIT(n) 297/* 0x00a48 */ u64 rxdcm_sm_err_mask; 298/* 0x00a50 */ u64 rxdcm_sm_err_alarm; 299/* 0x00a58 */ u64 rxdwm_sm_err_reg; 300#define VXGE_HAL_RXDWM_SM_ERR_REG_PRC_VP(n) mBIT(n) 301/* 0x00a60 */ u64 rxdwm_sm_err_mask; 302/* 0x00a68 */ u64 rxdwm_sm_err_alarm; 303/* 0x00a70 */ u64 rda_err_reg; 304#define VXGE_HAL_RDA_ERR_REG_RDA_SM0_ERR_ALARM mBIT(0) 305#define VXGE_HAL_RDA_ERR_REG_RDA_MISC_ERR mBIT(1) 306#define VXGE_HAL_RDA_ERR_REG_RDA_PCIX_ERR mBIT(2) 307#define VXGE_HAL_RDA_ERR_REG_RDA_RXD_ECC_DB_ERR mBIT(3) 308#define VXGE_HAL_RDA_ERR_REG_RDA_FRM_ECC_DB_ERR mBIT(4) 309#define VXGE_HAL_RDA_ERR_REG_RDA_UQM_ECC_DB_ERR mBIT(5) 310#define VXGE_HAL_RDA_ERR_REG_RDA_IMM_ECC_DB_ERR mBIT(6) 311#define VXGE_HAL_RDA_ERR_REG_RDA_TIM_ECC_DB_ERR mBIT(7) 312/* 0x00a78 */ u64 rda_err_mask; 313/* 0x00a80 */ u64 rda_err_alarm; 314/* 0x00a88 */ u64 rda_ecc_db_reg; 315#define VXGE_HAL_RDA_ECC_DB_REG_RDA_RXD_ERR(n) mBIT(n) 316/* 0x00a90 */ u64 rda_ecc_db_mask; 317/* 0x00a98 */ u64 rda_ecc_db_alarm; 318/* 0x00aa0 */ u64 rda_ecc_sg_reg; 319#define VXGE_HAL_RDA_ECC_SG_REG_RDA_RXD_ERR(n) mBIT(n) 320/* 0x00aa8 */ u64 rda_ecc_sg_mask; 321/* 0x00ab0 */ u64 rda_ecc_sg_alarm; 322/* 0x00ab8 */ u64 rqa_err_reg; 323#define VXGE_HAL_RQA_ERR_REG_RQA_SM_ERR_ALARM mBIT(0) 324/* 0x00ac0 */ u64 rqa_err_mask; 325/* 0x00ac8 */ u64 rqa_err_alarm; 326/* 0x00ad0 */ u64 frf_alarm_reg; 327#define VXGE_HAL_FRF_ALARM_REG_PRC_VP_FRF_SM_ERR(n) mBIT(n) 328/* 0x00ad8 */ u64 frf_alarm_mask; 329/* 0x00ae0 */ u64 frf_alarm_alarm; 330/* 0x00ae8 */ u64 rocrc_alarm_reg; 331#define VXGE_HAL_ROCRC_ALARM_REG_QCQ_QCC_BYP_ECC_DB mBIT(0) 332#define VXGE_HAL_ROCRC_ALARM_REG_QCQ_QCC_BYP_ECC_SG mBIT(1) 333#define VXGE_HAL_ROCRC_ALARM_REG_NOA_NMA_SM_ERR mBIT(2) 334#define VXGE_HAL_ROCRC_ALARM_REG_NOA_IMMM_ECC_DB mBIT(3) 335#define VXGE_HAL_ROCRC_ALARM_REG_NOA_IMMM_ECC_SG mBIT(4) 336#define VXGE_HAL_ROCRC_ALARM_REG_UDQ_UMQM_ECC_DB mBIT(5) 337#define VXGE_HAL_ROCRC_ALARM_REG_UDQ_UMQM_ECC_SG mBIT(6) 338#define VXGE_HAL_ROCRC_ALARM_REG_NOA_RCBM_ECC_DB mBIT(11) 339#define VXGE_HAL_ROCRC_ALARM_REG_NOA_RCBM_ECC_SG mBIT(12) 340#define VXGE_HAL_ROCRC_ALARM_REG_QCQ_MULTI_EGB_RSVD_ERR mBIT(13) 341#define VXGE_HAL_ROCRC_ALARM_REG_QCQ_MULTI_EGB_OWN_ERR mBIT(14) 342#define VXGE_HAL_ROCRC_ALARM_REG_QCQ_MULTI_BYP_OWN_ERR mBIT(15) 343#define VXGE_HAL_ROCRC_ALARM_REG_QCQ_OWN_NOT_ASSIGNED_ERR mBIT(16) 344#define VXGE_HAL_ROCRC_ALARM_REG_QCQ_OWN_RSVD_SYNC_ERR mBIT(17) 345#define VXGE_HAL_ROCRC_ALARM_REG_QCQ_LOST_EGB_ERR mBIT(18) 346#define VXGE_HAL_ROCRC_ALARM_REG_RCQ_BYPQ0_OVERFLOW mBIT(19) 347#define VXGE_HAL_ROCRC_ALARM_REG_RCQ_BYPQ1_OVERFLOW mBIT(20) 348#define VXGE_HAL_ROCRC_ALARM_REG_RCQ_BYPQ2_OVERFLOW mBIT(21) 349#define VXGE_HAL_ROCRC_ALARM_REG_NOA_WCT_CMD_FIFO_ERR mBIT(22) 350/* 0x00af0 */ u64 rocrc_alarm_mask; 351/* 0x00af8 */ u64 rocrc_alarm_alarm; 352/* 0x00b00 */ u64 wde0_alarm_reg; 353#define VXGE_HAL_WDE0_ALARM_REG_WDE0_DCC_SM_ERR mBIT(0) 354#define VXGE_HAL_WDE0_ALARM_REG_WDE0_PRM_SM_ERR mBIT(1) 355#define VXGE_HAL_WDE0_ALARM_REG_WDE0_CP_SM_ERR mBIT(2) 356#define VXGE_HAL_WDE0_ALARM_REG_WDE0_CP_CMD_ERR mBIT(3) 357#define VXGE_HAL_WDE0_ALARM_REG_WDE0_PCR_SM_ERR mBIT(4) 358/* 0x00b08 */ u64 wde0_alarm_mask; 359/* 0x00b10 */ u64 wde0_alarm_alarm; 360/* 0x00b18 */ u64 wde1_alarm_reg; 361#define VXGE_HAL_WDE1_ALARM_REG_WDE1_DCC_SM_ERR mBIT(0) 362#define VXGE_HAL_WDE1_ALARM_REG_WDE1_PRM_SM_ERR mBIT(1) 363#define VXGE_HAL_WDE1_ALARM_REG_WDE1_CP_SM_ERR mBIT(2) 364#define VXGE_HAL_WDE1_ALARM_REG_WDE1_CP_CMD_ERR mBIT(3) 365#define VXGE_HAL_WDE1_ALARM_REG_WDE1_PCR_SM_ERR mBIT(4) 366/* 0x00b20 */ u64 wde1_alarm_mask; 367/* 0x00b28 */ u64 wde1_alarm_alarm; 368/* 0x00b30 */ u64 wde2_alarm_reg; 369#define VXGE_HAL_WDE2_ALARM_REG_WDE2_DCC_SM_ERR mBIT(0) 370#define VXGE_HAL_WDE2_ALARM_REG_WDE2_PRM_SM_ERR mBIT(1) 371#define VXGE_HAL_WDE2_ALARM_REG_WDE2_CP_SM_ERR mBIT(2) 372#define VXGE_HAL_WDE2_ALARM_REG_WDE2_CP_CMD_ERR mBIT(3) 373#define VXGE_HAL_WDE2_ALARM_REG_WDE2_PCR_SM_ERR mBIT(4) 374/* 0x00b38 */ u64 wde2_alarm_mask; 375/* 0x00b40 */ u64 wde2_alarm_alarm; 376/* 0x00b48 */ u64 wde3_alarm_reg; 377#define VXGE_HAL_WDE3_ALARM_REG_WDE3_DCC_SM_ERR mBIT(0) 378#define VXGE_HAL_WDE3_ALARM_REG_WDE3_PRM_SM_ERR mBIT(1) 379#define VXGE_HAL_WDE3_ALARM_REG_WDE3_CP_SM_ERR mBIT(2) 380#define VXGE_HAL_WDE3_ALARM_REG_WDE3_CP_CMD_ERR mBIT(3) 381#define VXGE_HAL_WDE3_ALARM_REG_WDE3_PCR_SM_ERR mBIT(4) 382/* 0x00b50 */ u64 wde3_alarm_mask; 383/* 0x00b58 */ u64 wde3_alarm_alarm; 384/* 0x00b60 */ u64 rc_cfg; 385#define VXGE_HAL_RC_CFG_RXD_ERR_MASK(val) vBIT(val, 0, 4) 386#define VXGE_HAL_RC_CFG_RXD_RD_RO mBIT(12) 387#define VXGE_HAL_RC_CFG_FIXED_BUFFER_SIZE mBIT(13) 388#define VXGE_HAL_RC_CFG_ENABLE_VP_CFG_CHANGE_WHILE_BUSY mBIT(14) 389#define VXGE_HAL_RC_CFG_PRESERVE_BUFFER_SIZE mBIT(15) 390/* 0x00b68 */ u64 ecc_cfg; 391#define VXGE_HAL_ECC_CFG_RXD_RC_ECC_ENABLE_N mBIT(0) 392#define VXGE_HAL_ECC_CFG_RXD_RHS_ECC_ENABLE_N mBIT(1) 393#define VXGE_HAL_ECC_CFG_NOA_IMMM_ECC_ENABLE_N mBIT(4) 394#define VXGE_HAL_ECC_CFG_UDQ_UMQM_ECC_ENABLE_N mBIT(5) 395#define VXGE_HAL_ECC_CFG_RCBM_CQB_ECC_ENABLE_N mBIT(7) 396/* 0x00b70 */ u64 rxd_cfg_1bm; 397#define VXGE_HAL_RXD_CFG_1BM_QW_SIZE(val) vBIT(val, 5, 3) 398#define VXGE_HAL_RXD_CFG_1BM_QW2WRITE(val) vBIT(val, 8, 8) 399#define VXGE_HAL_RXD_CFG_1BM_HCW_QWOFF(val) vBIT(val, 21, 3) 400#define VXGE_HAL_RXD_CFG_1BM_RTH_VAL_QWOFF(val) vBIT(val, 29, 3) 401#define VXGE_HAL_RXD_CFG_1BM_RTH_VAL_W0OFF(val) vBIT(val, 38, 2) 402#define VXGE_HAL_RXD_CFG_1BM_RTH_VAL_W1OFF(val) vBIT(val, 46, 2) 403#define VXGE_HAL_RXD_CFG_1BM_HEAD_OWN_QWOFF(val) vBIT(val, 53, 3) 404#define VXGE_HAL_RXD_CFG_1BM_HEAD_OWN_BOFF(val) vBIT(val, 61, 3) 405/* 0x00b78 */ u64 rxd_cfg1_1bm; 406#define VXGE_HAL_RXD_CFG1_1BM_BUFF1_SIZE_QWOFF(val) vBIT(val, 5, 3) 407#define VXGE_HAL_RXD_CFG1_1BM_TRSF_CODE_QWOFF(val) vBIT(val, 45, 3) 408#define VXGE_HAL_RXD_CFG1_1BM_TRSF_CODE_BOFF(val) vBIT(val, 53, 3) 409#define VXGE_HAL_RXD_CFG1_1BM_RTH_BUCKET_DATA_QWOF(val) vBIT(val, 61, 3) 410/* 0x00b80 */ u64 rxd_cfg2_1bm; 411#define VXGE_HAL_RXD_CFG2_1BM_RTH_BUCKET_DATA_BOFF(val) vBIT(val, 5, 3) 412#define VXGE_HAL_RXD_CFG2_1BM_BUFF1_SIZE_WOFF(val) vBIT(val, 14, 2) 413#define VXGE_HAL_RXD_CFG2_1BM_FRM_INFO_QWOFF(val) vBIT(val, 53, 3) 414#define VXGE_HAL_RXD_CFG2_1BM_FRM_INFO_BOFF(val) vBIT(val, 61, 3) 415/* 0x00b88 */ u64 rxd_cfg3_1bm; 416#define VXGE_HAL_RXD_CFG3_1BM_BUFF1_PTR_QWOFF(val) vBIT(val, 5, 3) 417#define VXGE_HAL_RXD_CFG3_1BM_TAIL_OWN_QWOFF(val) vBIT(val, 45, 3) 418#define VXGE_HAL_RXD_CFG3_1BM_TAIL_OWN_BOFF(val) vBIT(val, 53, 3) 419#define VXGE_HAL_RXD_CFG3_1BM_HEAD_OWN_BIT_IDX(val) vBIT(val, 57, 3) 420#define VXGE_HAL_RXD_CFG3_1BM_TAIL_OWN_BIT_IDX(val) vBIT(val, 61, 3) 421/* 0x00b90 */ u64 rxd_cfg4_1bm; 422#define VXGE_HAL_RXD_CFG4_1BM_L3C_QWOFF(val) vBIT(val, 5, 3) 423#define VXGE_HAL_RXD_CFG4_1BM_L3C_WOFF(val) vBIT(val, 14, 2) 424#define VXGE_HAL_RXD_CFG4_1BM_L4C_QWOFF(val) vBIT(val, 21, 3) 425#define VXGE_HAL_RXD_CFG4_1BM_L4C_WOFF(val) vBIT(val, 30, 2) 426#define VXGE_HAL_RXD_CFG4_1BM_VTAG_QWOFF(val) vBIT(val, 37, 3) 427#define VXGE_HAL_RXD_CFG4_1BM_VTAG_WOFF(val) vBIT(val, 46, 2) 428#define VXGE_HAL_RXD_CFG4_1BM_RTH_INFO_QWOFF(val) vBIT(val, 53, 3) 429#define VXGE_HAL_RXD_CFG4_1BM_RTH_INFO_BOFF(val) vBIT(val, 61, 3) 430/* 0x00b98 */ u64 rxd_cfg_3bm; 431#define VXGE_HAL_RXD_CFG_3BM_QW_SIZE(val) vBIT(val, 5, 3) 432#define VXGE_HAL_RXD_CFG_3BM_QW2WRITE(val) vBIT(val, 8, 8) 433#define VXGE_HAL_RXD_CFG_3BM_HCW_QWOFF(val) vBIT(val, 21, 3) 434#define VXGE_HAL_RXD_CFG_3BM_RTH_VAL_QWOFF(val) vBIT(val, 29, 3) 435#define VXGE_HAL_RXD_CFG_3BM_RTH_VAL_W0OFF(val) vBIT(val, 38, 2) 436#define VXGE_HAL_RXD_CFG_3BM_RTH_VAL_W1OFF(val) vBIT(val, 46, 2) 437#define VXGE_HAL_RXD_CFG_3BM_HEAD_OWN_QWOFF(val) vBIT(val, 53, 3) 438#define VXGE_HAL_RXD_CFG_3BM_HEAD_OWN_BOFF(val) vBIT(val, 61, 3) 439/* 0x00ba0 */ u64 rxd_cfg1_3bm; 440#define VXGE_HAL_RXD_CFG1_3BM_BUFF1_SIZE_QWOFF(val) vBIT(val, 5, 3) 441#define VXGE_HAL_RXD_CFG1_3BM_BUFF2_SIZE_QWOFF(val) vBIT(val, 13, 3) 442#define VXGE_HAL_RXD_CFG1_3BM_BUFF3_SIZE_QWOFF(val) vBIT(val, 21, 3) 443#define VXGE_HAL_RXD_CFG1_3BM_TRSF_CODE_QWOFF(val) vBIT(val, 45, 3) 444#define VXGE_HAL_RXD_CFG1_3BM_TRSF_CODE_BOFF(val) vBIT(val, 53, 3) 445#define VXGE_HAL_RXD_CFG1_3BM_RTH_BUCKET_DATA_QWOF(val) vBIT(val, 61, 3) 446/* 0x00ba8 */ u64 rxd_cfg2_3bm; 447#define VXGE_HAL_RXD_CFG2_3BM_RTH_BUCKET_DATA_BOFF(val) vBIT(val, 5, 3) 448#define VXGE_HAL_RXD_CFG2_3BM_BUFF1_SIZE_WOFF(val) vBIT(val, 14, 2) 449#define VXGE_HAL_RXD_CFG2_3BM_BUFF2_SIZE_WOFF(val) vBIT(val, 22, 2) 450#define VXGE_HAL_RXD_CFG2_3BM_BUFF3_SIZE_WOFF(val) vBIT(val, 30, 2) 451#define VXGE_HAL_RXD_CFG2_3BM_FRM_INFO_QWOFF(val) vBIT(val, 53, 3) 452#define VXGE_HAL_RXD_CFG2_3BM_FRM_INFO_BOFF(val) vBIT(val, 61, 3) 453/* 0x00bb0 */ u64 rxd_cfg3_3bm; 454#define VXGE_HAL_RXD_CFG3_3BM_BUFF1_PTR_QWOFF(val) vBIT(val, 5, 3) 455#define VXGE_HAL_RXD_CFG3_3BM_BUFF2_PTR_QWOFF(val) vBIT(val, 13, 3) 456#define VXGE_HAL_RXD_CFG3_3BM_BUFF3_PTR_QWOFF(val) vBIT(val, 21, 3) 457#define VXGE_HAL_RXD_CFG3_3BM_TAIL_OWN_QWOFF(val) vBIT(val, 45, 3) 458#define VXGE_HAL_RXD_CFG3_3BM_TAIL_OWN_BOFF(val) vBIT(val, 53, 3) 459#define VXGE_HAL_RXD_CFG3_3BM_HEAD_OWN_BIT_IDX(val) vBIT(val, 57, 3) 460#define VXGE_HAL_RXD_CFG3_3BM_TAIL_OWN_BIT_IDX(val) vBIT(val, 61, 3) 461/* 0x00bb8 */ u64 rxd_cfg4_3bm; 462#define VXGE_HAL_RXD_CFG4_3BM_L3C_QWOFF(val) vBIT(val, 5, 3) 463#define VXGE_HAL_RXD_CFG4_3BM_L3C_WOFF(val) vBIT(val, 14, 2) 464#define VXGE_HAL_RXD_CFG4_3BM_L4C_QWOFF(val) vBIT(val, 21, 3) 465#define VXGE_HAL_RXD_CFG4_3BM_L4C_WOFF(val) vBIT(val, 30, 2) 466#define VXGE_HAL_RXD_CFG4_3BM_VTAG_QWOFF(val) vBIT(val, 37, 3) 467#define VXGE_HAL_RXD_CFG4_3BM_VTAG_WOFF(val) vBIT(val, 46, 2) 468#define VXGE_HAL_RXD_CFG4_3BM_RTH_INFO_QWOFF(val) vBIT(val, 53, 3) 469#define VXGE_HAL_RXD_CFG4_3BM_RTH_INFO_BOFF(val) vBIT(val, 61, 3) 470/* 0x00bc0 */ u64 rxd_cfg_5bm; 471#define VXGE_HAL_RXD_CFG_5BM_QW_SIZE(val) vBIT(val, 5, 3) 472#define VXGE_HAL_RXD_CFG_5BM_QW2WRITE(val) vBIT(val, 8, 8) 473#define VXGE_HAL_RXD_CFG_5BM_HCW_QWOFF(val) vBIT(val, 21, 3) 474#define VXGE_HAL_RXD_CFG_5BM_RTH_VAL_QWOFF(val) vBIT(val, 29, 3) 475#define VXGE_HAL_RXD_CFG_5BM_RTH_VAL_W0OFF(val) vBIT(val, 38, 2) 476#define VXGE_HAL_RXD_CFG_5BM_RTH_VAL_W1OFF(val) vBIT(val, 46, 2) 477#define VXGE_HAL_RXD_CFG_5BM_HEAD_OWN_QWOFF(val) vBIT(val, 53, 3) 478#define VXGE_HAL_RXD_CFG_5BM_HEAD_OWN_BOFF(val) vBIT(val, 61, 3) 479/* 0x00bc8 */ u64 rxd_cfg1_5bm; 480#define VXGE_HAL_RXD_CFG1_5BM_BUFF1_SIZE_QWOFF(val) vBIT(val, 5, 3) 481#define VXGE_HAL_RXD_CFG1_5BM_BUFF2_SIZE_QWOFF(val) vBIT(val, 13, 3) 482#define VXGE_HAL_RXD_CFG1_5BM_BUFF3_SIZE_QWOFF(val) vBIT(val, 21, 3) 483#define VXGE_HAL_RXD_CFG1_5BM_BUFF4_SIZE_QWOFF(val) vBIT(val, 29, 3) 484#define VXGE_HAL_RXD_CFG1_5BM_BUFF5_SIZE_QWOFF(val) vBIT(val, 37, 3) 485#define VXGE_HAL_RXD_CFG1_5BM_TRSF_CODE_QWOFF(val) vBIT(val, 45, 3) 486#define VXGE_HAL_RXD_CFG1_5BM_TRSF_CODE_BOFF(val) vBIT(val, 53, 3) 487#define VXGE_HAL_RXD_CFG1_5BM_RTH_BUCKET_DATA_QWOF(val) vBIT(val, 61, 3) 488/* 0x00bd0 */ u64 rxd_cfg2_5bm; 489#define VXGE_HAL_RXD_CFG2_5BM_RTH_BUCKET_DATA_BOFF(val) vBIT(val, 5, 3) 490#define VXGE_HAL_RXD_CFG2_5BM_BUFF1_SIZE_WOFF(val) vBIT(val, 14, 2) 491#define VXGE_HAL_RXD_CFG2_5BM_BUFF2_SIZE_WOFF(val) vBIT(val, 22, 2) 492#define VXGE_HAL_RXD_CFG2_5BM_BUFF3_SIZE_WOFF(val) vBIT(val, 30, 2) 493#define VXGE_HAL_RXD_CFG2_5BM_BUFF4_SIZE_WOFF(val) vBIT(val, 38, 2) 494#define VXGE_HAL_RXD_CFG2_5BM_BUFF5_SIZE_WOFF(val) vBIT(val, 46, 2) 495#define VXGE_HAL_RXD_CFG2_5BM_FRM_INFO_QWOFF(val) vBIT(val, 53, 3) 496#define VXGE_HAL_RXD_CFG2_5BM_FRM_INFO_BOFF(val) vBIT(val, 61, 3) 497/* 0x00bd8 */ u64 rxd_cfg3_5bm; 498#define VXGE_HAL_RXD_CFG3_5BM_BUFF1_PTR_QWOFF(val) vBIT(val, 5, 3) 499#define VXGE_HAL_RXD_CFG3_5BM_BUFF2_PTR_QWOFF(val) vBIT(val, 13, 3) 500#define VXGE_HAL_RXD_CFG3_5BM_BUFF3_PTR_QWOFF(val) vBIT(val, 21, 3) 501#define VXGE_HAL_RXD_CFG3_5BM_BUFF4_PTR_QWOFF(val) vBIT(val, 29, 3) 502#define VXGE_HAL_RXD_CFG3_5BM_BUFF5_PTR_QWOFF(val) vBIT(val, 37, 3) 503#define VXGE_HAL_RXD_CFG3_5BM_TAIL_OWN_QWOFF(val) vBIT(val, 45, 3) 504#define VXGE_HAL_RXD_CFG3_5BM_TAIL_OWN_BOFF(val) vBIT(val, 53, 3) 505#define VXGE_HAL_RXD_CFG3_5BM_HEAD_OWN_BIT_IDX(val) vBIT(val, 57, 3) 506#define VXGE_HAL_RXD_CFG3_5BM_TAIL_OWN_BIT_IDX(val) vBIT(val, 61, 3) 507/* 0x00be0 */ u64 rxd_cfg4_5bm; 508#define VXGE_HAL_RXD_CFG4_5BM_L3C_QWOFF(val) vBIT(val, 5, 3) 509#define VXGE_HAL_RXD_CFG4_5BM_L3C_WOFF(val) vBIT(val, 14, 2) 510#define VXGE_HAL_RXD_CFG4_5BM_L4C_QWOFF(val) vBIT(val, 21, 3) 511#define VXGE_HAL_RXD_CFG4_5BM_L4C_WOFF(val) vBIT(val, 30, 2) 512#define VXGE_HAL_RXD_CFG4_5BM_VTAG_QWOFF(val) vBIT(val, 37, 3) 513#define VXGE_HAL_RXD_CFG4_5BM_VTAG_WOFF(val) vBIT(val, 46, 2) 514#define VXGE_HAL_RXD_CFG4_5BM_RTH_INFO_QWOFF(val) vBIT(val, 53, 3) 515#define VXGE_HAL_RXD_CFG4_5BM_RTH_INFO_BOFF(val) vBIT(val, 61, 3) 516/* 0x00be8 */ u64 rx_w_round_robin_0; 517#define VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_0(val) vBIT(val, 3, 5) 518#define VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_1(val) vBIT(val, 11, 5) 519#define VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_2(val) vBIT(val, 19, 5) 520#define VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_3(val) vBIT(val, 27, 5) 521#define VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_4(val) vBIT(val, 35, 5) 522#define VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_5(val) vBIT(val, 43, 5) 523#define VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_6(val) vBIT(val, 51, 5) 524#define VXGE_HAL_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_7(val) vBIT(val, 59, 5) 525/* 0x00bf0 */ u64 rx_w_round_robin_1; 526#define VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_8(val) vBIT(val, 3, 5) 527#define VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_9(val) vBIT(val, 11, 5) 528#define VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_10(val) vBIT(val, 19, 5) 529#define VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_11(val) vBIT(val, 27, 5) 530#define VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_12(val) vBIT(val, 35, 5) 531#define VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_13(val) vBIT(val, 43, 5) 532#define VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_14(val) vBIT(val, 51, 5) 533#define VXGE_HAL_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_15(val) vBIT(val, 59, 5) 534/* 0x00bf8 */ u64 rx_w_round_robin_2; 535#define VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_16(val) vBIT(val, 3, 5) 536#define VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_17(val) vBIT(val, 11, 5) 537#define VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_18(val) vBIT(val, 19, 5) 538#define VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_19(val) vBIT(val, 27, 5) 539#define VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_20(val) vBIT(val, 35, 5) 540#define VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_21(val) vBIT(val, 43, 5) 541#define VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_22(val) vBIT(val, 51, 5) 542#define VXGE_HAL_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_23(val) vBIT(val, 59, 5) 543/* 0x00c00 */ u64 rx_w_round_robin_3; 544#define VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_24(val) vBIT(val, 3, 5) 545#define VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_25(val) vBIT(val, 11, 5) 546#define VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_26(val) vBIT(val, 19, 5) 547#define VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_27(val) vBIT(val, 27, 5) 548#define VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_28(val) vBIT(val, 35, 5) 549#define VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_29(val) vBIT(val, 43, 5) 550#define VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_30(val) vBIT(val, 51, 5) 551#define VXGE_HAL_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_31(val) vBIT(val, 59, 5) 552/* 0x00c08 */ u64 rx_w_round_robin_4; 553#define VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_32(val) vBIT(val, 3, 5) 554#define VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_33(val) vBIT(val, 11, 5) 555#define VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_34(val) vBIT(val, 19, 5) 556#define VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_35(val) vBIT(val, 27, 5) 557#define VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_36(val) vBIT(val, 35, 5) 558#define VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_37(val) vBIT(val, 43, 5) 559#define VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_38(val) vBIT(val, 51, 5) 560#define VXGE_HAL_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_39(val) vBIT(val, 59, 5) 561/* 0x00c10 */ u64 rx_w_round_robin_5; 562#define VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_40(val) vBIT(val, 3, 5) 563#define VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_41(val) vBIT(val, 11, 5) 564#define VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_42(val) vBIT(val, 19, 5) 565#define VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_43(val) vBIT(val, 27, 5) 566#define VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_44(val) vBIT(val, 35, 5) 567#define VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_45(val) vBIT(val, 43, 5) 568#define VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_46(val) vBIT(val, 51, 5) 569#define VXGE_HAL_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_47(val) vBIT(val, 59, 5) 570/* 0x00c18 */ u64 rx_w_round_robin_6; 571#define VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_48(val) vBIT(val, 3, 5) 572#define VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_49(val) vBIT(val, 11, 5) 573#define VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_50(val) vBIT(val, 19, 5) 574#define VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_51(val) vBIT(val, 27, 5) 575#define VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_52(val) vBIT(val, 35, 5) 576#define VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_53(val) vBIT(val, 43, 5) 577#define VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_54(val) vBIT(val, 51, 5) 578#define VXGE_HAL_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_55(val) vBIT(val, 59, 5) 579/* 0x00c20 */ u64 rx_w_round_robin_7; 580#define VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_56(val) vBIT(val, 3, 5) 581#define VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_57(val) vBIT(val, 11, 5) 582#define VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_58(val) vBIT(val, 19, 5) 583#define VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_59(val) vBIT(val, 27, 5) 584#define VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_60(val) vBIT(val, 35, 5) 585#define VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_61(val) vBIT(val, 43, 5) 586#define VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_62(val) vBIT(val, 51, 5) 587#define VXGE_HAL_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_63(val) vBIT(val, 59, 5) 588/* 0x00c28 */ u64 rx_w_round_robin_8; 589#define VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_64(val) vBIT(val, 3, 5) 590#define VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_65(val) vBIT(val, 11, 5) 591#define VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_66(val) vBIT(val, 19, 5) 592#define VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_67(val) vBIT(val, 27, 5) 593#define VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_68(val) vBIT(val, 35, 5) 594#define VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_69(val) vBIT(val, 43, 5) 595#define VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_70(val) vBIT(val, 51, 5) 596#define VXGE_HAL_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_71(val) vBIT(val, 59, 5) 597/* 0x00c30 */ u64 rx_w_round_robin_9; 598#define VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_72(val) vBIT(val, 3, 5) 599#define VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_73(val) vBIT(val, 11, 5) 600#define VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_74(val) vBIT(val, 19, 5) 601#define VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_75(val) vBIT(val, 27, 5) 602#define VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_76(val) vBIT(val, 35, 5) 603#define VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_77(val) vBIT(val, 43, 5) 604#define VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_78(val) vBIT(val, 51, 5) 605#define VXGE_HAL_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_79(val) vBIT(val, 59, 5) 606/* 0x00c38 */ u64 rx_w_round_robin_10; 607#define VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_80(val) vBIT(val, 3, 5) 608#define VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_81(val) vBIT(val, 11, 5) 609#define VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_82(val) vBIT(val, 19, 5) 610#define VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_83(val) vBIT(val, 27, 5) 611#define VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_84(val) vBIT(val, 35, 5) 612#define VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_85(val) vBIT(val, 43, 5) 613#define VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_86(val) vBIT(val, 51, 5) 614#define VXGE_HAL_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_87(val) vBIT(val, 59, 5) 615/* 0x00c40 */ u64 rx_w_round_robin_11; 616#define VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_88(val) vBIT(val, 3, 5) 617#define VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_89(val) vBIT(val, 11, 5) 618#define VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_90(val) vBIT(val, 19, 5) 619#define VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_91(val) vBIT(val, 27, 5) 620#define VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_92(val) vBIT(val, 35, 5) 621#define VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_93(val) vBIT(val, 43, 5) 622#define VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_94(val) vBIT(val, 51, 5) 623#define VXGE_HAL_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_95(val) vBIT(val, 59, 5) 624/* 0x00c48 */ u64 rx_w_round_robin_12; 625#define VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_96(val) vBIT(val, 3, 5) 626#define VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_97(val) vBIT(val, 11, 5) 627#define VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_98(val) vBIT(val, 19, 5) 628#define VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_99(val) vBIT(val, 27, 5) 629#define VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_100(val) vBIT(val, 35, 5) 630#define VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_101(val) vBIT(val, 43, 5) 631#define VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_102(val) vBIT(val, 51, 5) 632#define VXGE_HAL_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_103(val) vBIT(val, 59, 5) 633/* 0x00c50 */ u64 rx_w_round_robin_13; 634#define VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_104(val) vBIT(val, 3, 5) 635#define VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_105(val) vBIT(val, 11, 5) 636#define VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_106(val) vBIT(val, 19, 5) 637#define VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_107(val) vBIT(val, 27, 5) 638#define VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_108(val) vBIT(val, 35, 5) 639#define VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_109(val) vBIT(val, 43, 5) 640#define VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_110(val) vBIT(val, 51, 5) 641#define VXGE_HAL_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_111(val) vBIT(val, 59, 5) 642/* 0x00c58 */ u64 rx_w_round_robin_14; 643#define VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_112(val) vBIT(val, 3, 5) 644#define VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_113(val) vBIT(val, 11, 5) 645#define VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_114(val) vBIT(val, 19, 5) 646#define VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_115(val) vBIT(val, 27, 5) 647#define VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_116(val) vBIT(val, 35, 5) 648#define VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_117(val) vBIT(val, 43, 5) 649#define VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_118(val) vBIT(val, 51, 5) 650#define VXGE_HAL_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_119(val) vBIT(val, 59, 5) 651/* 0x00c60 */ u64 rx_w_round_robin_15; 652#define VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_120(val) vBIT(val, 3, 5) 653#define VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_121(val) vBIT(val, 11, 5) 654#define VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_122(val) vBIT(val, 19, 5) 655#define VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_123(val) vBIT(val, 27, 5) 656#define VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_124(val) vBIT(val, 35, 5) 657#define VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_125(val) vBIT(val, 43, 5) 658#define VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_126(val) vBIT(val, 51, 5) 659#define VXGE_HAL_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_127(val) vBIT(val, 59, 5) 660/* 0x00c68 */ u64 rx_w_round_robin_16; 661#define VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_128(val) vBIT(val, 3, 5) 662#define VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_129(val) vBIT(val, 11, 5) 663#define VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_130(val) vBIT(val, 19, 5) 664#define VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_131(val) vBIT(val, 27, 5) 665#define VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_132(val) vBIT(val, 35, 5) 666#define VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_133(val) vBIT(val, 43, 5) 667#define VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_134(val) vBIT(val, 51, 5) 668#define VXGE_HAL_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_135(val) vBIT(val, 59, 5) 669/* 0x00c70 */ u64 rx_w_round_robin_17; 670#define VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_136(val) vBIT(val, 3, 5) 671#define VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_137(val) vBIT(val, 11, 5) 672#define VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_138(val) vBIT(val, 19, 5) 673#define VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_139(val) vBIT(val, 27, 5) 674#define VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_140(val) vBIT(val, 35, 5) 675#define VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_141(val) vBIT(val, 43, 5) 676#define VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_142(val) vBIT(val, 51, 5) 677#define VXGE_HAL_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_143(val) vBIT(val, 59, 5) 678/* 0x00c78 */ u64 rx_w_round_robin_18; 679#define VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_144(val) vBIT(val, 3, 5) 680#define VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_145(val) vBIT(val, 11, 5) 681#define VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_146(val) vBIT(val, 19, 5) 682#define VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_147(val) vBIT(val, 27, 5) 683#define VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_148(val) vBIT(val, 35, 5) 684#define VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_149(val) vBIT(val, 43, 5) 685#define VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_150(val) vBIT(val, 51, 5) 686#define VXGE_HAL_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_151(val) vBIT(val, 59, 5) 687/* 0x00c80 */ u64 rx_w_round_robin_19; 688#define VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_152(val) vBIT(val, 3, 5) 689#define VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_153(val) vBIT(val, 11, 5) 690#define VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_154(val) vBIT(val, 19, 5) 691#define VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_155(val) vBIT(val, 27, 5) 692#define VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_156(val) vBIT(val, 35, 5) 693#define VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_157(val) vBIT(val, 43, 5) 694#define VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_158(val) vBIT(val, 51, 5) 695#define VXGE_HAL_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_159(val) vBIT(val, 59, 5) 696/* 0x00c88 */ u64 rx_w_round_robin_20; 697#define VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_160(val) vBIT(val, 3, 5) 698#define VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_161(val) vBIT(val, 11, 5) 699#define VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_162(val) vBIT(val, 19, 5) 700#define VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_163(val) vBIT(val, 27, 5) 701#define VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_164(val) vBIT(val, 35, 5) 702#define VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_165(val) vBIT(val, 43, 5) 703#define VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_166(val) vBIT(val, 51, 5) 704#define VXGE_HAL_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_167(val) vBIT(val, 59, 5) 705/* 0x00c90 */ u64 rx_w_round_robin_21; 706#define VXGE_HAL_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_168(val) vBIT(val, 3, 5) 707#define VXGE_HAL_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_169(val) vBIT(val, 11, 5) 708#define VXGE_HAL_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_170(val) vBIT(val, 19, 5) 709/* 0x00c98 */ u64 rx_queue_priority_0; 710#define VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_0(val) vBIT(val, 3, 5) 711#define VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_1(val) vBIT(val, 11, 5) 712#define VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_2(val) vBIT(val, 19, 5) 713#define VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_3(val) vBIT(val, 27, 5) 714#define VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_4(val) vBIT(val, 35, 5) 715#define VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_5(val) vBIT(val, 43, 5) 716#define VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_6(val) vBIT(val, 51, 5) 717#define VXGE_HAL_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_7(val) vBIT(val, 59, 5) 718/* 0x00ca0 */ u64 rx_queue_priority_1; 719#define VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_8(val) vBIT(val, 3, 5) 720#define VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_9(val) vBIT(val, 11, 5) 721#define VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_10(val) vBIT(val, 19, 5) 722#define VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_11(val) vBIT(val, 27, 5) 723#define VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_12(val) vBIT(val, 35, 5) 724#define VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_13(val) vBIT(val, 43, 5) 725#define VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_14(val) vBIT(val, 51, 5) 726#define VXGE_HAL_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_15(val) vBIT(val, 59, 5) 727/* 0x00ca8 */ u64 rx_queue_priority_2; 728#define VXGE_HAL_RX_QUEUE_PRIORITY_2_RX_Q_NUMBER_16(val) vBIT(val, 3, 5) 729 u8 unused00cc8[0x00cc8 - 0x00cb0]; 730 731/* 0x00cc8 */ u64 replication_queue_priority; 732#define VXGE_HAL_REPLICATION_QUEUE_PRIORITY_REPLICATION_QUEUE_PRIORITY(val)\ 733 vBIT(val, 59, 5) 734/* 0x00cd0 */ u64 rx_queue_select; 735#define VXGE_HAL_RX_QUEUE_SELECT_NUMBER(n) mBIT(n) 736#define VXGE_HAL_RX_QUEUE_SELECT_ENABLE_CODE mBIT(15) 737#define VXGE_HAL_RX_QUEUE_SELECT_ENABLE_HIERARCHICAL_PRTY mBIT(23) 738/* 0x00cd8 */ u64 rqa_vpbp_ctrl; 739#define VXGE_HAL_RQA_VPBP_CTRL_WR_XON_DIS mBIT(15) 740#define VXGE_HAL_RQA_VPBP_CTRL_ROCRC_DIS mBIT(23) 741#define VXGE_HAL_RQA_VPBP_CTRL_TXPE_DIS mBIT(31) 742/* 0x00ce0 */ u64 rx_multi_cast_ctrl; 743#define VXGE_HAL_RX_MULTI_CAST_CTRL_TIME_OUT_DIS mBIT(0) 744#define VXGE_HAL_RX_MULTI_CAST_CTRL_FRM_DROP_DIS mBIT(1) 745#define VXGE_HAL_RX_MULTI_CAST_CTRL_NO_RXD_TIME_OUT_CNT(val) vBIT(val, 2, 30) 746#define VXGE_HAL_RX_MULTI_CAST_CTRL_TIME_OUT_CNT(val) vBIT(val, 32, 32) 747/* 0x00ce8 */ u64 wde_prm_ctrl; 748#define VXGE_HAL_WDE_PRM_CTRL_SPAV_THRESHOLD(val) vBIT(val, 2, 10) 749#define VXGE_HAL_WDE_PRM_CTRL_SPLIT_THRESHOLD(val) vBIT(val, 18, 14) 750#define VXGE_HAL_WDE_PRM_CTRL_SPLIT_ON_1ST_ROW mBIT(32) 751#define VXGE_HAL_WDE_PRM_CTRL_SPLIT_ON_ROW_BNDRY mBIT(33) 752#define VXGE_HAL_WDE_PRM_CTRL_FB_ROW_SIZE(val) vBIT(val, 46, 2) 753/* 0x00cf0 */ u64 noa_ctrl; 754#define VXGE_HAL_NOA_CTRL_FRM_PRTY_QUOTA(val) vBIT(val, 3, 5) 755#define VXGE_HAL_NOA_CTRL_NON_FRM_PRTY_QUOTA(val) vBIT(val, 11, 5) 756#define VXGE_HAL_NOA_CTRL_IGNORE_KDFC_IF_STATUS mBIT(16) 757#define VXGE_HAL_NOA_CTRL_MAX_JOB_CNT_FOR_WDE0(val) vBIT(val, 37, 4) 758#define VXGE_HAL_NOA_CTRL_MAX_JOB_CNT_FOR_WDE1(val) vBIT(val, 45, 4) 759#define VXGE_HAL_NOA_CTRL_MAX_JOB_CNT_FOR_WDE2(val) vBIT(val, 53, 4) 760#define VXGE_HAL_NOA_CTRL_MAX_JOB_CNT_FOR_WDE3(val) vBIT(val, 60, 4) 761/* 0x00cf8 */ u64 phase_cfg; 762#define VXGE_HAL_PHASE_CFG_QCC_WR_PHASE_EN mBIT(0) 763#define VXGE_HAL_PHASE_CFG_QCC_RD_PHASE_EN mBIT(3) 764#define VXGE_HAL_PHASE_CFG_IMMM_WR_PHASE_EN mBIT(7) 765#define VXGE_HAL_PHASE_CFG_IMMM_RD_PHASE_EN mBIT(11) 766#define VXGE_HAL_PHASE_CFG_UMQM_WR_PHASE_EN mBIT(15) 767#define VXGE_HAL_PHASE_CFG_UMQM_RD_PHASE_EN mBIT(19) 768#define VXGE_HAL_PHASE_CFG_RCBM_WR_PHASE_EN mBIT(23) 769#define VXGE_HAL_PHASE_CFG_RCBM_RD_PHASE_EN mBIT(27) 770#define VXGE_HAL_PHASE_CFG_RXD_RC_WR_PHASE_EN mBIT(31) 771#define VXGE_HAL_PHASE_CFG_RXD_RC_RD_PHASE_EN mBIT(35) 772#define VXGE_HAL_PHASE_CFG_RXD_RHS_WR_PHASE_EN mBIT(39) 773#define VXGE_HAL_PHASE_CFG_RXD_RHS_RD_PHASE_EN mBIT(43) 774/* 0x00d00 */ u64 rcq_bypq_cfg; 775#define VXGE_HAL_RCQ_BYPQ_CFG_OVERFLOW_THRESHOLD(val) vBIT(val, 10, 22) 776#define VXGE_HAL_RCQ_BYPQ_CFG_BYP_ON_THRESHOLD(val) vBIT(val, 39, 9) 777#define VXGE_HAL_RCQ_BYPQ_CFG_BYP_OFF_THRESHOLD(val) vBIT(val, 55, 9) 778 u8 unused00e00[0x00e00 - 0x00d08]; 779 780/* 0x00e00 */ u64 doorbell_int_status; 781#define VXGE_HAL_DOORBELL_INT_STATUS_KDFC_ERR_REG_TXDMA_KDFC_INT mBIT(7) 782#define VXGE_HAL_DOORBELL_INT_STATUS_USDC_ERR_REG_TXDMA_USDC_INT mBIT(15) 783/* 0x00e08 */ u64 doorbell_int_mask; 784/* 0x00e10 */ u64 kdfc_err_reg; 785#define VXGE_HAL_KDFC_ERR_REG_KDFC_KDFC_ECC_SG_ERR mBIT(7) 786#define VXGE_HAL_KDFC_ERR_REG_KDFC_KDFC_ECC_DB_ERR mBIT(15) 787#define VXGE_HAL_KDFC_ERR_REG_KDFC_KDFC_SM_ERR_ALARM mBIT(23) 788#define VXGE_HAL_KDFC_ERR_REG_KDFC_KDFC_MISC_ERR_1 mBIT(32) 789#define VXGE_HAL_KDFC_ERR_REG_KDFC_KDFC_PCIX_ERR mBIT(39) 790/* 0x00e18 */ u64 kdfc_err_mask; 791/* 0x00e20 */ u64 kdfc_err_reg_alarm; 792#define VXGE_HAL_KDFC_ERR_REG_ALARM_KDFC_KDFC_ECC_SG_ERR mBIT(7) 793#define VXGE_HAL_KDFC_ERR_REG_ALARM_KDFC_KDFC_ECC_DB_ERR mBIT(15) 794#define VXGE_HAL_KDFC_ERR_REG_ALARM_KDFC_KDFC_SM_ERR_ALARM mBIT(23) 795#define VXGE_HAL_KDFC_ERR_REG_ALARM_KDFC_KDFC_MISC_ERR_1 mBIT(32) 796#define VXGE_HAL_KDFC_ERR_REG_ALARM_KDFC_KDFC_PCIX_ERR mBIT(39) 797/* 0x00e28 */ u64 usdc_err_reg; 798#define VXGE_HAL_USDC_ERR_REG_USDC_FIFO_ECC_SG_ERR mBIT(4) 799#define VXGE_HAL_USDC_ERR_REG_USDC_WA_ECC_SG_ERR mBIT(5) 800#define VXGE_HAL_USDC_ERR_REG_USDC_CA_ECC_SG_ERR mBIT(6) 801#define VXGE_HAL_USDC_ERR_REG_USDC_SA_ECC_SG_ERR mBIT(7) 802#define VXGE_HAL_USDC_ERR_REG_USDC_FIFO_ECC_DB_ERR mBIT(12) 803#define VXGE_HAL_USDC_ERR_REG_USDC_WA_ECC_DB_ERR mBIT(13) 804#define VXGE_HAL_USDC_ERR_REG_USDC_CA_ECC_DB_ERR mBIT(14) 805#define VXGE_HAL_USDC_ERR_REG_USDC_SA_ECC_DB_ERR mBIT(15) 806#define VXGE_HAL_USDC_ERR_REG_USDC_USDC_SM_ERR_ALARM mBIT(23) 807#define VXGE_HAL_USDC_ERR_REG_USDC_USDC_MISC_ERR_0 mBIT(30) 808#define VXGE_HAL_USDC_ERR_REG_USDC_USDC_MISC_ERR_1 mBIT(31) 809#define VXGE_HAL_USDC_ERR_REG_USDC_USDC_PCI_ERR mBIT(39) 810/* 0x00e30 */ u64 usdc_err_mask; 811/* 0x00e38 */ u64 usdc_err_reg_alarm; 812#define VXGE_HAL_USDC_ERR_REG_ALARM_USDC_FIFO_ECC_SG_ERR mBIT(4) 813#define VXGE_HAL_USDC_ERR_REG_ALARM_USDC_WA_ECC_SG_ERR mBIT(5) 814#define VXGE_HAL_USDC_ERR_REG_ALARM_USDC_CA_ECC_SG_ERR mBIT(6) 815#define VXGE_HAL_USDC_ERR_REG_ALARM_USDC_SA_ECC_SG_ERR mBIT(7) 816#define VXGE_HAL_USDC_ERR_REG_ALARM_USDC_FIFO_ECC_DB_ERR mBIT(12) 817#define VXGE_HAL_USDC_ERR_REG_ALARM_USDC_WA_ECC_DB_ERR mBIT(13) 818#define VXGE_HAL_USDC_ERR_REG_ALARM_USDC_CA_ECC_DB_ERR mBIT(14) 819#define VXGE_HAL_USDC_ERR_REG_ALARM_USDC_SA_ECC_DB_ERR mBIT(15) 820#define VXGE_HAL_USDC_ERR_REG_ALARM_USDC_USDC_SM_ERR_ALARM mBIT(23) 821#define VXGE_HAL_USDC_ERR_REG_ALARM_USDC_USDC_MISC_ERR_0 mBIT(30) 822#define VXGE_HAL_USDC_ERR_REG_ALARM_USDC_USDC_MISC_ERR_1 mBIT(31) 823#define VXGE_HAL_USDC_ERR_REG_ALARM_USDC_USDC_PCI_ERR mBIT(39) 824/* 0x00e40 */ u64 kdfc_vp_partition_0; 825#define VXGE_HAL_KDFC_VP_PARTITION_0_ENABLE mBIT(0) 826#define VXGE_HAL_KDFC_VP_PARTITION_0_NUMBER_0(val) vBIT(val, 5, 3) 827#define VXGE_HAL_KDFC_VP_PARTITION_0_LENGTH_0(val) vBIT(val, 17, 15) 828#define VXGE_HAL_KDFC_VP_PARTITION_0_NUMBER_1(val) vBIT(val, 37, 3) 829#define VXGE_HAL_KDFC_VP_PARTITION_0_LENGTH_1(val) vBIT(val, 49, 15) 830/* 0x00e48 */ u64 kdfc_vp_partition_1; 831#define VXGE_HAL_KDFC_VP_PARTITION_1_NUMBER_2(val) vBIT(val, 5, 3) 832#define VXGE_HAL_KDFC_VP_PARTITION_1_LENGTH_2(val) vBIT(val, 17, 15) 833#define VXGE_HAL_KDFC_VP_PARTITION_1_NUMBER_3(val) vBIT(val, 37, 3) 834#define VXGE_HAL_KDFC_VP_PARTITION_1_LENGTH_3(val) vBIT(val, 49, 15) 835/* 0x00e50 */ u64 kdfc_vp_partition_2; 836#define VXGE_HAL_KDFC_VP_PARTITION_2_NUMBER_4(val) vBIT(val, 5, 3) 837#define VXGE_HAL_KDFC_VP_PARTITION_2_LENGTH_4(val) vBIT(val, 17, 15) 838#define VXGE_HAL_KDFC_VP_PARTITION_2_NUMBER_5(val) vBIT(val, 37, 3) 839#define VXGE_HAL_KDFC_VP_PARTITION_2_LENGTH_5(val) vBIT(val, 49, 15) 840/* 0x00e58 */ u64 kdfc_vp_partition_3; 841#define VXGE_HAL_KDFC_VP_PARTITION_3_NUMBER_6(val) vBIT(val, 5, 3) 842#define VXGE_HAL_KDFC_VP_PARTITION_3_LENGTH_6(val) vBIT(val, 17, 15) 843#define VXGE_HAL_KDFC_VP_PARTITION_3_NUMBER_7(val) vBIT(val, 37, 3) 844#define VXGE_HAL_KDFC_VP_PARTITION_3_LENGTH_7(val) vBIT(val, 49, 15) 845/* 0x00e60 */ u64 kdfc_vp_partition_4; 846#define VXGE_HAL_KDFC_VP_PARTITION_4_LENGTH_8(val) vBIT(val, 17, 15) 847#define VXGE_HAL_KDFC_VP_PARTITION_4_LENGTH_9(val) vBIT(val, 49, 15) 848/* 0x00e68 */ u64 kdfc_vp_partition_5; 849#define VXGE_HAL_KDFC_VP_PARTITION_5_LENGTH_10(val) vBIT(val, 17, 15) 850#define VXGE_HAL_KDFC_VP_PARTITION_5_LENGTH_11(val) vBIT(val, 49, 15) 851/* 0x00e70 */ u64 kdfc_vp_partition_6; 852#define VXGE_HAL_KDFC_VP_PARTITION_6_LENGTH_12(val) vBIT(val, 17, 15) 853#define VXGE_HAL_KDFC_VP_PARTITION_6_LENGTH_13(val) vBIT(val, 49, 15) 854/* 0x00e78 */ u64 kdfc_vp_partition_7; 855#define VXGE_HAL_KDFC_VP_PARTITION_7_LENGTH_14(val) vBIT(val, 17, 15) 856#define VXGE_HAL_KDFC_VP_PARTITION_7_LENGTH_15(val) vBIT(val, 49, 15) 857/* 0x00e80 */ u64 kdfc_vp_partition_8; 858#define VXGE_HAL_KDFC_VP_PARTITION_8_LENGTH_16(val) vBIT(val, 17, 15) 859/* 0x00e88 */ u64 kdfc_w_round_robin_0; 860#define VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_0(val) vBIT(val, 3, 5) 861#define VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_1(val) vBIT(val, 11, 5) 862#define VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_2(val) vBIT(val, 19, 5) 863#define VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_3(val) vBIT(val, 27, 5) 864#define VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_4(val) vBIT(val, 35, 5) 865#define VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_5(val) vBIT(val, 43, 5) 866#define VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_6(val) vBIT(val, 51, 5) 867#define VXGE_HAL_KDFC_W_ROUND_ROBIN_0_NUMBER_7(val) vBIT(val, 59, 5) 868/* 0x00e90 */ u64 kdfc_w_round_robin_1; 869#define VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_8(val) vBIT(val, 3, 5) 870#define VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_9(val) vBIT(val, 11, 5) 871#define VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_10(val) vBIT(val, 19, 5) 872#define VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_11(val) vBIT(val, 27, 5) 873#define VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_12(val) vBIT(val, 35, 5) 874#define VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_13(val) vBIT(val, 43, 5) 875#define VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_14(val) vBIT(val, 51, 5) 876#define VXGE_HAL_KDFC_W_ROUND_ROBIN_1_NUMBER_15(val) vBIT(val, 59, 5) 877/* 0x00e98 */ u64 kdfc_w_round_robin_2; 878#define VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_16(val) vBIT(val, 3, 5) 879#define VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_17(val) vBIT(val, 11, 5) 880#define VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_18(val) vBIT(val, 19, 5) 881#define VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_19(val) vBIT(val, 27, 5) 882#define VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_20(val) vBIT(val, 35, 5) 883#define VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_21(val) vBIT(val, 43, 5) 884#define VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_22(val) vBIT(val, 51, 5) 885#define VXGE_HAL_KDFC_W_ROUND_ROBIN_2_NUMBER_23(val) vBIT(val, 59, 5) 886/* 0x00ea0 */ u64 kdfc_w_round_robin_3; 887#define VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_24(val) vBIT(val, 3, 5) 888#define VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_25(val) vBIT(val, 11, 5) 889#define VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_26(val) vBIT(val, 19, 5) 890#define VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_27(val) vBIT(val, 27, 5) 891#define VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_28(val) vBIT(val, 35, 5) 892#define VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_29(val) vBIT(val, 43, 5) 893#define VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_30(val) vBIT(val, 51, 5) 894#define VXGE_HAL_KDFC_W_ROUND_ROBIN_3_NUMBER_31(val) vBIT(val, 59, 5) 895/* 0x00ea8 */ u64 kdfc_w_round_robin_4; 896#define VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_32(val) vBIT(val, 3, 5) 897#define VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_33(val) vBIT(val, 11, 5) 898#define VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_34(val) vBIT(val, 19, 5) 899#define VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_35(val) vBIT(val, 27, 5) 900#define VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_36(val) vBIT(val, 35, 5) 901#define VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_37(val) vBIT(val, 43, 5) 902#define VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_38(val) vBIT(val, 51, 5) 903#define VXGE_HAL_KDFC_W_ROUND_ROBIN_4_NUMBER_39(val) vBIT(val, 59, 5) 904/* 0x00eb0 */ u64 kdfc_w_round_robin_5; 905#define VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_40(val) vBIT(val, 3, 5) 906#define VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_41(val) vBIT(val, 11, 5) 907#define VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_42(val) vBIT(val, 19, 5) 908#define VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_43(val) vBIT(val, 27, 5) 909#define VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_44(val) vBIT(val, 35, 5) 910#define VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_45(val) vBIT(val, 43, 5) 911#define VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_46(val) vBIT(val, 51, 5) 912#define VXGE_HAL_KDFC_W_ROUND_ROBIN_5_NUMBER_47(val) vBIT(val, 59, 5) 913/* 0x00eb8 */ u64 kdfc_w_round_robin_6; 914#define VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_48(val) vBIT(val, 3, 5) 915#define VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_49(val) vBIT(val, 11, 5) 916#define VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_50(val) vBIT(val, 19, 5) 917#define VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_51(val) vBIT(val, 27, 5) 918#define VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_52(val) vBIT(val, 35, 5) 919#define VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_53(val) vBIT(val, 43, 5) 920#define VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_54(val) vBIT(val, 51, 5) 921#define VXGE_HAL_KDFC_W_ROUND_ROBIN_6_NUMBER_55(val) vBIT(val, 59, 5) 922/* 0x00ec0 */ u64 kdfc_w_round_robin_7; 923#define VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_56(val) vBIT(val, 3, 5) 924#define VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_57(val) vBIT(val, 11, 5) 925#define VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_58(val) vBIT(val, 19, 5) 926#define VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_59(val) vBIT(val, 27, 5) 927#define VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_60(val) vBIT(val, 35, 5) 928#define VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_61(val) vBIT(val, 43, 5) 929#define VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_62(val) vBIT(val, 51, 5) 930#define VXGE_HAL_KDFC_W_ROUND_ROBIN_7_NUMBER_63(val) vBIT(val, 59, 5) 931/* 0x00ec8 */ u64 kdfc_w_round_robin_8; 932#define VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_64(val) vBIT(val, 3, 5) 933#define VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_65(val) vBIT(val, 11, 5) 934#define VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_66(val) vBIT(val, 19, 5) 935#define VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_67(val) vBIT(val, 27, 5) 936#define VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_68(val) vBIT(val, 35, 5) 937#define VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_69(val) vBIT(val, 43, 5) 938#define VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_70(val) vBIT(val, 51, 5) 939#define VXGE_HAL_KDFC_W_ROUND_ROBIN_8_NUMBER_71(val) vBIT(val, 59, 5) 940/* 0x00ed0 */ u64 kdfc_w_round_robin_9; 941#define VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_72(val) vBIT(val, 3, 5) 942#define VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_73(val) vBIT(val, 11, 5) 943#define VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_74(val) vBIT(val, 19, 5) 944#define VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_75(val) vBIT(val, 27, 5) 945#define VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_76(val) vBIT(val, 35, 5) 946#define VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_77(val) vBIT(val, 43, 5) 947#define VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_78(val) vBIT(val, 51, 5) 948#define VXGE_HAL_KDFC_W_ROUND_ROBIN_9_NUMBER_79(val) vBIT(val, 59, 5) 949/* 0x00ed8 */ u64 kdfc_w_round_robin_10; 950#define VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_80(val) vBIT(val, 3, 5) 951#define VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_81(val) vBIT(val, 11, 5) 952#define VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_82(val) vBIT(val, 19, 5) 953#define VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_83(val) vBIT(val, 27, 5) 954#define VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_84(val) vBIT(val, 35, 5) 955#define VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_85(val) vBIT(val, 43, 5) 956#define VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_86(val) vBIT(val, 51, 5) 957#define VXGE_HAL_KDFC_W_ROUND_ROBIN_10_NUMBER_87(val) vBIT(val, 59, 5) 958/* 0x00ee0 */ u64 kdfc_w_round_robin_11; 959#define VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_88(val) vBIT(val, 3, 5) 960#define VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_89(val) vBIT(val, 11, 5) 961#define VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_90(val) vBIT(val, 19, 5) 962#define VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_91(val) vBIT(val, 27, 5) 963#define VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_92(val) vBIT(val, 35, 5) 964#define VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_93(val) vBIT(val, 43, 5) 965#define VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_94(val) vBIT(val, 51, 5) 966#define VXGE_HAL_KDFC_W_ROUND_ROBIN_11_NUMBER_95(val) vBIT(val, 59, 5) 967/* 0x00ee8 */ u64 kdfc_w_round_robin_12; 968#define VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_96(val) vBIT(val, 3, 5) 969#define VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_97(val) vBIT(val, 11, 5) 970#define VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_98(val) vBIT(val, 19, 5) 971#define VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_99(val) vBIT(val, 27, 5) 972#define VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_100(val) vBIT(val, 35, 5) 973#define VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_101(val) vBIT(val, 43, 5) 974#define VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_102(val) vBIT(val, 51, 5) 975#define VXGE_HAL_KDFC_W_ROUND_ROBIN_12_NUMBER_103(val) vBIT(val, 59, 5) 976/* 0x00ef0 */ u64 kdfc_w_round_robin_13; 977#define VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_104(val) vBIT(val, 3, 5) 978#define VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_105(val) vBIT(val, 11, 5) 979#define VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_106(val) vBIT(val, 19, 5) 980#define VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_107(val) vBIT(val, 27, 5) 981#define VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_108(val) vBIT(val, 35, 5) 982#define VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_109(val) vBIT(val, 43, 5) 983#define VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_110(val) vBIT(val, 51, 5) 984#define VXGE_HAL_KDFC_W_ROUND_ROBIN_13_NUMBER_111(val) vBIT(val, 59, 5) 985/* 0x00ef8 */ u64 kdfc_w_round_robin_14; 986#define VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_112(val) vBIT(val, 3, 5) 987#define VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_113(val) vBIT(val, 11, 5) 988#define VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_114(val) vBIT(val, 19, 5) 989#define VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_115(val) vBIT(val, 27, 5) 990#define VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_116(val) vBIT(val, 35, 5) 991#define VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_117(val) vBIT(val, 43, 5) 992#define VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_118(val) vBIT(val, 51, 5) 993#define VXGE_HAL_KDFC_W_ROUND_ROBIN_14_NUMBER_119(val) vBIT(val, 59, 5) 994/* 0x00f00 */ u64 kdfc_w_round_robin_15; 995#define VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_120(val) vBIT(val, 3, 5) 996#define VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_121(val) vBIT(val, 11, 5) 997#define VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_122(val) vBIT(val, 19, 5) 998#define VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_123(val) vBIT(val, 27, 5) 999#define VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_124(val) vBIT(val, 35, 5) 1000#define VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_125(val) vBIT(val, 43, 5) 1001#define VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_126(val) vBIT(val, 51, 5) 1002#define VXGE_HAL_KDFC_W_ROUND_ROBIN_15_NUMBER_127(val) vBIT(val, 59, 5) 1003/* 0x00f08 */ u64 kdfc_w_round_robin_16; 1004#define VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_128(val) vBIT(val, 3, 5) 1005#define VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_129(val) vBIT(val, 11, 5) 1006#define VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_130(val) vBIT(val, 19, 5) 1007#define VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_131(val) vBIT(val, 27, 5) 1008#define VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_132(val) vBIT(val, 35, 5) 1009#define VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_133(val) vBIT(val, 43, 5) 1010#define VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_134(val) vBIT(val, 51, 5) 1011#define VXGE_HAL_KDFC_W_ROUND_ROBIN_16_NUMBER_135(val) vBIT(val, 59, 5) 1012/* 0x00f10 */ u64 kdfc_w_round_robin_17; 1013#define VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_136(val) vBIT(val, 3, 5) 1014#define VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_137(val) vBIT(val, 11, 5) 1015#define VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_138(val) vBIT(val, 19, 5) 1016#define VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_139(val) vBIT(val, 27, 5) 1017#define VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_140(val) vBIT(val, 35, 5) 1018#define VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_141(val) vBIT(val, 43, 5) 1019#define VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_142(val) vBIT(val, 51, 5) 1020#define VXGE_HAL_KDFC_W_ROUND_ROBIN_17_NUMBER_143(val) vBIT(val, 59, 5) 1021/* 0x00f18 */ u64 kdfc_w_round_robin_18; 1022#define VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_144(val) vBIT(val, 3, 5) 1023#define VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_145(val) vBIT(val, 11, 5) 1024#define VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_146(val) vBIT(val, 19, 5) 1025#define VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_147(val) vBIT(val, 27, 5) 1026#define VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_148(val) vBIT(val, 35, 5) 1027#define VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_149(val) vBIT(val, 43, 5) 1028#define VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_150(val) vBIT(val, 51, 5) 1029#define VXGE_HAL_KDFC_W_ROUND_ROBIN_18_NUMBER_151(val) vBIT(val, 59, 5) 1030/* 0x00f20 */ u64 kdfc_w_round_robin_19; 1031#define VXGE_HAL_KDFC_W_ROUND_ROBIN_19_NUMBER_152(val) vBIT(val, 3, 5) 1032/* 0x00f28 */ u64 kdfc_w_round_robin_20; 1033#define VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_0(val) vBIT(val, 3, 5) 1034#define VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_1(val) vBIT(val, 11, 5) 1035#define VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_2(val) vBIT(val, 19, 5) 1036#define VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_3(val) vBIT(val, 27, 5) 1037#define VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_4(val) vBIT(val, 35, 5) 1038#define VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_5(val) vBIT(val, 43, 5) 1039#define VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_6(val) vBIT(val, 51, 5) 1040#define VXGE_HAL_KDFC_W_ROUND_ROBIN_20_NUMBER_7(val) vBIT(val, 59, 5) 1041/* 0x00f30 */ u64 kdfc_w_round_robin_21; 1042#define VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_8(val) vBIT(val, 3, 5) 1043#define VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_9(val) vBIT(val, 11, 5) 1044#define VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_10(val) vBIT(val, 19, 5) 1045#define VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_11(val) vBIT(val, 27, 5) 1046#define VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_12(val) vBIT(val, 35, 5) 1047#define VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_13(val) vBIT(val, 43, 5) 1048#define VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_14(val) vBIT(val, 51, 5) 1049#define VXGE_HAL_KDFC_W_ROUND_ROBIN_21_NUMBER_15(val) vBIT(val, 59, 5) 1050/* 0x00f38 */ u64 kdfc_w_round_robin_22; 1051#define VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_16(val) vBIT(val, 3, 5) 1052#define VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_17(val) vBIT(val, 11, 5) 1053#define VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_18(val) vBIT(val, 19, 5) 1054#define VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_19(val) vBIT(val, 27, 5) 1055#define VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_20(val) vBIT(val, 35, 5) 1056#define VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_21(val) vBIT(val, 43, 5) 1057#define VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_22(val) vBIT(val, 51, 5) 1058#define VXGE_HAL_KDFC_W_ROUND_ROBIN_22_NUMBER_23(val) vBIT(val, 59, 5) 1059/* 0x00f40 */ u64 kdfc_w_round_robin_23; 1060#define VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_24(val) vBIT(val, 3, 5) 1061#define VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_25(val) vBIT(val, 11, 5) 1062#define VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_26(val) vBIT(val, 19, 5) 1063#define VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_27(val) vBIT(val, 27, 5) 1064#define VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_28(val) vBIT(val, 35, 5) 1065#define VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_29(val) vBIT(val, 43, 5) 1066#define VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_30(val) vBIT(val, 51, 5) 1067#define VXGE_HAL_KDFC_W_ROUND_ROBIN_23_NUMBER_31(val) vBIT(val, 59, 5) 1068/* 0x00f48 */ u64 kdfc_w_round_robin_24; 1069#define VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_32(val) vBIT(val, 3, 5) 1070#define VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_33(val) vBIT(val, 11, 5) 1071#define VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_34(val) vBIT(val, 19, 5) 1072#define VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_35(val) vBIT(val, 27, 5) 1073#define VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_36(val) vBIT(val, 35, 5) 1074#define VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_37(val) vBIT(val, 43, 5) 1075#define VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_38(val) vBIT(val, 51, 5) 1076#define VXGE_HAL_KDFC_W_ROUND_ROBIN_24_NUMBER_39(val) vBIT(val, 59, 5) 1077/* 0x00f50 */ u64 kdfc_w_round_robin_25; 1078#define VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_40(val) vBIT(val, 3, 5) 1079#define VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_41(val) vBIT(val, 11, 5) 1080#define VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_42(val) vBIT(val, 19, 5) 1081#define VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_43(val) vBIT(val, 27, 5) 1082#define VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_44(val) vBIT(val, 35, 5) 1083#define VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_45(val) vBIT(val, 43, 5) 1084#define VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_46(val) vBIT(val, 51, 5) 1085#define VXGE_HAL_KDFC_W_ROUND_ROBIN_25_NUMBER_47(val) vBIT(val, 59, 5) 1086/* 0x00f58 */ u64 kdfc_w_round_robin_26; 1087#define VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_48(val) vBIT(val, 3, 5) 1088#define VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_49(val) vBIT(val, 11, 5) 1089#define VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_50(val) vBIT(val, 19, 5) 1090#define VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_51(val) vBIT(val, 27, 5) 1091#define VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_52(val) vBIT(val, 35, 5) 1092#define VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_53(val) vBIT(val, 43, 5) 1093#define VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_54(val) vBIT(val, 51, 5) 1094#define VXGE_HAL_KDFC_W_ROUND_ROBIN_26_NUMBER_55(val) vBIT(val, 59, 5) 1095/* 0x00f60 */ u64 kdfc_w_round_robin_27; 1096#define VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_56(val) vBIT(val, 3, 5) 1097#define VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_57(val) vBIT(val, 11, 5) 1098#define VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_58(val) vBIT(val, 19, 5) 1099#define VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_59(val) vBIT(val, 27, 5) 1100#define VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_60(val) vBIT(val, 35, 5) 1101#define VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_61(val) vBIT(val, 43, 5) 1102#define VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_62(val) vBIT(val, 51, 5) 1103#define VXGE_HAL_KDFC_W_ROUND_ROBIN_27_NUMBER_63(val) vBIT(val, 59, 5) 1104/* 0x00f68 */ u64 kdfc_w_round_robin_28; 1105#define VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_64(val) vBIT(val, 3, 5) 1106#define VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_65(val) vBIT(val, 11, 5) 1107#define VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_66(val) vBIT(val, 19, 5) 1108#define VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_67(val) vBIT(val, 27, 5) 1109#define VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_68(val) vBIT(val, 35, 5) 1110#define VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_69(val) vBIT(val, 43, 5) 1111#define VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_70(val) vBIT(val, 51, 5) 1112#define VXGE_HAL_KDFC_W_ROUND_ROBIN_28_NUMBER_71(val) vBIT(val, 59, 5) 1113/* 0x00f70 */ u64 kdfc_w_round_robin_29; 1114#define VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_72(val) vBIT(val, 3, 5) 1115#define VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_73(val) vBIT(val, 11, 5) 1116#define VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_74(val) vBIT(val, 19, 5) 1117#define VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_75(val) vBIT(val, 27, 5) 1118#define VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_76(val) vBIT(val, 35, 5) 1119#define VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_77(val) vBIT(val, 43, 5) 1120#define VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_78(val) vBIT(val, 51, 5) 1121#define VXGE_HAL_KDFC_W_ROUND_ROBIN_29_NUMBER_79(val) vBIT(val, 59, 5) 1122/* 0x00f78 */ u64 kdfc_w_round_robin_30; 1123#define VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_80(val) vBIT(val, 3, 5) 1124#define VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_81(val) vBIT(val, 11, 5) 1125#define VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_82(val) vBIT(val, 19, 5) 1126#define VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_83(val) vBIT(val, 27, 5) 1127#define VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_84(val) vBIT(val, 35, 5) 1128#define VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_85(val) vBIT(val, 43, 5) 1129#define VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_86(val) vBIT(val, 51, 5) 1130#define VXGE_HAL_KDFC_W_ROUND_ROBIN_30_NUMBER_87(val) vBIT(val, 59, 5) 1131/* 0x00f80 */ u64 kdfc_w_round_robin_31; 1132#define VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_88(val) vBIT(val, 3, 5) 1133#define VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_89(val) vBIT(val, 11, 5) 1134#define VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_90(val) vBIT(val, 19, 5) 1135#define VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_91(val) vBIT(val, 27, 5) 1136#define VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_92(val) vBIT(val, 35, 5) 1137#define VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_93(val) vBIT(val, 43, 5) 1138#define VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_94(val) vBIT(val, 51, 5) 1139#define VXGE_HAL_KDFC_W_ROUND_ROBIN_31_NUMBER_95(val) vBIT(val, 59, 5) 1140/* 0x00f88 */ u64 kdfc_w_round_robin_32; 1141#define VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_96(val) vBIT(val, 3, 5) 1142#define VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_97(val) vBIT(val, 11, 5) 1143#define VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_98(val) vBIT(val, 19, 5) 1144#define VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_99(val) vBIT(val, 27, 5) 1145#define VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_100(val) vBIT(val, 35, 5) 1146#define VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_101(val) vBIT(val, 43, 5) 1147#define VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_102(val) vBIT(val, 51, 5) 1148#define VXGE_HAL_KDFC_W_ROUND_ROBIN_32_NUMBER_103(val) vBIT(val, 59, 5) 1149/* 0x00f90 */ u64 kdfc_w_round_robin_33; 1150#define VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_104(val) vBIT(val, 3, 5) 1151#define VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_105(val) vBIT(val, 11, 5) 1152#define VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_106(val) vBIT(val, 19, 5) 1153#define VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_107(val) vBIT(val, 27, 5) 1154#define VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_108(val) vBIT(val, 35, 5) 1155#define VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_109(val) vBIT(val, 43, 5) 1156#define VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_110(val) vBIT(val, 51, 5) 1157#define VXGE_HAL_KDFC_W_ROUND_ROBIN_33_NUMBER_111(val) vBIT(val, 59, 5) 1158/* 0x00f98 */ u64 kdfc_w_round_robin_34; 1159#define VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_112(val) vBIT(val, 3, 5) 1160#define VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_113(val) vBIT(val, 11, 5) 1161#define VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_114(val) vBIT(val, 19, 5) 1162#define VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_115(val) vBIT(val, 27, 5) 1163#define VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_116(val) vBIT(val, 35, 5) 1164#define VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_117(val) vBIT(val, 43, 5) 1165#define VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_118(val) vBIT(val, 51, 5) 1166#define VXGE_HAL_KDFC_W_ROUND_ROBIN_34_NUMBER_119(val) vBIT(val, 59, 5) 1167/* 0x00fa0 */ u64 kdfc_w_round_robin_35; 1168#define VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_120(val) vBIT(val, 3, 5) 1169#define VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_121(val) vBIT(val, 11, 5) 1170#define VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_122(val) vBIT(val, 19, 5) 1171#define VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_123(val) vBIT(val, 27, 5) 1172#define VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_124(val) vBIT(val, 35, 5) 1173#define VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_125(val) vBIT(val, 43, 5) 1174#define VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_126(val) vBIT(val, 51, 5) 1175#define VXGE_HAL_KDFC_W_ROUND_ROBIN_35_NUMBER_127(val) vBIT(val, 59, 5) 1176/* 0x00fa8 */ u64 kdfc_w_round_robin_36; 1177#define VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_128(val) vBIT(val, 3, 5) 1178#define VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_129(val) vBIT(val, 11, 5) 1179#define VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_130(val) vBIT(val, 19, 5) 1180#define VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_131(val) vBIT(val, 27, 5) 1181#define VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_132(val) vBIT(val, 35, 5) 1182#define VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_133(val) vBIT(val, 43, 5) 1183#define VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_134(val) vBIT(val, 51, 5) 1184#define VXGE_HAL_KDFC_W_ROUND_ROBIN_36_NUMBER_135(val) vBIT(val, 59, 5) 1185/* 0x00fb0 */ u64 kdfc_w_round_robin_37; 1186#define VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_136(val) vBIT(val, 3, 5) 1187#define VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_137(val) vBIT(val, 11, 5) 1188#define VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_138(val) vBIT(val, 19, 5) 1189#define VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_139(val) vBIT(val, 27, 5) 1190#define VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_140(val) vBIT(val, 35, 5) 1191#define VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_141(val) vBIT(val, 43, 5) 1192#define VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_142(val) vBIT(val, 51, 5) 1193#define VXGE_HAL_KDFC_W_ROUND_ROBIN_37_NUMBER_143(val) vBIT(val, 59, 5) 1194/* 0x00fb8 */ u64 kdfc_w_round_robin_38; 1195#define VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_144(val) vBIT(val, 3, 5) 1196#define VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_145(val) vBIT(val, 11, 5) 1197#define VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_146(val) vBIT(val, 19, 5) 1198#define VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_147(val) vBIT(val, 27, 5) 1199#define VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_148(val) vBIT(val, 35, 5) 1200#define VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_149(val) vBIT(val, 43, 5) 1201#define VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_150(val) vBIT(val, 51, 5) 1202#define VXGE_HAL_KDFC_W_ROUND_ROBIN_38_NUMBER_151(val) vBIT(val, 59, 5) 1203/* 0x00fc0 */ u64 kdfc_w_round_robin_39; 1204#define VXGE_HAL_KDFC_W_ROUND_ROBIN_39_NUMBER_152(val) vBIT(val, 3, 5) 1205/* 0x00fc8 */ u64 kdfc_w_round_robin_40; 1206#define VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_0(val) vBIT(val, 3, 5) 1207#define VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_1(val) vBIT(val, 11, 5) 1208#define VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_2(val) vBIT(val, 19, 5) 1209#define VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_3(val) vBIT(val, 27, 5) 1210#define VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_4(val) vBIT(val, 35, 5) 1211#define VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_5(val) vBIT(val, 43, 5) 1212#define VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_6(val) vBIT(val, 51, 5) 1213#define VXGE_HAL_KDFC_W_ROUND_ROBIN_40_NUMBER_7(val) vBIT(val, 59, 5) 1214/* 0x00fd0 */ u64 kdfc_w_round_robin_41; 1215#define VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_8(val) vBIT(val, 3, 5) 1216#define VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_9(val) vBIT(val, 11, 5) 1217#define VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_10(val) vBIT(val, 19, 5) 1218#define VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_11(val) vBIT(val, 27, 5) 1219#define VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_12(val) vBIT(val, 35, 5) 1220#define VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_13(val) vBIT(val, 43, 5) 1221#define VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_14(val) vBIT(val, 51, 5) 1222#define VXGE_HAL_KDFC_W_ROUND_ROBIN_41_NUMBER_15(val) vBIT(val, 59, 5) 1223/* 0x00fd8 */ u64 kdfc_w_round_robin_42; 1224#define VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_16(val) vBIT(val, 3, 5) 1225#define VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_17(val) vBIT(val, 11, 5) 1226#define VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_18(val) vBIT(val, 19, 5) 1227#define VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_19(val) vBIT(val, 27, 5) 1228#define VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_20(val) vBIT(val, 35, 5) 1229#define VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_21(val) vBIT(val, 43, 5) 1230#define VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_22(val) vBIT(val, 51, 5) 1231#define VXGE_HAL_KDFC_W_ROUND_ROBIN_42_NUMBER_23(val) vBIT(val, 59, 5) 1232/* 0x00fe0 */ u64 kdfc_w_round_robin_43; 1233#define VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_24(val) vBIT(val, 3, 5) 1234#define VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_25(val) vBIT(val, 11, 5) 1235#define VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_26(val) vBIT(val, 19, 5) 1236#define VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_27(val) vBIT(val, 27, 5) 1237#define VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_28(val) vBIT(val, 35, 5) 1238#define VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_29(val) vBIT(val, 43, 5) 1239#define VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_30(val) vBIT(val, 51, 5) 1240#define VXGE_HAL_KDFC_W_ROUND_ROBIN_43_NUMBER_31(val) vBIT(val, 59, 5) 1241/* 0x00fe8 */ u64 kdfc_w_round_robin_44; 1242#define VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_32(val) vBIT(val, 3, 5) 1243#define VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_33(val) vBIT(val, 11, 5) 1244#define VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_34(val) vBIT(val, 19, 5) 1245#define VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_35(val) vBIT(val, 27, 5) 1246#define VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_36(val) vBIT(val, 35, 5) 1247#define VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_37(val) vBIT(val, 43, 5) 1248#define VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_38(val) vBIT(val, 51, 5) 1249#define VXGE_HAL_KDFC_W_ROUND_ROBIN_44_NUMBER_39(val) vBIT(val, 59, 5) 1250/* 0x00ff0 */ u64 kdfc_w_round_robin_45; 1251#define VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_40(val) vBIT(val, 3, 5) 1252#define VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_41(val) vBIT(val, 11, 5) 1253#define VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_42(val) vBIT(val, 19, 5) 1254#define VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_43(val) vBIT(val, 27, 5) 1255#define VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_44(val) vBIT(val, 35, 5) 1256#define VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_45(val) vBIT(val, 43, 5) 1257#define VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_46(val) vBIT(val, 51, 5) 1258#define VXGE_HAL_KDFC_W_ROUND_ROBIN_45_NUMBER_47(val) vBIT(val, 59, 5) 1259/* 0x00ff8 */ u64 kdfc_w_round_robin_46; 1260#define VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_48(val) vBIT(val, 3, 5) 1261#define VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_49(val) vBIT(val, 11, 5) 1262#define VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_50(val) vBIT(val, 19, 5) 1263#define VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_51(val) vBIT(val, 27, 5) 1264#define VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_52(val) vBIT(val, 35, 5) 1265#define VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_53(val) vBIT(val, 43, 5) 1266#define VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_54(val) vBIT(val, 51, 5) 1267#define VXGE_HAL_KDFC_W_ROUND_ROBIN_46_NUMBER_55(val) vBIT(val, 59, 5) 1268/* 0x01000 */ u64 kdfc_w_round_robin_47; 1269#define VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_56(val) vBIT(val, 3, 5) 1270#define VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_57(val) vBIT(val, 11, 5) 1271#define VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_58(val) vBIT(val, 19, 5) 1272#define VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_59(val) vBIT(val, 27, 5) 1273#define VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_60(val) vBIT(val, 35, 5) 1274#define VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_61(val) vBIT(val, 43, 5) 1275#define VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_62(val) vBIT(val, 51, 5) 1276#define VXGE_HAL_KDFC_W_ROUND_ROBIN_47_NUMBER_63(val) vBIT(val, 59, 5) 1277/* 0x01008 */ u64 kdfc_w_round_robin_48; 1278#define VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_64(val) vBIT(val, 3, 5) 1279#define VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_65(val) vBIT(val, 11, 5) 1280#define VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_66(val) vBIT(val, 19, 5) 1281#define VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_67(val) vBIT(val, 27, 5) 1282#define VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_68(val) vBIT(val, 35, 5) 1283#define VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_69(val) vBIT(val, 43, 5) 1284#define VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_70(val) vBIT(val, 51, 5) 1285#define VXGE_HAL_KDFC_W_ROUND_ROBIN_48_NUMBER_71(val) vBIT(val, 59, 5) 1286/* 0x01010 */ u64 kdfc_w_round_robin_49; 1287#define VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_72(val) vBIT(val, 3, 5) 1288#define VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_73(val) vBIT(val, 11, 5) 1289#define VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_74(val) vBIT(val, 19, 5) 1290#define VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_75(val) vBIT(val, 27, 5) 1291#define VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_76(val) vBIT(val, 35, 5) 1292#define VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_77(val) vBIT(val, 43, 5) 1293#define VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_78(val) vBIT(val, 51, 5) 1294#define VXGE_HAL_KDFC_W_ROUND_ROBIN_49_NUMBER_79(val) vBIT(val, 59, 5) 1295/* 0x01018 */ u64 kdfc_w_round_robin_50; 1296#define VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_80(val) vBIT(val, 3, 5) 1297#define VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_81(val) vBIT(val, 11, 5) 1298#define VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_82(val) vBIT(val, 19, 5) 1299#define VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_83(val) vBIT(val, 27, 5) 1300#define VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_84(val) vBIT(val, 35, 5) 1301#define VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_85(val) vBIT(val, 43, 5) 1302#define VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_86(val) vBIT(val, 51, 5) 1303#define VXGE_HAL_KDFC_W_ROUND_ROBIN_50_NUMBER_87(val) vBIT(val, 59, 5) 1304/* 0x01020 */ u64 kdfc_w_round_robin_51; 1305#define VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_88(val) vBIT(val, 3, 5) 1306#define VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_89(val) vBIT(val, 11, 5) 1307#define VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_90(val) vBIT(val, 19, 5) 1308#define VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_91(val) vBIT(val, 27, 5) 1309#define VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_92(val) vBIT(val, 35, 5) 1310#define VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_93(val) vBIT(val, 43, 5) 1311#define VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_94(val) vBIT(val, 51, 5) 1312#define VXGE_HAL_KDFC_W_ROUND_ROBIN_51_NUMBER_95(val) vBIT(val, 59, 5) 1313/* 0x01028 */ u64 kdfc_w_round_robin_52; 1314#define VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_96(val) vBIT(val, 3, 5) 1315#define VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_97(val) vBIT(val, 11, 5) 1316#define VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_98(val) vBIT(val, 19, 5) 1317#define VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_99(val) vBIT(val, 27, 5) 1318#define VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_100(val) vBIT(val, 35, 5) 1319#define VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_101(val) vBIT(val, 43, 5) 1320#define VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_102(val) vBIT(val, 51, 5) 1321#define VXGE_HAL_KDFC_W_ROUND_ROBIN_52_NUMBER_103(val) vBIT(val, 59, 5) 1322/* 0x01030 */ u64 kdfc_w_round_robin_53; 1323#define VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_104(val) vBIT(val, 3, 5) 1324#define VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_105(val) vBIT(val, 11, 5) 1325#define VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_106(val) vBIT(val, 19, 5) 1326#define VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_107(val) vBIT(val, 27, 5) 1327#define VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_108(val) vBIT(val, 35, 5) 1328#define VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_109(val) vBIT(val, 43, 5) 1329#define VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_110(val) vBIT(val, 51, 5) 1330#define VXGE_HAL_KDFC_W_ROUND_ROBIN_53_NUMBER_111(val) vBIT(val, 59, 5) 1331/* 0x01038 */ u64 kdfc_w_round_robin_54; 1332#define VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_112(val) vBIT(val, 3, 5) 1333#define VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_113(val) vBIT(val, 11, 5) 1334#define VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_114(val) vBIT(val, 19, 5) 1335#define VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_115(val) vBIT(val, 27, 5) 1336#define VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_116(val) vBIT(val, 35, 5) 1337#define VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_117(val) vBIT(val, 43, 5) 1338#define VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_118(val) vBIT(val, 51, 5) 1339#define VXGE_HAL_KDFC_W_ROUND_ROBIN_54_NUMBER_119(val) vBIT(val, 59, 5) 1340/* 0x01040 */ u64 kdfc_w_round_robin_55; 1341#define VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_120(val) vBIT(val, 3, 5) 1342#define VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_121(val) vBIT(val, 11, 5) 1343#define VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_122(val) vBIT(val, 19, 5) 1344#define VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_123(val) vBIT(val, 27, 5) 1345#define VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_124(val) vBIT(val, 35, 5) 1346#define VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_125(val) vBIT(val, 43, 5) 1347#define VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_126(val) vBIT(val, 51, 5) 1348#define VXGE_HAL_KDFC_W_ROUND_ROBIN_55_NUMBER_127(val) vBIT(val, 59, 5) 1349/* 0x01048 */ u64 kdfc_w_round_robin_56; 1350#define VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_128(val) vBIT(val, 3, 5) 1351#define VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_129(val) vBIT(val, 11, 5) 1352#define VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_130(val) vBIT(val, 19, 5) 1353#define VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_131(val) vBIT(val, 27, 5) 1354#define VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_132(val) vBIT(val, 35, 5) 1355#define VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_133(val) vBIT(val, 43, 5) 1356#define VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_134(val) vBIT(val, 51, 5) 1357#define VXGE_HAL_KDFC_W_ROUND_ROBIN_56_NUMBER_135(val) vBIT(val, 59, 5) 1358/* 0x01050 */ u64 kdfc_w_round_robin_57; 1359#define VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_136(val) vBIT(val, 3, 5) 1360#define VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_137(val) vBIT(val, 11, 5) 1361#define VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_138(val) vBIT(val, 19, 5) 1362#define VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_139(val) vBIT(val, 27, 5) 1363#define VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_140(val) vBIT(val, 35, 5) 1364#define VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_141(val) vBIT(val, 43, 5) 1365#define VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_142(val) vBIT(val, 51, 5) 1366#define VXGE_HAL_KDFC_W_ROUND_ROBIN_57_NUMBER_143(val) vBIT(val, 59, 5) 1367/* 0x01058 */ u64 kdfc_w_round_robin_58; 1368#define VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_144(val) vBIT(val, 3, 5) 1369#define VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_145(val) vBIT(val, 11, 5) 1370#define VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_146(val) vBIT(val, 19, 5) 1371#define VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_147(val) vBIT(val, 27, 5) 1372#define VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_148(val) vBIT(val, 35, 5) 1373#define VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_149(val) vBIT(val, 43, 5) 1374#define VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_150(val) vBIT(val, 51, 5) 1375#define VXGE_HAL_KDFC_W_ROUND_ROBIN_58_NUMBER_151(val) vBIT(val, 59, 5) 1376/* 0x01060 */ u64 kdfc_w_round_robin_59; 1377#define VXGE_HAL_KDFC_W_ROUND_ROBIN_59_NUMBER_152(val) vBIT(val, 3, 5) 1378/* 0x01068 */ u64 kdfc_entry_type_sel_0; 1379#define VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_0(val) vBIT(val, 6, 2) 1380#define VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_1(val) vBIT(val, 14, 2) 1381#define VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_2(val) vBIT(val, 22, 2) 1382#define VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_3(val) vBIT(val, 30, 2) 1383#define VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_4(val) vBIT(val, 38, 2) 1384#define VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_5(val) vBIT(val, 46, 2) 1385#define VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_6(val) vBIT(val, 54, 2) 1386#define VXGE_HAL_KDFC_ENTRY_TYPE_SEL_0_NUMBER_7(val) vBIT(val, 62, 2) 1387/* 0x01070 */ u64 kdfc_entry_type_sel_1; 1388#define VXGE_HAL_KDFC_ENTRY_TYPE_SEL_1_NUMBER_8(val) vBIT(val, 6, 2) 1389/* 0x01078 */ u64 kdfc_fifo_0_ctrl; 1390#define VXGE_HAL_KDFC_FIFO_0_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1391/* 0x01080 */ u64 kdfc_fifo_1_ctrl; 1392#define VXGE_HAL_KDFC_FIFO_1_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1393/* 0x01088 */ u64 kdfc_fifo_2_ctrl; 1394#define VXGE_HAL_KDFC_FIFO_2_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1395/* 0x01090 */ u64 kdfc_fifo_3_ctrl; 1396#define VXGE_HAL_KDFC_FIFO_3_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1397/* 0x01098 */ u64 kdfc_fifo_4_ctrl; 1398#define VXGE_HAL_KDFC_FIFO_4_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1399/* 0x010a0 */ u64 kdfc_fifo_5_ctrl; 1400#define VXGE_HAL_KDFC_FIFO_5_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1401/* 0x010a8 */ u64 kdfc_fifo_6_ctrl; 1402#define VXGE_HAL_KDFC_FIFO_6_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1403/* 0x010b0 */ u64 kdfc_fifo_7_ctrl; 1404#define VXGE_HAL_KDFC_FIFO_7_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1405/* 0x010b8 */ u64 kdfc_fifo_8_ctrl; 1406#define VXGE_HAL_KDFC_FIFO_8_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1407/* 0x010c0 */ u64 kdfc_fifo_9_ctrl; 1408#define VXGE_HAL_KDFC_FIFO_9_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1409/* 0x010c8 */ u64 kdfc_fifo_10_ctrl; 1410#define VXGE_HAL_KDFC_FIFO_10_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1411/* 0x010d0 */ u64 kdfc_fifo_11_ctrl; 1412#define VXGE_HAL_KDFC_FIFO_11_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1413/* 0x010d8 */ u64 kdfc_fifo_12_ctrl; 1414#define VXGE_HAL_KDFC_FIFO_12_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1415/* 0x010e0 */ u64 kdfc_fifo_13_ctrl; 1416#define VXGE_HAL_KDFC_FIFO_13_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1417/* 0x010e8 */ u64 kdfc_fifo_14_ctrl; 1418#define VXGE_HAL_KDFC_FIFO_14_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1419/* 0x010f0 */ u64 kdfc_fifo_15_ctrl; 1420#define VXGE_HAL_KDFC_FIFO_15_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1421/* 0x010f8 */ u64 kdfc_fifo_16_ctrl; 1422#define VXGE_HAL_KDFC_FIFO_16_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1423/* 0x01100 */ u64 kdfc_fifo_17_ctrl; 1424#define VXGE_HAL_KDFC_FIFO_17_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1425/* 0x01108 */ u64 kdfc_fifo_18_ctrl; 1426#define VXGE_HAL_KDFC_FIFO_18_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1427/* 0x01110 */ u64 kdfc_fifo_19_ctrl; 1428#define VXGE_HAL_KDFC_FIFO_19_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1429/* 0x01118 */ u64 kdfc_fifo_20_ctrl; 1430#define VXGE_HAL_KDFC_FIFO_20_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1431/* 0x01120 */ u64 kdfc_fifo_21_ctrl; 1432#define VXGE_HAL_KDFC_FIFO_21_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1433/* 0x01128 */ u64 kdfc_fifo_22_ctrl; 1434#define VXGE_HAL_KDFC_FIFO_22_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1435/* 0x01130 */ u64 kdfc_fifo_23_ctrl; 1436#define VXGE_HAL_KDFC_FIFO_23_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1437/* 0x01138 */ u64 kdfc_fifo_24_ctrl; 1438#define VXGE_HAL_KDFC_FIFO_24_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1439/* 0x01140 */ u64 kdfc_fifo_25_ctrl; 1440#define VXGE_HAL_KDFC_FIFO_25_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1441/* 0x01148 */ u64 kdfc_fifo_26_ctrl; 1442#define VXGE_HAL_KDFC_FIFO_26_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1443/* 0x01150 */ u64 kdfc_fifo_27_ctrl; 1444#define VXGE_HAL_KDFC_FIFO_27_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1445/* 0x01158 */ u64 kdfc_fifo_28_ctrl; 1446#define VXGE_HAL_KDFC_FIFO_28_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1447/* 0x01160 */ u64 kdfc_fifo_29_ctrl; 1448#define VXGE_HAL_KDFC_FIFO_29_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1449/* 0x01168 */ u64 kdfc_fifo_30_ctrl; 1450#define VXGE_HAL_KDFC_FIFO_30_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1451/* 0x01170 */ u64 kdfc_fifo_31_ctrl; 1452#define VXGE_HAL_KDFC_FIFO_31_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1453/* 0x01178 */ u64 kdfc_fifo_32_ctrl; 1454#define VXGE_HAL_KDFC_FIFO_32_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1455/* 0x01180 */ u64 kdfc_fifo_33_ctrl; 1456#define VXGE_HAL_KDFC_FIFO_33_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1457/* 0x01188 */ u64 kdfc_fifo_34_ctrl; 1458#define VXGE_HAL_KDFC_FIFO_34_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1459/* 0x01190 */ u64 kdfc_fifo_35_ctrl; 1460#define VXGE_HAL_KDFC_FIFO_35_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1461/* 0x01198 */ u64 kdfc_fifo_36_ctrl; 1462#define VXGE_HAL_KDFC_FIFO_36_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1463/* 0x011a0 */ u64 kdfc_fifo_37_ctrl; 1464#define VXGE_HAL_KDFC_FIFO_37_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1465/* 0x011a8 */ u64 kdfc_fifo_38_ctrl; 1466#define VXGE_HAL_KDFC_FIFO_38_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1467/* 0x011b0 */ u64 kdfc_fifo_39_ctrl; 1468#define VXGE_HAL_KDFC_FIFO_39_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1469/* 0x011b8 */ u64 kdfc_fifo_40_ctrl; 1470#define VXGE_HAL_KDFC_FIFO_40_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1471/* 0x011c0 */ u64 kdfc_fifo_41_ctrl; 1472#define VXGE_HAL_KDFC_FIFO_41_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1473/* 0x011c8 */ u64 kdfc_fifo_42_ctrl; 1474#define VXGE_HAL_KDFC_FIFO_42_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1475/* 0x011d0 */ u64 kdfc_fifo_43_ctrl; 1476#define VXGE_HAL_KDFC_FIFO_43_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1477/* 0x011d8 */ u64 kdfc_fifo_44_ctrl; 1478#define VXGE_HAL_KDFC_FIFO_44_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1479/* 0x011e0 */ u64 kdfc_fifo_45_ctrl; 1480#define VXGE_HAL_KDFC_FIFO_45_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1481/* 0x011e8 */ u64 kdfc_fifo_46_ctrl; 1482#define VXGE_HAL_KDFC_FIFO_46_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1483/* 0x011f0 */ u64 kdfc_fifo_47_ctrl; 1484#define VXGE_HAL_KDFC_FIFO_47_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1485/* 0x011f8 */ u64 kdfc_fifo_48_ctrl; 1486#define VXGE_HAL_KDFC_FIFO_48_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1487/* 0x01200 */ u64 kdfc_fifo_49_ctrl; 1488#define VXGE_HAL_KDFC_FIFO_49_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1489/* 0x01208 */ u64 kdfc_fifo_50_ctrl; 1490#define VXGE_HAL_KDFC_FIFO_50_CTRL_WRR_NUMBER(val) vBIT(val, 3, 5) 1491/* 0x01210 */ u64 kdfc_krnl_usr_ctrl; 1492#define VXGE_HAL_KDFC_KRNL_USR_CTRL_CODE(val) vBIT(val, 4, 4) 1493/* 0x01218 */ u64 kdfc_pda_monitor; 1494#define VXGE_HAL_KDFC_PDA_MONITOR_KDFC_ACCEPT mBIT(7) 1495#define VXGE_HAL_KDFC_PDA_MONITOR_FIFO_NO(val) vBIT(val, 10, 6) 1496#define VXGE_HAL_KDFC_PDA_MONITOR_FIFO_ADD(val) vBIT(val, 17, 15) 1497#define VXGE_HAL_KDFC_PDA_MONITOR_TYPE(val) vBIT(val, 32, 8) 1498#define VXGE_HAL_KDFC_PDA_MONITOR_VP(val) vBIT(val, 43, 5) 1499/* 0x01220 */ u64 kdfc_mp_monitor; 1500#define VXGE_HAL_KDFC_MP_MONITOR_KDFC_ACCEPT mBIT(7) 1501#define VXGE_HAL_KDFC_MP_MONITOR_FIFO_NO(val) vBIT(val, 10, 6) 1502#define VXGE_HAL_KDFC_MP_MONITOR_FIFO_ADD(val) vBIT(val, 17, 15) 1503#define VXGE_HAL_KDFC_MP_MONITOR_TYPE(val) vBIT(val, 32, 8) 1504#define VXGE_HAL_KDFC_MP_MONITOR_VP(val) vBIT(val, 43, 5) 1505/* 0x01228 */ u64 kdfc_pe_monitor; 1506#define VXGE_HAL_KDFC_PE_MONITOR_KDFC_CREDIT mBIT(7) 1507#define VXGE_HAL_KDFC_PE_MONITOR_FIFO_NO(val) vBIT(val, 10, 6) 1508#define VXGE_HAL_KDFC_PE_MONITOR_FIFO_ADD(val) vBIT(val, 17, 15) 1509#define VXGE_HAL_KDFC_PE_MONITOR_TYPE(val) vBIT(val, 32, 8) 1510#define VXGE_HAL_KDFC_PE_MONITOR_VP(val) vBIT(val, 43, 5) 1511#define VXGE_HAL_KDFC_PE_MONITOR_IMM_DATA_CNT(val) vBIT(val, 48, 8) 1512/* 0x01230 */ u64 kdfc_read_cntrl; 1513#define VXGE_HAL_KDFC_READ_CNTRL_KDFC_FREEZE mBIT(7) 1514#define VXGE_HAL_KDFC_READ_CNTRL_KDFC_RDCTRL(val) vBIT(val, 14, 2) 1515#define VXGE_HAL_KDFC_READ_CNTRL_KDFC_WORD_SEL mBIT(23) 1516#define VXGE_HAL_KDFC_READ_CNTRL_KDFC_ADDR(val) vBIT(val, 49, 15) 1517/* 0x01238 */ u64 kdfc_read_data; 1518#define VXGE_HAL_KDFC_READ_DATA_READ_DATA(val) vBIT(val, 0, 64) 1519/* 0x01240 */ u64 kdfc_force_valid_ctrl; 1520#define VXGE_HAL_KDFC_FORCE_VALID_CTRL_FORCE_VALID mBIT(7) 1521/* 0x01248 */ u64 kdfc_multi_cycle_ctrl; 1522#define VXGE_HAL_KDFC_MULTI_CYCLE_CTRL_MULTI_CYCLE_SEL(val) vBIT(val, 6, 2) 1523/* 0x01250 */ u64 kdfc_ecc_ctrl; 1524#define VXGE_HAL_KDFC_ECC_CTRL_ECC_DISABLE mBIT(7) 1525/* 0x01258 */ u64 kdfc_vpbp_ctrl; 1526#define VXGE_HAL_KDFC_VPBP_CTRL_RD_XON_DIS mBIT(7) 1527#define VXGE_HAL_KDFC_VPBP_CTRL_ROCRC_DIS mBIT(23) 1528#define VXGE_HAL_KDFC_VPBP_CTRL_H2L_DIS mBIT(31) 1529#define VXGE_HAL_KDFC_VPBP_CTRL_MSG_ONE_DIS mBIT(39) 1530#define VXGE_HAL_KDFC_VPBP_CTRL_MSG_DMQ_DIS mBIT(47) 1531#define VXGE_HAL_KDFC_VPBP_CTRL_PDA_DIS mBIT(55) 1532 u8 unused01600[0x01600 - 0x01260]; 1533 1534/* 0x01600 */ u64 rxmac_int_status; 1535#define VXGE_HAL_RXMAC_INT_STATUS_RXMAC_GEN_ERR_RXMAC_GEN_INT mBIT(3) 1536#define VXGE_HAL_RXMAC_INT_STATUS_RXMAC_ECC_ERR_RXMAC_ECC_INT mBIT(7) 1537#define VXGE_HAL_RXMAC_INT_STATUS_RXMAC_VARIOUS_ERR_RXMAC_VARIOUS_INT mBIT(11) 1538/* 0x01608 */ u64 rxmac_int_mask; 1539 u8 unused01618[0x01618 - 0x01610]; 1540 1541/* 0x01618 */ u64 rxmac_gen_err_reg; 1542/* 0x01620 */ u64 rxmac_gen_err_mask; 1543/* 0x01628 */ u64 rxmac_gen_err_alarm; 1544/* 0x01630 */ u64 rxmac_ecc_err_reg; 1545#define VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_SG_ERR(val)\ 1546 vBIT(val, 0, 4) 1547#define VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_DB_ERR(val)\ 1548 vBIT(val, 4, 4) 1549#define VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT1_RMAC_RTS_PART_SG_ERR(val)\ 1550 vBIT(val, 8, 4) 1551#define VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT1_RMAC_RTS_PART_DB_ERR(val)\ 1552 vBIT(val, 12, 4) 1553#define VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT2_RMAC_RTS_PART_SG_ERR(val)\ 1554 vBIT(val, 16, 4) 1555#define VXGE_HAL_RXMAC_ECC_ERR_REG_RMAC_PORT2_RMAC_RTS_PART_DB_ERR(val)\ 1556 vBIT(val, 20, 4) 1557#define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT0_SG_ERR(val)\ 1558 vBIT(val, 24, 2) 1559#define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT0_DB_ERR(val)\ 1560 vBIT(val, 26, 2) 1561#define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT1_SG_ERR(val)\ 1562 vBIT(val, 28, 2) 1563#define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT1_DB_ERR(val)\ 1564 vBIT(val, 30, 2) 1565#define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_VID_LKP_SG_ERR mBIT(32) 1566#define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_VID_LKP_DB_ERR mBIT(33) 1567#define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT0_SG_ERR mBIT(34) 1568#define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT0_DB_ERR mBIT(35) 1569#define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT1_SG_ERR mBIT(36) 1570#define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT1_DB_ERR mBIT(37) 1571#define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT2_SG_ERR mBIT(38) 1572#define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT2_DB_ERR mBIT(39) 1573#define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_SG_ERR(val)\ 1574 vBIT(val, 40, 7) 1575#define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_DB_ERR(val)\ 1576 vBIT(val, 47, 7) 1577#define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_SG_ERR(val)\ 1578 vBIT(val, 54, 3) 1579#define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_DB_ERR(val)\ 1580 vBIT(val, 57, 3) 1581#define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DS_LKP_SG_ERR mBIT(60) 1582#define VXGE_HAL_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DS_LKP_DB_ERR mBIT(61) 1583/* 0x01638 */ u64 rxmac_ecc_err_mask; 1584/* 0x01640 */ u64 rxmac_ecc_err_alarm; 1585/* 0x01648 */ u64 rxmac_various_err_reg; 1586#define VXGE_HAL_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT0_FSM_ERR mBIT(0) 1587#define VXGE_HAL_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT1_FSM_ERR mBIT(1) 1588#define VXGE_HAL_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT2_FSM_ERR mBIT(2) 1589#define VXGE_HAL_RXMAC_VARIOUS_ERR_REG_RMACJ_RMACJ_FSM_ERR mBIT(3) 1590/* 0x01650 */ u64 rxmac_various_err_mask; 1591/* 0x01658 */ u64 rxmac_various_err_alarm; 1592/* 0x01660 */ u64 rxmac_gen_cfg; 1593#define VXGE_HAL_RXMAC_GEN_CFG_SCALE_RMAC_UTIL mBIT(11) 1594/* 0x01668 */ u64 rxmac_authorize_all_addr; 1595#define VXGE_HAL_RXMAC_AUTHORIZE_ALL_ADDR_VP(n) mBIT(n) 1596/* 0x01670 */ u64 rxmac_authorize_all_vid; 1597#define VXGE_HAL_RXMAC_AUTHORIZE_ALL_VID_VP(n) mBIT(n) 1598 u8 unused016b8[0x016b8 - 0x01678]; 1599 1600/* 0x016b8 */ u64 rxmac_thresh_cross_repl; 1601#define VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_PAUSE_LOW_UP_CROSSED mBIT(3) 1602#define VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_PAUSE_LOW_DOWN_CROSSED mBIT(7) 1603#define VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_PAUSE_HIGH_UP_CROSSED mBIT(11) 1604#define VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_PAUSE_HIGH_DOWN_CROSSED mBIT(15) 1605#define VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_RED0_UP_CROSSED mBIT(35) 1606#define VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_RED0_DOWN_CROSSED mBIT(39) 1607#define VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_RED1_UP_CROSSED mBIT(43) 1608#define VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_RED1_DOWN_CROSSED mBIT(47) 1609#define VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_RED2_UP_CROSSED mBIT(51) 1610#define VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_RED2_DOWN_CROSSED mBIT(55) 1611#define VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_RED3_UP_CROSSED mBIT(59) 1612#define VXGE_HAL_RXMAC_THRESH_CROSS_REPL_RMACJ_RED3_DOWN_CROSSED mBIT(63) 1613/* 0x016c0 */ u64 rxmac_red_rate_repl_queue; 1614#define VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR0(val) vBIT(val, 0, 4) 1615#define VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR1(val) vBIT(val, 4, 4) 1616#define VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR2(val) vBIT(val, 8, 4) 1617#define VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR3(val) vBIT(val, 12, 4) 1618#define VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR0(val) vBIT(val, 16, 4) 1619#define VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR1(val) vBIT(val, 20, 4) 1620#define VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR2(val) vBIT(val, 24, 4) 1621#define VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR3(val) vBIT(val, 28, 4) 1622#define VXGE_HAL_RXMAC_RED_RATE_REPL_QUEUE_TRICKLE_EN mBIT(35) 1623 u8 unused016e0[0x016e0 - 0x016c8]; 1624 1625/* 0x016e0 */ u64 rxmac_cfg0_port[3]; 1626#define VXGE_HAL_RXMAC_CFG0_PORT_RMAC_EN mBIT(3) 1627#define VXGE_HAL_RXMAC_CFG0_PORT_STRIP_FCS mBIT(7) 1628#define VXGE_HAL_RXMAC_CFG0_PORT_DISCARD_PFRM mBIT(11) 1629#define VXGE_HAL_RXMAC_CFG0_PORT_IGNORE_FCS_ERR mBIT(15) 1630#define VXGE_HAL_RXMAC_CFG0_PORT_IGNORE_LONG_ERR mBIT(19) 1631#define VXGE_HAL_RXMAC_CFG0_PORT_IGNORE_USIZED_ERR mBIT(23) 1632#define VXGE_HAL_RXMAC_CFG0_PORT_IGNORE_LEN_MISMATCH mBIT(27) 1633#define VXGE_HAL_RXMAC_CFG0_PORT_MAX_PYLD_LEN(val) vBIT(val, 50, 14) 1634 u8 unused01710[0x01710 - 0x016f8]; 1635 1636/* 0x01710 */ u64 rxmac_cfg2_port[3]; 1637#define VXGE_HAL_RXMAC_CFG2_PORT_PROM_EN mBIT(3) 1638/* 0x01728 */ u64 rxmac_pause_cfg_port[3]; 1639#define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_GEN_EN mBIT(3) 1640#define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_RCV_EN mBIT(7) 1641#define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_ACCEL_SEND(val) vBIT(val, 9, 3) 1642#define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_DUAL_THR mBIT(15) 1643#define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_HIGH_PTIME(val) vBIT(val, 20, 16) 1644#define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_IGNORE_PF_FCS_ERR mBIT(39) 1645#define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_IGNORE_PF_LEN_ERR mBIT(43) 1646#define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_LIMITER_EN mBIT(47) 1647#define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT(val) vBIT(val, 48, 8) 1648#define VXGE_HAL_RXMAC_PAUSE_CFG_PORT_PERMIT_RATEMGMT_CTRL mBIT(59) 1649 u8 unused01758[0x01758 - 0x01740]; 1650 1651/* 0x01758 */ u64 rxmac_red_cfg0_port[3]; 1652#define VXGE_HAL_RXMAC_RED_CFG0_PORT_RED_EN_VP(n) mBIT(n) 1653/* 0x01770 */ u64 rxmac_red_cfg1_port[3]; 1654#define VXGE_HAL_RXMAC_RED_CFG1_PORT_FINE_EN mBIT(3) 1655#define VXGE_HAL_RXMAC_RED_CFG1_PORT_RED_EN_REPL_QUEUE mBIT(11) 1656/* 0x01788 */ u64 rxmac_red_cfg2_port[3]; 1657#define VXGE_HAL_RXMAC_RED_CFG2_PORT_TRICKLE_EN_VP(n) mBIT(n) 1658/* 0x017a0 */ u64 rxmac_link_util_port[3]; 1659#define VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_UTILIZATION(val) vBIT(val, 1, 7) 1660#define VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_UTIL_CFG(val) vBIT(val, 8, 4) 1661#define VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_FRAC_UTIL(val) vBIT(val, 12, 4) 1662#define VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_PKT_WEIGHT(val) vBIT(val, 16, 4) 1663#define VXGE_HAL_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_SCALE_FACTOR mBIT(23) 1664 u8 unused017d0[0x017d0 - 0x017b8]; 1665 1666/* 0x017d0 */ u64 rxmac_status_port[3]; 1667#define VXGE_HAL_RXMAC_STATUS_PORT_RMAC_RX_FRM_RCVD mBIT(3) 1668 u8 unused01800[0x01800 - 0x017e8]; 1669 1670/* 0x01800 */ u64 rxmac_rx_pa_cfg0; 1671#define VXGE_HAL_RXMAC_RX_PA_CFG0_IGNORE_FRAME_ERR mBIT(3) 1672#define VXGE_HAL_RXMAC_RX_PA_CFG0_SUPPORT_SNAP_AB_N mBIT(7) 1673#define VXGE_HAL_RXMAC_RX_PA_CFG0_SEARCH_FOR_HAO mBIT(18) 1674#define VXGE_HAL_RXMAC_RX_PA_CFG0_SUPPORT_MOBILE_IPV6_HDRS mBIT(19) 1675#define VXGE_HAL_RXMAC_RX_PA_CFG0_IPV6_STOP_SEARCHING mBIT(23) 1676#define VXGE_HAL_RXMAC_RX_PA_CFG0_NO_PS_IF_UNKNOWN mBIT(27) 1677#define VXGE_HAL_RXMAC_RX_PA_CFG0_SEARCH_FOR_ETYPE mBIT(35) 1678#define VXGE_HAL_RXMAC_RX_PA_CFG0_TOSS_ANY_FRM_IF_L3_CSUM_ERR mBIT(39) 1679#define VXGE_HAL_RXMAC_RX_PA_CFG0_TOSS_OFFLD_FRM_IF_L3_CSUM_ERR mBIT(43) 1680#define VXGE_HAL_RXMAC_RX_PA_CFG0_TOSS_ANY_FRM_IF_L4_CSUM_ERR mBIT(47) 1681#define VXGE_HAL_RXMAC_RX_PA_CFG0_TOSS_OFFLD_FRM_IF_L4_CSUM_ERR mBIT(51) 1682#define VXGE_HAL_RXMAC_RX_PA_CFG0_TOSS_ANY_FRM_IF_RPA_ERR mBIT(55) 1683#define VXGE_HAL_RXMAC_RX_PA_CFG0_TOSS_OFFLD_FRM_IF_RPA_ERR mBIT(59) 1684#define VXGE_HAL_RXMAC_RX_PA_CFG0_JUMBO_SNAP_EN mBIT(63) 1685/* 0x01808 */ u64 rxmac_rx_pa_cfg1; 1686#define VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV4_TCP_INCL_PH mBIT(3) 1687#define VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV6_TCP_INCL_PH mBIT(7) 1688#define VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV4_UDP_INCL_PH mBIT(11) 1689#define VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_IPV6_UDP_INCL_PH mBIT(15) 1690#define VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_L4_INCL_CF mBIT(19) 1691#define VXGE_HAL_RXMAC_RX_PA_CFG1_REPL_STRIP_VLAN_TAG mBIT(23) 1692 u8 unused01828[0x01828 - 0x01810]; 1693 1694/* 0x01828 */ u64 rts_mgr_cfg0; 1695#define VXGE_HAL_RTS_MGR_CFG0_RTS_DP_SP_PRIORITY mBIT(3) 1696#define VXGE_HAL_RTS_MGR_CFG0_FLEX_L4PRTCL_VALUE(val) vBIT(val, 24, 8) 1697#define VXGE_HAL_RTS_MGR_CFG0_ICMP_TRASH mBIT(35) 1698#define VXGE_HAL_RTS_MGR_CFG0_TCPSYN_TRASH mBIT(39) 1699#define VXGE_HAL_RTS_MGR_CFG0_ZL4PYLD_TRASH mBIT(43) 1700#define VXGE_HAL_RTS_MGR_CFG0_L4PRTCL_TCP_TRASH mBIT(47) 1701#define VXGE_HAL_RTS_MGR_CFG0_L4PRTCL_UDP_TRASH mBIT(51) 1702#define VXGE_HAL_RTS_MGR_CFG0_L4PRTCL_FLEX_TRASH mBIT(55) 1703#define VXGE_HAL_RTS_MGR_CFG0_IPFRAG_TRASH mBIT(59) 1704/* 0x01830 */ u64 rts_mgr_cfg1; 1705#define VXGE_HAL_RTS_MGR_CFG1_DA_ACTIVE_TABLE mBIT(3) 1706#define VXGE_HAL_RTS_MGR_CFG1_PN_ACTIVE_TABLE mBIT(7) 1707/* 0x01838 */ u64 rts_mgr_criteria_priority; 1708#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_ETYPE(val) vBIT(val, 5, 3) 1709#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_ICMP_TCPSYN(val) vBIT(val, 9, 3) 1710#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_L4PN(val) vBIT(val, 13, 3) 1711#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_RANGE_L4PN(val) vBIT(val, 17, 3) 1712#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_RTH_IT(val) vBIT(val, 21, 3) 1713#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_DS(val) vBIT(val, 25, 3) 1714#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_QOS(val) vBIT(val, 29, 3) 1715#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_ZL4PYLD(val) vBIT(val, 33, 3) 1716#define VXGE_HAL_RTS_MGR_CRITERIA_PRIORITY_L4PRTCL(val) vBIT(val, 37, 3) 1717/* 0x01840 */ u64 rts_mgr_da_pause_cfg; 1718#define VXGE_HAL_RTS_MGR_DA_PAUSE_CFG_VPATH_VECTOR(val) vBIT(val, 0, 17) 1719/* 0x01848 */ u64 rts_mgr_da_slow_proto_cfg; 1720#define VXGE_HAL_RTS_MGR_DA_SLOW_PROTO_CFG_VPATH_VECTOR(val) vBIT(val, 0, 17) 1721 u8 unused018a8[0x018a8 - 0x01850]; 1722 1723/* 0x018a8 */ u64 rts_mgr_steer_ctrl; 1724#define VXGE_HAL_RTS_MGR_STEER_CTRL_WE mBIT(7) 1725#define VXGE_HAL_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL(val) vBIT(val, 8, 4) 1726#define VXGE_HAL_RTS_MGR_STEER_CTRL_STROBE mBIT(15) 1727#define VXGE_HAL_RTS_MGR_STEER_CTRL_BEHAV_TBL_SEL mBIT(23) 1728#define VXGE_HAL_RTS_MGR_STEER_CTRL_TABLE_SEL mBIT(27) 1729#define VXGE_HAL_RTS_MGR_STEER_CTRL_OFFSET(val) vBIT(val, 35, 13) 1730#define VXGE_HAL_RTS_MGR_STEER_CTRL_RMACJ_STATUS mBIT(0) 1731/* 0x018b0 */ u64 rts_mgr_steer_data0; 1732#define VXGE_HAL_RTS_MGR_STEER_DATA0_DATA(val) vBIT(val, 0, 64) 1733/* 0x018b8 */ u64 rts_mgr_steer_data1; 1734#define VXGE_HAL_RTS_MGR_STEER_DATA1_DATA(val) vBIT(val, 0, 64) 1735/* 0x018c0 */ u64 rts_mgr_steer_vpath_vector; 1736#define VXGE_HAL_RTS_MGR_STEER_VPATH_VECTOR_VPATH_VECTOR(val) vBIT(val, 0, 17) 1737 u8 unused01930[0x01930 - 0x018c8]; 1738 1739/* 0x01930 */ u64 xmac_stats_rx_xgmii_char; 1740#define VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_LANE_CHAR1(val) vBIT(val, 1, 3) 1741#define VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_RXC_CHAR1 mBIT(7) 1742#define VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_RXD_CHAR1(val) vBIT(val, 8, 8) 1743#define VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_LANE_CHAR2(val) vBIT(val, 17, 3) 1744#define VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_RXC_CHAR2 mBIT(23) 1745#define VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_RXD_CHAR2(val) vBIT(val, 24, 8) 1746#define VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_BEHAV_CHAR2_NEAR_CHAR1 mBIT(39) 1747#define VXGE_HAL_XMAC_STATS_RX_XGMII_CHAR_BEHAV_CHAR2_NUM_CHAR(val)\ 1748 vBIT(val, 40, 16) 1749/* 0x01938 */ u64 xmac_stats_rx_xgmii_column1; 1750#define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXC_LANE0 mBIT(7) 1751#define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXD_LANE0(val) vBIT(val, 8, 8) 1752#define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXC_LANE1 mBIT(23) 1753#define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXD_LANE1(val) vBIT(val, 24, 8) 1754#define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXC_LANE2 mBIT(39) 1755#define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXD_LANE2(val) vBIT(val, 40, 8) 1756#define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXC_LANE3 mBIT(55) 1757#define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN1_RXD_LANE3(val) vBIT(val, 56, 8) 1758/* 0x01940 */ u64 xmac_stats_rx_xgmii_column2; 1759#define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXC_LANE0 mBIT(7) 1760#define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXD_LANE0(val) vBIT(val, 8, 8) 1761#define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXC_LANE1 mBIT(23) 1762#define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXD_LANE1(val) vBIT(val, 24, 8) 1763#define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXC_LANE2 mBIT(39) 1764#define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXD_LANE2(val) vBIT(val, 40, 8) 1765#define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXC_LANE3 mBIT(55) 1766#define VXGE_HAL_XMAC_STATS_RX_XGMII_COLUMN2_RXD_LANE3(val) vBIT(val, 56, 8) 1767/* 0x01948 */ u64 xmac_stats_rx_xgmii_behav_column2; 1768#define VXGE_HAL_XMAC_STATS_RX_XGMII_BEHAV_COLUMN2_NEAR_COL1 mBIT(7) 1769#define VXGE_HAL_XMAC_STATS_RX_XGMII_BEHAV_COLUMN2_NUM_COL(val) vBIT(val, 8, 16) 1770/* 0x01950 */ u64 xmac_rx_xgmii_capture_ctrl_port[3]; 1771#define VXGE_HAL_XMAC_RX_XGMII_CAPTURE_CTRL_PORT_EN mBIT(3) 1772#define VXGE_HAL_XMAC_RX_XGMII_CAPTURE_CTRL_PORT_READBACK mBIT(7) 1773/* 0x01968 */ u64 dbg_stat_rx_any_frms; 1774#define VXGE_HAL_DBG_STAT_RX_ANY_FRMS_PORT0_RX_ANY_FRMS(val) vBIT(val, 0, 8) 1775#define VXGE_HAL_DBG_STAT_RX_ANY_FRMS_PORT1_RX_ANY_FRMS(val) vBIT(val, 8, 8) 1776#define VXGE_HAL_DBG_STAT_RX_ANY_FRMS_PORT2_RX_ANY_FRMS(val) vBIT(val, 16, 8) 1777 u8 unused01a00[0x01a00 - 0x01970]; 1778 1779/* 0x01a00 */ u64 rxmac_red_rate_vp[17]; 1780#define VXGE_HAL_RXMAC_RED_RATE_VP_CRATE_THR0(val) vBIT(val, 0, 4) 1781#define VXGE_HAL_RXMAC_RED_RATE_VP_CRATE_THR1(val) vBIT(val, 4, 4) 1782#define VXGE_HAL_RXMAC_RED_RATE_VP_CRATE_THR2(val) vBIT(val, 8, 4) 1783#define VXGE_HAL_RXMAC_RED_RATE_VP_CRATE_THR3(val) vBIT(val, 12, 4) 1784#define VXGE_HAL_RXMAC_RED_RATE_VP_FRATE_THR0(val) vBIT(val, 16, 4) 1785#define VXGE_HAL_RXMAC_RED_RATE_VP_FRATE_THR1(val) vBIT(val, 20, 4) 1786#define VXGE_HAL_RXMAC_RED_RATE_VP_FRATE_THR2(val) vBIT(val, 24, 4) 1787#define VXGE_HAL_RXMAC_RED_RATE_VP_FRATE_THR3(val) vBIT(val, 28, 4) 1788 u8 unused01c00[0x01c00 - 0x01a88]; 1789 1790/* 0x01c00 */ u64 rxmac_thresh_cross_vp[17]; 1791#define VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_PAUSE_LOW_UP_CROSSED mBIT(3) 1792#define VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_PAUSE_LOW_DOWN_CROSSED mBIT(7) 1793#define VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_PAUSE_HIGH_UP_CROSSED mBIT(11) 1794#define VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_PAUSE_HIGH_DOWN_CROSSED mBIT(15) 1795#define VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_RED_THR0_UP_CROSSED mBIT(35) 1796#define VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_RED_THR0_DOWN_CROSSED mBIT(39) 1797#define VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_RED_THR1_UP_CROSSED mBIT(43) 1798#define VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_RED_THR1_DOWN_CROSSED mBIT(47) 1799#define VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_RED_THR2_UP_CROSSED mBIT(51) 1800#define VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_RED_THR2_DOWN_CROSSED mBIT(55) 1801#define VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_RED_THR3_UP_CROSSED mBIT(59) 1802#define VXGE_HAL_RXMAC_THRESH_CROSS_VP_RMACJ_RED_THR3_DOWN_CROSSED mBIT(63) 1803 u8 unused01e00[0x01e00 - 0x01c88]; 1804 1805/* 0x01e00 */ u64 xgmac_int_status; 1806#define VXGE_HAL_XGMAC_INT_STATUS_XMAC_GEN_ERR_XMAC_GEN_INT mBIT(3) 1807#define VXGE_HAL_XGMAC_INT_STATUS_XMAC_LINK_ERR_PORT0_XMAC_LINK_INT_PORT0\ 1808 mBIT(7) 1809#define VXGE_HAL_XGMAC_INT_STATUS_XMAC_LINK_ERR_PORT1_XMAC_LINK_INT_PORT1\ 1810 mBIT(11) 1811#define VXGE_HAL_XGMAC_INT_STATUS_XGXS_GEN_ERR_XGXS_GEN_INT mBIT(15) 1812#define VXGE_HAL_XGMAC_INT_STATUS_ASIC_NTWK_ERR_ASIC_NTWK_INT mBIT(19) 1813#define VXGE_HAL_XGMAC_INT_STATUS_ASIC_GPIO_ERR_ASIC_GPIO_INT mBIT(23) 1814/* 0x01e08 */ u64 xgmac_int_mask; 1815/* 0x01e10 */ u64 xmac_gen_err_reg; 1816#define VXGE_HAL_XMAC_GEN_ERR_REG_LAGC_LAG_PORT0_ACTOR_CHURN_DETECTED mBIT(7) 1817#define VXGE_HAL_XMAC_GEN_ERR_REG_LAGC_LAG_PORT0_PARTNER_CHURN_DETECTED mBIT(11) 1818#define VXGE_HAL_XMAC_GEN_ERR_REG_LAGC_LAG_PORT0_RECEIVED_LACPDU mBIT(15) 1819#define VXGE_HAL_XMAC_GEN_ERR_REG_LAGC_LAG_PORT1_ACTOR_CHURN_DETECTED mBIT(19) 1820#define VXGE_HAL_XMAC_GEN_ERR_REG_LAGC_LAG_PORT1_PARTNER_CHURN_DETECTED mBIT(23) 1821#define VXGE_HAL_XMAC_GEN_ERR_REG_LAGC_LAG_PORT1_RECEIVED_LACPDU mBIT(27) 1822#define VXGE_HAL_XMAC_GEN_ERR_REG_XLCM_LAG_FAILOVER_DETECTED mBIT(31) 1823#define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_SG_ERR(val)\ 1824 vBIT(val, 40, 2) 1825#define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_DB_ERR(val)\ 1826 vBIT(val, 42, 2) 1827#define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE1_SG_ERR(val)\ 1828 vBIT(val, 44, 2) 1829#define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE1_DB_ERR(val)\ 1830 vBIT(val, 46, 2) 1831#define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE2_SG_ERR(val)\ 1832 vBIT(val, 48, 2) 1833#define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE2_DB_ERR(val)\ 1834 vBIT(val, 50, 2) 1835#define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE3_SG_ERR(val)\ 1836 vBIT(val, 52, 2) 1837#define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE3_DB_ERR(val)\ 1838 vBIT(val, 54, 2) 1839#define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE4_SG_ERR(val)\ 1840 vBIT(val, 56, 2) 1841#define VXGE_HAL_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE4_DB_ERR(val)\ 1842 vBIT(val, 58, 2) 1843#define VXGE_HAL_XMAC_GEN_ERR_REG_XMACJ_XMAC_FSM_ERR mBIT(63) 1844/* 0x01e18 */ u64 xmac_gen_err_mask; 1845/* 0x01e20 */ u64 xmac_gen_err_alarm; 1846/* 0x01e28 */ u64 xmac_link_err_port0_reg; 1847#define VXGE_HAL_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_DOWN mBIT(3) 1848#define VXGE_HAL_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_UP mBIT(7) 1849#define VXGE_HAL_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_WENT_DOWN mBIT(11) 1850#define VXGE_HAL_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_WENT_UP mBIT(15) 1851#define VXGE_HAL_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_REAFFIRMED_FAULT mBIT(19) 1852#define VXGE_HAL_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_REAFFIRMED_OK mBIT(23) 1853#define VXGE_HAL_XMAC_LINK_ERR_PORT_REG_XMACJ_LINK_DOWN mBIT(27) 1854#define VXGE_HAL_XMAC_LINK_ERR_PORT_REG_XMACJ_LINK_UP mBIT(31) 1855#define VXGE_HAL_XMAC_LINK_ERR_PORT_REG_RATEMGMT_RATE_CHANGE mBIT(35) 1856#define VXGE_HAL_XMAC_LINK_ERR_PORT_REG_RATEMGMT_LASI_INV mBIT(39) 1857#define VXGE_HAL_XMAC_LINK_ERR_PORT_REG_XMDIO_MDIO_MGR_ACCESS_COMPLETE mBIT(47) 1858/* 0x01e30 */ u64 xmac_link_err_port0_mask; 1859/* 0x01e38 */ u64 xmac_link_err_port0_alarm; 1860/* 0x01e40 */ u64 xmac_link_err_port1_reg; 1861/* 0x01e48 */ u64 xmac_link_err_port1_mask; 1862/* 0x01e50 */ u64 xmac_link_err_port1_alarm; 1863/* 0x01e58 */ u64 xgxs_gen_err_reg; 1864#define VXGE_HAL_XGXS_GEN_ERR_REG_XGXS_XGXS_FSM_ERR mBIT(63) 1865/* 0x01e60 */ u64 xgxs_gen_err_mask; 1866/* 0x01e68 */ u64 xgxs_gen_err_alarm; 1867/* 0x01e70 */ u64 asic_ntwk_err_reg; 1868#define VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_DOWN mBIT(3) 1869#define VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_UP mBIT(7) 1870#define VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_WENT_DOWN mBIT(11) 1871#define VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_WENT_UP mBIT(15) 1872#define VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT mBIT(19) 1873#define VXGE_HAL_ASIC_NTWK_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK mBIT(23) 1874/* 0x01e78 */ u64 asic_ntwk_err_mask; 1875/* 0x01e80 */ u64 asic_ntwk_err_alarm; 1876/* 0x01e88 */ u64 asic_gpio_err_reg; 1877#define VXGE_HAL_ASIC_GPIO_ERR_REG_XMACJ_GPIO_INT(n) mBIT(n) 1878/* 0x01e90 */ u64 asic_gpio_err_mask; 1879/* 0x01e98 */ u64 asic_gpio_err_alarm; 1880/* 0x01ea0 */ u64 xgmac_gen_status; 1881#define VXGE_HAL_XGMAC_GEN_STATUS_XMACJ_NTWK_OK mBIT(3) 1882#define VXGE_HAL_XGMAC_GEN_STATUS_XMACJ_NTWK_DATA_RATE mBIT(11) 1883/* 0x01ea8 */ u64 xgmac_gen_fw_memo_status; 1884#define VXGE_HAL_XGMAC_GEN_FW_MEMO_STATUS_XMACJ_EVENTS_PENDING(val)\ 1885 vBIT(val, 0, 17) 1886/* 0x01eb0 */ u64 xgmac_gen_fw_memo_mask; 1887#define VXGE_HAL_XGMAC_GEN_FW_MEMO_MASK_MASK(val) vBIT(val, 0, 64) 1888/* 0x01eb8 */ u64 xgmac_gen_fw_vpath_to_vsport_status; 1889#define VXGE_HAL_XGMAC_GEN_FW_VPATH_TO_VSPORT_STATUS_XMACJ_EVENTS_PENDING(val)\ 1890 vBIT(val, 0, 17) 1891/* 0x01ec0 */ u64 xgmac_main_cfg_port[2]; 1892#define VXGE_HAL_XGMAC_MAIN_CFG_PORT_PORT_EN mBIT(3) 1893/* 0x01ed0 */ u64 xgmac_debounce_port[2]; 1894#define VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_LINK_UP(val) vBIT(val, 0, 4) 1895#define VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_LINK_DOWN(val) vBIT(val, 4, 4) 1896#define VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_PORT_UP(val) vBIT(val, 8, 4) 1897#define VXGE_HAL_XGMAC_DEBOUNCE_PORT_PERIOD_PORT_DOWN(val) vBIT(val, 12, 4) 1898/* 0x01ee0 */ u64 xgmac_status_port[2]; 1899#define VXGE_HAL_XGMAC_STATUS_PORT_RMAC_REMOTE_FAULT mBIT(3) 1900#define VXGE_HAL_XGMAC_STATUS_PORT_RMAC_LOCAL_FAULT mBIT(7) 1901#define VXGE_HAL_XGMAC_STATUS_PORT_XMACJ_MAC_PHY_LAYER_AVAIL mBIT(11) 1902#define VXGE_HAL_XGMAC_STATUS_PORT_XMACJ_PORT_OK mBIT(15) 1903 u8 unused01f40[0x01f40 - 0x01ef0]; 1904 1905/* 0x01f40 */ u64 xmac_gen_cfg; 1906#define VXGE_HAL_XMAC_GEN_CFG_RATEMGMT_MAC_RATE_SEL(val) vBIT(val, 2, 2) 1907#define VXGE_HAL_XMAC_GEN_CFG_TX_HEAD_DROP_WHEN_FAULT mBIT(7) 1908#define VXGE_HAL_XMAC_GEN_CFG_FAULT_BEHAVIOUR mBIT(27) 1909#define VXGE_HAL_XMAC_GEN_CFG_PERIOD_NTWK_UP(val) vBIT(val, 28, 4) 1910#define VXGE_HAL_XMAC_GEN_CFG_PERIOD_NTWK_DOWN(val) vBIT(val, 32, 4) 1911/* 0x01f48 */ u64 xmac_timestamp; 1912#define VXGE_HAL_XMAC_TIMESTAMP_EN mBIT(3) 1913#define VXGE_HAL_XMAC_TIMESTAMP_USE_LINK_ID(val) vBIT(val, 6, 2) 1914#define VXGE_HAL_XMAC_TIMESTAMP_INTERVAL(val) vBIT(val, 12, 4) 1915#define VXGE_HAL_XMAC_TIMESTAMP_TIMER_RESTART mBIT(19) 1916#define VXGE_HAL_XMAC_TIMESTAMP_XMACJ_ROLLOVER_CNT(val) vBIT(val, 32, 16) 1917/* 0x01f50 */ u64 xmac_stats_gen_cfg; 1918#define VXGE_HAL_XMAC_STATS_GEN_CFG_PRTAGGR_CUM_TIMER(val) vBIT(val, 4, 4) 1919#define VXGE_HAL_XMAC_STATS_GEN_CFG_VPATH_CUM_TIMER(val) vBIT(val, 8, 4) 1920#define VXGE_HAL_XMAC_STATS_GEN_CFG_VLAN_HANDLING mBIT(15) 1921/* 0x01f58 */ u64 xmac_stats_sys_cmd; 1922#define VXGE_HAL_XMAC_STATS_SYS_CMD_OP(val) vBIT(val, 5, 3) 1923#define VXGE_HAL_XMAC_STATS_SYS_CMD_STROBE mBIT(15) 1924#define VXGE_HAL_XMAC_STATS_SYS_CMD_LOC_SEL(val) vBIT(val, 27, 5) 1925#define VXGE_HAL_XMAC_STATS_SYS_CMD_OFFSET_SEL(val) vBIT(val, 32, 8) 1926/* 0x01f60 */ u64 xmac_stats_sys_data; 1927#define VXGE_HAL_XMAC_STATS_SYS_DATA_XSMGR_DATA(val) vBIT(val, 0, 64) 1928 u8 unused01f80[0x01f80 - 0x01f68]; 1929 1930/* 0x01f80 */ u64 asic_ntwk_ctrl; 1931#define VXGE_HAL_ASIC_NTWK_CTRL_REQ_TEST_NTWK mBIT(3) 1932#define VXGE_HAL_ASIC_NTWK_CTRL_PORT0_REQ_TEST_PORT mBIT(11) 1933#define VXGE_HAL_ASIC_NTWK_CTRL_PORT1_REQ_TEST_PORT mBIT(15) 1934/* 0x01f88 */ u64 asic_ntwk_cfg_show_port_info; 1935#define VXGE_HAL_ASIC_NTWK_CFG_SHOW_PORT_INFO_VP(n) mBIT(n) 1936/* 0x01f90 */ u64 asic_ntwk_cfg_port_num; 1937#define VXGE_HAL_ASIC_NTWK_CFG_PORT_NUM_VP(n) mBIT(n) 1938/* 0x01f98 */ u64 xmac_cfg_port[3]; 1939#define VXGE_HAL_XMAC_CFG_PORT_XGMII_LOOPBACK mBIT(3) 1940#define VXGE_HAL_XMAC_CFG_PORT_XGMII_REVERSE_LOOPBACK mBIT(7) 1941#define VXGE_HAL_XMAC_CFG_PORT_XGMII_TX_BEHAV mBIT(11) 1942#define VXGE_HAL_XMAC_CFG_PORT_XGMII_RX_BEHAV mBIT(15) 1943/* 0x01fb0 */ u64 xmac_station_addr_port[2]; 1944#define VXGE_HAL_XMAC_STATION_ADDR_PORT_MAC_ADDR(val) vBIT(val, 0, 48) 1945/* 0x01fc0 */ u64 asic_led_activity_ctrl_port[3]; 1946#define VXGE_HAL_ASIC_LED_ACTIVITY_CTRL_PORT_TX_ACT_PULSE_EXTEND mBIT(11) 1947#define VXGE_HAL_ASIC_LED_ACTIVITY_CTRL_PORT_RX_ACT_PULSE_EXTEND mBIT(15) 1948#define VXGE_HAL_ASIC_LED_ACTIVITY_CTRL_PORT_COMBINE_TXRX mBIT(35) 1949 u8 unused02020[0x02020 - 0x01fd8]; 1950 1951/* 0x02020 */ u64 lag_cfg; 1952#define VXGE_HAL_LAG_CFG_EN mBIT(3) 1953#define VXGE_HAL_LAG_CFG_MODE(val) vBIT(val, 6, 2) 1954#define VXGE_HAL_LAG_CFG_TX_DISCARD_BEHAV mBIT(11) 1955#define VXGE_HAL_LAG_CFG_RX_DISCARD_BEHAV mBIT(15) 1956#define VXGE_HAL_LAG_CFG_PREF_INDIV_PORT_NUM mBIT(19) 1957/* 0x02028 */ u64 lag_status; 1958#define VXGE_HAL_LAG_STATUS_XLCM_WAITING_TO_FAILBACK mBIT(3) 1959#define VXGE_HAL_LAG_STATUS_XLCM_TIMER_VAL_COLD_FAILOVER(val) vBIT(val, 8, 8) 1960/* 0x02030 */ u64 lag_active_passive_cfg; 1961#define VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_HOT_STANDBY mBIT(3) 1962#define VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_LACP_DECIDES mBIT(7) 1963#define VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_PREF_ACTIVE_PORT_NUM mBIT(11) 1964#define VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_AUTO_FAILBACK mBIT(15) 1965#define VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_FAILBACK_EN mBIT(19) 1966#define VXGE_HAL_LAG_ACTIVE_PASSIVE_CFG_COLD_FAILOVER_TIMEOUT(val)\ 1967 vBIT(val, 32, 16) 1968 u8 unused02040[0x02040 - 0x02038]; 1969 1970/* 0x02040 */ u64 lag_lacp_cfg; 1971#define VXGE_HAL_LAG_LACP_CFG_EN mBIT(3) 1972#define VXGE_HAL_LAG_LACP_CFG_LACP_BEGIN mBIT(7) 1973#define VXGE_HAL_LAG_LACP_CFG_DISCARD_LACP mBIT(11) 1974#define VXGE_HAL_LAG_LACP_CFG_LIBERAL_LEN_CHK mBIT(15) 1975/* 0x02048 */ u64 lag_timer_cfg_1; 1976#define VXGE_HAL_LAG_TIMER_CFG_1_FAST_PER(val) vBIT(val, 0, 16) 1977#define VXGE_HAL_LAG_TIMER_CFG_1_SLOW_PER(val) vBIT(val, 16, 16) 1978#define VXGE_HAL_LAG_TIMER_CFG_1_SHORT_TIMEOUT(val) vBIT(val, 32, 16) 1979#define VXGE_HAL_LAG_TIMER_CFG_1_LONG_TIMEOUT(val) vBIT(val, 48, 16) 1980/* 0x02050 */ u64 lag_timer_cfg_2; 1981#define VXGE_HAL_LAG_TIMER_CFG_2_CHURN_DET(val) vBIT(val, 0, 16) 1982#define VXGE_HAL_LAG_TIMER_CFG_2_AGGR_WAIT(val) vBIT(val, 16, 16) 1983#define VXGE_HAL_LAG_TIMER_CFG_2_SHORT_TIMER_SCALE(val) vBIT(val, 32, 16) 1984#define VXGE_HAL_LAG_TIMER_CFG_2_LONG_TIMER_SCALE(val) vBIT(val, 48, 16) 1985/* 0x02058 */ u64 lag_sys_id; 1986#define VXGE_HAL_LAG_SYS_ID_ADDR(val) vBIT(val, 0, 48) 1987#define VXGE_HAL_LAG_SYS_ID_USE_PORT_ADDR mBIT(51) 1988#define VXGE_HAL_LAG_SYS_ID_ADDR_SEL mBIT(55) 1989/* 0x02060 */ u64 lag_sys_cfg; 1990#define VXGE_HAL_LAG_SYS_CFG_SYS_PRI(val) vBIT(val, 0, 16) 1991 u8 unused02070[0x02070 - 0x02068]; 1992 1993/* 0x02070 */ u64 lag_aggr_addr_cfg[2]; 1994#define VXGE_HAL_LAG_AGGR_ADDR_CFG_ADDR(val) vBIT(val, 0, 48) 1995#define VXGE_HAL_LAG_AGGR_ADDR_CFG_USE_PORT_ADDR mBIT(51) 1996#define VXGE_HAL_LAG_AGGR_ADDR_CFG_ADDR_SEL mBIT(55) 1997/* 0x02080 */ u64 lag_aggr_id_cfg[2]; 1998#define VXGE_HAL_LAG_AGGR_ID_CFG_ID(val) vBIT(val, 0, 16) 1999/* 0x02090 */ u64 lag_aggr_admin_key[2]; 2000#define VXGE_HAL_LAG_AGGR_ADMIN_KEY_KEY(val) vBIT(val, 0, 16) 2001/* 0x020a0 */ u64 lag_aggr_alt_admin_key; 2002#define VXGE_HAL_LAG_AGGR_ALT_ADMIN_KEY_KEY(val) vBIT(val, 0, 16) 2003#define VXGE_HAL_LAG_AGGR_ALT_ADMIN_KEY_ALT_AGGR mBIT(19) 2004/* 0x020a8 */ u64 lag_aggr_oper_key[2]; 2005#define VXGE_HAL_LAG_AGGR_OPER_KEY_LAGC_KEY(val) vBIT(val, 0, 16) 2006/* 0x020b8 */ u64 lag_aggr_partner_sys_id[2]; 2007#define VXGE_HAL_LAG_AGGR_PARTNER_SYS_ID_LAGC_ADDR(val) vBIT(val, 0, 48) 2008/* 0x020c8 */ u64 lag_aggr_partner_info[2]; 2009#define VXGE_HAL_LAG_AGGR_PARTNER_INFO_LAGC_SYS_PRI(val) vBIT(val, 0, 16) 2010#define VXGE_HAL_LAG_AGGR_PARTNER_INFO_LAGC_OPER_KEY(val) vBIT(val, 16, 16) 2011/* 0x020d8 */ u64 lag_aggr_state[2]; 2012#define VXGE_HAL_LAG_AGGR_STATE_LAGC_TX mBIT(3) 2013#define VXGE_HAL_LAG_AGGR_STATE_LAGC_RX mBIT(7) 2014#define VXGE_HAL_LAG_AGGR_STATE_LAGC_READY mBIT(11) 2015#define VXGE_HAL_LAG_AGGR_STATE_LAGC_INDIVIDUAL mBIT(15) 2016 u8 unused020f0[0x020f0 - 0x020e8]; 2017 2018/* 0x020f0 */ u64 lag_port_cfg[2]; 2019#define VXGE_HAL_LAG_PORT_CFG_EN mBIT(3) 2020#define VXGE_HAL_LAG_PORT_CFG_DISCARD_SLOW_PROTO mBIT(7) 2021#define VXGE_HAL_LAG_PORT_CFG_HOST_CHOSEN_AGGR mBIT(11) 2022#define VXGE_HAL_LAG_PORT_CFG_DISCARD_UNKNOWN_SLOW_PROTO mBIT(15) 2023/* 0x02100 */ u64 lag_port_actor_admin_cfg[2]; 2024#define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_PORT_NUM(val) vBIT(val, 0, 16) 2025#define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_PORT_PRI(val) vBIT(val, 16, 16) 2026#define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_KEY_10G(val) vBIT(val, 32, 16) 2027#define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_CFG_KEY_1G(val) vBIT(val, 48, 16) 2028/* 0x02110 */ u64 lag_port_actor_admin_state[2]; 2029#define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_LACP_ACTIVITY mBIT(3) 2030#define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_LACP_TIMEOUT mBIT(7) 2031#define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_AGGREGATION mBIT(11) 2032#define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_SYNCHRONIZATION mBIT(15) 2033#define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_COLLECTING mBIT(19) 2034#define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_DISTRIBUTING mBIT(23) 2035#define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_DEFAULTED mBIT(27) 2036#define VXGE_HAL_LAG_PORT_ACTOR_ADMIN_STATE_EXPIRED mBIT(31) 2037/* 0x02120 */ u64 lag_port_partner_admin_sys_id[2]; 2038#define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_SYS_ID_ADDR(val) vBIT(val, 0, 48) 2039/* 0x02130 */ u64 lag_port_partner_admin_cfg[2]; 2040#define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_SYS_PRI(val) vBIT(val, 0, 16) 2041#define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_KEY(val) vBIT(val, 16, 16) 2042#define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_PORT_NUM(val) vBIT(val, 32, 16) 2043#define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_CFG_PORT_PRI(val) vBIT(val, 48, 16) 2044/* 0x02140 */ u64 lag_port_partner_admin_state[2]; 2045#define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_LACP_ACTIVITY mBIT(3) 2046#define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_LACP_TIMEOUT mBIT(7) 2047#define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_AGGREGATION mBIT(11) 2048#define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_SYNCHRONIZATION mBIT(15) 2049#define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_COLLECTING mBIT(19) 2050#define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_DISTRIBUTING mBIT(23) 2051#define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_DEFAULTED mBIT(27) 2052#define VXGE_HAL_LAG_PORT_PARTNER_ADMIN_STATE_EXPIRED mBIT(31) 2053/* 0x02150 */ u64 lag_port_to_aggr[2]; 2054#define VXGE_HAL_LAG_PORT_TO_AGGR_LAGC_AGGR_ID(val) vBIT(val, 0, 16) 2055#define VXGE_HAL_LAG_PORT_TO_AGGR_LAGC_AGGR_VLD_ID mBIT(19) 2056/* 0x02160 */ u64 lag_port_actor_oper_key[2]; 2057#define VXGE_HAL_LAG_PORT_ACTOR_OPER_KEY_LAGC_KEY(val) vBIT(val, 0, 16) 2058/* 0x02170 */ u64 lag_port_actor_oper_state[2]; 2059#define VXGE_HAL_LAG_PORT_ACTOR_OPER_STATE_LAGC_LACP_ACTIVITY mBIT(3) 2060#define VXGE_HAL_LAG_PORT_ACTOR_OPER_STATE_LAGC_LACP_TIMEOUT mBIT(7) 2061#define VXGE_HAL_LAG_PORT_ACTOR_OPER_STATE_LAGC_AGGREGATION mBIT(11) 2062#define VXGE_HAL_LAG_PORT_ACTOR_OPER_STATE_LAGC_SYNCHRONIZATION mBIT(15) 2063#define VXGE_HAL_LAG_PORT_ACTOR_OPER_STATE_LAGC_COLLECTING mBIT(19) 2064#define VXGE_HAL_LAG_PORT_ACTOR_OPER_STATE_LAGC_DISTRIBUTING mBIT(23) 2065#define VXGE_HAL_LAG_PORT_ACTOR_OPER_STATE_LAGC_DEFAULTED mBIT(27) 2066#define VXGE_HAL_LAG_PORT_ACTOR_OPER_STATE_LAGC_EXPIRED mBIT(31) 2067/* 0x02180 */ u64 lag_port_partner_oper_sys_id[2]; 2068#define VXGE_HAL_LAG_PORT_PARTNER_OPER_SYS_ID_LAGC_ADDR(val) vBIT(val, 0, 48) 2069/* 0x02190 */ u64 lag_port_partner_oper_info[2]; 2070#define VXGE_HAL_LAG_PORT_PARTNER_OPER_INFO_LAGC_SYS_PRI(val) vBIT(val, 0, 16) 2071#define VXGE_HAL_LAG_PORT_PARTNER_OPER_INFO_LAGC_KEY(val) vBIT(val, 16, 16) 2072#define VXGE_HAL_LAG_PORT_PARTNER_OPER_INFO_LAGC_PORT_NUM(val) vBIT(val, 32, 16) 2073#define VXGE_HAL_LAG_PORT_PARTNER_OPER_INFO_LAGC_PORT_PRI(val) vBIT(val, 48, 16) 2074/* 0x021a0 */ u64 lag_port_partner_oper_state[2]; 2075#define VXGE_HAL_LAG_PORT_PARTNER_OPER_STATE_LAGC_LACP_ACTIVITY mBIT(3) 2076#define VXGE_HAL_LAG_PORT_PARTNER_OPER_STATE_LAGC_LACP_TIMEOUT mBIT(7) 2077#define VXGE_HAL_LAG_PORT_PARTNER_OPER_STATE_LAGC_AGGREGATION mBIT(11) 2078#define VXGE_HAL_LAG_PORT_PARTNER_OPER_STATE_LAGC_SYNCHRONIZATION mBIT(15) 2079#define VXGE_HAL_LAG_PORT_PARTNER_OPER_STATE_LAGC_COLLECTING mBIT(19) 2080#define VXGE_HAL_LAG_PORT_PARTNER_OPER_STATE_LAGC_DISTRIBUTING mBIT(23) 2081#define VXGE_HAL_LAG_PORT_PARTNER_OPER_STATE_LAGC_DEFAULTED mBIT(27) 2082#define VXGE_HAL_LAG_PORT_PARTNER_OPER_STATE_LAGC_EXPIRED mBIT(31) 2083/* 0x021b0 */ u64 lag_port_state_vars[2]; 2084#define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_READY mBIT(3) 2085#define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_SELECTED(val) vBIT(val, 6, 2) 2086#define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_AGGR_NUM mBIT(11) 2087#define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_PORT_MOVED mBIT(15) 2088#define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_PORT_ENABLED mBIT(18) 2089#define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_PORT_DISABLED mBIT(19) 2090#define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_NTT mBIT(23) 2091#define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN mBIT(27) 2092#define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN mBIT(31) 2093#define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_ACTOR_INFO_LEN_MISMATCH mBIT(32) 2094#define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_PARTNER_INFO_LEN_MISMATCH mBIT(33) 2095#define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_COLL_INFO_LEN_MISMATCH mBIT(34) 2096#define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_TERM_INFO_LEN_MISMATCH mBIT(35) 2097#define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_RX_FSM_STATE(val) vBIT(val, 37, 3) 2098#define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_MUX_FSM_STATE(val) vBIT(val, 41, 3) 2099#define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_MUX_REASON(val) vBIT(val, 44, 4) 2100#define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN_STATE mBIT(54) 2101#define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN_STATE mBIT(55) 2102#define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN_COUNT(val)\ 2103 vBIT(val, 56, 4) 2104#define VXGE_HAL_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN_COUNT(val)\ 2105 vBIT(val, 60, 4) 2106/* 0x021c0 */ u64 lag_port_timer_cntr[2]; 2107#define VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_CURRENT_while (val) vBIT(val, 0, 8) 2108#define VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_PERIODIC_while (val) vBIT(val, 8, 8) 2109#define VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_WAIT_while (val) vBIT(val, 16, 8) 2110#define VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_TX_LACP(val) vBIT(val, 24, 8) 2111#define VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_ACTOR_SYNC_TRANSITION_COUNT(val)\ 2112 vBIT(val, 32, 8) 2113#define VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_PARTNER_SYNC_TRANSITION_COUNT(val)\ 2114 vBIT(val, 40, 8) 2115#define VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_ACTOR_CHANGE_COUNT(val)\ 2116 vBIT(val, 48, 8) 2117#define VXGE_HAL_LAG_PORT_TIMER_CNTR_LAGC_PARTNER_CHANGE_COUNT(val)\ 2118 vBIT(val, 56, 8) 2119 u8 unused021e0[0x021e0 - 0x021d0]; 2120 2121/* 0x021e0 */ u64 transceiver_reset_port[2]; 2122#define VXGE_HAL_TRANSCEIVER_RESET_PORT_TCVR_RESET(val) vBIT(val, 0, 8) 2123/* 0x021f0 */ u64 transceiver_ctrl_port[2]; 2124#define VXGE_HAL_TRANSCEIVER_CTRL_PORT_TCVR_TX_ON mBIT(3) 2125/* 0x02200 */ u64 asic_gpio_ctrl; 2126#define VXGE_HAL_ASIC_GPIO_CTRL_XMACJ_GPIO_DATA_IN(n) mBIT(n) 2127#define VXGE_HAL_ASIC_GPIO_CTRL_GPIO_DATA_OUT(n) mBIT(n) 2128#define VXGE_HAL_ASIC_GPIO_CTRL_GPIO_OUT_EN(n) mBIT(n) 2129/* 0x02208 */ u64 asic_led_beacon_ctrl; 2130#define VXGE_HAL_ASIC_LED_BEACON_CTRL_PORT0_LINK_INVERT mBIT(3) 2131#define VXGE_HAL_ASIC_LED_BEACON_CTRL_PORT0_10G_INVERT mBIT(7) 2132#define VXGE_HAL_ASIC_LED_BEACON_CTRL_PORT0_TX_ACT_INVERT mBIT(11) 2133#define VXGE_HAL_ASIC_LED_BEACON_CTRL_PORT0_RX_ACT_INVERT mBIT(15) 2134#define VXGE_HAL_ASIC_LED_BEACON_CTRL_PORT1_LINK_INVERT mBIT(19) 2135#define VXGE_HAL_ASIC_LED_BEACON_CTRL_PORT1_10G_INVERT mBIT(23) 2136#define VXGE_HAL_ASIC_LED_BEACON_CTRL_PORT1_TX_ACT_INVERT mBIT(27) 2137#define VXGE_HAL_ASIC_LED_BEACON_CTRL_PORT1_RX_ACT_INVERT mBIT(31) 2138#define VXGE_HAL_ASIC_LED_BEACON_CTRL_AUX_LED1_INVERT mBIT(35) 2139#define VXGE_HAL_ASIC_LED_BEACON_CTRL_AUX_LED2_INVERT mBIT(39) 2140/* 0x02210 */ u64 asic_led_ctrl0; 2141#define VXGE_HAL_ASIC_LED_CTRL0_PORT0_LINK_ON mBIT(3) 2142#define VXGE_HAL_ASIC_LED_CTRL0_PORT0_10G_ON mBIT(7) 2143#define VXGE_HAL_ASIC_LED_CTRL0_PORT1_LINK_ON mBIT(19) 2144#define VXGE_HAL_ASIC_LED_CTRL0_PORT1_10G_ON mBIT(23) 2145#define VXGE_HAL_ASIC_LED_CTRL0_AUX_LED1_ON mBIT(35) 2146#define VXGE_HAL_ASIC_LED_CTRL0_AUX_LED2_ON mBIT(39) 2147/* 0x02218 */ u64 asic_led_ctrl1; 2148#define VXGE_HAL_ASIC_LED_CTRL1_PORT0_LINK_SOURCE(val) vBIT(val, 2, 2) 2149#define VXGE_HAL_ASIC_LED_CTRL1_PORT0_10G_SOURCE(val) vBIT(val, 6, 2) 2150#define VXGE_HAL_ASIC_LED_CTRL1_PORT1_LINK_SOURCE(val) vBIT(val, 10, 2) 2151#define VXGE_HAL_ASIC_LED_CTRL1_PORT1_10G_SOURCE(val) vBIT(val, 14, 2) 2152#define VXGE_HAL_ASIC_LED_CTRL1_PORT0_LINK_PULSE_EXTEND mBIT(19) 2153#define VXGE_HAL_ASIC_LED_CTRL1_PORT0_10G_PULSE_EXTEND mBIT(23) 2154#define VXGE_HAL_ASIC_LED_CTRL1_PORT1_LINK_PULSE_EXTEND mBIT(27) 2155#define VXGE_HAL_ASIC_LED_CTRL1_PORT1_10G_PULSE_EXTEND mBIT(31) 2156#define VXGE_HAL_ASIC_LED_CTRL1_PORT0_LINK_EXT_SEL(val) vBIT(val, 32, 4) 2157#define VXGE_HAL_ASIC_LED_CTRL1_PORT0_10G_EXT_SEL(val) vBIT(val, 36, 4) 2158#define VXGE_HAL_ASIC_LED_CTRL1_PORT1_LINK_EXT_SEL(val) vBIT(val, 40, 4) 2159#define VXGE_HAL_ASIC_LED_CTRL1_PORT1_10G_EXT_SEL(val) vBIT(val, 44, 4) 2160#define VXGE_HAL_ASIC_LED_CTRL1_PORT0_LINK_INT_SEL(val) vBIT(val, 48, 4) 2161#define VXGE_HAL_ASIC_LED_CTRL1_PORT0_10G_INT_SEL(val) vBIT(val, 52, 4) 2162#define VXGE_HAL_ASIC_LED_CTRL1_PORT1_LINK_INT_SEL(val) vBIT(val, 56, 4) 2163#define VXGE_HAL_ASIC_LED_CTRL1_PORT1_10G_INT_SEL(val) vBIT(val, 60, 4) 2164/* 0x02220 */ u64 asic_led_debug_sel; 2165#define VXGE_HAL_ASIC_LED_DEBUG_SEL_XGMAC_SEL0(val) vBIT(val, 2, 6) 2166#define VXGE_HAL_ASIC_LED_DEBUG_SEL_XGMAC_SEL1(val) vBIT(val, 10, 6) 2167#define VXGE_HAL_ASIC_LED_DEBUG_SEL_XGMAC_SEL2(val) vBIT(val, 18, 6) 2168#define VXGE_HAL_ASIC_LED_DEBUG_SEL_XGMAC_SEL3(val) vBIT(val, 26, 6) 2169 u8 unused02300[0x02300 - 0x02228]; 2170 2171/* 0x02300 */ u64 usdc_sgrp_partition; 2172#define VXGE_HAL_USDC_SGRP_PARTITION_ENABLE mBIT(7) 2173/* 0x02308 */ u64 usdc_ugrp_priority_0; 2174#define VXGE_HAL_USDC_UGRP_PRIORITY_0_NUMBER_0(val) vBIT(val, 3, 5) 2175/* 0x02310 */ u64 usdc_ugrp_priority_1; 2176#define VXGE_HAL_USDC_UGRP_PRIORITY_1_NUMBER_1(val) vBIT(val, 3, 5) 2177/* 0x02318 */ u64 usdc_ugrp_priority_2; 2178#define VXGE_HAL_USDC_UGRP_PRIORITY_2_NUMBER_2(val) vBIT(val, 3, 5) 2179/* 0x02320 */ u64 usdc_ugrp_priority_3; 2180#define VXGE_HAL_USDC_UGRP_PRIORITY_3_NUMBER_3(val) vBIT(val, 3, 5) 2181/* 0x02328 */ u64 usdc_ugrp_priority_4; 2182#define VXGE_HAL_USDC_UGRP_PRIORITY_4_NUMBER_4(val) vBIT(val, 3, 5) 2183/* 0x02330 */ u64 usdc_ugrp_priority_5; 2184#define VXGE_HAL_USDC_UGRP_PRIORITY_5_NUMBER_5(val) vBIT(val, 3, 5) 2185/* 0x02338 */ u64 usdc_ugrp_priority_6; 2186#define VXGE_HAL_USDC_UGRP_PRIORITY_6_NUMBER_6(val) vBIT(val, 3, 5) 2187/* 0x02340 */ u64 usdc_ugrp_priority_7; 2188#define VXGE_HAL_USDC_UGRP_PRIORITY_7_NUMBER_7(val) vBIT(val, 3, 5) 2189/* 0x02348 */ u64 usdc_ugrp_priority_8; 2190#define VXGE_HAL_USDC_UGRP_PRIORITY_8_NUMBER_8(val) vBIT(val, 3, 5) 2191/* 0x02350 */ u64 usdc_ugrp_priority_9; 2192#define VXGE_HAL_USDC_UGRP_PRIORITY_9_NUMBER_9(val) vBIT(val, 3, 5) 2193/* 0x02358 */ u64 usdc_ugrp_priority_10; 2194#define VXGE_HAL_USDC_UGRP_PRIORITY_10_NUMBER_10(val) vBIT(val, 3, 5) 2195/* 0x02360 */ u64 usdc_ugrp_priority_11; 2196#define VXGE_HAL_USDC_UGRP_PRIORITY_11_NUMBER_11(val) vBIT(val, 3, 5) 2197/* 0x02368 */ u64 usdc_ugrp_priority_12; 2198#define VXGE_HAL_USDC_UGRP_PRIORITY_12_NUMBER_12(val) vBIT(val, 3, 5) 2199/* 0x02370 */ u64 usdc_ugrp_priority_13; 2200#define VXGE_HAL_USDC_UGRP_PRIORITY_13_NUMBER_13(val) vBIT(val, 3, 5) 2201/* 0x02378 */ u64 usdc_ugrp_priority_14; 2202#define VXGE_HAL_USDC_UGRP_PRIORITY_14_NUMBER_14(val) vBIT(val, 3, 5) 2203/* 0x02380 */ u64 usdc_ugrp_priority_15; 2204#define VXGE_HAL_USDC_UGRP_PRIORITY_15_NUMBER_15(val) vBIT(val, 3, 5) 2205/* 0x02388 */ u64 usdc_ugrp_priority_16; 2206#define VXGE_HAL_USDC_UGRP_PRIORITY_16_NUMBER_16(val) vBIT(val, 3, 5) 2207 u8 unused02398[0x02398 - 0x02390]; 2208 2209/* 0x02398 */ u64 ugrp_htn_wrr_priority_0; 2210#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_0(val) vBIT(val, 3, 5) 2211#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_1(val) vBIT(val, 11, 5) 2212#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_2(val) vBIT(val, 19, 5) 2213#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_3(val) vBIT(val, 27, 5) 2214#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_4(val) vBIT(val, 35, 5) 2215#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_5(val) vBIT(val, 43, 5) 2216#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_6(val) vBIT(val, 51, 5) 2217#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_0_NUMBER_7(val) vBIT(val, 59, 5) 2218/* 0x023a0 */ u64 ugrp_htn_wrr_priority_1; 2219#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_8(val) vBIT(val, 3, 5) 2220#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_9(val) vBIT(val, 11, 5) 2221#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_10(val) vBIT(val, 19, 5) 2222#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_11(val) vBIT(val, 27, 5) 2223#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_12(val) vBIT(val, 35, 5) 2224#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_13(val) vBIT(val, 43, 5) 2225#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_14(val) vBIT(val, 51, 5) 2226#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_1_NUMBER_15(val) vBIT(val, 59, 5) 2227/* 0x023a8 */ u64 ugrp_htn_wrr_priority_2; 2228#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_16(val) vBIT(val, 3, 5) 2229#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_17(val) vBIT(val, 11, 5) 2230#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_18(val) vBIT(val, 19, 5) 2231#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_19(val) vBIT(val, 27, 5) 2232#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_20(val) vBIT(val, 35, 5) 2233#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_21(val) vBIT(val, 43, 5) 2234#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_22(val) vBIT(val, 51, 5) 2235#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_2_NUMBER_23(val) vBIT(val, 59, 5) 2236/* 0x023b0 */ u64 ugrp_htn_wrr_priority_3; 2237#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_24(val) vBIT(val, 3, 5) 2238#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_25(val) vBIT(val, 11, 5) 2239#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_26(val) vBIT(val, 19, 5) 2240#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_27(val) vBIT(val, 27, 5) 2241#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_28(val) vBIT(val, 35, 5) 2242#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_29(val) vBIT(val, 43, 5) 2243#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_30(val) vBIT(val, 51, 5) 2244#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_3_NUMBER_31(val) vBIT(val, 59, 5) 2245/* 0x023b8 */ u64 ugrp_htn_wrr_priority_4; 2246#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_32(val) vBIT(val, 3, 5) 2247#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_33(val) vBIT(val, 11, 5) 2248#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_34(val) vBIT(val, 19, 5) 2249#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_35(val) vBIT(val, 27, 5) 2250#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_36(val) vBIT(val, 35, 5) 2251#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_37(val) vBIT(val, 43, 5) 2252#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_38(val) vBIT(val, 51, 5) 2253#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_4_NUMBER_39(val) vBIT(val, 59, 5) 2254/* 0x023c0 */ u64 ugrp_htn_wrr_priority_5; 2255#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_40(val) vBIT(val, 3, 5) 2256#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_41(val) vBIT(val, 11, 5) 2257#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_42(val) vBIT(val, 19, 5) 2258#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_43(val) vBIT(val, 27, 5) 2259#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_44(val) vBIT(val, 35, 5) 2260#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_45(val) vBIT(val, 43, 5) 2261#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_46(val) vBIT(val, 51, 5) 2262#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_5_NUMBER_47(val) vBIT(val, 59, 5) 2263/* 0x023c8 */ u64 ugrp_htn_wrr_priority_6; 2264#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_48(val) vBIT(val, 3, 5) 2265#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_49(val) vBIT(val, 11, 5) 2266#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_50(val) vBIT(val, 19, 5) 2267#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_51(val) vBIT(val, 27, 5) 2268#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_52(val) vBIT(val, 35, 5) 2269#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_53(val) vBIT(val, 43, 5) 2270#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_54(val) vBIT(val, 51, 5) 2271#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_6_NUMBER_55(val) vBIT(val, 59, 5) 2272/* 0x023d0 */ u64 ugrp_htn_wrr_priority_7; 2273#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_56(val) vBIT(val, 3, 5) 2274#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_57(val) vBIT(val, 11, 5) 2275#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_58(val) vBIT(val, 19, 5) 2276#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_59(val) vBIT(val, 27, 5) 2277#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_60(val) vBIT(val, 35, 5) 2278#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_61(val) vBIT(val, 43, 5) 2279#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_62(val) vBIT(val, 51, 5) 2280#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_7_NUMBER_63(val) vBIT(val, 59, 5) 2281/* 0x023d8 */ u64 ugrp_htn_wrr_priority_8; 2282#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_64(val) vBIT(val, 3, 5) 2283#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_65(val) vBIT(val, 11, 5) 2284#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_66(val) vBIT(val, 19, 5) 2285#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_67(val) vBIT(val, 27, 5) 2286#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_68(val) vBIT(val, 35, 5) 2287#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_69(val) vBIT(val, 43, 5) 2288#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_70(val) vBIT(val, 51, 5) 2289#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_8_NUMBER_71(val) vBIT(val, 59, 5) 2290/* 0x023e0 */ u64 ugrp_htn_wrr_priority_9; 2291#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_72(val) vBIT(val, 3, 5) 2292#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_73(val) vBIT(val, 11, 5) 2293#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_74(val) vBIT(val, 19, 5) 2294#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_75(val) vBIT(val, 27, 5) 2295#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_76(val) vBIT(val, 35, 5) 2296#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_77(val) vBIT(val, 43, 5) 2297#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_78(val) vBIT(val, 51, 5) 2298#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_9_NUMBER_79(val) vBIT(val, 59, 5) 2299/* 0x023e8 */ u64 ugrp_htn_wrr_priority_10; 2300#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_80(val) vBIT(val, 3, 5) 2301#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_81(val) vBIT(val, 11, 5) 2302#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_82(val) vBIT(val, 19, 5) 2303#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_83(val) vBIT(val, 27, 5) 2304#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_84(val) vBIT(val, 35, 5) 2305#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_85(val) vBIT(val, 43, 5) 2306#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_86(val) vBIT(val, 51, 5) 2307#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_10_NUMBER_87(val) vBIT(val, 59, 5) 2308/* 0x023f0 */ u64 ugrp_htn_wrr_priority_11; 2309#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_88(val) vBIT(val, 3, 5) 2310#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_89(val) vBIT(val, 11, 5) 2311#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_90(val) vBIT(val, 19, 5) 2312#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_91(val) vBIT(val, 27, 5) 2313#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_92(val) vBIT(val, 35, 5) 2314#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_93(val) vBIT(val, 43, 5) 2315#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_94(val) vBIT(val, 51, 5) 2316#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_11_NUMBER_95(val) vBIT(val, 59, 5) 2317/* 0x023f8 */ u64 ugrp_htn_wrr_priority_12; 2318#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_96(val) vBIT(val, 3, 5) 2319#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_97(val) vBIT(val, 11, 5) 2320#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_98(val) vBIT(val, 19, 5) 2321#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_99(val) vBIT(val, 27, 5) 2322#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_100(val) vBIT(val, 35, 5) 2323#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_101(val) vBIT(val, 43, 5) 2324#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_102(val) vBIT(val, 51, 5) 2325#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_12_NUMBER_103(val) vBIT(val, 59, 5) 2326/* 0x02400 */ u64 ugrp_htn_wrr_priority_13; 2327#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_104(val) vBIT(val, 3, 5) 2328#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_105(val) vBIT(val, 11, 5) 2329#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_106(val) vBIT(val, 19, 5) 2330#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_107(val) vBIT(val, 27, 5) 2331#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_108(val) vBIT(val, 35, 5) 2332#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_109(val) vBIT(val, 43, 5) 2333#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_110(val) vBIT(val, 51, 5) 2334#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_13_NUMBER_111(val) vBIT(val, 59, 5) 2335/* 0x02408 */ u64 ugrp_htn_wrr_priority_14; 2336#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_112(val) vBIT(val, 3, 5) 2337#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_113(val) vBIT(val, 11, 5) 2338#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_114(val) vBIT(val, 19, 5) 2339#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_115(val) vBIT(val, 27, 5) 2340#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_116(val) vBIT(val, 35, 5) 2341#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_117(val) vBIT(val, 43, 5) 2342#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_118(val) vBIT(val, 51, 5) 2343#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_14_NUMBER_119(val) vBIT(val, 59, 5) 2344/* 0x02410 */ u64 ugrp_htn_wrr_priority_15; 2345#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_120(val) vBIT(val, 3, 5) 2346#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_121(val) vBIT(val, 11, 5) 2347#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_122(val) vBIT(val, 19, 5) 2348#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_123(val) vBIT(val, 27, 5) 2349#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_124(val) vBIT(val, 35, 5) 2350#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_125(val) vBIT(val, 43, 5) 2351#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_126(val) vBIT(val, 51, 5) 2352#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_15_NUMBER_127(val) vBIT(val, 59, 5) 2353/* 0x02418 */ u64 ugrp_htn_wrr_priority_16; 2354#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_128(val) vBIT(val, 3, 5) 2355#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_129(val) vBIT(val, 11, 5) 2356#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_130(val) vBIT(val, 19, 5) 2357#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_131(val) vBIT(val, 27, 5) 2358#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_132(val) vBIT(val, 35, 5) 2359#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_133(val) vBIT(val, 43, 5) 2360#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_134(val) vBIT(val, 51, 5) 2361#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_16_NUMBER_135(val) vBIT(val, 59, 5) 2362/* 0x02420 */ u64 ugrp_htn_wrr_priority_17; 2363#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_136(val) vBIT(val, 3, 5) 2364#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_137(val) vBIT(val, 11, 5) 2365#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_138(val) vBIT(val, 19, 5) 2366#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_139(val) vBIT(val, 27, 5) 2367#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_140(val) vBIT(val, 35, 5) 2368#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_141(val) vBIT(val, 43, 5) 2369#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_142(val) vBIT(val, 51, 5) 2370#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_17_NUMBER_143(val) vBIT(val, 59, 5) 2371/* 0x02428 */ u64 ugrp_htn_wrr_priority_18; 2372#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_144(val) vBIT(val, 3, 5) 2373#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_145(val) vBIT(val, 11, 5) 2374#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_146(val) vBIT(val, 19, 5) 2375#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_147(val) vBIT(val, 27, 5) 2376#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_148(val) vBIT(val, 35, 5) 2377#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_149(val) vBIT(val, 43, 5) 2378#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_150(val) vBIT(val, 51, 5) 2379#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_18_NUMBER_151(val) vBIT(val, 59, 5) 2380/* 0x02430 */ u64 ugrp_htn_wrr_priority_19; 2381#define VXGE_HAL_UGRP_HTN_WRR_PRIORITY_19_NUMBER_152(val) vBIT(val, 3, 5) 2382/* 0x02438 */ u64 usdc_vplane[17]; 2383#define VXGE_HAL_USDC_VPLANE_SGRP_OWN(val) vBIT(val, 0, 32) 2384 u8 unused024c8[0x024c8 - 0x024c0]; 2385 2386/* 0x024c8 */ u64 usdc_sgrp_assignment; 2387#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_0_ERR mBIT(0) 2388#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_1_ERR mBIT(1) 2389#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_2_ERR mBIT(2) 2390#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_3_ERR mBIT(3) 2391#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_4_ERR mBIT(4) 2392#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_5_ERR mBIT(5) 2393#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_6_ERR mBIT(6) 2394#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_7_ERR mBIT(7) 2395#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_8_ERR mBIT(8) 2396#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_9_ERR mBIT(9) 2397#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_10_ERR mBIT(10) 2398#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_11_ERR mBIT(11) 2399#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_12_ERR mBIT(12) 2400#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_13_ERR mBIT(13) 2401#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_14_ERR mBIT(14) 2402#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_15_ERR mBIT(15) 2403#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_16_ERR mBIT(16) 2404#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_17_ERR mBIT(17) 2405#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_18_ERR mBIT(18) 2406#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_19_ERR mBIT(19) 2407#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_20_ERR mBIT(20) 2408#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_21_ERR mBIT(21) 2409#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_22_ERR mBIT(22) 2410#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_23_ERR mBIT(23) 2411#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_24_ERR mBIT(24) 2412#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_25_ERR mBIT(25) 2413#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_26_ERR mBIT(26) 2414#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_27_ERR mBIT(27) 2415#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_28_ERR mBIT(28) 2416#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_29_ERR mBIT(29) 2417#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_30_ERR mBIT(30) 2418#define VXGE_HAL_USDC_SGRP_ASSIGNMENT_USDC_SGRP_31_ERR mBIT(31) 2419/* 0x024d0 */ u64 usdc_cntrl; 2420#define VXGE_HAL_USDC_CNTRL_MIN_VALUE(val) vBIT(val, 1, 7) 2421/* 0x024d8 */ u64 usdc_read_cntrl; 2422#define VXGE_HAL_USDC_READ_CNTRL_USDC_FREEZE mBIT(7) 2423#define VXGE_HAL_USDC_READ_CNTRL_USDC_RDCTRL(val) vBIT(val, 14, 2) 2424#define VXGE_HAL_USDC_READ_CNTRL_USDC_WORD_SEL mBIT(23) 2425#define VXGE_HAL_USDC_READ_CNTRL_USDC_ADDR(val) vBIT(val, 49, 15) 2426/* 0x024e0 */ u64 usdc_read_data; 2427#define VXGE_HAL_USDC_READ_DATA_READ_DATA(val) vBIT(val, 0, 64) 2428 u8 unused02500[0x02500 - 0x024e8]; 2429 2430/* 0x02500 */ u64 ugrp_srq_wrr_priority_0; 2431#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_0(val) vBIT(val, 3, 5) 2432#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_1(val) vBIT(val, 11, 5) 2433#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_2(val) vBIT(val, 19, 5) 2434#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_3(val) vBIT(val, 27, 5) 2435#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_4(val) vBIT(val, 35, 5) 2436#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_5(val) vBIT(val, 43, 5) 2437#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_6(val) vBIT(val, 51, 5) 2438#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_0_NUMBER_7(val) vBIT(val, 59, 5) 2439/* 0x02508 */ u64 ugrp_srq_wrr_priority_1; 2440#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_8(val) vBIT(val, 3, 5) 2441#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_9(val) vBIT(val, 11, 5) 2442#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_10(val) vBIT(val, 19, 5) 2443#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_11(val) vBIT(val, 27, 5) 2444#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_12(val) vBIT(val, 35, 5) 2445#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_13(val) vBIT(val, 43, 5) 2446#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_14(val) vBIT(val, 51, 5) 2447#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_1_NUMBER_15(val) vBIT(val, 59, 5) 2448/* 0x02510 */ u64 ugrp_srq_wrr_priority_2; 2449#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_16(val) vBIT(val, 3, 5) 2450#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_17(val) vBIT(val, 11, 5) 2451#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_18(val) vBIT(val, 19, 5) 2452#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_19(val) vBIT(val, 27, 5) 2453#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_20(val) vBIT(val, 35, 5) 2454#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_21(val) vBIT(val, 43, 5) 2455#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_22(val) vBIT(val, 51, 5) 2456#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_2_NUMBER_23(val) vBIT(val, 59, 5) 2457/* 0x02518 */ u64 ugrp_srq_wrr_priority_3; 2458#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_24(val) vBIT(val, 3, 5) 2459#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_25(val) vBIT(val, 11, 5) 2460#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_26(val) vBIT(val, 19, 5) 2461#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_27(val) vBIT(val, 27, 5) 2462#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_28(val) vBIT(val, 35, 5) 2463#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_29(val) vBIT(val, 43, 5) 2464#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_30(val) vBIT(val, 51, 5) 2465#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_3_NUMBER_31(val) vBIT(val, 59, 5) 2466/* 0x02520 */ u64 ugrp_srq_wrr_priority_4; 2467#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_32(val) vBIT(val, 3, 5) 2468#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_33(val) vBIT(val, 11, 5) 2469#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_34(val) vBIT(val, 19, 5) 2470#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_35(val) vBIT(val, 27, 5) 2471#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_36(val) vBIT(val, 35, 5) 2472#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_37(val) vBIT(val, 43, 5) 2473#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_38(val) vBIT(val, 51, 5) 2474#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_4_NUMBER_39(val) vBIT(val, 59, 5) 2475/* 0x02528 */ u64 ugrp_srq_wrr_priority_5; 2476#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_40(val) vBIT(val, 3, 5) 2477#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_41(val) vBIT(val, 11, 5) 2478#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_42(val) vBIT(val, 19, 5) 2479#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_43(val) vBIT(val, 27, 5) 2480#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_44(val) vBIT(val, 35, 5) 2481#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_45(val) vBIT(val, 43, 5) 2482#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_46(val) vBIT(val, 51, 5) 2483#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_5_NUMBER_47(val) vBIT(val, 59, 5) 2484/* 0x02530 */ u64 ugrp_srq_wrr_priority_6; 2485#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_48(val) vBIT(val, 3, 5) 2486#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_49(val) vBIT(val, 11, 5) 2487#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_50(val) vBIT(val, 19, 5) 2488#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_51(val) vBIT(val, 27, 5) 2489#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_52(val) vBIT(val, 35, 5) 2490#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_53(val) vBIT(val, 43, 5) 2491#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_54(val) vBIT(val, 51, 5) 2492#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_6_NUMBER_55(val) vBIT(val, 59, 5) 2493/* 0x02538 */ u64 ugrp_srq_wrr_priority_7; 2494#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_56(val) vBIT(val, 3, 5) 2495#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_57(val) vBIT(val, 11, 5) 2496#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_58(val) vBIT(val, 19, 5) 2497#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_59(val) vBIT(val, 27, 5) 2498#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_60(val) vBIT(val, 35, 5) 2499#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_61(val) vBIT(val, 43, 5) 2500#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_62(val) vBIT(val, 51, 5) 2501#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_7_NUMBER_63(val) vBIT(val, 59, 5) 2502/* 0x02540 */ u64 ugrp_srq_wrr_priority_8; 2503#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_64(val) vBIT(val, 3, 5) 2504#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_65(val) vBIT(val, 11, 5) 2505#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_66(val) vBIT(val, 19, 5) 2506#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_67(val) vBIT(val, 27, 5) 2507#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_68(val) vBIT(val, 35, 5) 2508#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_69(val) vBIT(val, 43, 5) 2509#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_70(val) vBIT(val, 51, 5) 2510#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_8_NUMBER_71(val) vBIT(val, 59, 5) 2511/* 0x02548 */ u64 ugrp_srq_wrr_priority_9; 2512#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_72(val) vBIT(val, 3, 5) 2513#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_73(val) vBIT(val, 11, 5) 2514#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_74(val) vBIT(val, 19, 5) 2515#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_75(val) vBIT(val, 27, 5) 2516#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_76(val) vBIT(val, 35, 5) 2517#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_77(val) vBIT(val, 43, 5) 2518#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_78(val) vBIT(val, 51, 5) 2519#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_9_NUMBER_79(val) vBIT(val, 59, 5) 2520/* 0x02550 */ u64 ugrp_srq_wrr_priority_10; 2521#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_80(val) vBIT(val, 3, 5) 2522#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_81(val) vBIT(val, 11, 5) 2523#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_82(val) vBIT(val, 19, 5) 2524#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_83(val) vBIT(val, 27, 5) 2525#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_84(val) vBIT(val, 35, 5) 2526#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_85(val) vBIT(val, 43, 5) 2527#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_86(val) vBIT(val, 51, 5) 2528#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_10_NUMBER_87(val) vBIT(val, 59, 5) 2529/* 0x02558 */ u64 ugrp_srq_wrr_priority_11; 2530#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_88(val) vBIT(val, 3, 5) 2531#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_89(val) vBIT(val, 11, 5) 2532#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_90(val) vBIT(val, 19, 5) 2533#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_91(val) vBIT(val, 27, 5) 2534#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_92(val) vBIT(val, 35, 5) 2535#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_93(val) vBIT(val, 43, 5) 2536#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_94(val) vBIT(val, 51, 5) 2537#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_11_NUMBER_95(val) vBIT(val, 59, 5) 2538/* 0x02560 */ u64 ugrp_srq_wrr_priority_12; 2539#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_96(val) vBIT(val, 3, 5) 2540#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_97(val) vBIT(val, 11, 5) 2541#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_98(val) vBIT(val, 19, 5) 2542#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_99(val) vBIT(val, 27, 5) 2543#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_100(val) vBIT(val, 35, 5) 2544#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_101(val) vBIT(val, 43, 5) 2545#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_102(val) vBIT(val, 51, 5) 2546#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_12_NUMBER_103(val) vBIT(val, 59, 5) 2547/* 0x02568 */ u64 ugrp_srq_wrr_priority_13; 2548#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_104(val) vBIT(val, 3, 5) 2549#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_105(val) vBIT(val, 11, 5) 2550#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_106(val) vBIT(val, 19, 5) 2551#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_107(val) vBIT(val, 27, 5) 2552#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_108(val) vBIT(val, 35, 5) 2553#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_109(val) vBIT(val, 43, 5) 2554#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_110(val) vBIT(val, 51, 5) 2555#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_13_NUMBER_111(val) vBIT(val, 59, 5) 2556/* 0x02570 */ u64 ugrp_srq_wrr_priority_14; 2557#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_112(val) vBIT(val, 3, 5) 2558#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_113(val) vBIT(val, 11, 5) 2559#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_114(val) vBIT(val, 19, 5) 2560#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_115(val) vBIT(val, 27, 5) 2561#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_116(val) vBIT(val, 35, 5) 2562#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_117(val) vBIT(val, 43, 5) 2563#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_118(val) vBIT(val, 51, 5) 2564#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_14_NUMBER_119(val) vBIT(val, 59, 5) 2565/* 0x02578 */ u64 ugrp_srq_wrr_priority_15; 2566#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_120(val) vBIT(val, 3, 5) 2567#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_121(val) vBIT(val, 11, 5) 2568#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_122(val) vBIT(val, 19, 5) 2569#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_123(val) vBIT(val, 27, 5) 2570#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_124(val) vBIT(val, 35, 5) 2571#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_125(val) vBIT(val, 43, 5) 2572#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_126(val) vBIT(val, 51, 5) 2573#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_15_NUMBER_127(val) vBIT(val, 59, 5) 2574/* 0x02580 */ u64 ugrp_srq_wrr_priority_16; 2575#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_128(val) vBIT(val, 3, 5) 2576#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_129(val) vBIT(val, 11, 5) 2577#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_130(val) vBIT(val, 19, 5) 2578#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_131(val) vBIT(val, 27, 5) 2579#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_132(val) vBIT(val, 35, 5) 2580#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_133(val) vBIT(val, 43, 5) 2581#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_134(val) vBIT(val, 51, 5) 2582#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_16_NUMBER_135(val) vBIT(val, 59, 5) 2583/* 0x02588 */ u64 ugrp_srq_wrr_priority_17; 2584#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_136(val) vBIT(val, 3, 5) 2585#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_137(val) vBIT(val, 11, 5) 2586#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_138(val) vBIT(val, 19, 5) 2587#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_139(val) vBIT(val, 27, 5) 2588#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_140(val) vBIT(val, 35, 5) 2589#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_141(val) vBIT(val, 43, 5) 2590#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_142(val) vBIT(val, 51, 5) 2591#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_17_NUMBER_143(val) vBIT(val, 59, 5) 2592/* 0x02590 */ u64 ugrp_srq_wrr_priority_18; 2593#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_144(val) vBIT(val, 3, 5) 2594#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_145(val) vBIT(val, 11, 5) 2595#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_146(val) vBIT(val, 19, 5) 2596#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_147(val) vBIT(val, 27, 5) 2597#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_148(val) vBIT(val, 35, 5) 2598#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_149(val) vBIT(val, 43, 5) 2599#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_150(val) vBIT(val, 51, 5) 2600#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_18_NUMBER_151(val) vBIT(val, 59, 5) 2601/* 0x02598 */ u64 ugrp_srq_wrr_priority_19; 2602#define VXGE_HAL_UGRP_SRQ_WRR_PRIORITY_19_NUMBER_152(val) vBIT(val, 3, 5) 2603/* 0x025a0 */ u64 ugrp_cqrq_wrr_priority_0; 2604#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_0(val) vBIT(val, 3, 5) 2605#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_1(val) vBIT(val, 11, 5) 2606#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_2(val) vBIT(val, 19, 5) 2607#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_3(val) vBIT(val, 27, 5) 2608#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_4(val) vBIT(val, 35, 5) 2609#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_5(val) vBIT(val, 43, 5) 2610#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_6(val) vBIT(val, 51, 5) 2611#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_0_NUMBER_7(val) vBIT(val, 59, 5) 2612/* 0x025a8 */ u64 ugrp_cqrq_wrr_priority_1; 2613#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_8(val) vBIT(val, 3, 5) 2614#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_9(val) vBIT(val, 11, 5) 2615#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_10(val) vBIT(val, 19, 5) 2616#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_11(val) vBIT(val, 27, 5) 2617#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_12(val) vBIT(val, 35, 5) 2618#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_13(val) vBIT(val, 43, 5) 2619#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_14(val) vBIT(val, 51, 5) 2620#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_1_NUMBER_15(val) vBIT(val, 59, 5) 2621/* 0x025b0 */ u64 ugrp_cqrq_wrr_priority_2; 2622#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_16(val) vBIT(val, 3, 5) 2623#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_17(val) vBIT(val, 11, 5) 2624#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_18(val) vBIT(val, 19, 5) 2625#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_19(val) vBIT(val, 27, 5) 2626#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_20(val) vBIT(val, 35, 5) 2627#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_21(val) vBIT(val, 43, 5) 2628#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_22(val) vBIT(val, 51, 5) 2629#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_2_NUMBER_23(val) vBIT(val, 59, 5) 2630/* 0x025b8 */ u64 ugrp_cqrq_wrr_priority_3; 2631#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_24(val) vBIT(val, 3, 5) 2632#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_25(val) vBIT(val, 11, 5) 2633#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_26(val) vBIT(val, 19, 5) 2634#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_27(val) vBIT(val, 27, 5) 2635#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_28(val) vBIT(val, 35, 5) 2636#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_29(val) vBIT(val, 43, 5) 2637#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_30(val) vBIT(val, 51, 5) 2638#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_3_NUMBER_31(val) vBIT(val, 59, 5) 2639/* 0x025c0 */ u64 ugrp_cqrq_wrr_priority_4; 2640#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_32(val) vBIT(val, 3, 5) 2641#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_33(val) vBIT(val, 11, 5) 2642#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_34(val) vBIT(val, 19, 5) 2643#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_35(val) vBIT(val, 27, 5) 2644#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_36(val) vBIT(val, 35, 5) 2645#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_37(val) vBIT(val, 43, 5) 2646#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_38(val) vBIT(val, 51, 5) 2647#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_4_NUMBER_39(val) vBIT(val, 59, 5) 2648/* 0x025c8 */ u64 ugrp_cqrq_wrr_priority_5; 2649#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_40(val) vBIT(val, 3, 5) 2650#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_41(val) vBIT(val, 11, 5) 2651#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_42(val) vBIT(val, 19, 5) 2652#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_43(val) vBIT(val, 27, 5) 2653#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_44(val) vBIT(val, 35, 5) 2654#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_45(val) vBIT(val, 43, 5) 2655#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_46(val) vBIT(val, 51, 5) 2656#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_5_NUMBER_47(val) vBIT(val, 59, 5) 2657/* 0x025d0 */ u64 ugrp_cqrq_wrr_priority_6; 2658#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_48(val) vBIT(val, 3, 5) 2659#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_49(val) vBIT(val, 11, 5) 2660#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_50(val) vBIT(val, 19, 5) 2661#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_51(val) vBIT(val, 27, 5) 2662#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_52(val) vBIT(val, 35, 5) 2663#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_53(val) vBIT(val, 43, 5) 2664#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_54(val) vBIT(val, 51, 5) 2665#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_6_NUMBER_55(val) vBIT(val, 59, 5) 2666/* 0x025d8 */ u64 ugrp_cqrq_wrr_priority_7; 2667#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_56(val) vBIT(val, 3, 5) 2668#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_57(val) vBIT(val, 11, 5) 2669#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_58(val) vBIT(val, 19, 5) 2670#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_59(val) vBIT(val, 27, 5) 2671#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_60(val) vBIT(val, 35, 5) 2672#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_61(val) vBIT(val, 43, 5) 2673#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_62(val) vBIT(val, 51, 5) 2674#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_7_NUMBER_63(val) vBIT(val, 59, 5) 2675/* 0x025e0 */ u64 ugrp_cqrq_wrr_priority_8; 2676#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_64(val) vBIT(val, 3, 5) 2677#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_65(val) vBIT(val, 11, 5) 2678#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_66(val) vBIT(val, 19, 5) 2679#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_67(val) vBIT(val, 27, 5) 2680#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_68(val) vBIT(val, 35, 5) 2681#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_69(val) vBIT(val, 43, 5) 2682#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_70(val) vBIT(val, 51, 5) 2683#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_8_NUMBER_71(val) vBIT(val, 59, 5) 2684/* 0x025e8 */ u64 ugrp_cqrq_wrr_priority_9; 2685#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_72(val) vBIT(val, 3, 5) 2686#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_73(val) vBIT(val, 11, 5) 2687#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_74(val) vBIT(val, 19, 5) 2688#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_75(val) vBIT(val, 27, 5) 2689#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_76(val) vBIT(val, 35, 5) 2690#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_77(val) vBIT(val, 43, 5) 2691#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_78(val) vBIT(val, 51, 5) 2692#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_9_NUMBER_79(val) vBIT(val, 59, 5) 2693/* 0x025f0 */ u64 ugrp_cqrq_wrr_priority_10; 2694#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_80(val) vBIT(val, 3, 5) 2695#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_81(val) vBIT(val, 11, 5) 2696#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_82(val) vBIT(val, 19, 5) 2697#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_83(val) vBIT(val, 27, 5) 2698#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_84(val) vBIT(val, 35, 5) 2699#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_85(val) vBIT(val, 43, 5) 2700#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_86(val) vBIT(val, 51, 5) 2701#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_10_NUMBER_87(val) vBIT(val, 59, 5) 2702/* 0x025f8 */ u64 ugrp_cqrq_wrr_priority_11; 2703#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_88(val) vBIT(val, 3, 5) 2704#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_89(val) vBIT(val, 11, 5) 2705#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_90(val) vBIT(val, 19, 5) 2706#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_91(val) vBIT(val, 27, 5) 2707#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_92(val) vBIT(val, 35, 5) 2708#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_93(val) vBIT(val, 43, 5) 2709#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_94(val) vBIT(val, 51, 5) 2710#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_11_NUMBER_95(val) vBIT(val, 59, 5) 2711/* 0x02600 */ u64 ugrp_cqrq_wrr_priority_12; 2712#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_96(val) vBIT(val, 3, 5) 2713#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_97(val) vBIT(val, 11, 5) 2714#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_98(val) vBIT(val, 19, 5) 2715#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_99(val) vBIT(val, 27, 5) 2716#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_100(val) vBIT(val, 35, 5) 2717#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_101(val) vBIT(val, 43, 5) 2718#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_102(val) vBIT(val, 51, 5) 2719#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_12_NUMBER_103(val) vBIT(val, 59, 5) 2720/* 0x02608 */ u64 ugrp_cqrq_wrr_priority_13; 2721#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_104(val) vBIT(val, 3, 5) 2722#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_105(val) vBIT(val, 11, 5) 2723#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_106(val) vBIT(val, 19, 5) 2724#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_107(val) vBIT(val, 27, 5) 2725#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_108(val) vBIT(val, 35, 5) 2726#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_109(val) vBIT(val, 43, 5) 2727#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_110(val) vBIT(val, 51, 5) 2728#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_13_NUMBER_111(val) vBIT(val, 59, 5) 2729/* 0x02610 */ u64 ugrp_cqrq_wrr_priority_14; 2730#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_112(val) vBIT(val, 3, 5) 2731#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_113(val) vBIT(val, 11, 5) 2732#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_114(val) vBIT(val, 19, 5) 2733#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_115(val) vBIT(val, 27, 5) 2734#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_116(val) vBIT(val, 35, 5) 2735#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_117(val) vBIT(val, 43, 5) 2736#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_118(val) vBIT(val, 51, 5) 2737#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_14_NUMBER_119(val) vBIT(val, 59, 5) 2738/* 0x02618 */ u64 ugrp_cqrq_wrr_priority_15; 2739#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_120(val) vBIT(val, 3, 5) 2740#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_121(val) vBIT(val, 11, 5) 2741#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_122(val) vBIT(val, 19, 5) 2742#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_123(val) vBIT(val, 27, 5) 2743#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_124(val) vBIT(val, 35, 5) 2744#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_125(val) vBIT(val, 43, 5) 2745#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_126(val) vBIT(val, 51, 5) 2746#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_15_NUMBER_127(val) vBIT(val, 59, 5) 2747/* 0x02620 */ u64 ugrp_cqrq_wrr_priority_16; 2748#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_128(val) vBIT(val, 3, 5) 2749#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_129(val) vBIT(val, 11, 5) 2750#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_130(val) vBIT(val, 19, 5) 2751#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_131(val) vBIT(val, 27, 5) 2752#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_132(val) vBIT(val, 35, 5) 2753#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_133(val) vBIT(val, 43, 5) 2754#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_134(val) vBIT(val, 51, 5) 2755#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_16_NUMBER_135(val) vBIT(val, 59, 5) 2756/* 0x02628 */ u64 ugrp_cqrq_wrr_priority_17; 2757#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_136(val) vBIT(val, 3, 5) 2758#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_137(val) vBIT(val, 11, 5) 2759#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_138(val) vBIT(val, 19, 5) 2760#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_139(val) vBIT(val, 27, 5) 2761#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_140(val) vBIT(val, 35, 5) 2762#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_141(val) vBIT(val, 43, 5) 2763#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_142(val) vBIT(val, 51, 5) 2764#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_17_NUMBER_143(val) vBIT(val, 59, 5) 2765/* 0x02630 */ u64 ugrp_cqrq_wrr_priority_18; 2766#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_144(val) vBIT(val, 3, 5) 2767#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_145(val) vBIT(val, 11, 5) 2768#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_146(val) vBIT(val, 19, 5) 2769#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_147(val) vBIT(val, 27, 5) 2770#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_148(val) vBIT(val, 35, 5) 2771#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_149(val) vBIT(val, 43, 5) 2772#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_150(val) vBIT(val, 51, 5) 2773#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_18_NUMBER_151(val) vBIT(val, 59, 5) 2774/* 0x02638 */ u64 ugrp_cqrq_wrr_priority_19; 2775#define VXGE_HAL_UGRP_CQRQ_WRR_PRIORITY_19_NUMBER_152(val) vBIT(val, 3, 5) 2776/* 0x02640 */ u64 usdc_ecc_ctrl; 2777#define VXGE_HAL_USDC_ECC_CTRL_ECC_DISABLE mBIT(7) 2778/* 0x02648 */ u64 usdc_vpbp_ctrl; 2779#define VXGE_HAL_USDC_VPBP_CTRL_MSG_DIS mBIT(0) 2780#define VXGE_HAL_USDC_VPBP_CTRL_H2L_DIS mBIT(1) 2781 u8 unused02700[0x02700 - 0x02650]; 2782 2783/* 0x02700 */ u64 rtdma_int_status; 2784#define VXGE_HAL_RTDMA_INT_STATUS_PDA_ALARM_PDA_INT mBIT(1) 2785#define VXGE_HAL_RTDMA_INT_STATUS_PCC_ERROR_PCC_INT mBIT(2) 2786#define VXGE_HAL_RTDMA_INT_STATUS_LSO_ERROR_LSO_INT mBIT(4) 2787#define VXGE_HAL_RTDMA_INT_STATUS_SM_ERROR_SM_INT mBIT(5) 2788/* 0x02708 */ u64 rtdma_int_mask; 2789/* 0x02710 */ u64 pda_alarm_reg; 2790#define VXGE_HAL_PDA_ALARM_REG_PDA_HSC_FIFO_ERR mBIT(0) 2791#define VXGE_HAL_PDA_ALARM_REG_PDA_SM_ERR mBIT(1) 2792/* 0x02718 */ u64 pda_alarm_mask; 2793/* 0x02720 */ u64 pda_alarm_alarm; 2794/* 0x02728 */ u64 pcc_error_reg; 2795#define VXGE_HAL_PCC_ERROR_REG_PCC_PCC_FRM_BUF_SBE(n) mBIT(n) 2796#define VXGE_HAL_PCC_ERROR_REG_PCC_PCC_TXDO_SBE(n) mBIT(n) 2797#define VXGE_HAL_PCC_ERROR_REG_PCC_PCC_FRM_BUF_DBE(n) mBIT(n) 2798#define VXGE_HAL_PCC_ERROR_REG_PCC_PCC_TXDO_DBE(n) mBIT(n) 2799#define VXGE_HAL_PCC_ERROR_REG_PCC_PCC_FSM_ERR_ALARM(n) mBIT(n) 2800#define VXGE_HAL_PCC_ERROR_REG_PCC_PCC_SERR(n) mBIT(n) 2801/* 0x02730 */ u64 pcc_error_mask; 2802/* 0x02738 */ u64 pcc_error_alarm; 2803/* 0x02740 */ u64 lso_error_reg; 2804#define VXGE_HAL_LSO_ERROR_REG_PCC_LSO_ABORT(n) mBIT(n) 2805#define VXGE_HAL_LSO_ERROR_REG_PCC_LSO_FSM_ERR_ALARM(n) mBIT(n) 2806/* 0x02748 */ u64 lso_error_mask; 2807/* 0x02750 */ u64 lso_error_alarm; 2808/* 0x02758 */ u64 sm_error_reg; 2809#define VXGE_HAL_SM_ERROR_REG_SM_FSM_ERR_ALARM mBIT(15) 2810/* 0x02760 */ u64 sm_error_mask; 2811/* 0x02768 */ u64 sm_error_alarm; 2812/* 0x02770 */ u64 pda_control; 2813#define VXGE_HAL_PDA_CONTROL_PCC_INTERLOCK_EN mBIT(7) 2814#define VXGE_HAL_PDA_CONTROL_SPLIT_IDLE mBIT(15) 2815#define VXGE_HAL_PDA_CONTROL_PCC_MAX_DISABLE mBIT(23) 2816#define VXGE_HAL_PDA_CONTROL_H2L_DO_GATE_EN mBIT(31) 2817#define VXGE_HAL_PDA_CONTROL_TXD_INT_NUM_CTLR mBIT(39) 2818#define VXGE_HAL_PDA_CONTROL_ISSUE_8B_READ mBIT(47) 2819/* 0x02778 */ u64 pda_pda_control_0; 2820#define VXGE_HAL_PDA_PDA_CONTROL_0_PCC_MAX(val) vBIT(val, 4, 4) 2821#define VXGE_HAL_PDA_PDA_CONTROL_0_FE_MAX(val) vBIT(val, 13, 3) 2822/* 0x02780 */ u64 pda_pda_service_state_0; 2823#define VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_0(val) vBIT(val, 5, 3) 2824#define VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_1(val) vBIT(val, 13, 3) 2825#define VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_2(val) vBIT(val, 21, 3) 2826#define VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_3(val) vBIT(val, 29, 3) 2827#define VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_4(val) vBIT(val, 37, 3) 2828#define VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_5(val) vBIT(val, 45, 3) 2829#define VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_6(val) vBIT(val, 53, 3) 2830#define VXGE_HAL_PDA_PDA_SERVICE_STATE_0_NUMBER_7(val) vBIT(val, 61, 3) 2831/* 0x02788 */ u64 pda_pda_service_state_1; 2832#define VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_8(val) vBIT(val, 5, 3) 2833#define VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_9(val) vBIT(val, 13, 3) 2834#define VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_10(val) vBIT(val, 21, 3) 2835#define VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_11(val) vBIT(val, 29, 3) 2836#define VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_12(val) vBIT(val, 37, 3) 2837#define VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_13(val) vBIT(val, 45, 3) 2838#define VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_14(val) vBIT(val, 53, 3) 2839#define VXGE_HAL_PDA_PDA_SERVICE_STATE_1_NUMBER_15(val) vBIT(val, 61, 3) 2840/* 0x02790 */ u64 pda_pda_service_state_2; 2841#define VXGE_HAL_PDA_PDA_SERVICE_STATE_2_NUMBER_16(val) vBIT(val, 5, 3) 2842#define VXGE_HAL_PDA_PDA_SERVICE_STATE_2_NUMBER_17(val) vBIT(val, 13, 3) 2843#define VXGE_HAL_PDA_PDA_SERVICE_STATE_2_NUMBER_18(val) vBIT(val, 21, 3) 2844#define VXGE_HAL_PDA_PDA_SERVICE_STATE_2_NUMBER_19(val) vBIT(val, 29, 3) 2845#define VXGE_HAL_PDA_PDA_SERVICE_STATE_2_NUMBER_20(val) vBIT(val, 37, 3) 2846/* 0x02798 */ u64 pda_pda_task_priority_number; 2847#define VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_CXP(val) vBIT(val, 5, 3) 2848#define VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_H2L(val) vBIT(val, 13, 3) 2849#define VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_KDFC(val) vBIT(val, 21, 3) 2850#define VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_MP(val) vBIT(val, 29, 3) 2851#define VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_PE(val) vBIT(val, 37, 3) 2852#define VXGE_HAL_PDA_PDA_TASK_PRIORITY_NUMBER_QCC(val) vBIT(val, 45, 3) 2853/* 0x027a0 */ u64 pda_vp; 2854#define VXGE_HAL_PDA_VP_RD_XON_ENABLE mBIT(0) 2855#define VXGE_HAL_PDA_VP_WR_XON_ENABLE mBIT(1) 2856#define VXGE_HAL_PDA_VP_NO_ACTIVITY_DISABLE mBIT(2) 2857/* 0x027a8 */ u64 txd_ownership_ctrl; 2858#define VXGE_HAL_TXD_OWNERSHIP_CTRL_KEEP_OWNERSHIP mBIT(7) 2859/* 0x027b0 */ u64 pcc_cfg; 2860#define VXGE_HAL_PCC_CFG_PCC_ENABLE(n) mBIT(n) 2861#define VXGE_HAL_PCC_CFG_PCC_ECC_ENABLE_N(n) mBIT(n) 2862/* 0x027b8 */ u64 pcc_control; 2863#define VXGE_HAL_PCC_CONTROL_FE_ENABLE(val) vBIT(val, 6, 2) 2864#define VXGE_HAL_PCC_CONTROL_EARLY_ASSIGN_EN mBIT(15) 2865#define VXGE_HAL_PCC_CONTROL_UNBLOCK_DB_ERR mBIT(31) 2866/* 0x027c0 */ u64 pda_status1; 2867#define VXGE_HAL_PDA_STATUS1_PDA_WRAP_0_CTR(val) vBIT(val, 4, 4) 2868#define VXGE_HAL_PDA_STATUS1_PDA_WRAP_1_CTR(val) vBIT(val, 12, 4) 2869#define VXGE_HAL_PDA_STATUS1_PDA_WRAP_2_CTR(val) vBIT(val, 20, 4) 2870#define VXGE_HAL_PDA_STATUS1_PDA_WRAP_3_CTR(val) vBIT(val, 28, 4) 2871#define VXGE_HAL_PDA_STATUS1_PDA_WRAP_4_CTR(val) vBIT(val, 36, 4) 2872#define VXGE_HAL_PDA_STATUS1_PDA_WRAP_5_CTR(val) vBIT(val, 44, 4) 2873#define VXGE_HAL_PDA_STATUS1_PDA_WRAP_6_CTR(val) vBIT(val, 52, 4) 2874#define VXGE_HAL_PDA_STATUS1_PDA_WRAP_7_CTR(val) vBIT(val, 60, 4) 2875/* 0x027c8 */ u64 rtdma_bw_timer; 2876#define VXGE_HAL_RTDMA_BW_TIMER_TIMER_CTRL(val) vBIT(val, 12, 4) 2877 u8 unused02900[0x02900 - 0x027d0]; 2878 2879/* 0x02900 */ u64 g3cmct_int_status; 2880#define VXGE_HAL_G3CMCT_INT_STATUS_ERR_G3IF_INT mBIT(0) 2881/* 0x02908 */ u64 g3cmct_int_mask; 2882/* 0x02910 */ u64 g3cmct_err_reg; 2883#define VXGE_HAL_G3CMCT_ERR_REG_G3IF_SM_ERR mBIT(4) 2884#define VXGE_HAL_G3CMCT_ERR_REG_G3IF_GDDR3_DECC mBIT(5) 2885#define VXGE_HAL_G3CMCT_ERR_REG_G3IF_GDDR3_U_DECC mBIT(6) 2886#define VXGE_HAL_G3CMCT_ERR_REG_G3IF_CTRL_FIFO_DECC mBIT(7) 2887#define VXGE_HAL_G3CMCT_ERR_REG_G3IF_GDDR3_SECC mBIT(29) 2888#define VXGE_HAL_G3CMCT_ERR_REG_G3IF_GDDR3_U_SECC mBIT(30) 2889#define VXGE_HAL_G3CMCT_ERR_REG_G3IF_CTRL_FIFO_SECC mBIT(31) 2890/* 0x02918 */ u64 g3cmct_err_mask; 2891/* 0x02920 */ u64 g3cmct_err_alarm; 2892/* 0x02928 */ u64 g3cmct_config0; 2893#define VXGE_HAL_G3CMCT_CONFIG0_RD_CMD_LATENCY_RPATH(val) vBIT(val, 5, 3) 2894#define VXGE_HAL_G3CMCT_CONFIG0_RD_CMD_LATENCY(val) vBIT(val, 13, 3) 2895#define VXGE_HAL_G3CMCT_CONFIG0_REFRESH_PER(val) vBIT(val, 16, 16) 2896#define VXGE_HAL_G3CMCT_CONFIG0_TRC(val) vBIT(val, 35, 5) 2897#define VXGE_HAL_G3CMCT_CONFIG0_TRRD(val) vBIT(val, 44, 4) 2898#define VXGE_HAL_G3CMCT_CONFIG0_TFAW(val) vBIT(val, 50, 6) 2899#define VXGE_HAL_G3CMCT_CONFIG0_RD_FIFO_THR(val) vBIT(val, 58, 6) 2900/* 0x02930 */ u64 g3cmct_config1; 2901#define VXGE_HAL_G3CMCT_CONFIG1_BIC_THR(val) vBIT(val, 3, 5) 2902#define VXGE_HAL_G3CMCT_CONFIG1_BIC_OFF mBIT(15) 2903#define VXGE_HAL_G3CMCT_CONFIG1_IGNORE_BEM mBIT(23) 2904#define VXGE_HAL_G3CMCT_CONFIG1_RD_SAMPLING(val) vBIT(val, 29, 3) 2905#define VXGE_HAL_G3CMCT_CONFIG1_CMD_START_PHASE mBIT(39) 2906#define VXGE_HAL_G3CMCT_CONFIG1_BIC_HI_THR(val) vBIT(val, 43, 5) 2907#define VXGE_HAL_G3CMCT_CONFIG1_BIC_MODE(val) vBIT(val, 54, 2) 2908#define VXGE_HAL_G3CMCT_CONFIG1_ECC_ENABLE(val) vBIT(val, 57, 7) 2909/* 0x02938 */ u64 g3cmct_config2; 2910#define VXGE_HAL_G3CMCT_CONFIG2_DEV_USE_ENABLE(val) vBIT(val, 6, 2) 2911#define VXGE_HAL_G3CMCT_CONFIG2_DEV_USE_VALUE(val) vBIT(val, 9, 7) 2912#define VXGE_HAL_G3CMCT_CONFIG2_ARBITER_CTRL(val) vBIT(val, 22, 2) 2913#define VXGE_HAL_G3CMCT_CONFIG2_DEFINE_CAD mBIT(31) 2914#define VXGE_HAL_G3CMCT_CONFIG2_DEFINE_NOP_AD mBIT(39) 2915#define VXGE_HAL_G3CMCT_CONFIG2_LAST_CADD(val) vBIT(val, 43, 13) 2916/* 0x02940 */ u64 g3cmct_init0; 2917#define VXGE_HAL_G3CMCT_INIT0_MRS_BAD(val) vBIT(val, 5, 3) 2918#define VXGE_HAL_G3CMCT_INIT0_MRS_WL(val) vBIT(val, 13, 3) 2919#define VXGE_HAL_G3CMCT_INIT0_MRS_DLL mBIT(23) 2920#define VXGE_HAL_G3CMCT_INIT0_MRS_TM mBIT(39) 2921#define VXGE_HAL_G3CMCT_INIT0_MRS_CL(val) vBIT(val, 44, 4) 2922#define VXGE_HAL_G3CMCT_INIT0_MRS_BT mBIT(55) 2923#define VXGE_HAL_G3CMCT_INIT0_MRS_BL(val) vBIT(val, 62, 2) 2924/* 0x02948 */ u64 g3cmct_init1; 2925#define VXGE_HAL_G3CMCT_INIT1_EMRS_BAD(val) vBIT(val, 5, 3) 2926#define VXGE_HAL_G3CMCT_INIT1_EMRS_AD_TER mBIT(15) 2927#define VXGE_HAL_G3CMCT_INIT1_EMRS_ID mBIT(23) 2928#define VXGE_HAL_G3CMCT_INIT1_EMRS_RON mBIT(39) 2929#define VXGE_HAL_G3CMCT_INIT1_EMRS_AL mBIT(47) 2930#define VXGE_HAL_G3CMCT_INIT1_EMRS_TWR(val) vBIT(val, 53, 3) 2931#define VXGE_HAL_G3CMCT_INIT1_EMRS_DQ_TER(val) vBIT(val, 62, 2) 2932/* 0x02950 */ u64 g3cmct_init2; 2933#define VXGE_HAL_G3CMCT_INIT2_EMRS_DR_STR(val) vBIT(val, 6, 2) 2934#define VXGE_HAL_G3CMCT_INIT2_START_INI mBIT(15) 2935#define VXGE_HAL_G3CMCT_INIT2_POWER_UP_DELAY(val) vBIT(val, 16, 24) 2936#define VXGE_HAL_G3CMCT_INIT2_ACTIVE_CMD_DELAY(val) vBIT(val, 40, 24) 2937/* 0x02958 */ u64 g3cmct_init3; 2938#define VXGE_HAL_G3CMCT_INIT3_TRP_DELAY(val) vBIT(val, 0, 8) 2939#define VXGE_HAL_G3CMCT_INIT3_TMRD_DELAY(val) vBIT(val, 8, 8) 2940#define VXGE_HAL_G3CMCT_INIT3_TWR2PRE_DELAY(val) vBIT(val, 16, 8) 2941#define VXGE_HAL_G3CMCT_INIT3_TRD2PRE_DELAY(val) vBIT(val, 24, 8) 2942#define VXGE_HAL_G3CMCT_INIT3_TRCDR_DELAY(val) vBIT(val, 32, 8) 2943#define VXGE_HAL_G3CMCT_INIT3_TRCDW_DELAY(val) vBIT(val, 40, 8) 2944#define VXGE_HAL_G3CMCT_INIT3_TWR2RD_DELAY(val) vBIT(val, 48, 8) 2945#define VXGE_HAL_G3CMCT_INIT3_TRD2WR_DELAY(val) vBIT(val, 56, 8) 2946/* 0x02960 */ u64 g3cmct_init4; 2947#define VXGE_HAL_G3CMCT_INIT4_TRFC_DELAY(val) vBIT(val, 0, 8) 2948#define VXGE_HAL_G3CMCT_INIT4_REFRESH_BURSTS(val) vBIT(val, 12, 4) 2949#define VXGE_HAL_G3CMCT_INIT4_CKE_INIT_VAL mBIT(31) 2950#define VXGE_HAL_G3CMCT_INIT4_VENDOR_ID(val) vBIT(val, 32, 8) 2951#define VXGE_HAL_G3CMCT_INIT4_OOO_DEPTH(val) vBIT(val, 42, 6) 2952#define VXGE_HAL_G3CMCT_INIT4_ICTRL_INIT_DONE mBIT(55) 2953#define VXGE_HAL_G3CMCT_INIT4_IOCAL_WAIT_DISABLE mBIT(63) 2954/* 0x02968 */ u64 g3cmct_init5; 2955#define VXGE_HAL_G3CMCT_INIT5_TRAS_DELAY(val) vBIT(val, 3, 5) 2956#define VXGE_HAL_G3CMCT_INIT5_TVID_DELAY(val) vBIT(val, 8, 8) 2957#define VXGE_HAL_G3CMCT_INIT5_TWR_APRE2CMD(val) vBIT(val, 16, 8) 2958#define VXGE_HAL_G3CMCT_INIT5_TRD_APRE2CMD(val) vBIT(val, 24, 8) 2959#define VXGE_HAL_G3CMCT_INIT5_TWR_APRE2CMD_CON(val) vBIT(val, 32, 8) 2960#define VXGE_HAL_G3CMCT_INIT5_GDDR3_DLL_DELAY(val) vBIT(val, 40, 24) 2961/* 0x02970 */ u64 g3cmct_dll_training1; 2962#define VXGE_HAL_G3CMCT_DLL_TRAINING1_DLL_TRA_DATA00(val) vBIT(val, 0, 64) 2963/* 0x02978 */ u64 g3cmct_dll_training2; 2964#define VXGE_HAL_G3CMCT_DLL_TRAINING2_DLL_TRA_DATA01(val) vBIT(val, 0, 64) 2965/* 0x02980 */ u64 g3cmct_dll_training3; 2966#define VXGE_HAL_G3CMCT_DLL_TRAINING3_DLL_TRA_DATA10(val) vBIT(val, 0, 64) 2967/* 0x02988 */ u64 g3cmct_dll_training4; 2968#define VXGE_HAL_G3CMCT_DLL_TRAINING4_DLL_TRA_DATA11(val) vBIT(val, 0, 64) 2969/* 0x02990 */ u64 g3cmct_dll_training6; 2970#define VXGE_HAL_G3CMCT_DLL_TRAINING6_DLL_TRA_DATA20(val) vBIT(val, 0, 64) 2971/* 0x02998 */ u64 g3cmct_dll_training7; 2972#define VXGE_HAL_G3CMCT_DLL_TRAINING7_DLL_TRA_DATA21(val) vBIT(val, 0, 64) 2973/* 0x029a0 */ u64 g3cmct_dll_training8; 2974#define VXGE_HAL_G3CMCT_DLL_TRAINING8_DLL_TRA_DATA30(val) vBIT(val, 0, 64) 2975/* 0x029a8 */ u64 g3cmct_dll_training9; 2976#define VXGE_HAL_G3CMCT_DLL_TRAINING9_DLL_TRA_DATA31(val) vBIT(val, 0, 64) 2977/* 0x029b0 */ u64 g3cmct_dll_training5; 2978#define VXGE_HAL_G3CMCT_DLL_TRAINING5_DLL_TRA_RADD(val) vBIT(val, 2, 14) 2979#define VXGE_HAL_G3CMCT_DLL_TRAINING5_DLL_TRA_CADD0(val) vBIT(val, 21, 11) 2980#define VXGE_HAL_G3CMCT_DLL_TRAINING5_DLL_TRA_CADD1(val) vBIT(val, 37, 11) 2981/* 0x029b8 */ u64 g3cmct_dll_training10; 2982#define VXGE_HAL_G3CMCT_DLL_TRAINING10_DLL_TP_READS(val) vBIT(val, 4, 4) 2983#define VXGE_HAL_G3CMCT_DLL_TRAINING10_DLL_SAMPLES(val) vBIT(val, 8, 8) 2984#define VXGE_HAL_G3CMCT_DLL_TRAINING10_TRA_LOOPS(val) vBIT(val, 18, 14) 2985#define VXGE_HAL_G3CMCT_DLL_TRAINING10_TRA_PASS_CNT(val) vBIT(val, 33, 7) 2986#define VXGE_HAL_G3CMCT_DLL_TRAINING10_TRA_STEP(val) vBIT(val, 41, 7) 2987/* 0x029c0 */ u64 g3cmct_dll_training11; 2988#define VXGE_HAL_G3CMCT_DLL_TRAINING11_ICTRL_DLL_TRA_CNT(val) vBIT(val, 0, 48) 2989#define VXGE_HAL_G3CMCT_DLL_TRAINING11_ICTRL_DLL_TRA_DIS(val) vBIT(val, 54, 2) 2990/* 0x029c8 */ u64 g3cmct_init6; 2991#define VXGE_HAL_G3CMCT_INIT6_TWR_APRE2RD_DELAY(val) vBIT(val, 4, 4) 2992#define VXGE_HAL_G3CMCT_INIT6_TWR_APRE2WR_DELAY(val) vBIT(val, 12, 4) 2993#define VXGE_HAL_G3CMCT_INIT6_TWR_APRE2PRE_DELAY(val) vBIT(val, 20, 4) 2994#define VXGE_HAL_G3CMCT_INIT6_TWR_APRE2ACT_DELAY(val) vBIT(val, 28, 4) 2995#define VXGE_HAL_G3CMCT_INIT6_TRD_APRE2RD_DELAY(val) vBIT(val, 36, 4) 2996#define VXGE_HAL_G3CMCT_INIT6_TRD_APRE2WR_DELAY(val) vBIT(val, 44, 4) 2997#define VXGE_HAL_G3CMCT_INIT6_TRD_APRE2PRE_DELAY(val) vBIT(val, 52, 4) 2998#define VXGE_HAL_G3CMCT_INIT6_TRD_APRE2ACT_DELAY(val) vBIT(val, 60, 4) 2999/* 0x029d0 */ u64 g3cmct_test0; 3000#define VXGE_HAL_G3CMCT_TEST0_TEST_START_RADD(val) vBIT(val, 2, 14) 3001#define VXGE_HAL_G3CMCT_TEST0_TEST_END_RADD(val) vBIT(val, 18, 14) 3002#define VXGE_HAL_G3CMCT_TEST0_TEST_START_CADD(val) vBIT(val, 37, 11) 3003#define VXGE_HAL_G3CMCT_TEST0_TEST_END_CADD(val) vBIT(val, 53, 11) 3004/* 0x029d8 */ u64 g3cmct_test01; 3005#define VXGE_HAL_G3CMCT_TEST01_TEST_BANK(val) vBIT(val, 0, 8) 3006#define VXGE_HAL_G3CMCT_TEST01_TEST_CTRL(val) vBIT(val, 12, 4) 3007#define VXGE_HAL_G3CMCT_TEST01_TEST_MODE mBIT(23) 3008#define VXGE_HAL_G3CMCT_TEST01_TEST_GO mBIT(31) 3009#define VXGE_HAL_G3CMCT_TEST01_TEST_DONE mBIT(39) 3010#define VXGE_HAL_G3CMCT_TEST01_ECC_DEC_TEST_FAIL_CNTR(val) vBIT(val, 40, 16) 3011#define VXGE_HAL_G3CMCT_TEST01_TEST_DATA_ADDR mBIT(63) 3012/* 0x029e0 */ u64 g3cmct_test1; 3013#define VXGE_HAL_G3CMCT_TEST1_TX_TEST_DATA(val) vBIT(val, 0, 64) 3014/* 0x029e8 */ u64 g3cmct_test2; 3015#define VXGE_HAL_G3CMCT_TEST2_TX_TEST_DATA(val) vBIT(val, 0, 64) 3016/* 0x029f0 */ u64 g3cmct_test11; 3017#define VXGE_HAL_G3CMCT_TEST11_TX_TEST_DATA1(val) vBIT(val, 0, 64) 3018/* 0x029f8 */ u64 g3cmct_test21; 3019#define VXGE_HAL_G3CMCT_TEST21_TX_TEST_DATA1(val) vBIT(val, 0, 64) 3020/* 0x02a00 */ u64 g3cmct_test3; 3021#define VXGE_HAL_G3CMCT_TEST3_ECC_DEC_RX_TEST_DATA(val) vBIT(val, 0, 64) 3022/* 0x02a08 */ u64 g3cmct_test4; 3023#define VXGE_HAL_G3CMCT_TEST4_ECC_DEC_RX_TEST_DATA(val) vBIT(val, 0, 64) 3024/* 0x02a10 */ u64 g3cmct_test31; 3025#define VXGE_HAL_G3CMCT_TEST31_ECC_DEC_RX_TEST_DATA1(val) vBIT(val, 0, 64) 3026/* 0x02a18 */ u64 g3cmct_test41; 3027#define VXGE_HAL_G3CMCT_TEST41_ECC_DEC_RX_TEST_DATA1(val) vBIT(val, 0, 64) 3028/* 0x02a20 */ u64 g3cmct_test5; 3029#define VXGE_HAL_G3CMCT_TEST5_ECC_DEC_RX_FAILED_TEST_DATA(val) vBIT(val, 0, 64) 3030/* 0x02a28 */ u64 g3cmct_test6; 3031#define VXGE_HAL_G3CMCT_TEST6_ECC_DEC_RX_FAILED_TEST_DATA(val) vBIT(val, 0, 64) 3032/* 0x02a30 */ u64 g3cmct_test51; 3033#define VXGE_HAL_G3CMCT_TEST51_ECC_DEC_RX_FAILED_TEST_DATA1(val)\ 3034 vBIT(val, 0, 64) 3035/* 0x02a38 */ u64 g3cmct_test61; 3036#define VXGE_HAL_G3CMCT_TEST61_ECC_DEC_RX_FAILED_TEST_DATA1(val)\ 3037 vBIT(val, 0, 64) 3038/* 0x02a40 */ u64 g3cmct_test7; 3039#define VXGE_HAL_G3CMCT_TEST7_ECC_DEC_TEST_FAILED_RADD(val) vBIT(val, 0, 14) 3040#define VXGE_HAL_G3CMCT_TEST7_ECC_DEC_TEST_FAILED_CADD(val) vBIT(val, 19, 11) 3041#define VXGE_HAL_G3CMCT_TEST7_ECC_DEC_TEST_FAILED_BANK(val) vBIT(val, 32, 8) 3042/* 0x02a48 */ u64 g3cmct_test71; 3043#define VXGE_HAL_G3CMCT_TEST71_ECC_DEC_TEST_FAILED_RADD1(val) vBIT(val, 0, 14) 3044#define VXGE_HAL_G3CMCT_TEST71_ECC_DEC_TEST_FAILED_CADD1(val) vBIT(val, 19, 11) 3045#define VXGE_HAL_G3CMCT_TEST71_ECC_DEC_TEST_FAILED_BANK1(val) vBIT(val, 32, 8) 3046/* 0x02a50 */ u64 g3cmct_init41; 3047#define VXGE_HAL_G3CMCT_INIT41_VENDOR_ID_U(val) vBIT(val, 0, 8) 3048#define VXGE_HAL_G3CMCT_INIT41_ENABLE_CMU mBIT(15) 3049/* 0x02a58 */ u64 g3cmct_test8; 3050#define VXGE_HAL_G3CMCT_TEST8_ECC_DEC_U_RX_TEST_DATA_U(val) vBIT(val, 0, 64) 3051/* 0x02a60 */ u64 g3cmct_test9; 3052#define VXGE_HAL_G3CMCT_TEST9_ECC_DEC_U_RX_TEST_DATA_U(val) vBIT(val, 0, 64) 3053/* 0x02a68 */ u64 g3cmct_test10; 3054#define VXGE_HAL_G3CMCT_TEST10_ECC_DEC_U_RX_TEST_DATA1_U(val) vBIT(val, 0, 64) 3055/* 0x02a70 */ u64 g3cmct_test101; 3056#define VXGE_HAL_G3CMCT_TEST101_ECC_DEC_U_RX_TEST_DATA1_U(val) vBIT(val, 0, 64) 3057/* 0x02a78 */ u64 g3cmct_test12; 3058#define VXGE_HAL_G3CMCT_TEST12_ECC_DEC_U_RX_FAILED_TEST_DATA_U(val)\ 3059 vBIT(val, 0, 64) 3060/* 0x02a80 */ u64 g3cmct_test13; 3061#define VXGE_HAL_G3CMCT_TEST13_ECC_DEC_U_RX_FAILED_TEST_DATA_U(val)\ 3062 vBIT(val, 0, 64) 3063/* 0x02a88 */ u64 g3cmct_test14; 3064#define VXGE_HAL_G3CMCT_TEST14_ECC_DEC_U_RX_FAILED_TEST_DATA1_U(val)\ 3065 vBIT(val, 0, 64) 3066/* 0x02a90 */ u64 g3cmct_test15; 3067#define VXGE_HAL_G3CMCT_TEST15_ECC_DEC_U_RX_FAILED_TEST_DATA1_U(val)\ 3068 vBIT(val, 0, 64) 3069/* 0x02a98 */ u64 g3cmct_test16; 3070#define VXGE_HAL_G3CMCT_TEST16_ECC_DEC_U_TEST_FAILED_RADD_U(val)\ 3071 vBIT(val, 0, 14) 3072#define VXGE_HAL_G3CMCT_TEST16_ECC_DEC_U_TEST_FAILED_CADD_U(val)\ 3073 vBIT(val, 19, 11) 3074#define VXGE_HAL_G3CMCT_TEST16_ECC_DEC_U_TEST_FAILED_BANK_U(val)\ 3075 vBIT(val, 32, 8) 3076/* 0x02aa0 */ u64 g3cmct_test17; 3077#define VXGE_HAL_G3CMCT_TEST17_ECC_DEC_U_TEST_FAILED_RADD1_U(val)\ 3078 vBIT(val, 0, 14) 3079#define VXGE_HAL_G3CMCT_TEST17_ECC_DEC_U_TEST_FAILED_CADD1_U(val)\ 3080 vBIT(val, 19, 11) 3081#define VXGE_HAL_G3CMCT_TEST17_ECC_DEC_U_TEST_FAILED_BANK1_U(val)\ 3082 vBIT(val, 32, 8) 3083/* 0x02aa8 */ u64 g3cmct_test18; 3084#define VXGE_HAL_G3CMCT_TEST18_ECC_DEC_U_TEST_FAIL_CNTR_U(val)\ 3085 vBIT(val, 0, 16) 3086/* 0x02ab0 */ u64 g3cmct_loop_back; 3087#define VXGE_HAL_G3CMCT_LOOP_BACK_TDATA(val) vBIT(val, 0, 32) 3088#define VXGE_HAL_G3CMCT_LOOP_BACK_MODE mBIT(39) 3089#define VXGE_HAL_G3CMCT_LOOP_BACK_GO mBIT(47) 3090#define VXGE_HAL_G3CMCT_LOOP_BACK_DONE mBIT(55) 3091#define VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_IDLE_VAL(val) vBIT(val, 56, 8) 3092/* 0x02ab8 */ u64 g3cmct_loop_back1; 3093#define VXGE_HAL_G3CMCT_LOOP_BACK1_RDLL_START_VAL(val) vBIT(val, 1, 7) 3094#define VXGE_HAL_G3CMCT_LOOP_BACK1_RDLL_END_VAL(val) vBIT(val, 9, 7) 3095#define VXGE_HAL_G3CMCT_LOOP_BACK1_WDLL_IDLE_VAL(val) vBIT(val, 16, 8) 3096#define VXGE_HAL_G3CMCT_LOOP_BACK1_WDLL_START_VAL(val) vBIT(val, 25, 7) 3097#define VXGE_HAL_G3CMCT_LOOP_BACK1_WDLL_END_VAL(val) vBIT(val, 33, 7) 3098#define VXGE_HAL_G3CMCT_LOOP_BACK1_STEPS(val) vBIT(val, 45, 3) 3099#define VXGE_HAL_G3CMCT_LOOP_BACK1_RDLL_MIN_FILTER(val) vBIT(val, 49, 7) 3100#define VXGE_HAL_G3CMCT_LOOP_BACK1_RDLL_MAX_FILTER(val) vBIT(val, 57, 7) 3101/* 0x02ac0 */ u64 g3cmct_loop_back2; 3102#define VXGE_HAL_G3CMCT_LOOP_BACK2_WDLL_MIN_FILTER(val) vBIT(val, 1, 7) 3103#define VXGE_HAL_G3CMCT_LOOP_BACK2_WDLL_MAX_FILTER(val) vBIT(val, 9, 7) 3104/* 0x02ac8 */ u64 g3cmct_loop_back3; 3105#define VXGE_HAL_G3CMCT_LOOP_BACK3_LBCTRL_CMU_RDLL_RESULT(val) vBIT(val, 0, 8) 3106#define VXGE_HAL_G3CMCT_LOOP_BACK3_LBCTRL_CMU_WDLL_RESULT(val) vBIT(val, 8, 8) 3107#define VXGE_HAL_G3CMCT_LOOP_BACK3_LBCTRL_CML_RDLL_RESULT(val) vBIT(val, 16, 8) 3108#define VXGE_HAL_G3CMCT_LOOP_BACK3_LBCTRL_CML_WDLL_RESULT(val) vBIT(val, 24, 8) 3109#define VXGE_HAL_G3CMCT_LOOP_BACK3_LBCTRL_CMU_RDLL_MON_RESULT(val)\ 3110 vBIT(val, 32, 8) 3111#define VXGE_HAL_G3CMCT_LOOP_BACK3_LBCTRL_CML_RDLL_MON_RESULT(val)\ 3112 vBIT(val, 40, 8) 3113/* 0x02ad0 */ u64 g3cmct_loop_back4; 3114#define VXGE_HAL_G3CMCT_LOOP_BACK4_LBCTRL_IO_U_PASS_FAILN(val) vBIT(val, 0, 32) 3115#define VXGE_HAL_G3CMCT_LOOP_BACK4_LBCTRL_IO_L_PASS_FAILN(val) vBIT(val, 32, 32) 3116/* 0x02ad8 */ u64 g3cmct_loop_back5; 3117#define VXGE_HAL_G3CMCT_LOOP_BACK5_RDLL_START_IO_VAL(val) vBIT(val, 1, 7) 3118#define VXGE_HAL_G3CMCT_LOOP_BACK5_RDLL_END_IO_VAL(val) vBIT(val, 9, 7) 3119 u8 unused02b00[0x02b00 - 0x02ae0]; 3120 3121/* 0x02b00 */ u64 g3cmct_loop_back_rdll[4]; 3122#define VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_U_MIN_VAL(val) vBIT(val, 1, 7) 3123#define VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_U_MAX_VAL(val) vBIT(val, 9, 7) 3124#define VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_L_MIN_VAL(val) vBIT(val, 17, 7) 3125#define VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_L_MAX_VAL(val) vBIT(val, 25, 7) 3126#define VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_MON_U_MIN_VAL(val)\ 3127 vBIT(val, 33, 7) 3128#define VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_MON_U_MAX_VAL(val)\ 3129 vBIT(val, 41, 7) 3130#define VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_MON_L_MIN_VAL(val)\ 3131 vBIT(val, 49, 7) 3132#define VXGE_HAL_G3CMCT_LOOP_BACK_RDLL_LBCTRL_MON_L_MAX_VAL(val)\ 3133 vBIT(val, 57, 7) 3134/* 0x02b20 */ u64 g3cmct_loop_back_wdll[4]; 3135#define VXGE_HAL_G3CMCT_LOOP_BACK_WDLL_LBCTRL_U_MIN_VAL(val) vBIT(val, 1, 7) 3136#define VXGE_HAL_G3CMCT_LOOP_BACK_WDLL_LBCTRL_U_MAX_VAL(val) vBIT(val, 9, 7) 3137#define VXGE_HAL_G3CMCT_LOOP_BACK_WDLL_LBCTRL_L_MIN_VAL(val) vBIT(val, 17, 7) 3138#define VXGE_HAL_G3CMCT_LOOP_BACK_WDLL_LBCTRL_L_MAX_VAL(val) vBIT(val, 25, 7) 3139/* 0x02b40 */ u64 g3cmct_tran_wrd_cnt; 3140#define VXGE_HAL_G3CMCT_TRAN_WRD_CNT_CTRL_PIPE_WR(val) vBIT(val, 0, 32) 3141#define VXGE_HAL_G3CMCT_TRAN_WRD_CNT_CTRL_PIPE_RD(val) vBIT(val, 32, 32) 3142/* 0x02b48 */ u64 g3cmct_tran_ap_cnt; 3143#define VXGE_HAL_G3CMCT_TRAN_AP_CNT_CTRL_PIPE_ACT(val) vBIT(val, 0, 16) 3144#define VXGE_HAL_G3CMCT_TRAN_AP_CNT_CTRL_PIPE_PRE(val) vBIT(val, 16, 16) 3145#define VXGE_HAL_G3CMCT_TRAN_AP_CNT_UPDATE mBIT(39) 3146/* 0x02b50 */ u64 g3cmct_g3bist; 3147#define VXGE_HAL_G3CMCT_G3BIST_DISABLE_MAIN mBIT(7) 3148#define VXGE_HAL_G3CMCT_G3BIST_DISABLE_ICTRL mBIT(15) 3149#define VXGE_HAL_G3CMCT_G3BIST_BTCTRL_STATUS_MAIN(val) vBIT(val, 21, 3) 3150#define VXGE_HAL_G3CMCT_G3BIST_BTCTRL_STATUS_ICTRL(val) vBIT(val, 29, 3) 3151 u8 unused03000[0x03000 - 0x02b58]; 3152 3153/* 0x03000 */ u64 mc_int_status; 3154#define VXGE_HAL_MC_INT_STATUS_MC_ERR_MC_INT mBIT(3) 3155#define VXGE_HAL_MC_INT_STATUS_GROCRC_ALARM_ROCRC_INT mBIT(7) 3156#define VXGE_HAL_MC_INT_STATUS_FAU_GEN_ERR_FAU_GEN_INT mBIT(11) 3157#define VXGE_HAL_MC_INT_STATUS_FAU_ECC_ERR_FAU_ECC_INT mBIT(15) 3158/* 0x03008 */ u64 mc_int_mask; 3159/* 0x03010 */ u64 mc_err_reg; 3160#define VXGE_HAL_MC_ERR_REG_MC_XFMD_MEM_ECC_SG_ERR_A mBIT(3) 3161#define VXGE_HAL_MC_ERR_REG_MC_XFMD_MEM_ECC_SG_ERR_B mBIT(4) 3162#define VXGE_HAL_MC_ERR_REG_MC_G3IF_RD_FIFO_ECC_SG_ERR mBIT(5) 3163#define VXGE_HAL_MC_ERR_REG_MC_MIRI_ECC_SG_ERR_0 mBIT(6) 3164#define VXGE_HAL_MC_ERR_REG_MC_MIRI_ECC_SG_ERR_1 mBIT(7) 3165#define VXGE_HAL_MC_ERR_REG_MC_XFMD_MEM_ECC_DB_ERR_A mBIT(10) 3166#define VXGE_HAL_MC_ERR_REG_MC_XFMD_MEM_ECC_DB_ERR_B mBIT(11) 3167#define VXGE_HAL_MC_ERR_REG_MC_G3IF_RD_FIFO_ECC_DB_ERR mBIT(12) 3168#define VXGE_HAL_MC_ERR_REG_MC_MIRI_ECC_DB_ERR_0 mBIT(13) 3169#define VXGE_HAL_MC_ERR_REG_MC_MIRI_ECC_DB_ERR_1 mBIT(14) 3170#define VXGE_HAL_MC_ERR_REG_MC_SM_ERR mBIT(15) 3171/* 0x03018 */ u64 mc_err_mask; 3172/* 0x03020 */ u64 mc_err_alarm; 3173/* 0x03028 */ u64 grocrc_alarm_reg; 3174#define VXGE_HAL_GROCRC_ALARM_REG_XFMD_WR_FIFO_ERR mBIT(3) 3175#define VXGE_HAL_GROCRC_ALARM_REG_WDE2MSR_RD_FIFO_ERR mBIT(7) 3176/* 0x03030 */ u64 grocrc_alarm_mask; 3177/* 0x03038 */ u64 grocrc_alarm_alarm; 3178 u8 unused03100[0x03100 - 0x03040]; 3179 3180/* 0x03100 */ u64 rx_thresh_cfg_repl; 3181#define VXGE_HAL_RX_THRESH_CFG_REPL_PAUSE_LOW_THR(val) vBIT(val, 0, 8) 3182#define VXGE_HAL_RX_THRESH_CFG_REPL_PAUSE_HIGH_THR(val) vBIT(val, 8, 8) 3183#define VXGE_HAL_RX_THRESH_CFG_REPL_RED_THR_0(val) vBIT(val, 16, 8) 3184#define VXGE_HAL_RX_THRESH_CFG_REPL_RED_THR_1(val) vBIT(val, 24, 8) 3185#define VXGE_HAL_RX_THRESH_CFG_REPL_RED_THR_2(val) vBIT(val, 32, 8) 3186#define VXGE_HAL_RX_THRESH_CFG_REPL_RED_THR_3(val) vBIT(val, 40, 8) 3187#define VXGE_HAL_RX_THRESH_CFG_REPL_GLOBAL_WOL_EN mBIT(62) 3188#define VXGE_HAL_RX_THRESH_CFG_REPL_EXACT_VP_MATCH_REQ mBIT(63) 3189/* 0x03108 */ u64 dbg_reg1_0; 3190#define VXGE_HAL_DBG_REG1_0_INCTRL_QUEUE0_RX_NON_OFFLOAD_FRM_CNT(val)\ 3191 vBIT(val, 0, 16) 3192#define VXGE_HAL_DBG_REG1_0_INCTRL_QUEUE0_RX_OFFLOAD_FRM_CNT(val)\ 3193 vBIT(val, 16, 16) 3194#define VXGE_HAL_DBG_REG1_0_RP_QUEUE0_NON_OFFLOAD_XMFD_CNT(val)\ 3195 vBIT(val, 32, 16) 3196#define VXGE_HAL_DBG_REG1_0_RP_QUEUE0_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16) 3197/* 0x03110 */ u64 dbg_reg1_1; 3198#define VXGE_HAL_DBG_REG1_1_INCTRL_QUEUE1_RX_NON_OFFLOAD_FRM_CNT(val)\ 3199 vBIT(val, 0, 16) 3200#define VXGE_HAL_DBG_REG1_1_INCTRL_QUEUE1_RX_OFFLOAD_FRM_CNT(val)\ 3201 vBIT(val, 16, 16) 3202#define VXGE_HAL_DBG_REG1_1_RP_QUEUE1_NON_OFFLOAD_XMFD_CNT(val)\ 3203 vBIT(val, 32, 16) 3204#define VXGE_HAL_DBG_REG1_1_RP_QUEUE1_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16) 3205/* 0x03118 */ u64 dbg_reg1_2; 3206#define VXGE_HAL_DBG_REG1_2_INCTRL_QUEUE2_RX_NON_OFFLOAD_FRM_CNT(val)\ 3207 vBIT(val, 0, 16) 3208#define VXGE_HAL_DBG_REG1_2_INCTRL_QUEUE2_RX_OFFLOAD_FRM_CNT(val)\ 3209 vBIT(val, 16, 16) 3210#define VXGE_HAL_DBG_REG1_2_RP_QUEUE2_NON_OFFLOAD_XMFD_CNT(val)\ 3211 vBIT(val, 32, 16) 3212#define VXGE_HAL_DBG_REG1_2_RP_QUEUE2_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16) 3213/* 0x03120 */ u64 dbg_reg1_3; 3214#define VXGE_HAL_DBG_REG1_3_INCTRL_QUEUE3_RX_NON_OFFLOAD_FRM_CNT(val)\ 3215 vBIT(val, 0, 16) 3216#define VXGE_HAL_DBG_REG1_3_INCTRL_QUEUE3_RX_OFFLOAD_FRM_CNT(val)\ 3217 vBIT(val, 16, 16) 3218#define VXGE_HAL_DBG_REG1_3_RP_QUEUE3_NON_OFFLOAD_XMFD_CNT(val)\ 3219 vBIT(val, 32, 16) 3220#define VXGE_HAL_DBG_REG1_3_RP_QUEUE3_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16) 3221/* 0x03128 */ u64 dbg_reg1_4; 3222#define VXGE_HAL_DBG_REG1_4_INCTRL_QUEUE4_RX_NON_OFFLOAD_FRM_CNT(val)\ 3223 vBIT(val, 0, 16) 3224#define VXGE_HAL_DBG_REG1_4_INCTRL_QUEUE4_RX_OFFLOAD_FRM_CNT(val)\ 3225 vBIT(val, 16, 16) 3226#define VXGE_HAL_DBG_REG1_4_RP_QUEUE4_NON_OFFLOAD_XMFD_CNT(val)\ 3227 vBIT(val, 32, 16) 3228#define VXGE_HAL_DBG_REG1_4_RP_QUEUE4_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16) 3229/* 0x03130 */ u64 dbg_reg1_5; 3230#define VXGE_HAL_DBG_REG1_5_INCTRL_QUEUE5_RX_NON_OFFLOAD_FRM_CNT(val)\ 3231 vBIT(val, 0, 16) 3232#define VXGE_HAL_DBG_REG1_5_INCTRL_QUEUE5_RX_OFFLOAD_FRM_CNT(val)\ 3233 vBIT(val, 16, 16) 3234#define VXGE_HAL_DBG_REG1_5_RP_QUEUE5_NON_OFFLOAD_XMFD_CNT(val)\ 3235 vBIT(val, 32, 16) 3236#define VXGE_HAL_DBG_REG1_5_RP_QUEUE5_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16) 3237/* 0x03138 */ u64 dbg_reg1_6; 3238#define VXGE_HAL_DBG_REG1_6_INCTRL_QUEUE6_RX_NON_OFFLOAD_FRM_CNT(val)\ 3239 vBIT(val, 0, 16) 3240#define VXGE_HAL_DBG_REG1_6_INCTRL_QUEUE6_RX_OFFLOAD_FRM_CNT(val)\ 3241 vBIT(val, 16, 16) 3242#define VXGE_HAL_DBG_REG1_6_RP_QUEUE6_NON_OFFLOAD_XMFD_CNT(val)\ 3243 vBIT(val, 32, 16) 3244#define VXGE_HAL_DBG_REG1_6_RP_QUEUE6_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16) 3245/* 0x03140 */ u64 dbg_reg1_7; 3246#define VXGE_HAL_DBG_REG1_7_INCTRL_QUEUE7_RX_NON_OFFLOAD_FRM_CNT(val)\ 3247 vBIT(val, 0, 16) 3248#define VXGE_HAL_DBG_REG1_7_INCTRL_QUEUE7_RX_OFFLOAD_FRM_CNT(val)\ 3249 vBIT(val, 16, 16) 3250#define VXGE_HAL_DBG_REG1_7_RP_QUEUE7_NON_OFFLOAD_XMFD_CNT(val)\ 3251 vBIT(val, 32, 16) 3252#define VXGE_HAL_DBG_REG1_7_RP_QUEUE7_OFFLOAD_XFMD_CNT(val) vBIT(val, 48, 16) 3253/* 0x03148 */ u64 dbg_reg2; 3254#define VXGE_HAL_DBG_REG2_XFMDCNT_XFMD_AVAILABLE(val) vBIT(val, 6, 18) 3255#define VXGE_HAL_DBG_REG2_RP_FBMC_PTM_DATA_PHASES(val) vBIT(val, 24, 32) 3256/* 0x03150 */ u64 dbg_reg3; 3257#define VXGE_HAL_DBG_REG3_XFMD_ADV_FBMC_RQA_QUEUE_STROBES(val) vBIT(val, 0, 16) 3258#define VXGE_HAL_DBG_REG3_XFMD_ADV_FBMC_RQA_MC_STROBES(val) vBIT(val, 16, 16) 3259#define VXGE_HAL_DBG_REG3_XFMD_ADV_RQA_FBMC_QUEUE_SELECT(val) vBIT(val, 32, 16) 3260#define VXGE_HAL_DBG_REG3_XFMD_ADV_RQA_FBMC_MC_SELECT(val) vBIT(val, 48, 16) 3261/* 0x03158 */ u64 dbg_reg4; 3262#define VXGE_HAL_DBG_REG4_RP_FBMC_ONE_HEADERS(val) vBIT(val, 0, 16) 3263/* 0x03160 */ u64 dbg_reg5; 3264#define VXGE_HAL_DBG_REG5_INCTRL_TOTAL_ING_FRMS(val) vBIT(val, 0, 32) 3265#define VXGE_HAL_DBG_REG5_RP_TOTAL_EGR_FRMS(val) vBIT(val, 32, 32) 3266 u8 unused03200[0x03200 - 0x03168]; 3267 3268/* 0x03200 */ u64 rx_queue_cfg; 3269#define VXGE_HAL_RX_QUEUE_CFG_QUEUE_SIZE_ENABLE mBIT(39) 3270#define VXGE_HAL_RX_QUEUE_CFG_INGRESS_FIFO_THR(val) vBIT(val, 60, 4) 3271/* 0x03208 */ u64 rx_queue_size_q[15]; 3272#define VXGE_HAL_RX_QUEUE_SIZE_Q_SIZE(val) vBIT(val, 0, 24) 3273#define VXGE_HAL_RX_QUEUE_SIZE_Q_LAST_ADD(val) vBIT(val, 24, 24) 3274/* 0x03280 */ u64 rx_queue_size_q15; 3275#define VXGE_HAL_RX_QUEUE_SIZE_Q15_SIZE(val) vBIT(val, 0, 24) 3276#define VXGE_HAL_RX_QUEUE_SIZE_Q15_LAST_ADD(val) vBIT(val, 24, 24) 3277/* 0x03288 */ u64 rx_queue_size_q16; 3278#define VXGE_HAL_RX_QUEUE_SIZE_Q16_SIZE(val) vBIT(val, 0, 24) 3279#define VXGE_HAL_RX_QUEUE_SIZE_Q16_LAST_ADD(val) vBIT(val, 24, 24) 3280/* 0x03290 */ u64 rx_queue_size_q17; 3281#define VXGE_HAL_RX_QUEUE_SIZE_Q17_SIZE(val) vBIT(val, 0, 24) 3282#define VXGE_HAL_RX_QUEUE_SIZE_Q17_LAST_ADD(val) vBIT(val, 24, 24) 3283 u8 unused032a0[0x032a0 - 0x03298]; 3284 3285/* 0x032a0 */ u64 rx_queue_start_q0; 3286#define VXGE_HAL_RX_QUEUE_START_Q0_QUEUE_BANKS(val) vBIT(val, 6, 2) 3287#define VXGE_HAL_RX_QUEUE_START_Q0_SBANK(val) vBIT(val, 13, 3) 3288#define VXGE_HAL_RX_QUEUE_START_Q0_SROW(val) vBIT(val, 18, 14) 3289#define VXGE_HAL_RX_QUEUE_START_Q0_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) 3290#define VXGE_HAL_RX_QUEUE_START_Q0_FDP_NONOFFLOAD_OUTST_FRMS(val)\ 3291 vBIT(val, 55, 9) 3292/* 0x032a8 */ u64 rx_queue_start_q1; 3293#define VXGE_HAL_RX_QUEUE_START_Q1_QUEUE_BANKS(val) vBIT(val, 6, 2) 3294#define VXGE_HAL_RX_QUEUE_START_Q1_SBANK(val) vBIT(val, 13, 3) 3295#define VXGE_HAL_RX_QUEUE_START_Q1_SROW(val) vBIT(val, 18, 14) 3296#define VXGE_HAL_RX_QUEUE_START_Q1_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) 3297#define VXGE_HAL_RX_QUEUE_START_Q1_FDP_NONOFFLOAD_OUTST_FRMS(val)\ 3298 vBIT(val, 55, 9) 3299/* 0x032b0 */ u64 rx_queue_start_q2; 3300#define VXGE_HAL_RX_QUEUE_START_Q2_QUEUE_BANKS(val) vBIT(val, 6, 2) 3301#define VXGE_HAL_RX_QUEUE_START_Q2_SBANK(val) vBIT(val, 13, 3) 3302#define VXGE_HAL_RX_QUEUE_START_Q2_SROW(val) vBIT(val, 18, 14) 3303#define VXGE_HAL_RX_QUEUE_START_Q2_FDP_OFFLOAD_OUTST_FRMS(val)\ 3304 vBIT(val, 39, 9) 3305#define VXGE_HAL_RX_QUEUE_START_Q2_FDP_NONOFFLOAD_OUTST_FRMS(val)\ 3306 vBIT(val, 55, 9) 3307/* 0x032b8 */ u64 rx_queue_start_q3; 3308#define VXGE_HAL_RX_QUEUE_START_Q3_QUEUE_BANKS(val) vBIT(val, 6, 2) 3309#define VXGE_HAL_RX_QUEUE_START_Q3_SBANK(val) vBIT(val, 13, 3) 3310#define VXGE_HAL_RX_QUEUE_START_Q3_SROW(val) vBIT(val, 18, 14) 3311#define VXGE_HAL_RX_QUEUE_START_Q3_FDP_OFFLOAD_OUTST_FRMS(val)\ 3312 vBIT(val, 39, 9) 3313#define VXGE_HAL_RX_QUEUE_START_Q3_FDP_NONOFFLOAD_OUTST_FRMS(val)\ 3314 vBIT(val, 55, 9) 3315/* 0x032c0 */ u64 rx_queue_start_q4; 3316#define VXGE_HAL_RX_QUEUE_START_Q4_QUEUE_BANKS(val) vBIT(val, 6, 2) 3317#define VXGE_HAL_RX_QUEUE_START_Q4_SBANK(val) vBIT(val, 13, 3) 3318#define VXGE_HAL_RX_QUEUE_START_Q4_SROW(val) vBIT(val, 18, 14) 3319#define VXGE_HAL_RX_QUEUE_START_Q4_FDP_OFFLOAD_OUTST_FRMS(val)\ 3320 vBIT(val, 39, 9) 3321#define VXGE_HAL_RX_QUEUE_START_Q4_FDP_NONOFFLOAD_OUTST_FRMS(val)\ 3322 vBIT(val, 55, 9) 3323/* 0x032c8 */ u64 rx_queue_start_q5; 3324#define VXGE_HAL_RX_QUEUE_START_Q5_QUEUE_BANKS(val) vBIT(val, 6, 2) 3325#define VXGE_HAL_RX_QUEUE_START_Q5_SBANK(val) vBIT(val, 13, 3) 3326#define VXGE_HAL_RX_QUEUE_START_Q5_SROW(val) vBIT(val, 18, 14) 3327#define VXGE_HAL_RX_QUEUE_START_Q5_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) 3328#define VXGE_HAL_RX_QUEUE_START_Q5_FDP_NONOFFLOAD_OUTST_FRMS(val)\ 3329 vBIT(val, 55, 9) 3330/* 0x032d0 */ u64 rx_queue_start_q6; 3331#define VXGE_HAL_RX_QUEUE_START_Q6_QUEUE_BANKS(val) vBIT(val, 6, 2) 3332#define VXGE_HAL_RX_QUEUE_START_Q6_SBANK(val) vBIT(val, 13, 3) 3333#define VXGE_HAL_RX_QUEUE_START_Q6_SROW(val) vBIT(val, 18, 14) 3334#define VXGE_HAL_RX_QUEUE_START_Q6_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) 3335#define VXGE_HAL_RX_QUEUE_START_Q6_FDP_NONOFFLOAD_OUTST_FRMS(val)\ 3336 vBIT(val, 55, 9) 3337/* 0x032d8 */ u64 rx_queue_start_q7; 3338#define VXGE_HAL_RX_QUEUE_START_Q7_QUEUE_BANKS(val) vBIT(val, 6, 2) 3339#define VXGE_HAL_RX_QUEUE_START_Q7_SBANK(val) vBIT(val, 13, 3) 3340#define VXGE_HAL_RX_QUEUE_START_Q7_SROW(val) vBIT(val, 18, 14) 3341#define VXGE_HAL_RX_QUEUE_START_Q7_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) 3342#define VXGE_HAL_RX_QUEUE_START_Q7_FDP_NONOFFLOAD_OUTST_FRMS(val)\ 3343 vBIT(val, 55, 9) 3344/* 0x032e0 */ u64 rx_queue_start_q8; 3345#define VXGE_HAL_RX_QUEUE_START_Q8_QUEUE_BANKS(val) vBIT(val, 6, 2) 3346#define VXGE_HAL_RX_QUEUE_START_Q8_SBANK(val) vBIT(val, 13, 3) 3347#define VXGE_HAL_RX_QUEUE_START_Q8_SROW(val) vBIT(val, 18, 14) 3348#define VXGE_HAL_RX_QUEUE_START_Q8_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) 3349/* 0x032e8 */ u64 rx_queue_start_q9; 3350#define VXGE_HAL_RX_QUEUE_START_Q9_QUEUE_BANKS(val) vBIT(val, 6, 2) 3351#define VXGE_HAL_RX_QUEUE_START_Q9_SBANK(val) vBIT(val, 13, 3) 3352#define VXGE_HAL_RX_QUEUE_START_Q9_SROW(val) vBIT(val, 18, 14) 3353#define VXGE_HAL_RX_QUEUE_START_Q9_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) 3354/* 0x032f0 */ u64 rx_queue_start_q10; 3355#define VXGE_HAL_RX_QUEUE_START_Q10_QUEUE_BANKS(val) vBIT(val, 6, 2) 3356#define VXGE_HAL_RX_QUEUE_START_Q10_SBANK(val) vBIT(val, 13, 3) 3357#define VXGE_HAL_RX_QUEUE_START_Q10_SROW(val) vBIT(val, 18, 14) 3358#define VXGE_HAL_RX_QUEUE_START_Q10_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) 3359/* 0x032f8 */ u64 rx_queue_start_q11; 3360#define VXGE_HAL_RX_QUEUE_START_Q11_QUEUE_BANKS(val) vBIT(val, 6, 2) 3361#define VXGE_HAL_RX_QUEUE_START_Q11_SBANK(val) vBIT(val, 13, 3) 3362#define VXGE_HAL_RX_QUEUE_START_Q11_SROW(val) vBIT(val, 18, 14) 3363#define VXGE_HAL_RX_QUEUE_START_Q11_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) 3364/* 0x03300 */ u64 rx_queue_start_q12; 3365#define VXGE_HAL_RX_QUEUE_START_Q12_QUEUE_BANKS(val) vBIT(val, 6, 2) 3366#define VXGE_HAL_RX_QUEUE_START_Q12_SBANK(val) vBIT(val, 13, 3) 3367#define VXGE_HAL_RX_QUEUE_START_Q12_SROW(val) vBIT(val, 18, 14) 3368#define VXGE_HAL_RX_QUEUE_START_Q12_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) 3369/* 0x03308 */ u64 rx_queue_start_q13; 3370#define VXGE_HAL_RX_QUEUE_START_Q13_QUEUE_BANKS(val) vBIT(val, 6, 2) 3371#define VXGE_HAL_RX_QUEUE_START_Q13_SBANK(val) vBIT(val, 13, 3) 3372#define VXGE_HAL_RX_QUEUE_START_Q13_SROW(val) vBIT(val, 18, 14) 3373#define VXGE_HAL_RX_QUEUE_START_Q13_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) 3374/* 0x03310 */ u64 rx_queue_start_q14; 3375#define VXGE_HAL_RX_QUEUE_START_Q14_QUEUE_BANKS(val) vBIT(val, 6, 2) 3376#define VXGE_HAL_RX_QUEUE_START_Q14_SBANK(val) vBIT(val, 13, 3) 3377#define VXGE_HAL_RX_QUEUE_START_Q14_SROW(val) vBIT(val, 18, 14) 3378#define VXGE_HAL_RX_QUEUE_START_Q14_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) 3379/* 0x03318 */ u64 rx_queue_start_q15; 3380#define VXGE_HAL_RX_QUEUE_START_Q15_QUEUE_BANKS(val) vBIT(val, 6, 2) 3381#define VXGE_HAL_RX_QUEUE_START_Q15_SBANK(val) vBIT(val, 13, 3) 3382#define VXGE_HAL_RX_QUEUE_START_Q15_SROW(val) vBIT(val, 18, 14) 3383#define VXGE_HAL_RX_QUEUE_START_Q15_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) 3384/* 0x03320 */ u64 rx_queue_start_q16; 3385#define VXGE_HAL_RX_QUEUE_START_Q16_QUEUE_BANKS(val) vBIT(val, 6, 2) 3386#define VXGE_HAL_RX_QUEUE_START_Q16_SBANK(val) vBIT(val, 13, 3) 3387#define VXGE_HAL_RX_QUEUE_START_Q16_SROW(val) vBIT(val, 18, 14) 3388#define VXGE_HAL_RX_QUEUE_START_Q16_FDP_OFFLOAD_OUTST_FRMS(val) vBIT(val, 39, 9) 3389/* 0x03328 */ u64 rx_queue_start_q17; 3390#define VXGE_HAL_RX_QUEUE_START_Q17_QUEUE_BANKS(val) vBIT(val, 6, 2) 3391#define VXGE_HAL_RX_QUEUE_START_Q17_SBANK(val) vBIT(val, 13, 3) 3392#define VXGE_HAL_RX_QUEUE_START_Q17_SROW(val) vBIT(val, 18, 14) 3393/* 0x03330 */ u64 fm_definition; 3394#define VXGE_HAL_FM_DEFINITION_FM_SIZE(val) vBIT(val, 6, 2) 3395#define VXGE_HAL_FM_DEFINITION_FM_COLUMNS(val) vBIT(val, 14, 2) 3396#define VXGE_HAL_FM_DEFINITION_QUEUE_SPAV_MARGIN(val) vBIT(val, 16, 8) 3397 u8 unused03380[0x03380 - 0x03338]; 3398 3399/* 0x03380 */ u64 traffic_ctrl; 3400#define VXGE_HAL_TRAFFIC_CTRL_BLOCK_ING_PATH mBIT(7) 3401#define VXGE_HAL_TRAFFIC_CTRL_BLOCK_EGR_PATH mBIT(15) 3402#define VXGE_HAL_TRAFFIC_CTRL_OFFLOAD_MAX_FRAMES(val) vBIT(val, 24, 8) 3403#define VXGE_HAL_TRAFFIC_CTRL_NOFFLOAD_MAX_FRAMES(val) vBIT(val, 32, 8) 3404#define VXGE_HAL_TRAFFIC_CTRL_MSP_MAX_FRAMES(val) vBIT(val, 40, 8) 3405/* 0x03388 */ u64 xfmd_arb_ctrl; 3406#define VXGE_HAL_XFMD_ARB_CTRL_ISTAGE_MASK mBIT(7) 3407#define VXGE_HAL_XFMD_ARB_CTRL_EN_OFF(val) vBIT(val, 15, 17) 3408#define VXGE_HAL_XFMD_ARB_CTRL_EN_NOFF(val) vBIT(val, 39, 17) 3409/* 0x03390 */ u64 xfmd_arb_ctrl1; 3410#define VXGE_HAL_XFMD_ARB_CTRL1_PROMOTE_NOFF(val) vBIT(val, 6, 18) 3411/* 0x03398 */ u64 rd_tranc_ctrl; 3412#define VXGE_HAL_RD_TRANC_CTRL_ARB(val) vBIT(val, 4, 4) 3413/* 0x033a0 */ u64 fm_arb; 3414#define VXGE_HAL_FM_ARB_CTRL(val) vBIT(val, 0, 8) 3415#define VXGE_HAL_FM_ARB_TIMER(val) vBIT(val, 8, 8) 3416#define VXGE_HAL_FM_ARB_EN_QHIST(val) vBIT(val, 16, 8) 3417#define VXGE_HAL_FM_ARB_ACT_ARB_QHIST(val) vBIT(val, 28, 4) 3418#define VXGE_HAL_FM_ARB_QHIST_CNT(val) vBIT(val, 32, 16) 3419#define VXGE_HAL_FM_ARB_WR_DELAY_CNT(val) vBIT(val, 52, 4) 3420#define VXGE_HAL_FM_ARB_WR_WINDOW_CNT(val) vBIT(val, 56, 8) 3421/* 0x033a8 */ u64 arb; 3422#define VXGE_HAL_ARB_HP_CAL(val) vBIT(val, 0, 8) 3423#define VXGE_HAL_ARB_XFMD_LAST_MASK(val) vBIT(val, 11, 5) 3424#define VXGE_HAL_ARB_HP_XFMD_PRI(val) vBIT(val, 22, 2) 3425/* 0x033b0 */ u64 settings0; 3426#define VXGE_HAL_SETTINGS0_CTRL_FIFO_THR(val) vBIT(val, 4, 4) 3427/* 0x033b8 */ u64 fbmc_ecc_cfg; 3428#define VXGE_HAL_FBMC_ECC_CFG_ENABLE(val) vBIT(val, 3, 5) 3429 u8 unused03400[0x03400 - 0x033c0]; 3430 3431/* 0x03400 */ u64 pcipif_int_status; 3432#define VXGE_HAL_PCIPIF_INT_STATUS_DBECC_ERR_DBECC_ERR_INT mBIT(3) 3433#define VXGE_HAL_PCIPIF_INT_STATUS_SBECC_ERR_SBECC_ERR_INT mBIT(7) 3434#define VXGE_HAL_PCIPIF_INT_STATUS_GENERAL_ERR_GENERAL_ERR_INT mBIT(11) 3435#define VXGE_HAL_PCIPIF_INT_STATUS_SRPCIM_MSG_SRPCIM_MSG_INT mBIT(15) 3436#define VXGE_HAL_PCIPIF_INT_STATUS_MRPCIM_SPARE_R1_MRPCIM_SPARE_R1_INT mBIT(19) 3437/* 0x03408 */ u64 pcipif_int_mask; 3438/* 0x03410 */ u64 dbecc_err_reg; 3439#define VXGE_HAL_DBECC_ERR_REG_PCI_RETRY_BUF_DB_ERR mBIT(3) 3440#define VXGE_HAL_DBECC_ERR_REG_PCI_RETRY_SOT_DB_ERR mBIT(7) 3441#define VXGE_HAL_DBECC_ERR_REG_PCI_P_HDR_DB_ERR mBIT(11) 3442#define VXGE_HAL_DBECC_ERR_REG_PCI_P_DATA_DB_ERR mBIT(15) 3443#define VXGE_HAL_DBECC_ERR_REG_PCI_NP_HDR_DB_ERR mBIT(19) 3444#define VXGE_HAL_DBECC_ERR_REG_PCI_NP_DATA_DB_ERR mBIT(23) 3445/* 0x03418 */ u64 dbecc_err_mask; 3446/* 0x03420 */ u64 dbecc_err_alarm; 3447/* 0x03428 */ u64 sbecc_err_reg; 3448#define VXGE_HAL_SBECC_ERR_REG_PCI_RETRY_BUF_SG_ERR mBIT(3) 3449#define VXGE_HAL_SBECC_ERR_REG_PCI_RETRY_SOT_SG_ERR mBIT(7) 3450#define VXGE_HAL_SBECC_ERR_REG_PCI_P_HDR_SG_ERR mBIT(11) 3451#define VXGE_HAL_SBECC_ERR_REG_PCI_P_DATA_SG_ERR mBIT(15) 3452#define VXGE_HAL_SBECC_ERR_REG_PCI_NP_HDR_SG_ERR mBIT(19) 3453#define VXGE_HAL_SBECC_ERR_REG_PCI_NP_DATA_SG_ERR mBIT(23) 3454/* 0x03430 */ u64 sbecc_err_mask; 3455/* 0x03438 */ u64 sbecc_err_alarm; 3456/* 0x03440 */ u64 general_err_reg; 3457#define VXGE_HAL_GENERAL_ERR_REG_PCI_DROPPED_ILLEGAL_CFG mBIT(3) 3458#define VXGE_HAL_GENERAL_ERR_REG_PCI_ILLEGAL_MEM_MAP_PROG mBIT(7) 3459#define VXGE_HAL_GENERAL_ERR_REG_PCI_LINK_RST_FSM_ERR mBIT(11) 3460#define VXGE_HAL_GENERAL_ERR_REG_PCI_RX_ILLEGAL_TLP_VPLANE mBIT(15) 3461#define VXGE_HAL_GENERAL_ERR_REG_PCI_TRAINING_RESET_DET mBIT(19) 3462#define VXGE_HAL_GENERAL_ERR_REG_PCI_PCI_LINK_DOWN_DET mBIT(23) 3463#define VXGE_HAL_GENERAL_ERR_REG_PCI_RESET_ACK_DLLP mBIT(27) 3464/* 0x03448 */ u64 general_err_mask; 3465/* 0x03450 */ u64 general_err_alarm; 3466/* 0x03458 */ u64 srpcim_msg_reg; 3467#define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE0_RMSG_INT mBIT(0) 3468#define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE1_RMSG_INT mBIT(1) 3469#define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE2_RMSG_INT mBIT(2) 3470#define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE3_RMSG_INT mBIT(3) 3471#define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE4_RMSG_INT mBIT(4) 3472#define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE5_RMSG_INT mBIT(5) 3473#define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE6_RMSG_INT mBIT(6) 3474#define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE7_RMSG_INT mBIT(7) 3475#define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE8_RMSG_INT mBIT(8) 3476#define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE9_RMSG_INT mBIT(9) 3477#define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE10_RMSG_INT mBIT(10) 3478#define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE11_RMSG_INT mBIT(11) 3479#define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE12_RMSG_INT mBIT(12) 3480#define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE13_RMSG_INT mBIT(13) 3481#define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE14_RMSG_INT mBIT(14) 3482#define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE15_RMSG_INT mBIT(15) 3483#define VXGE_HAL_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE16_RMSG_INT mBIT(16) 3484/* 0x03460 */ u64 srpcim_msg_mask; 3485/* 0x03468 */ u64 srpcim_msg_alarm; 3486 u8 unused03600[0x03600 - 0x03470]; 3487 3488/* 0x03600 */ u64 gcmg1_int_status; 3489#define VXGE_HAL_GCMG1_INT_STATUS_GSSCC_ERR_GSSCC_INT mBIT(0) 3490#define VXGE_HAL_GCMG1_INT_STATUS_GSSC0_ERR0_GSSC0_0_INT mBIT(1) 3491#define VXGE_HAL_GCMG1_INT_STATUS_GSSC0_ERR1_GSSC0_1_INT mBIT(2) 3492#define VXGE_HAL_GCMG1_INT_STATUS_GSSC1_ERR0_GSSC1_0_INT mBIT(3) 3493#define VXGE_HAL_GCMG1_INT_STATUS_GSSC1_ERR1_GSSC1_1_INT mBIT(4) 3494#define VXGE_HAL_GCMG1_INT_STATUS_GSSC2_ERR0_GSSC2_0_INT mBIT(5) 3495#define VXGE_HAL_GCMG1_INT_STATUS_GSSC2_ERR1_GSSC2_1_INT mBIT(6) 3496#define VXGE_HAL_GCMG1_INT_STATUS_UQM_ERR_UQM_INT mBIT(7) 3497#define VXGE_HAL_GCMG1_INT_STATUS_GQCC_ERR_GQCC_INT mBIT(8) 3498/* 0x03608 */ u64 gcmg1_int_mask; 3499/* 0x03610 */ u64 gsscc_err_reg; 3500#define VXGE_HAL_GSSCC_ERR_REG_SSCC_SSR_SG_ERR(val) vBIT(val, 6, 2) 3501#define VXGE_HAL_GSSCC_ERR_REG_SSCC_TSR_SG_ERR(val) vBIT(val, 10, 6) 3502#define VXGE_HAL_GSSCC_ERR_REG_SSCC_OVERLAPPING_SYNC_ERR mBIT(23) 3503#define VXGE_HAL_GSSCC_ERR_REG_SSCC_SSR_DB_ERR(val) vBIT(val, 38, 2) 3504#define VXGE_HAL_GSSCC_ERR_REG_SSCC_TSR_DB_ERR(val) vBIT(val, 42, 6) 3505#define VXGE_HAL_GSSCC_ERR_REG_SSCC_CP2STE_UFLOW_ERR mBIT(55) 3506#define VXGE_HAL_GSSCC_ERR_REG_SSCC_CP2TTE_UFLOW_ERR mBIT(63) 3507/* 0x03618 */ u64 gsscc_err_mask; 3508/* 0x03620 */ u64 gsscc_err_alarm; 3509/* 0x03628 */ u64 gssc_err0_reg[3]; 3510#define VXGE_HAL_GSSC_ERR0_REG_SSCC_STATE_SG_ERR(val) vBIT(val, 0, 8) 3511#define VXGE_HAL_GSSC_ERR0_REG_SSCC_CM_RESP_SG_ERR(val) vBIT(val, 12, 4) 3512#define VXGE_HAL_GSSC_ERR0_REG_SSCC_SSR_RESP_SG_ERR(val) vBIT(val, 22, 2) 3513#define VXGE_HAL_GSSC_ERR0_REG_SSCC_TSR_RESP_SG_ERR(val) vBIT(val, 26, 6) 3514#define VXGE_HAL_GSSC_ERR0_REG_SSCC_STATE_DB_ERR(val) vBIT(val, 32, 8) 3515#define VXGE_HAL_GSSC_ERR0_REG_SSCC_CM_RESP_DB_ERR(val) vBIT(val, 44, 4) 3516#define VXGE_HAL_GSSC_ERR0_REG_SSCC_SSR_RESP_DB_ERR(val) vBIT(val, 54, 2) 3517#define VXGE_HAL_GSSC_ERR0_REG_SSCC_TSR_RESP_DB_ERR(val) vBIT(val, 58, 6) 3518/* 0x03630 */ u64 gssc_err0_mask[3]; 3519/* 0x03638 */ u64 gssc_err0_alarm[3]; 3520/* 0x03670 */ u64 gssc_err1_reg[3]; 3521#define VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_RESP_DB_ERR mBIT(0) 3522#define VXGE_HAL_GSSC_ERR1_REG_SSCC_SCREQ_ERR mBIT(1) 3523#define VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_RESP_OFLOW_ERR mBIT(2) 3524#define VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_RESP_R_WN_ERR mBIT(3) 3525#define VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_RESP_UFLOW_ERR mBIT(4) 3526#define VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_REQ_OFLOW_ERR mBIT(5) 3527#define VXGE_HAL_GSSC_ERR1_REG_SSCC_CM_REQ_UFLOW_ERR mBIT(6) 3528#define VXGE_HAL_GSSC_ERR1_REG_SSCC_FSM_OFLOW_ERR mBIT(7) 3529#define VXGE_HAL_GSSC_ERR1_REG_SSCC_FSM_UFLOW_ERR mBIT(8) 3530#define VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_REQ_OFLOW_ERR mBIT(9) 3531#define VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_REQ_UFLOW_ERR mBIT(10) 3532#define VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_RESP_OFLOW_ERR mBIT(11) 3533#define VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_RESP_R_WN_ERR mBIT(12) 3534#define VXGE_HAL_GSSC_ERR1_REG_SSCC_SSR_RESP_UFLOW_ERR mBIT(13) 3535#define VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_REQ_OFLOW_ERR mBIT(14) 3536#define VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_REQ_UFLOW_ERR mBIT(15) 3537#define VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_RESP_OFLOW_ERR mBIT(16) 3538#define VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_RESP_R_WN_ERR mBIT(17) 3539#define VXGE_HAL_GSSC_ERR1_REG_SSCC_TSR_RESP_UFLOW_ERR mBIT(18) 3540#define VXGE_HAL_GSSC_ERR1_REG_SSCC_SCRESP_ERR mBIT(19) 3541/* 0x03678 */ u64 gssc_err1_mask[3]; 3542/* 0x03680 */ u64 gssc_err1_alarm[3]; 3543/* 0x036b8 */ u64 gqcc_err_reg; 3544#define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CACHE_PB_SG_ERR(val) vBIT(val, 0, 4) 3545#define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CACHE_PB_SG_ERR(val) vBIT(val, 4, 4) 3546#define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CACHE_PB_DB_ERR(val) vBIT(val, 8, 4) 3547#define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CACHE_PB_DB_ERR(val) vBIT(val, 12, 4) 3548#define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CCMREQCMD_FIFO_ERR mBIT(16) 3549#define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CCMREQDAT_FIFO_ERR mBIT(17) 3550#define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CCM_CAM_FIFO_PUSH_ERR mBIT(18) 3551#define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CCM_CAM_EIP_FIFO_PUSH_ERR mBIT(19) 3552#define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CCM2CMA_FIFO_POP_ERR mBIT(20) 3553#define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CCM_CAM_FIFO_PUSH_ERR mBIT(24) 3554#define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CCM_CAM_EIP_FIFO_PUSH_ERR mBIT(25) 3555#define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CCM2CMA_LP_FIFO_POP_ERR mBIT(26) 3556#define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CCM2CMA_HP_FIFO_POP_ERR mBIT(27) 3557#define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_WSE2CMA_FIFO_POP_ERR mBIT(28) 3558#define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_RRP2CMA_LP_FIFO_POP_ERR mBIT(29) 3559#define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_RRP2CMA_HP_FIFO_POP_ERR mBIT(30) 3560#define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_IPWOGRRESP_FIFO_POP_ERR mBIT(31) 3561#define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_LPRPEDAT_FIFO_ERR mBIT(32) 3562#define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_LPWRRESP_FIFO_PUSH_ERR mBIT(33) 3563#define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_LPCMCREQCMD_ERR mBIT(34) 3564#define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_HPCMCREQCMD_ERR mBIT(35) 3565#define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CMCREQDAT_ERR mBIT(36) 3566#define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CMA_CMR_SM_ERR mBIT(41) 3567#define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CMA_CAR_SM_ERR mBIT(42) 3568#define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CMA_HCMR_SM_ERR mBIT(43) 3569#define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CMA_LCMR_SM_ERR mBIT(44) 3570#define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CMA_CAR_SM_ERR mBIT(45) 3571#define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CMA_CMR_INFO_ERR mBIT(55) 3572#define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CMA_WSE_WQE_RD_ERR mBIT(56) 3573#define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CMA2WGM_NEXT_WQE_PTR_ERR mBIT(57) 3574#define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CMA2RLM_RMV_DATA_ERR mBIT(58) 3575#define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CMA2DLM_RMV_DATA_ERR mBIT(59) 3576#define VXGE_HAL_GQCC_ERR_REG_QCC_SQM_CMA2ELM_RMV_DATA_ERR mBIT(60) 3577#define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CMA2CGM_CQEGRP_ROW_DATA_ERR mBIT(61) 3578#define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CMA2RLM_RMV_DATA_ERR mBIT(62) 3579#define VXGE_HAL_GQCC_ERR_REG_QCC_CQM_CMA2ELM_RMV_DATA_ERR mBIT(63) 3580/* 0x036c0 */ u64 gqcc_err_mask; 3581/* 0x036c8 */ u64 gqcc_err_alarm; 3582/* 0x036d0 */ u64 uqm_err_reg; 3583#define VXGE_HAL_UQM_ERR_REG_UQM_UQM_CMCREQ_ECC_SG_ERR mBIT(0) 3584#define VXGE_HAL_UQM_ERR_REG_UQM_UQM_CMCREQ_ECC_DB_ERR mBIT(1) 3585#define VXGE_HAL_UQM_ERR_REG_UQM_UQM_SM_ERR mBIT(8) 3586/* 0x036d8 */ u64 uqm_err_mask; 3587/* 0x036e0 */ u64 uqm_err_alarm; 3588/* 0x036e8 */ u64 sscc_config; 3589#define VXGE_HAL_SSCC_CONFIG_HIT_SCHASH_INDEX_MSB(val) vBIT(val, 3, 5) 3590#define VXGE_HAL_SSCC_CONFIG_HIT_SCHASH_INDEX_LSB(val) vBIT(val, 11, 5) 3591#define VXGE_HAL_SSCC_CONFIG_TIMEOUT_VALUE(val) vBIT(val, 16, 16) 3592#define VXGE_HAL_SSCC_CONFIG_ALLOW_NOTFOUND_CACHING mBIT(39) 3593#define VXGE_HAL_SSCC_CONFIG_ALRO_SCHASH_INDEX_MSB(val) vBIT(val, 43, 5) 3594#define VXGE_HAL_SSCC_CONFIG_ALRO_SCHASH_INDEX_LSB(val) vBIT(val, 51, 5) 3595#define VXGE_HAL_SSCC_CONFIG_NULL_LOOKUP mBIT(63) 3596/* 0x036f0 */ u64 sscc_mask_0; 3597#define VXGE_HAL_SSCC_MASK_0_IPV6_SA_TOP(val) vBIT(val, 0, 64) 3598/* 0x036f8 */ u64 sscc_mask_1; 3599#define VXGE_HAL_SSCC_MASK_1_IPV6_SA_BOTTOM(val) vBIT(val, 0, 64) 3600/* 0x03700 */ u64 sscc_mask_2; 3601#define VXGE_HAL_SSCC_MASK_2_IPV6_DA_TOP(val) vBIT(val, 0, 64) 3602/* 0x03708 */ u64 sscc_mask_3; 3603#define VXGE_HAL_SSCC_MASK_3_IPV6_DA_BOTTOM(val) vBIT(val, 0, 64) 3604/* 0x03710 */ u64 sscc_mask_4; 3605#define VXGE_HAL_SSCC_MASK_4_IPV4_SA(val) vBIT(val, 0, 32) 3606#define VXGE_HAL_SSCC_MASK_4_IPV4_DA(val) vBIT(val, 32, 32) 3607/* 0x03718 */ u64 sscc_mask_5; 3608#define VXGE_HAL_SSCC_MASK_5_TCP_SP(val) vBIT(val, 0, 16) 3609#define VXGE_HAL_SSCC_MASK_5_TCP_DP(val) vBIT(val, 16, 16) 3610#define VXGE_HAL_SSCC_MASK_5_VLANID(val) vBIT(val, 52, 12) 3611/* 0x03720 */ u64 gcmg1_ecc; 3612#define VXGE_HAL_GCMG1_ECC_ENABLE_SSCC_N mBIT(7) 3613#define VXGE_HAL_GCMG1_ECC_ENABLE_UQM_N mBIT(15) 3614#define VXGE_HAL_GCMG1_ECC_ENABLE_QCC_N mBIT(23) 3615 u8 unused03a00[0x03a00 - 0x03728]; 3616 3617/* 0x03a00 */ u64 pcmg1_int_status; 3618#define VXGE_HAL_PCMG1_INT_STATUS_PSSCC_ERR_PSSCC_INT mBIT(0) 3619#define VXGE_HAL_PCMG1_INT_STATUS_PQCC_ERR_PQCC_INT mBIT(1) 3620#define VXGE_HAL_PCMG1_INT_STATUS_PQCC_CQM_ERR_PQCC_CQM_INT mBIT(2) 3621#define VXGE_HAL_PCMG1_INT_STATUS_PQCC_SQM_ERR_PQCC_SQM_INT mBIT(3) 3622/* 0x03a08 */ u64 pcmg1_int_mask; 3623/* 0x03a10 */ u64 psscc_err_reg; 3624#define VXGE_HAL_PSSCC_ERR_REG_SSCC_CP2STE_OFLOW_ERR mBIT(0) 3625#define VXGE_HAL_PSSCC_ERR_REG_SSCC_CP2TTE_OFLOW_ERR mBIT(1) 3626/* 0x03a18 */ u64 psscc_err_mask; 3627/* 0x03a20 */ u64 psscc_err_alarm; 3628/* 0x03a28 */ u64 pqcc_err_reg; 3629#define VXGE_HAL_PQCC_ERR_REG_QCC_SQM_MAX_WQE_GRP_INFO_ERR mBIT(0) 3630#define VXGE_HAL_PQCC_ERR_REG_QCC_SQM_WQE_FREE_LIST_EMPTY_INFO_ERR mBIT(1) 3631#define VXGE_HAL_PQCC_ERR_REG_QCC_SQM_FLM_WQE_ID_FIFO_ERR mBIT(2) 3632#define VXGE_HAL_PQCC_ERR_REG_QCC_SQM_CACHE_FULL_INFO_ERR mBIT(3) 3633#define VXGE_HAL_PQCC_ERR_REG_QCC_QCC_PDA_ARB_SM_ERR mBIT(32) 3634#define VXGE_HAL_PQCC_ERR_REG_QCC_QCC_CP_ARB_SM_ERR mBIT(33) 3635#define VXGE_HAL_PQCC_ERR_REG_QCC_QCC_CXP2QCC_FIFO_ERR mBIT(63) 3636/* 0x03a30 */ u64 pqcc_err_mask; 3637/* 0x03a38 */ u64 pqcc_err_alarm; 3638/* 0x03a40 */ u64 pqcc_cqm_err_reg; 3639#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CACHE_PA_SG_ERR(val) vBIT(val, 0, 4) 3640#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_DMACQERSP_SG_ERR mBIT(4) 3641#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CACHE_PA_DB_ERR(val) vBIT(val, 8, 4) 3642#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_DMACQERSP_DB_ER mBIT(12) 3643#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CCM_RMW_FIFO_ERR mBIT(16) 3644#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CAE_RLM_FIFO_ERR mBIT(17) 3645#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CCM_CAM_FIFO_POP_ERR mBIT(18) 3646#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CCM_CAM_EIP_FIFO_POP_ERR mBIT(19) 3647#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CCM2CMA_FIFO_PUSH_ERR mBIT(20) 3648#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_HPRPEREQ_FIFO_ERR mBIT(21) 3649#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_LPRPEREQ_FIFO_ERR mBIT(22) 3650#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_LPRPERSP_FIFO_ERR mBIT(23) 3651#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CMP_USDC_DBELL_FIFO_ERR mBIT(24) 3652#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CMP_CXP_MSG_IN_FIFO_ERR mBIT(25) 3653#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CMP_CXP_MSG_OUT_FIFO_ERR mBIT(26) 3654#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CAE_ELM_FIFO_ERR mBIT(27) 3655#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CGM_CCM_REQ_FIFO_ERR mBIT(28) 3656#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_EXCESSIVE_RD_RESP_ERR mBIT(29) 3657#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CDR_SERR mBIT(32) 3658#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_WGM_FLM_SM_ERR mBIT(33) 3659#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_WGM_CRP_SM_ERR mBIT(34) 3660#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_WGM_ARB_SM_ERR mBIT(35) 3661#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CMP_RCL_SM_ERR mBIT(36) 3662#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CMP_CIN_SM_ERR mBIT(37) 3663#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CSE_SM_ERR mBIT(38) 3664#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CCM_SM_ERR mBIT(39) 3665#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CAE_RLM_SM_ERR mBIT(40) 3666#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CAE_RLM_ADD_SM_ERR mBIT(41) 3667#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CAE_ELM_SM_ERR mBIT(42) 3668#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CAE_ELM_ADD_SM_ERR mBIT(43) 3669#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CACHE_FULL_INFO_ERR mBIT(58) 3670#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_MAX_CQE_GRP_INFO_ERR mBIT(59) 3671#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_CDR_SM_INFO_ERR mBIT(60) 3672#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_BAD_CIN_INFO_ERR mBIT(61) 3673#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_NO_CQE_GRP_INFO_ERR mBIT(62) 3674#define VXGE_HAL_PQCC_CQM_ERR_REG_QCC_CQM_BAD_VPIN_INFO_ERR mBIT(63) 3675/* 0x03a48 */ u64 pqcc_cqm_err_mask; 3676/* 0x03a50 */ u64 pqcc_cqm_err_alarm; 3677/* 0x03a58 */ u64 pqcc_sqm_err_reg; 3678#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CACHE_PA_SG_ERR(val) vBIT(val, 0, 4) 3679#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPRPEDAT_SG_ERR(val) vBIT(val, 4, 4) 3680#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_DMAWQERSP_SG_ERR mBIT(8) 3681#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_RPEREQDAT_SG_ERR mBIT(9) 3682#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_BAD_VPIN_INFO_ERR mBIT(10) 3683#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WDR_SM_INFO_ERR mBIT(11) 3684#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_BAD_SIN_INFO_ERR mBIT(12) 3685#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_EXCESSIVE_RD_RESP_ERR mBIT(13) 3686#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_DMAWQERSP_DB_ERR mBIT(14) 3687#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_RPEREQDAT_DB_ERR mBIT(15) 3688#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CACHE_PA_DB_ERR(val) vBIT(val, 16, 4) 3689#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPRPEDAT_DB_ERR(val) vBIT(val, 20, 4) 3690#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WAE_RLM_FIFO_ERR mBIT(24) 3691#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CCM_CAM_FIFO_POP_ERR mBIT(25) 3692#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CCM_CAM_EIP_FIFO_POP_ERR mBIT(26) 3693#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CCM2CMA_LP_FIFO_PUSH_ERR mBIT(27) 3694#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CCM2CMA_HP_FIFO_PUSH_ERR mBIT(28) 3695#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WSE2CMA_FIFO_PUSH_ERR mBIT(29) 3696#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_RRP2CMA_LP_FIFO_PUSH_ERR mBIT(30) 3697#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_RRP2CMA_HP_FIFO_PUSH_ERR mBIT(31) 3698#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_HPRPEREQ_FIFO_ERR mBIT(32) 3699#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_IPWOGRREQSB_FIFO_ERR mBIT(33) 3700#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_IPWOGRRESP_FIFO_POP_ERR mBIT(34) 3701#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPRPEDAT_FIFO_ERR mBIT(35) 3702#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPRPEREQ_FIFO_ERR mBIT(36) 3703#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPRPERESP_FIFO_ERR mBIT(37) 3704#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPRPERESPSB_FIFO_ERR mBIT(38) 3705#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPWRREQSB_FIFO_ERR mBIT(39) 3706#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_LPWRRESP_FIFO_POP_ERR mBIT(40) 3707#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_SWRRESP_FIFO_ERR mBIT(41) 3708#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WGM_RPE_REQ_FIFO_ERR mBIT(42) 3709#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WGM_RPE_LASTOD_FIFO_ERR mBIT(43) 3710#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CMP_USDC_DBELL_FIFO_ERR mBIT(44) 3711#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CMP_CXP_MSG_IN_FIFO_ERR mBIT(45) 3712#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CMP_CXP_MSG_OUT_FIFO_ERR mBIT(46) 3713#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CCM_RMW_FIFO_ERR mBIT(47) 3714#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WAE_ELM_FIFO_ERR mBIT(48) 3715#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WAE_DLM_FIFO_ERR mBIT(49) 3716#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_RRP_RESPDATA_ARB_SM_ERR mBIT(50) 3717#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WDR_SERR mBIT(51) 3718#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CMA_RLP_SM_ERR mBIT(52) 3719#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WGM_FLM_SM_ERR mBIT(53) 3720#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CMP_RCL_SM_ERR mBIT(54) 3721#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CMP_CIN_SM_ERR mBIT(55) 3722#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WSE_SM_ERR mBIT(56) 3723#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_CCM_SM_ERR mBIT(57) 3724#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WAE_RLM_SM_ERR mBIT(58) 3725#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WAE_RLM_ADD_SM_ERR mBIT(59) 3726#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WAE_ELM_SM_ERR mBIT(60) 3727#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WAE_ELM_ADD_SM_ERR mBIT(61) 3728#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WAE_DLM_SM_ERR mBIT(62) 3729#define VXGE_HAL_PQCC_SQM_ERR_REG_QCC_SQM_WAE_DLM_ADD_SM_ERR mBIT(63) 3730/* 0x03a60 */ u64 pqcc_sqm_err_mask; 3731/* 0x03a68 */ u64 pqcc_sqm_err_alarm; 3732/* 0x03a70 */ u64 qcc_srq_cqrq; 3733#define VXGE_HAL_QCC_SRQ_CQRQ_POLL_TIMER(val) vBIT(val, 0, 32) 3734#define VXGE_HAL_QCC_SRQ_CQRQ_MAX_EOL_POLLS(val) vBIT(val, 32, 8) 3735#define VXGE_HAL_QCC_SRQ_CQRQ_CONSERVATIVE_SM_CRD_RTN mBIT(47) 3736/* 0x03a78 */ u64 qcc_err_policy; 3737#define VXGE_HAL_QCC_ERR_POLICY_CQM_CQE(val) vBIT(val, 4, 4) 3738#define VXGE_HAL_QCC_ERR_POLICY_SQM_WQE(val) vBIT(val, 12, 4) 3739#define VXGE_HAL_QCC_ERR_POLICY_SQM_SRQIR(val) vBIT(val, 22, 2) 3740/* 0x03a80 */ u64 qcc_bp_ctrl; 3741#define VXGE_HAL_QCC_BP_CTRL_RD_XON mBIT(7) 3742/* 0x03a88 */ u64 pcmg1_ecc; 3743#define VXGE_HAL_PCMG1_ECC_ENABLE_QCC_N mBIT(23) 3744/* 0x03a90 */ u64 qcc_cqm_cqrq_id; 3745#define VXGE_HAL_QCC_CQM_CQRQ_ID_CQM_BAD_VPIN_CQRQ_ID(val) vBIT(val, 0, 16) 3746#define VXGE_HAL_QCC_CQM_CQRQ_ID_CQM_BAD_CIN_CQRQ_ID(val) vBIT(val, 16, 16) 3747#define VXGE_HAL_QCC_CQM_CQRQ_ID_CQM_MAX_CQE_GRP_CQRQ_ID(val) vBIT(val, 32, 16) 3748#define VXGE_HAL_QCC_CQM_CQRQ_ID_CQM_CQM_CDR_CQRQ_ID(val) vBIT(val, 48, 16) 3749/* 0x03a98 */ u64 qcc_sqm_srq_id; 3750#define VXGE_HAL_QCC_SQM_SRQ_ID_SQM_BAD_VPIN_SRQ_ID(val) vBIT(val, 0, 16) 3751#define VXGE_HAL_QCC_SQM_SRQ_ID_SQM_BAD_SIN_SRQ_ID(val) vBIT(val, 16, 16) 3752#define VXGE_HAL_QCC_SQM_SRQ_ID_SQM_MAX_WQE_GRP_SRQ_ID(val) vBIT(val, 32, 16) 3753#define VXGE_HAL_QCC_SQM_SRQ_ID_SQM_SQM_WDR_SRQ_ID(val) vBIT(val, 48, 16) 3754/* 0x03aa0 */ u64 qcc_cqm_flm_id; 3755#define VXGE_HAL_QCC_CQM_FLM_ID_CQM_CQM_CCM_STATE_SERR(val) vBIT(val, 1, 7) 3756#define VXGE_HAL_QCC_CQM_FLM_ID_CQM_CQM_FLM_HEAD_CQEGRP_ID(val) vBIT(val, 8, 24) 3757#define VXGE_HAL_QCC_CQM_FLM_ID_CQM_CQM_FLM_TAIL_CQEGRP_ID(val)\ 3758 vBIT(val, 40, 24) 3759/* 0x03aa8 */ u64 qcc_sqm_flm_id; 3760#define VXGE_HAL_QCC_SQM_FLM_ID_SQM_SQM_NO_WQE_OD_GRP_AVAIL mBIT(0) 3761#define VXGE_HAL_QCC_SQM_FLM_ID_SQM_SQM_CCM_STATE_SERR(val) vBIT(val, 1, 7) 3762#define VXGE_HAL_QCC_SQM_FLM_ID_SQM_SQM_FLM_HEAD_WQEGRP_ID(val) vBIT(val, 8, 24) 3763#define VXGE_HAL_QCC_SQM_FLM_ID_SQM_SQM_FLM_TAIL_WQEGRP_ID(val)\ 3764 vBIT(val, 40, 24) 3765 u8 unused04000[0x04000 - 0x03ab0]; 3766 3767/* 0x04000 */ u64 one_int_status; 3768#define VXGE_HAL_ONE_INT_STATUS_RXPE_ERR_RXPE_INT mBIT(7) 3769#define VXGE_HAL_ONE_INT_STATUS_TXPE_BCC_MEM_SG_ECC_ERR_TXPE_BCC_MEM_SG_ECC_INT\ 3770 mBIT(13) 3771#define VXGE_HAL_ONE_INT_STATUS_TXPE_BCC_MEM_DB_ECC_ERR_TXPE_BCC_MEM_DB_ECC_INT\ 3772 mBIT(14) 3773#define VXGE_HAL_ONE_INT_STATUS_TXPE_ERR_TXPE_INT mBIT(15) 3774#define VXGE_HAL_ONE_INT_STATUS_DLM_ERR_DLM_INT mBIT(23) 3775#define VXGE_HAL_ONE_INT_STATUS_PE_ERR_PE_INT mBIT(31) 3776#define VXGE_HAL_ONE_INT_STATUS_RPE_ERR_RPE_INT mBIT(39) 3777#define VXGE_HAL_ONE_INT_STATUS_RPE_FSM_ERR_RPE_FSM_INT mBIT(47) 3778#define VXGE_HAL_ONE_INT_STATUS_OES_ERR_OES_INT mBIT(55) 3779/* 0x04008 */ u64 one_int_mask; 3780/* 0x04010 */ u64 rpe_err_reg; 3781#define VXGE_HAL_RPE_ERR_REG_RPE_RCM_PA_DB_ERR(val) vBIT(val, 0, 4) 3782#define VXGE_HAL_RPE_ERR_REG_RPE_RCM_PB_DB_ERR(val) vBIT(val, 4, 4) 3783#define VXGE_HAL_RPE_ERR_REG_RPE_PDM_FRAME_DB_ERR mBIT(8) 3784#define VXGE_HAL_RPE_ERR_REG_RPE_PDM_RCMD_DB_ERR mBIT(9) 3785#define VXGE_HAL_RPE_ERR_REG_RPE_RCQ_DB_ERR mBIT(10) 3786#define VXGE_HAL_RPE_ERR_REG_RPE_RCO_PBLE_DB_ERR mBIT(11) 3787#define VXGE_HAL_RPE_ERR_REG_RPE_RCM_PA_SG_ERR(val) vBIT(val, 16, 4) 3788#define VXGE_HAL_RPE_ERR_REG_RPE_RCM_PB_SG_ERR(val) vBIT(val, 20, 4) 3789#define VXGE_HAL_RPE_ERR_REG_RPE_PDM_FRAME_SG_ERR mBIT(24) 3790#define VXGE_HAL_RPE_ERR_REG_RPE_PDM_RCMD_SG_ERR mBIT(25) 3791#define VXGE_HAL_RPE_ERR_REG_RPE_RCQ_SG_ERR mBIT(26) 3792#define VXGE_HAL_RPE_ERR_REG_RPE_RCO_PBLE_SG_ERR mBIT(27) 3793#define VXGE_HAL_RPE_ERR_REG_RPE_CMI_CTXTRDRQ_FIFO_ERR mBIT(32) 3794#define VXGE_HAL_RPE_ERR_REG_RPE_CMI_CTXTWRRQ_FIFO_ERR mBIT(33) 3795#define VXGE_HAL_RPE_ERR_REG_RPE_CMI_CQRQLDRQ_FIFO_ERR mBIT(34) 3796#define VXGE_HAL_RPE_ERR_REG_RPE_CMI_SRQLDRQ_FIFO_ERR mBIT(35) 3797#define VXGE_HAL_RPE_ERR_REG_RPE_CMI_WQERDRQ_FIFO_ERR mBIT(36) 3798#define VXGE_HAL_RPE_ERR_REG_RPE_CMI_WQEWRRQ_FIFO_ERR mBIT(37) 3799#define VXGE_HAL_RPE_ERR_REG_RPE_CMI_CQEAVAILRQ_FIFO_ERR mBIT(38) 3800#define VXGE_HAL_RPE_ERR_REG_RPE_CMI_WQECOMPL_FIFO_ERR mBIT(39) 3801#define VXGE_HAL_RPE_ERR_REG_RPE_CMI_CQEADDRRQ_FIFO_ERR mBIT(40) 3802#define VXGE_HAL_RPE_ERR_REG_RPE_RCC_CTXTLDNT_FIFO_ERR mBIT(41) 3803#define VXGE_HAL_RPE_ERR_REG_RPE_RCC_RCCRESP_FIFO_ERR mBIT(42) 3804#define VXGE_HAL_RPE_ERR_REG_RPE_QEM_OESPREINIT_FIFO_ERR mBIT(43) 3805#define VXGE_HAL_RPE_ERR_REG_RPE_QEM_EVENT_FIFO_ERR mBIT(44) 3806#define VXGE_HAL_RPE_ERR_REG_RPE_QEM_WQELDNT_FIFO_ERR mBIT(45) 3807#define VXGE_HAL_RPE_ERR_REG_RPE_QEM_QEMRESP_FIFO_ERR mBIT(46) 3808#define VXGE_HAL_RPE_ERR_REG_RPE_QEM_PDM_CMD_FIFO_ERR mBIT(47) 3809#define VXGE_HAL_RPE_ERR_REG_RPE_PDM_CMDRESP_FIFO_ERR mBIT(48) 3810#define VXGE_HAL_RPE_ERR_REG_RPE_PDM_FRAME_FIFO_ERR mBIT(49) 3811#define VXGE_HAL_RPE_ERR_REG_RPE_PDM_EPE_SPQ_FIFO_ERR mBIT(50) 3812#define VXGE_HAL_RPE_ERR_REG_RPE_PDM_EPE_STCRESP_FIFO_ERR mBIT(51) 3813#define VXGE_HAL_RPE_ERR_REG_RPE_PDM_RIM_RIMIPB_FIFO_ERR mBIT(52) 3814#define VXGE_HAL_RPE_ERR_REG_RPE_RCI_MCQLEN_FIFO_ERR mBIT(53) 3815#define VXGE_HAL_RPE_ERR_REG_RPE_RCI_PCQLEN_FIFO_ERR mBIT(54) 3816#define VXGE_HAL_RPE_ERR_REG_RPE_RCI_RDLIM_FIFO_ERR mBIT(55) 3817#define VXGE_HAL_RPE_ERR_REG_RPE_MSG_RCMD_FIFO_ERR mBIT(56) 3818#define VXGE_HAL_RPE_ERR_REG_RPE_DLM_RCMD_FIFO_ERR mBIT(57) 3819#define VXGE_HAL_RPE_ERR_REG_RPE_PDM_RCMD_FIFO_ERR mBIT(58) 3820#define VXGE_HAL_RPE_ERR_REG_RPE_RCQ_FIFO_ERR mBIT(59) 3821#define VXGE_HAL_RPE_ERR_REG_RPE_RCO_CQE_FIFO_ERR mBIT(60) 3822#define VXGE_HAL_RPE_ERR_REG_RPE_RCO_PBLE_FIFO_ERR mBIT(61) 3823/* 0x04018 */ u64 rpe_err_mask; 3824/* 0x04020 */ u64 rpe_err_alarm; 3825/* 0x04028 */ u64 pe_err_reg; 3826#define VXGE_HAL_PE_ERR_REG_PE_PE_CDP_CTXT_PA_SG_ERR mBIT(0) 3827#define VXGE_HAL_PE_ERR_REG_PE_PE_CDP_CTXT_PB_SG_ERR mBIT(1) 3828#define VXGE_HAL_PE_ERR_REG_PE_PE_TIMER_SG_ERR mBIT(2) 3829#define VXGE_HAL_PE_ERR_REG_PE_CDP_CTXTRRQ_RDFIFO_STATE_SM_ERR mBIT(8) 3830#define VXGE_HAL_PE_ERR_REG_PE_CDP_CTXTRRQ_STATE_SM_ERR mBIT(9) 3831#define VXGE_HAL_PE_ERR_REG_PE_CDP_CTXTWRQ_ADDR_STATE_SM_ERR mBIT(10) 3832#define VXGE_HAL_PE_ERR_REG_PE_CDP_CTXTWRQ_DATA_STATE_SM_ERR mBIT(11) 3833#define VXGE_HAL_PE_ERR_REG_PE_CDP_DLM_CTXT_STATE_SM_ERR mBIT(12) 3834#define VXGE_HAL_PE_ERR_REG_PE_CDP_RDMEM_ADDR_STATE_SM_ERR mBIT(13) 3835#define VXGE_HAL_PE_ERR_REG_PE_CDP_RDMEM_DATA_STATE_SM_ERR mBIT(14) 3836#define VXGE_HAL_PE_ERR_REG_PE_CDP_RDRESP_STATE_SM_ERR mBIT(15) 3837#define VXGE_HAL_PE_ERR_REG_PE_CDP_RXPE_RDCTXT_DATA_STATE_SM_ERR mBIT(16) 3838#define VXGE_HAL_PE_ERR_REG_PE_CDP_RXPEIF_STATE_SM_ERR mBIT(17) 3839#define VXGE_HAL_PE_ERR_REG_PE_CDP_TCM_CTXT_STATE_SM_ERR mBIT(18) 3840#define VXGE_HAL_PE_ERR_REG_PE_SCC_CTXT_CNTRL_SM_ERR mBIT(19) 3841#define VXGE_HAL_PE_ERR_REG_PE_SCC_RECALL_SM_ERR mBIT(20) 3842#define VXGE_HAL_PE_ERR_REG_PE_SCC_NCE_FETCH_STATE_SM_ERR mBIT(21) 3843#define VXGE_HAL_PE_ERR_REG_PE_NCC_NCE_CNTRL_SM_ERR mBIT(22) 3844#define VXGE_HAL_PE_ERR_REG_PE_NCC_NDP_MEMCNTRL_STATE_SM_ERR mBIT(23) 3845#define VXGE_HAL_PE_ERR_REG_PE_NCC_NDP_NRRQ_RDFIFO_STATE_SM_ERR mBIT(24) 3846#define VXGE_HAL_PE_ERR_REG_PE_NCC_NDP_NRRQ_STATE_SM_ERR mBIT(25) 3847#define VXGE_HAL_PE_ERR_REG_PE_NCC_NDP_NWRQ_RDFIFO_STATE_SM_ERR mBIT(26) 3848#define VXGE_HAL_PE_ERR_REG_PE_NCC_NDP_RDMEM_DATA_STATE_SM_ERR mBIT(27) 3849#define VXGE_HAL_PE_ERR_REG_PE_CMGIF_HDREQ_ARB_STATE_SM_ERR mBIT(28) 3850#define VXGE_HAL_PE_ERR_REG_PE_CMGIF_HNREQ_ARB_STATE_SM_ERR mBIT(29) 3851#define VXGE_HAL_PE_ERR_REG_PE_CMGIF_LDREQ_ARB_STATE_SM_ERR mBIT(30) 3852#define VXGE_HAL_PE_ERR_REG_PE_CMGIF_LNREQ_ARB_STATE_SM_ERR mBIT(31) 3853#define VXGE_HAL_PE_ERR_REG_PE_CDP_CTXTRRQ_FIFO_ERR mBIT(32) 3854#define VXGE_HAL_PE_ERR_REG_PE_CDP_CTXT_FIFO_ERR mBIT(33) 3855#define VXGE_HAL_PE_ERR_REG_PE_CDP_RXPE_CTXT_WR_PHASE_ERR mBIT(34) 3856#define VXGE_HAL_PE_ERR_REG_PE_CDP_RXPE_CTXT_RD_PHASE_ERR mBIT(35) 3857#define VXGE_HAL_PE_ERR_REG_PE_CDP_CTXTRRQ_RD_RESP_PHASE_ERR mBIT(36) 3858#define VXGE_HAL_PE_ERR_REG_PE_NDP_NRRQ_FIFO_ERR mBIT(37) 3859#define VXGE_HAL_PE_ERR_REG_PE_NDP_NWRQ_FIFO_ERR mBIT(38) 3860#define VXGE_HAL_PE_ERR_REG_PE_NCC_NDP_WRMEM_PHASE_ERR mBIT(39) 3861#define VXGE_HAL_PE_ERR_REG_PE_NCC_PE_RESP_CMD_PHASE_ERR mBIT(40) 3862#define VXGE_HAL_PE_ERR_REG_PE_PE_TIMER_SM_ERR mBIT(48) 3863#define VXGE_HAL_PE_ERR_REG_PE_PET_MEM_ARB_ERR mBIT(49) 3864#define VXGE_HAL_PE_ERR_REG_PE_PET_UPDATE_FSM_ERR mBIT(50) 3865#define VXGE_HAL_PE_ERR_REG_PE_PE_CDP_CTXT_PA_DB_ERR mBIT(61) 3866#define VXGE_HAL_PE_ERR_REG_PE_PE_CDP_CTXT_PB_DB_ERR mBIT(62) 3867#define VXGE_HAL_PE_ERR_REG_PE_PE_TIMER_DB_ERR mBIT(63) 3868/* 0x04030 */ u64 pe_err_mask; 3869/* 0x04038 */ u64 pe_err_alarm; 3870/* 0x04040 */ u64 rxpe_err_reg; 3871#define VXGE_HAL_RXPE_ERR_REG_RXPE_XT0_FRM_SG_ERR mBIT(0) 3872#define VXGE_HAL_RXPE_ERR_REG_RXPE_XT1_FRM_SG_ERR mBIT(1) 3873#define VXGE_HAL_RXPE_ERR_REG_RXPE_FPDU_MEM_SG_ERR mBIT(2) 3874#define VXGE_HAL_RXPE_ERR_REG_RXPE_MSG2RXPE_SG_ERR(val) vBIT(val, 3, 2) 3875#define VXGE_HAL_RXPE_ERR_REG_RXPE_XT0_IRAM_SG_ERR(val) vBIT(val, 5, 2) 3876#define VXGE_HAL_RXPE_ERR_REG_RXPE_XT1_IRAM_SG_ERR(val) vBIT(val, 7, 2) 3877#define VXGE_HAL_RXPE_ERR_REG_RXPE_XT_DRAM_PA_SG_ERR(val) vBIT(val, 9, 2) 3878#define VXGE_HAL_RXPE_ERR_REG_RXPE_XT_DRAM_PB_SG_ERR(val) vBIT(val, 11, 2) 3879#define VXGE_HAL_RXPE_ERR_REG_RXPE_XT0_TRCE_SG_ERR mBIT(13) 3880#define VXGE_HAL_RXPE_ERR_REG_RXPE_XT1_TRCE_SG_ERR mBIT(14) 3881#define VXGE_HAL_RXPE_ERR_REG_RXPE_XT0_FRM_DB_ERR mBIT(32) 3882#define VXGE_HAL_RXPE_ERR_REG_RXPE_XT1_FRM_DB_ERR mBIT(33) 3883#define VXGE_HAL_RXPE_ERR_REG_RXPE_FPDU_MEM_DB_ERR mBIT(34) 3884#define VXGE_HAL_RXPE_ERR_REG_RXPE_MSG2RXPE_DB_ERR(val) vBIT(val, 35, 2) 3885#define VXGE_HAL_RXPE_ERR_REG_RXPE_XT0_IRAM_DB_ERR(val) vBIT(val, 37, 2) 3886#define VXGE_HAL_RXPE_ERR_REG_RXPE_XT1_IRAM_DB_ERR(val) vBIT(val, 39, 2) 3887#define VXGE_HAL_RXPE_ERR_REG_RXPE_XT_DRAM_PA_DB_ERR(val) vBIT(val, 41, 2) 3888#define VXGE_HAL_RXPE_ERR_REG_RXPE_XT_DRAM_PB_DB_ERR(val) vBIT(val, 43, 2) 3889#define VXGE_HAL_RXPE_ERR_REG_RXPE_XT0_TRCE_DB_ERR mBIT(45) 3890#define VXGE_HAL_RXPE_ERR_REG_RXPE_XT1_TRCE_DB_ERR mBIT(46) 3891#define VXGE_HAL_RXPE_ERR_REG_RXPE_XT0_XLMI_SERR mBIT(54) 3892#define VXGE_HAL_RXPE_ERR_REG_RXPE_XT1_XLMI_SERR mBIT(55) 3893#define VXGE_HAL_RXPE_ERR_REG_RXPE_DRAM_WR_ERR mBIT(58) 3894#define VXGE_HAL_RXPE_ERR_REG_RXPE_IMSGIN_WR_FSM_ERR mBIT(59) 3895#define VXGE_HAL_RXPE_ERR_REG_RXPE_IMSGIN_EVCTRL_FSM_ERR mBIT(60) 3896#define VXGE_HAL_RXPE_ERR_REG_RXPE_MSG2RXPE_FIFO_ERR mBIT(61) 3897#define VXGE_HAL_RXPE_ERR_REG_RXPE_IMSGOUT_COLLISION_ERR mBIT(62) 3898#define VXGE_HAL_RXPE_ERR_REG_RXPE_SM_ERR mBIT(63) 3899/* 0x04048 */ u64 rxpe_err_mask; 3900/* 0x04050 */ u64 rxpe_err_alarm; 3901/* 0x04058 */ u64 dlm_err_reg; 3902#define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_CTXT_PA_SG_ERR mBIT(0) 3903#define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_CTXT_PB_SG_ERR mBIT(1) 3904#define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_ACK_PA_SG_ERR mBIT(2) 3905#define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_ACK_PB_SG_ERR mBIT(3) 3906#define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_RIRR_PA_SG_ERR mBIT(4) 3907#define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_RIRR_PB_SG_ERR mBIT(5) 3908#define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_AWRQ_MEM_SG_ERR mBIT(6) 3909#define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_LWRQ_MEM_SG_ERR mBIT(7) 3910#define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_CTXT_PA_DB_ERR mBIT(8) 3911#define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_CTXT_PB_DB_ERR mBIT(9) 3912#define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_ACK_PA_DB_ERR mBIT(10) 3913#define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_ACK_PB_DB_ERR mBIT(11) 3914#define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_RIRR_PA_DB_ERR mBIT(12) 3915#define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_RIRR_PB_DB_ERR mBIT(13) 3916#define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_AWRQ_MEM_DB_ERR mBIT(14) 3917#define VXGE_HAL_DLM_ERR_REG_DLM_PE_DLM_LWRQ_MEM_DB_ERR mBIT(15) 3918#define VXGE_HAL_DLM_ERR_REG_DLM_ACC_PA_STATE_SM_ERR mBIT(16) 3919#define VXGE_HAL_DLM_ERR_REG_DLM_ACC_PB_STATE_SM_ERR mBIT(17) 3920#define VXGE_HAL_DLM_ERR_REG_DLM_ACK_RDMEM_DATA_STATE_SM_ERR mBIT(18) 3921#define VXGE_HAL_DLM_ERR_REG_DLM_AFLM_RDFIFO_STATE_SM_ERR mBIT(19) 3922#define VXGE_HAL_DLM_ERR_REG_DLM_AFLM_STATE_SM_ERR mBIT(20) 3923#define VXGE_HAL_DLM_ERR_REG_DLM_APTR_ALLOC_STATE_SM_ERR mBIT(21) 3924#define VXGE_HAL_DLM_ERR_REG_DLM_ARRQ_RDFIFO_STATE_SM_ERR mBIT(22) 3925#define VXGE_HAL_DLM_ERR_REG_DLM_ARRQ_STATE_SM_ERR mBIT(23) 3926#define VXGE_HAL_DLM_ERR_REG_DLM_AWRQ_STATE_SM_ERR mBIT(24) 3927#define VXGE_HAL_DLM_ERR_REG_DLM_EVENT_CTXT_STATE_SM_ERR mBIT(25) 3928#define VXGE_HAL_DLM_ERR_REG_DLM_LCC_PA_STATE_SM_ERR mBIT(26) 3929#define VXGE_HAL_DLM_ERR_REG_DLM_LCC_PB_STATE_SM_ERR mBIT(27) 3930#define VXGE_HAL_DLM_ERR_REG_DLM_LFLM_RDFIFO_STATE_SM_ERR mBIT(28) 3931#define VXGE_HAL_DLM_ERR_REG_DLM_LFLM_STATE_SM_ERR mBIT(29) 3932#define VXGE_HAL_DLM_ERR_REG_DLM_LPTR_ALLOC_STATE_SM_ERR mBIT(30) 3933#define VXGE_HAL_DLM_ERR_REG_DLM_LRRQ_RDFIFO_STATE_SM_ERR mBIT(31) 3934#define VXGE_HAL_DLM_ERR_REG_DLM_LRRQ_STATE_SM_ERR mBIT(32) 3935#define VXGE_HAL_DLM_ERR_REG_DLM_LWRQ_STATE_SM_ERR mBIT(33) 3936#define VXGE_HAL_DLM_ERR_REG_DLM_PCIWR_STATE_SM_ERR mBIT(34) 3937#define VXGE_HAL_DLM_ERR_REG_DLM_PFETCH_STATE_SM_ERR mBIT(35) 3938#define VXGE_HAL_DLM_ERR_REG_DLM_RCC_PA_STATE_SM_ERR mBIT(36) 3939#define VXGE_HAL_DLM_ERR_REG_DLM_RCC_PB_STATE_SM_ERR mBIT(37) 3940#define VXGE_HAL_DLM_ERR_REG_DLM_RFLM_RDFIFO_STATE_SM_ERR mBIT(38) 3941#define VXGE_HAL_DLM_ERR_REG_DLM_RFLM_STATE_SM_ERR mBIT(39) 3942#define VXGE_HAL_DLM_ERR_REG_DLM_RIRR_RDMEM_DATA_STATE_SM_ERR mBIT(40) 3943#define VXGE_HAL_DLM_ERR_REG_DLM_RPTR_ALLOC_STATE_SM_ERR mBIT(41) 3944#define VXGE_HAL_DLM_ERR_REG_DLM_RRRQ_RDFIFO_STATE_SM_ERR mBIT(42) 3945#define VXGE_HAL_DLM_ERR_REG_DLM_RRRQ_STATE_SM_ERR mBIT(43) 3946#define VXGE_HAL_DLM_ERR_REG_DLM_RWRQ_STATE_SM_ERR mBIT(44) 3947#define VXGE_HAL_DLM_ERR_REG_DLM_RXACK_STATE_SM_ERR mBIT(45) 3948#define VXGE_HAL_DLM_ERR_REG_DLM_RXLIRR_STATE_SM_ERR mBIT(46) 3949#define VXGE_HAL_DLM_ERR_REG_DLM_RXRIRR_STATE_SM_ERR mBIT(47) 3950#define VXGE_HAL_DLM_ERR_REG_DLM_TXACK_RETX_STATE_SM_ERR mBIT(48) 3951#define VXGE_HAL_DLM_ERR_REG_DLM_TXACK_STATE_SM_ERR mBIT(49) 3952#define VXGE_HAL_DLM_ERR_REG_DLM_TXLIRR_STATE_SM_ERR mBIT(50) 3953#define VXGE_HAL_DLM_ERR_REG_DLM_TXRIRR_RETX_STATE_SM_ERR mBIT(51) 3954#define VXGE_HAL_DLM_ERR_REG_DLM_TXRIRR_STATE_SM_ERR mBIT(52) 3955#define VXGE_HAL_DLM_ERR_REG_DLM_PREFETCH_ERR mBIT(53) 3956#define VXGE_HAL_DLM_ERR_REG_DLM_AFLM_FIFO_ERR mBIT(55) 3957#define VXGE_HAL_DLM_ERR_REG_DLM_RFLM_FIFO_ERR mBIT(56) 3958#define VXGE_HAL_DLM_ERR_REG_DLM_LFLM_FIFO_ERR mBIT(57) 3959#define VXGE_HAL_DLM_ERR_REG_DLM_ARRQ_FIFO_ERR mBIT(58) 3960#define VXGE_HAL_DLM_ERR_REG_DLM_RRRQ_FIFO_ERR mBIT(59) 3961#define VXGE_HAL_DLM_ERR_REG_DLM_LRRQ_FIFO_ERR mBIT(60) 3962#define VXGE_HAL_DLM_ERR_REG_DLM_ACK_PTR_FIFO_ERR mBIT(61) 3963#define VXGE_HAL_DLM_ERR_REG_DLM_RIRR_PTR_FIFO_ERR mBIT(62) 3964#define VXGE_HAL_DLM_ERR_REG_DLM_LIRR_PTR_FIFO_ERR mBIT(63) 3965/* 0x04060 */ u64 dlm_err_mask; 3966/* 0x04068 */ u64 dlm_err_alarm; 3967/* 0x04070 */ u64 oes_err_reg; 3968#define VXGE_HAL_OES_ERR_REG_OES_INPUT_ARB_SM_ERR mBIT(0) 3969#define VXGE_HAL_OES_ERR_REG_OES_PEND_ARB_SM_ERR mBIT(1) 3970#define VXGE_HAL_OES_ERR_REG_OES_RXSEG_FIFO_ERR mBIT(2) 3971#define VXGE_HAL_OES_ERR_REG_OES_RXEVT_FIFO_ERR mBIT(3) 3972#define VXGE_HAL_OES_ERR_REG_OES_TXTDB_FIFO_ERR mBIT(4) 3973#define VXGE_HAL_OES_ERR_REG_OES_RXTX_FIFO_ERR mBIT(5) 3974#define VXGE_HAL_OES_ERR_REG_OES_TXIMSG_FIFO_ERR mBIT(6) 3975#define VXGE_HAL_OES_ERR_REG_OES_TXCONT_FIFO_ERR mBIT(7) 3976/* 0x04078 */ u64 oes_err_mask; 3977/* 0x04080 */ u64 oes_err_alarm; 3978/* 0x04088 */ u64 txpe_err_reg; 3979#define VXGE_HAL_TXPE_ERR_REG_TXPE_MSG2TXPE_SG_ERR(val) vBIT(val, 0, 2) 3980#define VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_DATA_PA_SG_ERR mBIT(2) 3981#define VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_DATA_PB_SG_ERR mBIT(3) 3982#define VXGE_HAL_TXPE_ERR_REG_TXPE_XT_DRAM_SG_ERR(val) vBIT(val, 4, 2) 3983#define VXGE_HAL_TXPE_ERR_REG_TXPE_XT_IRAM_SG_ERR(val) vBIT(val, 6, 2) 3984#define VXGE_HAL_TXPE_ERR_REG_TXPE_XT_TRACE_SG_ERR mBIT(8) 3985#define VXGE_HAL_TXPE_ERR_REG_TXPE_DOOR_IMM_SG_ERR mBIT(9) 3986#define VXGE_HAL_TXPE_ERR_REG_TXPE_NCE_PA_SG_ERR mBIT(10) 3987#define VXGE_HAL_TXPE_ERR_REG_TXPE_NCE_PB_SG_ERR mBIT(11) 3988#define VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_INFO_PA_SG_ERR mBIT(12) 3989#define VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_INFO_PB_SG_ERR mBIT(13) 3990#define VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_STG_SG_ERR mBIT(14) 3991#define VXGE_HAL_TXPE_ERR_REG_TXPE_MSG2TXPE_DB_ERR(val) vBIT(val, 16, 2) 3992#define VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_DATA_PA_DB_ERR mBIT(18) 3993#define VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_DATA_PB_DB_ERR mBIT(19) 3994#define VXGE_HAL_TXPE_ERR_REG_TXPE_XT_DRAM_DB_ERR(val) vBIT(val, 20, 2) 3995#define VXGE_HAL_TXPE_ERR_REG_TXPE_XT_IRAM_DB_ERR(val) vBIT(val, 22, 2) 3996#define VXGE_HAL_TXPE_ERR_REG_TXPE_XT_TRACE_DB_ERR mBIT(24) 3997#define VXGE_HAL_TXPE_ERR_REG_TXPE_DOOR_IMM_DB_ERR mBIT(25) 3998#define VXGE_HAL_TXPE_ERR_REG_TXPE_NCE_PA_DB_ERR mBIT(26) 3999#define VXGE_HAL_TXPE_ERR_REG_TXPE_NCE_PB_DB_ERR mBIT(27) 4000#define VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_INFO_PA_DB_ERR mBIT(28) 4001#define VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_INFO_PB_DB_ERR mBIT(29) 4002#define VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_STG_DB_ERR mBIT(30) 4003#define VXGE_HAL_TXPE_ERR_REG_TXPE_DOOR_SM_ERR mBIT(32) 4004#define VXGE_HAL_TXPE_ERR_REG_TXPE_IMSGIN_SM_ERR mBIT(33) 4005#define VXGE_HAL_TXPE_ERR_REG_TXPE_SEND_SM_ERR mBIT(34) 4006#define VXGE_HAL_TXPE_ERR_REG_TXPE_SEND_TCE_CHOICE_SM_ERR mBIT(35) 4007#define VXGE_HAL_TXPE_ERR_REG_TXPE_SEND_DIV_SM_ERR mBIT(36) 4008#define VXGE_HAL_TXPE_ERR_REG_TXPE_DMA_SM_ERR mBIT(37) 4009#define VXGE_HAL_TXPE_ERR_REG_TXPE_DMA_RES_SM_ERR mBIT(38) 4010#define VXGE_HAL_TXPE_ERR_REG_TXPE_DMA_NACK_SM_ERR mBIT(39) 4011#define VXGE_HAL_TXPE_ERR_REG_TXPE_RDTCE_SM_ERR mBIT(40) 4012#define VXGE_HAL_TXPE_ERR_REG_TXPE_CMGIF_RDRQ_SM_ERR mBIT(41) 4013#define VXGE_HAL_TXPE_ERR_REG_TXPE_CMGIF_READDRES_SM_ERR mBIT(42) 4014#define VXGE_HAL_TXPE_ERR_REG_TXPE_TCM_CTXT_SM_ERR mBIT(43) 4015#define VXGE_HAL_TXPE_ERR_REG_TXPE_PRI_TCE_UPDATE_SM_ERR mBIT(44) 4016#define VXGE_HAL_TXPE_ERR_REG_TXPE_DMA_GET_SM_ERR mBIT(45) 4017#define VXGE_HAL_TXPE_ERR_REG_TXPE_DMA_DONE_SM_ERR mBIT(46) 4018#define VXGE_HAL_TXPE_ERR_REG_TXPE_INIT_SM_ERR mBIT(47) 4019#define VXGE_HAL_TXPE_ERR_REG_TXPE_FETCH_SM_ERR mBIT(48) 4020#define VXGE_HAL_TXPE_ERR_REG_TXPE_HOG_SM_ERR mBIT(49) 4021#define VXGE_HAL_TXPE_ERR_REG_TXPE_PMON_SM_ERR mBIT(50) 4022#define VXGE_HAL_TXPE_ERR_REG_TXPE_XT_DRAM_SM_ERR mBIT(51) 4023#define VXGE_HAL_TXPE_ERR_REG_TXPE_NCM_CTXT_SM_ERR mBIT(52) 4024#define VXGE_HAL_TXPE_ERR_REG_TXPE_NCM_MEM_SM_ERR mBIT(53) 4025#define VXGE_HAL_TXPE_ERR_REG_TXPE_DMA_RQ_SM_ERR mBIT(54) 4026#define VXGE_HAL_TXPE_ERR_REG_TXPE_RDRES_PHASE_ERR mBIT(55) 4027#define VXGE_HAL_TXPE_ERR_REG_TXPE_XT_XLMI_SERR mBIT(56) 4028#define VXGE_HAL_TXPE_ERR_REG_TXPE_DOOR_WRP_ERR mBIT(57) 4029#define VXGE_HAL_TXPE_ERR_REG_TXPE_DOOR_FIFO_ERR mBIT(58) 4030#define VXGE_HAL_TXPE_ERR_REG_TXPE_DMA_DFIFO_ERR mBIT(59) 4031#define VXGE_HAL_TXPE_ERR_REG_TXPE_DMA_HFIFO_ERR mBIT(60) 4032#define VXGE_HAL_TXPE_ERR_REG_TXPE_SEND_DIVIDE_ERR mBIT(61) 4033#define VXGE_HAL_TXPE_ERR_REG_TXPE_PDA_NACK_FIFO_ERR mBIT(62) 4034#define VXGE_HAL_TXPE_ERR_REG_TXPE_MEM_CONFLICT_ERR mBIT(63) 4035/* 0x04090 */ u64 txpe_err_mask; 4036/* 0x04098 */ u64 txpe_err_alarm; 4037/* 0x040a0 */ u64 txpe_bcc_mem_sg_ecc_err_reg; 4038#define VXGE_HAL_TXPE_BCC_MEM_SG_ECC_ERR_REG_TXPE_BASE_TXPE_SG_ERR(val)\ 4039 vBIT(val, 0, 32) 4040#define VXGE_HAL_TXPE_BCC_MEM_SG_ECC_ERR_REG_TXPE_BASE_CDP_SG_ERR(val)\ 4041 vBIT(val, 32, 32) 4042/* 0x040a8 */ u64 txpe_bcc_mem_sg_ecc_err_mask; 4043/* 0x040b0 */ u64 txpe_bcc_mem_sg_ecc_err_alarm; 4044/* 0x040b8 */ u64 txpe_bcc_mem_db_ecc_err_reg; 4045#define VXGE_HAL_TXPE_BCC_MEM_DB_ECC_ERR_REG_TXPE_BASE_TXPE_DB_ERR(val)\ 4046 vBIT(val, 0, 32) 4047#define VXGE_HAL_TXPE_BCC_MEM_DB_ECC_ERR_REG_TXPE_BASE_CDP_DB_ERR(val)\ 4048 vBIT(val, 32, 32) 4049/* 0x040c0 */ u64 txpe_bcc_mem_db_ecc_err_mask; 4050/* 0x040c8 */ u64 txpe_bcc_mem_db_ecc_err_alarm; 4051/* 0x040d0 */ u64 rpe_fsm_err_reg; 4052#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_CMI_SHADOW_ERR mBIT(0) 4053#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCC_SHADOW_ERR mBIT(1) 4054#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCM_SHADOW_ERR mBIT(2) 4055#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_QEM_SHADOW_ERR mBIT(3) 4056#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_SHADOW_ERR mBIT(4) 4057#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCI_SHADOW_ERR mBIT(5) 4058#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCO_SHADOW_ERR mBIT(6) 4059#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_CMI_RWM_ERR mBIT(7) 4060#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_CMI_RRM_ERR mBIT(8) 4061#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCC_SCC_ERR mBIT(9) 4062#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCC_CMM_ERR mBIT(10) 4063#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_QEM_OIF_ERR mBIT(11) 4064#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_QEM_FPG_ERR mBIT(12) 4065#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_QEM_WCC_ERR mBIT(13) 4066#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_QEM_WMM_ERR mBIT(14) 4067#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_OIF_ERR mBIT(15) 4068#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_QRI_ERR mBIT(16) 4069#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_CTL_EFS_ERR mBIT(17) 4070#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_CTL_EFS_UNDEF_EVENT mBIT(18) 4071#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_EPE_BS_ERR mBIT(19) 4072#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_EPE_IWP_ERR mBIT(20) 4073#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_EPE_LRO_ERR mBIT(21) 4074#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_RIM_HDR_ERR mBIT(22) 4075#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_RIM_MUX_ERR mBIT(23) 4076#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_RIM_RLC_ERR mBIT(24) 4077#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCI_IPM_DLM_ERR mBIT(25) 4078#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCI_IPM_MSG_ERR mBIT(26) 4079#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCI_ARB_ERR mBIT(27) 4080#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCO_HBI_ERR mBIT(28) 4081#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_RCO_OPC_ERR mBIT(29) 4082#define VXGE_HAL_RPE_FSM_ERR_REG_RPE_PDM_CTL_EFS_FW_ERR mBIT(32) 4083/* 0x040d8 */ u64 rpe_fsm_err_mask; 4084/* 0x040e0 */ u64 rpe_fsm_err_alarm; 4085 u8 unused04100[0x04100 - 0x040e8]; 4086 4087/* 0x04100 */ u64 one_cfg; 4088#define VXGE_HAL_ONE_CFG_ONE_CFG_RDY mBIT(7) 4089/* 0x04108 */ u64 sgrp_alloc[17]; 4090#define VXGE_HAL_SGRP_ALLOC_SGRP_ALLOC(val) vBIT(val, 0, 64) 4091/* 0x04190 */ u64 sgrp_iwarp_lro_alloc; 4092#define VXGE_HAL_SGRP_IWARP_LRO_ALLOC_ENABLE_IWARP mBIT(7) 4093#define VXGE_HAL_SGRP_IWARP_LRO_ALLOC_LAST_IWARP_SGRP(val) vBIT(val, 11, 5) 4094/* 0x04198 */ u64 rpe_cfg0; 4095#define VXGE_HAL_RPE_CFG0_RCC_NBR_SLOTS(val) vBIT(val, 3, 5) 4096#define VXGE_HAL_RPE_CFG0_RCC_NBR_FREE_SLOTS(val) vBIT(val, 11, 5) 4097#define VXGE_HAL_RPE_CFG0_RCC_MODE mBIT(23) 4098#define VXGE_HAL_RPE_CFG0_LL_SEND_MAX_SIZE(val) vBIT(val, 24, 8) 4099#define VXGE_HAL_RPE_CFG0_BS_ACK_WQE_PF_ENA mBIT(38) 4100#define VXGE_HAL_RPE_CFG0_IWARP_ISL_PF_ENA mBIT(39) 4101#define VXGE_HAL_RPE_CFG0_PDM_FRAME_ECC_ENABLE_N mBIT(43) 4102#define VXGE_HAL_RPE_CFG0_PDM_RCMD_ECC_ENABLE_N mBIT(44) 4103#define VXGE_HAL_RPE_CFG0_RCQ_ECC_ENABLE_N mBIT(45) 4104#define VXGE_HAL_RPE_CFG0_RCO_PBLE_ECC_ENABLE_N mBIT(46) 4105#define VXGE_HAL_RPE_CFG0_RCM_ECC_ENABLE_N mBIT(47) 4106#define VXGE_HAL_RPE_CFG0_PDM_FRAME_PHASE_ENABLE mBIT(50) 4107#define VXGE_HAL_RPE_CFG0_DLM_RCMD_PHASE_ENABLE mBIT(51) 4108#define VXGE_HAL_RPE_CFG0_MSG_RCMD_PHASE_ENABLE mBIT(52) 4109#define VXGE_HAL_RPE_CFG0_PDM_RCMD_PHASE_ENABLE mBIT(53) 4110#define VXGE_HAL_RPE_CFG0_RCQ_PHASE_ENABLE mBIT(54) 4111#define VXGE_HAL_RPE_CFG0_RCO_PBLE_PHASE_ENABLE mBIT(55) 4112/* 0x041a0 */ u64 rpe_cfg1; 4113#define VXGE_HAL_RPE_CFG1_WQEOWN_LRO_CTR_ENA mBIT(5) 4114#define VXGE_HAL_RPE_CFG1_WQEOWN_BS_CTR_ENA mBIT(6) 4115#define VXGE_HAL_RPE_CFG1_WQEOWN_IWARP_CTR_ENA mBIT(7) 4116#define VXGE_HAL_RPE_CFG1_DLM_RCMD_MAX_CREDITS(val) vBIT(val, 10, 6) 4117#define VXGE_HAL_RPE_CFG1_MSG_RCMD_MAX_CREDITS(val) vBIT(val, 18, 6) 4118#define VXGE_HAL_RPE_CFG1_PDM_RCMD_MAX_CREDITS(val) vBIT(val, 25, 7) 4119#define VXGE_HAL_RPE_CFG1_RCQ_MAX_CREDITS(val) vBIT(val, 32, 8) 4120#define VXGE_HAL_RPE_CFG1_RCQ_DLM_PRI(val) vBIT(val, 46, 2) 4121#define VXGE_HAL_RPE_CFG1_RCQ_MSG_PRI(val) vBIT(val, 54, 2) 4122#define VXGE_HAL_RPE_CFG1_RCQ_PDM_PRI(val) vBIT(val, 62, 2) 4123/* 0x041a8 */ u64 rpe_cfg2; 4124#define VXGE_HAL_RPE_CFG2_RCQ_ARB_CAL0_PRI(val) vBIT(val, 6, 2) 4125#define VXGE_HAL_RPE_CFG2_RCQ_ARB_CAL1_PRI(val) vBIT(val, 14, 2) 4126#define VXGE_HAL_RPE_CFG2_RCQ_ARB_CAL2_PRI(val) vBIT(val, 22, 2) 4127#define VXGE_HAL_RPE_CFG2_RCQ_ARB_CAL3_PRI(val) vBIT(val, 30, 2) 4128#define VXGE_HAL_RPE_CFG2_RCQ_ARB_CAL4_PRI(val) vBIT(val, 38, 2) 4129#define VXGE_HAL_RPE_CFG2_RCQ_ARB_CAL5_PRI(val) vBIT(val, 46, 2) 4130#define VXGE_HAL_RPE_CFG2_RDMA_WRITE_ORDER_ENABLE mBIT(49) 4131#define VXGE_HAL_RPE_CFG2_RDMA_RDRESP_ORDER_ENABLE mBIT(50) 4132#define VXGE_HAL_RPE_CFG2_RDMA_SEND_ORDER_ENABLE mBIT(51) 4133#define VXGE_HAL_RPE_CFG2_RDMA_RDREQ_ORDER_ENABLE mBIT(52) 4134#define VXGE_HAL_RPE_CFG2_RDMA_TERMINATE_ORDER_ENABLE mBIT(53) 4135#define VXGE_HAL_RPE_CFG2_IWARP_MISALIGNED_ORDER_ENABLE mBIT(54) 4136#define VXGE_HAL_RPE_CFG2_IWARP_TIMER_ORDER_ENABLE mBIT(55) 4137#define VXGE_HAL_RPE_CFG2_IWARP_IMSG_ORDER_ENABLE mBIT(56) 4138#define VXGE_HAL_RPE_CFG2_BS_IWARP_ACK_ORDER_ENABLE mBIT(57) 4139#define VXGE_HAL_RPE_CFG2_BS_DATA_ORDER_ENABLE mBIT(58) 4140#define VXGE_HAL_RPE_CFG2_BS_TIMER_ORDER_ENABLE mBIT(59) 4141#define VXGE_HAL_RPE_CFG2_BS_IMSG_ORDER_ENABLE mBIT(60) 4142#define VXGE_HAL_RPE_CFG2_LRO_FRAME_ORDER_ENABLE mBIT(61) 4143#define VXGE_HAL_RPE_CFG2_LRO_TIMER_ORDER_ENABLE mBIT(62) 4144#define VXGE_HAL_RPE_CFG2_LRO_IMSG_ORDER_ENABLE mBIT(63) 4145 u8 unused041c0[0x041c0 - 0x041b0]; 4146 4147/* 0x041c0 */ u64 rpe_cfg5; 4148#define VXGE_HAL_RPE_CFG5_LRO_IGNORE_RPA_PARSE_ERRS mBIT(4) 4149#define VXGE_HAL_RPE_CFG5_LRO_IGNORE_FRM_INT_ERRS mBIT(5) 4150#define VXGE_HAL_RPE_CFG5_LRO_IGNORE_L3_CSUM_ERRS mBIT(6) 4151#define VXGE_HAL_RPE_CFG5_LRO_IGNORE_L4_CSUM_ERRS mBIT(7) 4152#define VXGE_HAL_RPE_CFG5_LRO_NORM_SCATTER_IPV4_OPTIONS mBIT(14) 4153#define VXGE_HAL_RPE_CFG5_LRO_NORM_SCATTER_IPV6_EXTHDRS mBIT(15) 4154#define VXGE_HAL_RPE_CFG5_USE_CONCISE_ADAPTIVE_LRO_CQE mBIT(22) 4155#define VXGE_HAL_RPE_CFG5_USE_CONCISE_PRECONFIG_LRO_CQE mBIT(23) 4156/* 0x041c8 */ u64 wqeown0; 4157#define VXGE_HAL_WQEOWN0_RPE_LRO_CTR(val) vBIT(val, 13, 19) 4158#define VXGE_HAL_WQEOWN0_RPE_BS_CTR(val) vBIT(val, 45, 19) 4159/* 0x041d0 */ u64 wqeown1; 4160#define VXGE_HAL_WQEOWN1_RPE_IWARP_CTR(val) vBIT(val, 13, 19) 4161/* 0x041d8 */ u64 rpe_wqeown2; 4162#define VXGE_HAL_RPE_WQEOWN2_LRO_THRESHOLD(val) vBIT(val, 13, 19) 4163#define VXGE_HAL_RPE_WQEOWN2_BS_THRESHOLD(val) vBIT(val, 45, 19) 4164 u8 unused04200[0x04200 - 0x041e0]; 4165 4166/* 0x04200 */ u64 pe_ctxt; 4167#define VXGE_HAL_PE_CTXT_SCC_TRIGGER_READ mBIT(7) 4168#define VXGE_HAL_PE_CTXT_S1_SIZE(val) vBIT(val, 10, 6) 4169#define VXGE_HAL_PE_CTXT_S2_SIZE(val) vBIT(val, 26, 6) 4170#define VXGE_HAL_PE_CTXT_S3_SIZE(val) vBIT(val, 42, 6) 4171#define VXGE_HAL_PE_CTXT_NP_XFER mBIT(55) 4172#define VXGE_HAL_PE_CTXT_NP_SPACER mBIT(63) 4173/* 0x04208 */ u64 pe_cfg; 4174#define VXGE_HAL_PE_CFG_RXPE_ECC_ENABLE_N mBIT(7) 4175#define VXGE_HAL_PE_CFG_TXPE_ECC_ENABLE_N mBIT(15) 4176#define VXGE_HAL_PE_CFG_DLM_ECC_ENABLE_N mBIT(23) 4177#define VXGE_HAL_PE_CFG_CDP_ECC_ENABLE_N mBIT(31) 4178#define VXGE_HAL_PE_CFG_PET_ECC_ENABLE_N mBIT(39) 4179#define VXGE_HAL_PE_CFG_MAX_RXB2B(val) vBIT(val, 56, 8) 4180/* 0x04210 */ u64 pe_stats_cmd; 4181#define VXGE_HAL_PE_STATS_CMD_GO mBIT(7) 4182#define VXGE_HAL_PE_STATS_CMD_SELECT_TXPE mBIT(15) 4183#define VXGE_HAL_PE_STATS_CMD_ADDRESS(val) vBIT(val, 21, 11) 4184/* 0x04218 */ u64 pe_stats_data; 4185#define VXGE_HAL_PE_STATS_DATA_PE_RETURNED(val) vBIT(val, 0, 64) 4186/* 0x04220 */ u64 rxpe_fp_mask; 4187#define VXGE_HAL_RXPE_FP_MASK_RXPE_FP_MASK(val) vBIT(val, 18, 46) 4188/* 0x04228 */ u64 rxpe_cfg; 4189#define VXGE_HAL_RXPE_CFG_FW_EXTEND_FP mBIT(7) 4190#define VXGE_HAL_RXPE_CFG_RETXK_SP_DONE mBIT(15) 4191/* 0x04230 */ u64 pe_xt_ctrl1; 4192#define VXGE_HAL_PE_XT_CTRL1_IRAM_ADDRESS(val) vBIT(val, 4, 12) 4193#define VXGE_HAL_PE_XT_CTRL1_ENABLE_GO_FOR_WR mBIT(23) 4194#define VXGE_HAL_PE_XT_CTRL1_IRAM_READ mBIT(27) 4195#define VXGE_HAL_PE_XT_CTRL1_TXP_IRAM_SEL mBIT(29) 4196#define VXGE_HAL_PE_XT_CTRL1_RXP0_IRAM_SEL mBIT(30) 4197#define VXGE_HAL_PE_XT_CTRL1_RXP1_IRAM_SEL mBIT(31) 4198#define VXGE_HAL_PE_XT_CTRL1_TXP_IRAM_ECC_ENABLE_N mBIT(37) 4199#define VXGE_HAL_PE_XT_CTRL1_RXP0_IRAM_ECC_ENABLE_N mBIT(38) 4200#define VXGE_HAL_PE_XT_CTRL1_RXP1_IRAM_ECC_ENABLE_N mBIT(39) 4201#define VXGE_HAL_PE_XT_CTRL1_TXP_DRAM_ECC_ENABLE_N mBIT(46) 4202#define VXGE_HAL_PE_XT_CTRL1_RXP_DRAM_ECC_ENABLE_N mBIT(47) 4203#define VXGE_HAL_PE_XT_CTRL1_TXP_RUNSTALL mBIT(53) 4204#define VXGE_HAL_PE_XT_CTRL1_RXP0_RUNSTALL mBIT(54) 4205#define VXGE_HAL_PE_XT_CTRL1_RXP1_RUNSTALL mBIT(55) 4206#define VXGE_HAL_PE_XT_CTRL1_TXP_BRESET mBIT(61) 4207#define VXGE_HAL_PE_XT_CTRL1_RXP0_BRESET mBIT(62) 4208#define VXGE_HAL_PE_XT_CTRL1_RXP1_BRESET mBIT(63) 4209/* 0x04238 */ u64 pe_xt_ctrl2; 4210#define VXGE_HAL_PE_XT_CTRL2_IRAM_WRITE_DATA(val) vBIT(val, 0, 64) 4211/* 0x04240 */ u64 pe_xt_ctrl3; 4212#define VXGE_HAL_PE_XT_CTRL3_GO mBIT(63) 4213/* 0x04248 */ u64 pe_xt_ctrl4; 4214#define VXGE_HAL_PE_XT_CTRL4_PE_IRAM_READ_DATA(val) vBIT(val, 0, 64) 4215/* 0x04250 */ u64 pet_iwarp_counters; 4216#define VXGE_HAL_PET_IWARP_COUNTERS_MASTER(val) vBIT(val, 0, 32) 4217#define VXGE_HAL_PET_IWARP_COUNTERS_INTERVAL(val) vBIT(val, 40, 24) 4218/* 0x04258 */ u64 pet_iwarp_slow_counter; 4219#define VXGE_HAL_PET_IWARP_SLOW_COUNTER_MASTER(val) vBIT(val, 0, 32) 4220/* 0x04260 */ u64 pet_iwarp_timers; 4221#define VXGE_HAL_PET_IWARP_TIMERS_TCP_NOW(val) vBIT(val, 0, 32) 4222#define VXGE_HAL_PET_IWARP_TIMERS_TCP_SLOW_CLK(val) vBIT(val, 32, 32) 4223/* 0x04268 */ u64 pet_lro_cfg; 4224#define VXGE_HAL_PET_LRO_CFG_START_VALUE(val) vBIT(val, 6, 2) 4225/* 0x04270 */ u64 pet_lro_counters; 4226#define VXGE_HAL_PET_LRO_COUNTERS_MASTER(val) vBIT(val, 0, 32) 4227#define VXGE_HAL_PET_LRO_COUNTERS_INTERVAL(val) vBIT(val, 40, 24) 4228/* 0x04278 */ u64 pet_timer_bp_ctrl; 4229#define VXGE_HAL_PET_TIMER_BP_CTRL_RD_XON mBIT(7) 4230#define VXGE_HAL_PET_TIMER_BP_CTRL_WR_XON mBIT(15) 4231#define VXGE_HAL_PET_TIMER_BP_CTRL_ROCRC_BYP mBIT(23) 4232#define VXGE_HAL_PET_TIMER_BP_CTRL_H2L_BYP mBIT(31) 4233/* 0x04280 */ u64 pe_vp_ack[17]; 4234#define VXGE_HAL_PE_VP_ACK_BLK_LIMIT(val) vBIT(val, 32, 32) 4235/* 0x04308 */ u64 pe_vp[17]; 4236#define VXGE_HAL_PE_VP_RIRR_BLK_LIMIT(val) vBIT(val, 0, 32) 4237#define VXGE_HAL_PE_VP_LIRR_BLK_LIMIT(val) vBIT(val, 32, 32) 4238/* 0x04390 */ u64 dlm_cfg; 4239#define VXGE_HAL_DLM_CFG_AWRQ_PHASE_ENABLE mBIT(7) 4240#define VXGE_HAL_DLM_CFG_ACK_PTR_AE_LEVEL(val) vBIT(val, 12, 4) 4241#define VXGE_HAL_DLM_CFG_LWRQ_PHASE_ENABLE mBIT(23) 4242#define VXGE_HAL_DLM_CFG_LIRR_PTR_AE_LEVEL(val) vBIT(val, 28, 4) 4243#define VXGE_HAL_DLM_CFG_RIRR_PTR_AE_LEVEL(val) vBIT(val, 44, 4) 4244 u8 unused04400[0x04400 - 0x04398]; 4245 4246/* 0x04400 */ u64 txpe_towi_cfg; 4247#define VXGE_HAL_TXPE_TOWI_CFG_TOWI_CACHE_SIZE(val) vBIT(val, 48, 8) 4248#define VXGE_HAL_TXPE_TOWI_CFG_TOWI_DMA_THRESHOLD(val) vBIT(val, 56, 8) 4249 u8 unused04410[0x04410 - 0x04408]; 4250 4251/* 0x04410 */ u64 txpe_pmon; 4252#define VXGE_HAL_TXPE_PMON_GO mBIT(15) 4253#define VXGE_HAL_TXPE_PMON_SAMPLE_PERIOD(val) vBIT(val, 16, 48) 4254/* 0x04418 */ u64 txpe_pmon_downcount; 4255#define VXGE_HAL_TXPE_PMON_DOWNCOUNT_TXPE_REMAINDER(val) vBIT(val, 16, 48) 4256/* 0x04420 */ u64 txpe_pmon_event; 4257#define VXGE_HAL_TXPE_PMON_EVENT_TXPE_STALL_CNT(val) vBIT(val, 16, 48) 4258/* 0x04428 */ u64 txpe_pmon_other; 4259#define VXGE_HAL_TXPE_PMON_OTHER_TXPE_STALL_CNT(val) vBIT(val, 16, 48) 4260 u8 unused04500[0x04500 - 0x04430]; 4261 4262/* 0x04500 */ u64 oes_inevt; 4263#define VXGE_HAL_OES_INEVT_PRIORITY_0(val) vBIT(val, 5, 3) 4264#define VXGE_HAL_OES_INEVT_PRIORITY_1(val) vBIT(val, 13, 3) 4265#define VXGE_HAL_OES_INEVT_PRIORITY_2(val) vBIT(val, 21, 3) 4266#define VXGE_HAL_OES_INEVT_PRIORITY_3(val) vBIT(val, 29, 3) 4267#define VXGE_HAL_OES_INEVT_PRIORITY_4(val) vBIT(val, 37, 3) 4268#define VXGE_HAL_OES_INEVT_CFG_SP_WRR mBIT(63) 4269/* 0x04508 */ u64 oes_inbkbkevt; 4270#define VXGE_HAL_OES_INBKBKEVT_PRIORITY_0(val) vBIT(val, 5, 3) 4271#define VXGE_HAL_OES_INBKBKEVT_PRIORITY_1(val) vBIT(val, 13, 3) 4272#define VXGE_HAL_OES_INBKBKEVT_PRIORITY_2(val) vBIT(val, 21, 3) 4273#define VXGE_HAL_OES_INBKBKEVT_PRIORITY_3(val) vBIT(val, 29, 3) 4274#define VXGE_HAL_OES_INBKBKEVT_PRIORITY_4(val) vBIT(val, 37, 3) 4275/* 0x04510 */ u64 oes_inevt_wrr0; 4276#define VXGE_HAL_OES_INEVT_WRR0_SS_0(val) vBIT(val, 5, 3) 4277#define VXGE_HAL_OES_INEVT_WRR0_SS_1(val) vBIT(val, 13, 3) 4278#define VXGE_HAL_OES_INEVT_WRR0_SS_2(val) vBIT(val, 21, 3) 4279#define VXGE_HAL_OES_INEVT_WRR0_SS_3(val) vBIT(val, 29, 3) 4280#define VXGE_HAL_OES_INEVT_WRR0_SS_4(val) vBIT(val, 37, 3) 4281#define VXGE_HAL_OES_INEVT_WRR0_SS_5(val) vBIT(val, 45, 3) 4282#define VXGE_HAL_OES_INEVT_WRR0_SS_6(val) vBIT(val, 53, 3) 4283#define VXGE_HAL_OES_INEVT_WRR0_SS_7(val) vBIT(val, 61, 3) 4284/* 0x04518 */ u64 oes_inevt_wrr1; 4285#define VXGE_HAL_OES_INEVT_WRR1_SS_8(val) vBIT(val, 5, 3) 4286#define VXGE_HAL_OES_INEVT_WRR1_SS_9(val) vBIT(val, 13, 3) 4287#define VXGE_HAL_OES_INEVT_WRR1_SS_10(val) vBIT(val, 21, 3) 4288#define VXGE_HAL_OES_INEVT_WRR1_SS_11(val) vBIT(val, 29, 3) 4289#define VXGE_HAL_OES_INEVT_WRR1_SS_12(val) vBIT(val, 37, 3) 4290#define VXGE_HAL_OES_INEVT_WRR1_SS_13(val) vBIT(val, 45, 3) 4291#define VXGE_HAL_OES_INEVT_WRR1_SS_14(val) vBIT(val, 53, 3) 4292/* 0x04520 */ u64 oes_pendevt; 4293#define VXGE_HAL_OES_PENDEVT_PRIORITY_0(val) vBIT(val, 5, 3) 4294#define VXGE_HAL_OES_PENDEVT_PRIORITY_1(val) vBIT(val, 13, 3) 4295#define VXGE_HAL_OES_PENDEVT_PRIORITY_2(val) vBIT(val, 21, 3) 4296#define VXGE_HAL_OES_PENDEVT_PRIORITY_3(val) vBIT(val, 29, 3) 4297#define VXGE_HAL_OES_PENDEVT_PRIORITY_4(val) vBIT(val, 37, 3) 4298#define VXGE_HAL_OES_PENDEVT_CFG_SP_WRR mBIT(63) 4299/* 0x04528 */ u64 oes_pendbkbkevt; 4300#define VXGE_HAL_OES_PENDBKBKEVT_PRIORITY_0(val) vBIT(val, 5, 3) 4301#define VXGE_HAL_OES_PENDBKBKEVT_PRIORITY_1(val) vBIT(val, 13, 3) 4302#define VXGE_HAL_OES_PENDBKBKEVT_PRIORITY_2(val) vBIT(val, 21, 3) 4303#define VXGE_HAL_OES_PENDBKBKEVT_PRIORITY_3(val) vBIT(val, 29, 3) 4304#define VXGE_HAL_OES_PENDBKBKEVT_PRIORITY_4(val) vBIT(val, 37, 3) 4305/* 0x04530 */ u64 oes_pendevt_wrr0; 4306#define VXGE_HAL_OES_PENDEVT_WRR0_SS_0(val) vBIT(val, 5, 3) 4307#define VXGE_HAL_OES_PENDEVT_WRR0_SS_1(val) vBIT(val, 13, 3) 4308#define VXGE_HAL_OES_PENDEVT_WRR0_SS_2(val) vBIT(val, 21, 3) 4309#define VXGE_HAL_OES_PENDEVT_WRR0_SS_3(val) vBIT(val, 29, 3) 4310#define VXGE_HAL_OES_PENDEVT_WRR0_SS_4(val) vBIT(val, 37, 3) 4311#define VXGE_HAL_OES_PENDEVT_WRR0_SS_5(val) vBIT(val, 45, 3) 4312#define VXGE_HAL_OES_PENDEVT_WRR0_SS_6(val) vBIT(val, 53, 3) 4313#define VXGE_HAL_OES_PENDEVT_WRR0_SS_7(val) vBIT(val, 61, 3) 4314/* 0x04538 */ u64 oes_pendevt_wrr1; 4315#define VXGE_HAL_OES_PENDEVT_WRR1_SS_8(val) vBIT(val, 5, 3) 4316#define VXGE_HAL_OES_PENDEVT_WRR1_SS_9(val) vBIT(val, 13, 3) 4317#define VXGE_HAL_OES_PENDEVT_WRR1_SS_10(val) vBIT(val, 21, 3) 4318#define VXGE_HAL_OES_PENDEVT_WRR1_SS_11(val) vBIT(val, 29, 3) 4319#define VXGE_HAL_OES_PENDEVT_WRR1_SS_12(val) vBIT(val, 37, 3) 4320#define VXGE_HAL_OES_PENDEVT_WRR1_SS_13(val) vBIT(val, 45, 3) 4321#define VXGE_HAL_OES_PENDEVT_WRR1_SS_14(val) vBIT(val, 53, 3) 4322/* 0x04540 */ u64 oes_pend_queue; 4323#define VXGE_HAL_OES_PEND_QUEUE_RX_PEND_THRESHOLD(val) vBIT(val, 27, 5) 4324#define VXGE_HAL_OES_PEND_QUEUE_TX_PEND_THRESHOLD(val) vBIT(val, 57, 7) 4325 u8 unused04800[0x04800 - 0x04548]; 4326 4327/* 0x04800 */ u64 rocrc_bypq0_stat_watermark; 4328#define VXGE_HAL_ROCRC_BYPQ0_STAT_WATERMARK_RCQ_ROCRC_BYPQ0_STAT_WATERMARK(val)\ 4329 vBIT(val, 11, 22) 4330/* 0x04808 */ u64 rocrc_bypq1_stat_watermark; 4331#define VXGE_HAL_ROCRC_BYPQ1_STAT_WATERMARK_RCQ_ROCRC_BYPQ1_STAT_WATERMARK(val)\ 4332 vBIT(val, 11, 22) 4333/* 0x04810 */ u64 rocrc_bypq2_stat_watermark; 4334#define VXGE_HAL_ROCRC_BYPQ2_STAT_WATERMARK_RCQ_ROCRC_BYPQ2_STAT_WATERMARK(val)\ 4335 vBIT(val, 11, 22) 4336/* 0x04818 */ u64 noa_wct_ctrl; 4337#define VXGE_HAL_NOA_WCT_CTRL_VP_INT_NUM mBIT(0) 4338/* 0x04820 */ u64 rc_cfg2; 4339#define VXGE_HAL_RC_CFG2_BUFF1_SIZE(val) vBIT(val, 0, 16) 4340#define VXGE_HAL_RC_CFG2_BUFF2_SIZE(val) vBIT(val, 16, 16) 4341#define VXGE_HAL_RC_CFG2_BUFF3_SIZE(val) vBIT(val, 32, 16) 4342#define VXGE_HAL_RC_CFG2_BUFF4_SIZE(val) vBIT(val, 48, 16) 4343/* 0x04828 */ u64 rc_cfg3; 4344#define VXGE_HAL_RC_CFG3_BUFF5_SIZE(val) vBIT(val, 0, 16) 4345/* 0x04830 */ u64 rx_multi_cast_ctrl1; 4346#define VXGE_HAL_RX_MULTI_CAST_CTRL1_ENABLE mBIT(7) 4347#define VXGE_HAL_RX_MULTI_CAST_CTRL1_DELAY_COUNT(val) vBIT(val, 11, 5) 4348/* 0x04838 */ u64 rxdm_dbg_rd; 4349#define VXGE_HAL_RXDM_DBG_RD_ADDR(val) vBIT(val, 0, 12) 4350#define VXGE_HAL_RXDM_DBG_RD_ENABLE mBIT(31) 4351/* 0x04840 */ u64 rxdm_dbg_rd_data; 4352#define VXGE_HAL_RXDM_DBG_RD_DATA_RMC_RXDM_DBG_RD_DATA(val) vBIT(val, 0, 64) 4353/* 0x04848 */ u64 rqa_top_prty_for_vh[17]; 4354#define VXGE_HAL_RQA_TOP_PRTY_FOR_VH_RQA_TOP_PRTY_FOR_VH(val) vBIT(val, 59, 5) 4355 u8 unused04900[0x04900 - 0x048d0]; 4356 4357/* 0x04900 */ u64 tim_status; 4358#define VXGE_HAL_TIM_STATUS_TIM_RESET_IN_PROGRESS mBIT(0) 4359/* 0x04908 */ u64 tim_ecc_enable; 4360#define VXGE_HAL_TIM_ECC_ENABLE_VBLS_N mBIT(7) 4361#define VXGE_HAL_TIM_ECC_ENABLE_BMAP_N mBIT(15) 4362#define VXGE_HAL_TIM_ECC_ENABLE_BMAP_MSG_N mBIT(23) 4363/* 0x04910 */ u64 tim_bp_ctrl; 4364#define VXGE_HAL_TIM_BP_CTRL_RD_XON mBIT(7) 4365#define VXGE_HAL_TIM_BP_CTRL_WR_XON mBIT(15) 4366#define VXGE_HAL_TIM_BP_CTRL_ROCRC_BYP mBIT(23) 4367/* 0x04918 */ u64 tim_resource_assignment_vh[17]; 4368#define VXGE_HAL_TIM_RESOURCE_ASSIGNMENT_VH_BMAP_ROOT(val) vBIT(val, 0, 32) 4369/* 0x049a0 */ u64 tim_bmap_mapping_vp_err[17]; 4370#define VXGE_HAL_TIM_BMAP_MAPPING_VP_ERR_TIM_DEST_VPATH(val) vBIT(val, 3, 5) 4371 u8 unused04b00[0x04b00 - 0x04a28]; 4372 4373/* 0x04b00 */ u64 gcmg2_int_status; 4374#define VXGE_HAL_GCMG2_INT_STATUS_GXTMC_ERR_GXTMC_INT mBIT(7) 4375#define VXGE_HAL_GCMG2_INT_STATUS_GCP_ERR_GCP_INT mBIT(15) 4376#define VXGE_HAL_GCMG2_INT_STATUS_CMC_ERR_CMC_INT mBIT(23) 4377/* 0x04b08 */ u64 gcmg2_int_mask; 4378/* 0x04b10 */ u64 gxtmc_err_reg; 4379#define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_MEM_DB_ERR(val) vBIT(val, 0, 4) 4380#define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_MEM_SG_ERR(val) vBIT(val, 4, 4) 4381#define VXGE_HAL_GXTMC_ERR_REG_XTMC_CMC_RD_DATA_DB_ERR mBIT(8) 4382#define VXGE_HAL_GXTMC_ERR_REG_XTMC_REQ_FIFO_ERR mBIT(9) 4383#define VXGE_HAL_GXTMC_ERR_REG_XTMC_REQ_DATA_FIFO_ERR mBIT(10) 4384#define VXGE_HAL_GXTMC_ERR_REG_XTMC_WR_RSP_FIFO_ERR mBIT(11) 4385#define VXGE_HAL_GXTMC_ERR_REG_XTMC_RD_RSP_FIFO_ERR mBIT(12) 4386#define VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_WRP_FIFO_ERR mBIT(13) 4387#define VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_WRP_ERR mBIT(14) 4388#define VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_RRP_FIFO_ERR mBIT(15) 4389#define VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_RRP_ERR mBIT(16) 4390#define VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_DATA_SM_ERR mBIT(17) 4391#define VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_CMC0_IF_ERR mBIT(18) 4392#define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_ARB_SM_ERR mBIT(19) 4393#define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_CFC_SM_ERR mBIT(20) 4394#define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_CREDIT_OVERFLOW mBIT(21) 4395#define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_CREDIT_UNDERFLOW mBIT(22) 4396#define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_SM_ERR mBIT(23) 4397#define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_CREDIT_OVERFLOW mBIT(24) 4398#define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_CREDIT_UNDERFLOW mBIT(25) 4399#define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_SM_ERR mBIT(26) 4400#define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_WCOMPL_SM_ERR mBIT(27) 4401#define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_WCOMPL_TAG_ERR mBIT(28) 4402#define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_WREQ_SM_ERR mBIT(29) 4403#define VXGE_HAL_GXTMC_ERR_REG_XTMC_BDT_CMI_WREQ_FIFO_ERR mBIT(30) 4404#define VXGE_HAL_GXTMC_ERR_REG_XTMC_CP2BDT_RFIFO_POP_ERR mBIT(31) 4405#define VXGE_HAL_GXTMC_ERR_REG_XTMC_XTMC_BDT_CMI_OP_ERR mBIT(32) 4406#define VXGE_HAL_GXTMC_ERR_REG_XTMC_XTMC_BDT_DFETCH_OP_ERR mBIT(33) 4407#define VXGE_HAL_GXTMC_ERR_REG_XTMC_XTMC_BDT_DFIFO_ERR mBIT(34) 4408#define VXGE_HAL_GXTMC_ERR_REG_XTMC_CMI_ARB_SM_ERR mBIT(35) 4409/* 0x04b18 */ u64 gxtmc_err_mask; 4410/* 0x04b20 */ u64 gxtmc_err_alarm; 4411/* 0x04b28 */ u64 cmc_err_reg; 4412#define VXGE_HAL_CMC_ERR_REG_CMC_CMC_SM_ERR mBIT(0) 4413/* 0x04b30 */ u64 cmc_err_mask; 4414/* 0x04b38 */ u64 cmc_err_alarm; 4415/* 0x04b40 */ u64 gcp_err_reg; 4416#define VXGE_HAL_GCP_ERR_REG_CP_H2L2CP_FIFO_ERR mBIT(0) 4417#define VXGE_HAL_GCP_ERR_REG_CP_STC2CP_FIFO_ERR mBIT(1) 4418#define VXGE_HAL_GCP_ERR_REG_CP_STE2CP_FIFO_ERR mBIT(2) 4419#define VXGE_HAL_GCP_ERR_REG_CP_TTE2CP_FIFO_ERR mBIT(3) 4420/* 0x04b48 */ u64 gcp_err_mask; 4421/* 0x04b50 */ u64 gcp_err_alarm; 4422/* 0x04b58 */ u64 cmc_l2_client_uqm_1; 4423#define VXGE_HAL_CMC_L2_CLIENT_UQM_1_NUMBER(val) vBIT(val, 5, 3) 4424/* 0x04b60 */ u64 cmc_l2_client_ssc_l; 4425#define VXGE_HAL_CMC_L2_CLIENT_SSC_L_NUMBER(val) vBIT(val, 5, 3) 4426/* 0x04b68 */ u64 cmc_l2_client_qcc_sqm_0; 4427#define VXGE_HAL_CMC_L2_CLIENT_QCC_SQM_0_NUMBER(val) vBIT(val, 5, 3) 4428/* 0x04b70 */ u64 cmc_l2_client_dam_0; 4429#define VXGE_HAL_CMC_L2_CLIENT_DAM_0_NUMBER(val) vBIT(val, 5, 3) 4430/* 0x04b78 */ u64 cmc_l2_client_h2l_0; 4431#define VXGE_HAL_CMC_L2_CLIENT_H2L_0_NUMBER(val) vBIT(val, 5, 3) 4432/* 0x04b80 */ u64 cmc_l2_client_stc_0; 4433#define VXGE_HAL_CMC_L2_CLIENT_STC_0_NUMBER(val) vBIT(val, 5, 3) 4434/* 0x04b88 */ u64 cmc_l2_client_xtmc_0; 4435#define VXGE_HAL_CMC_L2_CLIENT_XTMC_0_NUMBER(val) vBIT(val, 5, 3) 4436/* 0x04b90 */ u64 cmc_wrr_l2_calendar_0; 4437#define VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_0(val) vBIT(val, 5, 3) 4438#define VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_1(val) vBIT(val, 13, 3) 4439#define VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_2(val) vBIT(val, 21, 3) 4440#define VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_3(val) vBIT(val, 29, 3) 4441#define VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_4(val) vBIT(val, 37, 3) 4442#define VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_5(val) vBIT(val, 45, 3) 4443#define VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_6(val) vBIT(val, 53, 3) 4444#define VXGE_HAL_CMC_WRR_L2_CALENDAR_0_NUMBER_7(val) vBIT(val, 61, 3) 4445/* 0x04b98 */ u64 cmc_wrr_l2_calendar_1; 4446#define VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_8(val) vBIT(val, 5, 3) 4447#define VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_9(val) vBIT(val, 13, 3) 4448#define VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_10(val) vBIT(val, 21, 3) 4449#define VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_11(val) vBIT(val, 29, 3) 4450#define VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_12(val) vBIT(val, 37, 3) 4451#define VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_13(val) vBIT(val, 45, 3) 4452#define VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_14(val) vBIT(val, 53, 3) 4453#define VXGE_HAL_CMC_WRR_L2_CALENDAR_1_NUMBER_15(val) vBIT(val, 61, 3) 4454/* 0x04ba0 */ u64 cmc_wrr_l2_calendar_2; 4455#define VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_16(val) vBIT(val, 5, 3) 4456#define VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_17(val) vBIT(val, 13, 3) 4457#define VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_18(val) vBIT(val, 21, 3) 4458#define VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_19(val) vBIT(val, 29, 3) 4459#define VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_20(val) vBIT(val, 37, 3) 4460#define VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_21(val) vBIT(val, 45, 3) 4461#define VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_22(val) vBIT(val, 53, 3) 4462#define VXGE_HAL_CMC_WRR_L2_CALENDAR_2_NUMBER_23(val) vBIT(val, 61, 3) 4463/* 0x04ba8 */ u64 cmc_wrr_l2_calendar_3; 4464#define VXGE_HAL_CMC_WRR_L2_CALENDAR_3_NUMBER_24(val) vBIT(val, 5, 3) 4465#define VXGE_HAL_CMC_WRR_L2_CALENDAR_3_NUMBER_25(val) vBIT(val, 13, 3) 4466#define VXGE_HAL_CMC_WRR_L2_CALENDAR_3_NUMBER_26(val) vBIT(val, 21, 3) 4467#define VXGE_HAL_CMC_WRR_L2_CALENDAR_3_NUMBER_27(val) vBIT(val, 29, 3) 4468/* 0x04bb0 */ u64 cmc_l3_client_qcc_sqm_1; 4469#define VXGE_HAL_CMC_L3_CLIENT_QCC_SQM_1_NUMBER(val) vBIT(val, 5, 3) 4470/* 0x04bb8 */ u64 cmc_l3_client_qcc_cqm; 4471#define VXGE_HAL_CMC_L3_CLIENT_QCC_CQM_NUMBER(val) vBIT(val, 5, 3) 4472/* 0x04bc0 */ u64 cmc_l3_client_dam_1; 4473#define VXGE_HAL_CMC_L3_CLIENT_DAM_1_NUMBER(val) vBIT(val, 5, 3) 4474/* 0x04bc8 */ u64 cmc_l3_client_h2l_1; 4475#define VXGE_HAL_CMC_L3_CLIENT_H2L_1_NUMBER(val) vBIT(val, 5, 3) 4476/* 0x04bd0 */ u64 cmc_l3_client_stc_1; 4477#define VXGE_HAL_CMC_L3_CLIENT_STC_1_NUMBER(val) vBIT(val, 5, 3) 4478/* 0x04bd8 */ u64 cmc_l3_client_xtmc_1; 4479#define VXGE_HAL_CMC_L3_CLIENT_XTMC_1_NUMBER(val) vBIT(val, 5, 3) 4480/* 0x04be0 */ u64 cmc_wrr_l3_calendar_0; 4481#define VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_0(val) vBIT(val, 5, 3) 4482#define VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_1(val) vBIT(val, 13, 3) 4483#define VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_2(val) vBIT(val, 21, 3) 4484#define VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_3(val) vBIT(val, 29, 3) 4485#define VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_4(val) vBIT(val, 37, 3) 4486#define VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_5(val) vBIT(val, 45, 3) 4487#define VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_6(val) vBIT(val, 53, 3) 4488#define VXGE_HAL_CMC_WRR_L3_CALENDAR_0_NUMBER_7(val) vBIT(val, 61, 3) 4489/* 0x04be8 */ u64 cmc_wrr_l3_calendar_1; 4490#define VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_8(val) vBIT(val, 5, 3) 4491#define VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_9(val) vBIT(val, 13, 3) 4492#define VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_10(val) vBIT(val, 21, 3) 4493#define VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_11(val) vBIT(val, 29, 3) 4494#define VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_12(val) vBIT(val, 37, 3) 4495#define VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_13(val) vBIT(val, 45, 3) 4496#define VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_14(val) vBIT(val, 53, 3) 4497#define VXGE_HAL_CMC_WRR_L3_CALENDAR_1_NUMBER_15(val) vBIT(val, 61, 3) 4498/* 0x04bf0 */ u64 cmc_wrr_l3_calendar_2; 4499#define VXGE_HAL_CMC_WRR_L3_CALENDAR_2_NUMBER_16(val) vBIT(val, 5, 3) 4500#define VXGE_HAL_CMC_WRR_L3_CALENDAR_2_NUMBER_17(val) vBIT(val, 13, 3) 4501#define VXGE_HAL_CMC_WRR_L3_CALENDAR_2_NUMBER_18(val) vBIT(val, 21, 3) 4502#define VXGE_HAL_CMC_WRR_L3_CALENDAR_2_NUMBER_19(val) vBIT(val, 29, 3) 4503#define VXGE_HAL_CMC_WRR_L3_CALENDAR_2_NUMBER_20(val) vBIT(val, 37, 3) 4504/* 0x04bf8 */ u64 cmc_user_doorbell_partition; 4505#define VXGE_HAL_CMC_USER_DOORBELL_PARTITION_BASE(val) vBIT(val, 8, 24) 4506/* 0x04c00 */ u64 cmc_hit_record_partition_0; 4507#define VXGE_HAL_CMC_HIT_RECORD_PARTITION_0_BASE(val) vBIT(val, 8, 24) 4508/* 0x04c08 */ u64 cmc_hit_record_partition_1; 4509#define VXGE_HAL_CMC_HIT_RECORD_PARTITION_1_BASE(val) vBIT(val, 8, 24) 4510/* 0x04c10 */ u64 cmc_hit_record_partition_2; 4511#define VXGE_HAL_CMC_HIT_RECORD_PARTITION_2_BASE(val) vBIT(val, 8, 24) 4512/* 0x04c18 */ u64 cmc_hit_record_partition_3; 4513#define VXGE_HAL_CMC_HIT_RECORD_PARTITION_3_BASE(val) vBIT(val, 8, 24) 4514/* 0x04c20 */ u64 cmc_hit_record_partition_4; 4515#define VXGE_HAL_CMC_HIT_RECORD_PARTITION_4_BASE(val) vBIT(val, 8, 24) 4516/* 0x04c28 */ u64 cmc_hit_record_partition_5; 4517#define VXGE_HAL_CMC_HIT_RECORD_PARTITION_5_BASE(val) vBIT(val, 8, 24) 4518/* 0x04c30 */ u64 cmc_hit_record_partition_6; 4519#define VXGE_HAL_CMC_HIT_RECORD_PARTITION_6_BASE(val) vBIT(val, 8, 24) 4520/* 0x04c38 */ u64 cmc_hit_record_partition_7; 4521#define VXGE_HAL_CMC_HIT_RECORD_PARTITION_7_BASE(val) vBIT(val, 8, 24) 4522/* 0x04c40 */ u64 cmc_c_scr_record_partition_0; 4523#define VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_0_BASE(val) vBIT(val, 8, 24) 4524/* 0x04c48 */ u64 cmc_c_scr_record_partition_1; 4525#define VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_1_BASE(val) vBIT(val, 8, 24) 4526/* 0x04c50 */ u64 cmc_c_scr_record_partition_2; 4527#define VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_2_BASE(val) vBIT(val, 8, 24) 4528/* 0x04c58 */ u64 cmc_c_scr_record_partition_3; 4529#define VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_3_BASE(val) vBIT(val, 8, 24) 4530/* 0x04c60 */ u64 cmc_c_scr_record_partition_4; 4531#define VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_4_BASE(val) vBIT(val, 8, 24) 4532/* 0x04c68 */ u64 cmc_c_scr_record_partition_5; 4533#define VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_5_BASE(val) vBIT(val, 8, 24) 4534/* 0x04c70 */ u64 cmc_c_scr_record_partition_6; 4535#define VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_6_BASE(val) vBIT(val, 8, 24) 4536/* 0x04c78 */ u64 cmc_c_scr_record_partition_7; 4537#define VXGE_HAL_CMC_C_SCR_RECORD_PARTITION_7_BASE(val) vBIT(val, 8, 24) 4538/* 0x04c80 */ u64 cmc_wqe_od_group_record_partition; 4539#define VXGE_HAL_CMC_WQE_OD_GROUP_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) 4540/* 0x04c88 */ u64 cmc_ack_record_partition; 4541#define VXGE_HAL_CMC_ACK_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) 4542/* 0x04c90 */ u64 cmc_lirr_record_partition; 4543#define VXGE_HAL_CMC_LIRR_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) 4544/* 0x04c98 */ u64 cmc_rirr_record_partition; 4545#define VXGE_HAL_CMC_RIRR_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) 4546/* 0x04ca0 */ u64 cmc_tce_record_partition; 4547#define VXGE_HAL_CMC_TCE_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) 4548/* 0x04ca8 */ u64 cmc_hoq_record_partition; 4549#define VXGE_HAL_CMC_HOQ_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) 4550/* 0x04cb0 */ u64 cmc_stag_vp_record_partition[17]; 4551#define VXGE_HAL_CMC_STAG_VP_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) 4552/* 0x04d38 */ u64 cmc_r_scr_record_partition; 4553#define VXGE_HAL_CMC_R_SCR_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) 4554/* 0x04d40 */ u64 cmc_cqrq_context_record_partition; 4555#define VXGE_HAL_CMC_CQRQ_CONTEXT_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) 4556/* 0x04d48 */ u64 cmc_cqe_group_record_partition; 4557#define VXGE_HAL_CMC_CQE_GROUP_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) 4558/* 0x04d50 */ u64 cmc_p_scr_record_partition; 4559#define VXGE_HAL_CMC_P_SCR_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) 4560/* 0x04d58 */ u64 cmc_nce_context_record_partition; 4561#define VXGE_HAL_CMC_NCE_CONTEXT_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) 4562/* 0x04d60 */ u64 cmc_bypass_queue_partition; 4563#define VXGE_HAL_CMC_BYPASS_QUEUE_PARTITION_BASE(val) vBIT(val, 8, 24) 4564/* 0x04d68 */ u64 cmc_h_scr_record_partition; 4565#define VXGE_HAL_CMC_H_SCR_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) 4566/* 0x04d70 */ u64 cmc_pbl_record_partition; 4567#define VXGE_HAL_CMC_PBL_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) 4568/* 0x04d78 */ u64 cmc_lit_record_partition; 4569#define VXGE_HAL_CMC_LIT_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) 4570/* 0x04d80 */ u64 cmc_srq_context_record_partition; 4571#define VXGE_HAL_CMC_SRQ_CONTEXT_RECORD_PARTITION_BASE(val) vBIT(val, 8, 24) 4572/* 0x04d88 */ u64 cmc_p_scr_record; 4573#define VXGE_HAL_CMC_P_SCR_RECORD_SIZE(val) vBIT(val, 2, 6) 4574/* 0x04d90 */ u64 cmc_device_select; 4575#define VXGE_HAL_CMC_DEVICE_SELECT_CODE(val) vBIT(val, 5, 3) 4576/* 0x04d98 */ u64 g3if_fifo_dst_ecc; 4577#define VXGE_HAL_G3IF_FIFO_DST_ECC_ENABLE(val) vBIT(val, 3, 5) 4578/* 0x04da0 */ u64 gxtmc_cfg; 4579#define VXGE_HAL_GXTMC_CFG_CMC_PRI mBIT(7) 4580#define VXGE_HAL_GXTMC_CFG_GPSYNC_WAIT_TOKEN_ENABLE mBIT(13) 4581#define VXGE_HAL_GXTMC_CFG_GPSYNC_CNTDOWN_TIMER_ENABLE mBIT(14) 4582#define VXGE_HAL_GXTMC_CFG_GPSYNC_SRC_NOTIFY_ENABLE mBIT(15) 4583#define VXGE_HAL_GXTMC_CFG_GPSYNC_CNTDOWN_START_VALUE(val) vBIT(val, 20, 4) 4584#define VXGE_HAL_GXTMC_CFG_BDT_MEM_ECC_ENABLE_N mBIT(31) 4585 u8 unused04f00[0x04f00 - 0x04da8]; 4586 4587/* 0x04f00 */ u64 pcmg2_int_status; 4588#define VXGE_HAL_PCMG2_INT_STATUS_PXTMC_ERR_PXTMC_INT mBIT(7) 4589#define VXGE_HAL_PCMG2_INT_STATUS_CP_EXC_CP_XT_EXC_INT mBIT(15) 4590#define VXGE_HAL_PCMG2_INT_STATUS_CP_ERR_CP_ERR_INT mBIT(23) 4591/* 0x04f08 */ u64 pcmg2_int_mask; 4592/* 0x04f10 */ u64 pxtmc_err_reg; 4593#define VXGE_HAL_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_DB_ERR(val) vBIT(val, 0, 2) 4594#define VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_REQ_FIFO_ERR mBIT(2) 4595#define VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_PRSP_FIFO_ERR mBIT(3) 4596#define VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_WRSP_FIFO_ERR mBIT(4) 4597#define VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_REQ_FIFO_ERR mBIT(5) 4598#define VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_PRSP_FIFO_ERR mBIT(6) 4599#define VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_WRSP_FIFO_ERR mBIT(7) 4600#define VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_REQ_FIFO_ERR mBIT(8) 4601#define VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_PRSP_FIFO_ERR mBIT(9) 4602#define VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_WRSP_FIFO_ERR mBIT(10) 4603#define VXGE_HAL_PXTMC_ERR_REG_XTMC_REQ_FIFO_ERR mBIT(11) 4604#define VXGE_HAL_PXTMC_ERR_REG_XTMC_REQ_DATA_FIFO_ERR mBIT(12) 4605#define VXGE_HAL_PXTMC_ERR_REG_XTMC_WR_RSP_FIFO_ERR mBIT(13) 4606#define VXGE_HAL_PXTMC_ERR_REG_XTMC_RD_RSP_FIFO_ERR mBIT(14) 4607#define VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_REQ_SHADOW_ERR mBIT(15) 4608#define VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_RSP_SHADOW_ERR mBIT(16) 4609#define VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_REQ_SHADOW_ERR mBIT(17) 4610#define VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_RSP_SHADOW_ERR mBIT(18) 4611#define VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_REQ_SHADOW_ERR mBIT(19) 4612#define VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_RSP_SHADOW_ERR mBIT(20) 4613#define VXGE_HAL_PXTMC_ERR_REG_XTMC_XIL_SHADOW_ERR mBIT(21) 4614#define VXGE_HAL_PXTMC_ERR_REG_XTMC_ARB_SHADOW_ERR mBIT(22) 4615#define VXGE_HAL_PXTMC_ERR_REG_XTMC_RAM_SHADOW_ERR mBIT(23) 4616#define VXGE_HAL_PXTMC_ERR_REG_XTMC_CMW_SHADOW_ERR mBIT(24) 4617#define VXGE_HAL_PXTMC_ERR_REG_XTMC_CMR_SHADOW_ERR mBIT(25) 4618#define VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_REQ_FSM_ERR mBIT(26) 4619#define VXGE_HAL_PXTMC_ERR_REG_XTMC_MPT_RSP_FSM_ERR mBIT(27) 4620#define VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_REQ_FSM_ERR mBIT(28) 4621#define VXGE_HAL_PXTMC_ERR_REG_XTMC_UPT_RSP_FSM_ERR mBIT(29) 4622#define VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_REQ_FSM_ERR mBIT(30) 4623#define VXGE_HAL_PXTMC_ERR_REG_XTMC_CPT_RSP_FSM_ERR mBIT(31) 4624#define VXGE_HAL_PXTMC_ERR_REG_XTMC_XIL_FSM_ERR mBIT(32) 4625#define VXGE_HAL_PXTMC_ERR_REG_XTMC_ARB_FSM_ERR mBIT(33) 4626#define VXGE_HAL_PXTMC_ERR_REG_XTMC_CMW_FSM_ERR mBIT(34) 4627#define VXGE_HAL_PXTMC_ERR_REG_XTMC_CMR_FSM_ERR mBIT(35) 4628#define VXGE_HAL_PXTMC_ERR_REG_XTMC_MXP_RD_PROT_ERR mBIT(36) 4629#define VXGE_HAL_PXTMC_ERR_REG_XTMC_UXP_RD_PROT_ERR mBIT(37) 4630#define VXGE_HAL_PXTMC_ERR_REG_XTMC_CXP_RD_PROT_ERR mBIT(38) 4631#define VXGE_HAL_PXTMC_ERR_REG_XTMC_MXP_WR_PROT_ERR mBIT(39) 4632#define VXGE_HAL_PXTMC_ERR_REG_XTMC_UXP_WR_PROT_ERR mBIT(40) 4633#define VXGE_HAL_PXTMC_ERR_REG_XTMC_CXP_WR_PROT_ERR mBIT(41) 4634#define VXGE_HAL_PXTMC_ERR_REG_XTMC_MXP_INV_ADDR_ERR mBIT(42) 4635#define VXGE_HAL_PXTMC_ERR_REG_XTMC_UXP_INV_ADDR_ERR mBIT(43) 4636#define VXGE_HAL_PXTMC_ERR_REG_XTMC_CXP_INV_ADDR_ERR mBIT(44) 4637#define VXGE_HAL_PXTMC_ERR_REG_XTMC_MXP_RD_PROT_INFO_ERR mBIT(45) 4638#define VXGE_HAL_PXTMC_ERR_REG_XTMC_UXP_RD_PROT_INFO_ERR mBIT(46) 4639#define VXGE_HAL_PXTMC_ERR_REG_XTMC_CXP_RD_PROT_INFO_ERR mBIT(47) 4640#define VXGE_HAL_PXTMC_ERR_REG_XTMC_MXP_WR_PROT_INFO_ERR mBIT(48) 4641#define VXGE_HAL_PXTMC_ERR_REG_XTMC_UXP_WR_PROT_INFO_ERR mBIT(49) 4642#define VXGE_HAL_PXTMC_ERR_REG_XTMC_CXP_WR_PROT_INFO_ERR mBIT(50) 4643#define VXGE_HAL_PXTMC_ERR_REG_XTMC_MXP_INV_ADDR_INFO_ERR mBIT(51) 4644#define VXGE_HAL_PXTMC_ERR_REG_XTMC_UXP_INV_ADDR_INFO_ERR mBIT(52) 4645#define VXGE_HAL_PXTMC_ERR_REG_XTMC_CXP_INV_ADDR_INFO_ERR mBIT(53) 4646#define VXGE_HAL_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_SG_ERR(val) vBIT(val, 54, 2) 4647#define VXGE_HAL_PXTMC_ERR_REG_XTMC_CP2BDT_DFIFO_PUSH_ERR mBIT(56) 4648#define VXGE_HAL_PXTMC_ERR_REG_XTMC_CP2BDT_RFIFO_PUSH_ERR mBIT(57) 4649/* 0x04f18 */ u64 pxtmc_err_mask; 4650/* 0x04f20 */ u64 pxtmc_err_alarm; 4651/* 0x04f28 */ u64 cp_err_reg; 4652#define VXGE_HAL_CP_ERR_REG_CP_CP_DCACHE_SG_ERR(val) vBIT(val, 0, 8) 4653#define VXGE_HAL_CP_ERR_REG_CP_CP_ICACHE_SG_ERR(val) vBIT(val, 8, 2) 4654#define VXGE_HAL_CP_ERR_REG_CP_CP_DTAG_SG_ERR mBIT(10) 4655#define VXGE_HAL_CP_ERR_REG_CP_CP_ITAG_SG_ERR mBIT(11) 4656#define VXGE_HAL_CP_ERR_REG_CP_CP_TRACE_SG_ERR mBIT(12) 4657#define VXGE_HAL_CP_ERR_REG_CP_DMA2CP_SG_ERR mBIT(13) 4658#define VXGE_HAL_CP_ERR_REG_CP_MP2CP_SG_ERR mBIT(14) 4659#define VXGE_HAL_CP_ERR_REG_CP_QCC2CP_SG_ERR mBIT(15) 4660#define VXGE_HAL_CP_ERR_REG_CP_STC2CP_SG_ERR(val) vBIT(val, 16, 2) 4661#define VXGE_HAL_CP_ERR_REG_CP_CP_DCACHE_DB_ERR(val) vBIT(val, 24, 8) 4662#define VXGE_HAL_CP_ERR_REG_CP_CP_ICACHE_DB_ERR(val) vBIT(val, 32, 2) 4663#define VXGE_HAL_CP_ERR_REG_CP_CP_DTAG_DB_ERR mBIT(34) 4664#define VXGE_HAL_CP_ERR_REG_CP_CP_ITAG_DB_ERR mBIT(35) 4665#define VXGE_HAL_CP_ERR_REG_CP_CP_TRACE_DB_ERR mBIT(36) 4666#define VXGE_HAL_CP_ERR_REG_CP_DMA2CP_DB_ERR mBIT(37) 4667#define VXGE_HAL_CP_ERR_REG_CP_MP2CP_DB_ERR mBIT(38) 4668#define VXGE_HAL_CP_ERR_REG_CP_QCC2CP_DB_ERR mBIT(39) 4669#define VXGE_HAL_CP_ERR_REG_CP_STC2CP_DB_ERR(val) vBIT(val, 40, 2) 4670#define VXGE_HAL_CP_ERR_REG_CP_H2L2CP_FIFO_ERR mBIT(48) 4671#define VXGE_HAL_CP_ERR_REG_CP_STC2CP_FIFO_ERR mBIT(49) 4672#define VXGE_HAL_CP_ERR_REG_CP_STE2CP_FIFO_ERR mBIT(50) 4673#define VXGE_HAL_CP_ERR_REG_CP_TTE2CP_FIFO_ERR mBIT(51) 4674#define VXGE_HAL_CP_ERR_REG_CP_SWIF2CP_FIFO_ERR mBIT(52) 4675#define VXGE_HAL_CP_ERR_REG_CP_CP2DMA_FIFO_ERR mBIT(53) 4676#define VXGE_HAL_CP_ERR_REG_CP_DAM2CP_FIFO_ERR mBIT(54) 4677#define VXGE_HAL_CP_ERR_REG_CP_MP2CP_FIFO_ERR mBIT(55) 4678#define VXGE_HAL_CP_ERR_REG_CP_QCC2CP_FIFO_ERR mBIT(56) 4679#define VXGE_HAL_CP_ERR_REG_CP_DMA2CP_FIFO_ERR mBIT(57) 4680#define VXGE_HAL_CP_ERR_REG_CP_CP_WAKE_FSM_INTEGRITY_ERR mBIT(60) 4681#define VXGE_HAL_CP_ERR_REG_CP_CP_PMON_FSM_INTEGRITY_ERR mBIT(61) 4682#define VXGE_HAL_CP_ERR_REG_CP_DMA_RD_SHADOW_ERR mBIT(62) 4683#define VXGE_HAL_CP_ERR_REG_CP_PIFT_CREDIT_ERR mBIT(63) 4684/* 0x04f30 */ u64 cp_err_mask; 4685/* 0x04f38 */ u64 cp_err_alarm; 4686/* 0x04f40 */ u64 cp_xt_ctrl1; 4687#define VXGE_HAL_CP_XT_CTRL1_CP_WAKEUP mBIT(47) 4688#define VXGE_HAL_CP_XT_CTRL1_CP_RUNSTALL mBIT(55) 4689#define VXGE_HAL_CP_XT_CTRL1_CP_BRESET mBIT(63) 4690/* 0x04f48 */ u64 cp_gen_cfg; 4691#define VXGE_HAL_CP_GEN_CFG_MULT_DMA_RD_REQ_ENA mBIT(7) 4692#define VXGE_HAL_CP_GEN_CFG_DMA_RD_PER_VPLANE_CHK_ENA mBIT(15) 4693#define VXGE_HAL_CP_GEN_CFG_DMA_RD_XON_CHK_ENA mBIT(23) 4694#define VXGE_HAL_CP_GEN_CFG_CAUSE_INT_IS_CRITICAL mBIT(31) 4695/* 0x04f50 */ u64 cp_exc_reg; 4696#define VXGE_HAL_CP_EXC_REG_CP_CP_CAUSE_INFO_INT mBIT(47) 4697#define VXGE_HAL_CP_EXC_REG_CP_CP_CAUSE_CRIT_INT mBIT(55) 4698#define VXGE_HAL_CP_EXC_REG_CP_CP_SERR mBIT(63) 4699/* 0x04f58 */ u64 cp_exc_mask; 4700/* 0x04f60 */ u64 cp_exc_alarm; 4701/* 0x04f68 */ u64 cp_exc_cause; 4702#define VXGE_HAL_CP_EXC_CAUSE_CP_CP_CAUSE(val) vBIT(val, 32, 32) 4703 u8 unused04fe8[0x04fe8 - 0x04f70]; 4704 4705/* 0x04fe8 */ u64 xtmc_img_ctrl0; 4706#define VXGE_HAL_XTMC_IMG_CTRL0_LD_BANK_DEPTH(val) vBIT(val, 5, 3) 4707#define VXGE_HAL_XTMC_IMG_CTRL0_ENABLE_GO mBIT(15) 4708#define VXGE_HAL_XTMC_IMG_CTRL0_IMG_LD_COMPLETE mBIT(23) 4709#define VXGE_HAL_XTMC_IMG_CTRL0_LAST_DATA mBIT(31) 4710#define VXGE_HAL_XTMC_IMG_CTRL0_ADDR(val) vBIT(val, 40, 24) 4711/* 0x04ff0 */ u64 xtmc_img_ctrl1; 4712#define VXGE_HAL_XTMC_IMG_CTRL1_DATA(val) vBIT(val, 0, 64) 4713/* 0x04ff8 */ u64 xtmc_img_ctrl2; 4714#define VXGE_HAL_XTMC_IMG_CTRL2_XTMC_LD_BANK_AVAIL mBIT(63) 4715/* 0x05000 */ u64 xtmc_img_ctrl3; 4716#define VXGE_HAL_XTMC_IMG_CTRL3_XTMC_ALL_DATA_WRITTEN mBIT(63) 4717/* 0x05008 */ u64 xtmc_img_ctrl4; 4718#define VXGE_HAL_XTMC_IMG_CTRL4_GO mBIT(63) 4719/* 0x05010 */ u64 pxtmc_cfg0; 4720#define VXGE_HAL_PXTMC_CFG0_XT_PIF_SRAM_ECC_ENABLE_N mBIT(3) 4721#define VXGE_HAL_PXTMC_CFG0_XT_PIF_SRAM_PHASE_ENA mBIT(7) 4722#define VXGE_HAL_PXTMC_CFG0_MXP_RD_PROT_ENA mBIT(11) 4723#define VXGE_HAL_PXTMC_CFG0_MXP_WR_PROT_ENA mBIT(15) 4724#define VXGE_HAL_PXTMC_CFG0_UXP_RD_PROT_ENA mBIT(19) 4725#define VXGE_HAL_PXTMC_CFG0_UXP_WR_PROT_ENA mBIT(23) 4726#define VXGE_HAL_PXTMC_CFG0_CXP_RD_PROT_ENA mBIT(27) 4727#define VXGE_HAL_PXTMC_CFG0_CXP_WR_PROT_ENA mBIT(31) 4728#define VXGE_HAL_PXTMC_CFG0_INVALID_ADDR_CHECK_ENA mBIT(39) 4729#define VXGE_HAL_PXTMC_CFG0_SUPPRESS_RD_ON_ADDR_ERR mBIT(43) 4730#define VXGE_HAL_PXTMC_CFG0_SUPPRESS_WR_ON_ADDR_ERR mBIT(47) 4731#define VXGE_HAL_PXTMC_CFG0_ARB_DURING_4BYTE_WR_ENA mBIT(55) 4732/* 0x05018 */ u64 pxtmc_cfg1; 4733#define VXGE_HAL_PXTMC_CFG1_MAX_NBR_MXP_EVENTS(val) vBIT(val, 6, 2) 4734#define VXGE_HAL_PXTMC_CFG1_MAX_NBR_UXP_EVENTS(val) vBIT(val, 14, 2) 4735#define VXGE_HAL_PXTMC_CFG1_MAX_NBR_CXP_EVENTS(val) vBIT(val, 22, 2) 4736#define VXGE_HAL_PXTMC_CFG1_PGSYNC_WAIT_TOKEN_ENABLE mBIT(29) 4737#define VXGE_HAL_PXTMC_CFG1_PGSYNC_CNTDOWN_TIMER_ENABLE mBIT(30) 4738#define VXGE_HAL_PXTMC_CFG1_PGSYNC_SRC_NOTIFY_ENABLE mBIT(31) 4739#define VXGE_HAL_PXTMC_CFG1_PGSYNC_CNTDOWN_START_VALUE(val) vBIT(val, 36, 4) 4740/* 0x05020 */ u64 xtmc_mem_cfg; 4741#define VXGE_HAL_XTMC_MEM_CFG_CTXT_MEM_SPARSE_BASE(val) vBIT(val, 5, 3) 4742#define VXGE_HAL_XTMC_MEM_CFG_CTXT_MEM_PACKED_BASE(val) vBIT(val, 13, 3) 4743#define VXGE_HAL_XTMC_MEM_CFG_SHARED_SRAM_BASE(val) vBIT(val, 21, 3) 4744#define VXGE_HAL_XTMC_MEM_CFG_CTXT_MEM_SIZE(val) vBIT(val, 29, 3) 4745#define VXGE_HAL_XTMC_MEM_CFG_SRAM_SPARSE_BASE_ADDR(val) vBIT(val, 32, 16) 4746#define VXGE_HAL_XTMC_MEM_CFG_SRAM_PACKED_BASE_ADDR(val) vBIT(val, 48, 16) 4747/* 0x05028 */ u64 xtmc_mem_bypass_cfg; 4748#define VXGE_HAL_XTMC_MEM_BYPASS_CFG_CTXT_MEM_SPARSE_BASE(val) vBIT(val, 5, 3) 4749#define VXGE_HAL_XTMC_MEM_BYPASS_CFG_CTXT_MEM_PACKED_BASE(val) vBIT(val, 13, 3) 4750#define VXGE_HAL_XTMC_MEM_BYPASS_CFG_SHARED_SRAM_BASE(val) vBIT(val, 21, 3) 4751/* 0x05030 */ u64 xtmc_cxp_region0; 4752#define VXGE_HAL_XTMC_CXP_REGION0_START_ADDR(val) vBIT(val, 0, 32) 4753#define VXGE_HAL_XTMC_CXP_REGION0_END_ADDR(val) vBIT(val, 32, 32) 4754/* 0x05038 */ u64 xtmc_mxp_region0; 4755#define VXGE_HAL_XTMC_MXP_REGION0_START_ADDR(val) vBIT(val, 0, 32) 4756#define VXGE_HAL_XTMC_MXP_REGION0_END_ADDR(val) vBIT(val, 32, 32) 4757/* 0x05040 */ u64 xtmc_uxp_region0; 4758#define VXGE_HAL_XTMC_UXP_REGION0_START_ADDR(val) vBIT(val, 0, 32) 4759#define VXGE_HAL_XTMC_UXP_REGION0_END_ADDR(val) vBIT(val, 32, 32) 4760/* 0x05048 */ u64 xtmc_cxp_region1; 4761#define VXGE_HAL_XTMC_CXP_REGION1_START_ADDR(val) vBIT(val, 0, 32) 4762#define VXGE_HAL_XTMC_CXP_REGION1_END_ADDR(val) vBIT(val, 32, 32) 4763/* 0x05050 */ u64 xtmc_mxp_region1; 4764#define VXGE_HAL_XTMC_MXP_REGION1_START_ADDR(val) vBIT(val, 0, 32) 4765#define VXGE_HAL_XTMC_MXP_REGION1_END_ADDR(val) vBIT(val, 32, 32) 4766/* 0x05058 */ u64 xtmc_uxp_region1; 4767#define VXGE_HAL_XTMC_UXP_REGION1_START_ADDR(val) vBIT(val, 0, 32) 4768#define VXGE_HAL_XTMC_UXP_REGION1_END_ADDR(val) vBIT(val, 32, 32) 4769/* 0x05060 */ u64 xtmc_cxp_region2; 4770#define VXGE_HAL_XTMC_CXP_REGION2_START_ADDR(val) vBIT(val, 0, 32) 4771#define VXGE_HAL_XTMC_CXP_REGION2_END_ADDR(val) vBIT(val, 32, 32) 4772/* 0x05068 */ u64 xtmc_mxp_region2; 4773#define VXGE_HAL_XTMC_MXP_REGION2_START_ADDR(val) vBIT(val, 0, 32) 4774#define VXGE_HAL_XTMC_MXP_REGION2_END_ADDR(val) vBIT(val, 32, 32) 4775/* 0x05070 */ u64 xtmc_uxp_region2; 4776#define VXGE_HAL_XTMC_UXP_REGION2_START_ADDR(val) vBIT(val, 0, 32) 4777#define VXGE_HAL_XTMC_UXP_REGION2_END_ADDR(val) vBIT(val, 32, 32) 4778 u8 unused05200[0x05200 - 0x05078]; 4779 4780/* 0x05200 */ u64 msg_int_status; 4781#define VXGE_HAL_MSG_INT_STATUS_TIM_ERR_TIM_INT mBIT(7) 4782#define VXGE_HAL_MSG_INT_STATUS_MSG_EXC_MSG_XT_EXC_INT mBIT(60) 4783#define VXGE_HAL_MSG_INT_STATUS_MSG_ERR3_MSG_ERR3_INT mBIT(61) 4784#define VXGE_HAL_MSG_INT_STATUS_MSG_ERR2_MSG_ERR2_INT mBIT(62) 4785#define VXGE_HAL_MSG_INT_STATUS_MSG_ERR_MSG_ERR_INT mBIT(63) 4786/* 0x05208 */ u64 msg_int_mask; 4787/* 0x05210 */ u64 tim_err_reg; 4788#define VXGE_HAL_TIM_ERR_REG_TIM_VBLS_SG_ERR mBIT(4) 4789#define VXGE_HAL_TIM_ERR_REG_TIM_BMAP_PA_SG_ERR mBIT(5) 4790#define VXGE_HAL_TIM_ERR_REG_TIM_BMAP_PB_SG_ERR mBIT(6) 4791#define VXGE_HAL_TIM_ERR_REG_TIM_BMAP_MSG_SG_ERR mBIT(7) 4792#define VXGE_HAL_TIM_ERR_REG_TIM_VBLS_DB_ERR mBIT(12) 4793#define VXGE_HAL_TIM_ERR_REG_TIM_BMAP_PA_DB_ERR mBIT(13) 4794#define VXGE_HAL_TIM_ERR_REG_TIM_BMAP_PB_DB_ERR mBIT(14) 4795#define VXGE_HAL_TIM_ERR_REG_TIM_BMAP_MSG_DB_ERR mBIT(15) 4796#define VXGE_HAL_TIM_ERR_REG_TIM_BMAP_MEM_CNTRL_SM_ERR mBIT(18) 4797#define VXGE_HAL_TIM_ERR_REG_TIM_BMAP_MSG_MEM_CNTRL_SM_ERR mBIT(19) 4798#define VXGE_HAL_TIM_ERR_REG_TIM_MPIF_PCIWR_ERR mBIT(20) 4799#define VXGE_HAL_TIM_ERR_REG_TIM_ROCRC_BMAP_UPDT_FIFO_ERR mBIT(22) 4800#define VXGE_HAL_TIM_ERR_REG_TIM_CREATE_BMAPMSG_FIFO_ERR mBIT(23) 4801#define VXGE_HAL_TIM_ERR_REG_TIM_ROCRCIF_MISMATCH mBIT(46) 4802#define VXGE_HAL_TIM_ERR_REG_TIM_BMAP_MAPPING_VP_ERR(n) mBIT(n) 4803/* 0x05218 */ u64 tim_err_mask; 4804/* 0x05220 */ u64 tim_err_alarm; 4805/* 0x05228 */ u64 msg_err_reg; 4806#define VXGE_HAL_MSG_ERR_REG_UP_UXP_WAKE_FSM_INTEGRITY_ERR mBIT(0) 4807#define VXGE_HAL_MSG_ERR_REG_MP_MXP_WAKE_FSM_INTEGRITY_ERR mBIT(1) 4808#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMQ_DMA_READ_CMD_FSM_INTEGRITY_ERR mBIT(2) 4809#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMQ_DMA_RESP_FSM_INTEGRITY_ERR mBIT(3) 4810#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMQ_OWN_FSM_INTEGRITY_ERR mBIT(4) 4811#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_PDA_ACC_FSM_INTEGRITY_ERR mBIT(5) 4812#define VXGE_HAL_MSG_ERR_REG_MP_MXP_PMON_FSM_INTEGRITY_ERR mBIT(6) 4813#define VXGE_HAL_MSG_ERR_REG_UP_UXP_PMON_FSM_INTEGRITY_ERR mBIT(7) 4814#define VXGE_HAL_MSG_ERR_REG_UP_UXP_DTAG_SG_ERR mBIT(8) 4815#define VXGE_HAL_MSG_ERR_REG_UP_UXP_ITAG_SG_ERR mBIT(10) 4816#define VXGE_HAL_MSG_ERR_REG_MP_MXP_DTAG_SG_ERR mBIT(12) 4817#define VXGE_HAL_MSG_ERR_REG_MP_MXP_ITAG_SG_ERR mBIT(14) 4818#define VXGE_HAL_MSG_ERR_REG_UP_UXP_TRACE_SG_ERR mBIT(16) 4819#define VXGE_HAL_MSG_ERR_REG_MP_MXP_TRACE_SG_ERR mBIT(17) 4820#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_CMG2MSG_SG_ERR mBIT(18) 4821#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_TXPE2MSG_SG_ERR mBIT(19) 4822#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_RXPE2MSG_SG_ERR mBIT(20) 4823#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_RPE2MSG_SG_ERR mBIT(21) 4824#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_UMQ_SG_ERR mBIT(26) 4825#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_BWR_PF_SG_ERR mBIT(27) 4826#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMQ_ECC_SG_ERR mBIT(29) 4827#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMA_RESP_ECC_SG_ERR mBIT(31) 4828#define VXGE_HAL_MSG_ERR_REG_MSG_XFMDQRY_FSM_INTEGRITY_ERR mBIT(33) 4829#define VXGE_HAL_MSG_ERR_REG_MSG_FRMQRY_FSM_INTEGRITY_ERR mBIT(34) 4830#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_UMQ_WRITE_FSM_INTEGRITY_ERR mBIT(35) 4831#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_UMQ_BWR_PF_FSM_INTEGRITY_ERR mBIT(36) 4832#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_REG_RESP_FIFO_ERR mBIT(38) 4833#define VXGE_HAL_MSG_ERR_REG_UP_UXP_DTAG_DB_ERR mBIT(39) 4834#define VXGE_HAL_MSG_ERR_REG_UP_UXP_ITAG_DB_ERR mBIT(41) 4835#define VXGE_HAL_MSG_ERR_REG_MP_MXP_DTAG_DB_ERR mBIT(43) 4836#define VXGE_HAL_MSG_ERR_REG_MP_MXP_ITAG_DB_ERR mBIT(45) 4837#define VXGE_HAL_MSG_ERR_REG_UP_UXP_TRACE_DB_ERR mBIT(47) 4838#define VXGE_HAL_MSG_ERR_REG_MP_MXP_TRACE_DB_ERR mBIT(48) 4839#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_CMG2MSG_DB_ERR mBIT(49) 4840#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_TXPE2MSG_DB_ERR mBIT(50) 4841#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_RXPE2MSG_DB_ERR mBIT(51) 4842#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_RPE2MSG_DB_ERR mBIT(52) 4843#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_REG_READ_FIFO_ERR mBIT(53) 4844#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_MXP2UXP_FIFO_ERR mBIT(54) 4845#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_KDFC_SIF_FIFO_ERR mBIT(55) 4846#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_CXP2SWIF_FIFO_ERR mBIT(56) 4847#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_UMQ_DB_ERR mBIT(57) 4848#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_BWR_PF_DB_ERR mBIT(58) 4849#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_BWR_SIF_FIFO_ERR mBIT(59) 4850#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMQ_ECC_DB_ERR mBIT(60) 4851#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMA_READ_FIFO_ERR mBIT(61) 4852#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_DMA_RESP_ECC_DB_ERR mBIT(62) 4853#define VXGE_HAL_MSG_ERR_REG_MSG_QUE_UXP2MXP_FIFO_ERR mBIT(63) 4854/* 0x05230 */ u64 msg_err_mask; 4855/* 0x05238 */ u64 msg_err_alarm; 4856/* 0x05240 */ u64 msg_xt_ctrl; 4857#define VXGE_HAL_MSG_XT_CTRL_MXP_CAUSE_INT_IS_CRITICAL mBIT(35) 4858#define VXGE_HAL_MSG_XT_CTRL_UXP_CAUSE_INT_IS_CRITICAL mBIT(39) 4859#define VXGE_HAL_MSG_XT_CTRL_MXP_WAKEUP mBIT(46) 4860#define VXGE_HAL_MSG_XT_CTRL_UXP_WAKEUP mBIT(47) 4861#define VXGE_HAL_MSG_XT_CTRL_MXP_RUNSTALL mBIT(54) 4862#define VXGE_HAL_MSG_XT_CTRL_UXP_RUNSTALL mBIT(55) 4863#define VXGE_HAL_MSG_XT_CTRL_MXP_BRESET mBIT(62) 4864#define VXGE_HAL_MSG_XT_CTRL_UXP_BRESET mBIT(63) 4865 u8 unused052a8[0x052a8 - 0x05248]; 4866 4867/* 0x052a8 */ u64 msg_dispatch; 4868#define VXGE_HAL_MSG_DISPATCH_MESS_TYPE_ENABLE mBIT(55) 4869#define VXGE_HAL_MSG_DISPATCH_VPATH_CUTOFF(val) vBIT(val, 59, 5) 4870 u8 unused05340[0x05340 - 0x052b0]; 4871 4872/* 0x05340 */ u64 msg_exc_reg; 4873#define VXGE_HAL_MSG_EXC_REG_MP_MXP_CAUSE_INFO_INT mBIT(50) 4874#define VXGE_HAL_MSG_EXC_REG_MP_MXP_CAUSE_CRIT_INT mBIT(51) 4875#define VXGE_HAL_MSG_EXC_REG_UP_UXP_CAUSE_INFO_INT mBIT(54) 4876#define VXGE_HAL_MSG_EXC_REG_UP_UXP_CAUSE_CRIT_INT mBIT(55) 4877#define VXGE_HAL_MSG_EXC_REG_MP_MXP_SERR mBIT(62) 4878#define VXGE_HAL_MSG_EXC_REG_UP_UXP_SERR mBIT(63) 4879/* 0x05348 */ u64 msg_exc_mask; 4880/* 0x05350 */ u64 msg_exc_alarm; 4881/* 0x05358 */ u64 msg_exc_cause; 4882#define VXGE_HAL_MSG_EXC_CAUSE_MP_MXP(val) vBIT(val, 0, 32) 4883#define VXGE_HAL_MSG_EXC_CAUSE_UP_UXP(val) vBIT(val, 32, 32) 4884 u8 unused05368[0x05368 - 0x05360]; 4885 4886/* 0x05368 */ u64 msg_direct_pic; 4887#define VXGE_HAL_MSG_DIRECT_PIC_PIPELINE_EN mBIT(55) 4888#define VXGE_HAL_MSG_DIRECT_PIC_UMQ_WRITE_ENABLE mBIT(56) 4889#define VXGE_HAL_MSG_DIRECT_PIC_UMQ_VPA(val) vBIT(val, 59, 5) 4890/* 0x05370 */ u64 umq_ir_test_vpa; 4891#define VXGE_HAL_UMQ_IR_TEST_VPA_NUMBER(val) vBIT(val, 0, 5) 4892/* 0x05378 */ u64 umq_ir_test_byte; 4893#define VXGE_HAL_UMQ_IR_TEST_BYTE_VALUE_START(val) vBIT(val, 0, 32) 4894/* 0x05380 */ u64 msg_err2_reg; 4895#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_CMG2MSG_DISPATCH_FSM_INTEGRITY_ERR mBIT(0) 4896#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_DMQ_DISPATCH_FSM_INTEGRITY_ERR mBIT(1) 4897#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_SWIF_DISPATCH_FSM_INTEGRITY_ERR mBIT(2) 4898#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_PIC_WRITE_FSM_INTEGRITY_ERR mBIT(3) 4899#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_SWIFREG_FSM_INTEGRITY_ERR mBIT(4) 4900#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_TIM_WRITE_FSM_INTEGRITY_ERR mBIT(5) 4901#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_UMQ_TA_FSM_INTEGRITY_ERR mBIT(6) 4902#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_TXPE_TA_FSM_INTEGRITY_ERR mBIT(7) 4903#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_RXPE_TA_FSM_INTEGRITY_ERR mBIT(8) 4904#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_SWIF_TA_FSM_INTEGRITY_ERR mBIT(9) 4905#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_DMA_TA_FSM_INTEGRITY_ERR mBIT(10) 4906#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_CP_TA_FSM_INTEGRITY_ERR mBIT(11) 4907#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA16_FSM_INTEGRITY_ERR\ 4908 mBIT(12) 4909#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA15_FSM_INTEGRITY_ERR\ 4910 mBIT(13) 4911#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA14_FSM_INTEGRITY_ERR\ 4912 mBIT(14) 4913#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA13_FSM_INTEGRITY_ERR\ 4914 mBIT(15) 4915#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA12_FSM_INTEGRITY_ERR\ 4916 mBIT(16) 4917#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA11_FSM_INTEGRITY_ERR\ 4918 mBIT(17) 4919#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA10_FSM_INTEGRITY_ERR\ 4920 mBIT(18) 4921#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA9_FSM_INTEGRITY_ERR mBIT(19) 4922#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA8_FSM_INTEGRITY_ERR mBIT(20) 4923#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA7_FSM_INTEGRITY_ERR mBIT(21) 4924#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA6_FSM_INTEGRITY_ERR mBIT(22) 4925#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA5_FSM_INTEGRITY_ERR mBIT(23) 4926#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA4_FSM_INTEGRITY_ERR mBIT(24) 4927#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA3_FSM_INTEGRITY_ERR mBIT(25) 4928#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA2_FSM_INTEGRITY_ERR mBIT(26) 4929#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA1_FSM_INTEGRITY_ERR mBIT(27) 4930#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA0_FSM_INTEGRITY_ERR mBIT(28) 4931#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_FBMC_OWN_FSM_INTEGRITY_ERR mBIT(29) 4932#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_TXPE2MSG_DISPATCH_FSM_INTEGRITY_ERR\ 4933 mBIT(30) 4934#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_RXPE2MSG_DISPATCH_FSM_INTEGRITY_ERR\ 4935 mBIT(31) 4936#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_RPE2MSG_DISPATCH_FSM_INTEGRITY_ERR\ 4937 mBIT(32) 4938#define VXGE_HAL_MSG_ERR2_REG_MP_MP_PIFT_IF_CREDIT_CNT_ERR mBIT(33) 4939#define VXGE_HAL_MSG_ERR2_REG_UP_UP_PIFT_IF_CREDIT_CNT_ERR mBIT(34) 4940#define VXGE_HAL_MSG_ERR2_REG_MSG_QUE_UMQ2PIC_CMD_FIFO_ERR mBIT(62) 4941#define VXGE_HAL_MSG_ERR2_REG_TIM_TIM2MSG_CMD_FIFO_ERR mBIT(63) 4942/* 0x05388 */ u64 msg_err2_mask; 4943/* 0x05390 */ u64 msg_err2_alarm; 4944/* 0x05398 */ u64 msg_err3_reg; 4945#define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR0 mBIT(0) 4946#define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR1 mBIT(1) 4947#define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR2 mBIT(2) 4948#define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR3 mBIT(3) 4949#define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR4 mBIT(4) 4950#define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR5 mBIT(5) 4951#define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR6 mBIT(6) 4952#define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR7 mBIT(7) 4953#define VXGE_HAL_MSG_ERR3_REG_UP_UXP_ICACHE_SG_ERR0 mBIT(8) 4954#define VXGE_HAL_MSG_ERR3_REG_UP_UXP_ICACHE_SG_ERR1 mBIT(9) 4955#define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR0 mBIT(16) 4956#define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR1 mBIT(17) 4957#define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR2 mBIT(18) 4958#define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR3 mBIT(19) 4959#define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR4 mBIT(20) 4960#define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR5 mBIT(21) 4961#define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR6 mBIT(22) 4962#define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR7 mBIT(23) 4963#define VXGE_HAL_MSG_ERR3_REG_MP_MXP_ICACHE_SG_ERR0 mBIT(24) 4964#define VXGE_HAL_MSG_ERR3_REG_MP_MXP_ICACHE_SG_ERR1 mBIT(25) 4965#define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR0 mBIT(32) 4966#define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR1 mBIT(33) 4967#define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR2 mBIT(34) 4968#define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR3 mBIT(35) 4969#define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR4 mBIT(36) 4970#define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR5 mBIT(37) 4971#define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR6 mBIT(38) 4972#define VXGE_HAL_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR7 mBIT(39) 4973#define VXGE_HAL_MSG_ERR3_REG_UP_UXP_ICACHE_DB_ERR0 mBIT(40) 4974#define VXGE_HAL_MSG_ERR3_REG_UP_UXP_ICACHE_DB_ERR1 mBIT(41) 4975#define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR0 mBIT(48) 4976#define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR1 mBIT(49) 4977#define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR2 mBIT(50) 4978#define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR3 mBIT(51) 4979#define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR4 mBIT(52) 4980#define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR5 mBIT(53) 4981#define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR6 mBIT(54) 4982#define VXGE_HAL_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR7 mBIT(55) 4983#define VXGE_HAL_MSG_ERR3_REG_MP_MXP_ICACHE_DB_ERR0 mBIT(56) 4984#define VXGE_HAL_MSG_ERR3_REG_MP_MXP_ICACHE_DB_ERR1 mBIT(57) 4985/* 0x053a0 */ u64 msg_err3_mask; 4986/* 0x053a8 */ u64 msg_err3_alarm; 4987/* 0x053b0 */ u64 umq_ir_test_byte_notify; 4988#define VXGE_HAL_UMQ_IR_TEST_BYTE_NOTIFY_PULSE mBIT(3) 4989/* 0x053b8 */ u64 msg_bp_ctrl; 4990#define VXGE_HAL_MSG_BP_CTRL_RD_XON_EN mBIT(7) 4991#define VXGE_HAL_MSG_BP_CTRL_WR_XON_E mBIT(15) 4992#define VXGE_HAL_MSG_BP_CTRL_ROCRC_BYP_EN mBIT(23) 4993/* 0x053c0 */ u64 umq_bwr_pfch_init[17]; 4994#define VXGE_HAL_UMQ_BWR_PFCH_INIT_NUMBER(val) vBIT(val, 0, 8) 4995/* 0x05448 */ u64 umq_bwr_pfch_init_notify[17]; 4996#define VXGE_HAL_UMQ_BWR_PFCH_INIT_NOTIFY_PULSE mBIT(3) 4997/* 0x054d0 */ u64 umq_bwr_eol; 4998#define VXGE_HAL_UMQ_BWR_EOL_POLL_LATENCY(val) vBIT(val, 32, 32) 4999/* 0x054d8 */ u64 umq_bwr_eol_latency_notify; 5000#define VXGE_HAL_UMQ_BWR_EOL_LATENCY_NOTIFY_PULSE mBIT(3) 5001 u8 unused05600[0x05600 - 0x054e0]; 5002 5003/* 0x05600 */ u64 fau_gen_err_reg; 5004#define VXGE_HAL_FAU_GEN_ERR_REG_FMPF_PORT0_PERMANENT_STOP mBIT(3) 5005#define VXGE_HAL_FAU_GEN_ERR_REG_FMPF_PORT1_PERMANENT_STOP mBIT(7) 5006#define VXGE_HAL_FAU_GEN_ERR_REG_FMPF_PORT2_PERMANENT_STOP mBIT(11) 5007#define VXGE_HAL_FAU_GEN_ERR_REG_FALR_AUTO_LRO_NOTIF mBIT(15) 5008/* 0x05608 */ u64 fau_gen_err_mask; 5009/* 0x05610 */ u64 fau_gen_err_alarm; 5010/* 0x05618 */ u64 fau_ecc_err_reg; 5011#define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_N_SG_ERR mBIT(0) 5012#define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_N_DB_ERR mBIT(1) 5013#define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_W_SG_ERR(val)\ 5014 vBIT(val, 2, 2) 5015#define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_W_DB_ERR(val)\ 5016 vBIT(val, 4, 2) 5017#define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_N_SG_ERR mBIT(6) 5018#define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_N_DB_ERR mBIT(7) 5019#define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_W_SG_ERR(val)\ 5020 vBIT(val, 8, 2) 5021#define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_W_DB_ERR(val)\ 5022 vBIT(val, 10, 2) 5023#define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_N_SG_ERR mBIT(12) 5024#define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_N_DB_ERR mBIT(13) 5025#define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_W_SG_ERR(val)\ 5026 vBIT(val, 14, 2) 5027#define VXGE_HAL_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_W_DB_ERR(val)\ 5028 vBIT(val, 16, 2) 5029#define VXGE_HAL_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_SG_ERR(val) vBIT(val, 18, 2) 5030#define VXGE_HAL_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_DB_ERR(val) vBIT(val, 20, 2) 5031#define VXGE_HAL_FAU_ECC_ERR_REG_FAUJ_FAU_FSM_ERR mBIT(31) 5032/* 0x05620 */ u64 fau_ecc_err_mask; 5033/* 0x05628 */ u64 fau_ecc_err_alarm; 5034 u8 unused05648[0x05648 - 0x05630]; 5035 5036/* 0x05648 */ u64 fau_global_cfg; 5037#define VXGE_HAL_FAU_GLOBAL_CFG_ARB_ALG(val) vBIT(val, 2, 2) 5038/* 0x05650 */ u64 rx_datapath_util; 5039#define VXGE_HAL_RX_DATAPATH_UTIL_FAU_RX_UTILIZATION(val) vBIT(val, 7, 9) 5040#define VXGE_HAL_RX_DATAPATH_UTIL_RX_UTIL_CFG(val) vBIT(val, 16, 4) 5041#define VXGE_HAL_RX_DATAPATH_UTIL_FAU_RX_FRAC_UTIL(val) vBIT(val, 20, 4) 5042#define VXGE_HAL_RX_DATAPATH_UTIL_RX_PKT_WEIGHT(val) vBIT(val, 24, 4) 5043/* 0x05658 */ u64 fau_pa_cfg; 5044#define VXGE_HAL_FAU_PA_CFG_REPL_L4_COMP_CSUM mBIT(3) 5045#define VXGE_HAL_FAU_PA_CFG_REPL_L3_INCL_CF mBIT(7) 5046#define VXGE_HAL_FAU_PA_CFG_REPL_L3_COMP_CSUM mBIT(11) 5047 u8 unused05668[0x05668 - 0x05660]; 5048 5049/* 0x05668 */ u64 dbg_stats_fau_rx_path; 5050#define VXGE_HAL_DBG_STATS_FAU_RX_PATH_RX_PERMITTED_FRMS(val) vBIT(val, 32, 32) 5051/* 0x05670 */ u64 fau_auto_lro_control; 5052#define VXGE_HAL_FAU_AUTO_LRO_CONTROL_OPERATION_TYPE mBIT(7) 5053#define VXGE_HAL_FAU_AUTO_LRO_CONTROL_FRAME_COUNT(val) vBIT(val, 8, 24) 5054#define VXGE_HAL_FAU_AUTO_LRO_CONTROL_TIMER_VALUE(val) vBIT(val, 32, 32) 5055/* 0x05678 */ u64 fau_auto_lro_data_0; 5056#define VXGE_HAL_FAU_AUTO_LRO_DATA_0_SOURCE_VPATH(val) vBIT(val, 3, 5) 5057#define VXGE_HAL_FAU_AUTO_LRO_DATA_0_HAS_VLAN mBIT(14) 5058#define VXGE_HAL_FAU_AUTO_LRO_DATA_0_IS_IPV6 mBIT(15) 5059#define VXGE_HAL_FAU_AUTO_LRO_DATA_0_VLAN_VID(val) vBIT(val, 20, 12) 5060#define VXGE_HAL_FAU_AUTO_LRO_DATA_0_TCP_DEST_PORT(val) vBIT(val, 32, 16) 5061#define VXGE_HAL_FAU_AUTO_LRO_DATA_0_TCP_SOURCE_PORT(val) vBIT(val, 48, 16) 5062/* 0x05680 */ u64 fau_auto_lro_data_1; 5063#define VXGE_HAL_FAU_AUTO_LRO_DATA_1_IP_SOURCE_ADDR_0(val) vBIT(val, 0, 64) 5064/* 0x05688 */ u64 fau_auto_lro_data_2; 5065#define VXGE_HAL_FAU_AUTO_LRO_DATA_2_IP_SOURCE_ADDR_1(val) vBIT(val, 0, 64) 5066/* 0x05690 */ u64 fau_auto_lro_data_3; 5067#define VXGE_HAL_FAU_AUTO_LRO_DATA_3_IP_DEST_ADDR_0(val) vBIT(val, 0, 64) 5068/* 0x05698 */ u64 fau_auto_lro_data_4; 5069#define VXGE_HAL_FAU_AUTO_LRO_DATA_4_IP_DEST_ADDR_1(val) vBIT(val, 0, 64) 5070 u8 unused056c0[0x056c0 - 0x056a0]; 5071 5072/* 0x056c0 */ u64 fau_lag_cfg; 5073#define VXGE_HAL_FAU_LAG_CFG_COLL_ALG(val) vBIT(val, 2, 2) 5074#define VXGE_HAL_FAU_LAG_CFG_INCR_RX_AGGR_STATS mBIT(7) 5075 u8 unused05700[0x05700 - 0x056c8]; 5076 5077/* 0x05700 */ u64 fau_mpa_cfg; 5078#define VXGE_HAL_FAU_MPA_CFG_CRC_CHK_EN mBIT(3) 5079#define VXGE_HAL_FAU_MPA_CFG_MRK_LEN_CHK_EN mBIT(7) 5080 u8 unused057a0[0x057a0 - 0x05708]; 5081 5082/* 0x057a0 */ u64 xmac_rx_xgmii_capture_data_port[3]; 5083#define VXGE_HAL_XMAC_RX_XGMII_CAPTURE_DATA_PORT_COL_INDX(val) vBIT(val, 0, 12) 5084#define VXGE_HAL_XMAC_RX_XGMII_CAPTURE_DATA_PORT_FAUJ_FLAG(val) vBIT(val, 26, 2) 5085#define VXGE_HAL_XMAC_RX_XGMII_CAPTURE_DATA_PORT_FAUJ_RXC(val) vBIT(val, 28, 4) 5086#define VXGE_HAL_XMAC_RX_XGMII_CAPTURE_DATA_PORT_FAUJ_RXD(val) vBIT(val, 32, 32) 5087 u8 unused05800[0x05800 - 0x057b8]; 5088 5089/* 0x05800 */ u64 tpa_int_status; 5090#define VXGE_HAL_TPA_INT_STATUS_ORP_ERR_ORP_INT mBIT(15) 5091#define VXGE_HAL_TPA_INT_STATUS_PTM_ALARM_PTM_INT mBIT(23) 5092#define VXGE_HAL_TPA_INT_STATUS_TPA_ERROR_TPA_INT mBIT(31) 5093/* 0x05808 */ u64 tpa_int_mask; 5094/* 0x05810 */ u64 orp_err_reg; 5095#define VXGE_HAL_ORP_ERR_REG_ORP_FIFO_SG_ERR mBIT(3) 5096#define VXGE_HAL_ORP_ERR_REG_ORP_FIFO_DB_ERR mBIT(7) 5097#define VXGE_HAL_ORP_ERR_REG_ORP_XFMD_FIFO_UFLOW_ERR mBIT(11) 5098#define VXGE_HAL_ORP_ERR_REG_ORP_FRM_FIFO_UFLOW_ERR mBIT(15) 5099#define VXGE_HAL_ORP_ERR_REG_ORP_XFMD_RCV_FSM_ERR mBIT(19) 5100#define VXGE_HAL_ORP_ERR_REG_ORP_OUTREAD_FSM_ERR mBIT(23) 5101#define VXGE_HAL_ORP_ERR_REG_ORP_OUTQEM_FSM_ERR mBIT(27) 5102#define VXGE_HAL_ORP_ERR_REG_ORP_XFMD_RCV_SHADOW_ERR mBIT(31) 5103#define VXGE_HAL_ORP_ERR_REG_ORP_OUTREAD_SHADOW_ERR mBIT(35) 5104#define VXGE_HAL_ORP_ERR_REG_ORP_OUTQEM_SHADOW_ERR mBIT(39) 5105#define VXGE_HAL_ORP_ERR_REG_ORP_OUTFRM_SHADOW_ERR mBIT(43) 5106#define VXGE_HAL_ORP_ERR_REG_ORP_OPTPRS_SHADOW_ERR mBIT(47) 5107/* 0x05818 */ u64 orp_err_mask; 5108/* 0x05820 */ u64 orp_err_alarm; 5109/* 0x05828 */ u64 ptm_alarm_reg; 5110#define VXGE_HAL_PTM_ALARM_REG_PTM_RDCTRL_SYNC_ERR mBIT(3) 5111#define VXGE_HAL_PTM_ALARM_REG_PTM_RDCTRL_FIFO_ERR mBIT(7) 5112#define VXGE_HAL_PTM_ALARM_REG_XFMD_RD_FIFO_ERR mBIT(11) 5113#define VXGE_HAL_PTM_ALARM_REG_WDE2MSR_WR_FIFO_ERR mBIT(15) 5114#define VXGE_HAL_PTM_ALARM_REG_PTM_FRMM_ECC_DB_ERR(val) vBIT(val, 18, 2) 5115#define VXGE_HAL_PTM_ALARM_REG_PTM_FRMM_ECC_SG_ERR(val) vBIT(val, 22, 2) 5116/* 0x05830 */ u64 ptm_alarm_mask; 5117/* 0x05838 */ u64 ptm_alarm_alarm; 5118/* 0x05840 */ u64 tpa_error_reg; 5119#define VXGE_HAL_TPA_ERROR_REG_TPA_FSM_ERR_ALARM mBIT(3) 5120#define VXGE_HAL_TPA_ERROR_REG_TPA_TPA_DA_LKUP_PRT0_DB_ERR mBIT(7) 5121#define VXGE_HAL_TPA_ERROR_REG_TPA_TPA_DA_LKUP_PRT0_SG_ERR mBIT(11) 5122/* 0x05848 */ u64 tpa_error_mask; 5123/* 0x05850 */ u64 tpa_error_alarm; 5124/* 0x05858 */ u64 tpa_global_cfg; 5125#define VXGE_HAL_TPA_GLOBAL_CFG_SUPPORT_SNAP_AB_N mBIT(7) 5126#define VXGE_HAL_TPA_GLOBAL_CFG_ECC_ENABLE_N mBIT(35) 5127/* 0x05860 */ u64 tx_datapath_util; 5128#define VXGE_HAL_TX_DATAPATH_UTIL_TPA_TX_UTILIZATION(val) vBIT(val, 7, 9) 5129#define VXGE_HAL_TX_DATAPATH_UTIL_TX_UTIL_CFG(val) vBIT(val, 16, 4) 5130#define VXGE_HAL_TX_DATAPATH_UTIL_TPA_TX_FRAC_UTIL(val) vBIT(val, 20, 4) 5131#define VXGE_HAL_TX_DATAPATH_UTIL_TX_PKT_WEIGHT(val) vBIT(val, 24, 4) 5132/* 0x05868 */ u64 orp_cfg; 5133#define VXGE_HAL_ORP_CFG_FIFO_CREDITS(val) vBIT(val, 5, 3) 5134#define VXGE_HAL_ORP_CFG_ORP_FIFO_ECC_ENABLE_N mBIT(15) 5135#define VXGE_HAL_ORP_CFG_FIFO_PHASE_EN mBIT(23) 5136/* 0x05870 */ u64 ptm_ecc_cfg; 5137#define VXGE_HAL_PTM_ECC_CFG_PTM_FRMM_ECC_EN_N mBIT(3) 5138/* 0x05878 */ u64 ptm_phase_cfg; 5139#define VXGE_HAL_PTM_PHASE_CFG_FRMM_WR_PHASE_EN mBIT(3) 5140#define VXGE_HAL_PTM_PHASE_CFG_FRMM_RD_PHASE_EN mBIT(7) 5141/* 0x05880 */ u64 orp_lro_events; 5142#define VXGE_HAL_ORP_LRO_EVENTS_ORP_LRO_EVENTS(val) vBIT(val, 0, 64) 5143/* 0x05888 */ u64 orp_bs_events; 5144#define VXGE_HAL_ORP_BS_EVENTS_ORP_BS_EVENTS(val) vBIT(val, 0, 64) 5145/* 0x05890 */ u64 orp_iwarp_events; 5146#define VXGE_HAL_ORP_IWARP_EVENTS_ORP_IWARP_EVENTS(val) vBIT(val, 0, 64) 5147/* 0x05898 */ u64 dbg_stats_tpa_tx_path; 5148#define VXGE_HAL_DBG_STATS_TPA_TX_PATH_TX_PERMITTED_FRMS(val) vBIT(val, 32, 32) 5149 u8 unused05900[0x05900 - 0x058a0]; 5150 5151/* 0x05900 */ u64 tmac_int_status; 5152#define VXGE_HAL_TMAC_INT_STATUS_TXMAC_GEN_ERR_TXMAC_GEN_INT mBIT(3) 5153#define VXGE_HAL_TMAC_INT_STATUS_TXMAC_ECC_ERR_TXMAC_ECC_INT mBIT(7) 5154/* 0x05908 */ u64 tmac_int_mask; 5155/* 0x05910 */ u64 txmac_gen_err_reg; 5156#define VXGE_HAL_TXMAC_GEN_ERR_REG_TMACJ_PERMANENT_STOP mBIT(3) 5157#define VXGE_HAL_TXMAC_GEN_ERR_REG_TMACJ_NO_VALID_VSPORT mBIT(7) 5158/* 0x05918 */ u64 txmac_gen_err_mask; 5159/* 0x05920 */ u64 txmac_gen_err_alarm; 5160/* 0x05928 */ u64 txmac_ecc_err_reg; 5161#define VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2MAC_SG_ERR mBIT(3) 5162#define VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2MAC_DB_ERR mBIT(7) 5163#define VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_SB_SG_ERR mBIT(11) 5164#define VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_SB_DB_ERR mBIT(15) 5165#define VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_DA_SG_ERR mBIT(19) 5166#define VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_DA_DB_ERR mBIT(23) 5167#define VXGE_HAL_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT0_FSM_ERR mBIT(27) 5168#define VXGE_HAL_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT1_FSM_ERR mBIT(31) 5169#define VXGE_HAL_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT2_FSM_ERR mBIT(35) 5170#define VXGE_HAL_TXMAC_ECC_ERR_REG_TMACJ_TMACJ_FSM_ERR mBIT(39) 5171/* 0x05930 */ u64 txmac_ecc_err_mask; 5172/* 0x05938 */ u64 txmac_ecc_err_alarm; 5173 u8 unused05948[0x05948-0x05940]; 5174 5175/* 0x05948 */ u64 txmac_gen_cfg1; 5176#define VXGE_HAL_TXMAC_GEN_CFG1_TX_SWITCH_DISABLE mBIT(7) 5177#define VXGE_HAL_TXMAC_GEN_CFG1_LOSSY_SWITCH mBIT(11) 5178#define VXGE_HAL_TXMAC_GEN_CFG1_LOSSY_WIRE mBIT(15) 5179#define VXGE_HAL_TXMAC_GEN_CFG1_SCALE_TMAC_UTIL mBIT(27) 5180#define VXGE_HAL_TXMAC_GEN_CFG1_DISCARD_WHEN_TMAC_DISABLED mBIT(35) 5181#define VXGE_HAL_TXMAC_GEN_CFG1_IFS_EN mBIT(39) 5182#define VXGE_HAL_TXMAC_GEN_CFG1_IFS_STRETCH_RATIO(val) vBIT(val, 40, 16) 5183#define VXGE_HAL_TXMAC_GEN_CFG1_IFS_NUM_EXTENSION(val) vBIT(val, 59, 5) 5184 u8 unused05958[0x05958 - 0x05950]; 5185 5186/* 0x05958 */ u64 txmac_err_inject_cfg; 5187#define VXGE_HAL_TXMAC_ERR_INJECT_CFG_INJECTOR_ERROR_RATE(val) vBIT(val, 0, 32) 5188/* 0x05960 */ u64 txmac_frmgen_cfg; 5189#define VXGE_HAL_TXMAC_FRMGEN_CFG_EN mBIT(3) 5190#define VXGE_HAL_TXMAC_FRMGEN_CFG_MODE(val) vBIT(val, 6, 2) 5191#define VXGE_HAL_TXMAC_FRMGEN_CFG_PERIOD(val) vBIT(val, 8, 4) 5192#define VXGE_HAL_TXMAC_FRMGEN_CFG_SEND_TO_WIRE mBIT(15) 5193#define VXGE_HAL_TXMAC_FRMGEN_CFG_VPATH_VECTOR(val) vBIT(val, 19, 17) 5194#define VXGE_HAL_TXMAC_FRMGEN_CFG_SRC_VPATH(val) vBIT(val, 39, 5) 5195#define VXGE_HAL_TXMAC_FRMGEN_CFG_HOST_STEERING(val) vBIT(val, 44, 2) 5196#define VXGE_HAL_TXMAC_FRMGEN_CFG_IFS_SEL(val) vBIT(val, 47, 3) 5197/* 0x05968 */ u64 txmac_frmgen_contents; 5198#define VXGE_HAL_TXMAC_FRMGEN_CONTENTS_PATTERN_SEL(val) vBIT(val, 2, 2) 5199#define VXGE_HAL_TXMAC_FRMGEN_CONTENTS_DA_SEL(val) vBIT(val, 6, 2) 5200#define VXGE_HAL_TXMAC_FRMGEN_CONTENTS_LEN_SEL mBIT(11) 5201#define VXGE_HAL_TXMAC_FRMGEN_CONTENTS_MIN_LEN(val) vBIT(val, 14, 14) 5202#define VXGE_HAL_TXMAC_FRMGEN_CONTENTS_MAX_LEN(val) vBIT(val, 30, 14) 5203#define VXGE_HAL_TXMAC_FRMGEN_CONTENTS_LT_FIELD(val) vBIT(val, 44, 16) 5204#define VXGE_HAL_TXMAC_FRMGEN_CONTENTS_DATA_SEL(val) vBIT(val, 62, 2) 5205/* 0x05970 */ u64 txmac_frmgen_data; 5206#define VXGE_HAL_TXMAC_FRMGEN_DATA_FRMDATA(val) vBIT(val, 0, 64) 5207/* 0x05978 */ u64 dbg_stat_tx_any_frms; 5208#define VXGE_HAL_DBG_STAT_TX_ANY_FRMS_PORT0_TX_ANY_FRMS(val) vBIT(val, 0, 8) 5209#define VXGE_HAL_DBG_STAT_TX_ANY_FRMS_PORT1_TX_ANY_FRMS(val) vBIT(val, 8, 8) 5210#define VXGE_HAL_DBG_STAT_TX_ANY_FRMS_PORT2_TX_ANY_FRMS(val) vBIT(val, 16, 8) 5211 u8 unused059a0[0x059a0 - 0x05980]; 5212 5213/* 0x059a0 */ u64 txmac_link_util_port[3]; 5214#define VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_UTILIZATION(val) vBIT(val, 1, 7) 5215#define VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_UTIL_CFG(val) vBIT(val, 8, 4) 5216#define VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_FRAC_UTIL(val) vBIT(val, 12, 4) 5217#define VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_PKT_WEIGHT(val) vBIT(val, 16, 4) 5218#define VXGE_HAL_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_SCALE_FACTOR mBIT(23) 5219/* 0x059b8 */ u64 txmac_cfg0_port[3]; 5220#define VXGE_HAL_TXMAC_CFG0_PORT_TMAC_EN mBIT(3) 5221#define VXGE_HAL_TXMAC_CFG0_PORT_APPEND_PAD mBIT(7) 5222#define VXGE_HAL_TXMAC_CFG0_PORT_PAD_BYTE(val) vBIT(val, 8, 8) 5223/* 0x059d0 */ u64 txmac_cfg1_port[3]; 5224#define VXGE_HAL_TXMAC_CFG1_PORT_AVG_IPG(val) vBIT(val, 40, 8) 5225/* 0x059e8 */ u64 txmac_status_port[3]; 5226#define VXGE_HAL_TXMAC_STATUS_PORT_TMAC_TX_FRM_SENT mBIT(3) 5227 u8 unused05a20[0x05a20 - 0x05a00]; 5228 5229/* 0x05a20 */ u64 lag_distrib_dest; 5230#define VXGE_HAL_LAG_DISTRIB_DEST_MAP_VPATH(n) mBIT(n) 5231/* 0x05a28 */ u64 lag_marker_cfg; 5232#define VXGE_HAL_LAG_MARKER_CFG_GEN_RCVR_EN mBIT(3) 5233#define VXGE_HAL_LAG_MARKER_CFG_RESP_EN mBIT(7) 5234#define VXGE_HAL_LAG_MARKER_CFG_RESP_TIMEOUT(val) vBIT(val, 16, 16) 5235#define VXGE_HAL_LAG_MARKER_CFG_SLOW_PROTO_MRKR_MIN_INTERVAL(val)\ 5236 vBIT(val, 32, 16) 5237#define VXGE_HAL_LAG_MARKER_CFG_THROTTLE_MRKR_RESP mBIT(51) 5238/* 0x05a30 */ u64 lag_tx_cfg; 5239#define VXGE_HAL_LAG_TX_CFG_INCR_TX_AGGR_STATS mBIT(3) 5240#define VXGE_HAL_LAG_TX_CFG_DISTRIB_ALG_SEL(val) vBIT(val, 6, 2) 5241#define VXGE_HAL_LAG_TX_CFG_DISTRIB_REMAP_IF_FAIL mBIT(11) 5242#define VXGE_HAL_LAG_TX_CFG_COLL_MAX_DELAY(val) vBIT(val, 16, 16) 5243/* 0x05a38 */ u64 lag_tx_status; 5244#define VXGE_HAL_LAG_TX_STATUS_TLAG_TIMER_VAL_EMPTIED_LINK(val) vBIT(val, 0, 8) 5245#define VXGE_HAL_LAG_TX_STATUS_TLAG_TIMER_VAL_SLOW_PROTO_MRKR(val)\ 5246 vBIT(val, 8, 8) 5247#define VXGE_HAL_LAG_TX_STATUS_TLAG_TIMER_VAL_SLOW_PROTO_MRKRRESP(val)\ 5248 vBIT(val, 16, 8) 5249 u8 unused05a50[0x05a50 - 0x05a40]; 5250 5251/* 0x05a50 */ u64 txmac_stats_tx_xgmii_char; 5252#define VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_LANE_CHAR1(val) vBIT(val, 1, 3) 5253#define VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_TXC_CHAR1 mBIT(7) 5254#define VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_TXD_CHAR1(val) vBIT(val, 8, 8) 5255#define VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_LANE_CHAR2(val) vBIT(val, 17, 3) 5256#define VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_TXC_CHAR2 mBIT(23) 5257#define VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_TXD_CHAR2(val) vBIT(val, 24, 8) 5258#define VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_BEHAV_CHAR2_NEAR_CHAR1 mBIT(39) 5259#define VXGE_HAL_TXMAC_STATS_TX_XGMII_CHAR_BEHAV_CHAR2_NUM_CHAR(val)\ 5260 vBIT(val, 40, 16) 5261/* 0x05a58 */ u64 txmac_stats_tx_xgmii_column1; 5262#define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXC_LANE0 mBIT(7) 5263#define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXD_LANE0(val) vBIT(val, 8, 8) 5264#define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXC_LANE1 mBIT(23) 5265#define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXD_LANE1(val) vBIT(val, 24, 8) 5266#define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXC_LANE2 mBIT(39) 5267#define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXD_LANE2(val) vBIT(val, 40, 8) 5268#define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXC_LANE3 mBIT(55) 5269#define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN1_TXD_LANE3(val) vBIT(val, 56, 8) 5270/* 0x05a60 */ u64 txmac_stats_tx_xgmii_column2; 5271#define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXC_LANE0 mBIT(7) 5272#define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXD_LANE0(val) vBIT(val, 8, 8) 5273#define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXC_LANE1 mBIT(23) 5274#define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXD_LANE1(val) vBIT(val, 24, 8) 5275#define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXC_LANE2 mBIT(39) 5276#define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXD_LANE2(val) vBIT(val, 40, 8) 5277#define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXC_LANE3 mBIT(55) 5278#define VXGE_HAL_TXMAC_STATS_TX_XGMII_COLUMN2_TXD_LANE3(val) vBIT(val, 56, 8) 5279/* 0x05a68 */ u64 txmac_stats_tx_xgmii_behav_column2; 5280#define VXGE_HAL_TXMAC_STATS_TX_XGMII_BEHAV_COLUMN2_NEAR_COL1 mBIT(7) 5281#define VXGE_HAL_TXMAC_STATS_TX_XGMII_BEHAV_COLUMN2_NUM_COL(val)\ 5282 vBIT(val, 8, 16) 5283 u8 unused05b00[0x05b00 - 0x05a70]; 5284 5285/* 0x05b00 */ u64 sharedio_status; 5286#define VXGE_HAL_SHAREDIO_STATUS_PCI_NEGOTIATED_ACTIVE_VPLANE(val)\ 5287 vBIT(val, 0, 17) 5288#define VXGE_HAL_SHAREDIO_STATUS_PCI_NEGOTIATED_VPLANE_COUNT(val)\ 5289 vBIT(val, 20, 8) 5290#define VXGE_HAL_SHAREDIO_STATUS_PCI_NEGOTIATED_SHC mBIT(31) 5291#define VXGE_HAL_SHAREDIO_STATUS_PCI_SHARED_IO_MODE mBIT(34) 5292#define VXGE_HAL_SHAREDIO_STATUS_PCI_RX_ILLEGAL_TLP_VPLANE_VAL(val)\ 5293 vBIT(val, 36, 8) 5294/* 0x05b08 */ u64 crdt_status1_vplane[17]; 5295#define VXGE_HAL_CRDT_STATUS1_VPLANE_PCI_ABS_PD(val) vBIT(val, 4, 12) 5296#define VXGE_HAL_CRDT_STATUS1_VPLANE_PCI_ABS_NPD(val) vBIT(val, 20, 12) 5297#define VXGE_HAL_CRDT_STATUS1_VPLANE_PCI_ABS_CPLD(val) vBIT(val, 36, 12) 5298#define VXGE_HAL_CRDT_STATUS1_VPLANE_PCI_ABS_PD_INFINITE mBIT(51) 5299#define VXGE_HAL_CRDT_STATUS1_VPLANE_PCI_ABS_NPD_INFINITE mBIT(55) 5300#define VXGE_HAL_CRDT_STATUS1_VPLANE_PCI_ABS_CPLD_INFINITE mBIT(59) 5301/* 0x05b90 */ u64 crdt_status2_vplane[17]; 5302#define VXGE_HAL_CRDT_STATUS2_VPLANE_PCI_ABS_PH(val) vBIT(val, 0, 8) 5303#define VXGE_HAL_CRDT_STATUS2_VPLANE_PCI_ABS_NPH(val) vBIT(val, 8, 8) 5304#define VXGE_HAL_CRDT_STATUS2_VPLANE_PCI_ABS_CPLH(val) vBIT(val, 16, 8) 5305#define VXGE_HAL_CRDT_STATUS2_VPLANE_PCI_ABS_PH_INFINITE mBIT(31) 5306#define VXGE_HAL_CRDT_STATUS2_VPLANE_PCI_ABS_NPH_INFINITE mBIT(35) 5307#define VXGE_HAL_CRDT_STATUS2_VPLANE_PCI_ABS_CPLH_INFINITE mBIT(39) 5308/* 0x05c18 */ u64 crdt_status3_vplane[17]; 5309#define VXGE_HAL_CRDT_STATUS3_VPLANE_PCI_AVAIL_ABS_BUF_PD(val) vBIT(val, 4, 12) 5310#define VXGE_HAL_CRDT_STATUS3_VPLANE_PCI_AVAIL_ABS_BUF_NPD(val)\ 5311 vBIT(val, 20, 12) 5312#define VXGE_HAL_CRDT_STATUS3_VPLANE_PCI_AVAIL_ABS_BUF_CPLD(val)\ 5313 vBIT(val, 36, 12) 5314/* 0x05ca0 */ u64 crdt_status4_vplane[17]; 5315#define VXGE_HAL_CRDT_STATUS4_VPLANE_PCI_AVAIL_ABS_BUF_PH(val) vBIT(val, 0, 8) 5316#define VXGE_HAL_CRDT_STATUS4_VPLANE_PCI_AVAIL_ABS_BUF_NPH(val) vBIT(val, 8, 8) 5317#define VXGE_HAL_CRDT_STATUS4_VPLANE_PCI_AVAIL_ABS_BUF_CPLH(val)\ 5318 vBIT(val, 16, 8) 5319/* 0x05d28 */ u64 crdt_status5; 5320#define VXGE_HAL_CRDT_STATUS5_PCI_DEPL_PH(val) vBIT(val, 0, 17) 5321#define VXGE_HAL_CRDT_STATUS5_PCI_DEPL_NPH(val) vBIT(val, 20, 17) 5322#define VXGE_HAL_CRDT_STATUS5_PCI_DEPL_CPLH(val) vBIT(val, 40, 17) 5323/* 0x05d30 */ u64 crdt_status6; 5324#define VXGE_HAL_CRDT_STATUS6_PCI_DEPL_PD(val) vBIT(val, 0, 17) 5325#define VXGE_HAL_CRDT_STATUS6_PCI_DEPL_NPD(val) vBIT(val, 20, 17) 5326#define VXGE_HAL_CRDT_STATUS6_PCI_DEPL_CPLD(val) vBIT(val, 40, 17) 5327/* 0x05d38 */ u64 crdt_status7; 5328#define VXGE_HAL_CRDT_STATUS7_PCI_ABS_PD(val) vBIT(val, 4, 12) 5329#define VXGE_HAL_CRDT_STATUS7_PCI_ABS_NPD(val) vBIT(val, 20, 12) 5330#define VXGE_HAL_CRDT_STATUS7_PCI_ABS_CPLD(val) vBIT(val, 36, 12) 5331#define VXGE_HAL_CRDT_STATUS7_PCI_ABS_PD_INFINITE mBIT(51) 5332#define VXGE_HAL_CRDT_STATUS7_PCI_ABS_NPD_INFINITE mBIT(55) 5333#define VXGE_HAL_CRDT_STATUS7_PCI_ABS_CPLD_INFINITE mBIT(59) 5334/* 0x05d40 */ u64 crdt_status8; 5335#define VXGE_HAL_CRDT_STATUS8_PCI_ABS_PH(val) vBIT(val, 0, 8) 5336#define VXGE_HAL_CRDT_STATUS8_PCI_ABS_NPH(val) vBIT(val, 8, 8) 5337#define VXGE_HAL_CRDT_STATUS8_PCI_ABS_CPLH(val) vBIT(val, 16, 8) 5338#define VXGE_HAL_CRDT_STATUS8_PCI_ABS_PH_INFINITE mBIT(31) 5339#define VXGE_HAL_CRDT_STATUS8_PCI_ABS_NPH_INFINITE mBIT(35) 5340#define VXGE_HAL_CRDT_STATUS8_PCI_ABS_CPLH_INFINITE mBIT(39) 5341/* 0x05d48 */ u64 srpcim_to_mrpcim_vplane_rmsg[17]; 5342#define VXGE_HAL_SRPCIM_TO_MRPCIM_VPLANE_RMSG_RMSG(val) vBIT(val, 0, 64) 5343 u8 unused06000[0x06000 - 0x05dd0]; 5344 5345/* 0x06000 */ u64 pcie_lane_cfg1; 5346#define VXGE_HAL_PCIE_LANE_CFG1_RX_0_SEL(val) vBIT(val, 1, 3) 5347#define VXGE_HAL_PCIE_LANE_CFG1_RX_1_SEL(val) vBIT(val, 5, 3) 5348#define VXGE_HAL_PCIE_LANE_CFG1_RX_2_SEL(val) vBIT(val, 9, 3) 5349#define VXGE_HAL_PCIE_LANE_CFG1_RX_3_SEL(val) vBIT(val, 13, 3) 5350#define VXGE_HAL_PCIE_LANE_CFG1_RX_4_SEL(val) vBIT(val, 17, 3) 5351#define VXGE_HAL_PCIE_LANE_CFG1_RX_5_SEL(val) vBIT(val, 21, 3) 5352#define VXGE_HAL_PCIE_LANE_CFG1_RX_6_SEL(val) vBIT(val, 25, 3) 5353#define VXGE_HAL_PCIE_LANE_CFG1_RX_7_SEL(val) vBIT(val, 29, 3) 5354#define VXGE_HAL_PCIE_LANE_CFG1_TX_0_SEL(val) vBIT(val, 33, 3) 5355#define VXGE_HAL_PCIE_LANE_CFG1_TX_1_SEL(val) vBIT(val, 37, 3) 5356#define VXGE_HAL_PCIE_LANE_CFG1_TX_2_SEL(val) vBIT(val, 41, 3) 5357#define VXGE_HAL_PCIE_LANE_CFG1_TX_3_SEL(val) vBIT(val, 45, 3) 5358#define VXGE_HAL_PCIE_LANE_CFG1_TX_4_SEL(val) vBIT(val, 49, 3) 5359#define VXGE_HAL_PCIE_LANE_CFG1_TX_5_SEL(val) vBIT(val, 53, 3) 5360#define VXGE_HAL_PCIE_LANE_CFG1_TX_6_SEL(val) vBIT(val, 57, 3) 5361#define VXGE_HAL_PCIE_LANE_CFG1_TX_7_SEL(val) vBIT(val, 61, 3) 5362/* 0x06008 */ u64 pcie_lane_cfg2; 5363#define VXGE_HAL_PCIE_LANE_CFG2_STROBE mBIT(0) 5364/* 0x06010 */ u64 pcicfg_no_to_func_cfg[25]; 5365#define VXGE_HAL_PCICFG_NO_TO_FUNC_CFG_PCICFG_NO_TO_FUNC_CFG(val)\ 5366 vBIT(val, 3, 5) 5367/* 0x060d8 */ u64 resource_to_vplane_cfg[17]; 5368#define VXGE_HAL_RESOURCE_TO_VPLANE_CFG_RESOURCE_TO_VPLANE_CFG(val)\ 5369 vBIT(val, 3, 5) 5370/* 0x06160 */ u64 pcicfg_no_to_vplane_cfg[25]; 5371#define VXGE_HAL_PCICFG_NO_TO_VPLANE_CFG_PCICFG_NO_TO_VPLANE_CFG(val)\ 5372 vBIT(val, 3, 5) 5373/* 0x06228 */ u64 general_cfg; 5374#define VXGE_HAL_GENERAL_CFG_ENABLE_FLR_ON_MRIOV_DIS mBIT(0) 5375#define VXGE_HAL_GENERAL_CFG_ENABLE_FLR_ON_SRIOV_DIS mBIT(1) 5376#define VXGE_HAL_GENERAL_CFG_MULTI_FUNC_8_MODE mBIT(2) 5377#define VXGE_HAL_GENERAL_CFG_EN_RST_CPLTO_IN_LUT mBIT(3) 5378#define VXGE_HAL_GENERAL_CFG_RST_CPLTO_VAL(val) vBIT(val, 4, 4) 5379#define VXGE_HAL_GENERAL_CFG_SHARED_IO_MODE mBIT(11) 5380#define VXGE_HAL_GENERAL_CFG_INIT_OSD_COUNT(val) vBIT(val, 12, 8) 5381#define VXGE_HAL_GENERAL_CFG_INIT_SHC(val) vBIT(val, 20, 8) 5382#define VXGE_HAL_GENERAL_CFG_INITOSD_VERSION(val) vBIT(val, 29, 3) 5383#define VXGE_HAL_GENERAL_CFG_SNOOP_CPLH_CRDT_ON_BUS mBIT(35) 5384#define VXGE_HAL_GENERAL_CFG_FC_UPDT_FREQ_VAL(val) vBIT(val, 36, 4) 5385#define VXGE_HAL_GENERAL_CFG_RX_MEM_ECC_ENABLE_N mBIT(43) 5386#define VXGE_HAL_GENERAL_CFG_TX_MEM_ECC_ENABLE_N mBIT(47) 5387#define VXGE_HAL_GENERAL_CFG_MRIOV_CFG_EN mBIT(51) 5388#define VXGE_HAL_GENERAL_CFG_HIDE_VPD_CAPABILITY mBIT(53) 5389#define VXGE_HAL_GENERAL_CFG_FORCE_RDS_TO_USE_PF_REQID mBIT(54) 5390#define VXGE_HAL_GENERAL_CFG_POISON_ADVISORY mBIT(55) 5391#define VXGE_HAL_GENERAL_CFG_CPL_TIMEOUT_ADVISORY mBIT(56) 5392#define VXGE_HAL_GENERAL_CFG_UNEXP_CPL_ADVISORY mBIT(57) 5393#define VXGE_HAL_GENERAL_CFG_UR_ADVISORY mBIT(58) 5394#define VXGE_HAL_GENERAL_CFG_CA_ADVISORY mBIT(59) 5395#define VXGE_HAL_GENERAL_CFG_WAIT_FOR_CPLH_CRDT_ON_BUS mBIT(60) 5396#define VXGE_HAL_GENERAL_CFG_EN_SEND_ERR_MSG_FOR_SERR mBIT(61) 5397#define VXGE_HAL_GENERAL_CFG_SEND_NF_MSG_FOR_SERR mBIT(62) 5398#define VXGE_HAL_GENERAL_CFG_VF_MUST_USE_CFG_TYPE0 mBIT(63) 5399/* 0x06230 */ u64 start_bist; 5400#define VXGE_HAL_START_BIST_START_BIST mBIT(0) 5401/* 0x06238 */ u64 bist_cfg; 5402#define VXGE_HAL_BIST_CFG_IGNORE_MEM_RDY mBIT(3) 5403#define VXGE_HAL_BIST_CFG_ENABLE mBIT(7) 5404#define VXGE_HAL_BIST_CFG_JTAG_BIST_COMPLETION_CODE(val) vBIT(val, 8, 4) 5405/* 0x06240 */ u64 pci_link_control; 5406#define VXGE_HAL_PCI_LINK_CONTROL_APP_REQ_RETRY_EN mBIT(3) 5407#define VXGE_HAL_PCI_LINK_CONTROL_APP_LTSSM_EN mBIT(7) 5408/* 0x06248 */ u64 show_sriov_cap; 5409#define VXGE_HAL_SHOW_SRIOV_CAP_SHOW_SRIOV_CAP(val) vBIT(val, 0, 9) 5410/* 0x06250 */ u64 link_rst_wait_cnt; 5411#define VXGE_HAL_LINK_RST_WAIT_CNT_LINK_RST_WAIT_CNT(val) vBIT(val, 0, 16) 5412/* 0x06258 */ u64 pcie_based_crdt_cfg1; 5413#define VXGE_HAL_PCIE_BASED_CRDT_CFG1_INIT_PD(val) vBIT(val, 4, 12) 5414#define VXGE_HAL_PCIE_BASED_CRDT_CFG1_INIT_NPD(val) vBIT(val, 20, 12) 5415#define VXGE_HAL_PCIE_BASED_CRDT_CFG1_INIT_CPLD(val) vBIT(val, 36, 12) 5416/* 0x06260 */ u64 pcie_based_crdt_cfg2; 5417#define VXGE_HAL_PCIE_BASED_CRDT_CFG2_INIT_PH(val) vBIT(val, 0, 8) 5418#define VXGE_HAL_PCIE_BASED_CRDT_CFG2_INIT_NPH(val) vBIT(val, 8, 8) 5419#define VXGE_HAL_PCIE_BASED_CRDT_CFG2_INIT_CPLH(val) vBIT(val, 16, 8) 5420/* 0x06268 */ u64 sharedio_abs_based_crdt_cfg1_vplane[17]; 5421#define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG1_VPLANE_ABS_PD(val)\ 5422 vBIT(val, 4, 12) 5423#define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG1_VPLANE_ABS_NPD(val)\ 5424 vBIT(val, 20, 12) 5425#define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG1_VPLANE_ABS_CPLD(val)\ 5426 vBIT(val, 36, 12) 5427#define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG1_VPLANE_ABS_PD_INFINITE mBIT(51) 5428#define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG1_VPLANE_ABS_NPD_INFINITE mBIT(55) 5429#define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG1_VPLANE_ABS_CPLD_INFINITE mBIT(59) 5430/* 0x062f0 */ u64 sharedio_abs_based_crdt_cfg2_vplane[17]; 5431#define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG2_VPLANE_ABS_PH(val)\ 5432 vBIT(val, 0, 8) 5433#define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG2_VPLANE_ABS_NPH(val)\ 5434 vBIT(val, 8, 8) 5435#define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG2_VPLANE_ABS_CPLH(val)\ 5436 vBIT(val, 16, 8) 5437#define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG2_VPLANE_ABS_PH_INFINITE mBIT(31) 5438#define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG2_VPLANE_ABS_NPH_INFINITE mBIT(35) 5439#define VXGE_HAL_SHAREDIO_ABS_BASED_CRDT_CFG2_VPLANE_ABS_CPLH_INFINITE mBIT(39) 5440/* 0x06378 */ u64 arbiter_cfg; 5441#define VXGE_HAL_ARBITER_CFG_CPL_PRIORITY(val) vBIT(val, 2, 2) 5442#define VXGE_HAL_ARBITER_CFG_MRD_PRIORITY(val) vBIT(val, 6, 2) 5443#define VXGE_HAL_ARBITER_CFG_MWR_PRIORITY(val) vBIT(val, 10, 2) 5444#define VXGE_HAL_ARBITER_CFG_CHK_PRIORITY_MATCH_ONLY mBIT(15) 5445#define VXGE_HAL_ARBITER_CFG_CALSTATE0_PRIORITY(val) vBIT(val, 18, 2) 5446#define VXGE_HAL_ARBITER_CFG_CALSTATE1_PRIORITY(val) vBIT(val, 22, 2) 5447#define VXGE_HAL_ARBITER_CFG_CALSTATE2_PRIORITY(val) vBIT(val, 26, 2) 5448#define VXGE_HAL_ARBITER_CFG_CALSTATE3_PRIORITY(val) vBIT(val, 30, 2) 5449#define VXGE_HAL_ARBITER_CFG_CALSTATE4_PRIORITY(val) vBIT(val, 34, 2) 5450#define VXGE_HAL_ARBITER_CFG_CALSTATE5_PRIORITY(val) vBIT(val, 38, 2) 5451/* 0x06380 */ u64 serdes_cfg1; 5452#define VXGE_HAL_SERDES_CFG1_TX_CLOCK_ALIGN(val) vBIT(val, 0, 8) 5453#define VXGE_HAL_SERDES_CFG1_TX_CALC(val) vBIT(val, 8, 8) 5454#define VXGE_HAL_SERDES_CFG1_TX_LVL(val) vBIT(val, 19, 5) 5455#define VXGE_HAL_SERDES_CFG1_LOS_LVL(val) vBIT(val, 27, 5) 5456/* 0x06388 */ u64 serdes_cfg2; 5457#define VXGE_HAL_SERDES_CFG2_TX_0_BOOST(val) vBIT(val, 0, 4) 5458#define VXGE_HAL_SERDES_CFG2_TX_1_BOOST(val) vBIT(val, 4, 4) 5459#define VXGE_HAL_SERDES_CFG2_TX_2_BOOST(val) vBIT(val, 8, 4) 5460#define VXGE_HAL_SERDES_CFG2_TX_3_BOOST(val) vBIT(val, 12, 4) 5461#define VXGE_HAL_SERDES_CFG2_TX_4_BOOST(val) vBIT(val, 16, 4) 5462#define VXGE_HAL_SERDES_CFG2_TX_5_BOOST(val) vBIT(val, 20, 4) 5463#define VXGE_HAL_SERDES_CFG2_TX_6_BOOST(val) vBIT(val, 24, 4) 5464#define VXGE_HAL_SERDES_CFG2_TX_7_BOOST(val) vBIT(val, 28, 4) 5465#define VXGE_HAL_SERDES_CFG2_TX_0_ATTEN(val) vBIT(val, 33, 3) 5466#define VXGE_HAL_SERDES_CFG2_TX_1_ATTEN(val) vBIT(val, 37, 3) 5467#define VXGE_HAL_SERDES_CFG2_TX_2_ATTEN(val) vBIT(val, 41, 3) 5468#define VXGE_HAL_SERDES_CFG2_TX_3_ATTEN(val) vBIT(val, 45, 3) 5469#define VXGE_HAL_SERDES_CFG2_TX_4_ATTEN(val) vBIT(val, 49, 3) 5470#define VXGE_HAL_SERDES_CFG2_TX_5_ATTEN(val) vBIT(val, 53, 3) 5471#define VXGE_HAL_SERDES_CFG2_TX_6_ATTEN(val) vBIT(val, 57, 3) 5472#define VXGE_HAL_SERDES_CFG2_TX_7_ATTEN(val) vBIT(val, 61, 3) 5473/* 0x06390 */ u64 serdes_cfg3; 5474#define VXGE_HAL_SERDES_CFG3_TX_0_EDGERATE(val) vBIT(val, 2, 2) 5475#define VXGE_HAL_SERDES_CFG3_TX_1_EDGERATE(val) vBIT(val, 6, 2) 5476#define VXGE_HAL_SERDES_CFG3_TX_2_EDGERATE(val) vBIT(val, 10, 2) 5477#define VXGE_HAL_SERDES_CFG3_TX_3_EDGERATE(val) vBIT(val, 14, 2) 5478#define VXGE_HAL_SERDES_CFG3_TX_4_EDGERATE(val) vBIT(val, 18, 2) 5479#define VXGE_HAL_SERDES_CFG3_TX_5_EDGERATE(val) vBIT(val, 22, 2) 5480#define VXGE_HAL_SERDES_CFG3_TX_6_EDGERATE(val) vBIT(val, 26, 2) 5481#define VXGE_HAL_SERDES_CFG3_TX_7_EDGERATE(val) vBIT(val, 30, 2) 5482#define VXGE_HAL_SERDES_CFG3_RX_0_EQ_VAL(val) vBIT(val, 33, 3) 5483#define VXGE_HAL_SERDES_CFG3_RX_1_EQ_VAL(val) vBIT(val, 37, 3) 5484#define VXGE_HAL_SERDES_CFG3_RX_2_EQ_VAL(val) vBIT(val, 41, 3) 5485#define VXGE_HAL_SERDES_CFG3_RX_3_EQ_VAL(val) vBIT(val, 45, 3) 5486#define VXGE_HAL_SERDES_CFG3_RX_4_EQ_VAL(val) vBIT(val, 49, 3) 5487#define VXGE_HAL_SERDES_CFG3_RX_5_EQ_VAL(val) vBIT(val, 53, 3) 5488#define VXGE_HAL_SERDES_CFG3_RX_6_EQ_VAL(val) vBIT(val, 57, 3) 5489#define VXGE_HAL_SERDES_CFG3_RX_7_EQ_VAL(val) vBIT(val, 61, 3) 5490/* 0x06398 */ u64 vhlabel_to_vplane_cfg[17]; 5491#define VXGE_HAL_VHLABEL_TO_VPLANE_CFG_VHLABEL_TO_VPLANE_CFG(val)\ 5492 vBIT(val, 3, 5) 5493/* 0x06420 */ u64 mrpcim_to_srpcim_vplane_wmsg[17]; 5494#define VXGE_HAL_MRPCIM_TO_SRPCIM_VPLANE_WMSG_WMSG(val) vBIT(val, 0, 64) 5495/* 0x064a8 */ u64 mrpcim_to_srpcim_vplane_wmsg_trig[17]; 5496#define VXGE_HAL_MRPCIM_TO_SRPCIM_VPLANE_WMSG_TRIG_TRIG mBIT(0) 5497/* 0x06530 */ u64 debug_stats0; 5498#define VXGE_HAL_DEBUG_STATS0_RSTDROP_MSG(val) vBIT(val, 0, 32) 5499#define VXGE_HAL_DEBUG_STATS0_RSTDROP_CPL(val) vBIT(val, 32, 32) 5500/* 0x06538 */ u64 debug_stats1; 5501#define VXGE_HAL_DEBUG_STATS1_RSTDROP_CLIENT0(val) vBIT(val, 0, 32) 5502#define VXGE_HAL_DEBUG_STATS1_RSTDROP_CLIENT1(val) vBIT(val, 32, 32) 5503/* 0x06540 */ u64 debug_stats2; 5504#define VXGE_HAL_DEBUG_STATS2_RSTDROP_CLIENT2(val) vBIT(val, 0, 32) 5505/* 0x06548 */ u64 debug_stats3_vplane[17]; 5506#define VXGE_HAL_DEBUG_STATS3_VPLANE_DEPL_PH(val) vBIT(val, 0, 16) 5507#define VXGE_HAL_DEBUG_STATS3_VPLANE_DEPL_NPH(val) vBIT(val, 16, 16) 5508#define VXGE_HAL_DEBUG_STATS3_VPLANE_DEPL_CPLH(val) vBIT(val, 32, 16) 5509/* 0x065d0 */ u64 debug_stats4_vplane[17]; 5510#define VXGE_HAL_DEBUG_STATS4_VPLANE_DEPL_PD(val) vBIT(val, 0, 16) 5511#define VXGE_HAL_DEBUG_STATS4_VPLANE_DEPL_NPD(val) vBIT(val, 16, 16) 5512#define VXGE_HAL_DEBUG_STATS4_VPLANE_DEPL_CPLD(val) vBIT(val, 32, 16) 5513 u8 unused06b00[0x06b00 - 0x06658]; 5514 5515/* 0x06b00 */ u64 rc_rxdmem_end_ofst[16]; 5516#define VXGE_HAL_RC_RXDMEM_END_OFST_RC_RXDMEM_END_OFST(val) vBIT(val, 49, 8) 5517 u8 unused07000[0x07000 - 0x06b80]; 5518 5519/* 0x07000 */ u64 mrpcim_general_int_status; 5520#define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PIC_INT mBIT(0) 5521#define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PCI_INT mBIT(1) 5522#define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_RTDMA_INT mBIT(2) 5523#define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_WRDMA_INT mBIT(3) 5524#define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3CMCT_INT mBIT(4) 5525#define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_GCMG1_INT mBIT(5) 5526#define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_GCMG2_INT mBIT(6) 5527#define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_GCMG3_INT mBIT(7) 5528#define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3CMIFL_INT mBIT(8) 5529#define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3CMIFU_INT mBIT(9) 5530#define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PCMG1_INT mBIT(10) 5531#define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PCMG2_INT mBIT(11) 5532#define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_PCMG3_INT mBIT(12) 5533#define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_XMAC_INT mBIT(13) 5534#define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_RXMAC_INT mBIT(14) 5535#define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_TMAC_INT mBIT(15) 5536#define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3FBIF_INT mBIT(16) 5537#define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_FBMC_INT mBIT(17) 5538#define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_G3FBCT_INT mBIT(18) 5539#define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_TPA_INT mBIT(19) 5540#define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_DRBELL_INT mBIT(20) 5541#define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_ONE_INT mBIT(21) 5542#define VXGE_HAL_MRPCIM_GENERAL_INT_STATUS_MSG_INT mBIT(22) 5543/* 0x07008 */ u64 mrpcim_general_int_mask; 5544#define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_PIC_INT mBIT(0) 5545#define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_PCI_INT mBIT(1) 5546#define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_RTDMA_INT mBIT(2) 5547#define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_WRDMA_INT mBIT(3) 5548#define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_G3CMCT_INT mBIT(4) 5549#define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_GCMG1_INT mBIT(5) 5550#define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_GCMG2_INT mBIT(6) 5551#define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_GCMG3_INT mBIT(7) 5552#define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_G3CMIFL_INT mBIT(8) 5553#define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_G3CMIFU_INT mBIT(9) 5554#define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_PCMG1_INT mBIT(10) 5555#define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_PCMG2_INT mBIT(11) 5556#define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_PCMG3_INT mBIT(12) 5557#define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_XMAC_INT mBIT(13) 5558#define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_RXMAC_INT mBIT(14) 5559#define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_TMAC_INT mBIT(15) 5560#define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_G3FBIF_INT mBIT(16) 5561#define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_FBMC_INT mBIT(17) 5562#define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_G3FBCT_INT mBIT(18) 5563#define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_TPA_INT mBIT(19) 5564#define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_DRBELL_INT mBIT(20) 5565#define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_ONE_INT mBIT(21) 5566#define VXGE_HAL_MRPCIM_GENERAL_INT_MASK_MSG_INT mBIT(22) 5567/* 0x07010 */ u64 mrpcim_ppif_int_status; 5568#define VXGE_HAL_MRPCIM_PPIF_INT_STATUS_INI_ERRORS_INI_INT mBIT(3) 5569#define VXGE_HAL_MRPCIM_PPIF_INT_STATUS_DMA_ERRORS_DMA_INT mBIT(7) 5570#define VXGE_HAL_MRPCIM_PPIF_INT_STATUS_TGT_ERRORS_TGT_INT mBIT(11) 5571#define VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CONFIG_ERRORS_CONFIG_INT mBIT(15) 5572#define VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_CRDT_INT mBIT(19) 5573#define VXGE_HAL_MRPCIM_PPIF_INT_STATUS_MRPCIM_GENERAL_ERRORS_GENERAL_INT\ 5574 mBIT(23) 5575#define VXGE_HAL_MRPCIM_PPIF_INT_STATUS_PLL_ERRORS_PLL_INT mBIT(27) 5576#define VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE0_CRD_INT_VPLANE0_INT\ 5577 mBIT(31) 5578#define VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE1_CRD_INT_VPLANE1_INT\ 5579 mBIT(32) 5580#define VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE2_CRD_INT_VPLANE2_INT\ 5581 mBIT(33) 5582#define VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE3_CRD_INT_VPLANE3_INT\ 5583 mBIT(34) 5584#define VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE4_CRD_INT_VPLANE4_INT\ 5585 mBIT(35) 5586#define VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE5_CRD_INT_VPLANE5_INT\ 5587 mBIT(36) 5588#define VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE6_CRD_INT_VPLANE6_INT\ 5589 mBIT(37) 5590#define VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE7_CRD_INT_VPLANE7_INT\ 5591 mBIT(38) 5592#define VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE8_CRD_INT_VPLANE8_INT\ 5593 mBIT(39) 5594#define VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE9_CRD_INT_VPLANE9_INT\ 5595 mBIT(40) 5596#define \ 5597 VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE10_CRD_INT_VPLANE10_INT\ 5598 mBIT(41) 5599#define \ 5600 VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE11_CRD_INT_VPLANE11_INT\ 5601 mBIT(42) 5602#define \ 5603 VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE12_CRD_INT_VPLANE12_INT\ 5604 mBIT(43) 5605#define \ 5606 VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE13_CRD_INT_VPLANE13_INT\ 5607 mBIT(44) 5608#define \ 5609 VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE14_CRD_INT_VPLANE14_INT\ 5610 mBIT(45) 5611#define \ 5612 VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE15_CRD_INT_VPLANE15_INT\ 5613 mBIT(46) 5614#define \ 5615 VXGE_HAL_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE16_CRD_INT_VPLANE16_INT\ 5616 mBIT(47) 5617#define VXGE_HAL_MRPCIM_PPIF_INT_STATUS_SRPCIM_TO_MRPCIM_ALARM_INT mBIT(51) 5618#define VXGE_HAL_MRPCIM_PPIF_INT_STATUS_VPATH_TO_MRPCIM_ALARM_INT mBIT(55) 5619/* 0x07018 */ u64 mrpcim_ppif_int_mask; 5620 u8 unused07028[0x07028 - 0x07020]; 5621 5622/* 0x07028 */ u64 ini_errors_reg; 5623#define VXGE_HAL_INI_ERRORS_REG_SCPL_CPL_TIMEOUT_UNUSED_TAG mBIT(3) 5624#define VXGE_HAL_INI_ERRORS_REG_SCPL_CPL_TIMEOUT mBIT(7) 5625#define VXGE_HAL_INI_ERRORS_REG_DCPL_FSM_ERR mBIT(11) 5626#define VXGE_HAL_INI_ERRORS_REG_DCPL_POISON mBIT(12) 5627#define VXGE_HAL_INI_ERRORS_REG_DCPL_UNSUPPORTED mBIT(15) 5628#define VXGE_HAL_INI_ERRORS_REG_DCPL_ABORT mBIT(19) 5629#define VXGE_HAL_INI_ERRORS_REG_INI_TLP_ABORT mBIT(23) 5630#define VXGE_HAL_INI_ERRORS_REG_INI_DLLP_ABORT mBIT(27) 5631#define VXGE_HAL_INI_ERRORS_REG_INI_ECRC_ERR mBIT(31) 5632#define VXGE_HAL_INI_ERRORS_REG_INI_BUF_DB_ERR mBIT(35) 5633#define VXGE_HAL_INI_ERRORS_REG_INI_BUF_SG_ERR mBIT(39) 5634#define VXGE_HAL_INI_ERRORS_REG_INI_DATA_OVERFLOW mBIT(43) 5635#define VXGE_HAL_INI_ERRORS_REG_INI_HDR_OVERFLOW mBIT(47) 5636#define VXGE_HAL_INI_ERRORS_REG_INI_MRD_SYS_DROP mBIT(51) 5637#define VXGE_HAL_INI_ERRORS_REG_INI_MWR_SYS_DROP mBIT(55) 5638#define VXGE_HAL_INI_ERRORS_REG_INI_MRD_CLIENT_DROP mBIT(59) 5639#define VXGE_HAL_INI_ERRORS_REG_INI_MWR_CLIENT_DROP mBIT(63) 5640/* 0x07030 */ u64 ini_errors_mask; 5641/* 0x07038 */ u64 ini_errors_alarm; 5642/* 0x07040 */ u64 dma_errors_reg; 5643#define VXGE_HAL_DMA_ERRORS_REG_RDARB_FSM_ERR mBIT(3) 5644#define VXGE_HAL_DMA_ERRORS_REG_WRARB_FSM_ERR mBIT(7) 5645#define VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_WR_HDR_OVERFLOW mBIT(8) 5646#define VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_WR_HDR_UNDERFLOW mBIT(9) 5647#define VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_WR_DATA_OVERFLOW mBIT(10) 5648#define VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_WR_DATA_UNDERFLOW mBIT(11) 5649#define VXGE_HAL_DMA_ERRORS_REG_DMA_MSG_WR_HDR_OVERFLOW mBIT(12) 5650#define VXGE_HAL_DMA_ERRORS_REG_DMA_MSG_WR_HDR_UNDERFLOW mBIT(13) 5651#define VXGE_HAL_DMA_ERRORS_REG_DMA_MSG_WR_DATA_OVERFLOW mBIT(14) 5652#define VXGE_HAL_DMA_ERRORS_REG_DMA_MSG_WR_DATA_UNDERFLOW mBIT(15) 5653#define VXGE_HAL_DMA_ERRORS_REG_DMA_STATS_WR_HDR_OVERFLOW mBIT(16) 5654#define VXGE_HAL_DMA_ERRORS_REG_DMA_STATS_WR_HDR_UNDERFLOW mBIT(17) 5655#define VXGE_HAL_DMA_ERRORS_REG_DMA_STATS_WR_DATA_OVERFLOW mBIT(18) 5656#define VXGE_HAL_DMA_ERRORS_REG_DMA_STATS_WR_DATA_UNDERFLOW mBIT(19) 5657#define VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_WR_HDR_OVERFLOW mBIT(20) 5658#define VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_WR_HDR_UNDERFLOW mBIT(21) 5659#define VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_WR_DATA_OVERFLOW mBIT(22) 5660#define VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_WR_DATA_UNDERFLOW mBIT(23) 5661#define VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_RD_HDR_OVERFLOW mBIT(24) 5662#define VXGE_HAL_DMA_ERRORS_REG_DMA_WRDMA_RD_HDR_UNDERFLOW mBIT(25) 5663#define VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_RD_HDR_OVERFLOW mBIT(28) 5664#define VXGE_HAL_DMA_ERRORS_REG_DMA_RTDMA_RD_HDR_UNDERFLOW mBIT(29) 5665#define VXGE_HAL_DMA_ERRORS_REG_DBLGEN_FSM_ERR mBIT(32) 5666#define VXGE_HAL_DMA_ERRORS_REG_DBLGEN_CREDIT_FSM_ERR mBIT(33) 5667#define VXGE_HAL_DMA_ERRORS_REG_DBLGEN_DMA_WRR_SM_ERR mBIT(34) 5668/* 0x07048 */ u64 dma_errors_mask; 5669/* 0x07050 */ u64 dma_errors_alarm; 5670/* 0x07058 */ u64 tgt_errors_reg; 5671#define VXGE_HAL_TGT_ERRORS_REG_TGT_VENDOR_MSG mBIT(0) 5672#define VXGE_HAL_TGT_ERRORS_REG_TGT_MSG_UNLOCK mBIT(1) 5673#define VXGE_HAL_TGT_ERRORS_REG_TGT_ILLEGAL_TLP_BE mBIT(2) 5674#define VXGE_HAL_TGT_ERRORS_REG_TGT_BOOT_WRITE mBIT(3) 5675#define VXGE_HAL_TGT_ERRORS_REG_TGT_PIF_WR_CROSS_QWRANGE mBIT(4) 5676#define VXGE_HAL_TGT_ERRORS_REG_TGT_PIF_READ_CROSS_QWRANGE mBIT(5) 5677#define VXGE_HAL_TGT_ERRORS_REG_TGT_KDFC_READ mBIT(6) 5678#define VXGE_HAL_TGT_ERRORS_REG_TGT_USDC_READ mBIT(7) 5679#define VXGE_HAL_TGT_ERRORS_REG_TGT_USDC_WR_CROSS_QWRANGE mBIT(8) 5680#define VXGE_HAL_TGT_ERRORS_REG_TGT_MSIX_BEYOND_RANGE mBIT(9) 5681#define VXGE_HAL_TGT_ERRORS_REG_TGT_WR_TO_KDFC_POISON mBIT(10) 5682#define VXGE_HAL_TGT_ERRORS_REG_TGT_WR_TO_USDC_POISON mBIT(11) 5683#define VXGE_HAL_TGT_ERRORS_REG_TGT_WR_TO_PIF_POISON mBIT(12) 5684#define VXGE_HAL_TGT_ERRORS_REG_TGT_WR_TO_MSIX_POISON mBIT(13) 5685#define VXGE_HAL_TGT_ERRORS_REG_TGT_WR_TO_MRIOV_POISON mBIT(14) 5686#define VXGE_HAL_TGT_ERRORS_REG_TGT_NOT_MEM_TLP mBIT(15) 5687#define VXGE_HAL_TGT_ERRORS_REG_TGT_UNKNOWN_MEM_TLP mBIT(16) 5688#define VXGE_HAL_TGT_ERRORS_REG_TGT_REQ_FSM_ERR mBIT(17) 5689#define VXGE_HAL_TGT_ERRORS_REG_TGT_CPL_FSM_ERR mBIT(18) 5690#define VXGE_HAL_TGT_ERRORS_REG_TGT_KDFC_PROT_ERR mBIT(19) 5691#define VXGE_HAL_TGT_ERRORS_REG_TGT_SWIF_PROT_ERR mBIT(20) 5692#define VXGE_HAL_TGT_ERRORS_REG_TGT_MRIOV_MEM_MAP_CFG_ERR mBIT(21) 5693/* 0x07060 */ u64 tgt_errors_mask; 5694/* 0x07068 */ u64 tgt_errors_alarm; 5695/* 0x07070 */ u64 config_errors_reg; 5696#define VXGE_HAL_CONFIG_ERRORS_REG_I2C_ILLEGAL_STOP_COND mBIT(3) 5697#define VXGE_HAL_CONFIG_ERRORS_REG_I2C_ILLEGAL_START_COND mBIT(7) 5698#define VXGE_HAL_CONFIG_ERRORS_REG_I2C_EXP_RD_CNT mBIT(11) 5699#define VXGE_HAL_CONFIG_ERRORS_REG_I2C_EXTRA_CYCLE mBIT(15) 5700#define VXGE_HAL_CONFIG_ERRORS_REG_I2C_MAIN_FSM_ERR mBIT(19) 5701#define VXGE_HAL_CONFIG_ERRORS_REG_I2C_REQ_COLLISION mBIT(23) 5702#define VXGE_HAL_CONFIG_ERRORS_REG_I2C_REG_FSM_ERR mBIT(27) 5703#define VXGE_HAL_CONFIG_ERRORS_REG_CFGM_I2C_TIMEOUT mBIT(31) 5704#define VXGE_HAL_CONFIG_ERRORS_REG_RIC_I2C_TIMEOUT mBIT(35) 5705#define VXGE_HAL_CONFIG_ERRORS_REG_CFGM_FSM_ERR mBIT(39) 5706#define VXGE_HAL_CONFIG_ERRORS_REG_RIC_FSM_ERR mBIT(43) 5707#define VXGE_HAL_CONFIG_ERRORS_REG_PIFM_ILLEGAL_ACCESS mBIT(47) 5708#define VXGE_HAL_CONFIG_ERRORS_REG_PIFM_TIMEOUT mBIT(51) 5709#define VXGE_HAL_CONFIG_ERRORS_REG_PIFM_FSM_ERR mBIT(55) 5710#define VXGE_HAL_CONFIG_ERRORS_REG_PIFM_TO_FSM_ERR mBIT(59) 5711#define VXGE_HAL_CONFIG_ERRORS_REG_RIC_RIC_RD_TIMEOUT mBIT(63) 5712/* 0x07078 */ u64 config_errors_mask; 5713/* 0x07080 */ u64 config_errors_alarm; 5714 u8 unused07090[0x07090 - 0x07088]; 5715 5716/* 0x07090 */ u64 crdt_errors_reg; 5717#define VXGE_HAL_CRDT_ERRORS_REG_WRCRDTARB_FSM_ERR mBIT(11) 5718#define VXGE_HAL_CRDT_ERRORS_REG_WRCRDTARB_INTCTL_ILLEGAL_CRD_DEAL mBIT(15) 5719#define VXGE_HAL_CRDT_ERRORS_REG_WRCRDTARB_PDA_ILLEGAL_CRD_DEAL mBIT(19) 5720#define VXGE_HAL_CRDT_ERRORS_REG_WRCRDTARB_PCI_MSG_ILLEGAL_CRD_DEAL mBIT(23) 5721#define VXGE_HAL_CRDT_ERRORS_REG_RDCRDTARB_FSM_ERR mBIT(35) 5722#define VXGE_HAL_CRDT_ERRORS_REG_RDCRDTARB_RDA_ILLEGAL_CRD_DEAL mBIT(39) 5723#define VXGE_HAL_CRDT_ERRORS_REG_RDCRDTARB_PDA_ILLEGAL_CRD_DEAL mBIT(43) 5724#define VXGE_HAL_CRDT_ERRORS_REG_RDCRDTARB_DBLGEN_ILLEGAL_CRD_DEAL mBIT(47) 5725/* 0x07098 */ u64 crdt_errors_mask; 5726/* 0x070a0 */ u64 crdt_errors_alarm; 5727 u8 unused070b0[0x070b0 - 0x070a8]; 5728 5729/* 0x070b0 */ u64 mrpcim_general_errors_reg; 5730#define VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_STATSB_FSM_ERR mBIT(3) 5731#define VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_XGEN_FSM_ERR mBIT(7) 5732#define VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_XMEM_FSM_ERR mBIT(11) 5733#define VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_KDFCCTL_FSM_ERR mBIT(15) 5734#define VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_MRIOVCTL_FSM_ERR mBIT(19) 5735#define VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_SPI_FLSH_ERR mBIT(23) 5736#define VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_SPI_IIC_ACK_ERR mBIT(27) 5737#define VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_SPI_IIC_CHKSUM_ERR mBIT(31) 5738#define VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_INI_SERR_DET mBIT(35) 5739#define VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_INTCTL_MSIX_FSM_ERR mBIT(39) 5740#define VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_INTCTL_MSI_OVERFLOW mBIT(43) 5741#define VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_PPIF_PCI_NOT_FLUSH_SW_RESET\ 5742 mBIT(47) 5743#define VXGE_HAL_MRPCIM_GENERAL_ERRORS_REG_PPIF_SW_RESET_FSM_ERR mBIT(51) 5744/* 0x070b8 */ u64 mrpcim_general_errors_mask; 5745/* 0x070c0 */ u64 mrpcim_general_errors_alarm; 5746 u8 unused070d0[0x070d0 - 0x070c8]; 5747 5748/* 0x070d0 */ u64 pll_errors_reg; 5749#define VXGE_HAL_PLL_ERRORS_REG_CORE_CMG_PLL_OOL mBIT(3) 5750#define VXGE_HAL_PLL_ERRORS_REG_CORE_FB_PLL_OOL mBIT(7) 5751#define VXGE_HAL_PLL_ERRORS_REG_CORE_X_PLL_OOL mBIT(11) 5752/* 0x070d8 */ u64 pll_errors_mask; 5753/* 0x070e0 */ u64 pll_errors_alarm; 5754/* 0x070e8 */ u64 srpcim_to_mrpcim_alarm_reg; 5755#define VXGE_HAL_SRPCIM_TO_MRPCIM_ALARM_REG_ALARM(val) vBIT(val, 0, 17) 5756/* 0x070f0 */ u64 srpcim_to_mrpcim_alarm_mask; 5757/* 0x070f8 */ u64 srpcim_to_mrpcim_alarm_alarm; 5758/* 0x07100 */ u64 vpath_to_mrpcim_alarm_reg; 5759#define VXGE_HAL_VPATH_TO_MRPCIM_ALARM_REG_ALARM(val) vBIT(val, 0, 17) 5760/* 0x07108 */ u64 vpath_to_mrpcim_alarm_mask; 5761/* 0x07110 */ u64 vpath_to_mrpcim_alarm_alarm; 5762 u8 unused07128[0x07128 - 0x07118]; 5763 5764/* 0x07128 */ u64 crdt_errors_vplane_reg[17]; 5765#define VXGE_HAL_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_H_CONSUME_CRDT_ERR mBIT(3) 5766#define VXGE_HAL_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_D_CONSUME_CRDT_ERR mBIT(7) 5767#define VXGE_HAL_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_H_RETURN_CRDT_ERR mBIT(11) 5768#define VXGE_HAL_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_D_RETURN_CRDT_ERR mBIT(15) 5769#define VXGE_HAL_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_NP_H_CONSUME_CRDT_ERR mBIT(19) 5770#define VXGE_HAL_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_NP_H_RETURN_CRDT_ERR mBIT(23) 5771#define VXGE_HAL_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_TAG_CONSUME_TAG_ERR mBIT(27) 5772#define VXGE_HAL_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_TAG_RETURN_TAG_ERR mBIT(31) 5773/* 0x07130 */ u64 crdt_errors_vplane_mask[17]; 5774/* 0x07138 */ u64 crdt_errors_vplane_alarm[17]; 5775 u8 unused072f0[0x072f0 - 0x072c0]; 5776 5777/* 0x072f0 */ u64 mrpcim_rst_in_prog; 5778#define VXGE_HAL_MRPCIM_RST_IN_PROG_MRPCIM_RST_IN_PROG mBIT(7) 5779/* 0x072f8 */ u64 mrpcim_reg_modified; 5780#define VXGE_HAL_MRPCIM_REG_MODIFIED_MRPCIM_REG_MODIFIED mBIT(7) 5781/* 0x07300 */ u64 split_table_status1; 5782#define VXGE_HAL_SPLIT_TABLE_STATUS1_SCPL_TAG_ENTRY1(val) vBIT(val, 0, 64) 5783/* 0x07308 */ u64 split_table_status2; 5784#define VXGE_HAL_SPLIT_TABLE_STATUS2_SCPL_TAG_ENTRY2(val) vBIT(val, 0, 64) 5785/* 0x07310 */ u64 split_table_status3; 5786#define VXGE_HAL_SPLIT_TABLE_STATUS3_SCPL_TAG_ENTRY3(val) vBIT(val, 0, 64) 5787/* 0x07318 */ u64 mrpcim_general_status1; 5788#define VXGE_HAL_MRPCIM_GENERAL_STATUS1_INI_RCPL_ERRSYND(val) vBIT(val, 0, 8) 5789#define VXGE_HAL_MRPCIM_GENERAL_STATUS1_XGMAC_MISC_INT_ALARM mBIT(11) 5790#define VXGE_HAL_MRPCIM_GENERAL_STATUS1_SCPL_NUM_OUTSTANDING_RDS(val)\ 5791 vBIT(val, 18, 6) 5792#define VXGE_HAL_MRPCIM_GENERAL_STATUS1_TGT_VENDOR_MSG_PAYLOAD(val)\ 5793 vBIT(val, 32, 32) 5794/* 0x07320 */ u64 mrpcim_general_status2; 5795#define VXGE_HAL_MRPCIM_GENERAL_STATUS2_CFGM_TIMEOUT_ADDR(val) vBIT(val, 6, 10) 5796#define VXGE_HAL_MRPCIM_GENERAL_STATUS2_RIC_TIMEOUT_ADDR(val) vBIT(val, 22, 10) 5797#define VXGE_HAL_MRPCIM_GENERAL_STATUS2_PIFM_ILLEGAL_CLIENT(val)\ 5798 vBIT(val, 34, 2) 5799#define VXGE_HAL_MRPCIM_GENERAL_STATUS2_PIFM_ILLEGAL_RD_WRN mBIT(39) 5800#define VXGE_HAL_MRPCIM_GENERAL_STATUS2_PIFM_ILLEGAL_ADDR(val) vBIT(val, 44, 20) 5801/* 0x07328 */ u64 mrpcim_general_status3; 5802#define VXGE_HAL_MRPCIM_GENERAL_STATUS3_PIFM_TIMEOUT_ADDR(val) vBIT(val, 0, 20) 5803#define VXGE_HAL_MRPCIM_GENERAL_STATUS3_TGT_NOT_MEM_TLP_FMT(val)\ 5804 vBIT(val, 21, 2) 5805#define VXGE_HAL_MRPCIM_GENERAL_STATUS3_TGT_NOT_MEM_TLP_TYPE(val)\ 5806 vBIT(val, 23, 5) 5807#define VXGE_HAL_MRPCIM_GENERAL_STATUS3_TGT_UNKNOWN_MEM_TLP_FMT(val)\ 5808 vBIT(val, 29, 2) 5809#define VXGE_HAL_MRPCIM_GENERAL_STATUS3_TGT_UNKNOWN_MEM_TLP_TYPE(val)\ 5810 vBIT(val, 31, 5) 5811#define VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE0\ 5812 mBIT(40) 5813#define VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE1\ 5814 mBIT(41) 5815#define VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE2\ 5816 mBIT(42) 5817#define VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE3\ 5818 mBIT(43) 5819#define VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE4\ 5820 mBIT(44) 5821#define VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE5\ 5822 mBIT(45) 5823#define VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE6\ 5824 mBIT(46) 5825#define VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE7\ 5826 mBIT(47) 5827#define VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE8\ 5828 mBIT(48) 5829#define VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE9\ 5830 mBIT(49) 5831#define VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE10\ 5832 mBIT(50) 5833#define VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE11\ 5834 mBIT(51) 5835#define VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE12\ 5836 mBIT(52) 5837#define VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE13\ 5838 mBIT(53) 5839#define VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE14\ 5840 mBIT(54) 5841#define VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE15\ 5842 mBIT(55) 5843#define VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_TAGS_FOR_VPLANE16\ 5844 mBIT(56) 5845#define VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_TAGS_DEPLETED mBIT(60) 5846#define VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_RDA_TAGS mBIT(61) 5847#define VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_PDA_TAGS mBIT(62) 5848#define VXGE_HAL_MRPCIM_GENERAL_STATUS3_RDCRDTARB_REACHED_MAX_DBLGEN_TAGS\ 5849 mBIT(63) 5850 u8 unused07338[0x07338 - 0x07330]; 5851 5852/* 0x07338 */ u64 test_status; 5853#define VXGE_HAL_TEST_STATUS_PERR_INS_TX_WR_EP_DONE mBIT(3) 5854#define VXGE_HAL_TEST_STATUS_PERR_INS_TX_RD_EP_DONE mBIT(7) 5855#define VXGE_HAL_TEST_STATUS_PERR_INS_TX_CPL_EP_DONE mBIT(11) 5856#define VXGE_HAL_TEST_STATUS_PERR_INS_TX_ECRCERR_DONE mBIT(15) 5857#define VXGE_HAL_TEST_STATUS_PERR_INS_TX_LCRCERR_DONE mBIT(19) 5858#define VXGE_HAL_TEST_STATUS_PERR_INS_RX_ECRCERR_DONE mBIT(23) 5859#define VXGE_HAL_TEST_STATUS_PERR_INS_RX_LCRCERR_DONE mBIT(27) 5860 u8 unused07348[0x07348 - 0x07340]; 5861 5862/* 0x07348 */ u64 kdfcctl_dbg_status; 5863#define VXGE_HAL_KDFCCTL_DBG_STATUS_KDFCCTL_ADDR_ERR(val) vBIT(val, 2, 22) 5864#define VXGE_HAL_KDFCCTL_DBG_STATUS_KDFCCTL_FIFO_NO_ERR(val) vBIT(val, 26, 6) 5865/* 0x07350 */ u64 msix_addr; 5866#define VXGE_HAL_MSIX_ADDR_MSIX_ADDR(val) vBIT(val, 0, 64) 5867/* 0x07358 */ u64 msix_table; 5868#define VXGE_HAL_MSIX_TABLE_DATA(val) vBIT(val, 0, 32) 5869#define VXGE_HAL_MSIX_TABLE_MASK mBIT(63) 5870/* 0x07360 */ u64 msix_ctl; 5871#define VXGE_HAL_MSIX_CTL_VECTOR_NO(val) vBIT(val, 1, 7) 5872#define VXGE_HAL_MSIX_CTL_WRITE_OR_READ mBIT(15) 5873/* 0x07368 */ u64 msix_access_table; 5874#define VXGE_HAL_MSIX_ACCESS_TABLE_MSIX_ACCESS_TABLE mBIT(0) 5875 u8 unused07378[0x07378 - 0x07370]; 5876 5877/* 0x07378 */ u64 write_arb_pending; 5878#define VXGE_HAL_WRITE_ARB_PENDING_WRARB_WRDMA mBIT(3) 5879#define VXGE_HAL_WRITE_ARB_PENDING_WRARB_RTDMA mBIT(7) 5880#define VXGE_HAL_WRITE_ARB_PENDING_WRARB_MSG mBIT(11) 5881#define VXGE_HAL_WRITE_ARB_PENDING_WRARB_STATSB mBIT(15) 5882#define VXGE_HAL_WRITE_ARB_PENDING_WRARB_INTCTL mBIT(19) 5883/* 0x07380 */ u64 read_arb_pending; 5884#define VXGE_HAL_READ_ARB_PENDING_RDARB_WRDMA mBIT(3) 5885#define VXGE_HAL_READ_ARB_PENDING_RDARB_RTDMA mBIT(7) 5886#define VXGE_HAL_READ_ARB_PENDING_RDARB_DBLGEN mBIT(11) 5887/* 0x07388 */ u64 dmaif_dmadbl_pending; 5888#define VXGE_HAL_DMAIF_DMADBL_PENDING_DMAIF_WRDMA_WR mBIT(0) 5889#define VXGE_HAL_DMAIF_DMADBL_PENDING_DMAIF_WRDMA_RD mBIT(1) 5890#define VXGE_HAL_DMAIF_DMADBL_PENDING_DMAIF_RTDMA_WR mBIT(2) 5891#define VXGE_HAL_DMAIF_DMADBL_PENDING_DMAIF_RTDMA_RD mBIT(3) 5892#define VXGE_HAL_DMAIF_DMADBL_PENDING_DMAIF_MSG_WR mBIT(4) 5893#define VXGE_HAL_DMAIF_DMADBL_PENDING_DMAIF_STATS_WR mBIT(5) 5894#define VXGE_HAL_DMAIF_DMADBL_PENDING_DBLGEN_IN_PROG(val) vBIT(val, 13, 51) 5895/* 0x07390 */ u64 wrcrdtarb_status0_vplane[17]; 5896#define VXGE_HAL_WRCRDTARB_STATUS0_VPLANE_WRCRDTARB_ABS_AVAIL_P_H(val)\ 5897 vBIT(val, 0, 8) 5898/* 0x07418 */ u64 wrcrdtarb_status1_vplane[17]; 5899#define VXGE_HAL_WRCRDTARB_STATUS1_VPLANE_WRCRDTARB_ABS_AVAIL_P_D(val)\ 5900 vBIT(val, 4, 12) 5901 u8 unused07500[0x07500 - 0x074a0]; 5902 5903/* 0x07500 */ u64 mrpcim_general_cfg1; 5904#define VXGE_HAL_MRPCIM_GENERAL_CFG1_CLEAR_SERR mBIT(7) 5905/* 0x07508 */ u64 mrpcim_general_cfg2; 5906#define VXGE_HAL_MRPCIM_GENERAL_CFG2_INS_TX_WR_TD mBIT(3) 5907#define VXGE_HAL_MRPCIM_GENERAL_CFG2_INS_TX_RD_TD mBIT(7) 5908#define VXGE_HAL_MRPCIM_GENERAL_CFG2_INS_TX_CPL_TD mBIT(11) 5909#define VXGE_HAL_MRPCIM_GENERAL_CFG2_INI_TIMEOUT_EN_MWR mBIT(15) 5910#define VXGE_HAL_MRPCIM_GENERAL_CFG2_INI_TIMEOUT_EN_MRD mBIT(19) 5911#define VXGE_HAL_MRPCIM_GENERAL_CFG2_IGNORE_VPATH_RST_FOR_MSIX mBIT(23) 5912#define VXGE_HAL_MRPCIM_GENERAL_CFG2_FLASH_READ_MSB mBIT(27) 5913#define VXGE_HAL_MRPCIM_GENERAL_CFG2_DIS_HOST_PIPELINE_WR mBIT(31) 5914#define VXGE_HAL_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_ENABLE mBIT(43) 5915#define VXGE_HAL_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_MAP_TO_VPATH(val)\ 5916 vBIT(val, 47, 5) 5917#define VXGE_HAL_MRPCIM_GENERAL_CFG2_EN_BLOCK_MSIX_DUE_TO_SERR mBIT(55) 5918#define VXGE_HAL_MRPCIM_GENERAL_CFG2_FORCE_SENDING_INTA mBIT(59) 5919#define VXGE_HAL_MRPCIM_GENERAL_CFG2_DIS_SWIF_PROT_ON_RDS mBIT(63) 5920/* 0x07510 */ u64 mrpcim_general_cfg3; 5921#define VXGE_HAL_MRPCIM_GENERAL_CFG3_PROTECTION_CA_OR_UNSUPN mBIT(0) 5922#define VXGE_HAL_MRPCIM_GENERAL_CFG3_ILLEGAL_RD_CA_OR_UNSUPN mBIT(3) 5923#define VXGE_HAL_MRPCIM_GENERAL_CFG3_RD_BYTE_SWAPEN mBIT(7) 5924#define VXGE_HAL_MRPCIM_GENERAL_CFG3_RD_BIT_FLIPEN mBIT(11) 5925#define VXGE_HAL_MRPCIM_GENERAL_CFG3_WR_BYTE_SWAPEN mBIT(15) 5926#define VXGE_HAL_MRPCIM_GENERAL_CFG3_WR_BIT_FLIPEN mBIT(19) 5927#define VXGE_HAL_MRPCIM_GENERAL_CFG3_MR_MAX_MVFS(val) vBIT(val, 20, 16) 5928#define VXGE_HAL_MRPCIM_GENERAL_CFG3_MR_MVF_TBL_SIZE(val) vBIT(val, 36, 16) 5929#define VXGE_HAL_MRPCIM_GENERAL_CFG3_PF0_SW_RESET_EN mBIT(55) 5930#define VXGE_HAL_MRPCIM_GENERAL_CFG3_REG_MODIFIED_CFG(val) vBIT(val, 56, 2) 5931#define VXGE_HAL_MRPCIM_GENERAL_CFG3_CPL_ECC_ENABLE_N mBIT(59) 5932#define VXGE_HAL_MRPCIM_GENERAL_CFG3_BYPASS_DAISY_CHAIN mBIT(63) 5933/* 0x07518 */ u64 mrpcim_stats_start_host_addr; 5934#define VXGE_HAL_MRPCIM_STATS_START_HOST_ADDR_MRPCIM_STATS_START_HOST_ADDR(val)\ 5935 vBIT(val, 0, 57) 5936/* 0x07520 */ u64 asic_mode; 5937#define VXGE_HAL_ASIC_MODE_PIC(val) vBIT(val, 2, 2) 5938/* 0x07528 */ u64 dis_fw_pipeline_wr; 5939#define VXGE_HAL_DIS_FW_PIPELINE_WR_DIS_FW_PIPELINE_WR mBIT(0) 5940/* 0x07530 */ u64 ini_timeout_val; 5941#define VXGE_HAL_INI_TIMEOUT_VAL_MWR(val) vBIT(val, 0, 32) 5942#define VXGE_HAL_INI_TIMEOUT_VAL_MRD(val) vBIT(val, 32, 32) 5943/* 0x07538 */ u64 pic_arbiter_cfg; 5944#define VXGE_HAL_PIC_ARBITER_CFG_DMA_READ_EN mBIT(3) 5945#define VXGE_HAL_PIC_ARBITER_CFG_DMA_WRITE_EN mBIT(7) 5946#define VXGE_HAL_PIC_ARBITER_CFG_DBLGEN_WRR_EN mBIT(11) 5947#define VXGE_HAL_PIC_ARBITER_CFG_WRCRDTARB_EN mBIT(15) 5948#define VXGE_HAL_PIC_ARBITER_CFG_RDCRDTARB_EN mBIT(19) 5949/* 0x07540 */ u64 read_arbiter; 5950#define VXGE_HAL_READ_ARBITER_WRDMA_PRIORITY(val) vBIT(val, 2, 2) 5951#define VXGE_HAL_READ_ARBITER_RTDMA_PRIORITY(val) vBIT(val, 6, 2) 5952#define VXGE_HAL_READ_ARBITER_DBLGEN_PRIORITY(val) vBIT(val, 10, 2) 5953#define VXGE_HAL_READ_ARBITER_CALSTATE0_PRIORITY(val) vBIT(val, 14, 2) 5954#define VXGE_HAL_READ_ARBITER_CALSTATE1_PRIORITY(val) vBIT(val, 18, 2) 5955#define VXGE_HAL_READ_ARBITER_CALSTATE2_PRIORITY(val) vBIT(val, 22, 2) 5956#define VXGE_HAL_READ_ARBITER_CALSTATE3_PRIORITY(val) vBIT(val, 26, 2) 5957#define VXGE_HAL_READ_ARBITER_CALSTATE4_PRIORITY(val) vBIT(val, 30, 2) 5958#define VXGE_HAL_READ_ARBITER_CALSTATE5_PRIORITY(val) vBIT(val, 34, 2) 5959#define VXGE_HAL_READ_ARBITER_CHECK_PRIORITY_MATCH_ONLY mBIT(39) 5960/* 0x07548 */ u64 write_arbiter; 5961#define VXGE_HAL_WRITE_ARBITER_WRDMA_PRIORITY(val) vBIT(val, 2, 2) 5962#define VXGE_HAL_WRITE_ARBITER_RTDMA_PRIORITY(val) vBIT(val, 6, 2) 5963#define VXGE_HAL_WRITE_ARBITER_STATS_PRIORITY(val) vBIT(val, 10, 2) 5964#define VXGE_HAL_WRITE_ARBITER_MSG_PRIORITY(val) vBIT(val, 14, 2) 5965#define VXGE_HAL_WRITE_ARBITER_CALSTATE0_PRIORITY(val) vBIT(val, 18, 2) 5966#define VXGE_HAL_WRITE_ARBITER_CALSTATE1_PRIORITY(val) vBIT(val, 22, 2) 5967#define VXGE_HAL_WRITE_ARBITER_CALSTATE2_PRIORITY(val) vBIT(val, 26, 2) 5968#define VXGE_HAL_WRITE_ARBITER_CALSTATE3_PRIORITY(val) vBIT(val, 30, 2) 5969#define VXGE_HAL_WRITE_ARBITER_CALSTATE4_PRIORITY(val) vBIT(val, 34, 2) 5970#define VXGE_HAL_WRITE_ARBITER_CALSTATE5_PRIORITY(val) vBIT(val, 38, 2) 5971#define VXGE_HAL_WRITE_ARBITER_CALSTATE6_PRIORITY(val) vBIT(val, 42, 2) 5972#define VXGE_HAL_WRITE_ARBITER_CALSTATE7_PRIORITY(val) vBIT(val, 46, 2) 5973#define VXGE_HAL_WRITE_ARBITER_CALSTATE8_PRIORITY(val) vBIT(val, 50, 2) 5974#define VXGE_HAL_WRITE_ARBITER_CALSTATE9_PRIORITY(val) vBIT(val, 52, 2) 5975#define VXGE_HAL_WRITE_ARBITER_CHECK_PRIORITY_MATCH_ONLY mBIT(55) 5976/* 0x07550 */ u64 adapter_control; 5977#define VXGE_HAL_ADAPTER_CONTROL_ADAPTER_EN mBIT(7) 5978#define VXGE_HAL_ADAPTER_CONTROL_DISABLE_RIC mBIT(49) 5979#define VXGE_HAL_ADAPTER_CONTROL_ECC_ENABLE_N mBIT(55) 5980/* 0x07558 */ u64 program_cfg0; 5981#define VXGE_HAL_PROGRAM_CFG0_I2C_SLAVE_ADDR(val) vBIT(val, 1, 7) 5982#define VXGE_HAL_PROGRAM_CFG0_CFGM_TIMEOUT_EN mBIT(11) 5983#define VXGE_HAL_PROGRAM_CFG0_PIFM_TIMEOUT_EN mBIT(15) 5984/* 0x07560 */ u64 program_cfg1; 5985#define VXGE_HAL_PROGRAM_CFG1_CFGM_TIMEOUT_LOAD_VAL(val) vBIT(val, 0, 32) 5986#define VXGE_HAL_PROGRAM_CFG1_PIFM_TIMEOUT_LOAD_VAL(val) vBIT(val, 32, 32) 5987/* 0x07568 */ u64 dblgen_wrr_cfg1; 5988#define VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_0_NUM(val) vBIT(val, 3, 5) 5989#define VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_1_NUM(val) vBIT(val, 11, 5) 5990#define VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_2_NUM(val) vBIT(val, 19, 5) 5991#define VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_3_NUM(val) vBIT(val, 27, 5) 5992#define VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_4_NUM(val) vBIT(val, 35, 5) 5993#define VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_5_NUM(val) vBIT(val, 43, 5) 5994#define VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_6_NUM(val) vBIT(val, 51, 5) 5995#define VXGE_HAL_DBLGEN_WRR_CFG1_CTRL_SS_7_NUM(val) vBIT(val, 59, 5) 5996/* 0x07570 */ u64 dblgen_wrr_cfg2; 5997#define VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_8_NUM(val) vBIT(val, 3, 5) 5998#define VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_9_NUM(val) vBIT(val, 11, 5) 5999#define VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_10_NUM(val) vBIT(val, 19, 5) 6000#define VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_11_NUM(val) vBIT(val, 27, 5) 6001#define VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_12_NUM(val) vBIT(val, 35, 5) 6002#define VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_13_NUM(val) vBIT(val, 43, 5) 6003#define VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_14_NUM(val) vBIT(val, 51, 5) 6004#define VXGE_HAL_DBLGEN_WRR_CFG2_CTRL_SS_15_NUM(val) vBIT(val, 59, 5) 6005/* 0x07578 */ u64 dblgen_wrr_cfg3; 6006#define VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_16_NUM(val) vBIT(val, 3, 5) 6007#define VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_17_NUM(val) vBIT(val, 11, 5) 6008#define VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_18_NUM(val) vBIT(val, 19, 5) 6009#define VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_19_NUM(val) vBIT(val, 27, 5) 6010#define VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_20_NUM(val) vBIT(val, 35, 5) 6011#define VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_21_NUM(val) vBIT(val, 43, 5) 6012#define VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_22_NUM(val) vBIT(val, 51, 5) 6013#define VXGE_HAL_DBLGEN_WRR_CFG3_CTRL_SS_23_NUM(val) vBIT(val, 59, 5) 6014/* 0x07580 */ u64 dblgen_wrr_cfg4; 6015#define VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_24_NUM(val) vBIT(val, 3, 5) 6016#define VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_25_NUM(val) vBIT(val, 11, 5) 6017#define VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_26_NUM(val) vBIT(val, 19, 5) 6018#define VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_27_NUM(val) vBIT(val, 27, 5) 6019#define VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_28_NUM(val) vBIT(val, 35, 5) 6020#define VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_29_NUM(val) vBIT(val, 43, 5) 6021#define VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_30_NUM(val) vBIT(val, 51, 5) 6022#define VXGE_HAL_DBLGEN_WRR_CFG4_CTRL_SS_31_NUM(val) vBIT(val, 59, 5) 6023/* 0x07588 */ u64 dblgen_wrr_cfg5; 6024#define VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_32_NUM(val) vBIT(val, 3, 5) 6025#define VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_33_NUM(val) vBIT(val, 11, 5) 6026#define VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_34_NUM(val) vBIT(val, 19, 5) 6027#define VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_35_NUM(val) vBIT(val, 27, 5) 6028#define VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_36_NUM(val) vBIT(val, 35, 5) 6029#define VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_37_NUM(val) vBIT(val, 43, 5) 6030#define VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_38_NUM(val) vBIT(val, 51, 5) 6031#define VXGE_HAL_DBLGEN_WRR_CFG5_CTRL_SS_39_NUM(val) vBIT(val, 59, 5) 6032/* 0x07590 */ u64 dblgen_wrr_cfg6; 6033#define VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_40_NUM(val) vBIT(val, 3, 5) 6034#define VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_41_NUM(val) vBIT(val, 11, 5) 6035#define VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_42_NUM(val) vBIT(val, 19, 5) 6036#define VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_43_NUM(val) vBIT(val, 27, 5) 6037#define VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_44_NUM(val) vBIT(val, 35, 5) 6038#define VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_45_NUM(val) vBIT(val, 43, 5) 6039#define VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_46_NUM(val) vBIT(val, 51, 5) 6040#define VXGE_HAL_DBLGEN_WRR_CFG6_CTRL_SS_47_NUM(val) vBIT(val, 59, 5) 6041/* 0x07598 */ u64 dblgen_wrr_cfg7; 6042#define VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_48_NUM(val) vBIT(val, 3, 5) 6043#define VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_49_NUM(val) vBIT(val, 11, 5) 6044#define VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_50_NUM(val) vBIT(val, 19, 5) 6045#define VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_51_NUM(val) vBIT(val, 27, 5) 6046#define VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_52_NUM(val) vBIT(val, 35, 5) 6047#define VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_53_NUM(val) vBIT(val, 43, 5) 6048#define VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_54_NUM(val) vBIT(val, 51, 5) 6049#define VXGE_HAL_DBLGEN_WRR_CFG7_CTRL_SS_55_NUM(val) vBIT(val, 59, 5) 6050/* 0x075a0 */ u64 dblgen_wrr_cfg8; 6051#define VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_56_NUM(val) vBIT(val, 3, 5) 6052#define VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_57_NUM(val) vBIT(val, 11, 5) 6053#define VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_58_NUM(val) vBIT(val, 19, 5) 6054#define VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_59_NUM(val) vBIT(val, 27, 5) 6055#define VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_60_NUM(val) vBIT(val, 35, 5) 6056#define VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_61_NUM(val) vBIT(val, 43, 5) 6057#define VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_62_NUM(val) vBIT(val, 51, 5) 6058#define VXGE_HAL_DBLGEN_WRR_CFG8_CTRL_SS_63_NUM(val) vBIT(val, 59, 5) 6059/* 0x075a8 */ u64 dblgen_wrr_cfg9; 6060#define VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_64_NUM(val) vBIT(val, 3, 5) 6061#define VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_65_NUM(val) vBIT(val, 11, 5) 6062#define VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_66_NUM(val) vBIT(val, 19, 5) 6063#define VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_67_NUM(val) vBIT(val, 27, 5) 6064#define VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_68_NUM(val) vBIT(val, 35, 5) 6065#define VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_69_NUM(val) vBIT(val, 43, 5) 6066#define VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_70_NUM(val) vBIT(val, 51, 5) 6067#define VXGE_HAL_DBLGEN_WRR_CFG9_CTRL_SS_71_NUM(val) vBIT(val, 59, 5) 6068/* 0x075b0 */ u64 dblgen_wrr_cfg10; 6069#define VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_72_NUM(val) vBIT(val, 3, 5) 6070#define VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_73_NUM(val) vBIT(val, 11, 5) 6071#define VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_74_NUM(val) vBIT(val, 19, 5) 6072#define VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_75_NUM(val) vBIT(val, 27, 5) 6073#define VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_76_NUM(val) vBIT(val, 35, 5) 6074#define VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_77_NUM(val) vBIT(val, 43, 5) 6075#define VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_78_NUM(val) vBIT(val, 51, 5) 6076#define VXGE_HAL_DBLGEN_WRR_CFG10_CTRL_SS_79_NUM(val) vBIT(val, 59, 5) 6077/* 0x075b8 */ u64 dblgen_wrr_cfg11; 6078#define VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_80_NUM(val) vBIT(val, 3, 5) 6079#define VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_81_NUM(val) vBIT(val, 11, 5) 6080#define VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_82_NUM(val) vBIT(val, 19, 5) 6081#define VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_83_NUM(val) vBIT(val, 27, 5) 6082#define VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_84_NUM(val) vBIT(val, 35, 5) 6083#define VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_85_NUM(val) vBIT(val, 43, 5) 6084#define VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_86_NUM(val) vBIT(val, 51, 5) 6085#define VXGE_HAL_DBLGEN_WRR_CFG11_CTRL_SS_87_NUM(val) vBIT(val, 59, 5) 6086/* 0x075c0 */ u64 dblgen_wrr_cfg12; 6087#define VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_88_NUM(val) vBIT(val, 3, 5) 6088#define VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_89_NUM(val) vBIT(val, 11, 5) 6089#define VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_90_NUM(val) vBIT(val, 19, 5) 6090#define VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_91_NUM(val) vBIT(val, 27, 5) 6091#define VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_92_NUM(val) vBIT(val, 35, 5) 6092#define VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_93_NUM(val) vBIT(val, 43, 5) 6093#define VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_94_NUM(val) vBIT(val, 51, 5) 6094#define VXGE_HAL_DBLGEN_WRR_CFG12_CTRL_SS_95_NUM(val) vBIT(val, 59, 5) 6095/* 0x075c8 */ u64 dblgen_wrr_cfg13; 6096#define VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_96_NUM(val) vBIT(val, 3, 5) 6097#define VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_97_NUM(val) vBIT(val, 11, 5) 6098#define VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_98_NUM(val) vBIT(val, 19, 5) 6099#define VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_99_NUM(val) vBIT(val, 27, 5) 6100#define VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_100_NUM(val) vBIT(val, 35, 5) 6101#define VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_101_NUM(val) vBIT(val, 43, 5) 6102#define VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_102_NUM(val) vBIT(val, 51, 5) 6103#define VXGE_HAL_DBLGEN_WRR_CFG13_CTRL_SS_103_NUM(val) vBIT(val, 59, 5) 6104/* 0x075d0 */ u64 dblgen_wrr_cfg14; 6105#define VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_104_NUM(val) vBIT(val, 3, 5) 6106#define VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_105_NUM(val) vBIT(val, 11, 5) 6107#define VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_106_NUM(val) vBIT(val, 19, 5) 6108#define VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_107_NUM(val) vBIT(val, 27, 5) 6109#define VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_108_NUM(val) vBIT(val, 35, 5) 6110#define VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_109_NUM(val) vBIT(val, 43, 5) 6111#define VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_110_NUM(val) vBIT(val, 51, 5) 6112#define VXGE_HAL_DBLGEN_WRR_CFG14_CTRL_SS_111_NUM(val) vBIT(val, 59, 5) 6113/* 0x075d8 */ u64 dblgen_wrr_cfg15; 6114#define VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_112_NUM(val) vBIT(val, 3, 5) 6115#define VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_113_NUM(val) vBIT(val, 11, 5) 6116#define VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_114_NUM(val) vBIT(val, 19, 5) 6117#define VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_115_NUM(val) vBIT(val, 27, 5) 6118#define VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_116_NUM(val) vBIT(val, 35, 5) 6119#define VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_117_NUM(val) vBIT(val, 43, 5) 6120#define VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_118_NUM(val) vBIT(val, 51, 5) 6121#define VXGE_HAL_DBLGEN_WRR_CFG15_CTRL_SS_119_NUM(val) vBIT(val, 59, 5) 6122/* 0x075e0 */ u64 dblgen_wrr_cfg16; 6123#define VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_120_NUM(val) vBIT(val, 3, 5) 6124#define VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_121_NUM(val) vBIT(val, 11, 5) 6125#define VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_122_NUM(val) vBIT(val, 19, 5) 6126#define VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_123_NUM(val) vBIT(val, 27, 5) 6127#define VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_124_NUM(val) vBIT(val, 35, 5) 6128#define VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_125_NUM(val) vBIT(val, 43, 5) 6129#define VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_126_NUM(val) vBIT(val, 51, 5) 6130#define VXGE_HAL_DBLGEN_WRR_CFG16_CTRL_SS_127_NUM(val) vBIT(val, 59, 5) 6131/* 0x075e8 */ u64 dblgen_wrr_cfg17; 6132#define VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_128_NUM(val) vBIT(val, 3, 5) 6133#define VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_129_NUM(val) vBIT(val, 11, 5) 6134#define VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_130_NUM(val) vBIT(val, 19, 5) 6135#define VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_131_NUM(val) vBIT(val, 27, 5) 6136#define VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_132_NUM(val) vBIT(val, 35, 5) 6137#define VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_133_NUM(val) vBIT(val, 43, 5) 6138#define VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_134_NUM(val) vBIT(val, 51, 5) 6139#define VXGE_HAL_DBLGEN_WRR_CFG17_CTRL_SS_135_NUM(val) vBIT(val, 59, 5) 6140/* 0x075f0 */ u64 dblgen_wrr_cfg18; 6141#define VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_136_NUM(val) vBIT(val, 3, 5) 6142#define VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_137_NUM(val) vBIT(val, 11, 5) 6143#define VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_138_NUM(val) vBIT(val, 19, 5) 6144#define VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_139_NUM(val) vBIT(val, 27, 5) 6145#define VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_140_NUM(val) vBIT(val, 35, 5) 6146#define VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_141_NUM(val) vBIT(val, 43, 5) 6147#define VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_142_NUM(val) vBIT(val, 51, 5) 6148#define VXGE_HAL_DBLGEN_WRR_CFG18_CTRL_SS_143_NUM(val) vBIT(val, 59, 5) 6149/* 0x075f8 */ u64 dblgen_wrr_cfg19; 6150#define VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_144_NUM(val) vBIT(val, 3, 5) 6151#define VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_145_NUM(val) vBIT(val, 11, 5) 6152#define VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_146_NUM(val) vBIT(val, 19, 5) 6153#define VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_147_NUM(val) vBIT(val, 27, 5) 6154#define VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_148_NUM(val) vBIT(val, 35, 5) 6155#define VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_149_NUM(val) vBIT(val, 43, 5) 6156#define VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_150_NUM(val) vBIT(val, 51, 5) 6157#define VXGE_HAL_DBLGEN_WRR_CFG19_CTRL_SS_151_NUM(val) vBIT(val, 59, 5) 6158/* 0x07600 */ u64 dblgen_wrr_cfg20; 6159#define VXGE_HAL_DBLGEN_WRR_CFG20_CTRL_SS_152_NUM(val) vBIT(val, 3, 5) 6160/* 0x07608 */ u64 debug_cfg1; 6161#define VXGE_HAL_DEBUG_CFG1_TAG_TO_OBSERVE(val) vBIT(val, 3, 5) 6162#define VXGE_HAL_DEBUG_CFG1_DIS_REL_OF_TAG_DUE_TO_ERR mBIT(11) 6163 u8 unused07900[0x07900 - 0x07610]; 6164 6165/* 0x07900 */ u64 test_cfg1; 6166#define VXGE_HAL_TEST_CFG1_PERR_INS_TX_WR_EP mBIT(19) 6167#define VXGE_HAL_TEST_CFG1_PERR_INS_TX_RD_EP mBIT(23) 6168#define VXGE_HAL_TEST_CFG1_PERR_INS_TX_CPL_EP mBIT(27) 6169#define VXGE_HAL_TEST_CFG1_PERR_INS_TX_ECRCERR mBIT(31) 6170#define VXGE_HAL_TEST_CFG1_PERR_INS_TX_LCRCERR mBIT(35) 6171#define VXGE_HAL_TEST_CFG1_PERR_INS_RX_ECRCERR mBIT(39) 6172#define VXGE_HAL_TEST_CFG1_PERR_INS_RX_LCRCERR mBIT(43) 6173/* 0x07908 */ u64 test_cfg2; 6174#define VXGE_HAL_TEST_CFG2_PERR_TIMEOUT_VAL(val) vBIT(val, 0, 32) 6175/* 0x07910 */ u64 test_cfg3; 6176#define VXGE_HAL_TEST_CFG3_PERR_TRIGGER_TIMER mBIT(0) 6177/* 0x07918 */ u64 wrcrdtarb_cfg0; 6178#define VXGE_HAL_WRCRDTARB_CFG0_WAIT_CNT(val) vBIT(val, 48, 4) 6179#define VXGE_HAL_WRCRDTARB_CFG0_STATS_PRTY_TIMEOUT_EN mBIT(55) 6180#define VXGE_HAL_WRCRDTARB_CFG0_STATS_DROP_TIMEOUT_EN mBIT(59) 6181#define VXGE_HAL_WRCRDTARB_CFG0_EN_XON mBIT(63) 6182/* 0x07920 */ u64 wrcrdtarb_cfg1; 6183#define VXGE_HAL_WRCRDTARB_CFG1_RST_CREDIT mBIT(0) 6184/* 0x07928 */ u64 wrcrdtarb_cfg2; 6185#define VXGE_HAL_WRCRDTARB_CFG2_STATS_PRTY_TIMEOUT_VAL(val) vBIT(val, 0, 32) 6186#define VXGE_HAL_WRCRDTARB_CFG2_STATS_DROP_TIMEOUT_VAL(val) vBIT(val, 32, 32) 6187/* 0x07930 */ u64 test_wrcrdtarb_cfg1; 6188#define VXGE_HAL_TEST_WRCRDTARB_CFG1_BLOCK_VPLANE_TIMEOUT1_VAL(val)\ 6189 vBIT(val, 0, 32) 6190#define VXGE_HAL_TEST_WRCRDTARB_CFG1_BLOCK_VPLANE_TIMEOUT2_VAL(val)\ 6191 vBIT(val, 32, 32) 6192/* 0x07938 */ u64 test_wrcrdtarb_cfg2; 6193#define VXGE_HAL_TEST_WRCRDTARB_CFG2_BLOCK_VPLANE_TIMEOUT3_VAL(val)\ 6194 vBIT(val, 0, 32) 6195#define VXGE_HAL_TEST_WRCRDTARB_CFG2_BLOCK_VPLANE_TIMEOUT4_VAL(val)\ 6196 vBIT(val, 32, 32) 6197/* 0x07940 */ u64 test_wrcrdtarb_cfg3; 6198#define VXGE_HAL_TEST_WRCRDTARB_CFG3_TIMEOUT1_MAP(val) vBIT(val, 3, 5) 6199#define VXGE_HAL_TEST_WRCRDTARB_CFG3_TIMEOUT2_MAP(val) vBIT(val, 11, 5) 6200#define VXGE_HAL_TEST_WRCRDTARB_CFG3_TIMEOUT3_MAP(val) vBIT(val, 19, 5) 6201#define VXGE_HAL_TEST_WRCRDTARB_CFG3_TIMEOUT4_MAP(val) vBIT(val, 27, 5) 6202/* 0x07948 */ u64 test_wrcrdtarb_cfg4; 6203#define VXGE_HAL_TEST_WRCRDTARB_CFG4_BLOCK_VPLANE_TIMEOUT1_EN mBIT(3) 6204#define VXGE_HAL_TEST_WRCRDTARB_CFG4_BLOCK_VPLANE_TIMEOUT2_EN mBIT(7) 6205#define VXGE_HAL_TEST_WRCRDTARB_CFG4_BLOCK_VPLANE_TIMEOUT3_EN mBIT(11) 6206#define VXGE_HAL_TEST_WRCRDTARB_CFG4_BLOCK_VPLANE_TIMEOUT4_EN mBIT(15) 6207/* 0x07950 */ u64 rdcrdtarb_cfg0; 6208#define VXGE_HAL_RDCRDTARB_CFG0_RDA_MAX_OUTSTANDING_RDS(val) vBIT(val, 18, 6) 6209#define VXGE_HAL_RDCRDTARB_CFG0_PDA_MAX_OUTSTANDING_RDS(val) vBIT(val, 26, 6) 6210#define VXGE_HAL_RDCRDTARB_CFG0_DBLGEN_MAX_OUTSTANDING_RDS(val) vBIT(val, 34, 6) 6211#define VXGE_HAL_RDCRDTARB_CFG0_WAIT_CNT(val) vBIT(val, 48, 4) 6212#define VXGE_HAL_RDCRDTARB_CFG0_MAX_OUTSTANDING_RDS(val) vBIT(val, 54, 6) 6213#define VXGE_HAL_RDCRDTARB_CFG0_EN_XON mBIT(63) 6214/* 0x07958 */ u64 rdcrdtarb_cfg1; 6215#define VXGE_HAL_RDCRDTARB_CFG1_RST_CREDIT mBIT(0) 6216/* 0x07960 */ u64 rdcrdtarb_cfg2; 6217#define VXGE_HAL_RDCRDTARB_CFG2_SOFTNAK_TIMER_VAL_DIV4(val) vBIT(val, 0, 32) 6218/* 0x07968 */ u64 test_rdcrdtarb_cfg1; 6219#define VXGE_HAL_TEST_RDCRDTARB_CFG1_BLOCK_VPLANE_TIMEOUT1_VAL(val)\ 6220 vBIT(val, 0, 32) 6221#define VXGE_HAL_TEST_RDCRDTARB_CFG1_BLOCK_VPLANE_TIMEOUT2_VAL(val)\ 6222 vBIT(val, 32, 32) 6223/* 0x07970 */ u64 test_rdcrdtarb_cfg2; 6224#define VXGE_HAL_TEST_RDCRDTARB_CFG2_BLOCK_VPLANE_TIMEOUT3_VAL(val)\ 6225 vBIT(val, 0, 32) 6226#define VXGE_HAL_TEST_RDCRDTARB_CFG2_BLOCK_VPLANE_TIMEOUT4_VAL(val)\ 6227 vBIT(val, 32, 32) 6228/* 0x07978 */ u64 test_rdcrdtarb_cfg3; 6229#define VXGE_HAL_TEST_RDCRDTARB_CFG3_TIMEOUT1_MAP(val) vBIT(val, 3, 5) 6230#define VXGE_HAL_TEST_RDCRDTARB_CFG3_TIMEOUT2_MAP(val) vBIT(val, 11, 5) 6231#define VXGE_HAL_TEST_RDCRDTARB_CFG3_TIMEOUT3_MAP(val) vBIT(val, 19, 5) 6232#define VXGE_HAL_TEST_RDCRDTARB_CFG3_TIMEOUT4_MAP(val) vBIT(val, 27, 5) 6233/* 0x07980 */ u64 test_rdcrdtarb_cfg4; 6234#define VXGE_HAL_TEST_RDCRDTARB_CFG4_BLOCK_VPLANE_TIMEOUT1_EN mBIT(3) 6235#define VXGE_HAL_TEST_RDCRDTARB_CFG4_BLOCK_VPLANE_TIMEOUT2_EN mBIT(7) 6236#define VXGE_HAL_TEST_RDCRDTARB_CFG4_BLOCK_VPLANE_TIMEOUT3_EN mBIT(11) 6237#define VXGE_HAL_TEST_RDCRDTARB_CFG4_BLOCK_VPLANE_TIMEOUT4_EN mBIT(15) 6238/* 0x07988 */ u64 pic_debug_control; 6239#define VXGE_HAL_PIC_DEBUG_CONTROL_DBG_ALL_CLKA_SEL(val) vBIT(val, 0, 4) 6240#define VXGE_HAL_PIC_DEBUG_CONTROL_DBG_ALL_CLKB_SEL(val) vBIT(val, 4, 4) 6241#define VXGE_HAL_PIC_DEBUG_CONTROL_DBG_ALL_DA_SEL(val) vBIT(val, 10, 6) 6242#define VXGE_HAL_PIC_DEBUG_CONTROL_DBG_ALL_DB_SEL(val) vBIT(val, 18, 6) 6243#define VXGE_HAL_PIC_DEBUG_CONTROL_DBGA_SEL(val) vBIT(val, 28, 4) 6244#define VXGE_HAL_PIC_DEBUG_CONTROL_DBGB_SEL(val) vBIT(val, 32, 4) 6245 u8 unused079d8[0x079d8 - 0x07990]; 6246 6247/* 0x079d8 */ u64 spi_control_3_reg; 6248#define VXGE_HAL_SPI_CONTROL_3_REG_SECTOR_0_WR_EN(val) vBIT(val, 0, 32) 6249/* 0x079e0 */ u64 clock_cfg0; 6250#define VXGE_HAL_CLOCK_CFG0_ONE_LRO_EN mBIT(3) 6251#define VXGE_HAL_CLOCK_CFG0_ONE_IWARP_EN mBIT(7) 6252/* 0x079e8 */ u64 stats_bp_ctrl; 6253#define VXGE_HAL_STATS_BP_CTRL_WR_XON mBIT(7) 6254/* 0x079f0 */ u64 kdfcdma_bp_ctrl; 6255#define VXGE_HAL_KDFCDMA_BP_CTRL_RD_XON mBIT(3) 6256/* 0x079f8 */ u64 intctl_bp_ctrl; 6257#define VXGE_HAL_INTCTL_BP_CTRL_WR_XON mBIT(3) 6258/* 0x07a00 */ u64 vector_srpcim_alarm_map[9]; 6259#define VXGE_HAL_VECTOR_SRPCIM_ALARM_MAP_VECTOR_SRPCIM_ALARM_MAP(val)\ 6260 vBIT(val, 17, 7) 6261 u8 unused07b10[0x07b10 - 0x07a48]; 6262 6263/* 0x07b10 */ u64 vplane_rdcrdtarb_cfg0[17]; 6264#define VXGE_HAL_VPLANE_RDCRDTARB_CFG0_TAGS_THRESHOLD_XOFF(val)\ 6265 vBIT(val, 27, 5) 6266#define VXGE_HAL_VPLANE_RDCRDTARB_CFG0_MAX_OUTSTANDING_RDS(val)\ 6267 vBIT(val, 34, 6) 6268 u8 unused07ba0[0x07ba0 - 0x07b98]; 6269 6270/* 0x07ba0 */ u64 mrpcim_spi_control; 6271#define VXGE_HAL_MRPCIM_SPI_CONTROL_KEY(val) vBIT(val, 0, 4) 6272#define VXGE_HAL_MRPCIM_SPI_CONTROL_SEL1 mBIT(4) 6273#define VXGE_HAL_MRPCIM_SPI_CONTROL_NACK mBIT(5) 6274#define VXGE_HAL_MRPCIM_SPI_CONTROL_DONE mBIT(6) 6275#define VXGE_HAL_MRPCIM_SPI_CONTROL_REQ mBIT(7) 6276#define VXGE_HAL_MRPCIM_SPI_CONTROL_BYTE_CNT(val) vBIT(val, 29, 3) 6277#define VXGE_HAL_MRPCIM_SPI_CONTROL_CMD(val) vBIT(val, 32, 8) 6278#define VXGE_HAL_MRPCIM_SPI_CONTROL_ADD(val) vBIT(val, 40, 24) 6279/* 0x07ba8 */ u64 mrpcim_spi_data; 6280#define VXGE_HAL_MRPCIM_SPI_DATA_SPI_RWDATA(val) vBIT(val, 0, 64) 6281/* 0x07bb0 */ u64 mrpcim_spi_write_protect; 6282#define VXGE_HAL_MRPCIM_SPI_WRITE_PROTECT_HWPE mBIT(7) 6283#define VXGE_HAL_MRPCIM_SPI_WRITE_PROTECT_SPI_16ADDR_EN mBIT(14) 6284#define VXGE_HAL_MRPCIM_SPI_WRITE_PROTECT_SPI_2DEV_EN mBIT(15) 6285#define VXGE_HAL_MRPCIM_SPI_WRITE_PROTECT_SLOWCK mBIT(63) 6286 u8 unused07be0[0x07be0 - 0x07bb8]; 6287 6288/* 0x07be0 */ u64 chip_full_reset; 6289#define VXGE_HAL_CHIP_FULL_RESET_CHIP_FULL_RESET(val) vBIT(val, 0, 8) 6290/* 0x07be8 */ u64 bf_sw_reset; 6291#define VXGE_HAL_BF_SW_RESET_BF_SW_RESET(val) vBIT(val, 0, 8) 6292/* 0x07bf0 */ u64 sw_reset_status; 6293#define VXGE_HAL_SW_RESET_STATUS_RESET_CMPLT mBIT(7) 6294#define VXGE_HAL_SW_RESET_STATUS_INIT_CMPLT mBIT(15) 6295 u8 unused07c28[0x07c20 - 0x07bf8]; 6296 6297/* 0x07c20 */ u64 sw_reset_cfg1; 6298#define VXGE_HAL_SW_RESET_CFG1_TYPE mBIT(0) 6299#define VXGE_HAL_SW_RESET_CFG1_WAIT_TIME_FOR_FLUSH_PCI(val) vBIT(val, 7, 25) 6300#define VXGE_HAL_SW_RESET_CFG1_SOPR_ASSERT_TIME(val) vBIT(val, 32, 4) 6301#define VXGE_HAL_SW_RESET_CFG1_WAIT_TIME_AFTER_RESET(val) vBIT(val, 38, 25) 6302/* 0x07c28 */ u64 ric_timeout; 6303#define VXGE_HAL_RIC_TIMEOUT_EN mBIT(3) 6304#define VXGE_HAL_RIC_TIMEOUT_VAL(val) vBIT(val, 32, 32) 6305/* 0x07c30 */ u64 mrpcim_pci_config_access_cfg1; 6306#define VXGE_HAL_MRPCIM_PCI_CONFIG_ACCESS_CFG1_ADDRESS(val) vBIT(val, 4, 10) 6307#define VXGE_HAL_MRPCIM_PCI_CONFIG_ACCESS_CFG1_VPLANE(val) vBIT(val, 19, 5) 6308#define VXGE_HAL_MRPCIM_PCI_CONFIG_ACCESS_CFG1_FUNC(val) vBIT(val, 27, 5) 6309#define VXGE_HAL_MRPCIM_PCI_CONFIG_ACCESS_CFG1_RD_OR_WRN mBIT(39) 6310/* 0x07c38 */ u64 mrpcim_pci_config_access_cfg2; 6311#define VXGE_HAL_MRPCIM_PCI_CONFIG_ACCESS_CFG2_REQ mBIT(0) 6312/* 0x07c40 */ u64 mrpcim_pci_config_access_status; 6313#define VXGE_HAL_MRPCIM_PCI_CONFIG_ACCESS_STATUS_ACCESS_ERR mBIT(0) 6314#define VXGE_HAL_MRPCIM_PCI_CONFIG_ACCESS_STATUS_DATA(val) vBIT(val, 32, 32) 6315 u8 unused07ca8[0x07ca8 - 0x07c48]; 6316 6317/* 0x07ca8 */ u64 rdcrdtarb_status0_vplane[17]; 6318#define VXGE_HAL_RDCRDTARB_STATUS0_VPLANE_RDCRDTARB_ABS_AVAIL_NP_H(val)\ 6319 vBIT(val, 0, 8) 6320/* 0x07d30 */ u64 mrpcim_debug_stats0; 6321#define VXGE_HAL_MRPCIM_DEBUG_STATS0_INI_WR_DROP(val) vBIT(val, 0, 32) 6322#define VXGE_HAL_MRPCIM_DEBUG_STATS0_INI_RD_DROP(val) vBIT(val, 32, 32) 6323/* 0x07d38 */ u64 mrpcim_debug_stats1_vplane[17]; 6324#define VXGE_HAL_MRPCIM_DEBUG_STATS1_VPLANE_WRCRDTARB_PH_CRDT_DEPLETED(val)\ 6325 vBIT(val, 32, 32) 6326/* 0x07dc0 */ u64 mrpcim_debug_stats2_vplane[17]; 6327#define VXGE_HAL_MRPCIM_DEBUG_STATS2_VPLANE_WRCRDTARB_PD_CRDT_DEPLETED(val)\ 6328 vBIT(val, 32, 32) 6329/* 0x07e48 */ u64 mrpcim_debug_stats3_vplane[17]; 6330#define VXGE_HAL_MRPCIM_DEBUG_STATS3_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED(val)\ 6331 vBIT(val, 32, 32) 6332/* 0x07ed0 */ u64 mrpcim_debug_stats4; 6333#define VXGE_HAL_MRPCIM_DEBUG_STATS4_INI_WR_VPIN_DROP(val) vBIT(val, 0, 32) 6334#define VXGE_HAL_MRPCIM_DEBUG_STATS4_INI_RD_VPIN_DROP(val) vBIT(val, 32, 32) 6335/* 0x07ed8 */ u64 genstats_count01; 6336#define VXGE_HAL_GENSTATS_COUNT01_GENSTATS_COUNT1(val) vBIT(val, 0, 32) 6337#define VXGE_HAL_GENSTATS_COUNT01_GENSTATS_COUNT0(val) vBIT(val, 32, 32) 6338/* 0x07ee0 */ u64 genstats_count23; 6339#define VXGE_HAL_GENSTATS_COUNT23_GENSTATS_COUNT3(val) vBIT(val, 0, 32) 6340#define VXGE_HAL_GENSTATS_COUNT23_GENSTATS_COUNT2(val) vBIT(val, 32, 32) 6341/* 0x07ee8 */ u64 genstats_count4; 6342#define VXGE_HAL_GENSTATS_COUNT4_GENSTATS_COUNT4(val) vBIT(val, 32, 32) 6343/* 0x07ef0 */ u64 genstats_count5; 6344#define VXGE_HAL_GENSTATS_COUNT5_GENSTATS_COUNT5(val) vBIT(val, 32, 32) 6345/* 0x07ef8 */ u64 mrpcim_mmio_cfg1; 6346#define VXGE_HAL_MRPCIM_MMIO_CFG1_WRITE_DATA(val) vBIT(val, 0, 32) 6347#define VXGE_HAL_MRPCIM_MMIO_CFG1_ADDRESS(val) vBIT(val, 34, 6) 6348#define VXGE_HAL_MRPCIM_MMIO_CFG1_MRIOVCTL_READ_DATA(val) vBIT(val, 48, 16) 6349/* 0x07f00 */ u64 mrpcim_mmio_cfg2; 6350#define VXGE_HAL_MRPCIM_MMIO_CFG2_WRITE_CS mBIT(0) 6351/* 0x07f08 */ u64 genstats_cfg[6]; 6352#define VXGE_HAL_GENSTATS_CFG_DTYPE_SEL(val) vBIT(val, 3, 5) 6353#define VXGE_HAL_GENSTATS_CFG_CLIENT_NO_SEL(val) vBIT(val, 9, 3) 6354#define VXGE_HAL_GENSTATS_CFG_WR_RD_CPL_SEL(val) vBIT(val, 14, 2) 6355#define VXGE_HAL_GENSTATS_CFG_VPATH_SEL(val) vBIT(val, 31, 17) 6356/* 0x07f38 */ u64 genstat_64bit_cfg; 6357#define VXGE_HAL_GENSTAT_64BIT_CFG_EN_FOR_GENSTATS0 mBIT(3) 6358#define VXGE_HAL_GENSTAT_64BIT_CFG_EN_FOR_GENSTATS2 mBIT(7) 6359/* 0x07f40 */ u64 pll_slip_counters; 6360#define VXGE_HAL_PLL_SLIP_COUNTERS_CMG(val) vBIT(val, 0, 16) 6361#define VXGE_HAL_PLL_SLIP_COUNTERS_FB(val) vBIT(val, 16, 16) 6362#define VXGE_HAL_PLL_SLIP_COUNTERS_X(val) vBIT(val, 32, 16) 6363 u8 unused08000[0x08000 - 0x07f48]; 6364 6365/* 0x08000 */ u64 gcmg3_int_status; 6366#define VXGE_HAL_GCMG3_INT_STATUS_GSTC_ERR0_GSTC0_INT mBIT(0) 6367#define VXGE_HAL_GCMG3_INT_STATUS_GSTC_ERR1_GSTC1_INT mBIT(1) 6368#define VXGE_HAL_GCMG3_INT_STATUS_GH2L_ERR0_GH2L0_INT mBIT(2) 6369#define VXGE_HAL_GCMG3_INT_STATUS_GHSQ_ERR_GH2L1_INT mBIT(3) 6370#define VXGE_HAL_GCMG3_INT_STATUS_GHSQ_ERR2_GH2L2_INT mBIT(4) 6371#define VXGE_HAL_GCMG3_INT_STATUS_GH2L_SMERR0_GH2L3_INT mBIT(5) 6372#define VXGE_HAL_GCMG3_INT_STATUS_GHSQ_ERR3_GH2L4_INT mBIT(6) 6373/* 0x08008 */ u64 gcmg3_int_mask; 6374/* 0x08010 */ u64 gstc_err0_reg; 6375#define VXGE_HAL_GSTC_ERR0_REG_STC_BDM_CACHE_DB_ERR(val) vBIT(val, 0, 3) 6376#define VXGE_HAL_GSTC_ERR0_REG_STC_BDM_CMRSP_DB_ERR(val) vBIT(val, 3, 5) 6377#define VXGE_HAL_GSTC_ERR0_REG_STC_ECI_CACHE0_DB_ERR(val) vBIT(val, 8, 4) 6378#define VXGE_HAL_GSTC_ERR0_REG_STC_ECI_CACHE1_DB_ERR(val) vBIT(val, 12, 4) 6379#define VXGE_HAL_GSTC_ERR0_REG_STC_H2L_EVENT_DB_ERR(val) vBIT(val, 16, 5) 6380#define VXGE_HAL_GSTC_ERR0_REG_STC_PRM_EVENT_DB_ERR(val) vBIT(val, 21, 3) 6381#define VXGE_HAL_GSTC_ERR0_REG_STC_SRCH_MEM_DB_ERR(val) vBIT(val, 24, 2) 6382#define VXGE_HAL_GSTC_ERR0_REG_STC_CMCIF_RD_DATA_DB_ERR mBIT(26) 6383#define VXGE_HAL_GSTC_ERR0_REG_STC_BDM_CACHE_SG_ERR(val) vBIT(val, 32, 3) 6384#define VXGE_HAL_GSTC_ERR0_REG_STC_BDM_CMRSP_SG_ERR(val) vBIT(val, 35, 5) 6385#define VXGE_HAL_GSTC_ERR0_REG_STC_ECI_CACHE0_SG_ERR(val) vBIT(val, 40, 4) 6386#define VXGE_HAL_GSTC_ERR0_REG_STC_ECI_CACHE1_SG_ERR(val) vBIT(val, 44, 4) 6387#define VXGE_HAL_GSTC_ERR0_REG_STC_H2L_EVENT_SG_ERR(val) vBIT(val, 48, 5) 6388#define VXGE_HAL_GSTC_ERR0_REG_STC_PRM_EVENT_SG_ERR(val) vBIT(val, 53, 3) 6389#define VXGE_HAL_GSTC_ERR0_REG_STC_SRCH_MEM_SG_ERR(val) vBIT(val, 56, 2) 6390/* 0x08018 */ u64 gstc_err0_mask; 6391/* 0x08020 */ u64 gstc_err0_alarm; 6392/* 0x08028 */ u64 gstc_err1_reg; 6393#define VXGE_HAL_GSTC_ERR1_REG_STC_RPEIF_REQ_FIFO_ERR mBIT(0) 6394#define VXGE_HAL_GSTC_ERR1_REG_STC_RPEIF_ECRESP_FIFO_ERR mBIT(1) 6395#define VXGE_HAL_GSTC_ERR1_REG_STC_RPEIF_BUFFRESP_FIFO_ERR mBIT(2) 6396#define VXGE_HAL_GSTC_ERR1_REG_STC_H2L_EVENT_FIFO_ERR mBIT(3) 6397#define VXGE_HAL_GSTC_ERR1_REG_STC_ARB_RPE_FIFO_ERR mBIT(4) 6398#define VXGE_HAL_GSTC_ERR1_REG_STC_ARB_REQ_FIFO_ERR mBIT(5) 6399#define VXGE_HAL_GSTC_ERR1_REG_STC_SSM_EVENT_FIFO_ERR mBIT(6) 6400#define VXGE_HAL_GSTC_ERR1_REG_STC_SSM_CMRSP_FIFO_ERR mBIT(7) 6401#define VXGE_HAL_GSTC_ERR1_REG_STC_ECI_ARB_FIFO_ERR mBIT(8) 6402#define VXGE_HAL_GSTC_ERR1_REG_STC_PRM_EVENT_FIFO_ERR mBIT(9) 6403#define VXGE_HAL_GSTC_ERR1_REG_STC_PRM_PAC_FIFO_ERR mBIT(10) 6404#define VXGE_HAL_GSTC_ERR1_REG_STC_BDM_EVENT_FIFO_ERR mBIT(11) 6405#define VXGE_HAL_GSTC_ERR1_REG_STC_BDM_CMRSP_FIFO_ERR mBIT(12) 6406#define VXGE_HAL_GSTC_ERR1_REG_STC_CMCIF_FIFO_ERR mBIT(13) 6407#define VXGE_HAL_GSTC_ERR1_REG_STC_CP2STC_FIFO_ERR mBIT(14) 6408#define VXGE_HAL_GSTC_ERR1_REG_STC_CPIF_CREDIT_FIFO_ERR mBIT(15) 6409#define VXGE_HAL_GSTC_ERR1_REG_STC_RPEIF_SHADOW_ERR mBIT(16) 6410#define VXGE_HAL_GSTC_ERR1_REG_STC_ARB_REQ_SHADOW_ERR mBIT(17) 6411#define VXGE_HAL_GSTC_ERR1_REG_STC_ARB_CTL_SHADOW_ERR mBIT(18) 6412#define VXGE_HAL_GSTC_ERR1_REG_STC_SCC_SHADOW_ERR mBIT(19) 6413#define VXGE_HAL_GSTC_ERR1_REG_STC_SSM_SHADOW_ERR mBIT(20) 6414#define VXGE_HAL_GSTC_ERR1_REG_STC_SSM_SYNC_SHADOW_ERR mBIT(21) 6415#define VXGE_HAL_GSTC_ERR1_REG_STC_ECI_ARB_SHADOW_ERR mBIT(22) 6416#define VXGE_HAL_GSTC_ERR1_REG_STC_ECI_SYNC_SHADOW_ERR mBIT(23) 6417#define VXGE_HAL_GSTC_ERR1_REG_STC_ECI_EPE_SHADOW_ERR mBIT(24) 6418#define VXGE_HAL_GSTC_ERR1_REG_STC_PRM_PAC_SHADOW_ERR mBIT(25) 6419#define VXGE_HAL_GSTC_ERR1_REG_STC_PRM_PSM_SHADOW_ERR mBIT(26) 6420#define VXGE_HAL_GSTC_ERR1_REG_STC_PRM_PRC_SHADOW_ERR mBIT(27) 6421#define VXGE_HAL_GSTC_ERR1_REG_STC_BDM_SHADOW_ERR mBIT(28) 6422#define VXGE_HAL_GSTC_ERR1_REG_STC_CMCIF_SHADOW_ERR mBIT(29) 6423#define VXGE_HAL_GSTC_ERR1_REG_STC_CPIF_SHADOW_ERR mBIT(30) 6424#define VXGE_HAL_GSTC_ERR1_REG_STC_SCC_CLM_ERR mBIT(32) 6425#define VXGE_HAL_GSTC_ERR1_REG_STC_SCC_RMM_FSM_ERR mBIT(33) 6426#define VXGE_HAL_GSTC_ERR1_REG_STC_ECI_EPE_FSM_ERR mBIT(34) 6427#define VXGE_HAL_GSTC_ERR1_REG_STC_PRM_PAC_PBLESIZE0_ERR mBIT(35) 6428#define VXGE_HAL_GSTC_ERR1_REG_STC_PRM_PAC_QUOTIENT_ERR mBIT(36) 6429#define VXGE_HAL_GSTC_ERR1_REG_STC_PRM_PRC_FSM_ERR mBIT(37) 6430#define VXGE_HAL_GSTC_ERR1_REG_STC_BDM_FSM_ERR mBIT(38) 6431#define VXGE_HAL_GSTC_ERR1_REG_STC_BDM_WRAP_ERR mBIT(39) 6432#define VXGE_HAL_GSTC_ERR1_REG_STC_RPEIF_BUFFER_ERR mBIT(40) 6433#define VXGE_HAL_GSTC_ERR1_REG_STC_CMCIF_FSM_ERR mBIT(41) 6434#define VXGE_HAL_GSTC_ERR1_REG_STC_UNK_CP_MSG_TYPE mBIT(42) 6435/* 0x08030 */ u64 gstc_err1_mask; 6436/* 0x08038 */ u64 gstc_err1_alarm; 6437/* 0x08040 */ u64 gh2l_err0_reg; 6438#define VXGE_HAL_GH2L_ERR0_REG_H2L_HOC_DATX_DB_ERR(val) vBIT(val, 0, 2) 6439#define VXGE_HAL_GH2L_ERR0_REG_H2L_WRDBL0_DB_ERR(val) vBIT(val, 2, 2) 6440#define VXGE_HAL_GH2L_ERR0_REG_H2L_WRDBL1_DB_ERR(val) vBIT(val, 4, 2) 6441#define VXGE_HAL_GH2L_ERR0_REG_H2L_WRBUF_DB_ERR(val) vBIT(val, 6, 2) 6442#define VXGE_HAL_GH2L_ERR0_REG_H2L_RD_RSP_DB_ERR mBIT(8) 6443#define VXGE_HAL_GH2L_ERR0_REG_H2L_CMCRSP_DB_ERR(val) vBIT(val, 9, 4) 6444#define VXGE_HAL_GH2L_ERR0_REG_H2L_HOC_HEAD_DB_ERR(val) vBIT(val, 13, 2) 6445#define VXGE_HAL_GH2L_ERR0_REG_H2L_OD_MEM_PA_DB_ERR mBIT(15) 6446#define VXGE_HAL_GH2L_ERR0_REG_H2L_OD_MEM_PB_DB_ERR mBIT(16) 6447#define VXGE_HAL_GH2L_ERR0_REG_H2L_HOC_DATX_SG_ERR(val) vBIT(val, 32, 2) 6448#define VXGE_HAL_GH2L_ERR0_REG_H2L_WRDBL0_SG_ERR(val) vBIT(val, 34, 2) 6449#define VXGE_HAL_GH2L_ERR0_REG_H2L_WRDBL1_SG_ERR(val) vBIT(val, 36, 2) 6450#define VXGE_HAL_GH2L_ERR0_REG_H2L_WRBUF_SG_ERR(val) vBIT(val, 38, 2) 6451#define VXGE_HAL_GH2L_ERR0_REG_H2L_CMCRSP_SG_ERR(val) vBIT(val, 41, 4) 6452#define VXGE_HAL_GH2L_ERR0_REG_H2L_HOC_HEAD_SG_ERR(val) vBIT(val, 45, 2) 6453#define VXGE_HAL_GH2L_ERR0_REG_H2L_OD_MEM_PA_SG_ERR mBIT(47) 6454#define VXGE_HAL_GH2L_ERR0_REG_H2L_OD_MEM_PB_SG_ERR mBIT(48) 6455/* 0x08048 */ u64 gh2l_err0_mask; 6456/* 0x08050 */ u64 gh2l_err0_alarm; 6457/* 0x08058 */ u64 ghsq_err_reg; 6458#define VXGE_HAL_GHSQ_ERR_REG_H2L_CMP_WR_COMP_OFLOW_ERR mBIT(0) 6459#define VXGE_HAL_GHSQ_ERR_REG_H2L_CMP_WR_COMP_UFLOW_ERR mBIT(1) 6460#define VXGE_HAL_GHSQ_ERR_REG_H2L_DAT_CTL_OFLOW_ERR mBIT(2) 6461#define VXGE_HAL_GHSQ_ERR_REG_H2L_DAT_CTL_UFLOW_ERR mBIT(3) 6462#define VXGE_HAL_GHSQ_ERR_REG_H2L_DAT_OFLOW_ERR mBIT(4) 6463#define VXGE_HAL_GHSQ_ERR_REG_H2L_DAT_UFLOW_ERR mBIT(5) 6464#define VXGE_HAL_GHSQ_ERR_REG_H2L_WR_DAT224_BB_OFLOW_ERR mBIT(6) 6465#define VXGE_HAL_GHSQ_ERR_REG_H2L_WR_DAT224_BB_UFLOW_ERR mBIT(7) 6466#define VXGE_HAL_GHSQ_ERR_REG_H2L_WR_REQ_OFLOW_ERR mBIT(8) 6467#define VXGE_HAL_GHSQ_ERR_REG_H2L_WR_REQ_UFLOW_ERR mBIT(9) 6468#define VXGE_HAL_GHSQ_ERR_REG_H2L_WRDBL_OFLOW_ERR mBIT(10) 6469#define VXGE_HAL_GHSQ_ERR_REG_H2L_WRDBL_UFLOW_ERR mBIT(11) 6470#define VXGE_HAL_GHSQ_ERR_REG_H2L_HOC_XFER_DATX_UFLOW_ERR mBIT(12) 6471#define VXGE_HAL_GHSQ_ERR_REG_H2L_HOC_XFER_CTLX_UFLOW_ERR mBIT(13) 6472#define VXGE_HAL_GHSQ_ERR_REG_H2L_CMP_RD_RSP_OFLOW_ERR mBIT(14) 6473#define VXGE_HAL_GHSQ_ERR_REG_H2L_CMP_RD_RSP_UFLOW_ERR mBIT(15) 6474#define VXGE_HAL_GHSQ_ERR_REG_H2L_CMP_RD_TRANS_POPCRDCNT_OFLOW_ERR mBIT(16) 6475#define VXGE_HAL_GHSQ_ERR_REG_H2L_CMP_RD_TRANS_POPCRDCNT_UFLOW_ERR mBIT(17) 6476/* 0x08060 */ u64 ghsq_err_mask; 6477/* 0x08068 */ u64 ghsq_err_alarm; 6478/* 0x08070 */ u64 ghsq_err2_reg; 6479#define VXGE_HAL_GHSQ_ERR2_REG_H2L_OFLOW_ERR(n) mBIT(n) 6480#define VXGE_HAL_GHSQ_ERR2_REG_H2L_UFLOW_ERR(n) mBIT(n) 6481/* 0x08078 */ u64 ghsq_err2_mask; 6482/* 0x08080 */ u64 ghsq_err2_alarm; 6483/* 0x08088 */ u64 ghsq_err3_reg; 6484#define VXGE_HAL_GHSQ_ERR3_REG_H2L_OFLOW_ERR(n) mBIT(n) 6485#define VXGE_HAL_GHSQ_ERR3_REG_H2L_UFLOW_ERR(n) mBIT(n) 6486/* 0x08090 */ u64 ghsq_err3_mask; 6487/* 0x08098 */ u64 ghsq_err3_alarm; 6488/* 0x080a0 */ u64 gh2l_smerr0_reg; 6489#define VXGE_HAL_GH2L_SMERR0_REG_H2L_OAE_HOPIF_SM_ERR mBIT(0) 6490#define VXGE_HAL_GH2L_SMERR0_REG_H2L_OAE_NR_SM_ERR mBIT(1) 6491#define VXGE_HAL_GH2L_SMERR0_REG_H2L_OAE_HOF_SM_ERR mBIT(2) 6492#define VXGE_HAL_GH2L_SMERR0_REG_H2L_OAE_ROP_SM_ERR mBIT(3) 6493#define VXGE_HAL_GH2L_SMERR0_REG_H2L_OAE_OADE_SM_ERR mBIT(4) 6494#define VXGE_HAL_GH2L_SMERR0_REG_H2L_OAE_ODOG_SM_ERR mBIT(5) 6495#define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_BATCH_DONE_SM_ERROR0 mBIT(6) 6496#define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_BATCH_DONE_SM_ERROR1 mBIT(7) 6497#define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_BATCH_DONE_SM_ERROR2 mBIT(8) 6498#define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_BATCH_DONE_SM_ERROR3 mBIT(9) 6499#define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_DOGLE_SM_ERROR0 mBIT(10) 6500#define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_DOGLE_SM_ERROR1 mBIT(11) 6501#define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_DOGLE_SM_ERROR2 mBIT(12) 6502#define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_DOGLE_SM_ERROR3 mBIT(13) 6503#define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_ERR_KILL_SM_ERROR0 mBIT(14) 6504#define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_ERR_KILL_SM_ERROR1 mBIT(15) 6505#define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_ERR_KILL_SM_ERROR2 mBIT(16) 6506#define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_ERR_KILL_SM_ERROR3 mBIT(17) 6507#define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_MSG_GEN_SM_ERROR0 mBIT(18) 6508#define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_MSG_GEN_SM_ERROR1 mBIT(19) 6509#define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_MSG_GEN_SM_ERROR2 mBIT(20) 6510#define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_MSG_GEN_SM_ERROR3 mBIT(21) 6511#define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_ORD_SM_ERROR0 mBIT(22) 6512#define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_ORD_SM_ERROR1 mBIT(23) 6513#define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_ORD_SM_ERROR2 mBIT(24) 6514#define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_ORD_SM_ERROR3 mBIT(25) 6515#define VXGE_HAL_GH2L_SMERR0_REG_H2L_DOG_STAG_KILL_SM_ERROR mBIT(26) 6516#define VXGE_HAL_GH2L_SMERR0_REG_H2L_H2L_CPIF_IMP_SM_ERROR mBIT(27) 6517#define VXGE_HAL_GH2L_SMERR0_REG_H2L_H2L_CPIF_OMP_SM_ERROR mBIT(28) 6518#define VXGE_HAL_GH2L_SMERR0_REG_H2L_H2L_CPIF_RECALL_SM_ERROR mBIT(29) 6519#define VXGE_HAL_GH2L_SMERR0_REG_H2L_LOG_CCTL_FIFO_ERR mBIT(30) 6520#define VXGE_HAL_GH2L_SMERR0_REG_H2L_RETXK_CCTL_FIFO_ERR mBIT(31) 6521#define VXGE_HAL_GH2L_SMERR0_REG_H2L_HOP_HCC_HANDSHAKE_ERR mBIT(32) 6522#define VXGE_HAL_GH2L_SMERR0_REG_H2L_HOP_ARB_HANDSHAKE_ERR mBIT(33) 6523#define VXGE_HAL_GH2L_SMERR0_REG_H2L_HOP_RETXK_HANDSHAKE_ERR mBIT(34) 6524#define VXGE_HAL_GH2L_SMERR0_REG_H2L_HOP_OAE_HANDSHAKE_ERR mBIT(35) 6525#define VXGE_HAL_GH2L_SMERR0_REG_H2L_HOP_VPATH_ERR mBIT(36) 6526#define VXGE_HAL_GH2L_SMERR0_REG_H2L_HOP_HO_SIZE_ERR mBIT(37) 6527#define VXGE_HAL_GH2L_SMERR0_REG_H2L_HOP_HO_PARSE_ERR mBIT(38) 6528#define VXGE_HAL_GH2L_SMERR0_REG_H2L_HOP_ARB_SM_ERR mBIT(39) 6529/* 0x080a8 */ u64 gh2l_smerr0_mask; 6530/* 0x080b0 */ u64 gh2l_smerr0_alarm; 6531/* 0x080b8 */ u64 hcc_alarm_reg; 6532#define VXGE_HAL_HCC_ALARM_REG_H2L_RWCRA_RW0_SG_ERR(val) vBIT(val, 0, 4) 6533#define VXGE_HAL_HCC_ALARM_REG_H2L_RWCRA_RW0_DB_ERR(val) vBIT(val, 4, 4) 6534#define VXGE_HAL_HCC_ALARM_REG_H2L_RWCRA_RW1_SG_ERR(val) vBIT(val, 8, 4) 6535#define VXGE_HAL_HCC_ALARM_REG_H2L_RWCRA_RW1_DB_ERR(val) vBIT(val, 12, 4) 6536#define VXGE_HAL_HCC_ALARM_REG_H2L_CWBC_FSM_ERR mBIT(19) 6537#define VXGE_HAL_HCC_ALARM_REG_H2L_RCC_FSM_ERR mBIT(23) 6538/* 0x080c0 */ u64 hcc_alarm_mask; 6539/* 0x080c8 */ u64 hcc_alarm_alarm; 6540/* 0x080d0 */ u64 gstc_cfg0; 6541#define VXGE_HAL_GSTC_CFG0_RPE_PF_ENA mBIT(7) 6542#define VXGE_HAL_GSTC_CFG0_SCC_MODE mBIT(15) 6543#define VXGE_HAL_GSTC_CFG0_SCC_NBR_FREE_SLOTS(val) vBIT(val, 18, 6) 6544#define VXGE_HAL_GSTC_CFG0_STC_LEFT_HASH_INDEX(val) vBIT(val, 27, 5) 6545#define VXGE_HAL_GSTC_CFG0_STC_RIGHT_HASH_INDEX(val) vBIT(val, 35, 5) 6546#define VXGE_HAL_GSTC_CFG0_INCL_ECI_FIFOS_PBL_SYNC mBIT(47) 6547#define VXGE_HAL_GSTC_CFG0_MW_LOCAL_ACCESS_ENA mBIT(55) 6548#define VXGE_HAL_GSTC_CFG0_LD_FW_CTRL_FIELDS mBIT(62) 6549#define VXGE_HAL_GSTC_CFG0_ONLY_ROW0_DUSE1_WRITABLE mBIT(63) 6550/* 0x080d8 */ u64 gstc_cfg1; 6551#define VXGE_HAL_GSTC_CFG1_INDIRECT_MODE(val) vBIT(val, 0, 17) 6552#define VXGE_HAL_GSTC_CFG1_RPE_PF_COUNTDOWN(val) vBIT(val, 36, 12) 6553#define VXGE_HAL_GSTC_CFG1_BDM_RATE_CTRL(val) vBIT(val, 54, 2) 6554#define VXGE_HAL_GSTC_CFG1_BDM_EXTRA_RPE_PRM_RD mBIT(63) 6555/* 0x080e0 */ u64 gstc_cfg2; 6556#define VXGE_HAL_GSTC_CFG2_MAX_FRE_CMREQ_ENTRIES(val) vBIT(val, 5, 3) 6557#define VXGE_HAL_GSTC_CFG2_NO_STAG_KILL_WIRE_INV mBIT(12) 6558#define VXGE_HAL_GSTC_CFG2_NO_STAG_KILL_CP_INV mBIT(13) 6559#define VXGE_HAL_GSTC_CFG2_NO_STAG_KILL_CP_DEALLOC mBIT(14) 6560#define VXGE_HAL_GSTC_CFG2_NO_STAG_KILL_CP_SUSP mBIT(15) 6561#define VXGE_HAL_GSTC_CFG2_BDM_CACHE_ECC_ENABLE_N mBIT(16) 6562#define VXGE_HAL_GSTC_CFG2_BDM_CMRSP_ECC_ENABLE_N mBIT(17) 6563#define VXGE_HAL_GSTC_CFG2_ECI_CACHE0_ECC_ENABLE_N mBIT(18) 6564#define VXGE_HAL_GSTC_CFG2_ECI_CACHE1_ECC_ENABLE_N mBIT(19) 6565#define VXGE_HAL_GSTC_CFG2_H2L_EVENT_ECC_ENABLE_N mBIT(20) 6566#define VXGE_HAL_GSTC_CFG2_PRM_EVENT_ECC_ENABLE_N mBIT(21) 6567#define VXGE_HAL_GSTC_CFG2_SRCH_MEM_ECC_ENABLE_N mBIT(22) 6568#define VXGE_HAL_GSTC_CFG2_GPSYNC_WAIT_TOKEN_ENABLE mBIT(29) 6569#define VXGE_HAL_GSTC_CFG2_GPSYNC_CNTDOWN_TIMER_ENABLE mBIT(30) 6570#define VXGE_HAL_GSTC_CFG2_GPSYNC_SRC_NOTIFY_ENABLE mBIT(31) 6571#define VXGE_HAL_GSTC_CFG2_GPSYNC_CNTDOWN_START_VALUE(val) vBIT(val, 36, 4) 6572/* 0x080e8 */ u64 stc_arb_cfg0; 6573#define VXGE_HAL_STC_ARB_CFG0_RPE_PRI(val) vBIT(val, 6, 2) 6574#define VXGE_HAL_STC_ARB_CFG0_H2L_PRI(val) vBIT(val, 14, 2) 6575#define VXGE_HAL_STC_ARB_CFG0_CP_PRI(val) vBIT(val, 22, 2) 6576#define VXGE_HAL_STC_ARB_CFG0_CAL0_PRI(val) vBIT(val, 30, 2) 6577#define VXGE_HAL_STC_ARB_CFG0_CAL1_PRI(val) vBIT(val, 38, 2) 6578#define VXGE_HAL_STC_ARB_CFG0_CAL2_PRI(val) vBIT(val, 46, 2) 6579#define VXGE_HAL_STC_ARB_CFG0_CAL3_PRI(val) vBIT(val, 54, 2) 6580#define VXGE_HAL_STC_ARB_CFG0_CAL4_PRI(val) vBIT(val, 62, 2) 6581/* 0x080f0 */ u64 stc_arb_cfg1; 6582#define VXGE_HAL_STC_ARB_CFG1_CAL5_PRI(val) vBIT(val, 6, 2) 6583#define VXGE_HAL_STC_ARB_CFG1_CAL6_PRI(val) vBIT(val, 14, 2) 6584#define VXGE_HAL_STC_ARB_CFG1_CAL7_PRI(val) vBIT(val, 22, 2) 6585#define VXGE_HAL_STC_ARB_CFG1_CAL8_PRI(val) vBIT(val, 30, 2) 6586/* 0x080f8 */ u64 stc_arb_cfg2; 6587#define VXGE_HAL_STC_ARB_CFG2_MAX_NBR_H2L0_EVENTS(val) vBIT(val, 4, 4) 6588#define VXGE_HAL_STC_ARB_CFG2_MAX_NBR_H2L1_EVENTS(val) vBIT(val, 12, 4) 6589#define VXGE_HAL_STC_ARB_CFG2_MAX_NBR_H2L2_EVENTS(val) vBIT(val, 20, 4) 6590#define VXGE_HAL_STC_ARB_CFG2_MAX_NBR_H2L3_EVENTS(val) vBIT(val, 28, 4) 6591#define VXGE_HAL_STC_ARB_CFG2_MAX_NBR_RPE_EVENTS(val) vBIT(val, 35, 5) 6592#define VXGE_HAL_STC_ARB_CFG2_MAX_NBR_MR_EVENTS(val) vBIT(val, 45, 3) 6593/* 0x08100 */ u64 stc_arb_cfg3; 6594#define VXGE_HAL_STC_ARB_CFG3_MAX_NBR_H2L0_FETCHES(val) vBIT(val, 5, 3) 6595#define VXGE_HAL_STC_ARB_CFG3_MAX_NBR_H2L1_FETCHES(val) vBIT(val, 13, 3) 6596#define VXGE_HAL_STC_ARB_CFG3_MAX_NBR_H2L2_FETCHES(val) vBIT(val, 21, 3) 6597#define VXGE_HAL_STC_ARB_CFG3_MAX_NBR_H2L3_FETCHES(val) vBIT(val, 29, 3) 6598#define VXGE_HAL_STC_ARB_CFG3_MAX_NBR_RPE_FETCHES(val) vBIT(val, 37, 3) 6599#define VXGE_HAL_STC_ARB_CFG3_MAX_NBR_RPE_PF_FETCHES(val) vBIT(val, 46, 2) 6600/* 0x08108 */ u64 stc_jhash_cfg; 6601#define VXGE_HAL_STC_JHASH_CFG_GOLDEN(val) vBIT(val, 0, 32) 6602#define VXGE_HAL_STC_JHASH_CFG_INIT_VAL(val) vBIT(val, 32, 32) 6603/* 0x08110 */ u64 stc_smi_arb_cfg0; 6604#define VXGE_HAL_STC_SMI_ARB_CFG0_RPE_PRI(val) vBIT(val, 6, 2) 6605#define VXGE_HAL_STC_SMI_ARB_CFG0_H2L_PRI(val) vBIT(val, 14, 2) 6606#define VXGE_HAL_STC_SMI_ARB_CFG0_CP_PRI(val) vBIT(val, 22, 2) 6607#define VXGE_HAL_STC_SMI_ARB_CFG0_CAL0_PRI(val) vBIT(val, 30, 2) 6608#define VXGE_HAL_STC_SMI_ARB_CFG0_CAL1_PRI(val) vBIT(val, 38, 2) 6609#define VXGE_HAL_STC_SMI_ARB_CFG0_CAL2_PRI(val) vBIT(val, 46, 2) 6610#define VXGE_HAL_STC_SMI_ARB_CFG0_CAL3_PRI(val) vBIT(val, 54, 2) 6611#define VXGE_HAL_STC_SMI_ARB_CFG0_CAL4_PRI(val) vBIT(val, 62, 2) 6612/* 0x08118 */ u64 stc_smi_arb_cfg1; 6613#define VXGE_HAL_STC_SMI_ARB_CFG1_CAL5_PRI(val) vBIT(val, 6, 2) 6614#define VXGE_HAL_STC_SMI_ARB_CFG1_CAL6_PRI(val) vBIT(val, 14, 2) 6615#define VXGE_HAL_STC_SMI_ARB_CFG1_CAL7_PRI(val) vBIT(val, 22, 2) 6616#define VXGE_HAL_STC_SMI_ARB_CFG1_CAL8_PRI(val) vBIT(val, 30, 2) 6617#define VXGE_HAL_STC_SMI_ARB_CFG1_CAL9_PRI(val) vBIT(val, 38, 2) 6618#define VXGE_HAL_STC_SMI_ARB_CFG1_SAME_PRI_B2B_CAL mBIT(48) 6619/* 0x08120 */ u64 stc_caa_arb_cfg0; 6620#define VXGE_HAL_STC_CAA_ARB_CFG0_RPE_PRI(val) vBIT(val, 6, 2) 6621#define VXGE_HAL_STC_CAA_ARB_CFG0_H2L_PRI(val) vBIT(val, 14, 2) 6622#define VXGE_HAL_STC_CAA_ARB_CFG0_CP_PRI(val) vBIT(val, 22, 2) 6623#define VXGE_HAL_STC_CAA_ARB_CFG0_CAL0_PRI(val) vBIT(val, 30, 2) 6624#define VXGE_HAL_STC_CAA_ARB_CFG0_CAL1_PRI(val) vBIT(val, 38, 2) 6625#define VXGE_HAL_STC_CAA_ARB_CFG0_CAL2_PRI(val) vBIT(val, 46, 2) 6626#define VXGE_HAL_STC_CAA_ARB_CFG0_CAL3_PRI(val) vBIT(val, 54, 2) 6627#define VXGE_HAL_STC_CAA_ARB_CFG0_CAL4_PRI(val) vBIT(val, 62, 2) 6628/* 0x08128 */ u64 stc_caa_arb_cfg1; 6629#define VXGE_HAL_STC_CAA_ARB_CFG1_CAL5_PRI(val) vBIT(val, 6, 2) 6630#define VXGE_HAL_STC_CAA_ARB_CFG1_CAL6_PRI(val) vBIT(val, 14, 2) 6631#define VXGE_HAL_STC_CAA_ARB_CFG1_CAL7_PRI(val) vBIT(val, 22, 2) 6632#define VXGE_HAL_STC_CAA_ARB_CFG1_CAL8_PRI(val) vBIT(val, 30, 2) 6633#define VXGE_HAL_STC_CAA_ARB_CFG1_SAME_PRI_B2B_CAL mBIT(39) 6634/* 0x08130 */ u64 stc_eci_arb_cfg0; 6635#define VXGE_HAL_STC_ECI_ARB_CFG0_RPE_PRI(val) vBIT(val, 6, 2) 6636#define VXGE_HAL_STC_ECI_ARB_CFG0_H2L_PRI(val) vBIT(val, 14, 2) 6637#define VXGE_HAL_STC_ECI_ARB_CFG0_CP_PRI(val) vBIT(val, 22, 2) 6638#define VXGE_HAL_STC_ECI_ARB_CFG0_CAL0_PRI(val) vBIT(val, 30, 2) 6639#define VXGE_HAL_STC_ECI_ARB_CFG0_CAL1_PRI(val) vBIT(val, 38, 2) 6640#define VXGE_HAL_STC_ECI_ARB_CFG0_CAL2_PRI(val) vBIT(val, 46, 2) 6641#define VXGE_HAL_STC_ECI_ARB_CFG0_CAL3_PRI(val) vBIT(val, 54, 2) 6642#define VXGE_HAL_STC_ECI_ARB_CFG0_CAL4_PRI(val) vBIT(val, 62, 2) 6643/* 0x08138 */ u64 stc_eci_arb_cfg1; 6644#define VXGE_HAL_STC_ECI_ARB_CFG1_CAL5_PRI(val) vBIT(val, 6, 2) 6645#define VXGE_HAL_STC_ECI_ARB_CFG1_CAL6_PRI(val) vBIT(val, 14, 2) 6646#define VXGE_HAL_STC_ECI_ARB_CFG1_CAL7_PRI(val) vBIT(val, 22, 2) 6647#define VXGE_HAL_STC_ECI_ARB_CFG1_CAL8_PRI(val) vBIT(val, 30, 2) 6648/* 0x08140 */ u64 stc_eci_cfg0; 6649#define VXGE_HAL_STC_ECI_CFG0_SUSPEND_DEALLOC_STAGS_ENA mBIT(4) 6650#define VXGE_HAL_STC_ECI_CFG0_MULT_SUSPEND_ERR_ENA mBIT(5) 6651#define VXGE_HAL_STC_ECI_CFG0_SUSPEND_PDID_CHECK_ENA mBIT(6) 6652#define VXGE_HAL_STC_ECI_CFG0_UNSUSPEND_PDID_CHECK_ENA mBIT(7) 6653#define VXGE_HAL_STC_ECI_CFG0_ALTER_NUM_MWS_KEY_CHECK_ENA mBIT(14) 6654#define VXGE_HAL_STC_ECI_CFG0_ALTER_NUM_MWS_PDID_CHECK_ENA mBIT(15) 6655#define VXGE_HAL_STC_ECI_CFG0_SET_SHARED_KEY_CHECK_ENA mBIT(23) 6656#define VXGE_HAL_STC_ECI_CFG0_STAG_WR_FAIL_IF_DEALLOC mBIT(31) 6657#define VXGE_HAL_STC_ECI_CFG0_PLACEMENT_MR_DEFERRAL_ENA mBIT(34) 6658#define VXGE_HAL_STC_ECI_CFG0_SUSPEND_MR_DEFERRAL_ENA mBIT(35) 6659#define VXGE_HAL_STC_ECI_CFG0_ALTER_NUM_MWS_MR_DEFERRAL_ENA mBIT(36) 6660#define VXGE_HAL_STC_ECI_CFG0_BIND_MW_MR_DEFERRAL_ENA mBIT(37) 6661#define VXGE_HAL_STC_ECI_CFG0_SET_SHARED_MR_DEFERRAL_ENA mBIT(38) 6662#define VXGE_HAL_STC_ECI_CFG0_STAG_WR_MR_DEFERRAL_ENA mBIT(39) 6663#define VXGE_HAL_STC_ECI_CFG0_RESUBMIT_INTERVAL(val) vBIT(val, 40, 8) 6664#define VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_PLACE_STALL_ENA mBIT(54) 6665#define VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_WIRE_INV_STALL_ENA mBIT(55) 6666#define VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_WIRE_INV_ENA mBIT(56) 6667#define VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_CP_INV_ENA mBIT(57) 6668#define VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_MR_EVENT_ENA mBIT(58) 6669#define VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_DEALLOC_ENA mBIT(59) 6670#define VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_ALTER_NUM_MWS_ENA mBIT(60) 6671#define VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_BIND_MW_ENA mBIT(61) 6672#define VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_SET_SHARED_ENA mBIT(62) 6673#define VXGE_HAL_STC_ECI_CFG0_SUSP_STAG_STAG_WR_ENA mBIT(63) 6674/* 0x08148 */ u64 stc_prm_cfg0; 6675#define VXGE_HAL_STC_PRM_CFG0_PAC_RPE_PRI mBIT(6) 6676#define VXGE_HAL_STC_PRM_CFG0_PAC_H2L_PRI mBIT(7) 6677#define VXGE_HAL_STC_PRM_CFG0_PAC_CAL0_PRI mBIT(8) 6678#define VXGE_HAL_STC_PRM_CFG0_PAC_CAL1_PRI mBIT(9) 6679#define VXGE_HAL_STC_PRM_CFG0_PAC_CAL2_PRI mBIT(10) 6680#define VXGE_HAL_STC_PRM_CFG0_PAC_CAL3_PRI mBIT(11) 6681#define VXGE_HAL_STC_PRM_CFG0_PAC_CAL4_PRI mBIT(12) 6682#define VXGE_HAL_STC_PRM_CFG0_PAC_CAL5_PRI mBIT(13) 6683#define VXGE_HAL_STC_PRM_CFG0_PAC_CAL6_PRI mBIT(14) 6684#define VXGE_HAL_STC_PRM_CFG0_PAC_CAL7_PRI mBIT(15) 6685#define VXGE_HAL_STC_PRM_CFG0_PRC_RPE_PRI mBIT(22) 6686#define VXGE_HAL_STC_PRM_CFG0_PRC_H2L_PRI mBIT(23) 6687#define VXGE_HAL_STC_PRM_CFG0_PRC_CAL0_PRI mBIT(24) 6688#define VXGE_HAL_STC_PRM_CFG0_PRC_CAL1_PRI mBIT(25) 6689#define VXGE_HAL_STC_PRM_CFG0_PRC_CAL2_PRI mBIT(26) 6690#define VXGE_HAL_STC_PRM_CFG0_PRC_CAL3_PRI mBIT(27) 6691#define VXGE_HAL_STC_PRM_CFG0_PRC_CAL4_PRI mBIT(28) 6692#define VXGE_HAL_STC_PRM_CFG0_PRC_CAL5_PRI mBIT(29) 6693#define VXGE_HAL_STC_PRM_CFG0_PRC_CAL6_PRI mBIT(30) 6694#define VXGE_HAL_STC_PRM_CFG0_PRC_CAL7_PRI mBIT(31) 6695#define VXGE_HAL_STC_PRM_CFG0_RDUSE_ENA mBIT(39) 6696/* 0x08150 */ u64 h2l_misc_cfg; 6697#define VXGE_HAL_H2L_MISC_CFG_HSQ_FORCE_CMP mBIT(0) 6698#define VXGE_HAL_H2L_MISC_CFG_HOP_IPID_MSB mBIT(1) 6699#define VXGE_HAL_H2L_MISC_CFG_HOP_ARB_ENABLE mBIT(2) 6700#define VXGE_HAL_H2L_MISC_CFG_HOP_ENFORCE_HSN mBIT(3) 6701#define VXGE_HAL_H2L_MISC_CFG_HOP_ENFORCE_RD_XON mBIT(4) 6702#define VXGE_HAL_H2L_MISC_CFG_HOP_ENFORCE_PDA_VPBP mBIT(5) 6703#define VXGE_HAL_H2L_MISC_CFG_OAE_VPBP_CHECK_ENA mBIT(6) 6704#define VXGE_HAL_H2L_MISC_CFG_OAE_XON_CHECK_ENA mBIT(7) 6705#define VXGE_HAL_H2L_MISC_CFG_HOCHEAD_RD_THRES(val) vBIT(val, 10, 6) 6706#define VXGE_HAL_H2L_MISC_CFG_HCC_WB_THRESHOLD(val) vBIT(val, 19, 5) 6707#define VXGE_HAL_H2L_MISC_CFG_HOP_BCK_STATS_MODE(val) vBIT(val, 25, 2) 6708#define VXGE_HAL_H2L_MISC_CFG_HOP_BCK_STATS_VPATH(val) vBIT(val, 27, 5) 6709#define VXGE_HAL_H2L_MISC_CFG_HOC_DATX_ECC_ENABLE_N mBIT(35) 6710#define VXGE_HAL_H2L_MISC_CFG_WRDBL_ECC_ENABLE_N mBIT(36) 6711#define VXGE_HAL_H2L_MISC_CFG_WRBUF_ECC_ENABLE_N mBIT(37) 6712#define VXGE_HAL_H2L_MISC_CFG_CMCRSP_ECC_ENABLE_N mBIT(38) 6713#define VXGE_HAL_H2L_MISC_CFG_HOC_HEAD_ECC_ENABLE_N mBIT(39) 6714#define VXGE_HAL_H2L_MISC_CFG_OD_MEM_ECC_ENABLE_N mBIT(40) 6715#define VXGE_HAL_H2L_MISC_CFG_RW_CACHE_ECC_ENABLE_N mBIT(41) 6716/* 0x08158 */ u64 hsq_cfg[17]; 6717#define VXGE_HAL_HSQ_CFG_BASE_ADDR(val) vBIT(val, 8, 24) 6718#define VXGE_HAL_HSQ_CFG_SIZE224(val) vBIT(val, 40, 24) 6719/* 0x081e0 */ u64 usdc_vpbp_cfg; 6720#define VXGE_HAL_USDC_VPBP_CFG_THRES224(val) vBIT(val, 8, 24) 6721#define VXGE_HAL_USDC_VPBP_CFG_HYST224(val) vBIT(val, 40, 24) 6722/* 0x081e8 */ u64 kdfc_vpbp_cfg; 6723#define VXGE_HAL_KDFC_VPBP_CFG_THRES224(val) vBIT(val, 8, 24) 6724#define VXGE_HAL_KDFC_VPBP_CFG_HYST224(val) vBIT(val, 40, 24) 6725/* 0x081f0 */ u64 txpe_vpbp_cfg; 6726#define VXGE_HAL_TXPE_VPBP_CFG_THRES224(val) vBIT(val, 8, 24) 6727#define VXGE_HAL_TXPE_VPBP_CFG_HYST224(val) vBIT(val, 40, 24) 6728/* 0x081f8 */ u64 one_vpbp_cfg; 6729#define VXGE_HAL_ONE_VPBP_CFG_THRES224(val) vBIT(val, 8, 24) 6730#define VXGE_HAL_ONE_VPBP_CFG_HYST224(val) vBIT(val, 40, 24) 6731/* 0x08200 */ u64 hoparb_wrr_ctrl_0; 6732#define VXGE_HAL_HOPARB_WRR_CTRL_0_SS_0_NUM(val) vBIT(val, 3, 5) 6733#define VXGE_HAL_HOPARB_WRR_CTRL_0_SS_1_NUM(val) vBIT(val, 11, 5) 6734#define VXGE_HAL_HOPARB_WRR_CTRL_0_SS_2_NUM(val) vBIT(val, 19, 5) 6735#define VXGE_HAL_HOPARB_WRR_CTRL_0_SS_3_NUM(val) vBIT(val, 27, 5) 6736#define VXGE_HAL_HOPARB_WRR_CTRL_0_SS_4_NUM(val) vBIT(val, 35, 5) 6737#define VXGE_HAL_HOPARB_WRR_CTRL_0_SS_5_NUM(val) vBIT(val, 43, 5) 6738#define VXGE_HAL_HOPARB_WRR_CTRL_0_SS_6_NUM(val) vBIT(val, 51, 5) 6739#define VXGE_HAL_HOPARB_WRR_CTRL_0_SS_7_NUM(val) vBIT(val, 59, 5) 6740/* 0x08208 */ u64 hoparb_wrr_ctrl_1; 6741#define VXGE_HAL_HOPARB_WRR_CTRL_1_SS_8_NUM(val) vBIT(val, 3, 5) 6742#define VXGE_HAL_HOPARB_WRR_CTRL_1_SS_9_NUM(val) vBIT(val, 11, 5) 6743#define VXGE_HAL_HOPARB_WRR_CTRL_1_SS_10_NUM(val) vBIT(val, 19, 5) 6744#define VXGE_HAL_HOPARB_WRR_CTRL_1_SS_11_NUM(val) vBIT(val, 27, 5) 6745#define VXGE_HAL_HOPARB_WRR_CTRL_1_SS_12_NUM(val) vBIT(val, 35, 5) 6746#define VXGE_HAL_HOPARB_WRR_CTRL_1_SS_13_NUM(val) vBIT(val, 43, 5) 6747#define VXGE_HAL_HOPARB_WRR_CTRL_1_SS_14_NUM(val) vBIT(val, 51, 5) 6748#define VXGE_HAL_HOPARB_WRR_CTRL_1_SS_15_NUM(val) vBIT(val, 59, 5) 6749/* 0x08210 */ u64 hoparb_wrr_ctrl_2; 6750#define VXGE_HAL_HOPARB_WRR_CTRL_2_SS_16_NUM(val) vBIT(val, 3, 5) 6751#define VXGE_HAL_HOPARB_WRR_CTRL_2_SS_17_NUM(val) vBIT(val, 11, 5) 6752#define VXGE_HAL_HOPARB_WRR_CTRL_2_SS_18_NUM(val) vBIT(val, 19, 5) 6753#define VXGE_HAL_HOPARB_WRR_CTRL_2_SS_19_NUM(val) vBIT(val, 27, 5) 6754#define VXGE_HAL_HOPARB_WRR_CTRL_2_SS_20_NUM(val) vBIT(val, 35, 5) 6755#define VXGE_HAL_HOPARB_WRR_CTRL_2_SS_21_NUM(val) vBIT(val, 43, 5) 6756#define VXGE_HAL_HOPARB_WRR_CTRL_2_SS_22_NUM(val) vBIT(val, 51, 5) 6757#define VXGE_HAL_HOPARB_WRR_CTRL_2_SS_23_NUM(val) vBIT(val, 59, 5) 6758/* 0x08218 */ u64 hoparb_wrr_ctrl_3; 6759#define VXGE_HAL_HOPARB_WRR_CTRL_3_SS_24_NUM(val) vBIT(val, 3, 5) 6760#define VXGE_HAL_HOPARB_WRR_CTRL_3_SS_25_NUM(val) vBIT(val, 11, 5) 6761#define VXGE_HAL_HOPARB_WRR_CTRL_3_SS_26_NUM(val) vBIT(val, 19, 5) 6762#define VXGE_HAL_HOPARB_WRR_CTRL_3_SS_27_NUM(val) vBIT(val, 27, 5) 6763#define VXGE_HAL_HOPARB_WRR_CTRL_3_SS_28_NUM(val) vBIT(val, 35, 5) 6764#define VXGE_HAL_HOPARB_WRR_CTRL_3_SS_29_NUM(val) vBIT(val, 43, 5) 6765#define VXGE_HAL_HOPARB_WRR_CTRL_3_SS_30_NUM(val) vBIT(val, 51, 5) 6766#define VXGE_HAL_HOPARB_WRR_CTRL_3_SS_31_NUM(val) vBIT(val, 59, 5) 6767/* 0x08220 */ u64 hoparb_wrr_ctrl_4; 6768#define VXGE_HAL_HOPARB_WRR_CTRL_4_SS_32_NUM(val) vBIT(val, 3, 5) 6769#define VXGE_HAL_HOPARB_WRR_CTRL_4_SS_33_NUM(val) vBIT(val, 11, 5) 6770#define VXGE_HAL_HOPARB_WRR_CTRL_4_SS_34_NUM(val) vBIT(val, 19, 5) 6771#define VXGE_HAL_HOPARB_WRR_CTRL_4_SS_35_NUM(val) vBIT(val, 27, 5) 6772#define VXGE_HAL_HOPARB_WRR_CTRL_4_SS_36_NUM(val) vBIT(val, 35, 5) 6773#define VXGE_HAL_HOPARB_WRR_CTRL_4_SS_37_NUM(val) vBIT(val, 43, 5) 6774#define VXGE_HAL_HOPARB_WRR_CTRL_4_SS_38_NUM(val) vBIT(val, 51, 5) 6775#define VXGE_HAL_HOPARB_WRR_CTRL_4_SS_39_NUM(val) vBIT(val, 59, 5) 6776/* 0x08228 */ u64 hoparb_wrr_ctrl_5; 6777#define VXGE_HAL_HOPARB_WRR_CTRL_5_SS_40_NUM(val) vBIT(val, 3, 5) 6778#define VXGE_HAL_HOPARB_WRR_CTRL_5_SS_41_NUM(val) vBIT(val, 11, 5) 6779#define VXGE_HAL_HOPARB_WRR_CTRL_5_SS_42_NUM(val) vBIT(val, 19, 5) 6780#define VXGE_HAL_HOPARB_WRR_CTRL_5_SS_43_NUM(val) vBIT(val, 27, 5) 6781#define VXGE_HAL_HOPARB_WRR_CTRL_5_SS_44_NUM(val) vBIT(val, 35, 5) 6782#define VXGE_HAL_HOPARB_WRR_CTRL_5_SS_45_NUM(val) vBIT(val, 43, 5) 6783#define VXGE_HAL_HOPARB_WRR_CTRL_5_SS_46_NUM(val) vBIT(val, 51, 5) 6784#define VXGE_HAL_HOPARB_WRR_CTRL_5_SS_47_NUM(val) vBIT(val, 59, 5) 6785/* 0x08230 */ u64 hoparb_wrr_ctrl_6; 6786#define VXGE_HAL_HOPARB_WRR_CTRL_6_SS_48_NUM(val) vBIT(val, 3, 5) 6787#define VXGE_HAL_HOPARB_WRR_CTRL_6_SS_49_NUM(val) vBIT(val, 11, 5) 6788#define VXGE_HAL_HOPARB_WRR_CTRL_6_SS_50_NUM(val) vBIT(val, 19, 5) 6789#define VXGE_HAL_HOPARB_WRR_CTRL_6_SS_51_NUM(val) vBIT(val, 27, 5) 6790#define VXGE_HAL_HOPARB_WRR_CTRL_6_SS_52_NUM(val) vBIT(val, 35, 5) 6791#define VXGE_HAL_HOPARB_WRR_CTRL_6_SS_53_NUM(val) vBIT(val, 43, 5) 6792#define VXGE_HAL_HOPARB_WRR_CTRL_6_SS_54_NUM(val) vBIT(val, 51, 5) 6793#define VXGE_HAL_HOPARB_WRR_CTRL_6_SS_55_NUM(val) vBIT(val, 59, 5) 6794/* 0x08238 */ u64 hoparb_wrr_ctrl_7; 6795#define VXGE_HAL_HOPARB_WRR_CTRL_7_SS_56_NUM(val) vBIT(val, 3, 5) 6796#define VXGE_HAL_HOPARB_WRR_CTRL_7_SS_57_NUM(val) vBIT(val, 11, 5) 6797#define VXGE_HAL_HOPARB_WRR_CTRL_7_SS_58_NUM(val) vBIT(val, 19, 5) 6798#define VXGE_HAL_HOPARB_WRR_CTRL_7_SS_59_NUM(val) vBIT(val, 27, 5) 6799#define VXGE_HAL_HOPARB_WRR_CTRL_7_SS_60_NUM(val) vBIT(val, 35, 5) 6800#define VXGE_HAL_HOPARB_WRR_CTRL_7_SS_61_NUM(val) vBIT(val, 43, 5) 6801#define VXGE_HAL_HOPARB_WRR_CTRL_7_SS_62_NUM(val) vBIT(val, 51, 5) 6802#define VXGE_HAL_HOPARB_WRR_CTRL_7_SS_63_NUM(val) vBIT(val, 59, 5) 6803/* 0x08240 */ u64 hoparb_wrr_ctrl_8; 6804#define VXGE_HAL_HOPARB_WRR_CTRL_8_SS_64_NUM(val) vBIT(val, 3, 5) 6805#define VXGE_HAL_HOPARB_WRR_CTRL_8_SS_65_NUM(val) vBIT(val, 11, 5) 6806#define VXGE_HAL_HOPARB_WRR_CTRL_8_SS_66_NUM(val) vBIT(val, 19, 5) 6807#define VXGE_HAL_HOPARB_WRR_CTRL_8_SS_67_NUM(val) vBIT(val, 27, 5) 6808#define VXGE_HAL_HOPARB_WRR_CTRL_8_SS_68_NUM(val) vBIT(val, 35, 5) 6809#define VXGE_HAL_HOPARB_WRR_CTRL_8_SS_69_NUM(val) vBIT(val, 43, 5) 6810#define VXGE_HAL_HOPARB_WRR_CTRL_8_SS_70_NUM(val) vBIT(val, 51, 5) 6811#define VXGE_HAL_HOPARB_WRR_CTRL_8_SS_71_NUM(val) vBIT(val, 59, 5) 6812/* 0x08248 */ u64 hoparb_wrr_ctrl_9; 6813#define VXGE_HAL_HOPARB_WRR_CTRL_9_SS_72_NUM(val) vBIT(val, 3, 5) 6814#define VXGE_HAL_HOPARB_WRR_CTRL_9_SS_73_NUM(val) vBIT(val, 11, 5) 6815#define VXGE_HAL_HOPARB_WRR_CTRL_9_SS_74_NUM(val) vBIT(val, 19, 5) 6816#define VXGE_HAL_HOPARB_WRR_CTRL_9_SS_75_NUM(val) vBIT(val, 27, 5) 6817#define VXGE_HAL_HOPARB_WRR_CTRL_9_SS_76_NUM(val) vBIT(val, 35, 5) 6818#define VXGE_HAL_HOPARB_WRR_CTRL_9_SS_77_NUM(val) vBIT(val, 43, 5) 6819#define VXGE_HAL_HOPARB_WRR_CTRL_9_SS_78_NUM(val) vBIT(val, 51, 5) 6820#define VXGE_HAL_HOPARB_WRR_CTRL_9_SS_79_NUM(val) vBIT(val, 59, 5) 6821/* 0x08250 */ u64 hoparb_wrr_ctrl_10; 6822#define VXGE_HAL_HOPARB_WRR_CTRL_10_SS_80_NUM(val) vBIT(val, 3, 5) 6823#define VXGE_HAL_HOPARB_WRR_CTRL_10_SS_81_NUM(val) vBIT(val, 11, 5) 6824#define VXGE_HAL_HOPARB_WRR_CTRL_10_SS_82_NUM(val) vBIT(val, 19, 5) 6825#define VXGE_HAL_HOPARB_WRR_CTRL_10_SS_83_NUM(val) vBIT(val, 27, 5) 6826#define VXGE_HAL_HOPARB_WRR_CTRL_10_SS_84_NUM(val) vBIT(val, 35, 5) 6827#define VXGE_HAL_HOPARB_WRR_CTRL_10_SS_85_NUM(val) vBIT(val, 43, 5) 6828#define VXGE_HAL_HOPARB_WRR_CTRL_10_SS_86_NUM(val) vBIT(val, 51, 5) 6829#define VXGE_HAL_HOPARB_WRR_CTRL_10_SS_87_NUM(val) vBIT(val, 59, 5) 6830/* 0x08258 */ u64 hoparb_wrr_ctrl_11; 6831#define VXGE_HAL_HOPARB_WRR_CTRL_11_SS_88_NUM(val) vBIT(val, 3, 5) 6832#define VXGE_HAL_HOPARB_WRR_CTRL_11_SS_89_NUM(val) vBIT(val, 11, 5) 6833#define VXGE_HAL_HOPARB_WRR_CTRL_11_SS_90_NUM(val) vBIT(val, 19, 5) 6834#define VXGE_HAL_HOPARB_WRR_CTRL_11_SS_91_NUM(val) vBIT(val, 27, 5) 6835#define VXGE_HAL_HOPARB_WRR_CTRL_11_SS_92_NUM(val) vBIT(val, 35, 5) 6836#define VXGE_HAL_HOPARB_WRR_CTRL_11_SS_93_NUM(val) vBIT(val, 43, 5) 6837#define VXGE_HAL_HOPARB_WRR_CTRL_11_SS_94_NUM(val) vBIT(val, 51, 5) 6838#define VXGE_HAL_HOPARB_WRR_CTRL_11_SS_95_NUM(val) vBIT(val, 59, 5) 6839/* 0x08260 */ u64 hoparb_wrr_ctrl_12; 6840#define VXGE_HAL_HOPARB_WRR_CTRL_12_SS_96_NUM(val) vBIT(val, 3, 5) 6841#define VXGE_HAL_HOPARB_WRR_CTRL_12_SS_97_NUM(val) vBIT(val, 11, 5) 6842#define VXGE_HAL_HOPARB_WRR_CTRL_12_SS_98_NUM(val) vBIT(val, 19, 5) 6843#define VXGE_HAL_HOPARB_WRR_CTRL_12_SS_99_NUM(val) vBIT(val, 27, 5) 6844#define VXGE_HAL_HOPARB_WRR_CTRL_12_SS_100_NUM(val) vBIT(val, 35, 5) 6845#define VXGE_HAL_HOPARB_WRR_CTRL_12_SS_101_NUM(val) vBIT(val, 43, 5) 6846#define VXGE_HAL_HOPARB_WRR_CTRL_12_SS_102_NUM(val) vBIT(val, 51, 5) 6847#define VXGE_HAL_HOPARB_WRR_CTRL_12_SS_103_NUM(val) vBIT(val, 59, 5) 6848/* 0x08268 */ u64 hoparb_wrr_ctrl_13; 6849#define VXGE_HAL_HOPARB_WRR_CTRL_13_SS_104_NUM(val) vBIT(val, 3, 5) 6850#define VXGE_HAL_HOPARB_WRR_CTRL_13_SS_105_NUM(val) vBIT(val, 11, 5) 6851#define VXGE_HAL_HOPARB_WRR_CTRL_13_SS_106_NUM(val) vBIT(val, 19, 5) 6852#define VXGE_HAL_HOPARB_WRR_CTRL_13_SS_107_NUM(val) vBIT(val, 27, 5) 6853#define VXGE_HAL_HOPARB_WRR_CTRL_13_SS_108_NUM(val) vBIT(val, 35, 5) 6854#define VXGE_HAL_HOPARB_WRR_CTRL_13_SS_109_NUM(val) vBIT(val, 43, 5) 6855#define VXGE_HAL_HOPARB_WRR_CTRL_13_SS_110_NUM(val) vBIT(val, 51, 5) 6856#define VXGE_HAL_HOPARB_WRR_CTRL_13_SS_111_NUM(val) vBIT(val, 59, 5) 6857/* 0x08270 */ u64 hoparb_wrr_ctrl_14; 6858#define VXGE_HAL_HOPARB_WRR_CTRL_14_SS_112_NUM(val) vBIT(val, 3, 5) 6859#define VXGE_HAL_HOPARB_WRR_CTRL_14_SS_113_NUM(val) vBIT(val, 11, 5) 6860#define VXGE_HAL_HOPARB_WRR_CTRL_14_SS_114_NUM(val) vBIT(val, 19, 5) 6861#define VXGE_HAL_HOPARB_WRR_CTRL_14_SS_115_NUM(val) vBIT(val, 27, 5) 6862#define VXGE_HAL_HOPARB_WRR_CTRL_14_SS_116_NUM(val) vBIT(val, 35, 5) 6863#define VXGE_HAL_HOPARB_WRR_CTRL_14_SS_117_NUM(val) vBIT(val, 43, 5) 6864#define VXGE_HAL_HOPARB_WRR_CTRL_14_SS_118_NUM(val) vBIT(val, 51, 5) 6865#define VXGE_HAL_HOPARB_WRR_CTRL_14_SS_119_NUM(val) vBIT(val, 59, 5) 6866/* 0x08278 */ u64 hoparb_wrr_ctrl_15; 6867#define VXGE_HAL_HOPARB_WRR_CTRL_15_SS_120_NUM(val) vBIT(val, 3, 5) 6868#define VXGE_HAL_HOPARB_WRR_CTRL_15_SS_121_NUM(val) vBIT(val, 11, 5) 6869#define VXGE_HAL_HOPARB_WRR_CTRL_15_SS_122_NUM(val) vBIT(val, 19, 5) 6870#define VXGE_HAL_HOPARB_WRR_CTRL_15_SS_123_NUM(val) vBIT(val, 27, 5) 6871#define VXGE_HAL_HOPARB_WRR_CTRL_15_SS_124_NUM(val) vBIT(val, 35, 5) 6872#define VXGE_HAL_HOPARB_WRR_CTRL_15_SS_125_NUM(val) vBIT(val, 43, 5) 6873#define VXGE_HAL_HOPARB_WRR_CTRL_15_SS_126_NUM(val) vBIT(val, 51, 5) 6874#define VXGE_HAL_HOPARB_WRR_CTRL_15_SS_127_NUM(val) vBIT(val, 59, 5) 6875/* 0x08280 */ u64 hoparb_wrr_ctrl_16; 6876#define VXGE_HAL_HOPARB_WRR_CTRL_16_SS_128_NUM(val) vBIT(val, 3, 5) 6877#define VXGE_HAL_HOPARB_WRR_CTRL_16_SS_129_NUM(val) vBIT(val, 11, 5) 6878#define VXGE_HAL_HOPARB_WRR_CTRL_16_SS_130_NUM(val) vBIT(val, 19, 5) 6879#define VXGE_HAL_HOPARB_WRR_CTRL_16_SS_131_NUM(val) vBIT(val, 27, 5) 6880#define VXGE_HAL_HOPARB_WRR_CTRL_16_SS_132_NUM(val) vBIT(val, 35, 5) 6881#define VXGE_HAL_HOPARB_WRR_CTRL_16_SS_133_NUM(val) vBIT(val, 43, 5) 6882#define VXGE_HAL_HOPARB_WRR_CTRL_16_SS_134_NUM(val) vBIT(val, 51, 5) 6883#define VXGE_HAL_HOPARB_WRR_CTRL_16_SS_135_NUM(val) vBIT(val, 59, 5) 6884/* 0x08288 */ u64 hoparb_wrr_ctrl_17; 6885#define VXGE_HAL_HOPARB_WRR_CTRL_17_SS_136_NUM(val) vBIT(val, 3, 5) 6886#define VXGE_HAL_HOPARB_WRR_CTRL_17_SS_137_NUM(val) vBIT(val, 11, 5) 6887#define VXGE_HAL_HOPARB_WRR_CTRL_17_SS_138_NUM(val) vBIT(val, 19, 5) 6888#define VXGE_HAL_HOPARB_WRR_CTRL_17_SS_139_NUM(val) vBIT(val, 27, 5) 6889#define VXGE_HAL_HOPARB_WRR_CTRL_17_SS_140_NUM(val) vBIT(val, 35, 5) 6890#define VXGE_HAL_HOPARB_WRR_CTRL_17_SS_141_NUM(val) vBIT(val, 43, 5) 6891#define VXGE_HAL_HOPARB_WRR_CTRL_17_SS_142_NUM(val) vBIT(val, 51, 5) 6892#define VXGE_HAL_HOPARB_WRR_CTRL_17_SS_143_NUM(val) vBIT(val, 59, 5) 6893/* 0x08290 */ u64 hoparb_wrr_ctrl_18; 6894#define VXGE_HAL_HOPARB_WRR_CTRL_18_SS_144_NUM(val) vBIT(val, 3, 5) 6895#define VXGE_HAL_HOPARB_WRR_CTRL_18_SS_145_NUM(val) vBIT(val, 11, 5) 6896#define VXGE_HAL_HOPARB_WRR_CTRL_18_SS_146_NUM(val) vBIT(val, 19, 5) 6897#define VXGE_HAL_HOPARB_WRR_CTRL_18_SS_147_NUM(val) vBIT(val, 27, 5) 6898#define VXGE_HAL_HOPARB_WRR_CTRL_18_SS_148_NUM(val) vBIT(val, 35, 5) 6899#define VXGE_HAL_HOPARB_WRR_CTRL_18_SS_149_NUM(val) vBIT(val, 43, 5) 6900#define VXGE_HAL_HOPARB_WRR_CTRL_18_SS_150_NUM(val) vBIT(val, 51, 5) 6901#define VXGE_HAL_HOPARB_WRR_CTRL_18_SS_151_NUM(val) vBIT(val, 59, 5) 6902/* 0x08298 */ u64 hoparb_wrr_ctrl_19; 6903#define VXGE_HAL_HOPARB_WRR_CTRL_19_SS_152_NUM(val) vBIT(val, 3, 5) 6904/* 0x082a0 */ u64 hoparb_wrr_cmp_0; 6905#define VXGE_HAL_HOPARB_WRR_CMP_0_VP0_NUM(val) vBIT(val, 3, 5) 6906#define VXGE_HAL_HOPARB_WRR_CMP_0_VP1_NUM(val) vBIT(val, 11, 5) 6907#define VXGE_HAL_HOPARB_WRR_CMP_0_VP2_NUM(val) vBIT(val, 19, 5) 6908#define VXGE_HAL_HOPARB_WRR_CMP_0_VP3_NUM(val) vBIT(val, 27, 5) 6909#define VXGE_HAL_HOPARB_WRR_CMP_0_VP4_NUM(val) vBIT(val, 35, 5) 6910#define VXGE_HAL_HOPARB_WRR_CMP_0_VP5_NUM(val) vBIT(val, 43, 5) 6911#define VXGE_HAL_HOPARB_WRR_CMP_0_VP6_NUM(val) vBIT(val, 51, 5) 6912#define VXGE_HAL_HOPARB_WRR_CMP_0_VP7_NUM(val) vBIT(val, 59, 5) 6913/* 0x082a8 */ u64 hoparb_wrr_cmp_1; 6914#define VXGE_HAL_HOPARB_WRR_CMP_1_VP8_NUM(val) vBIT(val, 3, 5) 6915#define VXGE_HAL_HOPARB_WRR_CMP_1_VP9_NUM(val) vBIT(val, 11, 5) 6916#define VXGE_HAL_HOPARB_WRR_CMP_1_VP10_NUM(val) vBIT(val, 19, 5) 6917#define VXGE_HAL_HOPARB_WRR_CMP_1_VP11_NUM(val) vBIT(val, 27, 5) 6918#define VXGE_HAL_HOPARB_WRR_CMP_1_VP12_NUM(val) vBIT(val, 35, 5) 6919#define VXGE_HAL_HOPARB_WRR_CMP_1_VP13_NUM(val) vBIT(val, 43, 5) 6920#define VXGE_HAL_HOPARB_WRR_CMP_1_VP14_NUM(val) vBIT(val, 51, 5) 6921#define VXGE_HAL_HOPARB_WRR_CMP_1_VP15_NUM(val) vBIT(val, 59, 5) 6922/* 0x082b0 */ u64 hoparb_wrr_cmp_2; 6923#define VXGE_HAL_HOPARB_WRR_CMP_2_VP16_NUM(val) vBIT(val, 3, 5) 6924 u8 unused082e8[0x082e8 - 0x082b8]; 6925 6926/* 0x082e8 */ u64 hop_bck_stats0; 6927#define VXGE_HAL_HOP_BCK_STATS0_HO_DISPATCH_CNT(val) vBIT(val, 0, 32) 6928#define VXGE_HAL_HOP_BCK_STATS0_HO_DROP_CNT(val) vBIT(val, 32, 32) 6929 u8 unused08400[0x08400 - 0x082f0]; 6930 6931/* 0x08400 */ u64 pcmg3_int_status; 6932#define VXGE_HAL_PCMG3_INT_STATUS_DAM_ERR_DAM_INT mBIT(0) 6933#define VXGE_HAL_PCMG3_INT_STATUS_PSTC_ERR_PSTC_INT mBIT(1) 6934#define VXGE_HAL_PCMG3_INT_STATUS_PH2L_ERR0_PH2L_INT mBIT(2) 6935/* 0x08408 */ u64 pcmg3_int_mask; 6936/* 0x08410 */ u64 dam_err_reg; 6937#define VXGE_HAL_DAM_ERR_REG_DAM_RDSB_ECC_SG_ERR mBIT(0) 6938#define VXGE_HAL_DAM_ERR_REG_DAM_WRSB_ECC_SG_ERR mBIT(1) 6939#define VXGE_HAL_DAM_ERR_REG_DAM_HPPEDAT_ECC_SG_ERR mBIT(3) 6940#define VXGE_HAL_DAM_ERR_REG_DAM_LPPEDAT_ECC_SG_ERR mBIT(4) 6941#define VXGE_HAL_DAM_ERR_REG_DAM_WRRESP_ECC_SG_ERR mBIT(5) 6942#define VXGE_HAL_DAM_ERR_REG_DAM_RDSB_ECC_DB_ERR mBIT(32) 6943#define VXGE_HAL_DAM_ERR_REG_DAM_WRSB_ECC_DB_ERR mBIT(33) 6944#define VXGE_HAL_DAM_ERR_REG_DAM_HPPEDAT_ECC_DB_ERR mBIT(34) 6945#define VXGE_HAL_DAM_ERR_REG_DAM_LPPEDAT_ECC_DB_ERR mBIT(35) 6946#define VXGE_HAL_DAM_ERR_REG_DAM_WRRESP_ECC_DB_ERR mBIT(36) 6947#define VXGE_HAL_DAM_ERR_REG_DAM_HPRD_ERR mBIT(40) 6948#define VXGE_HAL_DAM_ERR_REG_DAM_LPRD_0_ERR mBIT(41) 6949#define VXGE_HAL_DAM_ERR_REG_DAM_LPRD_1_ERR mBIT(42) 6950#define VXGE_HAL_DAM_ERR_REG_DAM_HPPEDAT_OVERFLOW_ERR mBIT(48) 6951#define VXGE_HAL_DAM_ERR_REG_DAM_LPPEDAT_OVERFLOW_ERR mBIT(49) 6952#define VXGE_HAL_DAM_ERR_REG_DAM_WRRESP_OVERFLOW_ERR mBIT(50) 6953#define VXGE_HAL_DAM_ERR_REG_DAM_SM_ERR mBIT(56) 6954/* 0x08418 */ u64 dam_err_mask; 6955/* 0x08420 */ u64 dam_err_alarm; 6956/* 0x08428 */ u64 pstc_err_reg; 6957#define VXGE_HAL_PSTC_ERR_REG_STC_RPEIF_REQ_FIFO_ERR mBIT(0) 6958#define VXGE_HAL_PSTC_ERR_REG_STC_RPEIF_ECRESP_FIFO_ERR mBIT(1) 6959#define VXGE_HAL_PSTC_ERR_REG_STC_RPEIF_BUFFRESP_FIFO_ERR mBIT(2) 6960#define VXGE_HAL_PSTC_ERR_REG_STC_ARB_RPE_FIFO_ERR mBIT(3) 6961#define VXGE_HAL_PSTC_ERR_REG_STC_CP2STC_FIFO_ERR mBIT(4) 6962/* 0x08430 */ u64 pstc_err_mask; 6963/* 0x08438 */ u64 pstc_err_alarm; 6964/* 0x08440 */ u64 ph2l_err0_reg; 6965#define VXGE_HAL_PH2L_ERR0_REG_H2L_HOC_XFER_DATX_OFLOW_ERR mBIT(0) 6966#define VXGE_HAL_PH2L_ERR0_REG_H2L_HOC_XFER_CTLX_OFLOW_ERR mBIT(1) 6967#define VXGE_HAL_PH2L_ERR0_REG_H2L_HOC_XFER_PARSE_ERR mBIT(2) 6968#define VXGE_HAL_PH2L_ERR0_REG_H2L_HOC_XFER_TCPOP_BYTES_ERR mBIT(3) 6969#define VXGE_HAL_PH2L_ERR0_REG_H2L_HOC_XFER_IDATA_BYTES_ERR mBIT(4) 6970#define VXGE_HAL_PH2L_ERR0_REG_H2L_HOC_XFER_PLDTYPE_ERR mBIT(5) 6971#define VXGE_HAL_PH2L_ERR0_REG_H2L_HOC_XFER_OD_ODLIST_LEN_ERR mBIT(6) 6972#define VXGE_HAL_PH2L_ERR0_REG_H2L_HOC_XFER_VPATH_ERR mBIT(7) 6973#define VXGE_HAL_PH2L_ERR0_REG_H2L_PHDR_MEM_DB_ERR(val) vBIT(val, 8, 2) 6974#define VXGE_HAL_PH2L_ERR0_REG_H2L_IDATA_MEM_DB_ERR(val) vBIT(val, 10, 2) 6975#define VXGE_HAL_PH2L_ERR0_REG_H2L_RO_CACHE_DB_ERR(val) vBIT(val, 12, 3) 6976#define VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_TBL_DB_ERR mBIT(15) 6977#define VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_MUX_FIFO_ERR mBIT(16) 6978#define VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_CCTL_FIFO_ERR mBIT(17) 6979#define VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_CCTL_FIFO_ERR mBIT(18) 6980#define VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_MUX_CRED_CNT_ERR mBIT(19) 6981#define VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_PDI_CRED_CNT_ERR mBIT(20) 6982#define VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_PCTL_SHADOW_ERR mBIT(21) 6983#define VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_OPC_SHADOW_ERR mBIT(22) 6984#define VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_MUX_SHADOW_ERR mBIT(23) 6985#define VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_PDI_SHADOW_ERR mBIT(24) 6986#define VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_LCTL_SHADOW_ERR mBIT(26) 6987#define VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_TXI_SHADOW_ERR mBIT(27) 6988#define VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_RXI_SHADOW_ERR mBIT(28) 6989#define VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_HPI_SHADOW_ERR mBIT(29) 6990#define VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_CCTL_SHADOW_ERR mBIT(30) 6991#define VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_PCTL_FSM_ERR mBIT(31) 6992#define VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_MUX_FSM_ERR mBIT(32) 6993#define VXGE_HAL_PH2L_ERR0_REG_H2L_LOG_LO_COMPL_ERR mBIT(33) 6994#define VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_LCTL_FSM_ERR mBIT(34) 6995#define VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_TXI_FSM_ERR mBIT(35) 6996#define VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_SLOT_MGMT_ERR mBIT(36) 6997#define VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_HPI_FSM_ERR mBIT(37) 6998#define VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_CCTL_FSM_ERR mBIT(38) 6999#define VXGE_HAL_PH2L_ERR0_REG_H2L_ROCRC_HOP_OFLOW_ERR mBIT(39) 7000#define VXGE_HAL_PH2L_ERR0_REG_H2L_PDA_H2L_DONE_FIFO_OVERFLOW mBIT(40) 7001#define VXGE_HAL_PH2L_ERR0_REG_H2L_PHDR_MEM_SG_ERR(val) vBIT(val, 48, 2) 7002#define VXGE_HAL_PH2L_ERR0_REG_H2L_IDATA_MEM_SG_ERR(val) vBIT(val, 50, 2) 7003#define VXGE_HAL_PH2L_ERR0_REG_H2L_RO_CACHE_SG_ERR(val) vBIT(val, 52, 3) 7004#define VXGE_HAL_PH2L_ERR0_REG_H2L_RETXK_TBL_SG_ERR mBIT(55) 7005/* 0x08448 */ u64 ph2l_err0_mask; 7006/* 0x08450 */ u64 ph2l_err0_alarm; 7007/* 0x08458 */ u64 dam_bypass_queue_0; 7008#define VXGE_HAL_DAM_BYPASS_QUEUE_0_ENABLE mBIT(0) 7009#define VXGE_HAL_DAM_BYPASS_QUEUE_0_BASE(val) vBIT(val, 8, 24) 7010#define VXGE_HAL_DAM_BYPASS_QUEUE_0_LENGTH(val) vBIT(val, 40, 24) 7011/* 0x08460 */ u64 dam_bypass_queue_1; 7012#define VXGE_HAL_DAM_BYPASS_QUEUE_1_BASE(val) vBIT(val, 8, 24) 7013#define VXGE_HAL_DAM_BYPASS_QUEUE_1_LENGTH(val) vBIT(val, 40, 24) 7014/* 0x08468 */ u64 dam_bypass_queue_2; 7015#define VXGE_HAL_DAM_BYPASS_QUEUE_2_BASE(val) vBIT(val, 8, 24) 7016#define VXGE_HAL_DAM_BYPASS_QUEUE_2_LENGTH(val) vBIT(val, 40, 24) 7017/* 0x08470 */ u64 dam_ecc_ctrl; 7018#define VXGE_HAL_DAM_ECC_CTRL_DISABLE mBIT(0) 7019/* 0x08478 */ u64 ph2l_cfg0; 7020#define VXGE_HAL_PH2L_CFG0_PHDR_MEM_ECC_ENABLE_N mBIT(15) 7021#define VXGE_HAL_PH2L_CFG0_IDATA_MEM_ECC_ENABLE_N mBIT(23) 7022#define VXGE_HAL_PH2L_CFG0_RO_CACHE_ECC_ENABLE_N mBIT(31) 7023#define VXGE_HAL_PH2L_CFG0_RETXK_TBL_ECC_ENABLE_N mBIT(39) 7024#define VXGE_HAL_PH2L_CFG0_LOG_XON_CHECK_ENA mBIT(47) 7025#define VXGE_HAL_PH2L_CFG0_LOG_VPBP_CHECK_ENA mBIT(55) 7026#define VXGE_HAL_PH2L_CFG0_NBR_RETX_SLOTS_PER_VP(val) vBIT(val, 62, 2) 7027/* 0x08480 */ u64 pstc_cfg0; 7028#define VXGE_HAL_PSTC_CFG0_PGSYNC_WAIT_TOKEN_ENABLE mBIT(5) 7029#define VXGE_HAL_PSTC_CFG0_PGSYNC_CNTDOWN_TIMER_ENABLE mBIT(6) 7030#define VXGE_HAL_PSTC_CFG0_PGSYNC_SRC_NOTIFY_ENABLE mBIT(7) 7031#define VXGE_HAL_PSTC_CFG0_PGSYNC_CNTDOWN_START_VALUE(val) vBIT(val, 12, 4) 7032 u8 unused08510[0x08510 - 0x08488]; 7033 7034/* 0x08510 */ u64 neterion_membist_control; 7035#define VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_CMG1 mBIT(0) 7036#define VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_CMG2 mBIT(1) 7037#define VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_CMG3 mBIT(2) 7038#define VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_DRBELL mBIT(3) 7039#define VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_FBIF mBIT(4) 7040#define VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_MSG mBIT(5) 7041#define VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_ONE mBIT(6) 7042#define VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_PCI mBIT(7) 7043#define VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_RTDMA mBIT(8) 7044#define VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_WRDMA mBIT(9) 7045#define VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_XGMAC mBIT(10) 7046#define VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_FB mBIT(11) 7047#define VXGE_HAL_NETERION_MEMBIST_CONTROL_INC_CM mBIT(12) 7048#define VXGE_HAL_NETERION_MEMBIST_CONTROL_OVERRIDE_FB_DONE mBIT(16) 7049#define VXGE_HAL_NETERION_MEMBIST_CONTROL_OVERRIDE_CM_DONE mBIT(17) 7050#define VXGE_HAL_NETERION_MEMBIST_CONTROL_INCLUDE_PCIE_MEMS mBIT(24) 7051#define VXGE_HAL_NETERION_MEMBIST_CONTROL_LAUNCH mBIT(31) 7052#define VXGE_HAL_NETERION_MEMBIST_CONTROL_NMBC_DONE mBIT(48) 7053#define VXGE_HAL_NETERION_MEMBIST_CONTROL_NMBC_ERROR(val) vBIT(val, 56, 4) 7054/* 0x08518 */ u64 neterion_membist_errors; 7055#define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_CMG1(val) vBIT(val, 0, 3) 7056#define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_CMG2(val) vBIT(val, 3, 3) 7057#define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_CMG3(val) vBIT(val, 6, 3) 7058#define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_DRBELL(val) vBIT(val, 9, 3) 7059#define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_FBif (val) vBIT(val, 12, 3) 7060#define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_MSG(val) vBIT(val, 15, 3) 7061#define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_ONE(val) vBIT(val, 18, 3) 7062#define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_PCI(val) vBIT(val, 21, 3) 7063#define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_RTDMA(val) vBIT(val, 24, 3) 7064#define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_WRDMA(val) vBIT(val, 27, 3) 7065#define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_XGMAC(val) vBIT(val, 30, 3) 7066#define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_FB mBIT(33) 7067#define VXGE_HAL_NETERION_MEMBIST_ERRORS_NMBC_CM mBIT(34) 7068/* 0x08520 */ u64 rr_cqm_cache_rtl_top_0; 7069#define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7070 vBIT(val, 0, 2) 7071#define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK1_FUSE(val)\ 7072 vBIT(val, 2, 8) 7073#define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK1_ADD_FUSE(val)\ 7074 vBIT(val, 10, 2) 7075#define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK0_FUSE(val)\ 7076 vBIT(val, 12, 8) 7077#define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK0_ADD_FUSE(val)\ 7078 vBIT(val, 20, 2) 7079/* 0x08528 */ u64 rr_cqm_cache_rtl_top_1; 7080#define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7081 vBIT(val, 0, 2) 7082#define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK1_FUSE(val)\ 7083 vBIT(val, 2, 8) 7084#define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK1_ADD_FUSE(val)\ 7085 vBIT(val, 10, 2) 7086#define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK0_FUSE(val)\ 7087 vBIT(val, 12, 8) 7088#define VXGE_HAL_RR_CQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK0_ADD_FUSE(val)\ 7089 vBIT(val, 20, 2) 7090/* 0x08530 */ u64 rr_sqm_cache_rtl_top_0; 7091#define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7092 vBIT(val, 0, 2) 7093#define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK1_FUSE(val)\ 7094 vBIT(val, 2, 8) 7095#define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK1_ADD_FUSE(val)\ 7096 vBIT(val, 10, 2) 7097#define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK0_FUSE(val)\ 7098 vBIT(val, 12, 8) 7099#define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_0_CMG1_NMB_IO_BANK0_ADD_FUSE(val)\ 7100 vBIT(val, 20, 2) 7101/* 0x08538 */ u64 rr_sqm_cache_rtl_top_1; 7102#define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7103 vBIT(val, 0, 2) 7104#define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK1_FUSE(val)\ 7105 vBIT(val, 2, 8) 7106#define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK1_ADD_FUSE(val)\ 7107 vBIT(val, 10, 2) 7108#define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK0_FUSE(val)\ 7109 vBIT(val, 12, 8) 7110#define VXGE_HAL_RR_SQM_CACHE_RTL_TOP_1_CMG1_NMB_IO_BANK0_ADD_FUSE(val)\ 7111 vBIT(val, 20, 2) 7112/* 0x08540 */ u64 rf_sqm_lprpedat_rtl_top_0; 7113#define VXGE_HAL_RF_SQM_LPRPEDAT_RTL_TOP_0_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7114 vBIT(val, 0, 2) 7115#define VXGE_HAL_RF_SQM_LPRPEDAT_RTL_TOP_0_CMG1_NMB_IO_ALL_FUSE(val)\ 7116 vBIT(val, 2, 8) 7117/* 0x08548 */ u64 rf_sqm_lprpedat_rtl_top_1; 7118#define VXGE_HAL_RF_SQM_LPRPEDAT_RTL_TOP_1_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7119 vBIT(val, 0, 2) 7120#define VXGE_HAL_RF_SQM_LPRPEDAT_RTL_TOP_1_CMG1_NMB_IO_ALL_FUSE(val)\ 7121 vBIT(val, 2, 8) 7122/* 0x08550 */ u64 rr_sqm_dmawqersp_rtl_top_0; 7123#define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_0_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7124 vBIT(val, 0, 2) 7125#define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_0_CMG1_NMB_IO_BANK1_FUSE(val)\ 7126 vBIT(val, 2, 7) 7127#define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_0_CMG1_NMB_IO_BANK1_ADD_FUSE(val)\ 7128 vBIT(val, 9, 3) 7129#define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_0_CMG1_NMB_IO_BANK0_FUSE(val)\ 7130 vBIT(val, 12, 7) 7131#define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_0_CMG1_NMB_IO_BANK0_ADD_FUSE(val)\ 7132 vBIT(val, 19, 3) 7133/* 0x08558 */ u64 rr_sqm_dmawqersp_rtl_top_1; 7134#define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_1_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7135 vBIT(val, 0, 2) 7136#define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_1_CMG1_NMB_IO_BANK1_FUSE(val)\ 7137 vBIT(val, 2, 7) 7138#define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_1_CMG1_NMB_IO_BANK1_ADD_FUSE(val)\ 7139 vBIT(val, 9, 3) 7140#define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_1_CMG1_NMB_IO_BANK0_FUSE(val)\ 7141 vBIT(val, 12, 7) 7142#define VXGE_HAL_RR_SQM_DMAWQERSP_RTL_TOP_1_CMG1_NMB_IO_BANK0_ADD_FUSE(val)\ 7143 vBIT(val, 19, 3) 7144/* 0x08560 */ u64 rf_cqm_dmacqersp_rtl_top; 7145#define VXGE_HAL_RF_CQM_DMACQERSP_RTL_TOP_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7146 vBIT(val, 0, 2) 7147#define VXGE_HAL_RF_CQM_DMACQERSP_RTL_TOP_CMG1_NMB_IO_ALL_FUSE(val)\ 7148 vBIT(val, 2, 8) 7149/* 0x08568 */ u64 rf_sqm_rpereqdat_rtl_top_0; 7150#define VXGE_HAL_RF_SQM_RPEREQDAT_RTL_TOP_0_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7151 vBIT(val, 0, 2) 7152#define VXGE_HAL_RF_SQM_RPEREQDAT_RTL_TOP_0_CMG1_NMB_IO_ALL_FUSE(val)\ 7153 vBIT(val, 2, 8) 7154/* 0x08570 */ u64 rf_sqm_rpereqdat_rtl_top_1; 7155#define VXGE_HAL_RF_SQM_RPEREQDAT_RTL_TOP_1_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7156 vBIT(val, 0, 2) 7157#define VXGE_HAL_RF_SQM_RPEREQDAT_RTL_TOP_1_CMG1_NMB_IO_ALL_FUSE(val)\ 7158 vBIT(val, 2, 8) 7159/* 0x08578 */ u64 rf_sscc_ssr_rtl_top_0_0; 7160#define VXGE_HAL_RF_SSCC_SSR_RTL_TOP_0_0_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7161 vBIT(val, 0, 2) 7162#define VXGE_HAL_RF_SSCC_SSR_RTL_TOP_0_0_CMG1_NMB_IO_ALL_FUSE(val)\ 7163 vBIT(val, 2, 7) 7164/* 0x08580 */ u64 rf_sscc_ssr_rtl_top_1_0; 7165#define VXGE_HAL_RF_SSCC_SSR_RTL_TOP_1_0_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7166 vBIT(val, 0, 2) 7167#define VXGE_HAL_RF_SSCC_SSR_RTL_TOP_1_0_CMG1_NMB_IO_ALL_FUSE(val)\ 7168 vBIT(val, 2, 7) 7169/* 0x08588 */ u64 rf_sscc_ssr_rtl_top_0_1; 7170#define VXGE_HAL_RF_SSCC_SSR_RTL_TOP_0_1_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7171 vBIT(val, 0, 2) 7172#define VXGE_HAL_RF_SSCC_SSR_RTL_TOP_0_1_CMG1_NMB_IO_ALL_FUSE(val)\ 7173 vBIT(val, 2, 7) 7174/* 0x08590 */ u64 rf_sscc_ssr_rtl_top_1_1; 7175#define VXGE_HAL_RF_SSCC_SSR_RTL_TOP_1_1_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7176 vBIT(val, 0, 2) 7177#define VXGE_HAL_RF_SSCC_SSR_RTL_TOP_1_1_CMG1_NMB_IO_ALL_FUSE(val)\ 7178 vBIT(val, 2, 7) 7179/* 0x08598 */ u64 rf_ssc_cm_resp_rtl_top_1_ssc0; 7180#define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_1_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7181 vBIT(val, 0, 2) 7182#define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_1_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\ 7183 vBIT(val, 2, 8) 7184/* 0x085a0 */ u64 rf_ssc_cm_resp_rtl_top_0_ssc1; 7185#define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_0_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7186 vBIT(val, 0, 2) 7187#define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_0_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\ 7188 vBIT(val, 2, 8) 7189/* 0x085a8 */ u64 rf_ssc_cm_resp_rtl_top_1_sscl; 7190#define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_1_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7191 vBIT(val, 0, 2) 7192#define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_1_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\ 7193 vBIT(val, 2, 8) 7194/* 0x085b0 */ u64 rf_ssc_cm_resp_rtl_top_0_ssc0; 7195#define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_0_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7196 vBIT(val, 0, 2) 7197#define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_0_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\ 7198 vBIT(val, 2, 8) 7199/* 0x085b8 */ u64 rf_ssc_cm_resp_rtl_top_1_ssc1; 7200#define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_1_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7201 vBIT(val, 0, 2) 7202#define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_1_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\ 7203 vBIT(val, 2, 8) 7204/* 0x085c0 */ u64 rf_ssc_cm_resp_rtl_top_0_sscl; 7205#define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_0_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7206 vBIT(val, 0, 2) 7207#define VXGE_HAL_RF_SSC_CM_RESP_RTL_TOP_0_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\ 7208 vBIT(val, 2, 8) 7209/* 0x085c8 */ u64 rf_ssc_ssr_resp_rtl_top_ssc0; 7210#define VXGE_HAL_RF_SSC_SSR_RESP_RTL_TOP_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7211 vBIT(val, 0, 2) 7212#define VXGE_HAL_RF_SSC_SSR_RESP_RTL_TOP_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\ 7213 vBIT(val, 2, 8) 7214/* 0x085d0 */ u64 rf_ssc_ssr_resp_rtl_top_ssc1; 7215#define VXGE_HAL_RF_SSC_SSR_RESP_RTL_TOP_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7216 vBIT(val, 0, 2) 7217#define VXGE_HAL_RF_SSC_SSR_RESP_RTL_TOP_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\ 7218 vBIT(val, 2, 8) 7219/* 0x085d8 */ u64 rf_ssc_ssr_resp_rtl_top_sscl; 7220#define VXGE_HAL_RF_SSC_SSR_RESP_RTL_TOP_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7221 vBIT(val, 0, 2) 7222#define VXGE_HAL_RF_SSC_SSR_RESP_RTL_TOP_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\ 7223 vBIT(val, 2, 8) 7224/* 0x085e0 */ u64 rf_ssc_tsr_resp_rtl_top_1_ssc0; 7225#define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_1_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7226 vBIT(val, 0, 2) 7227#define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_1_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\ 7228 vBIT(val, 2, 8) 7229/* 0x085e8 */ u64 rf_ssc_tsr_resp_rtl_top_2_ssc0; 7230#define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_2_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7231 vBIT(val, 0, 2) 7232#define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_2_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\ 7233 vBIT(val, 2, 8) 7234/* 0x085f0 */ u64 rf_ssc_tsr_resp_rtl_top_2_ssc1; 7235#define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_2_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7236 vBIT(val, 0, 2) 7237#define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_2_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\ 7238 vBIT(val, 2, 8) 7239/* 0x085f8 */ u64 rf_ssc_tsr_resp_rtl_top_0_sscl; 7240#define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_0_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7241 vBIT(val, 0, 2) 7242#define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_0_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\ 7243 vBIT(val, 2, 8) 7244/* 0x08600 */ u64 rf_ssc_tsr_resp_rtl_top_0_ssc0; 7245#define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_0_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7246 vBIT(val, 0, 2) 7247#define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_0_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\ 7248 vBIT(val, 2, 8) 7249/* 0x08608 */ u64 rf_ssc_tsr_resp_rtl_top_0_ssc1; 7250#define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_0_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7251 vBIT(val, 0, 2) 7252#define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_0_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\ 7253 vBIT(val, 2, 8) 7254/* 0x08610 */ u64 rf_ssc_tsr_resp_rtl_top_1_ssc1; 7255#define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_1_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7256 vBIT(val, 0, 2) 7257#define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_1_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\ 7258 vBIT(val, 2, 8) 7259/* 0x08618 */ u64 rf_ssc_tsr_resp_rtl_top_1_sscl; 7260#define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_1_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7261 vBIT(val, 0, 2) 7262#define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_1_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\ 7263 vBIT(val, 2, 8) 7264/* 0x08620 */ u64 rf_ssc_tsr_resp_rtl_top_2_sscl; 7265#define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_2_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7266 vBIT(val, 0, 2) 7267#define VXGE_HAL_RF_SSC_TSR_RESP_RTL_TOP_2_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\ 7268 vBIT(val, 2, 8) 7269/* 0x08628 */ u64 rf_ssc_state_rtl_top_1_ssc0; 7270#define VXGE_HAL_RF_SSC_STATE_RTL_TOP_1_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7271 vBIT(val, 0, 2) 7272#define VXGE_HAL_RF_SSC_STATE_RTL_TOP_1_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\ 7273 vBIT(val, 2, 8) 7274/* 0x08630 */ u64 rf_ssc_state_rtl_top_2_ssc0; 7275#define VXGE_HAL_RF_SSC_STATE_RTL_TOP_2_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7276 vBIT(val, 0, 2) 7277#define VXGE_HAL_RF_SSC_STATE_RTL_TOP_2_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\ 7278 vBIT(val, 2, 8) 7279/* 0x08638 */ u64 rf_ssc_state_rtl_top_1_ssc1; 7280#define VXGE_HAL_RF_SSC_STATE_RTL_TOP_1_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7281 vBIT(val, 0, 2) 7282#define VXGE_HAL_RF_SSC_STATE_RTL_TOP_1_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\ 7283 vBIT(val, 2, 8) 7284/* 0x08640 */ u64 rf_ssc_state_rtl_top_2_ssc1; 7285#define VXGE_HAL_RF_SSC_STATE_RTL_TOP_2_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7286 vBIT(val, 0, 2) 7287#define VXGE_HAL_RF_SSC_STATE_RTL_TOP_2_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\ 7288 vBIT(val, 2, 8) 7289/* 0x08648 */ u64 rf_ssc_state_rtl_top_1_sscl; 7290#define VXGE_HAL_RF_SSC_STATE_RTL_TOP_1_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7291 vBIT(val, 0, 2) 7292#define VXGE_HAL_RF_SSC_STATE_RTL_TOP_1_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\ 7293 vBIT(val, 2, 8) 7294/* 0x08650 */ u64 rf_ssc_state_rtl_top_2_sscl; 7295#define VXGE_HAL_RF_SSC_STATE_RTL_TOP_2_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7296 vBIT(val, 0, 2) 7297#define VXGE_HAL_RF_SSC_STATE_RTL_TOP_2_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\ 7298 vBIT(val, 2, 8) 7299/* 0x08658 */ u64 rf_ssc_state_rtl_top_0_ssc0; 7300#define VXGE_HAL_RF_SSC_STATE_RTL_TOP_0_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7301 vBIT(val, 0, 2) 7302#define VXGE_HAL_RF_SSC_STATE_RTL_TOP_0_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\ 7303 vBIT(val, 2, 8) 7304/* 0x08660 */ u64 rf_ssc_state_rtl_top_3_ssc0; 7305#define VXGE_HAL_RF_SSC_STATE_RTL_TOP_3_SSC0_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7306 vBIT(val, 0, 2) 7307#define VXGE_HAL_RF_SSC_STATE_RTL_TOP_3_SSC0_CMG1_NMB_IO_ALL_FUSE(val)\ 7308 vBIT(val, 2, 8) 7309/* 0x08668 */ u64 rf_ssc_state_rtl_top_0_ssc1; 7310#define VXGE_HAL_RF_SSC_STATE_RTL_TOP_0_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7311 vBIT(val, 0, 2) 7312#define VXGE_HAL_RF_SSC_STATE_RTL_TOP_0_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\ 7313 vBIT(val, 2, 8) 7314/* 0x08670 */ u64 rf_ssc_state_rtl_top_3_ssc1; 7315#define VXGE_HAL_RF_SSC_STATE_RTL_TOP_3_SSC1_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7316 vBIT(val, 0, 2) 7317#define VXGE_HAL_RF_SSC_STATE_RTL_TOP_3_SSC1_CMG1_NMB_IO_ALL_FUSE(val)\ 7318 vBIT(val, 2, 8) 7319/* 0x08678 */ u64 rf_ssc_state_rtl_top_0_sscl; 7320#define VXGE_HAL_RF_SSC_STATE_RTL_TOP_0_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7321 vBIT(val, 0, 2) 7322#define VXGE_HAL_RF_SSC_STATE_RTL_TOP_0_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\ 7323 vBIT(val, 2, 8) 7324/* 0x08680 */ u64 rf_ssc_state_rtl_top_3_sscl; 7325#define VXGE_HAL_RF_SSC_STATE_RTL_TOP_3_SSCL_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7326 vBIT(val, 0, 2) 7327#define VXGE_HAL_RF_SSC_STATE_RTL_TOP_3_SSCL_CMG1_NMB_IO_ALL_FUSE(val)\ 7328 vBIT(val, 2, 8) 7329/* 0x08688 */ u64 rf_sscc_tsr_rtl_top_0; 7330#define VXGE_HAL_RF_SSCC_TSR_RTL_TOP_0_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7331 vBIT(val, 0, 2) 7332#define VXGE_HAL_RF_SSCC_TSR_RTL_TOP_0_CMG1_NMB_IO_ALL_FUSE(val)\ 7333 vBIT(val, 2, 8) 7334/* 0x08690 */ u64 rf_sscc_tsr_rtl_top_1; 7335#define VXGE_HAL_RF_SSCC_TSR_RTL_TOP_1_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7336 vBIT(val, 0, 2) 7337#define VXGE_HAL_RF_SSCC_TSR_RTL_TOP_1_CMG1_NMB_IO_ALL_FUSE(val)\ 7338 vBIT(val, 2, 8) 7339/* 0x08698 */ u64 rf_sscc_tsr_rtl_top_2; 7340#define VXGE_HAL_RF_SSCC_TSR_RTL_TOP_2_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7341 vBIT(val, 0, 2) 7342#define VXGE_HAL_RF_SSCC_TSR_RTL_TOP_2_CMG1_NMB_IO_ALL_FUSE(val)\ 7343 vBIT(val, 2, 8) 7344/* 0x086a0 */ u64 rf_uqm_cmcreq_rtl_top; 7345#define VXGE_HAL_RF_UQM_CMCREQ_RTL_TOP_CMG1_NMB_IO_REPAIR_STATUS(val)\ 7346 vBIT(val, 0, 2) 7347#define VXGE_HAL_RF_UQM_CMCREQ_RTL_TOP_CMG1_NMB_IO_ALL_FUSE(val)\ 7348 vBIT(val, 2, 8) 7349/* 0x086a8 */ u64 rr0_g3if_cm_ctrl_rtl_top; 7350#define VXGE_HAL_RR0_G3IF_CM_CTRL_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7351 vBIT(val, 0, 2) 7352#define VXGE_HAL_RR0_G3IF_CM_CTRL_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\ 7353 vBIT(val, 2, 8) 7354/* 0x086b0 */ u64 rr1_g3if_cm_ctrl_rtl_top; 7355#define VXGE_HAL_RR1_G3IF_CM_CTRL_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7356 vBIT(val, 0, 2) 7357#define VXGE_HAL_RR1_G3IF_CM_CTRL_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\ 7358 vBIT(val, 2, 8) 7359/* 0x086b8 */ u64 rr2_g3if_cm_ctrl_rtl_top; 7360#define VXGE_HAL_RR2_G3IF_CM_CTRL_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7361 vBIT(val, 0, 2) 7362#define VXGE_HAL_RR2_G3IF_CM_CTRL_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\ 7363 vBIT(val, 2, 8) 7364/* 0x086c0 */ u64 rf_g3if_cm_rd_rtl_top0; 7365#define VXGE_HAL_RF_G3IF_CM_RD_RTL_TOP0_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7366 vBIT(val, 0, 2) 7367#define VXGE_HAL_RF_G3IF_CM_RD_RTL_TOP0_CMG2_NMB_IO_ALL_FUSE(val)\ 7368 vBIT(val, 2, 8) 7369/* 0x086c8 */ u64 rf_g3if_cm_rd_rtl_top1; 7370#define VXGE_HAL_RF_G3IF_CM_RD_RTL_TOP1_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7371 vBIT(val, 0, 2) 7372#define VXGE_HAL_RF_G3IF_CM_RD_RTL_TOP1_CMG2_NMB_IO_ALL_FUSE(val)\ 7373 vBIT(val, 2, 8) 7374/* 0x086d0 */ u64 rf_g3if_cm_rd_rtl_top2; 7375#define VXGE_HAL_RF_G3IF_CM_RD_RTL_TOP2_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7376 vBIT(val, 0, 2) 7377#define VXGE_HAL_RF_G3IF_CM_RD_RTL_TOP2_CMG2_NMB_IO_ALL_FUSE(val)\ 7378 vBIT(val, 2, 8) 7379/* 0x086d8 */ u64 rf_cmg_msg2cmg_rtl_top_0_0; 7380#define VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_0_0_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7381 vBIT(val, 0, 2) 7382#define VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_0_0_CMG2_NMB_IO_ALL_FUSE(val)\ 7383 vBIT(val, 2, 6) 7384/* 0x086e0 */ u64 rf_cmg_msg2cmg_rtl_top_1_0; 7385#define VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_1_0_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7386 vBIT(val, 0, 2) 7387#define VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_1_0_CMG2_NMB_IO_ALL_FUSE(val)\ 7388 vBIT(val, 2, 6) 7389/* 0x086e8 */ u64 rf_cmg_msg2cmg_rtl_top_0_1; 7390#define VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_0_1_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7391 vBIT(val, 0, 2) 7392#define VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_0_1_CMG2_NMB_IO_ALL_FUSE(val)\ 7393 vBIT(val, 2, 6) 7394/* 0x086f0 */ u64 rf_cmg_msg2cmg_rtl_top_1_1; 7395#define VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_1_1_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7396 vBIT(val, 0, 2) 7397#define VXGE_HAL_RF_CMG_MSG2CMG_RTL_TOP_1_1_CMG2_NMB_IO_ALL_FUSE(val)\ 7398 vBIT(val, 2, 6) 7399/* 0x086f8 */ u64 rf_cp_dma_resp_rtl_top_0; 7400#define VXGE_HAL_RF_CP_DMA_RESP_RTL_TOP_0_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7401 vBIT(val, 0, 2) 7402#define VXGE_HAL_RF_CP_DMA_RESP_RTL_TOP_0_CMG2_NMB_IO_ALL_FUSE(val)\ 7403 vBIT(val, 2, 6) 7404/* 0x08700 */ u64 rf_cp_dma_resp_rtl_top_1; 7405#define VXGE_HAL_RF_CP_DMA_RESP_RTL_TOP_1_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7406 vBIT(val, 0, 2) 7407#define VXGE_HAL_RF_CP_DMA_RESP_RTL_TOP_1_CMG2_NMB_IO_ALL_FUSE(val)\ 7408 vBIT(val, 2, 6) 7409/* 0x08708 */ u64 rf_cp_dma_resp_rtl_top_2; 7410#define VXGE_HAL_RF_CP_DMA_RESP_RTL_TOP_2_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7411 vBIT(val, 0, 2) 7412#define VXGE_HAL_RF_CP_DMA_RESP_RTL_TOP_2_CMG2_NMB_IO_ALL_FUSE(val)\ 7413 vBIT(val, 2, 6) 7414/* 0x08710 */ u64 rf_cp_qcc2cxp_rtl_top; 7415#define VXGE_HAL_RF_CP_QCC2CXP_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7416 vBIT(val, 0, 2) 7417#define VXGE_HAL_RF_CP_QCC2CXP_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\ 7418 vBIT(val, 2, 7) 7419/* 0x08718 */ u64 rf_cp_stc2cp_rtl_top; 7420#define VXGE_HAL_RF_CP_STC2CP_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7421 vBIT(val, 0, 2) 7422#define VXGE_HAL_RF_CP_STC2CP_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\ 7423 vBIT(val, 2, 8) 7424/* 0x08720 */ u64 rf_cp_xt_trace_rtl_top; 7425#define VXGE_HAL_RF_CP_XT_TRACE_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7426 vBIT(val, 0, 2) 7427#define VXGE_HAL_RF_CP_XT_TRACE_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\ 7428 vBIT(val, 2, 8) 7429/* 0x08728 */ u64 rf_cp_xt_dtag_rtl_top; 7430#define VXGE_HAL_RF_CP_XT_DTAG_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7431 vBIT(val, 0, 2) 7432#define VXGE_HAL_RF_CP_XT_DTAG_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\ 7433 vBIT(val, 2, 6) 7434/* 0x08730 */ u64 rf_cp_xt_icache_rtl_top_0_0; 7435#define VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_0_0_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7436 vBIT(val, 0, 2) 7437#define VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_0_0_CMG2_NMB_IO_ALL_FUSE(val)\ 7438 vBIT(val, 2, 7) 7439/* 0x08738 */ u64 rf_cp_xt_icache_rtl_top_1_0; 7440#define VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_1_0_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7441 vBIT(val, 0, 2) 7442#define VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_1_0_CMG2_NMB_IO_ALL_FUSE(val)\ 7443 vBIT(val, 2, 7) 7444/* 0x08740 */ u64 rf_cp_xt_icache_rtl_top_0_1; 7445#define VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_0_1_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7446 vBIT(val, 0, 2) 7447#define VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_0_1_CMG2_NMB_IO_ALL_FUSE(val)\ 7448 vBIT(val, 2, 7) 7449/* 0x08748 */ u64 rf_cp_xt_icache_rtl_top_1_1; 7450#define VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_1_1_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7451 vBIT(val, 0, 2) 7452#define VXGE_HAL_RF_CP_XT_ICACHE_RTL_TOP_1_1_CMG2_NMB_IO_ALL_FUSE(val)\ 7453 vBIT(val, 2, 7) 7454/* 0x08750 */ u64 rf_cp_xt_itag_rtl_top; 7455#define VXGE_HAL_RF_CP_XT_ITAG_RTL_TOP_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7456 vBIT(val, 0, 2) 7457#define VXGE_HAL_RF_CP_XT_ITAG_RTL_TOP_CMG2_NMB_IO_ALL_FUSE(val)\ 7458 vBIT(val, 2, 6) 7459/* 0x08758 */ u64 rf_cp_xt_dcache_rtl_top_0_0; 7460#define VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_0_0_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7461 vBIT(val, 0, 2) 7462#define VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_0_0_CMG2_NMB_IO_ALL_FUSE(val)\ 7463 vBIT(val, 2, 7) 7464/* 0x08760 */ u64 rf_cp_xt_dcache_rtl_top_1_0; 7465#define VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_1_0_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7466 vBIT(val, 0, 2) 7467#define VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_1_0_CMG2_NMB_IO_ALL_FUSE(val)\ 7468 vBIT(val, 2, 7) 7469/* 0x08768 */ u64 rf_cp_xt_dcache_rtl_top_0_1; 7470#define VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_0_1_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7471 vBIT(val, 0, 2) 7472#define VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_0_1_CMG2_NMB_IO_ALL_FUSE(val)\ 7473 vBIT(val, 2, 7) 7474/* 0x08770 */ u64 rf_cp_xt_dcache_rtl_top_1_1; 7475#define VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_1_1_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7476 vBIT(val, 0, 2) 7477#define VXGE_HAL_RF_CP_XT_DCACHE_RTL_TOP_1_1_CMG2_NMB_IO_ALL_FUSE(val)\ 7478 vBIT(val, 2, 7) 7479/* 0x08778 */ u64 rf_xtmc_bdt_mem_rtl_top_0; 7480#define VXGE_HAL_RF_XTMC_BDT_MEM_RTL_TOP_0_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7481 vBIT(val, 0, 2) 7482#define VXGE_HAL_RF_XTMC_BDT_MEM_RTL_TOP_0_CMG2_NMB_IO_ALL_FUSE(val)\ 7483 vBIT(val, 2, 8) 7484/* 0x08780 */ u64 rf_xtmc_bdt_mem_rtl_top_1; 7485#define VXGE_HAL_RF_XTMC_BDT_MEM_RTL_TOP_1_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7486 vBIT(val, 0, 2) 7487#define VXGE_HAL_RF_XTMC_BDT_MEM_RTL_TOP_1_CMG2_NMB_IO_ALL_FUSE(val)\ 7488 vBIT(val, 2, 8) 7489/* 0x08788 */ u64 rf_xt_pif_sram_rtl_top_sram0; 7490#define VXGE_HAL_RF_XT_PIF_SRAM_RTL_TOP_SRAM0_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7491 vBIT(val, 0, 2) 7492#define VXGE_HAL_RF_XT_PIF_SRAM_RTL_TOP_SRAM0_CMG2_NMB_IO_ALL_FUSE(val)\ 7493 vBIT(val, 2, 8) 7494/* 0x08790 */ u64 rf_xt_pif_sram_rtl_top_sram1; 7495#define VXGE_HAL_RF_XT_PIF_SRAM_RTL_TOP_SRAM1_CMG2_NMB_IO_REPAIR_STATUS(val)\ 7496 vBIT(val, 0, 2) 7497#define VXGE_HAL_RF_XT_PIF_SRAM_RTL_TOP_SRAM1_CMG2_NMB_IO_ALL_FUSE(val)\ 7498 vBIT(val, 2, 8) 7499/* 0x08798 */ u64 rf_stc_srch_mem_rtl_top_0_0; 7500#define VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_0_0_CMG3_NMB_IO_REPAIR_STATUS(val)\ 7501 vBIT(val, 0, 2) 7502#define VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_0_0_CMG3_NMB_IO_ALL_FUSE(val)\ 7503 vBIT(val, 2, 8) 7504/* 0x087a0 */ u64 rf_stc_srch_mem_rtl_top_1_0; 7505#define VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_1_0_CMG3_NMB_IO_REPAIR_STATUS(val)\ 7506 vBIT(val, 0, 2) 7507#define VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_1_0_CMG3_NMB_IO_ALL_FUSE(val)\ 7508 vBIT(val, 2, 8) 7509/* 0x087a8 */ u64 rf_stc_srch_mem_rtl_top_0_1; 7510#define VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_0_1_CMG3_NMB_IO_REPAIR_STATUS(val)\ 7511 vBIT(val, 0, 2) 7512#define VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_0_1_CMG3_NMB_IO_ALL_FUSE(val)\ 7513 vBIT(val, 2, 8) 7514/* 0x087b0 */ u64 rf_stc_srch_mem_rtl_top_1_1; 7515#define VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_1_1_CMG3_NMB_IO_REPAIR_STATUS(val)\ 7516 vBIT(val, 0, 2) 7517#define VXGE_HAL_RF_STC_SRCH_MEM_RTL_TOP_1_1_CMG3_NMB_IO_ALL_FUSE(val)\ 7518 vBIT(val, 2, 8) 7519/* 0x087b8 */ u64 rf_dam_wrresp_rtl_top; 7520#define VXGE_HAL_RF_DAM_WRRESP_RTL_TOP_CMG3_NMB_IO_REPAIR_STATUS(val)\ 7521 vBIT(val, 0, 2) 7522#define VXGE_HAL_RF_DAM_WRRESP_RTL_TOP_CMG3_NMB_IO_ALL_FUSE(val)\ 7523 vBIT(val, 2, 6) 7524/* 0x087c0 */ u64 rf_dam_rdsb_fifo_rtl_top; 7525#define VXGE_HAL_RF_DAM_RDSB_FIFO_RTL_TOP_CMG3_NMB_IO_REPAIR_STATUS(val)\ 7526 vBIT(val, 0, 2) 7527#define VXGE_HAL_RF_DAM_RDSB_FIFO_RTL_TOP_CMG3_NMB_IO_ALL_FUSE(val)\ 7528 vBIT(val, 2, 7) 7529/* 0x087c8 */ u64 rf_dam_wrsb_fifo_rtl_top; 7530#define VXGE_HAL_RF_DAM_WRSB_FIFO_RTL_TOP_CMG3_NMB_IO_REPAIR_STATUS(val)\ 7531 vBIT(val, 0, 2) 7532#define VXGE_HAL_RF_DAM_WRSB_FIFO_RTL_TOP_CMG3_NMB_IO_ALL_FUSE(val)\ 7533 vBIT(val, 2, 7) 7534/* 0x087d0 */ u64 rr_dbf_ladd_0_dbl_rtl_top; 7535#define VXGE_HAL_RR_DBF_LADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ 7536 vBIT(val, 0, 2) 7537#define VXGE_HAL_RR_DBF_LADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_FUSE(val)\ 7538 vBIT(val, 2, 6) 7539#define VXGE_HAL_RR_DBF_LADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_ADD_FUSE(val)\ 7540 vBIT(val, 8, 5) 7541#define VXGE_HAL_RR_DBF_LADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_FUSE(val)\ 7542 vBIT(val, 13, 6) 7543#define VXGE_HAL_RR_DBF_LADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_ADD_FUSE(val)\ 7544 vBIT(val, 19, 5) 7545/* 0x087d8 */ u64 rr_dbf_ladd_1_dbl_rtl_top; 7546#define VXGE_HAL_RR_DBF_LADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ 7547 vBIT(val, 0, 2) 7548#define VXGE_HAL_RR_DBF_LADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_FUSE(val)\ 7549 vBIT(val, 2, 6) 7550#define VXGE_HAL_RR_DBF_LADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_ADD_FUSE(val)\ 7551 vBIT(val, 8, 5) 7552#define VXGE_HAL_RR_DBF_LADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_FUSE(val)\ 7553 vBIT(val, 13, 6) 7554#define VXGE_HAL_RR_DBF_LADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_ADD_FUSE(val)\ 7555 vBIT(val, 19, 5) 7556/* 0x087e0 */ u64 rr_dbf_ladd_2_dbl_rtl_top; 7557#define VXGE_HAL_RR_DBF_LADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ 7558 vBIT(val, 0, 2) 7559#define VXGE_HAL_RR_DBF_LADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_FUSE(val)\ 7560 vBIT(val, 2, 6) 7561#define VXGE_HAL_RR_DBF_LADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_ADD_FUSE(val)\ 7562 vBIT(val, 8, 5) 7563#define VXGE_HAL_RR_DBF_LADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_FUSE(val)\ 7564 vBIT(val, 13, 6) 7565#define VXGE_HAL_RR_DBF_LADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_ADD_FUSE(val)\ 7566 vBIT(val, 19, 5) 7567/* 0x087e8 */ u64 rr_dbf_hadd_0_dbl_rtl_top; 7568#define VXGE_HAL_RR_DBF_HADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ 7569 vBIT(val, 0, 2) 7570#define VXGE_HAL_RR_DBF_HADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_FUSE(val)\ 7571 vBIT(val, 2, 6) 7572#define VXGE_HAL_RR_DBF_HADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_ADD_FUSE(val)\ 7573 vBIT(val, 8, 5) 7574#define VXGE_HAL_RR_DBF_HADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_FUSE(val)\ 7575 vBIT(val, 13, 6) 7576#define VXGE_HAL_RR_DBF_HADD_0_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_ADD_FUSE(val)\ 7577 vBIT(val, 19, 5) 7578/* 0x087f0 */ u64 rr_dbf_hadd_1_dbl_rtl_top; 7579#define VXGE_HAL_RR_DBF_HADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ 7580 vBIT(val, 0, 2) 7581#define VXGE_HAL_RR_DBF_HADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_FUSE(val)\ 7582 vBIT(val, 2, 6) 7583#define VXGE_HAL_RR_DBF_HADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_ADD_FUSE(val)\ 7584 vBIT(val, 8, 5) 7585#define VXGE_HAL_RR_DBF_HADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_FUSE(val)\ 7586 vBIT(val, 13, 6) 7587#define VXGE_HAL_RR_DBF_HADD_1_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_ADD_FUSE(val)\ 7588 vBIT(val, 19, 5) 7589/* 0x087f8 */ u64 rr_dbf_hadd_2_dbl_rtl_top; 7590#define VXGE_HAL_RR_DBF_HADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ 7591 vBIT(val, 0, 2) 7592#define VXGE_HAL_RR_DBF_HADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_FUSE(val)\ 7593 vBIT(val, 2, 6) 7594#define VXGE_HAL_RR_DBF_HADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK1_ADD_FUSE(val)\ 7595 vBIT(val, 8, 5) 7596#define VXGE_HAL_RR_DBF_HADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_FUSE(val)\ 7597 vBIT(val, 13, 6) 7598#define VXGE_HAL_RR_DBF_HADD_2_DBL_RTL_TOP_DRBELL_NMB_IO_BANK0_ADD_FUSE(val)\ 7599 vBIT(val, 19, 5) 7600/* 0x08800 */ u64 rf_usdc_0_fifo_rtl_top; 7601#define VXGE_HAL_RF_USDC_0_FIFO_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ 7602 vBIT(val, 0, 2) 7603#define VXGE_HAL_RF_USDC_0_FIFO_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\ 7604 vBIT(val, 2, 7) 7605/* 0x08808 */ u64 rf_usdc_1_fifo_rtl_top; 7606#define VXGE_HAL_RF_USDC_1_FIFO_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ 7607 vBIT(val, 0, 2) 7608#define VXGE_HAL_RF_USDC_1_FIFO_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\ 7609 vBIT(val, 2, 7) 7610/* 0x08810 */ u64 rf_usdc_0_wa_rtl_top; 7611#define VXGE_HAL_RF_USDC_0_WA_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ 7612 vBIT(val, 0, 2) 7613#define VXGE_HAL_RF_USDC_0_WA_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\ 7614 vBIT(val, 2, 7) 7615/* 0x08818 */ u64 rf_usdc_1_wa_rtl_top; 7616#define VXGE_HAL_RF_USDC_1_WA_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ 7617 vBIT(val, 0, 2) 7618#define VXGE_HAL_RF_USDC_1_WA_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\ 7619 vBIT(val, 2, 7) 7620/* 0x08820 */ u64 rf_usdc_0_sa_rtl_top; 7621#define VXGE_HAL_RF_USDC_0_SA_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ 7622 vBIT(val, 0, 2) 7623#define VXGE_HAL_RF_USDC_0_SA_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\ 7624 vBIT(val, 2, 7) 7625/* 0x08828 */ u64 rf_usdc_1_sa_rtl_top; 7626#define VXGE_HAL_RF_USDC_1_SA_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ 7627 vBIT(val, 0, 2) 7628#define VXGE_HAL_RF_USDC_1_SA_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\ 7629 vBIT(val, 2, 7) 7630/* 0x08830 */ u64 rf_usdc_0_ca_rtl_top; 7631#define VXGE_HAL_RF_USDC_0_CA_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ 7632 vBIT(val, 0, 2) 7633#define VXGE_HAL_RF_USDC_0_CA_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\ 7634 vBIT(val, 2, 7) 7635/* 0x08838 */ u64 rf_usdc_1_ca_rtl_top; 7636#define VXGE_HAL_RF_USDC_1_CA_RTL_TOP_DRBELL_NMB_IO_REPAIR_STATUS(val)\ 7637 vBIT(val, 0, 2) 7638#define VXGE_HAL_RF_USDC_1_CA_RTL_TOP_DRBELL_NMB_IO_ALL_FUSE(val)\ 7639 vBIT(val, 2, 7) 7640/* 0x08840 */ u64 rf_g3if_fb_rd1; 7641#define VXGE_HAL_RF_G3IF_FB_RD1_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7642 vBIT(val, 0, 2) 7643#define VXGE_HAL_RF_G3IF_FB_RD1_FBIF_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 8) 7644/* 0x08848 */ u64 rf_g3if_fb_rd2; 7645#define VXGE_HAL_RF_G3IF_FB_RD2_FBIF_NMB_IO_REPAIR_STATUS(val) vBIT(val, 0, 2) 7646#define VXGE_HAL_RF_G3IF_FB_RD2_FBIF_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 8) 7647/* 0x08850 */ u64 rf_g3if_fb_ctrl_rtl_top1; 7648#define VXGE_HAL_RF_G3IF_FB_CTRL_RTL_TOP1_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7649 vBIT(val, 0, 2) 7650#define VXGE_HAL_RF_G3IF_FB_CTRL_RTL_TOP1_FBIF_NMB_IO_ALL_FUSE(val)\ 7651 vBIT(val, 2, 8) 7652/* 0x08858 */ u64 rf_g3if_fb_ctrl_rtl_top; 7653#define VXGE_HAL_RF_G3IF_FB_CTRL_RTL_TOP_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7654 vBIT(val, 0, 2) 7655#define VXGE_HAL_RF_G3IF_FB_CTRL_RTL_TOP_FBIF_NMB_IO_ALL_FUSE(val)\ 7656 vBIT(val, 2, 8) 7657/* 0x08860 */ u64 rr_rocrc_frmbuf_rtl_top_0; 7658#define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_0_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7659 vBIT(val, 0, 2) 7660#define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_0_FBIF_NMB_IO_BANK1_FUSE(val)\ 7661 vBIT(val, 2, 8) 7662#define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_0_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\ 7663 vBIT(val, 10, 2) 7664#define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_0_FBIF_NMB_IO_BANK0_FUSE(val)\ 7665 vBIT(val, 12, 8) 7666#define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_0_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\ 7667 vBIT(val, 20, 2) 7668/* 0x08868 */ u64 rr_rocrc_frmbuf_rtl_top_1; 7669#define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_1_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7670 vBIT(val, 0, 2) 7671#define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_1_FBIF_NMB_IO_BANK1_FUSE(val)\ 7672 vBIT(val, 2, 8) 7673#define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_1_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\ 7674 vBIT(val, 10, 2) 7675#define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_1_FBIF_NMB_IO_BANK0_FUSE(val)\ 7676 vBIT(val, 12, 8) 7677#define VXGE_HAL_RR_ROCRC_FRMBUF_RTL_TOP_1_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\ 7678 vBIT(val, 20, 2) 7679/* 0x08870 */ u64 rr_fau_xfmd_ins_rtl_top; 7680#define VXGE_HAL_RR_FAU_XFMD_INS_RTL_TOP_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7681 vBIT(val, 0, 2) 7682#define VXGE_HAL_RR_FAU_XFMD_INS_RTL_TOP_FBIF_NMB_IO_BANK1_FUSE(val)\ 7683 vBIT(val, 2, 8) 7684#define VXGE_HAL_RR_FAU_XFMD_INS_RTL_TOP_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\ 7685 vBIT(val, 10, 2) 7686#define VXGE_HAL_RR_FAU_XFMD_INS_RTL_TOP_FBIF_NMB_IO_BANK0_FUSE(val)\ 7687 vBIT(val, 12, 8) 7688#define VXGE_HAL_RR_FAU_XFMD_INS_RTL_TOP_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\ 7689 vBIT(val, 20, 2) 7690/* 0x08878 */ u64 rf_fbmc_xfmd_rtl_top_a1; 7691#define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_A1_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7692 vBIT(val, 0, 2) 7693#define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_A1_FBIF_NMB_IO_ALL_FUSE(val)\ 7694 vBIT(val, 2, 7) 7695/* 0x08880 */ u64 rf_fbmc_xfmd_rtl_top_a2; 7696#define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_A2_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7697 vBIT(val, 0, 2) 7698#define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_A2_FBIF_NMB_IO_ALL_FUSE(val)\ 7699 vBIT(val, 2, 7) 7700/* 0x08888 */ u64 rf_fbmc_xfmd_rtl_top_a3; 7701#define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_A3_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7702 vBIT(val, 0, 2) 7703#define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_A3_FBIF_NMB_IO_ALL_FUSE(val)\ 7704 vBIT(val, 2, 7) 7705/* 0x08890 */ u64 rf_fbmc_xfmd_rtl_top_b1; 7706#define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_B1_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7707 vBIT(val, 0, 2) 7708#define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_B1_FBIF_NMB_IO_ALL_FUSE(val)\ 7709 vBIT(val, 2, 7) 7710/* 0x08898 */ u64 rf_fbmc_xfmd_rtl_top_b2; 7711#define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_B2_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7712 vBIT(val, 0, 2) 7713#define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_B2_FBIF_NMB_IO_ALL_FUSE(val)\ 7714 vBIT(val, 2, 7) 7715/* 0x088a0 */ u64 rf_fbmc_xfmd_rtl_top_b3; 7716#define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_B3_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7717 vBIT(val, 0, 2) 7718#define VXGE_HAL_RF_FBMC_XFMD_RTL_TOP_B3_FBIF_NMB_IO_ALL_FUSE(val)\ 7719 vBIT(val, 2, 7) 7720/* 0x088a8 */ u64 rr_fau_mac2f_w_h_rtl_top_port0; 7721#define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT0_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7722 vBIT(val, 0, 2) 7723#define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK1_FUSE(val)\ 7724 vBIT(val, 2, 8) 7725#define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\ 7726 vBIT(val, 10, 2) 7727#define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK0_FUSE(val)\ 7728 vBIT(val, 12, 8) 7729#define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\ 7730 vBIT(val, 20, 2) 7731/* 0x088b0 */ u64 rr_fau_mac2f_w_h_rtl_top_port1; 7732#define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT1_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7733 vBIT(val, 0, 2) 7734#define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK1_FUSE(val)\ 7735 vBIT(val, 2, 8) 7736#define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\ 7737 vBIT(val, 10, 2) 7738#define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK0_FUSE(val)\ 7739 vBIT(val, 12, 8) 7740#define VXGE_HAL_RR_FAU_MAC2F_W_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\ 7741 vBIT(val, 20, 2) 7742/* 0x088b8 */ u64 rr_fau_mac2f_n_h_rtl_top_port0; 7743#define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT0_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7744 vBIT(val, 0, 2) 7745#define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK1_FUSE(val)\ 7746 vBIT(val, 2, 7) 7747#define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\ 7748 vBIT(val, 9, 3) 7749#define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK0_FUSE(val)\ 7750 vBIT(val, 12, 7) 7751#define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT0_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\ 7752 vBIT(val, 19, 3) 7753/* 0x088c0 */ u64 rr_fau_mac2f_n_h_rtl_top_port1; 7754#define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT1_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7755 vBIT(val, 0, 2) 7756#define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK1_FUSE(val)\ 7757 vBIT(val, 2, 7) 7758#define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\ 7759 vBIT(val, 9, 3) 7760#define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK0_FUSE(val)\ 7761 vBIT(val, 12, 7) 7762#define VXGE_HAL_RR_FAU_MAC2F_N_H_RTL_TOP_PORT1_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\ 7763 vBIT(val, 19, 3) 7764/* 0x088c8 */ u64 rr_fau_mac2f_w_l_rtl_top_port2; 7765#define VXGE_HAL_RR_FAU_MAC2F_W_L_RTL_TOP_PORT2_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7766 vBIT(val, 0, 2) 7767#define VXGE_HAL_RR_FAU_MAC2F_W_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK1_FUSE(val)\ 7768 vBIT(val, 2, 8) 7769#define VXGE_HAL_RR_FAU_MAC2F_W_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\ 7770 vBIT(val, 10, 2) 7771#define VXGE_HAL_RR_FAU_MAC2F_W_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK0_FUSE(val)\ 7772 vBIT(val, 12, 8) 7773#define VXGE_HAL_RR_FAU_MAC2F_W_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\ 7774 vBIT(val, 20, 2) 7775/* 0x088d0 */ u64 rr_fau_mac2f_n_l_rtl_top_port2; 7776#define VXGE_HAL_RR_FAU_MAC2F_N_L_RTL_TOP_PORT2_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7777 vBIT(val, 0, 2) 7778#define VXGE_HAL_RR_FAU_MAC2F_N_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK1_FUSE(val)\ 7779 vBIT(val, 2, 7) 7780#define VXGE_HAL_RR_FAU_MAC2F_N_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK1_ADD_FUSE(val)\ 7781 vBIT(val, 9, 3) 7782#define VXGE_HAL_RR_FAU_MAC2F_N_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK0_FUSE(val)\ 7783 vBIT(val, 12, 7) 7784#define VXGE_HAL_RR_FAU_MAC2F_N_L_RTL_TOP_PORT2_FBIF_NMB_IO_BANK0_ADD_FUSE(val)\ 7785 vBIT(val, 19, 3) 7786/* 0x088d8 */ u64 rf_orp_frm_fifo_rtl_top_0; 7787#define VXGE_HAL_RF_ORP_FRM_FIFO_RTL_TOP_0_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7788 vBIT(val, 0, 2) 7789#define VXGE_HAL_RF_ORP_FRM_FIFO_RTL_TOP_0_FBIF_NMB_IO_ALL_FUSE(val)\ 7790 vBIT(val, 2, 7) 7791/* 0x088e0 */ u64 rf_orp_frm_fifo_rtl_top_1; 7792#define VXGE_HAL_RF_ORP_FRM_FIFO_RTL_TOP_1_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7793 vBIT(val, 0, 2) 7794#define VXGE_HAL_RF_ORP_FRM_FIFO_RTL_TOP_1_FBIF_NMB_IO_ALL_FUSE(val)\ 7795 vBIT(val, 2, 7) 7796/* 0x088e8 */ u64 rf_tpa_da_lkp_rtl_top_0_0; 7797#define VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_0_0_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7798 vBIT(val, 0, 2) 7799#define VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_0_0_FBIF_NMB_IO_ALL_FUSE(val)\ 7800 vBIT(val, 2, 7) 7801/* 0x088f0 */ u64 rf_tpa_da_lkp_rtl_top_1_0; 7802#define VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_1_0_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7803 vBIT(val, 0, 2) 7804#define VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_1_0_FBIF_NMB_IO_ALL_FUSE(val)\ 7805 vBIT(val, 2, 7) 7806/* 0x088f8 */ u64 rf_tpa_da_lkp_rtl_top_0_1; 7807#define VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_0_1_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7808 vBIT(val, 0, 2) 7809#define VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_0_1_FBIF_NMB_IO_ALL_FUSE(val)\ 7810 vBIT(val, 2, 7) 7811/* 0x08900 */ u64 rf_tpa_da_lkp_rtl_top_1_1; 7812#define VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_1_1_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7813 vBIT(val, 0, 2) 7814#define VXGE_HAL_RF_TPA_DA_LKP_RTL_TOP_1_1_FBIF_NMB_IO_ALL_FUSE(val)\ 7815 vBIT(val, 2, 7) 7816/* 0x08908 */ u64 rf_tmac_tpa2mac_rtl_top_0_0; 7817#define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_0_0_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7818 vBIT(val, 0, 2) 7819#define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_0_0_FBIF_NMB_IO_ALL_FUSE(val)\ 7820 vBIT(val, 2, 6) 7821/* 0x08910 */ u64 rf_tmac_tpa2mac_rtl_top_1_0; 7822#define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_1_0_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7823 vBIT(val, 0, 2) 7824#define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_1_0_FBIF_NMB_IO_ALL_FUSE(val)\ 7825 vBIT(val, 2, 6) 7826/* 0x08918 */ u64 rf_tmac_tpa2mac_rtl_top_2_0; 7827#define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_2_0_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7828 vBIT(val, 0, 2) 7829#define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_2_0_FBIF_NMB_IO_ALL_FUSE(val)\ 7830 vBIT(val, 2, 6) 7831/* 0x08920 */ u64 rf_tmac_tpa2mac_rtl_top_0_1; 7832#define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_0_1_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7833 vBIT(val, 0, 2) 7834#define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_0_1_FBIF_NMB_IO_ALL_FUSE(val)\ 7835 vBIT(val, 2, 6) 7836/* 0x08928 */ u64 rf_tmac_tpa2mac_rtl_top_1_1; 7837#define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_1_1_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7838 vBIT(val, 0, 2) 7839#define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_1_1_FBIF_NMB_IO_ALL_FUSE(val)\ 7840 vBIT(val, 2, 6) 7841/* 0x08930 */ u64 rf_tmac_tpa2mac_rtl_top_2_1; 7842#define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_2_1_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7843 vBIT(val, 0, 2) 7844#define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_2_1_FBIF_NMB_IO_ALL_FUSE(val)\ 7845 vBIT(val, 2, 6) 7846/* 0x08938 */ u64 rf_tmac_tpa2mac_rtl_top_0_2; 7847#define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_0_2_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7848 vBIT(val, 0, 2) 7849#define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_0_2_FBIF_NMB_IO_ALL_FUSE(val)\ 7850 vBIT(val, 2, 6) 7851/* 0x08940 */ u64 rf_tmac_tpa2mac_rtl_top_1_2; 7852#define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_1_2_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7853 vBIT(val, 0, 2) 7854#define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_1_2_FBIF_NMB_IO_ALL_FUSE(val)\ 7855 vBIT(val, 2, 6) 7856/* 0x08948 */ u64 rf_tmac_tpa2mac_rtl_top_2_2; 7857#define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_2_2_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7858 vBIT(val, 0, 2) 7859#define VXGE_HAL_RF_TMAC_TPA2MAC_RTL_TOP_2_2_FBIF_NMB_IO_ALL_FUSE(val)\ 7860 vBIT(val, 2, 6) 7861/* 0x08950 */ u64 rf_tmac_tpa2m_da_rtl_top; 7862#define VXGE_HAL_RF_TMAC_TPA2M_DA_RTL_TOP_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7863 vBIT(val, 0, 2) 7864#define VXGE_HAL_RF_TMAC_TPA2M_DA_RTL_TOP_FBIF_NMB_IO_ALL_FUSE(val)\ 7865 vBIT(val, 2, 6) 7866/* 0x08958 */ u64 rf_tmac_tpa2m_sb_rtl_top; 7867#define VXGE_HAL_RF_TMAC_TPA2M_SB_RTL_TOP_FBIF_NMB_IO_REPAIR_STATUS(val)\ 7868 vBIT(val, 0, 2) 7869#define VXGE_HAL_RF_TMAC_TPA2M_SB_RTL_TOP_FBIF_NMB_IO_ALL_FUSE(val)\ 7870 vBIT(val, 2, 8) 7871/* 0x08960 */ u64 rf_xt_trace_rtl_top_mp; 7872#define VXGE_HAL_RF_XT_TRACE_RTL_TOP_MP_MSG_NMB_IO_REPAIR_STATUS(val)\ 7873 vBIT(val, 0, 2) 7874#define VXGE_HAL_RF_XT_TRACE_RTL_TOP_MP_MSG_NMB_IO_ALL_FUSE(val)\ 7875 vBIT(val, 2, 8) 7876/* 0x08968 */ u64 rf_mp_xt_dtag_rtl_top; 7877#define VXGE_HAL_RF_MP_XT_DTAG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\ 7878 vBIT(val, 0, 2) 7879#define VXGE_HAL_RF_MP_XT_DTAG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6) 7880/* 0x08970 */ u64 rf_mp_xt_icache_rtl_top_0_0; 7881#define VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_0_0_MSG_NMB_IO_REPAIR_STATUS(val)\ 7882 vBIT(val, 0, 2) 7883#define VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_0_0_MSG_NMB_IO_ALL_FUSE(val)\ 7884 vBIT(val, 2, 7) 7885/* 0x08978 */ u64 rf_mp_xt_icache_rtl_top_1_0; 7886#define VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_1_0_MSG_NMB_IO_REPAIR_STATUS(val)\ 7887 vBIT(val, 0, 2) 7888#define VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_1_0_MSG_NMB_IO_ALL_FUSE(val)\ 7889 vBIT(val, 2, 7) 7890/* 0x08980 */ u64 rf_mp_xt_icache_rtl_top_0_1; 7891#define VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_0_1_MSG_NMB_IO_REPAIR_STATUS(val)\ 7892 vBIT(val, 0, 2) 7893#define VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_0_1_MSG_NMB_IO_ALL_FUSE(val)\ 7894 vBIT(val, 2, 7) 7895/* 0x08988 */ u64 rf_mp_xt_icache_rtl_top_1_1; 7896#define VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_1_1_MSG_NMB_IO_REPAIR_STATUS(val)\ 7897 vBIT(val, 0, 2) 7898#define VXGE_HAL_RF_MP_XT_ICACHE_RTL_TOP_1_1_MSG_NMB_IO_ALL_FUSE(val)\ 7899 vBIT(val, 2, 7) 7900/* 0x08990 */ u64 rf_mp_xt_itag_rtl_top; 7901#define VXGE_HAL_RF_MP_XT_ITAG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\ 7902 vBIT(val, 0, 2) 7903#define VXGE_HAL_RF_MP_XT_ITAG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6) 7904/* 0x08998 */ u64 rf_mp_xt_dcache_rtl_top_0_0; 7905#define VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_0_0_MSG_NMB_IO_REPAIR_STATUS(val)\ 7906 vBIT(val, 0, 2) 7907#define VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_0_0_MSG_NMB_IO_ALL_FUSE(val)\ 7908 vBIT(val, 2, 7) 7909/* 0x089a0 */ u64 rf_mp_xt_dcache_rtl_top_1_0; 7910#define VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_1_0_MSG_NMB_IO_REPAIR_STATUS(val)\ 7911 vBIT(val, 0, 2) 7912#define VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_1_0_MSG_NMB_IO_ALL_FUSE(val)\ 7913 vBIT(val, 2, 7) 7914/* 0x089a8 */ u64 rf_mp_xt_dcache_rtl_top_0_1; 7915#define VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_0_1_MSG_NMB_IO_REPAIR_STATUS(val)\ 7916 vBIT(val, 0, 2) 7917#define VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_0_1_MSG_NMB_IO_ALL_FUSE(val)\ 7918 vBIT(val, 2, 7) 7919/* 0x089b0 */ u64 rf_mp_xt_dcache_rtl_top_1_1; 7920#define VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_1_1_MSG_NMB_IO_REPAIR_STATUS(val)\ 7921 vBIT(val, 0, 2) 7922#define VXGE_HAL_RF_MP_XT_DCACHE_RTL_TOP_1_1_MSG_NMB_IO_ALL_FUSE(val)\ 7923 vBIT(val, 2, 7) 7924/* 0x089b8 */ u64 rf_msg_bwr_pf_rtl_top_0; 7925#define VXGE_HAL_RF_MSG_BWR_PF_RTL_TOP_0_MSG_NMB_IO_REPAIR_STATUS(val)\ 7926 vBIT(val, 0, 2) 7927#define VXGE_HAL_RF_MSG_BWR_PF_RTL_TOP_0_MSG_NMB_IO_ALL_FUSE(val)\ 7928 vBIT(val, 2, 8) 7929/* 0x089c0 */ u64 rf_msg_bwr_pf_rtl_top_1; 7930#define VXGE_HAL_RF_MSG_BWR_PF_RTL_TOP_1_MSG_NMB_IO_REPAIR_STATUS(val)\ 7931 vBIT(val, 0, 2) 7932#define VXGE_HAL_RF_MSG_BWR_PF_RTL_TOP_1_MSG_NMB_IO_ALL_FUSE(val)\ 7933 vBIT(val, 2, 8) 7934/* 0x089c8 */ u64 rf_msg_umq_rtl_top_0; 7935#define VXGE_HAL_RF_MSG_UMQ_RTL_TOP_0_MSG_NMB_IO_REPAIR_STATUS(val)\ 7936 vBIT(val, 0, 2) 7937#define VXGE_HAL_RF_MSG_UMQ_RTL_TOP_0_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 7) 7938/* 0x089d0 */ u64 rf_msg_umq_rtl_top_1; 7939#define VXGE_HAL_RF_MSG_UMQ_RTL_TOP_1_MSG_NMB_IO_REPAIR_STATUS(val)\ 7940 vBIT(val, 0, 2) 7941#define VXGE_HAL_RF_MSG_UMQ_RTL_TOP_1_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 7) 7942/* 0x089d8 */ u64 rf_msg_dmq_rtl_top_0; 7943#define VXGE_HAL_RF_MSG_DMQ_RTL_TOP_0_MSG_NMB_IO_REPAIR_STATUS(val)\ 7944 vBIT(val, 0, 2) 7945#define VXGE_HAL_RF_MSG_DMQ_RTL_TOP_0_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6) 7946/* 0x089e0 */ u64 rf_msg_dmq_rtl_top_1; 7947#define VXGE_HAL_RF_MSG_DMQ_RTL_TOP_1_MSG_NMB_IO_REPAIR_STATUS(val)\ 7948 vBIT(val, 0, 2) 7949#define VXGE_HAL_RF_MSG_DMQ_RTL_TOP_1_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6) 7950/* 0x089e8 */ u64 rf_msg_dmq_rtl_top_2; 7951#define VXGE_HAL_RF_MSG_DMQ_RTL_TOP_2_MSG_NMB_IO_REPAIR_STATUS(val)\ 7952 vBIT(val, 0, 2) 7953#define VXGE_HAL_RF_MSG_DMQ_RTL_TOP_2_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6) 7954/* 0x089f0 */ u64 rf_msg_dma_resp_rtl_top_0; 7955#define VXGE_HAL_RF_MSG_DMA_RESP_RTL_TOP_0_MSG_NMB_IO_REPAIR_STATUS(val)\ 7956 vBIT(val, 0, 2) 7957#define VXGE_HAL_RF_MSG_DMA_RESP_RTL_TOP_0_MSG_NMB_IO_ALL_FUSE(val)\ 7958 vBIT(val, 2, 6) 7959/* 0x089f8 */ u64 rf_msg_dma_resp_rtl_top_1; 7960#define VXGE_HAL_RF_MSG_DMA_RESP_RTL_TOP_1_MSG_NMB_IO_REPAIR_STATUS(val)\ 7961 vBIT(val, 0, 2) 7962#define VXGE_HAL_RF_MSG_DMA_RESP_RTL_TOP_1_MSG_NMB_IO_ALL_FUSE(val)\ 7963 vBIT(val, 2, 6) 7964/* 0x08a00 */ u64 rf_msg_dma_resp_rtl_top_2; 7965#define VXGE_HAL_RF_MSG_DMA_RESP_RTL_TOP_2_MSG_NMB_IO_REPAIR_STATUS(val)\ 7966 vBIT(val, 0, 2) 7967#define VXGE_HAL_RF_MSG_DMA_RESP_RTL_TOP_2_MSG_NMB_IO_ALL_FUSE(val)\ 7968 vBIT(val, 2, 6) 7969/* 0x08a08 */ u64 rf_msg_cmg2msg_rtl_top_0_0; 7970#define VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_0_0_MSG_NMB_IO_REPAIR_STATUS(val)\ 7971 vBIT(val, 0, 2) 7972#define VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_0_0_MSG_NMB_IO_ALL_FUSE(val)\ 7973 vBIT(val, 2, 6) 7974/* 0x08a10 */ u64 rf_msg_cmg2msg_rtl_top_1_0; 7975#define VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_1_0_MSG_NMB_IO_REPAIR_STATUS(val)\ 7976 vBIT(val, 0, 2) 7977#define VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_1_0_MSG_NMB_IO_ALL_FUSE(val)\ 7978 vBIT(val, 2, 6) 7979/* 0x08a18 */ u64 rf_msg_cmg2msg_rtl_top_0_1; 7980#define VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_0_1_MSG_NMB_IO_REPAIR_STATUS(val)\ 7981 vBIT(val, 0, 2) 7982#define VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_0_1_MSG_NMB_IO_ALL_FUSE(val)\ 7983 vBIT(val, 2, 6) 7984/* 0x08a20 */ u64 rf_msg_cmg2msg_rtl_top_1_1; 7985#define VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_1_1_MSG_NMB_IO_REPAIR_STATUS(val)\ 7986 vBIT(val, 0, 2) 7987#define VXGE_HAL_RF_MSG_CMG2MSG_RTL_TOP_1_1_MSG_NMB_IO_ALL_FUSE(val)\ 7988 vBIT(val, 2, 6) 7989/* 0x08a28 */ u64 rf_msg_txpe2msg_rtl_top; 7990#define VXGE_HAL_RF_MSG_TXPE2MSG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\ 7991 vBIT(val, 0, 2) 7992#define VXGE_HAL_RF_MSG_TXPE2MSG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val)\ 7993 vBIT(val, 2, 7) 7994/* 0x08a30 */ u64 rf_msg_rxpe2msg_rtl_top; 7995#define VXGE_HAL_RF_MSG_RXPE2MSG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\ 7996 vBIT(val, 0, 2) 7997#define VXGE_HAL_RF_MSG_RXPE2MSG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val)\ 7998 vBIT(val, 2, 7) 7999/* 0x08a38 */ u64 rf_msg_rpe2msg_rtl_top; 8000#define VXGE_HAL_RF_MSG_RPE2MSG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\ 8001 vBIT(val, 0, 2) 8002#define VXGE_HAL_RF_MSG_RPE2MSG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val)\ 8003 vBIT(val, 2, 7) 8004/* 0x08a40 */ u64 rr_tim_bmap_rtl_top; 8005#define VXGE_HAL_RR_TIM_BMAP_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\ 8006 vBIT(val, 0, 2) 8007#define VXGE_HAL_RR_TIM_BMAP_RTL_TOP_MSG_NMB_IO_BANK1_FUSE(val) vBIT(val, 2, 8) 8008#define VXGE_HAL_RR_TIM_BMAP_RTL_TOP_MSG_NMB_IO_BANK1_ADD_FUSE(val)\ 8009 vBIT(val, 10, 2) 8010#define VXGE_HAL_RR_TIM_BMAP_RTL_TOP_MSG_NMB_IO_BANK0_FUSE(val) vBIT(val, 12, 8) 8011#define VXGE_HAL_RR_TIM_BMAP_RTL_TOP_MSG_NMB_IO_BANK0_ADD_FUSE(val)\ 8012 vBIT(val, 20, 2) 8013/* 0x08a48 */ u64 rf_tim_vbls_rtl_top; 8014#define VXGE_HAL_RF_TIM_VBLS_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\ 8015 vBIT(val, 0, 2) 8016#define VXGE_HAL_RF_TIM_VBLS_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 8) 8017/* 0x08a50 */ u64 rf_tim_bmap_msg_rtl_top_0_0; 8018#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_0_MSG_NMB_IO_REPAIR_STATUS(val)\ 8019 vBIT(val, 0, 2) 8020#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_0_MSG_NMB_IO_ALL_FUSE(val)\ 8021 vBIT(val, 2, 6) 8022/* 0x08a58 */ u64 rf_tim_bmap_msg_rtl_top_1_0; 8023#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_0_MSG_NMB_IO_REPAIR_STATUS(val)\ 8024 vBIT(val, 0, 2) 8025#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_0_MSG_NMB_IO_ALL_FUSE(val)\ 8026 vBIT(val, 2, 6) 8027/* 0x08a60 */ u64 rf_tim_bmap_msg_rtl_top_2_0; 8028#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_0_MSG_NMB_IO_REPAIR_STATUS(val)\ 8029 vBIT(val, 0, 2) 8030#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_0_MSG_NMB_IO_ALL_FUSE(val)\ 8031 vBIT(val, 2, 6) 8032/* 0x08a68 */ u64 rf_tim_bmap_msg_rtl_top_0_1; 8033#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_1_MSG_NMB_IO_REPAIR_STATUS(val)\ 8034 vBIT(val, 0, 2) 8035#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_1_MSG_NMB_IO_ALL_FUSE(val)\ 8036 vBIT(val, 2, 6) 8037/* 0x08a70 */ u64 rf_tim_bmap_msg_rtl_top_1_1; 8038#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_1_MSG_NMB_IO_REPAIR_STATUS(val)\ 8039 vBIT(val, 0, 2) 8040#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_1_MSG_NMB_IO_ALL_FUSE(val)\ 8041 vBIT(val, 2, 6) 8042/* 0x08a78 */ u64 rf_tim_bmap_msg_rtl_top_2_1; 8043#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_1_MSG_NMB_IO_REPAIR_STATUS(val)\ 8044 vBIT(val, 0, 2) 8045#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_1_MSG_NMB_IO_ALL_FUSE(val)\ 8046 vBIT(val, 2, 6) 8047/* 0x08a80 */ u64 rf_tim_bmap_msg_rtl_top_0_2; 8048#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_2_MSG_NMB_IO_REPAIR_STATUS(val)\ 8049 vBIT(val, 0, 2) 8050#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_2_MSG_NMB_IO_ALL_FUSE(val)\ 8051 vBIT(val, 2, 6) 8052/* 0x08a88 */ u64 rf_tim_bmap_msg_rtl_top_1_2; 8053#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_2_MSG_NMB_IO_REPAIR_STATUS(val)\ 8054 vBIT(val, 0, 2) 8055#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_2_MSG_NMB_IO_ALL_FUSE(val)\ 8056 vBIT(val, 2, 6) 8057/* 0x08a90 */ u64 rf_tim_bmap_msg_rtl_top_2_2; 8058#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_2_MSG_NMB_IO_REPAIR_STATUS(val)\ 8059 vBIT(val, 0, 2) 8060#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_2_MSG_NMB_IO_ALL_FUSE(val)\ 8061 vBIT(val, 2, 6) 8062/* 0x08a98 */ u64 rf_tim_bmap_msg_rtl_top_0_3; 8063#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_3_MSG_NMB_IO_REPAIR_STATUS(val)\ 8064 vBIT(val, 0, 2) 8065#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_3_MSG_NMB_IO_ALL_FUSE(val)\ 8066 vBIT(val, 2, 6) 8067/* 0x08aa0 */ u64 rf_tim_bmap_msg_rtl_top_1_3; 8068#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_3_MSG_NMB_IO_REPAIR_STATUS(val)\ 8069 vBIT(val, 0, 2) 8070#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_3_MSG_NMB_IO_ALL_FUSE(val)\ 8071 vBIT(val, 2, 6) 8072/* 0x08aa8 */ u64 rf_tim_bmap_msg_rtl_top_2_3; 8073#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_3_MSG_NMB_IO_REPAIR_STATUS(val)\ 8074 vBIT(val, 0, 2) 8075#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_3_MSG_NMB_IO_ALL_FUSE(val)\ 8076 vBIT(val, 2, 6) 8077/* 0x08ab0 */ u64 rf_tim_bmap_msg_rtl_top_0_4; 8078#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_4_MSG_NMB_IO_REPAIR_STATUS(val)\ 8079 vBIT(val, 0, 2) 8080#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_0_4_MSG_NMB_IO_ALL_FUSE(val)\ 8081 vBIT(val, 2, 6) 8082/* 0x08ab8 */ u64 rf_tim_bmap_msg_rtl_top_1_4; 8083#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_4_MSG_NMB_IO_REPAIR_STATUS(val)\ 8084 vBIT(val, 0, 2) 8085#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_1_4_MSG_NMB_IO_ALL_FUSE(val)\ 8086 vBIT(val, 2, 6) 8087/* 0x08ac0 */ u64 rf_tim_bmap_msg_rtl_top_2_4; 8088#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_4_MSG_NMB_IO_REPAIR_STATUS(val)\ 8089 vBIT(val, 0, 2) 8090#define VXGE_HAL_RF_TIM_BMAP_MSG_RTL_TOP_2_4_MSG_NMB_IO_ALL_FUSE(val)\ 8091 vBIT(val, 2, 6) 8092/* 0x08ac8 */ u64 rf_xt_trace_rtl_top_up; 8093#define VXGE_HAL_RF_XT_TRACE_RTL_TOP_UP_MSG_NMB_IO_REPAIR_STATUS(val)\ 8094 vBIT(val, 0, 2) 8095#define VXGE_HAL_RF_XT_TRACE_RTL_TOP_UP_MSG_NMB_IO_ALL_FUSE(val)\ 8096 vBIT(val, 2, 8) 8097/* 0x08ad0 */ u64 rf_up_xt_dtag_rtl_top; 8098#define VXGE_HAL_RF_UP_XT_DTAG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\ 8099 vBIT(val, 0, 2) 8100#define VXGE_HAL_RF_UP_XT_DTAG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6) 8101/* 0x08ad8 */ u64 rf_up_xt_icache_rtl_top_0_0; 8102#define VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_0_0_MSG_NMB_IO_REPAIR_STATUS(val)\ 8103 vBIT(val, 0, 2) 8104#define VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_0_0_MSG_NMB_IO_ALL_FUSE(val)\ 8105 vBIT(val, 2, 7) 8106/* 0x08ae0 */ u64 rf_up_xt_icache_rtl_top_1_0; 8107#define VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_1_0_MSG_NMB_IO_REPAIR_STATUS(val)\ 8108 vBIT(val, 0, 2) 8109#define VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_1_0_MSG_NMB_IO_ALL_FUSE(val)\ 8110 vBIT(val, 2, 7) 8111/* 0x08ae8 */ u64 rf_up_xt_icache_rtl_top_0_1; 8112#define VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_0_1_MSG_NMB_IO_REPAIR_STATUS(val)\ 8113 vBIT(val, 0, 2) 8114#define VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_0_1_MSG_NMB_IO_ALL_FUSE(val)\ 8115 vBIT(val, 2, 7) 8116/* 0x08af0 */ u64 rf_up_xt_icache_rtl_top_1_1; 8117#define VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_1_1_MSG_NMB_IO_REPAIR_STATUS(val)\ 8118 vBIT(val, 0, 2) 8119#define VXGE_HAL_RF_UP_XT_ICACHE_RTL_TOP_1_1_MSG_NMB_IO_ALL_FUSE(val)\ 8120 vBIT(val, 2, 7) 8121/* 0x08af8 */ u64 rf_up_xt_itag_rtl_top; 8122#define VXGE_HAL_RF_UP_XT_ITAG_RTL_TOP_MSG_NMB_IO_REPAIR_STATUS(val)\ 8123 vBIT(val, 0, 2) 8124#define VXGE_HAL_RF_UP_XT_ITAG_RTL_TOP_MSG_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 6) 8125/* 0x08b00 */ u64 rf_up_xt_dcache_rtl_top_0_0; 8126#define VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_0_0_MSG_NMB_IO_REPAIR_STATUS(val)\ 8127 vBIT(val, 0, 2) 8128#define VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_0_0_MSG_NMB_IO_ALL_FUSE(val)\ 8129 vBIT(val, 2, 7) 8130/* 0x08b08 */ u64 rf_up_xt_dcache_rtl_top_1_0; 8131#define VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_1_0_MSG_NMB_IO_REPAIR_STATUS(val)\ 8132 vBIT(val, 0, 2) 8133#define VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_1_0_MSG_NMB_IO_ALL_FUSE(val)\ 8134 vBIT(val, 2, 7) 8135/* 0x08b10 */ u64 rf_up_xt_dcache_rtl_top_0_1; 8136#define VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_0_1_MSG_NMB_IO_REPAIR_STATUS(val)\ 8137 vBIT(val, 0, 2) 8138#define VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_0_1_MSG_NMB_IO_ALL_FUSE(val)\ 8139 vBIT(val, 2, 7) 8140/* 0x08b18 */ u64 rf_up_xt_dcache_rtl_top_1_1; 8141#define VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_1_1_MSG_NMB_IO_REPAIR_STATUS(val)\ 8142 vBIT(val, 0, 2) 8143#define VXGE_HAL_RF_UP_XT_DCACHE_RTL_TOP_1_1_MSG_NMB_IO_ALL_FUSE(val)\ 8144 vBIT(val, 2, 7) 8145/* 0x08b20 */ u64 rr_rxpe_xt0_iram_rtl_top_0; 8146#define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\ 8147 vBIT(val, 0, 2) 8148#define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK1_FUSE(val)\ 8149 vBIT(val, 2, 7) 8150#define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK1_ADD_FUSE(val)\ 8151 vBIT(val, 9, 4) 8152#define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK0_FUSE(val)\ 8153 vBIT(val, 13, 7) 8154#define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK0_ADD_FUSE(val)\ 8155 vBIT(val, 20, 4) 8156/* 0x08b28 */ u64 rr_rxpe_xt0_iram_rtl_top_1; 8157#define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\ 8158 vBIT(val, 0, 2) 8159#define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK1_FUSE(val)\ 8160 vBIT(val, 2, 7) 8161#define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK1_ADD_FUSE(val)\ 8162 vBIT(val, 9, 4) 8163#define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK0_FUSE(val)\ 8164 vBIT(val, 13, 7) 8165#define VXGE_HAL_RR_RXPE_XT0_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK0_ADD_FUSE(val)\ 8166 vBIT(val, 20, 4) 8167/* 0x08b30 */ u64 rr_rxpe_xt_dram_rtl_top_0; 8168#define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\ 8169 vBIT(val, 0, 2) 8170#define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_0_ONE_NMB_IO_BANK1_FUSE(val)\ 8171 vBIT(val, 2, 7) 8172#define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_0_ONE_NMB_IO_BANK1_ADD_FUSE(val)\ 8173 vBIT(val, 9, 3) 8174#define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_0_ONE_NMB_IO_BANK0_FUSE(val)\ 8175 vBIT(val, 12, 7) 8176#define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_0_ONE_NMB_IO_BANK0_ADD_FUSE(val)\ 8177 vBIT(val, 19, 3) 8178/* 0x08b38 */ u64 rr_rxpe_xt_dram_rtl_top_1; 8179#define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\ 8180 vBIT(val, 0, 2) 8181#define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_1_ONE_NMB_IO_BANK1_FUSE(val)\ 8182 vBIT(val, 2, 7) 8183#define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_1_ONE_NMB_IO_BANK1_ADD_FUSE(val)\ 8184 vBIT(val, 9, 3) 8185#define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_1_ONE_NMB_IO_BANK0_FUSE(val)\ 8186 vBIT(val, 12, 7) 8187#define VXGE_HAL_RR_RXPE_XT_DRAM_RTL_TOP_1_ONE_NMB_IO_BANK0_ADD_FUSE(val)\ 8188 vBIT(val, 19, 3) 8189/* 0x08b40 */ u64 rf_rxpe_msg2rxpe_rtl_top_0; 8190#define VXGE_HAL_RF_RXPE_MSG2RXPE_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\ 8191 vBIT(val, 0, 2) 8192#define VXGE_HAL_RF_RXPE_MSG2RXPE_RTL_TOP_0_ONE_NMB_IO_ALL_FUSE(val)\ 8193 vBIT(val, 2, 7) 8194/* 0x08b48 */ u64 rf_rxpe_msg2rxpe_rtl_top_1; 8195#define VXGE_HAL_RF_RXPE_MSG2RXPE_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\ 8196 vBIT(val, 0, 2) 8197#define VXGE_HAL_RF_RXPE_MSG2RXPE_RTL_TOP_1_ONE_NMB_IO_ALL_FUSE(val)\ 8198 vBIT(val, 2, 7) 8199/* 0x08b50 */ u64 rf_rxpe_xt0_frm_rtl_top; 8200#define VXGE_HAL_RF_RXPE_XT0_FRM_RTL_TOP_ONE_NMB_IO_REPAIR_STATUS(val)\ 8201 vBIT(val, 0, 2) 8202#define VXGE_HAL_RF_RXPE_XT0_FRM_RTL_TOP_ONE_NMB_IO_ALL_FUSE(val)\ 8203 vBIT(val, 2, 8) 8204/* 0x08b58 */ u64 rf_rpe_pdm_rcmd_rtl_top; 8205#define VXGE_HAL_RF_RPE_PDM_RCMD_RTL_TOP_ONE_NMB_IO_REPAIR_STATUS(val)\ 8206 vBIT(val, 0, 2) 8207#define VXGE_HAL_RF_RPE_PDM_RCMD_RTL_TOP_ONE_NMB_IO_ALL_FUSE(val)\ 8208 vBIT(val, 2, 8) 8209/* 0x08b60 */ u64 rf_rpe_rcq_rtl_top; 8210#define VXGE_HAL_RF_RPE_RCQ_RTL_TOP_ONE_NMB_IO_REPAIR_STATUS(val)\ 8211 vBIT(val, 0, 2) 8212#define VXGE_HAL_RF_RPE_RCQ_RTL_TOP_ONE_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 8) 8213/* 0x08b68 */ u64 rf_rpe_rco_pble_rtl_top; 8214#define VXGE_HAL_RF_RPE_RCO_PBLE_RTL_TOP_ONE_NMB_IO_REPAIR_STATUS(val)\ 8215 vBIT(val, 0, 2) 8216#define VXGE_HAL_RF_RPE_RCO_PBLE_RTL_TOP_ONE_NMB_IO_ALL_FUSE(val)\ 8217 vBIT(val, 2, 8) 8218/* 0x08b70 */ u64 rr_rxpe_xt1_iram_rtl_top_0; 8219#define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\ 8220 vBIT(val, 0, 2) 8221#define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK1_FUSE(val)\ 8222 vBIT(val, 2, 7) 8223#define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK1_ADD_FUSE(val)\ 8224 vBIT(val, 9, 4) 8225#define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK0_FUSE(val)\ 8226 vBIT(val, 13, 7) 8227#define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_0_ONE_NMB_IO_BANK0_ADD_FUSE(val)\ 8228 vBIT(val, 20, 4) 8229/* 0x08b78 */ u64 rr_rxpe_xt1_iram_rtl_top_1; 8230#define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\ 8231 vBIT(val, 0, 2) 8232#define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK1_FUSE(val)\ 8233 vBIT(val, 2, 7) 8234#define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK1_ADD_FUSE(val)\ 8235 vBIT(val, 9, 4) 8236#define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK0_FUSE(val)\ 8237 vBIT(val, 13, 7) 8238#define VXGE_HAL_RR_RXPE_XT1_IRAM_RTL_TOP_1_ONE_NMB_IO_BANK0_ADD_FUSE(val)\ 8239 vBIT(val, 20, 4) 8240/* 0x08b80 */ u64 rr_rpe_sccm_rtl_top_0; 8241#define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\ 8242 vBIT(val, 0, 2) 8243#define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_0_ONE_NMB_IO_BANK1_FUSE(val)\ 8244 vBIT(val, 2, 8) 8245#define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_0_ONE_NMB_IO_BANK1_ADD_FUSE(val)\ 8246 vBIT(val, 10, 2) 8247#define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_0_ONE_NMB_IO_BANK0_FUSE(val)\ 8248 vBIT(val, 12, 8) 8249#define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_0_ONE_NMB_IO_BANK0_ADD_FUSE(val)\ 8250 vBIT(val, 20, 2) 8251/* 0x08b88 */ u64 rr_rpe_sccm_rtl_top_1; 8252#define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\ 8253 vBIT(val, 0, 2) 8254#define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_1_ONE_NMB_IO_BANK1_FUSE(val)\ 8255 vBIT(val, 2, 8) 8256#define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_1_ONE_NMB_IO_BANK1_ADD_FUSE(val)\ 8257 vBIT(val, 10, 2) 8258#define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_1_ONE_NMB_IO_BANK0_FUSE(val)\ 8259 vBIT(val, 12, 8) 8260#define VXGE_HAL_RR_RPE_SCCM_RTL_TOP_1_ONE_NMB_IO_BANK0_ADD_FUSE(val)\ 8261 vBIT(val, 20, 2) 8262/* 0x08b90 */ u64 rr_pe_pet_timer_rtl_top_0; 8263#define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\ 8264 vBIT(val, 0, 2) 8265#define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_0_ONE_NMB_IO_BANK1_FUSE(val)\ 8266 vBIT(val, 2, 7) 8267#define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_0_ONE_NMB_IO_BANK1_ADD_FUSE(val)\ 8268 vBIT(val, 9, 3) 8269#define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_0_ONE_NMB_IO_BANK0_FUSE(val)\ 8270 vBIT(val, 12, 7) 8271#define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_0_ONE_NMB_IO_BANK0_ADD_FUSE(val)\ 8272 vBIT(val, 19, 3) 8273/* 0x08b98 */ u64 rr_pe_pet_timer_rtl_top_1; 8274#define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\ 8275 vBIT(val, 0, 2) 8276#define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_1_ONE_NMB_IO_BANK1_FUSE(val)\ 8277 vBIT(val, 2, 7) 8278#define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_1_ONE_NMB_IO_BANK1_ADD_FUSE(val)\ 8279 vBIT(val, 9, 3) 8280#define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_1_ONE_NMB_IO_BANK0_FUSE(val)\ 8281 vBIT(val, 12, 7) 8282#define VXGE_HAL_RR_PE_PET_TIMER_RTL_TOP_1_ONE_NMB_IO_BANK0_ADD_FUSE(val)\ 8283 vBIT(val, 19, 3) 8284/* 0x08ba0 */ u64 rf_pe_dlm_lwrq_rtl_top_0; 8285#define VXGE_HAL_RF_PE_DLM_LWRQ_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\ 8286 vBIT(val, 0, 2) 8287#define VXGE_HAL_RF_PE_DLM_LWRQ_RTL_TOP_0_ONE_NMB_IO_ALL_FUSE(val)\ 8288 vBIT(val, 2, 8) 8289/* 0x08ba8 */ u64 rf_pe_dlm_lwrq_rtl_top_1; 8290#define VXGE_HAL_RF_PE_DLM_LWRQ_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\ 8291 vBIT(val, 0, 2) 8292#define VXGE_HAL_RF_PE_DLM_LWRQ_RTL_TOP_1_ONE_NMB_IO_ALL_FUSE(val)\ 8293 vBIT(val, 2, 8) 8294/* 0x08bb0 */ u64 rf_txpe_msg2txpe_rtl_top_0; 8295#define VXGE_HAL_RF_TXPE_MSG2TXPE_RTL_TOP_0_ONE_NMB_IO_REPAIR_STATUS(val)\ 8296 vBIT(val, 0, 2) 8297#define VXGE_HAL_RF_TXPE_MSG2TXPE_RTL_TOP_0_ONE_NMB_IO_ALL_FUSE(val)\ 8298 vBIT(val, 2, 8) 8299/* 0x08bb8 */ u64 rf_txpe_msg2txpe_rtl_top_1; 8300#define VXGE_HAL_RF_TXPE_MSG2TXPE_RTL_TOP_1_ONE_NMB_IO_REPAIR_STATUS(val)\ 8301 vBIT(val, 0, 2) 8302#define VXGE_HAL_RF_TXPE_MSG2TXPE_RTL_TOP_1_ONE_NMB_IO_ALL_FUSE(val)\ 8303 vBIT(val, 2, 8) 8304/* 0x08bc0 */ u64 rf_pci_retry_buf_rtl_top_0; 8305#define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_0_PCI_NMB_IO_REPAIR_STATUS(val)\ 8306 vBIT(val, 0, 2) 8307#define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_0_PCI_NMB_IO_ALL_FUSE(val)\ 8308 vBIT(val, 2, 8) 8309/* 0x08bc8 */ u64 rf_pci_retry_buf_rtl_top_1; 8310#define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_1_PCI_NMB_IO_REPAIR_STATUS(val)\ 8311 vBIT(val, 0, 2) 8312#define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_1_PCI_NMB_IO_ALL_FUSE(val)\ 8313 vBIT(val, 2, 8) 8314/* 0x08bd0 */ u64 rf_pci_retry_buf_rtl_top_2; 8315#define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_2_PCI_NMB_IO_REPAIR_STATUS(val)\ 8316 vBIT(val, 0, 2) 8317#define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_2_PCI_NMB_IO_ALL_FUSE(val)\ 8318 vBIT(val, 2, 8) 8319/* 0x08bd8 */ u64 rf_pci_retry_buf_rtl_top_3; 8320#define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_3_PCI_NMB_IO_REPAIR_STATUS(val)\ 8321 vBIT(val, 0, 2) 8322#define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_3_PCI_NMB_IO_ALL_FUSE(val)\ 8323 vBIT(val, 2, 8) 8324/* 0x08be0 */ u64 rf_pci_retry_buf_rtl_top_4; 8325#define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_4_PCI_NMB_IO_REPAIR_STATUS(val)\ 8326 vBIT(val, 0, 2) 8327#define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_4_PCI_NMB_IO_ALL_FUSE(val)\ 8328 vBIT(val, 2, 8) 8329/* 0x08be8 */ u64 rf_pci_retry_buf_rtl_top_5; 8330#define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_5_PCI_NMB_IO_REPAIR_STATUS(val)\ 8331 vBIT(val, 0, 2) 8332#define VXGE_HAL_RF_PCI_RETRY_BUF_RTL_TOP_5_PCI_NMB_IO_ALL_FUSE(val)\ 8333 vBIT(val, 2, 8) 8334/* 0x08bf0 */ u64 rf_pci_sot_buf_rtl_top; 8335#define VXGE_HAL_RF_PCI_SOT_BUF_RTL_TOP_PCI_NMB_IO_REPAIR_STATUS(val)\ 8336 vBIT(val, 0, 2) 8337#define VXGE_HAL_RF_PCI_SOT_BUF_RTL_TOP_PCI_NMB_IO_ALL_FUSE(val)\ 8338 vBIT(val, 2, 6) 8339/* 0x08bf8 */ u64 rf_pci_rx_ph_rtl_top; 8340#define VXGE_HAL_RF_PCI_RX_PH_RTL_TOP_PCI_NMB_IO_REPAIR_STATUS(val)\ 8341 vBIT(val, 0, 2) 8342#define VXGE_HAL_RF_PCI_RX_PH_RTL_TOP_PCI_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 8) 8343/* 0x08c00 */ u64 rf_pci_rx_nph_rtl_top; 8344#define VXGE_HAL_RF_PCI_RX_NPH_RTL_TOP_PCI_NMB_IO_REPAIR_STATUS(val)\ 8345 vBIT(val, 0, 2) 8346#define VXGE_HAL_RF_PCI_RX_NPH_RTL_TOP_PCI_NMB_IO_ALL_FUSE(val) vBIT(val, 2, 8) 8347/* 0x08c08 */ u64 rf_pci_rx_pd_rtl_top_0; 8348#define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_0_PCI_NMB_IO_REPAIR_STATUS(val)\ 8349 vBIT(val, 0, 2) 8350#define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_0_PCI_NMB_IO_ALL_FUSE(val)\ 8351 vBIT(val, 2, 7) 8352/* 0x08c10 */ u64 rf_pci_rx_pd_rtl_top_1; 8353#define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_1_PCI_NMB_IO_REPAIR_STATUS(val)\ 8354 vBIT(val, 0, 2) 8355#define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_1_PCI_NMB_IO_ALL_FUSE(val)\ 8356 vBIT(val, 2, 7) 8357/* 0x08c18 */ u64 rf_pci_rx_pd_rtl_top_2; 8358#define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_2_PCI_NMB_IO_REPAIR_STATUS(val)\ 8359 vBIT(val, 0, 2) 8360#define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_2_PCI_NMB_IO_ALL_FUSE(val)\ 8361 vBIT(val, 2, 7) 8362/* 0x08c20 */ u64 rf_pci_rx_pd_rtl_top_3; 8363#define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_3_PCI_NMB_IO_REPAIR_STATUS(val)\ 8364 vBIT(val, 0, 2) 8365#define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_3_PCI_NMB_IO_ALL_FUSE(val)\ 8366 vBIT(val, 2, 7) 8367/* 0x08c28 */ u64 rf_pci_rx_pd_rtl_top_4; 8368#define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_4_PCI_NMB_IO_REPAIR_STATUS(val)\ 8369 vBIT(val, 0, 2) 8370#define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_4_PCI_NMB_IO_ALL_FUSE(val)\ 8371 vBIT(val, 2, 7) 8372/* 0x08c30 */ u64 rf_pci_rx_pd_rtl_top_5; 8373#define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_5_PCI_NMB_IO_REPAIR_STATUS(val)\ 8374 vBIT(val, 0, 2) 8375#define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_5_PCI_NMB_IO_ALL_FUSE(val)\ 8376 vBIT(val, 2, 7) 8377/* 0x08c38 */ u64 rf_pci_rx_pd_rtl_top_6; 8378#define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_6_PCI_NMB_IO_REPAIR_STATUS(val)\ 8379 vBIT(val, 0, 2) 8380#define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_6_PCI_NMB_IO_ALL_FUSE(val)\ 8381 vBIT(val, 2, 7) 8382/* 0x08c40 */ u64 rf_pci_rx_pd_rtl_top_7; 8383#define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_7_PCI_NMB_IO_REPAIR_STATUS(val)\ 8384 vBIT(val, 0, 2) 8385#define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_7_PCI_NMB_IO_ALL_FUSE(val)\ 8386 vBIT(val, 2, 7) 8387/* 0x08c48 */ u64 rf_pci_rx_pd_rtl_top_8; 8388#define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_8_PCI_NMB_IO_REPAIR_STATUS(val)\ 8389 vBIT(val, 0, 2) 8390#define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_8_PCI_NMB_IO_ALL_FUSE(val)\ 8391 vBIT(val, 2, 7) 8392/* 0x08c50 */ u64 rf_pci_rx_pd_rtl_top_9; 8393#define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_9_PCI_NMB_IO_REPAIR_STATUS(val)\ 8394 vBIT(val, 0, 2) 8395#define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_9_PCI_NMB_IO_ALL_FUSE(val)\ 8396 vBIT(val, 2, 7) 8397/* 0x08c58 */ u64 rf_pci_rx_pd_rtl_top_10; 8398#define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_10_PCI_NMB_IO_REPAIR_STATUS(val)\ 8399 vBIT(val, 0, 2) 8400#define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_10_PCI_NMB_IO_ALL_FUSE(val)\ 8401 vBIT(val, 2, 7) 8402/* 0x08c60 */ u64 rf_pci_rx_pd_rtl_top_11; 8403#define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_11_PCI_NMB_IO_REPAIR_STATUS(val)\ 8404 vBIT(val, 0, 2) 8405#define VXGE_HAL_RF_PCI_RX_PD_RTL_TOP_11_PCI_NMB_IO_ALL_FUSE(val)\ 8406 vBIT(val, 2, 7) 8407/* 0x08c68 */ u64 rf_pci_rx_npd_rtl_top_0; 8408#define VXGE_HAL_RF_PCI_RX_NPD_RTL_TOP_0_PCI_NMB_IO_REPAIR_STATUS(val)\ 8409 vBIT(val, 0, 2) 8410#define VXGE_HAL_RF_PCI_RX_NPD_RTL_TOP_0_PCI_NMB_IO_ALL_FUSE(val)\ 8411 vBIT(val, 2, 7) 8412/* 0x08c70 */ u64 rf_pci_rx_npd_rtl_top_1; 8413#define VXGE_HAL_RF_PCI_RX_NPD_RTL_TOP_1_PCI_NMB_IO_REPAIR_STATUS(val)\ 8414 vBIT(val, 0, 2) 8415#define VXGE_HAL_RF_PCI_RX_NPD_RTL_TOP_1_PCI_NMB_IO_ALL_FUSE(val)\ 8416 vBIT(val, 2, 7) 8417/* 0x08c78 */ u64 rf_pic_kdfc_dbl_rtl_top_0; 8418#define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_0_PCI_NMB_IO_REPAIR_STATUS(val)\ 8419 vBIT(val, 0, 2) 8420#define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_0_PCI_NMB_IO_ALL_FUSE(val)\ 8421 vBIT(val, 2, 8) 8422/* 0x08c80 */ u64 rf_pic_kdfc_dbl_rtl_top_1; 8423#define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_1_PCI_NMB_IO_REPAIR_STATUS(val)\ 8424 vBIT(val, 0, 2) 8425#define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_1_PCI_NMB_IO_ALL_FUSE(val)\ 8426 vBIT(val, 2, 8) 8427/* 0x08c88 */ u64 rf_pic_kdfc_dbl_rtl_top_2; 8428#define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_2_PCI_NMB_IO_REPAIR_STATUS(val)\ 8429 vBIT(val, 0, 2) 8430#define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_2_PCI_NMB_IO_ALL_FUSE(val)\ 8431 vBIT(val, 2, 8) 8432/* 0x08c90 */ u64 rf_pic_kdfc_dbl_rtl_top_3; 8433#define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_3_PCI_NMB_IO_REPAIR_STATUS(val)\ 8434 vBIT(val, 0, 2) 8435#define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_3_PCI_NMB_IO_ALL_FUSE(val)\ 8436 vBIT(val, 2, 8) 8437/* 0x08c98 */ u64 rf_pic_kdfc_dbl_rtl_top_4; 8438#define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_4_PCI_NMB_IO_REPAIR_STATUS(val)\ 8439 vBIT(val, 0, 2) 8440#define VXGE_HAL_RF_PIC_KDFC_DBL_RTL_TOP_4_PCI_NMB_IO_ALL_FUSE(val)\ 8441 vBIT(val, 2, 8) 8442/* 0x08ca0 */ u64 rf_pcc_txdo_rtl_top_pcc0; 8443#define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC0_RTDMA_NMB_IO_REPAIR_STATUS(val)\ 8444 vBIT(val, 0, 2) 8445#define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC0_RTDMA_NMB_IO_ALL_FUSE(val)\ 8446 vBIT(val, 2, 8) 8447/* 0x08ca8 */ u64 rf_pcc_txdo_rtl_top_pcc1; 8448#define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC1_RTDMA_NMB_IO_REPAIR_STATUS(val)\ 8449 vBIT(val, 0, 2) 8450#define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC1_RTDMA_NMB_IO_ALL_FUSE(val)\ 8451 vBIT(val, 2, 8) 8452/* 0x08cb0 */ u64 rf_pcc_txdo_rtl_top_pcc2; 8453#define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC2_RTDMA_NMB_IO_REPAIR_STATUS(val)\ 8454 vBIT(val, 0, 2) 8455#define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC2_RTDMA_NMB_IO_ALL_FUSE(val)\ 8456 vBIT(val, 2, 8) 8457/* 0x08cb8 */ u64 rf_pcc_txdo_rtl_top_pcc3; 8458#define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC3_RTDMA_NMB_IO_REPAIR_STATUS(val)\ 8459 vBIT(val, 0, 2) 8460#define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC3_RTDMA_NMB_IO_ALL_FUSE(val)\ 8461 vBIT(val, 2, 8) 8462/* 0x08cc0 */ u64 rf_pcc_txdo_rtl_top_pcc4; 8463#define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC4_RTDMA_NMB_IO_REPAIR_STATUS(val)\ 8464 vBIT(val, 0, 2) 8465#define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC4_RTDMA_NMB_IO_ALL_FUSE(val)\ 8466 vBIT(val, 2, 8) 8467/* 0x08cc8 */ u64 rf_pcc_txdo_rtl_top_pcc5; 8468#define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC5_RTDMA_NMB_IO_REPAIR_STATUS(val)\ 8469 vBIT(val, 0, 2) 8470#define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC5_RTDMA_NMB_IO_ALL_FUSE(val)\ 8471 vBIT(val, 2, 8) 8472/* 0x08cd0 */ u64 rf_pcc_txdo_rtl_top_pcc6; 8473#define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC6_RTDMA_NMB_IO_REPAIR_STATUS(val)\ 8474 vBIT(val, 0, 2) 8475#define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC6_RTDMA_NMB_IO_ALL_FUSE(val)\ 8476 vBIT(val, 2, 8) 8477/* 0x08cd8 */ u64 rf_pcc_txdo_rtl_top_pcc7; 8478#define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC7_RTDMA_NMB_IO_REPAIR_STATUS(val)\ 8479 vBIT(val, 0, 2) 8480#define VXGE_HAL_RF_PCC_TXDO_RTL_TOP_PCC7_RTDMA_NMB_IO_ALL_FUSE(val)\ 8481 vBIT(val, 2, 8) 8482/* 0x08ce0 */ u64 rr_pcc_ass_buf_rtl_top_pcc1; 8483#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC1_RTDMA_NMB_IO_REPAIR_STATUS(val)\ 8484 vBIT(val, 0, 2) 8485#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC1_RTDMA_NMB_IO_BANK1_FUSE(val)\ 8486 vBIT(val, 2, 8) 8487#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC1_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\ 8488 vBIT(val, 10, 2) 8489#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC1_RTDMA_NMB_IO_BANK0_FUSE(val)\ 8490 vBIT(val, 12, 8) 8491#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC1_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\ 8492 vBIT(val, 20, 2) 8493/* 0x08ce8 */ u64 rr_pcc_ass_buf_rtl_top_pcc3; 8494#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC3_RTDMA_NMB_IO_REPAIR_STATUS(val)\ 8495 vBIT(val, 0, 2) 8496#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC3_RTDMA_NMB_IO_BANK1_FUSE(val)\ 8497 vBIT(val, 2, 8) 8498#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC3_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\ 8499 vBIT(val, 10, 2) 8500#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC3_RTDMA_NMB_IO_BANK0_FUSE(val)\ 8501 vBIT(val, 12, 8) 8502#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC3_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\ 8503 vBIT(val, 20, 2) 8504/* 0x08cf0 */ u64 rr_pcc_ass_buf_rtl_top_pcc5; 8505#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC5_RTDMA_NMB_IO_REPAIR_STATUS(val)\ 8506 vBIT(val, 0, 2) 8507#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC5_RTDMA_NMB_IO_BANK1_FUSE(val)\ 8508 vBIT(val, 2, 8) 8509#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC5_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\ 8510 vBIT(val, 10, 2) 8511#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC5_RTDMA_NMB_IO_BANK0_FUSE(val)\ 8512 vBIT(val, 12, 8) 8513#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC5_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\ 8514 vBIT(val, 20, 2) 8515/* 0x08cf8 */ u64 rr_pcc_ass_buf_rtl_top_pcc7; 8516#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC7_RTDMA_NMB_IO_REPAIR_STATUS(val)\ 8517 vBIT(val, 0, 2) 8518#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC7_RTDMA_NMB_IO_BANK1_FUSE(val)\ 8519 vBIT(val, 2, 8) 8520#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC7_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\ 8521 vBIT(val, 10, 2) 8522#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC7_RTDMA_NMB_IO_BANK0_FUSE(val)\ 8523 vBIT(val, 12, 8) 8524#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC7_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\ 8525 vBIT(val, 20, 2) 8526/* 0x08d00 */ u64 rr_pcc_ass_buf_rtl_top_pcc0; 8527#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC0_RTDMA_NMB_IO_REPAIR_STATUS(val)\ 8528 vBIT(val, 0, 2) 8529#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC0_RTDMA_NMB_IO_BANK1_FUSE(val)\ 8530 vBIT(val, 2, 8) 8531#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC0_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\ 8532 vBIT(val, 10, 2) 8533#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC0_RTDMA_NMB_IO_BANK0_FUSE(val)\ 8534 vBIT(val, 12, 8) 8535#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC0_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\ 8536 vBIT(val, 20, 2) 8537/* 0x08d08 */ u64 rr_pcc_ass_buf_rtl_top_pcc2; 8538#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC2_RTDMA_NMB_IO_REPAIR_STATUS(val)\ 8539 vBIT(val, 0, 2) 8540#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC2_RTDMA_NMB_IO_BANK1_FUSE(val)\ 8541 vBIT(val, 2, 8) 8542#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC2_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\ 8543 vBIT(val, 10, 2) 8544#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC2_RTDMA_NMB_IO_BANK0_FUSE(val)\ 8545 vBIT(val, 12, 8) 8546#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC2_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\ 8547 vBIT(val, 20, 2) 8548/* 0x08d10 */ u64 rr_pcc_ass_buf_rtl_top_pcc6; 8549#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC6_RTDMA_NMB_IO_REPAIR_STATUS(val)\ 8550 vBIT(val, 0, 2) 8551#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC6_RTDMA_NMB_IO_BANK1_FUSE(val)\ 8552 vBIT(val, 2, 8) 8553#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC6_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\ 8554 vBIT(val, 10, 2) 8555#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC6_RTDMA_NMB_IO_BANK0_FUSE(val)\ 8556 vBIT(val, 12, 8) 8557#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC6_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\ 8558 vBIT(val, 20, 2) 8559/* 0x08d18 */ u64 rr_pcc_ass_buf_rtl_top_pcc4; 8560#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC4_RTDMA_NMB_IO_REPAIR_STATUS(val)\ 8561 vBIT(val, 0, 2) 8562#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC4_RTDMA_NMB_IO_BANK1_FUSE(val)\ 8563 vBIT(val, 2, 8) 8564#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC4_RTDMA_NMB_IO_BANK1_ADD_FUSE(val)\ 8565 vBIT(val, 10, 2) 8566#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC4_RTDMA_NMB_IO_BANK0_FUSE(val)\ 8567 vBIT(val, 12, 8) 8568#define VXGE_HAL_RR_PCC_ASS_BUF_RTL_TOP_PCC4_RTDMA_NMB_IO_BANK0_ADD_FUSE(val)\ 8569 vBIT(val, 20, 2) 8570/* 0x08d20 */ u64 rf_rocrc_cmdq_bp_rtl_top_0_wrapper0; 8571#define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_0_W0_WRDMA_NMB_IO_REPAIR_STATUS(val)\ 8572 vBIT(val, 0, 2) 8573#define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_0_W0_WRDMA_NMB_IO_ALL_FUSE(val)\ 8574 vBIT(val, 2, 8) 8575/* 0x08d28 */ u64 rf_rocrc_cmdq_bp_rtl_top_1_wrapper0; 8576#define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_1_W0_WRDMA_NMB_IO_REPAIR_STATUS(val)\ 8577 vBIT(val, 0, 2) 8578#define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_1_W0_WRDMA_NMB_IO_ALL_FUSE(val)\ 8579 vBIT(val, 2, 8) 8580/* 0x08d30 */ u64 rf_rocrc_cmdq_bp_rtl_top_2_wrapper0; 8581#define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_2_W0_WRDMA_NMB_IO_REPAIR_STATUS(val)\ 8582 vBIT(val, 0, 2) 8583#define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_2_WRAPPER0_WRDMA_NMB_IO_ALL_FUSE(val)\ 8584 vBIT(val, 2, 8) 8585/* 0x08d38 */ u64 rf_rocrc_cmdq_bp_rtl_top_0_wrapper1; 8586#define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_0_W1_WRDMA_NMB_IO_REPAIR_STATUS(val)\ 8587 vBIT(val, 0, 2) 8588#define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_0_W1_WRDMA_NMB_IO_ALL_FUSE(val)\ 8589 vBIT(val, 2, 8) 8590/* 0x08d40 */ u64 rf_rocrc_cmdq_bp_rtl_top_1_wrapper1; 8591#define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_1_W1_WRDMA_NMB_IO_REPAIR_STATUS(val)\ 8592 vBIT(val, 0, 2) 8593#define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_1_W1_WRDMA_NMB_IO_ALL_FUSE(val)\ 8594 vBIT(val, 2, 8) 8595/* 0x08d48 */ u64 rf_rocrc_cmdq_bp_rtl_top_2_wrapper1; 8596#define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_2_W1_WRDMA_NMB_IO_REPAIR_STATUS(val)\ 8597 vBIT(val, 0, 2) 8598#define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_2_W1_WRDMA_NMB_IO_ALL_FUSE(val)\ 8599 vBIT(val, 2, 8) 8600/* 0x08d50 */ u64 rf_rocrc_cmdq_bp_rtl_top_0_wrapper2; 8601#define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_0_W2_WRDMA_NMB_IO_REPAIR_STATUS(val)\ 8602 vBIT(val, 0, 2) 8603#define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_0_WRAPPER2_WRDMA_NMB_IO_ALL_FUSE(val)\ 8604 vBIT(val, 2, 8) 8605/* 0x08d58 */ u64 rf_rocrc_cmdq_bp_rtl_top_1_wrapper2; 8606#define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_1_W2_WRDMA_NMB_IO_REPAIR_STATUS(val)\ 8607 vBIT(val, 0, 2) 8608#define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_1_W2_WRDMA_NMB_IO_ALL_FUSE(val)\ 8609 vBIT(val, 2, 8) 8610/* 0x08d60 */ u64 rf_rocrc_cmdq_bp_rtl_top_2_wrapper2; 8611#define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_2_W2_WRDMA_NMB_IO_REPAIR_STATUS(val)\ 8612 vBIT(val, 0, 2) 8613#define VXGE_HAL_RF_ROCRC_CMDQ_BP_RTL_TOP_2_W2_WRDMA_NMB_IO_ALL_FUSE(val)\ 8614 vBIT(val, 2, 8) 8615/* 0x08d68 */ u64 rr_rocrc_rxd_rtl_top_rxd0; 8616#define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD0_WRDMA_NMB_IO_REPAIR_STATUS(val)\ 8617 vBIT(val, 0, 2) 8618#define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD0_WRDMA_NMB_IO_BANK1_FUSE(val)\ 8619 vBIT(val, 2, 8) 8620#define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD0_WRDMA_NMB_IO_BANK1_ADD_FUSE(val)\ 8621 vBIT(val, 10, 2) 8622#define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD0_WRDMA_NMB_IO_BANK0_FUSE(val)\ 8623 vBIT(val, 12, 8) 8624#define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD0_WRDMA_NMB_IO_BANK0_ADD_FUSE(val)\ 8625 vBIT(val, 20, 2) 8626/* 0x08d70 */ u64 rr_rocrc_rxd_rtl_top_rxd1; 8627#define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD1_WRDMA_NMB_IO_REPAIR_STATUS(val)\ 8628 vBIT(val, 0, 2) 8629#define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD1_WRDMA_NMB_IO_BANK1_FUSE(val)\ 8630 vBIT(val, 2, 8) 8631#define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD1_WRDMA_NMB_IO_BANK1_ADD_FUSE(val)\ 8632 vBIT(val, 10, 2) 8633#define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD1_WRDMA_NMB_IO_BANK0_FUSE(val)\ 8634 vBIT(val, 12, 8) 8635#define VXGE_HAL_RR_ROCRC_RXD_RTL_TOP_RXD1_WRDMA_NMB_IO_BANK0_ADD_FUSE(val)\ 8636 vBIT(val, 20, 2) 8637/* 0x08d78 */ u64 rf_rocrc_umq_mdq_rtl_top_0; 8638#define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_0_WRDMA_NMB_IO_REPAIR_STATUS(val)\ 8639 vBIT(val, 0, 2) 8640#define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_0_WRDMA_NMB_IO_ALL_FUSE(val)\ 8641 vBIT(val, 2, 8) 8642/* 0x08d80 */ u64 rf_rocrc_umq_mdq_rtl_top_1; 8643#define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_1_WRDMA_NMB_IO_REPAIR_STATUS(val)\ 8644 vBIT(val, 0, 2) 8645#define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_1_WRDMA_NMB_IO_ALL_FUSE(val)\ 8646 vBIT(val, 2, 8) 8647/* 0x08d88 */ u64 rf_rocrc_umq_mdq_rtl_top_2; 8648#define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_2_WRDMA_NMB_IO_REPAIR_STATUS(val)\ 8649 vBIT(val, 0, 2) 8650#define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_2_WRDMA_NMB_IO_ALL_FUSE(val)\ 8651 vBIT(val, 2, 8) 8652/* 0x08d90 */ u64 rf_rocrc_umq_mdq_rtl_top_3; 8653#define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_3_WRDMA_NMB_IO_REPAIR_STATUS(val)\ 8654 vBIT(val, 0, 2) 8655#define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_3_WRDMA_NMB_IO_ALL_FUSE(val)\ 8656 vBIT(val, 2, 8) 8657/* 0x08d98 */ u64 rf_rocrc_umq_mdq_rtl_top_4; 8658#define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_4_WRDMA_NMB_IO_REPAIR_STATUS(val)\ 8659 vBIT(val, 0, 2) 8660#define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_4_WRDMA_NMB_IO_ALL_FUSE(val)\ 8661 vBIT(val, 2, 8) 8662/* 0x08da0 */ u64 rf_rocrc_umq_mdq_rtl_top_5; 8663#define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_5_WRDMA_NMB_IO_REPAIR_STATUS(val)\ 8664 vBIT(val, 0, 2) 8665#define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_5_WRDMA_NMB_IO_ALL_FUSE(val)\ 8666 vBIT(val, 2, 8) 8667/* 0x08da8 */ u64 rf_rocrc_umq_mdq_rtl_top_6; 8668#define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_6_WRDMA_NMB_IO_REPAIR_STATUS(val)\ 8669 vBIT(val, 0, 2) 8670#define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_6_WRDMA_NMB_IO_ALL_FUSE(val)\ 8671 vBIT(val, 2, 8) 8672/* 0x08db0 */ u64 rf_rocrc_umq_mdq_rtl_top_7; 8673#define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_7_WRDMA_NMB_IO_REPAIR_STATUS(val)\ 8674 vBIT(val, 0, 2) 8675#define VXGE_HAL_RF_ROCRC_UMQ_MDQ_RTL_TOP_7_WRDMA_NMB_IO_ALL_FUSE(val)\ 8676 vBIT(val, 2, 8) 8677/* 0x08db8 */ u64 rf_rocrc_immdbuf_rtl_top; 8678#define VXGE_HAL_RF_ROCRC_IMMDBUF_RTL_TOP_WRDMA_NMB_IO_REPAIR_STATUS(val)\ 8679 vBIT(val, 0, 2) 8680#define VXGE_HAL_RF_ROCRC_IMMDBUF_RTL_TOP_WRDMA_NMB_IO_ALL_FUSE(val)\ 8681 vBIT(val, 2, 8) 8682/* 0x08dc0 */ u64 rf_rocrc_qcc_byp_rtl_top_0; 8683#define VXGE_HAL_RF_ROCRC_QCC_BYP_RTL_TOP_0_WRDMA_NMB_IO_REPAIR_STATUS(val)\ 8684 vBIT(val, 0, 2) 8685#define VXGE_HAL_RF_ROCRC_QCC_BYP_RTL_TOP_0_WRDMA_NMB_IO_ALL_FUSE(val)\ 8686 vBIT(val, 2, 8) 8687/* 0x08dc8 */ u64 rf_rocrc_qcc_byp_rtl_top_1; 8688#define VXGE_HAL_RF_ROCRC_QCC_BYP_RTL_TOP_1_WRDMA_NMB_IO_REPAIR_STATUS(val)\ 8689 vBIT(val, 0, 2) 8690#define VXGE_HAL_RF_ROCRC_QCC_BYP_RTL_TOP_1_WRDMA_NMB_IO_ALL_FUSE(val)\ 8691 vBIT(val, 2, 8) 8692/* 0x08dd0 */ u64 rr_rmac_da_lkp_rtl_top_0; 8693#define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_0_XGMAC_NMB_IO_REPAIR_STATUS(val)\ 8694 vBIT(val, 0, 2) 8695#define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_0_XGMAC_NMB_IO_BANK1_FUSE(val)\ 8696 vBIT(val, 2, 6) 8697#define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_0_XGMAC_NMB_IO_BANK1_ADD_FUSE(val)\ 8698 vBIT(val, 8, 2) 8699#define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_0_XGMAC_NMB_IO_BANK0_FUSE(val)\ 8700 vBIT(val, 10, 6) 8701#define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_0_XGMAC_NMB_IO_BANK0_ADD_FUSE(val)\ 8702 vBIT(val, 16, 2) 8703/* 0x08dd8 */ u64 rr_rmac_da_lkp_rtl_top_1; 8704#define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_1_XGMAC_NMB_IO_REPAIR_STATUS(val)\ 8705 vBIT(val, 0, 2) 8706#define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_1_XGMAC_NMB_IO_BANK1_FUSE(val)\ 8707 vBIT(val, 2, 6) 8708#define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_1_XGMAC_NMB_IO_BANK1_ADD_FUSE(val)\ 8709 vBIT(val, 8, 2) 8710#define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_1_XGMAC_NMB_IO_BANK0_FUSE(val)\ 8711 vBIT(val, 10, 6) 8712#define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_1_XGMAC_NMB_IO_BANK0_ADD_FUSE(val)\ 8713 vBIT(val, 16, 2) 8714/* 0x08de0 */ u64 rr_rmac_da_lkp_rtl_top_2; 8715#define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_2_XGMAC_NMB_IO_REPAIR_STATUS(val)\ 8716 vBIT(val, 0, 2) 8717#define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_2_XGMAC_NMB_IO_BANK1_FUSE(val)\ 8718 vBIT(val, 2, 6) 8719#define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_2_XGMAC_NMB_IO_BANK1_ADD_FUSE(val)\ 8720 vBIT(val, 8, 2) 8721#define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_2_XGMAC_NMB_IO_BANK0_FUSE(val)\ 8722 vBIT(val, 10, 6) 8723#define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_2_XGMAC_NMB_IO_BANK0_ADD_FUSE(val)\ 8724 vBIT(val, 16, 2) 8725/* 0x08de8 */ u64 rr_rmac_da_lkp_rtl_top_3; 8726#define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_3_XGMAC_NMB_IO_REPAIR_STATUS(val)\ 8727 vBIT(val, 0, 2) 8728#define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_3_XGMAC_NMB_IO_BANK1_FUSE(val)\ 8729 vBIT(val, 2, 6) 8730#define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_3_XGMAC_NMB_IO_BANK1_ADD_FUSE(val)\ 8731 vBIT(val, 8, 2) 8732#define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_3_XGMAC_NMB_IO_BANK0_FUSE(val)\ 8733 vBIT(val, 10, 6) 8734#define VXGE_HAL_RR_RMAC_DA_LKP_RTL_TOP_3_XGMAC_NMB_IO_BANK0_ADD_FUSE(val)\ 8735 vBIT(val, 16, 2) 8736/* 0x08df0 */ u64 rr_rmac_pn_lkp_d_rtl_top; 8737#define VXGE_HAL_RR_RMAC_PN_LKP_D_RTL_TOP_XGMAC_NMB_IO_REPAIR_STATUS(val)\ 8738 vBIT(val, 0, 2) 8739#define VXGE_HAL_RR_RMAC_PN_LKP_D_RTL_TOP_XGMAC_NMB_IO_BANK1_FUSE(val)\ 8740 vBIT(val, 2, 7) 8741#define VXGE_HAL_RR_RMAC_PN_LKP_D_RTL_TOP_XGMAC_NMB_IO_BANK1_ADD_FUSE(val)\ 8742 vBIT(val, 9, 2) 8743#define VXGE_HAL_RR_RMAC_PN_LKP_D_RTL_TOP_XGMAC_NMB_IO_BANK0_FUSE(val)\ 8744 vBIT(val, 11, 7) 8745#define VXGE_HAL_RR_RMAC_PN_LKP_D_RTL_TOP_XGMAC_NMB_IO_BANK0_ADD_FUSE(val)\ 8746 vBIT(val, 18, 2) 8747/* 0x08df8 */ u64 rf_rmac_pn_lkp_s_rtl_top_0; 8748#define VXGE_HAL_RF_RMAC_PN_LKP_S_RTL_TOP_0_XGMAC_NMB_IO_REPAIR_STATUS(val)\ 8749 vBIT(val, 0, 2) 8750#define VXGE_HAL_RF_RMAC_PN_LKP_S_RTL_TOP_0_XGMAC_NMB_IO_ALL_FUSE(val)\ 8751 vBIT(val, 2, 7) 8752/* 0x08e00 */ u64 rf_rmac_pn_lkp_s_rtl_top_1; 8753#define VXGE_HAL_RF_RMAC_PN_LKP_S_RTL_TOP_1_XGMAC_NMB_IO_REPAIR_STATUS(val)\ 8754 vBIT(val, 0, 2) 8755#define VXGE_HAL_RF_RMAC_PN_LKP_S_RTL_TOP_1_XGMAC_NMB_IO_ALL_FUSE(val)\ 8756 vBIT(val, 2, 7) 8757/* 0x08e08 */ u64 rf_rmac_rth_lkp_rtl_top_0_0; 8758#define VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_0_0_XGMAC_NMB_IO_REPAIR_STATUS(val)\ 8759 vBIT(val, 0, 2) 8760#define VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_0_0_XGMAC_NMB_IO_ALL_FUSE(val)\ 8761 vBIT(val, 2, 8) 8762/* 0x08e10 */ u64 rf_rmac_rth_lkp_rtl_top_1_0; 8763#define VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_1_0_XGMAC_NMB_IO_REPAIR_STATUS(val)\ 8764 vBIT(val, 0, 2) 8765#define VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_1_0_XGMAC_NMB_IO_ALL_FUSE(val)\ 8766 vBIT(val, 2, 8) 8767/* 0x08e18 */ u64 rf_rmac_rth_lkp_rtl_top_0_1; 8768#define VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_0_1_XGMAC_NMB_IO_REPAIR_STATUS(val)\ 8769 vBIT(val, 0, 2) 8770#define VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_0_1_XGMAC_NMB_IO_ALL_FUSE(val)\ 8771 vBIT(val, 2, 8) 8772/* 0x08e20 */ u64 rf_rmac_rth_lkp_rtl_top_1_1; 8773#define VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_1_1_XGMAC_NMB_IO_REPAIR_STATUS(val)\ 8774 vBIT(val, 0, 2) 8775#define VXGE_HAL_RF_RMAC_RTH_LKP_RTL_TOP_1_1_XGMAC_NMB_IO_ALL_FUSE(val)\ 8776 vBIT(val, 2, 8) 8777/* 0x08e28 */ u64 rf_rmac_ds_lkp_rtl_top; 8778#define VXGE_HAL_RF_RMAC_DS_LKP_RTL_TOP_XGMAC_NMB_IO_REPAIR_STATUS(val)\ 8779 vBIT(val, 0, 2) 8780#define VXGE_HAL_RF_RMAC_DS_LKP_RTL_TOP_XGMAC_NMB_IO_ALL_FUSE(val)\ 8781 vBIT(val, 2, 6) 8782/* 0x08e30 */ u64 rf_rmac_rts_part_rtl_top_0_rmac0; 8783#define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_0_RMAC0_XGMAC_NMB_IO_REP_STATUS(val)\ 8784 vBIT(val, 0, 2) 8785#define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_0_RMAC0_XGMAC_NMB_IO_ALL_FUSE(val)\ 8786 vBIT(val, 2, 8) 8787/* 0x08e38 */ u64 rf_rmac_rts_part_rtl_top_1_rmac0; 8788#define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_1_RMAC0_XGMAC_NMB_IO_REP_STATUS(val)\ 8789 vBIT(val, 0, 2) 8790#define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_1_RMAC0_XGMAC_NMB_IO_ALL_FUSE(val)\ 8791 vBIT(val, 2, 8) 8792/* 0x08e40 */ u64 rf_rmac_rts_part_rtl_top_0_rmac1; 8793#define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_0_RMAC1_XGMAC_NMB_IO_REP_STATUS(val)\ 8794 vBIT(val, 0, 2) 8795#define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_0_RMAC1_XGMAC_NMB_IO_ALL_FUSE(val)\ 8796 vBIT(val, 2, 8) 8797/* 0x08e48 */ u64 rf_rmac_rts_part_rtl_top_1_rmac1; 8798#define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_1_RMAC1_XGMAC_NMB_IO_REP_STATUS(val)\ 8799 vBIT(val, 0, 2) 8800#define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_1_RMAC1_XGMAC_NMB_IO_ALL_FUSE(val)\ 8801 vBIT(val, 2, 8) 8802/* 0x08e50 */ u64 rf_rmac_rts_part_rtl_top_0_rmac2; 8803#define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_0_RMAC2_XGMAC_NMB_IO_REP_STATUS(val)\ 8804 vBIT(val, 0, 2) 8805#define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_0_RMAC2_XGMAC_NMB_IO_ALL_FUSE(val)\ 8806 vBIT(val, 2, 8) 8807/* 0x08e58 */ u64 rf_rmac_rts_part_rtl_top_1_rmac2; 8808#define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_1_RMAC2_XGMAC_NMB_IO_REP_STATUS(val)\ 8809 vBIT(val, 0, 2) 8810#define VXGE_HAL_RF_RMAC_RTS_PART_RTL_TOP_1_RMAC2_XGMAC_NMB_IO_ALL_FUSE(val)\ 8811 vBIT(val, 2, 8) 8812/* 0x08e60 */ u64 rf_rmac_rth_mask_rtl_top_0; 8813#define VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_0_XGMAC_NMB_IO_REPAIR_STATUS(val)\ 8814 vBIT(val, 0, 2) 8815#define VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_0_XGMAC_NMB_IO_ALL_FUSE(val)\ 8816 vBIT(val, 2, 8) 8817/* 0x08e68 */ u64 rf_rmac_rth_mask_rtl_top_1; 8818#define VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_1_XGMAC_NMB_IO_REPAIR_STATUS(val)\ 8819 vBIT(val, 0, 2) 8820#define VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_1_XGMAC_NMB_IO_ALL_FUSE(val)\ 8821 vBIT(val, 2, 8) 8822/* 0x08e70 */ u64 rf_rmac_rth_mask_rtl_top_2; 8823#define VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_2_XGMAC_NMB_IO_REPAIR_STATUS(val)\ 8824 vBIT(val, 0, 2) 8825#define VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_2_XGMAC_NMB_IO_ALL_FUSE(val)\ 8826 vBIT(val, 2, 8) 8827/* 0x08e78 */ u64 rf_rmac_rth_mask_rtl_top_3; 8828#define VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_3_XGMAC_NMB_IO_REPAIR_STATUS(val)\ 8829 vBIT(val, 0, 2) 8830#define VXGE_HAL_RF_RMAC_RTH_MASK_RTL_TOP_3_XGMAC_NMB_IO_ALL_FUSE(val)\ 8831 vBIT(val, 2, 8) 8832/* 0x08e80 */ u64 rf_rmac_vid_lkp_rtl_top_0; 8833#define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_0_XGMAC_NMB_IO_REPAIR_STATUS(val)\ 8834 vBIT(val, 0, 2) 8835#define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_0_XGMAC_NMB_IO_ALL_FUSE(val)\ 8836 vBIT(val, 2, 6) 8837/* 0x08e88 */ u64 rf_rmac_vid_lkp_rtl_top_1; 8838#define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_1_XGMAC_NMB_IO_REPAIR_STATUS(val)\ 8839 vBIT(val, 0, 2) 8840#define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_1_XGMAC_NMB_IO_ALL_FUSE(val)\ 8841 vBIT(val, 2, 6) 8842/* 0x08e90 */ u64 rf_rmac_vid_lkp_rtl_top_2; 8843#define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_2_XGMAC_NMB_IO_REPAIR_STATUS(val)\ 8844 vBIT(val, 0, 2) 8845#define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_2_XGMAC_NMB_IO_ALL_FUSE(val)\ 8846 vBIT(val, 2, 6) 8847/* 0x08e98 */ u64 rf_rmac_vid_lkp_rtl_top_3; 8848#define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_3_XGMAC_NMB_IO_REPAIR_STATUS(val)\ 8849 vBIT(val, 0, 2) 8850#define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_3_XGMAC_NMB_IO_ALL_FUSE(val)\ 8851 vBIT(val, 2, 6) 8852/* 0x08ea0 */ u64 rf_rmac_vid_lkp_rtl_top_4; 8853#define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_4_XGMAC_NMB_IO_REPAIR_STATUS(val)\ 8854 vBIT(val, 0, 2) 8855#define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_4_XGMAC_NMB_IO_ALL_FUSE(val)\ 8856 vBIT(val, 2, 6) 8857/* 0x08ea8 */ u64 rf_rmac_vid_lkp_rtl_top_5; 8858#define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_5_XGMAC_NMB_IO_REPAIR_STATUS(val)\ 8859 vBIT(val, 0, 2) 8860#define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_5_XGMAC_NMB_IO_ALL_FUSE(val)\ 8861 vBIT(val, 2, 6) 8862/* 0x08eb0 */ u64 rf_rmac_vid_lkp_rtl_top_6; 8863#define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_6_XGMAC_NMB_IO_REPAIR_STATUS(val)\ 8864 vBIT(val, 0, 2) 8865#define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_6_XGMAC_NMB_IO_ALL_FUSE(val)\ 8866 vBIT(val, 2, 6) 8867/* 0x08eb8 */ u64 rf_rmac_vid_lkp_rtl_top_7; 8868#define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_7_XGMAC_NMB_IO_REPAIR_STATUS(val)\ 8869 vBIT(val, 0, 2) 8870#define VXGE_HAL_RF_RMAC_VID_LKP_RTL_TOP_7_XGMAC_NMB_IO_ALL_FUSE(val)\ 8871 vBIT(val, 2, 6) 8872/* 0x08ec0 */ u64 rf_rmac_stats_rtl_top_0_stats_0; 8873#define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_0_XGMAC_NMB_IO_REP_STATUS(val)\ 8874 vBIT(val, 0, 2) 8875#define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_0_XGMAC_NMB_IO_ALL_FUSE(val)\ 8876 vBIT(val, 2, 7) 8877/* 0x08ec8 */ u64 rf_rmac_stats_rtl_top_1_stats_0; 8878#define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_0_XGMAC_NMB_IO_REP_STATUS(val)\ 8879 vBIT(val, 0, 2) 8880#define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_0_XGMAC_NMB_IO_ALL_FUSE(val)\ 8881 vBIT(val, 2, 7) 8882/* 0x08ed0 */ u64 rf_rmac_stats_rtl_top_0_stats_1; 8883#define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_1_XGMAC_NMB_IO_REP_STATUS(val)\ 8884 vBIT(val, 0, 2) 8885#define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_1_XGMAC_NMB_IO_ALL_FUSE(val)\ 8886 vBIT(val, 2, 7) 8887/* 0x08ed8 */ u64 rf_rmac_stats_rtl_top_1_stats_1; 8888#define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_1_XGMAC_NMB_IO_REP_STATUS(val)\ 8889 vBIT(val, 0, 2) 8890#define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_1_XGMAC_NMB_IO_ALL_FUSE(val)\ 8891 vBIT(val, 2, 7) 8892/* 0x08ee0 */ u64 rf_rmac_stats_rtl_top_0_stats_2; 8893#define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_2_XGMAC_NMB_IO_REP_STATUS(val)\ 8894 vBIT(val, 0, 2) 8895#define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_2_XGMAC_NMB_IO_ALL_FUSE(val)\ 8896 vBIT(val, 2, 7) 8897/* 0x08ee8 */ u64 rf_rmac_stats_rtl_top_1_stats_2; 8898#define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_2_XGMAC_NMB_IO_REP_STATUS(val)\ 8899 vBIT(val, 0, 2) 8900#define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_2_XGMAC_NMB_IO_ALL_FUSE(val)\ 8901 vBIT(val, 2, 7) 8902/* 0x08ef0 */ u64 rf_rmac_stats_rtl_top_0_stats_3; 8903#define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_3_XGMAC_NMB_IO_REP_STATUS(val)\ 8904 vBIT(val, 0, 2) 8905#define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_3_XGMAC_NMB_IO_ALL_FUSE(val)\ 8906 vBIT(val, 2, 7) 8907/* 0x08ef8 */ u64 rf_rmac_stats_rtl_top_1_stats_3; 8908#define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_3_XGMAC_NMB_IO_REP_STATUS(val)\ 8909 vBIT(val, 0, 2) 8910#define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_3_XGMAC_NMB_IO_ALL_FUSE(val)\ 8911 vBIT(val, 2, 7) 8912/* 0x08f00 */ u64 rf_rmac_stats_rtl_top_0_stats_4; 8913#define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_4_XGMAC_NMB_IO_REP_STATUS(val)\ 8914 vBIT(val, 0, 2) 8915#define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_0_STATS_4_XGMAC_NMB_IO_ALL_FUSE(val)\ 8916 vBIT(val, 2, 7) 8917/* 0x08f08 */ u64 rf_rmac_stats_rtl_top_1_stats_4; 8918#define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_4_XGMAC_NMB_IO_REP_STATUS(val)\ 8919 vBIT(val, 0, 2) 8920#define VXGE_HAL_RF_RMAC_STATS_RTL_TOP_1_STATS_4_XGMAC_NMB_IO_ALL_FUSE(val)\ 8921 vBIT(val, 2, 7) 8922 u8 unused09000[0x09000 - 0x08f10]; 8923 8924/* 0x09000 */ u64 g3ifcmd_fb_int_status; 8925#define VXGE_HAL_G3IFCMD_FB_INT_STATUS_ERR_G3IF_INT mBIT(0) 8926/* 0x09008 */ u64 g3ifcmd_fb_int_mask; 8927/* 0x09010 */ u64 g3ifcmd_fb_err_reg; 8928#define VXGE_HAL_G3IFCMD_FB_ERR_REG_G3IF_CK_DLL_LOCK mBIT(6) 8929#define VXGE_HAL_G3IFCMD_FB_ERR_REG_G3IF_SM_ERR mBIT(7) 8930#define VXGE_HAL_G3IFCMD_FB_ERR_REG_G3IF_RWDQS_DLL_LOCK(val) vBIT(val, 24, 8) 8931#define VXGE_HAL_G3IFCMD_FB_ERR_REG_G3IF_IOCAL_FAULT mBIT(55) 8932/* 0x09018 */ u64 g3ifcmd_fb_err_mask; 8933/* 0x09020 */ u64 g3ifcmd_fb_err_alarm; 8934/* 0x09028 */ u64 g3ifcmd_fb_dll_ck0; 8935#define VXGE_HAL_G3IFCMD_FB_DLL_CK0_DLL_0_SA_CAL(val) vBIT(val, 0, 8) 8936#define VXGE_HAL_G3IFCMD_FB_DLL_CK0_DLL_0_SB_CAL(val) vBIT(val, 8, 8) 8937#define VXGE_HAL_G3IFCMD_FB_DLL_CK0_ROLL mBIT(23) 8938#define VXGE_HAL_G3IFCMD_FB_DLL_CK0_CMD_ADD_DLL_0_S(val) vBIT(val, 25, 7) 8939#define VXGE_HAL_G3IFCMD_FB_DLL_CK0_DLL_ENABLE mBIT(39) 8940#define VXGE_HAL_G3IFCMD_FB_DLL_CK0_DLL_UPD(val) vBIT(val, 44, 4) 8941/* 0x09030 */ u64 g3ifcmd_fb_io_ctrl; 8942#define VXGE_HAL_G3IFCMD_FB_IO_CTRL_DRIVE mBIT(7) 8943#define VXGE_HAL_G3IFCMD_FB_IO_CTRL_TERM(val) vBIT(val, 13, 3) 8944/* 0x09038 */ u64 g3ifcmd_fb_iocal; 8945#define VXGE_HAL_G3IFCMD_FB_IOCAL_RST_CYCLES(val) vBIT(val, 0, 16) 8946#define VXGE_HAL_G3IFCMD_FB_IOCAL_RST_VALUE(val) vBIT(val, 17, 7) 8947#define VXGE_HAL_G3IFCMD_FB_IOCAL_CORR_VALUE(val) vBIT(val, 24, 8) 8948#define VXGE_HAL_G3IFCMD_FB_IOCAL_IOCAL_CTRL_CAL_VALUE0(val) vBIT(val, 33, 7) 8949#define VXGE_HAL_G3IFCMD_FB_IOCAL_IOCAL_CTRL_CAL_VALUE1(val) vBIT(val, 41, 7) 8950#define VXGE_HAL_G3IFCMD_FB_IOCAL_IOCAL_CTRL_CAL_VALUE2(val) vBIT(val, 49, 7) 8951#define VXGE_HAL_G3IFCMD_FB_IOCAL_IOCAL_CTRL_CAL_VALUE3(val) vBIT(val, 57, 7) 8952/* 0x09040 */ u64 g3ifcmd_fb_master_dll_ck; 8953#define VXGE_HAL_G3IFCMD_FB_MASTER_DLL_CK_DDR_GR_RAW(val) vBIT(val, 1, 7) 8954#define VXGE_HAL_G3IFCMD_FB_MASTER_DLL_CK_SAMPLE(val) vBIT(val, 8, 8) 8955/* 0x09048 */ u64 g3ifcmd_fb_dll_training; 8956#define VXGE_HAL_G3IFCMD_FB_DLL_TRAINING_TRA_START mBIT(6) 8957#define VXGE_HAL_G3IFCMD_FB_DLL_TRAINING_TRA_DISABLE mBIT(7) 8958#define VXGE_HAL_G3IFCMD_FB_DLL_TRAINING_START_CODE(val) vBIT(val, 9, 7) 8959#define VXGE_HAL_G3IFCMD_FB_DLL_TRAINING_END_CODE(val) vBIT(val, 17, 7) 8960 u8 unused09110[0x09110 - 0x09050]; 8961 8962/* 0x09110 */ u64 g3ifgr01_fb_group0_dll_rdqs; 8963#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8) 8964#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8) 8965#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8) 8966#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8) 8967#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7) 8968/* 0x09118 */ u64 g3ifgr01_fb_group0_dll_rdqs1; 8969#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS1_ROLL mBIT(7) 8970#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS1_DLL_ENABLE mBIT(14) 8971#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15) 8972#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3) 8973/* 0x09120 */ u64 g3ifgr01_fb_group0_dll_wdqs; 8974#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8) 8975#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8) 8976#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7) 8977/* 0x09128 */ u64 g3ifgr01_fb_group0_dll_wdqs1; 8978#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_WDQS1_ROLL mBIT(7) 8979#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_WDQS1_DLL_ENABLE mBIT(15) 8980#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3) 8981#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_WDQS1_SEL_MASTER_WDQS_CKN mBIT(31) 8982/* 0x09130 */ u64 g3ifgr01_fb_group0_dll_training1; 8983#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING1_DDR_TRA_STATUS(val)\ 8984 vBIT(val, 4, 4) 8985#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING1_DDR_TRA_MIN(val)\ 8986 vBIT(val, 9, 7) 8987#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING1_DDR_TRA_MAX(val)\ 8988 vBIT(val, 17, 7) 8989#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING1_DDR_ATRA_STATUS(val)\ 8990 vBIT(val, 36, 4) 8991#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING1_DDR_ATRA_MIN(val)\ 8992 vBIT(val, 41, 7) 8993#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING1_DDR_ATRA_MAX(val)\ 8994 vBIT(val, 49, 7) 8995/* 0x09138 */ u64 g3ifgr01_fb_group0_dll_training2; 8996#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\ 8997 vBIT(val, 0, 32) 8998#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\ 8999 vBIT(val, 32, 16) 9000#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\ 9001 vBIT(val, 48, 16) 9002/* 0x09140 */ u64 g3ifgr01_fb_group0_dll_training3; 9003#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING3_DLL_TRA_DATA00(val)\ 9004 vBIT(val, 0, 16) 9005#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING3_DLL_TRA_DATA01(val)\ 9006 vBIT(val, 16, 16) 9007/* 0x09148 */ u64 g3ifgr01_fb_group0_dll_act_training5; 9008#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ACT_TRAINING5_START_CODE(val)\ 9009 vBIT(val, 1, 7) 9010#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ACT_TRAINING5_END_CODE(val)\ 9011 vBIT(val, 9, 7) 9012#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ACT_TRAINING5_DISABLE mBIT(23) 9013#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ACT_TRAINING5_TCNT(val)\ 9014 vBIT(val, 28, 4) 9015/* 0x09150 */ u64 g3ifgr01_fb_group0_dll_training6; 9016#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING6_DLL_TRA_EN_HALF_EYE_VALID\ 9017 mBIT(7) 9018#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING6_DLL_ATRA_EN_HALF_EYE_VALID\ 9019 mBIT(15) 9020#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING6_DLL_TRA_EN_MASTER_CORR\ 9021 mBIT(23) 9022#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING6_DLL_ATRA_EN_MASTER_CORR\ 9023 mBIT(31) 9024#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39) 9025#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47) 9026/* 0x09158 */ u64 g3ifgr01_fb_group0_dll_atra_offset; 9027#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_OFFSET_EQUATION(val)\ 9028 vBIT(val, 6, 2) 9029#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_OFFSET_DDR_VALUE(val)\ 9030 vBIT(val, 8, 8) 9031/* 0x09160 */ u64 g3ifgr01_fb_group0_dll_tra_hold; 9032#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\ 9033 vBIT(val, 1, 7) 9034#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\ 9035 vBIT(val, 9, 7) 9036#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRA_HOLD_DDR_TIME(val)\ 9037 vBIT(val, 16, 24) 9038#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_TRA_HOLD_DDR_UPDATES(val)\ 9039 vBIT(val, 40, 24) 9040/* 0x09168 */ u64 g3ifgr01_fb_group0_dll_atra_hold; 9041#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\ 9042 vBIT(val, 1, 7) 9043#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\ 9044 vBIT(val, 9, 7) 9045#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_HOLD_DDR_TIME(val)\ 9046 vBIT(val, 16, 24) 9047#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_HOLD_DDR_UPDATES(val)\ 9048 vBIT(val, 40, 24) 9049/* 0x09170 */ u64 g3ifgr01_fb_group0_dll_master_codes; 9050#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\ 9051 vBIT(val, 9, 7) 9052#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\ 9053 vBIT(val, 25, 7) 9054#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\ 9055 vBIT(val, 41, 7) 9056#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\ 9057 vBIT(val, 57, 7) 9058/* 0x09178 */ u64 g3ifgr01_fb_group0_dll_atra_timer; 9059#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_TIMER_VALUE(val)\ 9060 vBIT(val, 0, 16) 9061#define VXGE_HAL_G3IFGR01_FB_GROUP0_DLL_ATRA_TIMER_ENABLED mBIT(23) 9062/* 0x09180 */ u64 g3ifgr01_fb_group1_dll_rdqs; 9063#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS_SA_CAL(val)\ 9064 vBIT(val, 0, 8) 9065#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS_SB_CAL(val)\ 9066 vBIT(val, 8, 8) 9067#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS_ATRA_SA_CAL(val)\ 9068 vBIT(val, 32, 8) 9069#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS_ATRA_SB_CAL(val)\ 9070 vBIT(val, 40, 8) 9071#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS_DDR_DLL_S(val)\ 9072 vBIT(val, 57, 7) 9073/* 0x09188 */ u64 g3ifgr01_fb_group1_dll_rdqs1; 9074#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS1_ROLL mBIT(7) 9075#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS1_DLL_ENABLE mBIT(14) 9076#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15) 9077#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3) 9078/* 0x09190 */ u64 g3ifgr01_fb_group1_dll_wdqs; 9079#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8) 9080#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8) 9081#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7) 9082/* 0x09198 */ u64 g3ifgr01_fb_group1_dll_wdqs1; 9083#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_WDQS1_ROLL mBIT(7) 9084#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_WDQS1_DLL_ENABLE mBIT(15) 9085#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3) 9086#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_WDQS1_SEL_MASTER_WDQS_CKN mBIT(31) 9087/* 0x091a0 */ u64 g3ifgr01_fb_group1_dll_training1; 9088#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING1_DDR_TRA_STATUS(val)\ 9089 vBIT(val, 4, 4) 9090#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING1_DDR_TRA_MIN(val)\ 9091 vBIT(val, 9, 7) 9092#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING1_DDR_TRA_MAX(val)\ 9093 vBIT(val, 17, 7) 9094#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING1_DDR_ATRA_STATUS(val)\ 9095 vBIT(val, 36, 4) 9096#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING1_DDR_ATRA_MIN(val)\ 9097 vBIT(val, 41, 7) 9098#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING1_DDR_ATRA_MAX(val)\ 9099 vBIT(val, 49, 7) 9100/* 0x091a8 */ u64 g3ifgr01_fb_group1_dll_training2; 9101#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\ 9102 vBIT(val, 0, 32) 9103#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\ 9104 vBIT(val, 32, 16) 9105#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\ 9106 vBIT(val, 48, 16) 9107/* 0x091b0 */ u64 g3ifgr01_fb_group1_dll_training3; 9108#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING3_DLL_TRA_DATA00(val)\ 9109 vBIT(val, 0, 16) 9110#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING3_DLL_TRA_DATA01(val)\ 9111 vBIT(val, 16, 16) 9112/* 0x091b8 */ u64 g3ifgr01_fb_group1_dll_act_training5; 9113#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ACT_TRAINING5_START_CODE(val)\ 9114 vBIT(val, 1, 7) 9115#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ACT_TRAINING5_END_CODE(val)\ 9116 vBIT(val, 9, 7) 9117#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ACT_TRAINING5_DISABLE mBIT(23) 9118#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ACT_TRAINING5_TCNT(val) vBIT(val, 28, 4) 9119/* 0x091c0 */ u64 g3ifgr01_fb_group1_dll_training6; 9120#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING6_DLL_TRA_EN_HALF_EYE_VALID\ 9121 mBIT(7) 9122#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING6_DLL_ATRA_EN_HALF_EYE_VALID\ 9123 mBIT(15) 9124#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING6_DLL_TRA_EN_MASTER_CORRECTION\ 9125 mBIT(23) 9126#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING6_DLL_ATRA_EN_MASTER_CORRECTION\ 9127 mBIT(31) 9128#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39) 9129#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47) 9130/* 0x091c8 */ u64 g3ifgr01_fb_group1_dll_atra_offset; 9131#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_OFFSET_EQUATION(val)\ 9132 vBIT(val, 6, 2) 9133#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_OFFSET_DDR_VALUE(val)\ 9134 vBIT(val, 8, 8) 9135/* 0x091d0 */ u64 g3ifgr01_fb_group1_dll_tra_hold; 9136#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\ 9137 vBIT(val, 1, 7) 9138#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\ 9139 vBIT(val, 9, 7) 9140#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRA_HOLD_DDR_TIME(val)\ 9141 vBIT(val, 16, 24) 9142#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_TRA_HOLD_DDR_UPDATES(val)\ 9143 vBIT(val, 40, 24) 9144/* 0x091d8 */ u64 g3ifgr01_fb_group1_dll_atra_hold; 9145#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\ 9146 vBIT(val, 1, 7) 9147#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\ 9148 vBIT(val, 9, 7) 9149#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_HOLD_DDR_TIME(val)\ 9150 vBIT(val, 16, 24) 9151#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_HOLD_DDR_UPDATES(val)\ 9152 vBIT(val, 40, 24) 9153/* 0x091e0 */ u64 g3ifgr01_fb_group1_dll_master_codes; 9154#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\ 9155 vBIT(val, 9, 7) 9156#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\ 9157 vBIT(val, 25, 7) 9158#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\ 9159 vBIT(val, 41, 7) 9160#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\ 9161 vBIT(val, 57, 7) 9162/* 0x091e8 */ u64 g3ifgr01_fb_group1_dll_atra_timer; 9163#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16) 9164#define VXGE_HAL_G3IFGR01_FB_GROUP1_DLL_ATRA_TIMER_ENABLED mBIT(23) 9165 u8 unused09210[0x09210 - 0x091f0]; 9166 9167/* 0x09210 */ u64 g3ifgr23_fb_group2_dll_rdqs; 9168#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8) 9169#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8) 9170#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8) 9171#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8) 9172#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7) 9173/* 0x09218 */ u64 g3ifgr23_fb_group2_dll_rdqs1; 9174#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS1_ROLL mBIT(7) 9175#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS1_DLL_ENABLE mBIT(14) 9176#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15) 9177#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3) 9178/* 0x09220 */ u64 g3ifgr23_fb_group2_dll_wdqs; 9179#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8) 9180#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8) 9181#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7) 9182/* 0x09228 */ u64 g3ifgr23_fb_group2_dll_wdqs1; 9183#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_WDQS1_ROLL mBIT(7) 9184#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_WDQS1_DLL_ENABLE mBIT(15) 9185#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3) 9186#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_WDQS1_SEL_MASTER_WDQS_CKN mBIT(31) 9187/* 0x09230 */ u64 g3ifgr23_fb_group2_dll_training1; 9188#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING1_DDR_TRA_STATUS(val)\ 9189 vBIT(val, 4, 4) 9190#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING1_DDR_TRA_MIN(val)\ 9191 vBIT(val, 9, 7) 9192#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING1_DDR_TRA_MAX(val)\ 9193 vBIT(val, 17, 7) 9194#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING1_DDR_ATRA_STATUS(val)\ 9195 vBIT(val, 36, 4) 9196#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING1_DDR_ATRA_MIN(val)\ 9197 vBIT(val, 41, 7) 9198#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING1_DDR_ATRA_MAX(val)\ 9199 vBIT(val, 49, 7) 9200/* 0x09238 */ u64 g3ifgr23_fb_group2_dll_training2; 9201#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\ 9202 vBIT(val, 0, 32) 9203#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\ 9204 vBIT(val, 32, 16) 9205#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\ 9206 vBIT(val, 48, 16) 9207/* 0x09240 */ u64 g3ifgr23_fb_group2_dll_training3; 9208#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING3_DLL_TRA_DATA00(val)\ 9209 vBIT(val, 0, 16) 9210#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING3_DLL_TRA_DATA01(val)\ 9211 vBIT(val, 16, 16) 9212/* 0x09248 */ u64 g3ifgr23_fb_group2_dll_act_training5; 9213#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ACT_TRAINING5_START_CODE(val)\ 9214 vBIT(val, 1, 7) 9215#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ACT_TRAINING5_END_CODE(val)\ 9216 vBIT(val, 9, 7) 9217#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ACT_TRAINING5_DISABLE mBIT(23) 9218#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ACT_TRAINING5_TCNT(val)\ 9219 vBIT(val, 28, 4) 9220/* 0x09250 */ u64 g3ifgr23_fb_group2_dll_training6; 9221#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING6_DLL_TRA_EN_HALF_EYE_VALID\ 9222 mBIT(7) 9223#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING6_DLL_ATRA_EN_HALF_EYE_VALID\ 9224 mBIT(15) 9225#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING6_DLL_TRA_EN_MASTER_CORRECTION\ 9226 mBIT(23) 9227#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING6_DLL_ATRA_EN_MASTER_CORRECTION\ 9228 mBIT(31) 9229#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39) 9230#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47) 9231/* 0x09258 */ u64 g3ifgr23_fb_group2_dll_atra_offset; 9232#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_OFFSET_EQUATION(val)\ 9233 vBIT(val, 6, 2) 9234#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_OFFSET_DDR_VALUE(val)\ 9235 vBIT(val, 8, 8) 9236/* 0x09260 */ u64 g3ifgr23_fb_group2_dll_tra_hold; 9237#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\ 9238 vBIT(val, 1, 7) 9239#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\ 9240 vBIT(val, 9, 7) 9241#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRA_HOLD_DDR_TIME(val)\ 9242 vBIT(val, 16, 24) 9243#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_TRA_HOLD_DDR_UPDATES(val)\ 9244 vBIT(val, 40, 24) 9245/* 0x09268 */ u64 g3ifgr23_fb_group2_dll_atra_hold; 9246#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\ 9247 vBIT(val, 1, 7) 9248#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\ 9249 vBIT(val, 9, 7) 9250#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_HOLD_DDR_TIME(val)\ 9251 vBIT(val, 16, 24) 9252#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_HOLD_DDR_UPDATES(val)\ 9253 vBIT(val, 40, 24) 9254/* 0x09270 */ u64 g3ifgr23_fb_group2_dll_master_codes; 9255#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\ 9256 vBIT(val, 9, 7) 9257#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\ 9258 vBIT(val, 25, 7) 9259#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\ 9260 vBIT(val, 41, 7) 9261#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\ 9262 vBIT(val, 57, 7) 9263/* 0x09278 */ u64 g3ifgr23_fb_group2_dll_atra_timer; 9264#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16) 9265#define VXGE_HAL_G3IFGR23_FB_GROUP2_DLL_ATRA_TIMER_ENABLED mBIT(23) 9266/* 0x09280 */ u64 g3ifgr23_fb_group3_dll_rdqs; 9267#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8) 9268#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8) 9269#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8) 9270#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8) 9271#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7) 9272/* 0x09288 */ u64 g3ifgr23_fb_group3_dll_rdqs1; 9273#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS1_ROLL mBIT(7) 9274#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS1_DLL_ENABLE mBIT(14) 9275#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15) 9276#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3) 9277/* 0x09290 */ u64 g3ifgr23_fb_group3_dll_wdqs; 9278#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8) 9279#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8) 9280#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7) 9281/* 0x09298 */ u64 g3ifgr23_fb_group3_dll_wdqs1; 9282#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_WDQS1_ROLL mBIT(7) 9283#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_WDQS1_DLL_ENABLE mBIT(15) 9284#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3) 9285#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_WDQS1_SEL_MASTER_WDQS_CKN mBIT(31) 9286/* 0x092a0 */ u64 g3ifgr23_fb_group3_dll_training1; 9287#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING1_DDR_TRA_STATUS(val)\ 9288 vBIT(val, 4, 4) 9289#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING1_DDR_TRA_MIN(val)\ 9290 vBIT(val, 9, 7) 9291#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING1_DDR_TRA_MAX(val)\ 9292 vBIT(val, 17, 7) 9293#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING1_DDR_ATRA_STATUS(val)\ 9294 vBIT(val, 36, 4) 9295#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING1_DDR_ATRA_MIN(val)\ 9296 vBIT(val, 41, 7) 9297#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING1_DDR_ATRA_MAX(val)\ 9298 vBIT(val, 49, 7) 9299/* 0x092a8 */ u64 g3ifgr23_fb_group3_dll_training2; 9300#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\ 9301 vBIT(val, 0, 32) 9302#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\ 9303 vBIT(val, 32, 16) 9304#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\ 9305 vBIT(val, 48, 16) 9306/* 0x092b0 */ u64 g3ifgr23_fb_group3_dll_training3; 9307#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING3_DLL_TRA_DATA00(val)\ 9308 vBIT(val, 0, 16) 9309#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING3_DLL_TRA_DATA01(val)\ 9310 vBIT(val, 16, 16) 9311/* 0x092b8 */ u64 g3ifgr23_fb_group3_dll_act_training5; 9312#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ACT_TRAINING5_START_CODE(val)\ 9313 vBIT(val, 1, 7) 9314#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ACT_TRAINING5_END_CODE(val)\ 9315 vBIT(val, 9, 7) 9316#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ACT_TRAINING5_DISABLE mBIT(23) 9317#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ACT_TRAINING5_TCNT(val) vBIT(val, 28, 4) 9318/* 0x092c0 */ u64 g3ifgr23_fb_group3_dll_training6; 9319#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING6_DLL_TRA_EN_HALF_EYE_VALID\ 9320 mBIT(7) 9321#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING6_DLL_ATRA_EN_HALF_EYE_VALID\ 9322 mBIT(15) 9323#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING6_DLL_TRA_EN_MASTER_CORRECTION\ 9324 mBIT(23) 9325#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING6_DLL_ATRA_EN_MASTER_CORRECTION\ 9326 mBIT(31) 9327#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39) 9328#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47) 9329/* 0x092c8 */ u64 g3ifgr23_fb_group3_dll_atra_offset; 9330#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_OFFSET_EQUATION(val)\ 9331 vBIT(val, 6, 2) 9332#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_OFFSET_DDR_VALUE(val)\ 9333 vBIT(val, 8, 8) 9334/* 0x092d0 */ u64 g3ifgr23_fb_group3_dll_tra_hold; 9335#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\ 9336 vBIT(val, 1, 7) 9337#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\ 9338 vBIT(val, 9, 7) 9339#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRA_HOLD_DDR_TIME(val)\ 9340 vBIT(val, 16, 24) 9341#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_TRA_HOLD_DDR_UPDATES(val)\ 9342 vBIT(val, 40, 24) 9343/* 0x092d8 */ u64 g3ifgr23_fb_group3_dll_atra_hold; 9344#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\ 9345 vBIT(val, 1, 7) 9346#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\ 9347 vBIT(val, 9, 7) 9348#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_HOLD_DDR_TIME(val)\ 9349 vBIT(val, 16, 24) 9350#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_HOLD_DDR_UPDATES(val)\ 9351 vBIT(val, 40, 24) 9352/* 0x092e0 */ u64 g3ifgr23_fb_group3_dll_master_codes; 9353#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\ 9354 vBIT(val, 9, 7) 9355#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\ 9356 vBIT(val, 25, 7) 9357#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\ 9358 vBIT(val, 41, 7) 9359#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\ 9360 vBIT(val, 57, 7) 9361/* 0x092e8 */ u64 g3ifgr23_fb_group3_dll_atra_timer; 9362#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16) 9363#define VXGE_HAL_G3IFGR23_FB_GROUP3_DLL_ATRA_TIMER_ENABLED mBIT(23) 9364 u8 unused09400[0x09400 - 0x092f0]; 9365 9366/* 0x09400 */ u64 g3ifcmd_cmu_int_status; 9367#define VXGE_HAL_G3IFCMD_CMU_INT_STATUS_ERR_G3IF_INT mBIT(0) 9368/* 0x09408 */ u64 g3ifcmd_cmu_int_mask; 9369/* 0x09410 */ u64 g3ifcmd_cmu_err_reg; 9370#define VXGE_HAL_G3IFCMD_CMU_ERR_REG_G3IF_CK_DLL_LOCK mBIT(6) 9371#define VXGE_HAL_G3IFCMD_CMU_ERR_REG_G3IF_SM_ERR mBIT(7) 9372#define VXGE_HAL_G3IFCMD_CMU_ERR_REG_G3IF_RWDQS_DLL_LOCK(val) vBIT(val, 24, 8) 9373#define VXGE_HAL_G3IFCMD_CMU_ERR_REG_G3IF_IOCAL_FAULT mBIT(55) 9374/* 0x09418 */ u64 g3ifcmd_cmu_err_mask; 9375/* 0x09420 */ u64 g3ifcmd_cmu_err_alarm; 9376/* 0x09428 */ u64 g3ifcmd_cmu_dll_ck0; 9377#define VXGE_HAL_G3IFCMD_CMU_DLL_CK0_DLL_0_SA_CAL(val) vBIT(val, 0, 8) 9378#define VXGE_HAL_G3IFCMD_CMU_DLL_CK0_DLL_0_SB_CAL(val) vBIT(val, 8, 8) 9379#define VXGE_HAL_G3IFCMD_CMU_DLL_CK0_ROLL mBIT(23) 9380#define VXGE_HAL_G3IFCMD_CMU_DLL_CK0_CMD_ADD_DLL_0_S(val) vBIT(val, 25, 7) 9381#define VXGE_HAL_G3IFCMD_CMU_DLL_CK0_DLL_ENABLE mBIT(39) 9382#define VXGE_HAL_G3IFCMD_CMU_DLL_CK0_DLL_UPD(val) vBIT(val, 44, 4) 9383/* 0x09430 */ u64 g3ifcmd_cmu_io_ctrl; 9384#define VXGE_HAL_G3IFCMD_CMU_IO_CTRL_DRIVE mBIT(7) 9385#define VXGE_HAL_G3IFCMD_CMU_IO_CTRL_TERM(val) vBIT(val, 13, 3) 9386/* 0x09438 */ u64 g3ifcmd_cmu_iocal; 9387#define VXGE_HAL_G3IFCMD_CMU_IOCAL_RST_CYCLES(val) vBIT(val, 0, 16) 9388#define VXGE_HAL_G3IFCMD_CMU_IOCAL_RST_VALUE(val) vBIT(val, 17, 7) 9389#define VXGE_HAL_G3IFCMD_CMU_IOCAL_CORR_VALUE(val) vBIT(val, 24, 8) 9390#define VXGE_HAL_G3IFCMD_CMU_IOCAL_IOCAL_CTRL_CAL_VALUE0(val) vBIT(val, 33, 7) 9391#define VXGE_HAL_G3IFCMD_CMU_IOCAL_IOCAL_CTRL_CAL_VALUE1(val) vBIT(val, 41, 7) 9392#define VXGE_HAL_G3IFCMD_CMU_IOCAL_IOCAL_CTRL_CAL_VALUE2(val) vBIT(val, 49, 7) 9393#define VXGE_HAL_G3IFCMD_CMU_IOCAL_IOCAL_CTRL_CAL_VALUE3(val) vBIT(val, 57, 7) 9394/* 0x09440 */ u64 g3ifcmd_cmu_master_dll_ck; 9395#define VXGE_HAL_G3IFCMD_CMU_MASTER_DLL_CK_DDR_GR_RAW(val) vBIT(val, 1, 7) 9396#define VXGE_HAL_G3IFCMD_CMU_MASTER_DLL_CK_SAMPLE(val) vBIT(val, 8, 8) 9397/* 0x09448 */ u64 g3ifcmd_cmu_dll_training; 9398#define VXGE_HAL_G3IFCMD_CMU_DLL_TRAINING_TRA_START mBIT(6) 9399#define VXGE_HAL_G3IFCMD_CMU_DLL_TRAINING_TRA_DISABLE mBIT(7) 9400#define VXGE_HAL_G3IFCMD_CMU_DLL_TRAINING_START_CODE(val) vBIT(val, 9, 7) 9401#define VXGE_HAL_G3IFCMD_CMU_DLL_TRAINING_END_CODE(val) vBIT(val, 17, 7) 9402 u8 unused09510[0x09510 - 0x09450]; 9403 9404/* 0x09510 */ u64 g3ifgr01_cmu_group0_dll_rdqs; 9405#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8) 9406#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8) 9407#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8) 9408#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8) 9409#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7) 9410/* 0x09518 */ u64 g3ifgr01_cmu_group0_dll_rdqs1; 9411#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS1_ROLL mBIT(7) 9412#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS1_DLL_ENABLE mBIT(14) 9413#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15) 9414#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3) 9415/* 0x09520 */ u64 g3ifgr01_cmu_group0_dll_wdqs; 9416#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8) 9417#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8) 9418#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7) 9419/* 0x09528 */ u64 g3ifgr01_cmu_group0_dll_wdqs1; 9420#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_WDQS1_ROLL mBIT(7) 9421#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_WDQS1_DLL_ENABLE mBIT(15) 9422#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3) 9423#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_WDQS1_SEL_MASTER_WDQS_CKN\ 9424 mBIT(31) 9425/* 0x09530 */ u64 g3ifgr01_cmu_group0_dll_training1; 9426#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING1_DDR_TRA_STATUS(val)\ 9427 vBIT(val, 4, 4) 9428#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING1_DDR_TRA_MIN(val)\ 9429 vBIT(val, 9, 7) 9430#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING1_DDR_TRA_MAX(val)\ 9431 vBIT(val, 17, 7) 9432#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING1_DDR_ATRA_STATUS(val)\ 9433 vBIT(val, 36, 4) 9434#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING1_DDR_ATRA_MIN(val)\ 9435 vBIT(val, 41, 7) 9436#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING1_DDR_ATRA_MAX(val)\ 9437 vBIT(val, 49, 7) 9438/* 0x09538 */ u64 g3ifgr01_cmu_group0_dll_training2; 9439#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\ 9440 vBIT(val, 0, 32) 9441#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\ 9442 vBIT(val, 32, 16) 9443#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\ 9444 vBIT(val, 48, 16) 9445/* 0x09540 */ u64 g3ifgr01_cmu_group0_dll_training3; 9446#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING3_DLL_TRA_DATA00(val)\ 9447 vBIT(val, 0, 16) 9448#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING3_DLL_TRA_DATA01(val)\ 9449 vBIT(val, 16, 16) 9450/* 0x09548 */ u64 g3ifgr01_cmu_group0_dll_act_training5; 9451#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ACT_TRAINING5_START_CODE(val)\ 9452 vBIT(val, 1, 7) 9453#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ACT_TRAINING5_END_CODE(val)\ 9454 vBIT(val, 9, 7) 9455#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ACT_TRAINING5_DISABLE mBIT(23) 9456#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ACT_TRAINING5_TCNT(val)\ 9457 vBIT(val, 28, 4) 9458/* 0x09550 */ u64 g3ifgr01_cmu_group0_dll_training6; 9459#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING6_DLL_TRA_EN_HALF_EYE_VALID\ 9460 mBIT(7) 9461#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING6_DLL_ATRA_EN_HALF_EYE_VALID\ 9462 mBIT(15) 9463#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING6_DLL_TRA_EN_MASTER_CORR\ 9464 mBIT(23) 9465#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING6_DLL_ATRA_EN_MASTER_CORR\ 9466 mBIT(31) 9467#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39) 9468#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47) 9469/* 0x09558 */ u64 g3ifgr01_cmu_group0_dll_atra_offset; 9470#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_OFFSET_EQUATION(val)\ 9471 vBIT(val, 6, 2) 9472#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_OFFSET_DDR_VALUE(val)\ 9473 vBIT(val, 8, 8) 9474/* 0x09560 */ u64 g3ifgr01_cmu_group0_dll_tra_hold; 9475#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\ 9476 vBIT(val, 1, 7) 9477#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\ 9478 vBIT(val, 9, 7) 9479#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRA_HOLD_DDR_TIME(val)\ 9480 vBIT(val, 16, 24) 9481#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_TRA_HOLD_DDR_UPDATES(val)\ 9482 vBIT(val, 40, 24) 9483/* 0x09568 */ u64 g3ifgr01_cmu_group0_dll_atra_hold; 9484#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\ 9485 vBIT(val, 1, 7) 9486#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\ 9487 vBIT(val, 9, 7) 9488#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_HOLD_DDR_TIME(val)\ 9489 vBIT(val, 16, 24) 9490#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_HOLD_DDR_UPDATES(val)\ 9491 vBIT(val, 40, 24) 9492/* 0x09570 */ u64 g3ifgr01_cmu_group0_dll_master_codes; 9493#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\ 9494 vBIT(val, 9, 7) 9495#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\ 9496 vBIT(val, 25, 7) 9497#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\ 9498 vBIT(val, 41, 7) 9499#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\ 9500 vBIT(val, 57, 7) 9501/* 0x09578 */ u64 g3ifgr01_cmu_group0_dll_atra_timer; 9502#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16) 9503#define VXGE_HAL_G3IFGR01_CMU_GROUP0_DLL_ATRA_TIMER_ENABLED mBIT(23) 9504/* 0x09580 */ u64 g3ifgr01_cmu_group1_dll_rdqs; 9505#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8) 9506#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8) 9507#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8) 9508#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8) 9509#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7) 9510/* 0x09588 */ u64 g3ifgr01_cmu_group1_dll_rdqs1; 9511#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS1_ROLL mBIT(7) 9512#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS1_DLL_ENABLE mBIT(14) 9513#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15) 9514#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3) 9515/* 0x09590 */ u64 g3ifgr01_cmu_group1_dll_wdqs; 9516#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8) 9517#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8) 9518#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7) 9519/* 0x09598 */ u64 g3ifgr01_cmu_group1_dll_wdqs1; 9520#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_WDQS1_ROLL mBIT(7) 9521#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_WDQS1_DLL_ENABLE mBIT(15) 9522#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3) 9523#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_WDQS1_SEL_MASTER_WDQS_CKN mBIT(31) 9524/* 0x095a0 */ u64 g3ifgr01_cmu_group1_dll_training1; 9525#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING1_DDR_TRA_STATUS(val)\ 9526 vBIT(val, 4, 4) 9527#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING1_DDR_TRA_MIN(val)\ 9528 vBIT(val, 9, 7) 9529#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING1_DDR_TRA_MAX(val)\ 9530 vBIT(val, 17, 7) 9531#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING1_DDR_ATRA_STATUS(val)\ 9532 vBIT(val, 36, 4) 9533#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING1_DDR_ATRA_MIN(val)\ 9534 vBIT(val, 41, 7) 9535#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING1_DDR_ATRA_MAX(val)\ 9536 vBIT(val, 49, 7) 9537/* 0x095a8 */ u64 g3ifgr01_cmu_group1_dll_training2; 9538#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\ 9539 vBIT(val, 0, 32) 9540#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\ 9541 vBIT(val, 32, 16) 9542#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\ 9543 vBIT(val, 48, 16) 9544/* 0x095b0 */ u64 g3ifgr01_cmu_group1_dll_training3; 9545#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING3_DLL_TRA_DATA00(val)\ 9546 vBIT(val, 0, 16) 9547#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING3_DLL_TRA_DATA01(val)\ 9548 vBIT(val, 16, 16) 9549/* 0x095b8 */ u64 g3ifgr01_cmu_group1_dll_act_training5; 9550#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ACT_TRAINING5_START_CODE(val)\ 9551 vBIT(val, 1, 7) 9552#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ACT_TRAINING5_END_CODE(val)\ 9553 vBIT(val, 9, 7) 9554#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ACT_TRAINING5_DISABLE mBIT(23) 9555#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ACT_TRAINING5_TCNT(val)\ 9556 vBIT(val, 28, 4) 9557/* 0x095c0 */ u64 g3ifgr01_cmu_group1_dll_training6; 9558#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING6_DLL_TRA_EN_HALF_EYE_VALID\ 9559 mBIT(7) 9560#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING6_DLL_ATRA_EN_HALF_EYE_VALID\ 9561 mBIT(15) 9562#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING6_DLL_TRA_EN_MASTER_CORR\ 9563 mBIT(23) 9564#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING6_DLL_ATRA_EN_MASTER_CORR\ 9565 mBIT(31) 9566#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39) 9567#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47) 9568/* 0x095c8 */ u64 g3ifgr01_cmu_group1_dll_atra_offset; 9569#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_OFFSET_EQUATION(val)\ 9570 vBIT(val, 6, 2) 9571#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_OFFSET_DDR_VALUE(val)\ 9572 vBIT(val, 8, 8) 9573/* 0x095d0 */ u64 g3ifgr01_cmu_group1_dll_tra_hold; 9574#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\ 9575 vBIT(val, 1, 7) 9576#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\ 9577 vBIT(val, 9, 7) 9578#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRA_HOLD_DDR_TIME(val)\ 9579 vBIT(val, 16, 24) 9580#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_TRA_HOLD_DDR_UPDATES(val)\ 9581 vBIT(val, 40, 24) 9582/* 0x095d8 */ u64 g3ifgr01_cmu_group1_dll_atra_hold; 9583#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\ 9584 vBIT(val, 1, 7) 9585#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\ 9586 vBIT(val, 9, 7) 9587#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_HOLD_DDR_TIME(val)\ 9588 vBIT(val, 16, 24) 9589#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_HOLD_DDR_UPDATES(val)\ 9590 vBIT(val, 40, 24) 9591/* 0x095e0 */ u64 g3ifgr01_cmu_group1_dll_master_codes; 9592#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\ 9593 vBIT(val, 9, 7) 9594#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\ 9595 vBIT(val, 25, 7) 9596#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\ 9597 vBIT(val, 41, 7) 9598#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\ 9599 vBIT(val, 57, 7) 9600/* 0x095e8 */ u64 g3ifgr01_cmu_group1_dll_atra_timer; 9601#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16) 9602#define VXGE_HAL_G3IFGR01_CMU_GROUP1_DLL_ATRA_TIMER_ENABLED mBIT(23) 9603 u8 unused09610[0x09610 - 0x095f0]; 9604 9605/* 0x09610 */ u64 g3ifgr23_cmu_group2_dll_rdqs; 9606#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8) 9607#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8) 9608#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8) 9609#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8) 9610#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7) 9611/* 0x09618 */ u64 g3ifgr23_cmu_group2_dll_rdqs1; 9612#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS1_ROLL mBIT(7) 9613#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS1_DLL_ENABLE mBIT(14) 9614#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15) 9615#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3) 9616/* 0x09620 */ u64 g3ifgr23_cmu_group2_dll_wdqs; 9617#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8) 9618#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8) 9619#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7) 9620/* 0x09628 */ u64 g3ifgr23_cmu_group2_dll_wdqs1; 9621#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_WDQS1_ROLL mBIT(7) 9622#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_WDQS1_DLL_ENABLE\ 9623 mBIT(15) 9624#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_WDQS1_DLL_UPD(val)\ 9625 vBIT(val, 21, 3) 9626#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_WDQS1_SEL_MASTER_WDQS_CKN\ 9627 mBIT(31) 9628/* 0x09630 */ u64 g3ifgr23_cmu_group2_dll_training1; 9629#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING1_DDR_TRA_STATUS(val)\ 9630 vBIT(val, 4, 4) 9631#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING1_DDR_TRA_MIN(val)\ 9632 vBIT(val, 9, 7) 9633#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING1_DDR_TRA_MAX(val)\ 9634 vBIT(val, 17, 7) 9635#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING1_DDR_ATRA_STATUS(val)\ 9636 vBIT(val, 36, 4) 9637#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING1_DDR_ATRA_MIN(val)\ 9638 vBIT(val, 41, 7) 9639#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING1_DDR_ATRA_MAX(val)\ 9640 vBIT(val, 49, 7) 9641/* 0x09638 */ u64 g3ifgr23_cmu_group2_dll_training2; 9642#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\ 9643 vBIT(val, 0, 32) 9644#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\ 9645 vBIT(val, 32, 16) 9646#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\ 9647 vBIT(val, 48, 16) 9648/* 0x09640 */ u64 g3ifgr23_cmu_group2_dll_training3; 9649#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING3_DLL_TRA_DATA00(val)\ 9650 vBIT(val, 0, 16) 9651#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING3_DLL_TRA_DATA01(val)\ 9652 vBIT(val, 16, 16) 9653/* 0x09648 */ u64 g3ifgr23_cmu_group2_dll_act_training5; 9654#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ACT_TRAINING5_START_CODE(val)\ 9655 vBIT(val, 1, 7) 9656#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ACT_TRAINING5_END_CODE(val)\ 9657 vBIT(val, 9, 7) 9658#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ACT_TRAINING5_DISABLE mBIT(23) 9659#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ACT_TRAINING5_TCNT(val)\ 9660 vBIT(val, 28, 4) 9661/* 0x09650 */ u64 g3ifgr23_cmu_group2_dll_training6; 9662#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING6_DLL_TRA_EN_HALF_EYE_VALID\ 9663 mBIT(7) 9664#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING6_DLL_ATRA_EN_HALF_EYE_VALID\ 9665 mBIT(15) 9666#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING6_DLL_TRA_EN_MASTER_CORR\ 9667 mBIT(23) 9668#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING6_DLL_ATRA_EN_MASTER_CORR\ 9669 mBIT(31) 9670#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39) 9671#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47) 9672/* 0x09658 */ u64 g3ifgr23_cmu_group2_dll_atra_offset; 9673#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_OFFSET_EQUATION(val)\ 9674 vBIT(val, 6, 2) 9675#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_OFFSET_DDR_VALUE(val)\ 9676 vBIT(val, 8, 8) 9677/* 0x09660 */ u64 g3ifgr23_cmu_group2_dll_tra_hold; 9678#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\ 9679 vBIT(val, 1, 7) 9680#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\ 9681 vBIT(val, 9, 7) 9682#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRA_HOLD_DDR_TIME(val)\ 9683 vBIT(val, 16, 24) 9684#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_TRA_HOLD_DDR_UPDATES(val)\ 9685 vBIT(val, 40, 24) 9686/* 0x09668 */ u64 g3ifgr23_cmu_group2_dll_atra_hold; 9687#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\ 9688 vBIT(val, 1, 7) 9689#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\ 9690 vBIT(val, 9, 7) 9691#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_HOLD_DDR_TIME(val)\ 9692 vBIT(val, 16, 24) 9693#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_HOLD_DDR_UPDATES(val)\ 9694 vBIT(val, 40, 24) 9695/* 0x09670 */ u64 g3ifgr23_cmu_group2_dll_master_codes; 9696#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\ 9697 vBIT(val, 9, 7) 9698#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\ 9699 vBIT(val, 25, 7) 9700#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\ 9701 vBIT(val, 41, 7) 9702#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\ 9703 vBIT(val, 57, 7) 9704/* 0x09678 */ u64 g3ifgr23_cmu_group2_dll_atra_timer; 9705#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16) 9706#define VXGE_HAL_G3IFGR23_CMU_GROUP2_DLL_ATRA_TIMER_ENABLED mBIT(23) 9707/* 0x09680 */ u64 g3ifgr23_cmu_group3_dll_rdqs; 9708#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8) 9709#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8) 9710#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8) 9711#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8) 9712#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7) 9713/* 0x09688 */ u64 g3ifgr23_cmu_group3_dll_rdqs1; 9714#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS1_ROLL mBIT(7) 9715#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS1_DLL_ENABLE mBIT(14) 9716#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15) 9717#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3) 9718/* 0x09690 */ u64 g3ifgr23_cmu_group3_dll_wdqs; 9719#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8) 9720#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8) 9721#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7) 9722/* 0x09698 */ u64 g3ifgr23_cmu_group3_dll_wdqs1; 9723#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_WDQS1_ROLL mBIT(7) 9724#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_WDQS1_DLL_ENABLE mBIT(15) 9725#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3) 9726#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_WDQS1_SEL_MASTER_WDQS_CKN mBIT(31) 9727/* 0x096a0 */ u64 g3ifgr23_cmu_group3_dll_training1; 9728#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING1_DDR_TRA_STATUS(val)\ 9729 vBIT(val, 4, 4) 9730#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING1_DDR_TRA_MIN(val)\ 9731 vBIT(val, 9, 7) 9732#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING1_DDR_TRA_MAX(val)\ 9733 vBIT(val, 17, 7) 9734#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING1_DDR_ATRA_STATUS(val)\ 9735 vBIT(val, 36, 4) 9736#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING1_DDR_ATRA_MIN(val)\ 9737 vBIT(val, 41, 7) 9738#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING1_DDR_ATRA_MAX(val)\ 9739 vBIT(val, 49, 7) 9740/* 0x096a8 */ u64 g3ifgr23_cmu_group3_dll_training2; 9741#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\ 9742 vBIT(val, 0, 32) 9743#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\ 9744 vBIT(val, 32, 16) 9745#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\ 9746 vBIT(val, 48, 16) 9747/* 0x096b0 */ u64 g3ifgr23_cmu_group3_dll_training3; 9748#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING3_DLL_TRA_DATA00(val)\ 9749 vBIT(val, 0, 16) 9750#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING3_DLL_TRA_DATA01(val)\ 9751 vBIT(val, 16, 16) 9752/* 0x096b8 */ u64 g3ifgr23_cmu_group3_dll_act_training5; 9753#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ACT_TRAINING5_START_CODE(val)\ 9754 vBIT(val, 1, 7) 9755#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ACT_TRAINING5_END_CODE(val)\ 9756 vBIT(val, 9, 7) 9757#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ACT_TRAINING5_DISABLE\ 9758 mBIT(23) 9759#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ACT_TRAINING5_TCNT(val)\ 9760 vBIT(val, 28, 4) 9761/* 0x096c0 */ u64 g3ifgr23_cmu_group3_dll_training6; 9762#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING6_DLL_TRA_EN_HALF_EYE_VALID\ 9763 mBIT(7) 9764#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING6_DLL_ATRA_EN_HALF_EYE_VALID\ 9765 mBIT(15) 9766#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING6_DLL_TRA_EN_MASTER_CORR\ 9767 mBIT(23) 9768#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING6_DLL_ATRA_EN_MASTER_CORR\ 9769 mBIT(31) 9770#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39) 9771#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47) 9772/* 0x096c8 */ u64 g3ifgr23_cmu_group3_dll_atra_offset; 9773#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_OFFSET_EQUATION(val)\ 9774 vBIT(val, 6, 2) 9775#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_OFFSET_DDR_VALUE(val)\ 9776 vBIT(val, 8, 8) 9777/* 0x096d0 */ u64 g3ifgr23_cmu_group3_dll_tra_hold; 9778#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\ 9779 vBIT(val, 1, 7) 9780#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\ 9781 vBIT(val, 9, 7) 9782#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRA_HOLD_DDR_TIME(val)\ 9783 vBIT(val, 16, 24) 9784#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_TRA_HOLD_DDR_UPDATES(val)\ 9785 vBIT(val, 40, 24) 9786/* 0x096d8 */ u64 g3ifgr23_cmu_group3_dll_atra_hold; 9787#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\ 9788 vBIT(val, 1, 7) 9789#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\ 9790 vBIT(val, 9, 7) 9791#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_HOLD_DDR_TIME(val)\ 9792 vBIT(val, 16, 24) 9793#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_HOLD_DDR_UPDATES(val)\ 9794 vBIT(val, 40, 24) 9795/* 0x096e0 */ u64 g3ifgr23_cmu_group3_dll_master_codes; 9796#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\ 9797 vBIT(val, 9, 7) 9798#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\ 9799 vBIT(val, 25, 7) 9800#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\ 9801 vBIT(val, 41, 7) 9802#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\ 9803 vBIT(val, 57, 7) 9804/* 0x096e8 */ u64 g3ifgr23_cmu_group3_dll_atra_timer; 9805#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16) 9806#define VXGE_HAL_G3IFGR23_CMU_GROUP3_DLL_ATRA_TIMER_ENABLED mBIT(23) 9807 u8 unused09800[0x09800 - 0x096f0]; 9808 9809/* 0x09800 */ u64 g3ifcmd_cml_int_status; 9810#define VXGE_HAL_G3IFCMD_CML_INT_STATUS_ERR_G3IF_INT mBIT(0) 9811/* 0x09808 */ u64 g3ifcmd_cml_int_mask; 9812/* 0x09810 */ u64 g3ifcmd_cml_err_reg; 9813#define VXGE_HAL_G3IFCMD_CML_ERR_REG_G3IF_CK_DLL_LOCK mBIT(6) 9814#define VXGE_HAL_G3IFCMD_CML_ERR_REG_G3IF_SM_ERR mBIT(7) 9815#define VXGE_HAL_G3IFCMD_CML_ERR_REG_G3IF_RWDQS_DLL_LOCK(val)\ 9816 vBIT(val, 24, 8) 9817#define VXGE_HAL_G3IFCMD_CML_ERR_REG_G3IF_IOCAL_FAULT mBIT(55) 9818/* 0x09818 */ u64 g3ifcmd_cml_err_mask; 9819/* 0x09820 */ u64 g3ifcmd_cml_err_alarm; 9820/* 0x09828 */ u64 g3ifcmd_cml_dll_ck0; 9821#define VXGE_HAL_G3IFCMD_CML_DLL_CK0_DLL_0_SA_CAL(val) vBIT(val, 0, 8) 9822#define VXGE_HAL_G3IFCMD_CML_DLL_CK0_DLL_0_SB_CAL(val) vBIT(val, 8, 8) 9823#define VXGE_HAL_G3IFCMD_CML_DLL_CK0_ROLL mBIT(23) 9824#define VXGE_HAL_G3IFCMD_CML_DLL_CK0_CMD_ADD_DLL_0_S(val) vBIT(val, 25, 7) 9825#define VXGE_HAL_G3IFCMD_CML_DLL_CK0_DLL_ENABLE mBIT(39) 9826#define VXGE_HAL_G3IFCMD_CML_DLL_CK0_DLL_UPD(val) vBIT(val, 44, 4) 9827/* 0x09830 */ u64 g3ifcmd_cml_io_ctrl; 9828#define VXGE_HAL_G3IFCMD_CML_IO_CTRL_DRIVE mBIT(7) 9829#define VXGE_HAL_G3IFCMD_CML_IO_CTRL_TERM(val) vBIT(val, 13, 3) 9830/* 0x09838 */ u64 g3ifcmd_cml_iocal; 9831#define VXGE_HAL_G3IFCMD_CML_IOCAL_RST_CYCLES(val) vBIT(val, 0, 16) 9832#define VXGE_HAL_G3IFCMD_CML_IOCAL_RST_VALUE(val) vBIT(val, 17, 7) 9833#define VXGE_HAL_G3IFCMD_CML_IOCAL_CORR_VALUE(val) vBIT(val, 24, 8) 9834#define VXGE_HAL_G3IFCMD_CML_IOCAL_IOCAL_CTRL_CAL_VALUE0(val)\ 9835 vBIT(val, 33, 7) 9836#define VXGE_HAL_G3IFCMD_CML_IOCAL_IOCAL_CTRL_CAL_VALUE1(val)\ 9837 vBIT(val, 41, 7) 9838#define VXGE_HAL_G3IFCMD_CML_IOCAL_IOCAL_CTRL_CAL_VALUE2(val)\ 9839 vBIT(val, 49, 7) 9840#define VXGE_HAL_G3IFCMD_CML_IOCAL_IOCAL_CTRL_CAL_VALUE3(val)\ 9841 vBIT(val, 57, 7) 9842/* 0x09840 */ u64 g3ifcmd_cml_master_dll_ck; 9843#define VXGE_HAL_G3IFCMD_CML_MASTER_DLL_CK_DDR_GR_RAW(val) vBIT(val, 1, 7) 9844#define VXGE_HAL_G3IFCMD_CML_MASTER_DLL_CK_SAMPLE(val) vBIT(val, 8, 8) 9845/* 0x09848 */ u64 g3ifcmd_cml_dll_training; 9846#define VXGE_HAL_G3IFCMD_CML_DLL_TRAINING_TRA_START mBIT(6) 9847#define VXGE_HAL_G3IFCMD_CML_DLL_TRAINING_TRA_DISABLE mBIT(7) 9848#define VXGE_HAL_G3IFCMD_CML_DLL_TRAINING_START_CODE(val) vBIT(val, 9, 7) 9849#define VXGE_HAL_G3IFCMD_CML_DLL_TRAINING_END_CODE(val) vBIT(val, 17, 7) 9850 u8 unused09910[0x09910 - 0x09850]; 9851 9852/* 0x09910 */ u64 g3ifgr01_cml_group0_dll_rdqs; 9853#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8) 9854#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8) 9855#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS_ATRA_SA_CAL(val)\ 9856 vBIT(val, 32, 8) 9857#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS_ATRA_SB_CAL(val)\ 9858 vBIT(val, 40, 8) 9859#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7) 9860/* 0x09918 */ u64 g3ifgr01_cml_group0_dll_rdqs1; 9861#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS1_ROLL mBIT(7) 9862#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS1_DLL_ENABLE mBIT(14) 9863#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15) 9864#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3) 9865/* 0x09920 */ u64 g3ifgr01_cml_group0_dll_wdqs; 9866#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8) 9867#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8) 9868#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7) 9869/* 0x09928 */ u64 g3ifgr01_cml_group0_dll_wdqs1; 9870#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_WDQS1_ROLL mBIT(7) 9871#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_WDQS1_DLL_ENABLE mBIT(15) 9872#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3) 9873#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_WDQS1_SEL_MASTER_WDQS_CKN\ 9874 mBIT(31) 9875/* 0x09930 */ u64 g3ifgr01_cml_group0_dll_training1; 9876#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING1_DDR_TRA_STATUS(val)\ 9877 vBIT(val, 4, 4) 9878#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING1_DDR_TRA_MIN(val)\ 9879 vBIT(val, 9, 7) 9880#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING1_DDR_TRA_MAX(val)\ 9881 vBIT(val, 17, 7) 9882#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING1_DDR_ATRA_STATUS(val)\ 9883 vBIT(val, 36, 4) 9884#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING1_DDR_ATRA_MIN(val)\ 9885 vBIT(val, 41, 7) 9886#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING1_DDR_ATRA_MAX(val)\ 9887 vBIT(val, 49, 7) 9888/* 0x09938 */ u64 g3ifgr01_cml_group0_dll_training2; 9889#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\ 9890 vBIT(val, 0, 32) 9891#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\ 9892 vBIT(val, 32, 16) 9893#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\ 9894 vBIT(val, 48, 16) 9895/* 0x09940 */ u64 g3ifgr01_cml_group0_dll_training3; 9896#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING3_DLL_TRA_DATA00(val)\ 9897 vBIT(val, 0, 16) 9898#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING3_DLL_TRA_DATA01(val)\ 9899 vBIT(val, 16, 16) 9900/* 0x09948 */ u64 g3ifgr01_cml_group0_dll_act_training5; 9901#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ACT_TRAINING5_START_CODE(val)\ 9902 vBIT(val, 1, 7) 9903#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ACT_TRAINING5_END_CODE(val)\ 9904 vBIT(val, 9, 7) 9905#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ACT_TRAINING5_DISABLE mBIT(23) 9906#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ACT_TRAINING5_TCNT(val)\ 9907 vBIT(val, 28, 4) 9908/* 0x09950 */ u64 g3ifgr01_cml_group0_dll_training6; 9909#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING6_DLL_TRA_EN_HALF_EYE_VALID\ 9910 mBIT(7) 9911#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING6_DLL_ATRA_EN_HALF_EYE_VALID\ 9912 mBIT(15) 9913#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING6_DLL_TRA_EN_MASTER_CORR\ 9914 mBIT(23) 9915#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING6_DLL_ATRA_EN_MASTER_CORR\ 9916 mBIT(31) 9917#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39) 9918#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47) 9919/* 0x09958 */ u64 g3ifgr01_cml_group0_dll_atra_offset; 9920#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_OFFSET_EQUATION(val)\ 9921 vBIT(val, 6, 2) 9922#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_OFFSET_DDR_VALUE(val)\ 9923 vBIT(val, 8, 8) 9924/* 0x09960 */ u64 g3ifgr01_cml_group0_dll_tra_hold; 9925#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\ 9926 vBIT(val, 1, 7) 9927#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\ 9928 vBIT(val, 9, 7) 9929#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRA_HOLD_DDR_TIME(val)\ 9930 vBIT(val, 16, 24) 9931#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_TRA_HOLD_DDR_UPDATES(val)\ 9932 vBIT(val, 40, 24) 9933/* 0x09968 */ u64 g3ifgr01_cml_group0_dll_atra_hold; 9934#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\ 9935 vBIT(val, 1, 7) 9936#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\ 9937 vBIT(val, 9, 7) 9938#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_HOLD_DDR_TIME(val)\ 9939 vBIT(val, 16, 24) 9940#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_HOLD_DDR_UPDATES(val)\ 9941 vBIT(val, 40, 24) 9942/* 0x09970 */ u64 g3ifgr01_cml_group0_dll_master_codes; 9943#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\ 9944 vBIT(val, 9, 7) 9945#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\ 9946 vBIT(val, 25, 7) 9947#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\ 9948 vBIT(val, 41, 7) 9949#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\ 9950 vBIT(val, 57, 7) 9951/* 0x09978 */ u64 g3ifgr01_cml_group0_dll_atra_timer; 9952#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16) 9953#define VXGE_HAL_G3IFGR01_CML_GROUP0_DLL_ATRA_TIMER_ENABLED mBIT(23) 9954/* 0x09980 */ u64 g3ifgr01_cml_group1_dll_rdqs; 9955#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8) 9956#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8) 9957#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8) 9958#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8) 9959#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7) 9960/* 0x09988 */ u64 g3ifgr01_cml_group1_dll_rdqs1; 9961#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS1_ROLL mBIT(7) 9962#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS1_DLL_ENABLE mBIT(14) 9963#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15) 9964#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3) 9965/* 0x09990 */ u64 g3ifgr01_cml_group1_dll_wdqs; 9966#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8) 9967#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8) 9968#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7) 9969/* 0x09998 */ u64 g3ifgr01_cml_group1_dll_wdqs1; 9970#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_WDQS1_ROLL mBIT(7) 9971#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_WDQS1_DLL_ENABLE mBIT(15) 9972#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3) 9973#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_WDQS1_SEL_MASTER_WDQS_CKN mBIT(31) 9974/* 0x099a0 */ u64 g3ifgr01_cml_group1_dll_training1; 9975#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING1_DDR_TRA_STATUS(val)\ 9976 vBIT(val, 4, 4) 9977#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING1_DDR_TRA_MIN(val)\ 9978 vBIT(val, 9, 7) 9979#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING1_DDR_TRA_MAX(val)\ 9980 vBIT(val, 17, 7) 9981#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING1_DDR_ATRA_STATUS(val)\ 9982 vBIT(val, 36, 4) 9983#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING1_DDR_ATRA_MIN(val)\ 9984 vBIT(val, 41, 7) 9985#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING1_DDR_ATRA_MAX(val)\ 9986 vBIT(val, 49, 7) 9987/* 0x099a8 */ u64 g3ifgr01_cml_group1_dll_training2; 9988#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\ 9989 vBIT(val, 0, 32) 9990#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\ 9991 vBIT(val, 32, 16) 9992#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\ 9993 vBIT(val, 48, 16) 9994/* 0x099b0 */ u64 g3ifgr01_cml_group1_dll_training3; 9995#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING3_DLL_TRA_DATA00(val)\ 9996 vBIT(val, 0, 16) 9997#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING3_DLL_TRA_DATA01(val)\ 9998 vBIT(val, 16, 16) 9999/* 0x099b8 */ u64 g3ifgr01_cml_group1_dll_act_training5; 10000#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ACT_TRAINING5_START_CODE(val)\ 10001 vBIT(val, 1, 7) 10002#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ACT_TRAINING5_END_CODE(val)\ 10003 vBIT(val, 9, 7) 10004#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ACT_TRAINING5_DISABLE mBIT(23) 10005#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ACT_TRAINING5_TCNT(val)\ 10006 vBIT(val, 28, 4) 10007/* 0x099c0 */ u64 g3ifgr01_cml_group1_dll_training6; 10008#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING6_DLL_TRA_EN_HALF_EYE_VALID\ 10009 mBIT(7) 10010#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING6_DLL_ATRA_EN_HALF_EYE_VALID\ 10011 mBIT(15) 10012#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING6_DLL_TRA_EN_MASTER_CORR\ 10013 mBIT(23) 10014#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING6_DLL_ATRA_EN_MASTER_CORR\ 10015 mBIT(31) 10016#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39) 10017#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47) 10018/* 0x099c8 */ u64 g3ifgr01_cml_group1_dll_atra_offset; 10019#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_OFFSET_EQUATION(val)\ 10020 vBIT(val, 6, 2) 10021#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_OFFSET_DDR_VALUE(val)\ 10022 vBIT(val, 8, 8) 10023/* 0x099d0 */ u64 g3ifgr01_cml_group1_dll_tra_hold; 10024#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\ 10025 vBIT(val, 1, 7) 10026#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\ 10027 vBIT(val, 9, 7) 10028#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRA_HOLD_DDR_TIME(val)\ 10029 vBIT(val, 16, 24) 10030#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_TRA_HOLD_DDR_UPDATES(val)\ 10031 vBIT(val, 40, 24) 10032/* 0x099d8 */ u64 g3ifgr01_cml_group1_dll_atra_hold; 10033#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\ 10034 vBIT(val, 1, 7) 10035#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\ 10036 vBIT(val, 9, 7) 10037#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_HOLD_DDR_TIME(val)\ 10038 vBIT(val, 16, 24) 10039#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_HOLD_DDR_UPDATES(val)\ 10040 vBIT(val, 40, 24) 10041/* 0x099e0 */ u64 g3ifgr01_cml_group1_dll_master_codes; 10042#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\ 10043 vBIT(val, 9, 7) 10044#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\ 10045 vBIT(val, 25, 7) 10046#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\ 10047 vBIT(val, 41, 7) 10048#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\ 10049 vBIT(val, 57, 7) 10050/* 0x099e8 */ u64 g3ifgr01_cml_group1_dll_atra_timer; 10051#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_TIMER_VALUE(val)\ 10052 vBIT(val, 0, 16) 10053#define VXGE_HAL_G3IFGR01_CML_GROUP1_DLL_ATRA_TIMER_ENABLED mBIT(23) 10054 u8 unused09a10[0x09a10 - 0x099f0]; 10055 10056/* 0x09a10 */ u64 g3ifgr23_cml_group2_dll_rdqs; 10057#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8) 10058#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8) 10059#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8) 10060#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8) 10061#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7) 10062/* 0x09a18 */ u64 g3ifgr23_cml_group2_dll_rdqs1; 10063#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS1_ROLL mBIT(7) 10064#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS1_DLL_ENABLE mBIT(14) 10065#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15) 10066#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3) 10067/* 0x09a20 */ u64 g3ifgr23_cml_group2_dll_wdqs; 10068#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8) 10069#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8) 10070#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7) 10071/* 0x09a28 */ u64 g3ifgr23_cml_group2_dll_wdqs1; 10072#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_WDQS1_ROLL mBIT(7) 10073#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_WDQS1_DLL_ENABLE mBIT(15) 10074#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3) 10075#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_WDQS1_SEL_MASTER_WDQS_CKN\ 10076 mBIT(31) 10077/* 0x09a30 */ u64 g3ifgr23_cml_group2_dll_training1; 10078#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING1_DDR_TRA_STATUS(val)\ 10079 vBIT(val, 4, 4) 10080#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING1_DDR_TRA_MIN(val)\ 10081 vBIT(val, 9, 7) 10082#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING1_DDR_TRA_MAX(val)\ 10083 vBIT(val, 17, 7) 10084#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING1_DDR_ATRA_STATUS(val)\ 10085 vBIT(val, 36, 4) 10086#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING1_DDR_ATRA_MIN(val)\ 10087 vBIT(val, 41, 7) 10088#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING1_DDR_ATRA_MAX(val)\ 10089 vBIT(val, 49, 7) 10090/* 0x09a38 */ u64 g3ifgr23_cml_group2_dll_training2; 10091#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\ 10092 vBIT(val, 0, 32) 10093#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\ 10094 vBIT(val, 32, 16) 10095#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\ 10096 vBIT(val, 48, 16) 10097/* 0x09a40 */ u64 g3ifgr23_cml_group2_dll_training3; 10098#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING3_DLL_TRA_DATA00(val)\ 10099 vBIT(val, 0, 16) 10100#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING3_DLL_TRA_DATA01(val)\ 10101 vBIT(val, 16, 16) 10102/* 0x09a48 */ u64 g3ifgr23_cml_group2_dll_act_training5; 10103#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ACT_TRAINING5_START_CODE(val)\ 10104 vBIT(val, 1, 7) 10105#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ACT_TRAINING5_END_CODE(val)\ 10106 vBIT(val, 9, 7) 10107#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ACT_TRAINING5_DISABLE mBIT(23) 10108#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ACT_TRAINING5_TCNT(val) \ 10109 vBIT(val, 28, 4) 10110/* 0x09a50 */ u64 g3ifgr23_cml_group2_dll_training6; 10111#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING6_DLL_TRA_EN_HALF_EYE_VALID\ 10112 mBIT(7) 10113#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING6_DLL_ATRA_EN_HALF_EYE_VALID\ 10114 mBIT(15) 10115#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING6_DLL_TRA_EN_MASTER_CORR\ 10116 mBIT(23) 10117#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING6_DLL_ATRA_EN_MASTER_CORR\ 10118 mBIT(31) 10119#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39) 10120#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47) 10121/* 0x09a58 */ u64 g3ifgr23_cml_group2_dll_atra_offset; 10122#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_OFFSET_EQUATION(val)\ 10123 vBIT(val, 6, 2) 10124#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_OFFSET_DDR_VALUE(val)\ 10125 vBIT(val, 8, 8) 10126/* 0x09a60 */ u64 g3ifgr23_cml_group2_dll_tra_hold; 10127#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\ 10128 vBIT(val, 1, 7) 10129#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\ 10130 vBIT(val, 9, 7) 10131#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRA_HOLD_DDR_TIME(val)\ 10132 vBIT(val, 16, 24) 10133#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_TRA_HOLD_DDR_UPDATES(val)\ 10134 vBIT(val, 40, 24) 10135/* 0x09a68 */ u64 g3ifgr23_cml_group2_dll_atra_hold; 10136#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\ 10137 vBIT(val, 1, 7) 10138#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\ 10139 vBIT(val, 9, 7) 10140#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_HOLD_DDR_TIME(val)\ 10141 vBIT(val, 16, 24) 10142#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_HOLD_DDR_UPDATES(val)\ 10143 vBIT(val, 40, 24) 10144/* 0x09a70 */ u64 g3ifgr23_cml_group2_dll_master_codes; 10145#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\ 10146 vBIT(val, 9, 7) 10147#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\ 10148 vBIT(val, 25, 7) 10149#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\ 10150 vBIT(val, 41, 7) 10151#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\ 10152 vBIT(val, 57, 7) 10153/* 0x09a78 */ u64 g3ifgr23_cml_group2_dll_atra_timer; 10154#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16) 10155#define VXGE_HAL_G3IFGR23_CML_GROUP2_DLL_ATRA_TIMER_ENABLED mBIT(23) 10156/* 0x09a80 */ u64 g3ifgr23_cml_group3_dll_rdqs; 10157#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS_SA_CAL(val) vBIT(val, 0, 8) 10158#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS_SB_CAL(val) vBIT(val, 8, 8) 10159#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS_ATRA_SA_CAL(val) vBIT(val, 32, 8) 10160#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS_ATRA_SB_CAL(val) vBIT(val, 40, 8) 10161#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS_DDR_DLL_S(val) vBIT(val, 57, 7) 10162/* 0x09a88 */ u64 g3ifgr23_cml_group3_dll_rdqs1; 10163#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS1_ROLL mBIT(7) 10164#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS1_DLL_ENABLE mBIT(14) 10165#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS1_DLL_ENABLE_ATRA mBIT(15) 10166#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_RDQS1_DLL_UPD(val) vBIT(val, 21, 3) 10167/* 0x09a90 */ u64 g3ifgr23_cml_group3_dll_wdqs; 10168#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_WDQS_SA_CAL(val) vBIT(val, 0, 8) 10169#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_WDQS_SB_CAL(val) vBIT(val, 8, 8) 10170#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_WDQS_DDR_DLL_S(val) vBIT(val, 57, 7) 10171/* 0x09a98 */ u64 g3ifgr23_cml_group3_dll_wdqs1; 10172#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_WDQS1_ROLL mBIT(7) 10173#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_WDQS1_DLL_ENABLE mBIT(15) 10174#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_WDQS1_DLL_UPD(val) vBIT(val, 21, 3) 10175#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_WDQS1_SEL_MASTER_WDQS_CKN mBIT(31) 10176/* 0x09aa0 */ u64 g3ifgr23_cml_group3_dll_training1; 10177#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING1_DDR_TRA_STATUS(val)\ 10178 vBIT(val, 4, 4) 10179#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING1_DDR_TRA_MIN(val)\ 10180 vBIT(val, 9, 7) 10181#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING1_DDR_TRA_MAX(val)\ 10182 vBIT(val, 17, 7) 10183#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING1_DDR_ATRA_STATUS(val)\ 10184 vBIT(val, 36, 4) 10185#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING1_DDR_ATRA_MIN(val)\ 10186 vBIT(val, 41, 7) 10187#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING1_DDR_ATRA_MAX(val)\ 10188 vBIT(val, 49, 7) 10189/* 0x09aa8 */ u64 g3ifgr23_cml_group3_dll_training2; 10190#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING2_DDR_ATRA_PASS_CNT(val)\ 10191 vBIT(val, 0, 32) 10192#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING2_DDR_ATRA_FAIL_CNT(val)\ 10193 vBIT(val, 32, 16) 10194#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING2_DDR_ATRA_TIMER_FAIL_CNT(val)\ 10195 vBIT(val, 48, 16) 10196/* 0x09ab0 */ u64 g3ifgr23_cml_group3_dll_training3; 10197#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING3_DLL_TRA_DATA00(val)\ 10198 vBIT(val, 0, 16) 10199#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING3_DLL_TRA_DATA01(val)\ 10200 vBIT(val, 16, 16) 10201/* 0x09ab8 */ u64 g3ifgr23_cml_group3_dll_act_training5; 10202#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ACT_TRAINING5_START_CODE(val)\ 10203 vBIT(val, 1, 7) 10204#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ACT_TRAINING5_END_CODE(val)\ 10205 vBIT(val, 9, 7) 10206#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ACT_TRAINING5_DISABLE mBIT(23) 10207#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ACT_TRAINING5_TCNT(val)\ 10208 vBIT(val, 28, 4) 10209/* 0x09ac0 */ u64 g3ifgr23_cml_group3_dll_training6; 10210#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING6_DLL_TRA_EN_HALF_EYE_VALID\ 10211 mBIT(7) 10212#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING6_DLL_ATRA_EN_HALF_EYE_VALID\ 10213 mBIT(15) 10214#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING6_DLL_TRA_EN_MASTER_CORR\ 10215 mBIT(23) 10216#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING6_DLL_ATRA_EN_MASTER_CORR\ 10217 mBIT(31) 10218#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING6_DLL_SEL_TRA_ONLY mBIT(39) 10219#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRAINING6_DLL_EN_MOVING_AVR mBIT(47) 10220/* 0x09ac8 */ u64 g3ifgr23_cml_group3_dll_atra_offset; 10221#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_OFFSET_EQUATION(val)\ 10222 vBIT(val, 6, 2) 10223#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_OFFSET_DDR_VALUE(val)\ 10224 vBIT(val, 8, 8) 10225/* 0x09ad0 */ u64 g3ifgr23_cml_group3_dll_tra_hold; 10226#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRA_HOLD_DDR_MASTER_MIN(val)\ 10227 vBIT(val, 1, 7) 10228#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRA_HOLD_DDR_MASTER_MAX(val)\ 10229 vBIT(val, 9, 7) 10230#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRA_HOLD_DDR_TIME(val)\ 10231 vBIT(val, 16, 24) 10232#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_TRA_HOLD_DDR_UPDATES(val)\ 10233 vBIT(val, 40, 24) 10234/* 0x09ad8 */ u64 g3ifgr23_cml_group3_dll_atra_hold; 10235#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_HOLD_DDR_MASTER_MIN(val)\ 10236 vBIT(val, 1, 7) 10237#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_HOLD_DDR_MASTER_MAX(val)\ 10238 vBIT(val, 9, 7) 10239#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_HOLD_DDR_TIME(val)\ 10240 vBIT(val, 16, 24) 10241#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_HOLD_DDR_UPDATES(val)\ 10242 vBIT(val, 40, 24) 10243/* 0x09ae0 */ u64 g3ifgr23_cml_group3_dll_master_codes; 10244#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_MASTER_CODES_DDR_RDQS_TRA_HOLD(val)\ 10245 vBIT(val, 9, 7) 10246#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_MASTER_CODES_DDR_RDQS_ATRA_HOLD(val)\ 10247 vBIT(val, 25, 7) 10248#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_MASTER_CODES_DDR_WDQS_RAW(val)\ 10249 vBIT(val, 41, 7) 10250#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_MASTER_CODES_DDR_RDQS_RAW(val)\ 10251 vBIT(val, 57, 7) 10252/* 0x09ae8 */ u64 g3ifgr23_cml_group3_dll_atra_timer; 10253#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_TIMER_VALUE(val) vBIT(val, 0, 16) 10254#define VXGE_HAL_G3IFGR23_CML_GROUP3_DLL_ATRA_TIMER_ENABLED mBIT(23) 10255 u8 unused09b00[0x09b00 - 0x09af0]; 10256 10257/* 0x09b00 */ u64 vpath_to_vplane_map[17]; 10258#define VXGE_HAL_VPATH_TO_VPLANE_MAP_VPATH_TO_VPLANE_MAP(val) vBIT(val, 3, 5) 10259 u8 unused09c30[0x09c30 - 0x09b88]; 10260 10261/* 0x09c30 */ u64 xgxs_cfg_port[2]; 10262#define VXGE_HAL_XGXS_CFG_PORT_SIG_DETECT_FORCE_LOS(val) vBIT(val, 16, 4) 10263#define VXGE_HAL_XGXS_CFG_PORT_SIG_DETECT_FORCE_VALID(val) vBIT(val, 20, 4) 10264#define VXGE_HAL_XGXS_CFG_PORT_SEL_INFO_0 mBIT(27) 10265#define VXGE_HAL_XGXS_CFG_PORT_SEL_INFO_1(val) vBIT(val, 29, 3) 10266#define VXGE_HAL_XGXS_CFG_PORT_TX_LANE0_SKEW(val) vBIT(val, 32, 4) 10267#define VXGE_HAL_XGXS_CFG_PORT_TX_LANE1_SKEW(val) vBIT(val, 36, 4) 10268#define VXGE_HAL_XGXS_CFG_PORT_TX_LANE2_SKEW(val) vBIT(val, 40, 4) 10269#define VXGE_HAL_XGXS_CFG_PORT_TX_LANE3_SKEW(val) vBIT(val, 44, 4) 10270/* 0x09c40 */ u64 xgxs_rxber_cfg_port[2]; 10271#define VXGE_HAL_XGXS_RXBER_CFG_PORT_INTERVAL_DUR(val) vBIT(val, 0, 4) 10272#define VXGE_HAL_XGXS_RXBER_CFG_PORT_RXGXS_INTERVAL_CNT(val) vBIT(val, 16, 48) 10273/* 0x09c50 */ u64 xgxs_rxber_status_port[2]; 10274#define VXGE_HAL_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_A_ERR_CNT(val)\ 10275 vBIT(val, 0, 16) 10276#define VXGE_HAL_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_B_ERR_CNT(val)\ 10277 vBIT(val, 16, 16) 10278#define VXGE_HAL_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_C_ERR_CNT(val)\ 10279 vBIT(val, 32, 16) 10280#define VXGE_HAL_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_D_ERR_CNT(val)\ 10281 vBIT(val, 48, 16) 10282/* 0x09c60 */ u64 xgxs_status_port[2]; 10283#define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_TX_ACTIVITY(val) vBIT(val, 0, 4) 10284#define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_RX_ACTIVITY(val) vBIT(val, 4, 4) 10285#define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_CTC_FIFO_ERR BIT(11) 10286#define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_BYTE_SYNC_LOST(val) vBIT(val, 12, 4) 10287#define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_CTC_ERR(val) vBIT(val, 16, 4) 10288#define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_ALIGNMENT_ERR mBIT(23) 10289#define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_DEC_ERR(val) vBIT(val, 24, 8) 10290#define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_SKIP_INS_REQ(val) vBIT(val, 32, 4) 10291#define VXGE_HAL_XGXS_STATUS_PORT_XMACJ_PCS_SKIP_DEL_REQ(val) vBIT(val, 36, 4) 10292/* 0x09c70 */ u64 xgxs_pma_reset_port[2]; 10293#define VXGE_HAL_XGXS_PMA_RESET_PORT_SERDES_RESET(val) vBIT(val, 0, 8) 10294 u8 unused09c90[0x09c90 - 0x09c80]; 10295 10296/* 0x09c90 */ u64 xgxs_static_cfg_port[2]; 10297#define VXGE_HAL_XGXS_STATIC_CFG_PORT_FW_CTRL_SERDES mBIT(3) 10298 u8 unused09cc0[0x09cc0 - 0x09ca0]; 10299 10300/* 0x09cc0 */ u64 xgxs_serdes_fw_cfg_port[2]; 10301#define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_TX_EN_LANE0(val) vBIT(val, 1, 3) 10302#define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_TX_EN_LANE1(val) vBIT(val, 5, 3) 10303#define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_TX_EN_LANE2(val) vBIT(val, 9, 3) 10304#define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_TX_EN_LANE3(val) vBIT(val, 13, 3) 10305#define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_EN_LANE0 mBIT(16) 10306#define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_EN_LANE1 mBIT(17) 10307#define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_EN_LANE2 mBIT(18) 10308#define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_EN_LANE3 mBIT(19) 10309#define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_PLL_PWRON_LANE0 mBIT(20) 10310#define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_PLL_PWRON_LANE1 mBIT(21) 10311#define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_PLL_PWRON_LANE2 mBIT(22) 10312#define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_PLL_PWRON_LANE3 mBIT(23) 10313#define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_TERM_EN_LANE0 mBIT(24) 10314#define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_TERM_EN_LANE1 mBIT(25) 10315#define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_TERM_EN_LANE2 mBIT(26) 10316#define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_TERM_EN_LANE3 mBIT(27) 10317#define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_MPLL_CK_OFF mBIT(31) 10318#define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_MPLL_PWRON mBIT(35) 10319#define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_CKO_WORD_CON(val) vBIT(val, 37, 3) 10320#define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RESET_N mBIT(43) 10321#define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_CKO_WORD_READY mBIT(47) 10322#define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_CK_READY_LANE0 mBIT(48) 10323#define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_CK_READY_LANE1 mBIT(49) 10324#define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_CK_READY_LANE2 mBIT(50) 10325#define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_RX_CK_READY_LANE3 mBIT(51) 10326#define VXGE_HAL_XGXS_SERDES_FW_CFG_PORT_TRUST_HW_RX_CK_READY mBIT(55) 10327/* 0x09cd0 */ u64 xgxs_serdes_tx_cfg_port[2]; 10328#define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_BOOST_LANE0(val) vBIT(val, 0, 4) 10329#define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_BOOST_LANE1(val) vBIT(val, 4, 4) 10330#define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_BOOST_LANE2(val) vBIT(val, 8, 4) 10331#define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_BOOST_LANE3(val) vBIT(val, 12, 4) 10332#define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_ATTEN_LANE0(val) vBIT(val, 17, 3) 10333#define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_ATTEN_LANE1(val) vBIT(val, 21, 3) 10334#define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_ATTEN_LANE2(val) vBIT(val, 25, 3) 10335#define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_ATTEN_LANE3(val) vBIT(val, 29, 3) 10336#define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CALC_LANE0 mBIT(32) 10337#define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CALC_LANE1 mBIT(33) 10338#define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CALC_LANE2 mBIT(34) 10339#define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CALC_LANE3 mBIT(35) 10340#define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CLK_ALIGN_LANE0 mBIT(36) 10341#define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CLK_ALIGN_LANE1 mBIT(37) 10342#define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CLK_ALIGN_LANE2 mBIT(38) 10343#define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CLK_ALIGN_LANE3 mBIT(39) 10344#define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CKO_EN_LANE0 mBIT(40) 10345#define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CKO_EN_LANE1 mBIT(41) 10346#define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CKO_EN_LANE2 mBIT(42) 10347#define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_CKO_EN_LANE3 mBIT(43) 10348#define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_EDGERATE_LANE0(val) vBIT(val, 44, 2) 10349#define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_EDGERATE_LANE1(val) vBIT(val, 46, 2) 10350#define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_EDGERATE_LANE2(val) vBIT(val, 48, 2) 10351#define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_EDGERATE_LANE3(val) vBIT(val, 50, 2) 10352#define VXGE_HAL_XGXS_SERDES_TX_CFG_PORT_TX_LVL(val) vBIT(val, 55, 5) 10353/* 0x09ce0 */ u64 xgxs_serdes_rx_cfg_port[2]; 10354#define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_ALIGN_EN_LANE0 mBIT(0) 10355#define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_ALIGN_EN_LANE1 mBIT(1) 10356#define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_ALIGN_EN_LANE2 mBIT(2) 10357#define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_ALIGN_EN_LANE3 mBIT(3) 10358#define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_EQ_VAL_LANE0(val) vBIT(val, 5, 3) 10359#define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_EQ_VAL_LANE1(val) vBIT(val, 9, 3) 10360#define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_EQ_VAL_LANE2(val) vBIT(val, 13, 3) 10361#define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_EQ_VAL_LANE3(val) vBIT(val, 17, 3) 10362#define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_DPLL_MODE_LANE0(val)\ 10363 vBIT(val, 21, 3) 10364#define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_DPLL_MODE_LANE1(val)\ 10365 vBIT(val, 25, 3) 10366#define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_DPLL_MODE_LANE2(val)\ 10367 vBIT(val, 29, 3) 10368#define VXGE_HAL_XGXS_SERDES_RX_CFG_PORT_RX_DPLL_MODE_LANE3(val)\ 10369 vBIT(val, 33, 3) 10370/* 0x09cf0 */ u64 xgxs_serdes_extra_cfg_port[2]; 10371#define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_DPLL_RESET_LANE0 mBIT(0) 10372#define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_DPLL_RESET_LANE1 mBIT(1) 10373#define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_DPLL_RESET_LANE2 mBIT(2) 10374#define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_DPLL_RESET_LANE3 mBIT(3) 10375#define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_LOS_CTL_LANE0(val) vBIT(val, 4, 2) 10376#define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_LOS_CTL_LANE1(val) vBIT(val, 6, 2) 10377#define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_LOS_CTL_LANE2(val) vBIT(val, 8, 2) 10378#define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_LOS_CTL_LANE3(val) vBIT(val, 10, 2) 10379#define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_WIDE_XFACE mBIT(14) 10380#define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_RTUNE_DO_TUNE mBIT(15) 10381#define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_LOS_LVL(val) vBIT(val, 19, 5) 10382#define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_CKO_ALIVE_CON(val) vBIT(val, 28, 2) 10383#define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_MPLL_SS_EN mBIT(32) 10384#define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_MPLL_INT_CTL(val) vBIT(val, 33, 3) 10385#define VXGE_HAL_XGXS_SERDES_EXTRA_CFG_PORT_MPLL_PROP_CTL(val) vBIT(val, 37, 3) 10386/* 0x09d00 */ u64 xgxs_serdes_status_port[2]; 10387#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_COMMA_DET_LANE0(val)\ 10388 vBIT(val, 0, 2) 10389#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_COMMA_DET_LANE1(val)\ 10390 vBIT(val, 2, 2) 10391#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_COMMA_DET_LANE2(val)\ 10392 vBIT(val, 4, 2) 10393#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_COMMA_DET_LANE3(val)\ 10394 vBIT(val, 6, 2) 10395#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_TX_RXPRES_LANE0 mBIT(8) 10396#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_TX_RXPRES_LANE1 mBIT(9) 10397#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_TX_RXPRES_LANE2 mBIT(10) 10398#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_TX_RXPRES_LANE3 mBIT(11) 10399#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_TX_DONE_LANE0 mBIT(12) 10400#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_TX_DONE_LANE1 mBIT(13) 10401#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_TX_DONE_LANE2 mBIT(14) 10402#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_TX_DONE_LANE3 mBIT(15) 10403#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_PLL_STATE_LANE0 mBIT(16) 10404#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_PLL_STATE_LANE1 mBIT(17) 10405#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_PLL_STATE_LANE2 mBIT(18) 10406#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_PLL_STATE_LANE3 mBIT(19) 10407#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_VALID_LANE0 mBIT(20) 10408#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_VALID_LANE1 mBIT(21) 10409#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_VALID_LANE2 mBIT(22) 10410#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_RX_VALID_LANE3 mBIT(23) 10411#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_LOS_LANE0 mBIT(24) 10412#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_LOS_LANE1 mBIT(25) 10413#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_LOS_LANE2 mBIT(26) 10414#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_LOS_LANE3 mBIT(27) 10415#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_OP_DONE_ASSERTED mBIT(30) 10416#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_OP_DONE_DEASSERTED mBIT(31) 10417#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_POWER_GOOD mBIT(35) 10418#define VXGE_HAL_XGXS_SERDES_STATUS_PORT_XPRG_SERDES_INIT_COMPLETE mBIT(39) 10419/* 0x09d10 */ u64 xgxs_serdes_cr_access_port[2]; 10420#define VXGE_HAL_XGXS_SERDES_CR_ACCESS_PORT_WE mBIT(3) 10421#define VXGE_HAL_XGXS_SERDES_CR_ACCESS_PORT_STROBE mBIT(7) 10422#define VXGE_HAL_XGXS_SERDES_CR_ACCESS_PORT_ADDR(val) vBIT(val, 16, 16) 10423#define VXGE_HAL_XGXS_SERDES_CR_ACCESS_PORT_DATA(val) vBIT(val, 48, 16) 10424 u8 unused09d40[0x09d40 - 0x09d20]; 10425 10426/* 0x09d40 */ u64 xgxs_info_port[2]; 10427#define VXGE_HAL_XGXS_INFO_PORT_XMACJ_INFO_0(val) vBIT(val, 0, 32) 10428#define VXGE_HAL_XGXS_INFO_PORT_XMACJ_INFO_1(val) vBIT(val, 32, 32) 10429/* 0x09d50 */ u64 ratemgmt_cfg_port[2]; 10430#define VXGE_HAL_RATEMGMT_CFG_PORT_MODE(val) vBIT(val, 2, 2) 10431#define VXGE_HAL_RATEMGMT_CFG_PORT_RATE mBIT(7) 10432#define VXGE_HAL_RATEMGMT_CFG_PORT_FIXED_USE_FSM mBIT(11) 10433#define VXGE_HAL_RATEMGMT_CFG_PORT_ANTP_USE_FSM mBIT(15) 10434#define VXGE_HAL_RATEMGMT_CFG_PORT_ANBE_USE_FSM mBIT(19) 10435/* 0x09d60 */ u64 ratemgmt_status_port[2]; 10436#define VXGE_HAL_RATEMGMT_STATUS_PORT_RATEMGMT_COMPLETE mBIT(3) 10437#define VXGE_HAL_RATEMGMT_STATUS_PORT_RATEMGMT_RATE mBIT(7) 10438#define VXGE_HAL_RATEMGMT_STATUS_PORT_RATEMGMT_MAC_MATCHES_PHY mBIT(11) 10439 u8 unused09d80[0x09d80 - 0x09d70]; 10440 10441/* 0x09d80 */ u64 ratemgmt_fixed_cfg_port[2]; 10442#define VXGE_HAL_RATEMGMT_FIXED_CFG_PORT_RESTART mBIT(7) 10443/* 0x09d90 */ u64 ratemgmt_antp_cfg_port[2]; 10444#define VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_RESTART mBIT(7) 10445#define VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_USE_PREAMBLE_EXT_PHY mBIT(11) 10446#define VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_USE_ACT_SEL mBIT(15) 10447#define VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_T_RETRY_PHY_QUERY(val)\ 10448 vBIT(val, 16, 4) 10449#define VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_T_WAIT_MDIO_RESP(val)\ 10450 vBIT(val, 20, 4) 10451#define VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_T_LDOWN_REAUTO_RESP(val)\ 10452 vBIT(val, 24, 4) 10453#define VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_ADVERTISE_10G mBIT(31) 10454#define VXGE_HAL_RATEMGMT_ANTP_CFG_PORT_ADVERTISE_1G mBIT(35) 10455/* 0x09da0 */ u64 ratemgmt_anbe_cfg_port[2]; 10456#define VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_RESTART mBIT(7) 10457#define VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_PARALLEL_DETECT_10G_KX4_ENABLE mBIT(11) 10458#define VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_PARALLEL_DETECT_1G_KX_ENABLE mBIT(15) 10459#define VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_T_SYNC_10G_KX4(val) vBIT(val, 16, 4) 10460#define VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_T_SYNC_1G_KX(val) vBIT(val, 20, 4) 10461#define VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_T_DME_EXCHANGE(val) vBIT(val, 24, 4) 10462#define VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_ADVERTISE_10G_KX4 mBIT(31) 10463#define VXGE_HAL_RATEMGMT_ANBE_CFG_PORT_ADVERTISE_1G_KX mBIT(35) 10464/* 0x09db0 */ u64 anbe_cfg_port[2]; 10465#define VXGE_HAL_ANBE_CFG_PORT_RESET_CFG_REGS(val) vBIT(val, 0, 8) 10466#define VXGE_HAL_ANBE_CFG_PORT_ALIGN_10G_KX4_OVERRIDE(val) vBIT(val, 10, 2) 10467#define VXGE_HAL_ANBE_CFG_PORT_SYNC_1G_KX_OVERRIDE(val) vBIT(val, 14, 2) 10468/* 0x09dc0 */ u64 anbe_mgr_ctrl_port[2]; 10469#define VXGE_HAL_ANBE_MGR_CTRL_PORT_WE mBIT(3) 10470#define VXGE_HAL_ANBE_MGR_CTRL_PORT_STROBE mBIT(7) 10471#define VXGE_HAL_ANBE_MGR_CTRL_PORT_ADDR(val) vBIT(val, 15, 9) 10472#define VXGE_HAL_ANBE_MGR_CTRL_PORT_DATA(val) vBIT(val, 32, 32) 10473 u8 unused09de0[0x09de0 - 0x09dd0]; 10474 10475/* 0x09de0 */ u64 anbe_fw_mstr_port[2]; 10476#define VXGE_HAL_ANBE_FW_MSTR_PORT_CONNECT_BEAN_TO_SERDES mBIT(3) 10477#define VXGE_HAL_ANBE_FW_MSTR_PORT_TX_ZEROES_TO_SERDES mBIT(7) 10478/* 0x09df0 */ u64 anbe_hwfsm_gen_status_port[2]; 10479#define VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_10G_KX4_USING_PD\ 10480 mBIT(3) 10481#define VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_10G_KX4_USING_DME\ 10482 mBIT(7) 10483#define VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_1G_KX_USING_PD\ 10484 mBIT(11) 10485#define VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_1G_KX_USING_DME\ 10486 mBIT(15) 10487#define VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_ANBEFSM_STATE(val)\ 10488 vBIT(val, 18, 6) 10489#define VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_BEAN_NEXT_PAGE_RECEIVED\ 10490 mBIT(27) 10491#define VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_BEAN_PARALLEL_DETECT_FAULT\ 10492 mBIT(31) 10493#define VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_BEAN_BASE_PAGE_RECEIVED\ 10494 mBIT(35) 10495#define VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_BEAN_AUTONEG_COMPLETE\ 10496 mBIT(39) 10497#define VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXP_NP_BEFORE_BP\ 10498 mBIT(43) 10499#define VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXP_AN_COMPL_BEFORE_BP\ 10500 mBIT(47) 10501#define VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXP_AN_COMPL_BEFORE_NP\ 10502 mBIT(51) 10503#define VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXP_MODE_WHEN_AN_COMPL\ 10504 mBIT(55) 10505#define VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_COUNT_BP(val)\ 10506 vBIT(val, 56, 4) 10507#define VXGE_HAL_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_COUNT_NP(val)\ 10508 vBIT(val, 60, 4) 10509/* 0x09e00 */ u64 anbe_hwfsm_bp_status_port[2]; 10510#define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_FEC_ENABLE mBIT(32) 10511#define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_FEC_ABILITY mBIT(33) 10512#define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_10G_KR_CAPABLE mBIT(40) 10513#define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_10G_KX4_CAPABLE mBIT(41) 10514#define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_1G_KX_CAPABLE mBIT(42) 10515#define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_TX_NONCE(val)\ 10516 vBIT(val, 43, 5) 10517#define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_NP mBIT(48) 10518#define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ACK mBIT(49) 10519#define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_REMOTE_FAULT mBIT(50) 10520#define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ASM_DIR mBIT(51) 10521#define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_PAUSE mBIT(53) 10522#define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ECHOED_NONCE(val)\ 10523 vBIT(val, 54, 5) 10524#define VXGE_HAL_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_SELECTOR_FIELD(val)\ 10525 vBIT(val, 59, 5) 10526/* 0x09e10 */ u64 anbe_hwfsm_np_status_port[2]; 10527#define VXGE_HAL_ANBE_HWFSM_NP_STATUS_PORT_RATEMGMT_NP_BITS_47_TO_32(val)\ 10528 vBIT(val, 16, 16) 10529#define VXGE_HAL_ANBE_HWFSM_NP_STATUS_PORT_RATEMGMT_NP_BITS_31_TO_0(val)\ 10530 vBIT(val, 32, 32) 10531 u8 unused09e30[0x09e30 - 0x09e20]; 10532 10533/* 0x09e30 */ u64 antp_gen_cfg_port[2]; 10534/* 0x09e40 */ u64 antp_hwfsm_gen_status_port[2]; 10535#define VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_10G mBIT(3) 10536#define VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_1G mBIT(7) 10537#define VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_ANTPFSM_STATE(val)\ 10538 vBIT(val, 10, 6) 10539#define VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_TIMEOUT mBIT(19) 10540#define VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_AUTONEG_COMPLETE mBIT(23) 10541#define VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_NO_LP_XNP\ 10542 mBIT(27) 10543#define VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_GOT_LP_XNP mBIT(31) 10544#define VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_MESSAGE_CODE\ 10545 mBIT(35) 10546#define VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_GOT_LP_MESSAGE_CODE_10G_1K\ 10547 mBIT(39) 10548#define VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_NO_HCD mBIT(43) 10549#define VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_FOUND_HCD mBIT(47) 10550#define VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_INVALID_RATE\ 10551 mBIT(51) 10552#define VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_VALID_RATE mBIT(55) 10553#define VXGE_HAL_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_PERSISTENT_LDOWN mBIT(59) 10554/* 0x09e50 */ u64 antp_hwfsm_bp_status_port[2]; 10555#define VXGE_HAL_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_NP mBIT(0) 10556#define VXGE_HAL_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ACK mBIT(1) 10557#define VXGE_HAL_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_RF mBIT(2) 10558#define VXGE_HAL_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_XNP mBIT(3) 10559#define VXGE_HAL_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ABILITY_FIELD(val)\ 10560 vBIT(val, 4, 7) 10561#define VXGE_HAL_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_SELECTOR_FIELD(val)\ 10562 vBIT(val, 11, 5) 10563/* 0x09e60 */ u64 antp_hwfsm_xnp_status_port[2]; 10564#define VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_NP mBIT(0) 10565#define VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_ACK mBIT(1) 10566#define VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_MP mBIT(2) 10567#define VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_ACK2 mBIT(3) 10568#define VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_TOGGLE mBIT(4) 10569#define VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_MESSAGE_CODE(val)\ 10570 vBIT(val, 5, 11) 10571#define VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_UNF_CODE_FIELD1(val)\ 10572 vBIT(val, 16, 16) 10573#define VXGE_HAL_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_UNF_CODE_FIELD2(val)\ 10574 vBIT(val, 32, 16) 10575/* 0x09e70 */ u64 mdio_mgr_access_port[2]; 10576#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_STROBE_ONE mBIT(3) 10577#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_OP_TYPE(val) vBIT(val, 5, 3) 10578#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_DEVAD(val) vBIT(val, 11, 5) 10579#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ADDR(val) vBIT(val, 16, 16) 10580#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_DATA(val) vBIT(val, 32, 16) 10581#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_ST_PATTERN(val) vBIT(val, 49, 2) 10582#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_PREAMBLE mBIT(51) 10583#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_PRTAD(val) vBIT(val, 55, 5) 10584#define VXGE_HAL_MDIO_MGR_ACCESS_PORT_STROBE_TWO mBIT(63) 10585 u8 unused09ea0[0x09ea0 - 0x09e80]; 10586 10587/* 0x09ea0 */ u64 mdio_gen_cfg_port[2]; 10588 10589 u8 unused0a200[0x0a200 - 0x09eb0]; 10590 10591/* 0x0a200 */ u64 xmac_vsport_choices_vh[17]; 10592#define VXGE_HAL_XMAC_VSPORT_CHOICES_VH_VSPORT_VECTOR(val) vBIT(val, 0, 17) 10593 u8 unused0a400[0x0a400 - 0x0a288]; 10594 10595/* 0x0a400 */ u64 rx_thresh_cfg_vp[17]; 10596#define VXGE_HAL_RX_THRESH_CFG_VP_PAUSE_LOW_THR(val) vBIT(val, 0, 8) 10597#define VXGE_HAL_RX_THRESH_CFG_VP_PAUSE_HIGH_THR(val) vBIT(val, 8, 8) 10598#define VXGE_HAL_RX_THRESH_CFG_VP_RED_THR_0(val) vBIT(val, 16, 8) 10599#define VXGE_HAL_RX_THRESH_CFG_VP_RED_THR_1(val) vBIT(val, 24, 8) 10600#define VXGE_HAL_RX_THRESH_CFG_VP_RED_THR_2(val) vBIT(val, 32, 8) 10601#define VXGE_HAL_RX_THRESH_CFG_VP_RED_THR_3(val) vBIT(val, 40, 8) 10602 u8 unused0ac00[0x0ac00 - 0x0a488]; 10603 10604/* 0x0ac00 */ u64 fau_adaptive_lro_vpath_enable; 10605#define VXGE_HAL_FAU_ADAPTIVE_LRO_VPATH_ENABLE_EN(val) vBIT(val, 0, 17) 10606/* 0x0ac08 */ u64 fau_adaptive_lro_base_sid_vp[17]; 10607#define VXGE_HAL_FAU_ADAPTIVE_LRO_BASE_SID_VP_VALUE(val) vBIT(val, 2, 6) 10608#define VXGE_HAL_FAU_ADAPTIVE_LRO_BASE_SID_VP_USE_HASH_WIDTH(val)\ 10609 vBIT(val, 11, 5) 10610 10611} vxge_hal_mrpcim_reg_t; 10612 10613__EXTERN_END_DECLS 10614 10615#endif /* VXGE_HAL_MRPCIM_REGS_H */ 10616