if_vge.c revision 227835
1/*- 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/vge/if_vge.c 227835 2011-11-22 20:45:09Z yongari $"); 35 36/* 37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 46 * combines a tri-speed ethernet MAC and PHY, with the following 47 * features: 48 * 49 * o Jumbo frame support up to 16K 50 * o Transmit and receive flow control 51 * o IPv4 checksum offload 52 * o VLAN tag insertion and stripping 53 * o TCP large send 54 * o 64-bit multicast hash table filter 55 * o 64 entry CAM filter 56 * o 16K RX FIFO and 48K TX FIFO memory 57 * o Interrupt moderation 58 * 59 * The VT6122 supports up to four transmit DMA queues. The descriptors 60 * in the transmit ring can address up to 7 data fragments; frames which 61 * span more than 7 data buffers must be coalesced, but in general the 62 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 63 * long. The receive descriptors address only a single buffer. 64 * 65 * There are two peculiar design issues with the VT6122. One is that 66 * receive data buffers must be aligned on a 32-bit boundary. This is 67 * not a problem where the VT6122 is used as a LOM device in x86-based 68 * systems, but on architectures that generate unaligned access traps, we 69 * have to do some copying. 70 * 71 * The other issue has to do with the way 64-bit addresses are handled. 72 * The DMA descriptors only allow you to specify 48 bits of addressing 73 * information. The remaining 16 bits are specified using one of the 74 * I/O registers. If you only have a 32-bit system, then this isn't 75 * an issue, but if you have a 64-bit system and more than 4GB of 76 * memory, you must have to make sure your network data buffers reside 77 * in the same 48-bit 'segment.' 78 * 79 * Special thanks to Ryan Fu at VIA Networking for providing documentation 80 * and sample NICs for testing. 81 */ 82 83#ifdef HAVE_KERNEL_OPTION_HEADERS 84#include "opt_device_polling.h" 85#endif 86 87#include <sys/param.h> 88#include <sys/endian.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/module.h> 94#include <sys/kernel.h> 95#include <sys/socket.h> 96#include <sys/sysctl.h> 97 98#include <net/if.h> 99#include <net/if_arp.h> 100#include <net/ethernet.h> 101#include <net/if_dl.h> 102#include <net/if_media.h> 103#include <net/if_types.h> 104#include <net/if_vlan_var.h> 105 106#include <net/bpf.h> 107 108#include <machine/bus.h> 109#include <machine/resource.h> 110#include <sys/bus.h> 111#include <sys/rman.h> 112 113#include <dev/mii/mii.h> 114#include <dev/mii/miivar.h> 115 116#include <dev/pci/pcireg.h> 117#include <dev/pci/pcivar.h> 118 119MODULE_DEPEND(vge, pci, 1, 1, 1); 120MODULE_DEPEND(vge, ether, 1, 1, 1); 121MODULE_DEPEND(vge, miibus, 1, 1, 1); 122 123/* "device miibus" required. See GENERIC if you get errors here. */ 124#include "miibus_if.h" 125 126#include <dev/vge/if_vgereg.h> 127#include <dev/vge/if_vgevar.h> 128 129#define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 130 131/* Tunables */ 132static int msi_disable = 0; 133TUNABLE_INT("hw.vge.msi_disable", &msi_disable); 134 135/* 136 * The SQE error counter of MIB seems to report bogus value. 137 * Vendor's workaround does not seem to work on PCIe based 138 * controllers. Disable it until we find better workaround. 139 */ 140#undef VGE_ENABLE_SQEERR 141 142/* 143 * Various supported device vendors/types and their names. 144 */ 145static struct vge_type vge_devs[] = { 146 { VIA_VENDORID, VIA_DEVICEID_61XX, 147 "VIA Networking Velocity Gigabit Ethernet" }, 148 { 0, 0, NULL } 149}; 150 151static int vge_attach(device_t); 152static int vge_detach(device_t); 153static int vge_probe(device_t); 154static int vge_resume(device_t); 155static int vge_shutdown(device_t); 156static int vge_suspend(device_t); 157 158static void vge_cam_clear(struct vge_softc *); 159static int vge_cam_set(struct vge_softc *, uint8_t *); 160static void vge_clrwol(struct vge_softc *); 161static void vge_discard_rxbuf(struct vge_softc *, int); 162static int vge_dma_alloc(struct vge_softc *); 163static void vge_dma_free(struct vge_softc *); 164static void vge_dmamap_cb(void *, bus_dma_segment_t *, int, int); 165#ifdef VGE_EEPROM 166static void vge_eeprom_getword(struct vge_softc *, int, uint16_t *); 167#endif 168static int vge_encap(struct vge_softc *, struct mbuf **); 169#ifndef __NO_STRICT_ALIGNMENT 170static __inline void 171 vge_fixup_rx(struct mbuf *); 172#endif 173static void vge_freebufs(struct vge_softc *); 174static void vge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 175static int vge_ifmedia_upd(struct ifnet *); 176static int vge_ifmedia_upd_locked(struct vge_softc *); 177static void vge_init(void *); 178static void vge_init_locked(struct vge_softc *); 179static void vge_intr(void *); 180static void vge_intr_holdoff(struct vge_softc *); 181static int vge_ioctl(struct ifnet *, u_long, caddr_t); 182static void vge_link_statchg(void *); 183static int vge_miibus_readreg(device_t, int, int); 184static int vge_miibus_writereg(device_t, int, int, int); 185static void vge_miipoll_start(struct vge_softc *); 186static void vge_miipoll_stop(struct vge_softc *); 187static int vge_newbuf(struct vge_softc *, int); 188static void vge_read_eeprom(struct vge_softc *, caddr_t, int, int, int); 189static void vge_reset(struct vge_softc *); 190static int vge_rx_list_init(struct vge_softc *); 191static int vge_rxeof(struct vge_softc *, int); 192static void vge_rxfilter(struct vge_softc *); 193static void vge_setmedia(struct vge_softc *); 194static void vge_setvlan(struct vge_softc *); 195static void vge_setwol(struct vge_softc *); 196static void vge_start(struct ifnet *); 197static void vge_start_locked(struct ifnet *); 198static void vge_stats_clear(struct vge_softc *); 199static void vge_stats_update(struct vge_softc *); 200static void vge_stop(struct vge_softc *); 201static void vge_sysctl_node(struct vge_softc *); 202static int vge_tx_list_init(struct vge_softc *); 203static void vge_txeof(struct vge_softc *); 204static void vge_watchdog(void *); 205 206static device_method_t vge_methods[] = { 207 /* Device interface */ 208 DEVMETHOD(device_probe, vge_probe), 209 DEVMETHOD(device_attach, vge_attach), 210 DEVMETHOD(device_detach, vge_detach), 211 DEVMETHOD(device_suspend, vge_suspend), 212 DEVMETHOD(device_resume, vge_resume), 213 DEVMETHOD(device_shutdown, vge_shutdown), 214 215 /* bus interface */ 216 DEVMETHOD(bus_print_child, bus_generic_print_child), 217 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 218 219 /* MII interface */ 220 DEVMETHOD(miibus_readreg, vge_miibus_readreg), 221 DEVMETHOD(miibus_writereg, vge_miibus_writereg), 222 223 { 0, 0 } 224}; 225 226static driver_t vge_driver = { 227 "vge", 228 vge_methods, 229 sizeof(struct vge_softc) 230}; 231 232static devclass_t vge_devclass; 233 234DRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0); 235DRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0); 236 237#ifdef VGE_EEPROM 238/* 239 * Read a word of data stored in the EEPROM at address 'addr.' 240 */ 241static void 242vge_eeprom_getword(struct vge_softc *sc, int addr, uint16_t *dest) 243{ 244 int i; 245 uint16_t word = 0; 246 247 /* 248 * Enter EEPROM embedded programming mode. In order to 249 * access the EEPROM at all, we first have to set the 250 * EELOAD bit in the CHIPCFG2 register. 251 */ 252 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 253 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 254 255 /* Select the address of the word we want to read */ 256 CSR_WRITE_1(sc, VGE_EEADDR, addr); 257 258 /* Issue read command */ 259 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 260 261 /* Wait for the done bit to be set. */ 262 for (i = 0; i < VGE_TIMEOUT; i++) { 263 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 264 break; 265 } 266 267 if (i == VGE_TIMEOUT) { 268 device_printf(sc->vge_dev, "EEPROM read timed out\n"); 269 *dest = 0; 270 return; 271 } 272 273 /* Read the result */ 274 word = CSR_READ_2(sc, VGE_EERDDAT); 275 276 /* Turn off EEPROM access mode. */ 277 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 278 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 279 280 *dest = word; 281} 282#endif 283 284/* 285 * Read a sequence of words from the EEPROM. 286 */ 287static void 288vge_read_eeprom(struct vge_softc *sc, caddr_t dest, int off, int cnt, int swap) 289{ 290 int i; 291#ifdef VGE_EEPROM 292 uint16_t word = 0, *ptr; 293 294 for (i = 0; i < cnt; i++) { 295 vge_eeprom_getword(sc, off + i, &word); 296 ptr = (uint16_t *)(dest + (i * 2)); 297 if (swap) 298 *ptr = ntohs(word); 299 else 300 *ptr = word; 301 } 302#else 303 for (i = 0; i < ETHER_ADDR_LEN; i++) 304 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 305#endif 306} 307 308static void 309vge_miipoll_stop(struct vge_softc *sc) 310{ 311 int i; 312 313 CSR_WRITE_1(sc, VGE_MIICMD, 0); 314 315 for (i = 0; i < VGE_TIMEOUT; i++) { 316 DELAY(1); 317 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 318 break; 319 } 320 321 if (i == VGE_TIMEOUT) 322 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 323} 324 325static void 326vge_miipoll_start(struct vge_softc *sc) 327{ 328 int i; 329 330 /* First, make sure we're idle. */ 331 332 CSR_WRITE_1(sc, VGE_MIICMD, 0); 333 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 334 335 for (i = 0; i < VGE_TIMEOUT; i++) { 336 DELAY(1); 337 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 338 break; 339 } 340 341 if (i == VGE_TIMEOUT) { 342 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 343 return; 344 } 345 346 /* Now enable auto poll mode. */ 347 348 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 349 350 /* And make sure it started. */ 351 352 for (i = 0; i < VGE_TIMEOUT; i++) { 353 DELAY(1); 354 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 355 break; 356 } 357 358 if (i == VGE_TIMEOUT) 359 device_printf(sc->vge_dev, "failed to start MII autopoll\n"); 360} 361 362static int 363vge_miibus_readreg(device_t dev, int phy, int reg) 364{ 365 struct vge_softc *sc; 366 int i; 367 uint16_t rval = 0; 368 369 sc = device_get_softc(dev); 370 371 vge_miipoll_stop(sc); 372 373 /* Specify the register we want to read. */ 374 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 375 376 /* Issue read command. */ 377 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 378 379 /* Wait for the read command bit to self-clear. */ 380 for (i = 0; i < VGE_TIMEOUT; i++) { 381 DELAY(1); 382 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 383 break; 384 } 385 386 if (i == VGE_TIMEOUT) 387 device_printf(sc->vge_dev, "MII read timed out\n"); 388 else 389 rval = CSR_READ_2(sc, VGE_MIIDATA); 390 391 vge_miipoll_start(sc); 392 393 return (rval); 394} 395 396static int 397vge_miibus_writereg(device_t dev, int phy, int reg, int data) 398{ 399 struct vge_softc *sc; 400 int i, rval = 0; 401 402 sc = device_get_softc(dev); 403 404 vge_miipoll_stop(sc); 405 406 /* Specify the register we want to write. */ 407 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 408 409 /* Specify the data we want to write. */ 410 CSR_WRITE_2(sc, VGE_MIIDATA, data); 411 412 /* Issue write command. */ 413 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 414 415 /* Wait for the write command bit to self-clear. */ 416 for (i = 0; i < VGE_TIMEOUT; i++) { 417 DELAY(1); 418 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 419 break; 420 } 421 422 if (i == VGE_TIMEOUT) { 423 device_printf(sc->vge_dev, "MII write timed out\n"); 424 rval = EIO; 425 } 426 427 vge_miipoll_start(sc); 428 429 return (rval); 430} 431 432static void 433vge_cam_clear(struct vge_softc *sc) 434{ 435 int i; 436 437 /* 438 * Turn off all the mask bits. This tells the chip 439 * that none of the entries in the CAM filter are valid. 440 * desired entries will be enabled as we fill the filter in. 441 */ 442 443 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 444 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 445 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 446 for (i = 0; i < 8; i++) 447 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 448 449 /* Clear the VLAN filter too. */ 450 451 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 452 for (i = 0; i < 8; i++) 453 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 454 455 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 456 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 457 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 458 459 sc->vge_camidx = 0; 460} 461 462static int 463vge_cam_set(struct vge_softc *sc, uint8_t *addr) 464{ 465 int i, error = 0; 466 467 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 468 return (ENOSPC); 469 470 /* Select the CAM data page. */ 471 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 472 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 473 474 /* Set the filter entry we want to update and enable writing. */ 475 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 476 477 /* Write the address to the CAM registers */ 478 for (i = 0; i < ETHER_ADDR_LEN; i++) 479 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 480 481 /* Issue a write command. */ 482 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 483 484 /* Wake for it to clear. */ 485 for (i = 0; i < VGE_TIMEOUT; i++) { 486 DELAY(1); 487 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 488 break; 489 } 490 491 if (i == VGE_TIMEOUT) { 492 device_printf(sc->vge_dev, "setting CAM filter failed\n"); 493 error = EIO; 494 goto fail; 495 } 496 497 /* Select the CAM mask page. */ 498 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 499 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 500 501 /* Set the mask bit that enables this filter. */ 502 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 503 1<<(sc->vge_camidx & 7)); 504 505 sc->vge_camidx++; 506 507fail: 508 /* Turn off access to CAM. */ 509 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 510 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 511 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 512 513 return (error); 514} 515 516static void 517vge_setvlan(struct vge_softc *sc) 518{ 519 struct ifnet *ifp; 520 uint8_t cfg; 521 522 VGE_LOCK_ASSERT(sc); 523 524 ifp = sc->vge_ifp; 525 cfg = CSR_READ_1(sc, VGE_RXCFG); 526 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 527 cfg |= VGE_VTAG_OPT2; 528 else 529 cfg &= ~VGE_VTAG_OPT2; 530 CSR_WRITE_1(sc, VGE_RXCFG, cfg); 531} 532 533/* 534 * Program the multicast filter. We use the 64-entry CAM filter 535 * for perfect filtering. If there's more than 64 multicast addresses, 536 * we use the hash filter instead. 537 */ 538static void 539vge_rxfilter(struct vge_softc *sc) 540{ 541 struct ifnet *ifp; 542 struct ifmultiaddr *ifma; 543 uint32_t h, hashes[2]; 544 uint8_t rxcfg; 545 int error = 0; 546 547 VGE_LOCK_ASSERT(sc); 548 549 /* First, zot all the multicast entries. */ 550 hashes[0] = 0; 551 hashes[1] = 0; 552 553 rxcfg = CSR_READ_1(sc, VGE_RXCTL); 554 rxcfg &= ~(VGE_RXCTL_RX_MCAST | VGE_RXCTL_RX_BCAST | 555 VGE_RXCTL_RX_PROMISC); 556 /* 557 * Always allow VLAN oversized frames and frames for 558 * this host. 559 */ 560 rxcfg |= VGE_RXCTL_RX_GIANT | VGE_RXCTL_RX_UCAST; 561 562 ifp = sc->vge_ifp; 563 if ((ifp->if_flags & IFF_BROADCAST) != 0) 564 rxcfg |= VGE_RXCTL_RX_BCAST; 565 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 566 if ((ifp->if_flags & IFF_PROMISC) != 0) 567 rxcfg |= VGE_RXCTL_RX_PROMISC; 568 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 569 hashes[0] = 0xFFFFFFFF; 570 hashes[1] = 0xFFFFFFFF; 571 } 572 goto done; 573 } 574 575 vge_cam_clear(sc); 576 /* Now program new ones */ 577 if_maddr_rlock(ifp); 578 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 579 if (ifma->ifma_addr->sa_family != AF_LINK) 580 continue; 581 error = vge_cam_set(sc, 582 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 583 if (error) 584 break; 585 } 586 587 /* If there were too many addresses, use the hash filter. */ 588 if (error) { 589 vge_cam_clear(sc); 590 591 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 592 if (ifma->ifma_addr->sa_family != AF_LINK) 593 continue; 594 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 595 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 596 if (h < 32) 597 hashes[0] |= (1 << h); 598 else 599 hashes[1] |= (1 << (h - 32)); 600 } 601 } 602 if_maddr_runlock(ifp); 603 604done: 605 if (hashes[0] != 0 || hashes[1] != 0) 606 rxcfg |= VGE_RXCTL_RX_MCAST; 607 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 608 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 609 CSR_WRITE_1(sc, VGE_RXCTL, rxcfg); 610} 611 612static void 613vge_reset(struct vge_softc *sc) 614{ 615 int i; 616 617 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 618 619 for (i = 0; i < VGE_TIMEOUT; i++) { 620 DELAY(5); 621 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 622 break; 623 } 624 625 if (i == VGE_TIMEOUT) { 626 device_printf(sc->vge_dev, "soft reset timed out\n"); 627 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 628 DELAY(2000); 629 } 630 631 DELAY(5000); 632} 633 634/* 635 * Probe for a VIA gigabit chip. Check the PCI vendor and device 636 * IDs against our list and return a device name if we find a match. 637 */ 638static int 639vge_probe(device_t dev) 640{ 641 struct vge_type *t; 642 643 t = vge_devs; 644 645 while (t->vge_name != NULL) { 646 if ((pci_get_vendor(dev) == t->vge_vid) && 647 (pci_get_device(dev) == t->vge_did)) { 648 device_set_desc(dev, t->vge_name); 649 return (BUS_PROBE_DEFAULT); 650 } 651 t++; 652 } 653 654 return (ENXIO); 655} 656 657/* 658 * Map a single buffer address. 659 */ 660 661struct vge_dmamap_arg { 662 bus_addr_t vge_busaddr; 663}; 664 665static void 666vge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 667{ 668 struct vge_dmamap_arg *ctx; 669 670 if (error != 0) 671 return; 672 673 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 674 675 ctx = (struct vge_dmamap_arg *)arg; 676 ctx->vge_busaddr = segs[0].ds_addr; 677} 678 679static int 680vge_dma_alloc(struct vge_softc *sc) 681{ 682 struct vge_dmamap_arg ctx; 683 struct vge_txdesc *txd; 684 struct vge_rxdesc *rxd; 685 bus_addr_t lowaddr, tx_ring_end, rx_ring_end; 686 int error, i; 687 688 /* 689 * It seems old PCI controllers do not support DAC. DAC 690 * configuration can be enabled by accessing VGE_CHIPCFG3 691 * register but honor EEPROM configuration instead of 692 * blindly overriding DAC configuration. PCIe based 693 * controllers are supposed to support 64bit DMA so enable 694 * 64bit DMA on these controllers. 695 */ 696 if ((sc->vge_flags & VGE_FLAG_PCIE) != 0) 697 lowaddr = BUS_SPACE_MAXADDR; 698 else 699 lowaddr = BUS_SPACE_MAXADDR_32BIT; 700 701again: 702 /* Create parent ring tag. */ 703 error = bus_dma_tag_create(bus_get_dma_tag(sc->vge_dev),/* parent */ 704 1, 0, /* algnmnt, boundary */ 705 lowaddr, /* lowaddr */ 706 BUS_SPACE_MAXADDR, /* highaddr */ 707 NULL, NULL, /* filter, filterarg */ 708 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 709 0, /* nsegments */ 710 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 711 0, /* flags */ 712 NULL, NULL, /* lockfunc, lockarg */ 713 &sc->vge_cdata.vge_ring_tag); 714 if (error != 0) { 715 device_printf(sc->vge_dev, 716 "could not create parent DMA tag.\n"); 717 goto fail; 718 } 719 720 /* Create tag for Tx ring. */ 721 error = bus_dma_tag_create(sc->vge_cdata.vge_ring_tag,/* parent */ 722 VGE_TX_RING_ALIGN, 0, /* algnmnt, boundary */ 723 BUS_SPACE_MAXADDR, /* lowaddr */ 724 BUS_SPACE_MAXADDR, /* highaddr */ 725 NULL, NULL, /* filter, filterarg */ 726 VGE_TX_LIST_SZ, /* maxsize */ 727 1, /* nsegments */ 728 VGE_TX_LIST_SZ, /* maxsegsize */ 729 0, /* flags */ 730 NULL, NULL, /* lockfunc, lockarg */ 731 &sc->vge_cdata.vge_tx_ring_tag); 732 if (error != 0) { 733 device_printf(sc->vge_dev, 734 "could not allocate Tx ring DMA tag.\n"); 735 goto fail; 736 } 737 738 /* Create tag for Rx ring. */ 739 error = bus_dma_tag_create(sc->vge_cdata.vge_ring_tag,/* parent */ 740 VGE_RX_RING_ALIGN, 0, /* algnmnt, boundary */ 741 BUS_SPACE_MAXADDR, /* lowaddr */ 742 BUS_SPACE_MAXADDR, /* highaddr */ 743 NULL, NULL, /* filter, filterarg */ 744 VGE_RX_LIST_SZ, /* maxsize */ 745 1, /* nsegments */ 746 VGE_RX_LIST_SZ, /* maxsegsize */ 747 0, /* flags */ 748 NULL, NULL, /* lockfunc, lockarg */ 749 &sc->vge_cdata.vge_rx_ring_tag); 750 if (error != 0) { 751 device_printf(sc->vge_dev, 752 "could not allocate Rx ring DMA tag.\n"); 753 goto fail; 754 } 755 756 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 757 error = bus_dmamem_alloc(sc->vge_cdata.vge_tx_ring_tag, 758 (void **)&sc->vge_rdata.vge_tx_ring, 759 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 760 &sc->vge_cdata.vge_tx_ring_map); 761 if (error != 0) { 762 device_printf(sc->vge_dev, 763 "could not allocate DMA'able memory for Tx ring.\n"); 764 goto fail; 765 } 766 767 ctx.vge_busaddr = 0; 768 error = bus_dmamap_load(sc->vge_cdata.vge_tx_ring_tag, 769 sc->vge_cdata.vge_tx_ring_map, sc->vge_rdata.vge_tx_ring, 770 VGE_TX_LIST_SZ, vge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 771 if (error != 0 || ctx.vge_busaddr == 0) { 772 device_printf(sc->vge_dev, 773 "could not load DMA'able memory for Tx ring.\n"); 774 goto fail; 775 } 776 sc->vge_rdata.vge_tx_ring_paddr = ctx.vge_busaddr; 777 778 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 779 error = bus_dmamem_alloc(sc->vge_cdata.vge_rx_ring_tag, 780 (void **)&sc->vge_rdata.vge_rx_ring, 781 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 782 &sc->vge_cdata.vge_rx_ring_map); 783 if (error != 0) { 784 device_printf(sc->vge_dev, 785 "could not allocate DMA'able memory for Rx ring.\n"); 786 goto fail; 787 } 788 789 ctx.vge_busaddr = 0; 790 error = bus_dmamap_load(sc->vge_cdata.vge_rx_ring_tag, 791 sc->vge_cdata.vge_rx_ring_map, sc->vge_rdata.vge_rx_ring, 792 VGE_RX_LIST_SZ, vge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 793 if (error != 0 || ctx.vge_busaddr == 0) { 794 device_printf(sc->vge_dev, 795 "could not load DMA'able memory for Rx ring.\n"); 796 goto fail; 797 } 798 sc->vge_rdata.vge_rx_ring_paddr = ctx.vge_busaddr; 799 800 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 801 tx_ring_end = sc->vge_rdata.vge_tx_ring_paddr + VGE_TX_LIST_SZ; 802 rx_ring_end = sc->vge_rdata.vge_rx_ring_paddr + VGE_RX_LIST_SZ; 803 if ((VGE_ADDR_HI(tx_ring_end) != 804 VGE_ADDR_HI(sc->vge_rdata.vge_tx_ring_paddr)) || 805 (VGE_ADDR_HI(rx_ring_end) != 806 VGE_ADDR_HI(sc->vge_rdata.vge_rx_ring_paddr)) || 807 VGE_ADDR_HI(tx_ring_end) != VGE_ADDR_HI(rx_ring_end)) { 808 device_printf(sc->vge_dev, "4GB boundary crossed, " 809 "switching to 32bit DMA address mode.\n"); 810 vge_dma_free(sc); 811 /* Limit DMA address space to 32bit and try again. */ 812 lowaddr = BUS_SPACE_MAXADDR_32BIT; 813 goto again; 814 } 815 816 if ((sc->vge_flags & VGE_FLAG_PCIE) != 0) 817 lowaddr = VGE_BUF_DMA_MAXADDR; 818 else 819 lowaddr = BUS_SPACE_MAXADDR_32BIT; 820 /* Create parent buffer tag. */ 821 error = bus_dma_tag_create(bus_get_dma_tag(sc->vge_dev),/* parent */ 822 1, 0, /* algnmnt, boundary */ 823 lowaddr, /* lowaddr */ 824 BUS_SPACE_MAXADDR, /* highaddr */ 825 NULL, NULL, /* filter, filterarg */ 826 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 827 0, /* nsegments */ 828 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 829 0, /* flags */ 830 NULL, NULL, /* lockfunc, lockarg */ 831 &sc->vge_cdata.vge_buffer_tag); 832 if (error != 0) { 833 device_printf(sc->vge_dev, 834 "could not create parent buffer DMA tag.\n"); 835 goto fail; 836 } 837 838 /* Create tag for Tx buffers. */ 839 error = bus_dma_tag_create(sc->vge_cdata.vge_buffer_tag,/* parent */ 840 1, 0, /* algnmnt, boundary */ 841 BUS_SPACE_MAXADDR, /* lowaddr */ 842 BUS_SPACE_MAXADDR, /* highaddr */ 843 NULL, NULL, /* filter, filterarg */ 844 MCLBYTES * VGE_MAXTXSEGS, /* maxsize */ 845 VGE_MAXTXSEGS, /* nsegments */ 846 MCLBYTES, /* maxsegsize */ 847 0, /* flags */ 848 NULL, NULL, /* lockfunc, lockarg */ 849 &sc->vge_cdata.vge_tx_tag); 850 if (error != 0) { 851 device_printf(sc->vge_dev, "could not create Tx DMA tag.\n"); 852 goto fail; 853 } 854 855 /* Create tag for Rx buffers. */ 856 error = bus_dma_tag_create(sc->vge_cdata.vge_buffer_tag,/* parent */ 857 VGE_RX_BUF_ALIGN, 0, /* algnmnt, boundary */ 858 BUS_SPACE_MAXADDR, /* lowaddr */ 859 BUS_SPACE_MAXADDR, /* highaddr */ 860 NULL, NULL, /* filter, filterarg */ 861 MCLBYTES, /* maxsize */ 862 1, /* nsegments */ 863 MCLBYTES, /* maxsegsize */ 864 0, /* flags */ 865 NULL, NULL, /* lockfunc, lockarg */ 866 &sc->vge_cdata.vge_rx_tag); 867 if (error != 0) { 868 device_printf(sc->vge_dev, "could not create Rx DMA tag.\n"); 869 goto fail; 870 } 871 872 /* Create DMA maps for Tx buffers. */ 873 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 874 txd = &sc->vge_cdata.vge_txdesc[i]; 875 txd->tx_m = NULL; 876 txd->tx_dmamap = NULL; 877 error = bus_dmamap_create(sc->vge_cdata.vge_tx_tag, 0, 878 &txd->tx_dmamap); 879 if (error != 0) { 880 device_printf(sc->vge_dev, 881 "could not create Tx dmamap.\n"); 882 goto fail; 883 } 884 } 885 /* Create DMA maps for Rx buffers. */ 886 if ((error = bus_dmamap_create(sc->vge_cdata.vge_rx_tag, 0, 887 &sc->vge_cdata.vge_rx_sparemap)) != 0) { 888 device_printf(sc->vge_dev, 889 "could not create spare Rx dmamap.\n"); 890 goto fail; 891 } 892 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 893 rxd = &sc->vge_cdata.vge_rxdesc[i]; 894 rxd->rx_m = NULL; 895 rxd->rx_dmamap = NULL; 896 error = bus_dmamap_create(sc->vge_cdata.vge_rx_tag, 0, 897 &rxd->rx_dmamap); 898 if (error != 0) { 899 device_printf(sc->vge_dev, 900 "could not create Rx dmamap.\n"); 901 goto fail; 902 } 903 } 904 905fail: 906 return (error); 907} 908 909static void 910vge_dma_free(struct vge_softc *sc) 911{ 912 struct vge_txdesc *txd; 913 struct vge_rxdesc *rxd; 914 int i; 915 916 /* Tx ring. */ 917 if (sc->vge_cdata.vge_tx_ring_tag != NULL) { 918 if (sc->vge_cdata.vge_tx_ring_map) 919 bus_dmamap_unload(sc->vge_cdata.vge_tx_ring_tag, 920 sc->vge_cdata.vge_tx_ring_map); 921 if (sc->vge_cdata.vge_tx_ring_map && 922 sc->vge_rdata.vge_tx_ring) 923 bus_dmamem_free(sc->vge_cdata.vge_tx_ring_tag, 924 sc->vge_rdata.vge_tx_ring, 925 sc->vge_cdata.vge_tx_ring_map); 926 sc->vge_rdata.vge_tx_ring = NULL; 927 sc->vge_cdata.vge_tx_ring_map = NULL; 928 bus_dma_tag_destroy(sc->vge_cdata.vge_tx_ring_tag); 929 sc->vge_cdata.vge_tx_ring_tag = NULL; 930 } 931 /* Rx ring. */ 932 if (sc->vge_cdata.vge_rx_ring_tag != NULL) { 933 if (sc->vge_cdata.vge_rx_ring_map) 934 bus_dmamap_unload(sc->vge_cdata.vge_rx_ring_tag, 935 sc->vge_cdata.vge_rx_ring_map); 936 if (sc->vge_cdata.vge_rx_ring_map && 937 sc->vge_rdata.vge_rx_ring) 938 bus_dmamem_free(sc->vge_cdata.vge_rx_ring_tag, 939 sc->vge_rdata.vge_rx_ring, 940 sc->vge_cdata.vge_rx_ring_map); 941 sc->vge_rdata.vge_rx_ring = NULL; 942 sc->vge_cdata.vge_rx_ring_map = NULL; 943 bus_dma_tag_destroy(sc->vge_cdata.vge_rx_ring_tag); 944 sc->vge_cdata.vge_rx_ring_tag = NULL; 945 } 946 /* Tx buffers. */ 947 if (sc->vge_cdata.vge_tx_tag != NULL) { 948 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 949 txd = &sc->vge_cdata.vge_txdesc[i]; 950 if (txd->tx_dmamap != NULL) { 951 bus_dmamap_destroy(sc->vge_cdata.vge_tx_tag, 952 txd->tx_dmamap); 953 txd->tx_dmamap = NULL; 954 } 955 } 956 bus_dma_tag_destroy(sc->vge_cdata.vge_tx_tag); 957 sc->vge_cdata.vge_tx_tag = NULL; 958 } 959 /* Rx buffers. */ 960 if (sc->vge_cdata.vge_rx_tag != NULL) { 961 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 962 rxd = &sc->vge_cdata.vge_rxdesc[i]; 963 if (rxd->rx_dmamap != NULL) { 964 bus_dmamap_destroy(sc->vge_cdata.vge_rx_tag, 965 rxd->rx_dmamap); 966 rxd->rx_dmamap = NULL; 967 } 968 } 969 if (sc->vge_cdata.vge_rx_sparemap != NULL) { 970 bus_dmamap_destroy(sc->vge_cdata.vge_rx_tag, 971 sc->vge_cdata.vge_rx_sparemap); 972 sc->vge_cdata.vge_rx_sparemap = NULL; 973 } 974 bus_dma_tag_destroy(sc->vge_cdata.vge_rx_tag); 975 sc->vge_cdata.vge_rx_tag = NULL; 976 } 977 978 if (sc->vge_cdata.vge_buffer_tag != NULL) { 979 bus_dma_tag_destroy(sc->vge_cdata.vge_buffer_tag); 980 sc->vge_cdata.vge_buffer_tag = NULL; 981 } 982 if (sc->vge_cdata.vge_ring_tag != NULL) { 983 bus_dma_tag_destroy(sc->vge_cdata.vge_ring_tag); 984 sc->vge_cdata.vge_ring_tag = NULL; 985 } 986} 987 988/* 989 * Attach the interface. Allocate softc structures, do ifmedia 990 * setup and ethernet/BPF attach. 991 */ 992static int 993vge_attach(device_t dev) 994{ 995 u_char eaddr[ETHER_ADDR_LEN]; 996 struct vge_softc *sc; 997 struct ifnet *ifp; 998 int error = 0, cap, i, msic, rid; 999 1000 sc = device_get_softc(dev); 1001 sc->vge_dev = dev; 1002 1003 mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1004 MTX_DEF); 1005 callout_init_mtx(&sc->vge_watchdog, &sc->vge_mtx, 0); 1006 1007 /* 1008 * Map control/status registers. 1009 */ 1010 pci_enable_busmaster(dev); 1011 1012 rid = PCIR_BAR(1); 1013 sc->vge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1014 RF_ACTIVE); 1015 1016 if (sc->vge_res == NULL) { 1017 device_printf(dev, "couldn't map ports/memory\n"); 1018 error = ENXIO; 1019 goto fail; 1020 } 1021 1022 if (pci_find_cap(dev, PCIY_EXPRESS, &cap) == 0) { 1023 sc->vge_flags |= VGE_FLAG_PCIE; 1024 sc->vge_expcap = cap; 1025 } else 1026 sc->vge_flags |= VGE_FLAG_JUMBO; 1027 if (pci_find_cap(dev, PCIY_PMG, &cap) == 0) { 1028 sc->vge_flags |= VGE_FLAG_PMCAP; 1029 sc->vge_pmcap = cap; 1030 } 1031 rid = 0; 1032 msic = pci_msi_count(dev); 1033 if (msi_disable == 0 && msic > 0) { 1034 msic = 1; 1035 if (pci_alloc_msi(dev, &msic) == 0) { 1036 if (msic == 1) { 1037 sc->vge_flags |= VGE_FLAG_MSI; 1038 device_printf(dev, "Using %d MSI message\n", 1039 msic); 1040 rid = 1; 1041 } else 1042 pci_release_msi(dev); 1043 } 1044 } 1045 1046 /* Allocate interrupt */ 1047 sc->vge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1048 ((sc->vge_flags & VGE_FLAG_MSI) ? 0 : RF_SHAREABLE) | RF_ACTIVE); 1049 if (sc->vge_irq == NULL) { 1050 device_printf(dev, "couldn't map interrupt\n"); 1051 error = ENXIO; 1052 goto fail; 1053 } 1054 1055 /* Reset the adapter. */ 1056 vge_reset(sc); 1057 /* Reload EEPROM. */ 1058 CSR_WRITE_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 1059 for (i = 0; i < VGE_TIMEOUT; i++) { 1060 DELAY(5); 1061 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 1062 break; 1063 } 1064 if (i == VGE_TIMEOUT) 1065 device_printf(dev, "EEPROM reload timed out\n"); 1066 /* 1067 * Clear PACPI as EEPROM reload will set the bit. Otherwise 1068 * MAC will receive magic packet which in turn confuses 1069 * controller. 1070 */ 1071 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 1072 1073 /* 1074 * Get station address from the EEPROM. 1075 */ 1076 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 1077 /* 1078 * Save configured PHY address. 1079 * It seems the PHY address of PCIe controllers just 1080 * reflects media jump strapping status so we assume the 1081 * internal PHY address of PCIe controller is at 1. 1082 */ 1083 if ((sc->vge_flags & VGE_FLAG_PCIE) != 0) 1084 sc->vge_phyaddr = 1; 1085 else 1086 sc->vge_phyaddr = CSR_READ_1(sc, VGE_MIICFG) & 1087 VGE_MIICFG_PHYADDR; 1088 /* Clear WOL and take hardware from powerdown. */ 1089 vge_clrwol(sc); 1090 vge_sysctl_node(sc); 1091 error = vge_dma_alloc(sc); 1092 if (error) 1093 goto fail; 1094 1095 ifp = sc->vge_ifp = if_alloc(IFT_ETHER); 1096 if (ifp == NULL) { 1097 device_printf(dev, "can not if_alloc()\n"); 1098 error = ENOSPC; 1099 goto fail; 1100 } 1101 1102 vge_miipoll_start(sc); 1103 /* Do MII setup */ 1104 error = mii_attach(dev, &sc->vge_miibus, ifp, vge_ifmedia_upd, 1105 vge_ifmedia_sts, BMSR_DEFCAPMASK, sc->vge_phyaddr, MII_OFFSET_ANY, 1106 0); 1107 if (error != 0) { 1108 device_printf(dev, "attaching PHYs failed\n"); 1109 goto fail; 1110 } 1111 1112 ifp->if_softc = sc; 1113 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1114 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1115 ifp->if_ioctl = vge_ioctl; 1116 ifp->if_capabilities = IFCAP_VLAN_MTU; 1117 ifp->if_start = vge_start; 1118 ifp->if_hwassist = VGE_CSUM_FEATURES; 1119 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | 1120 IFCAP_VLAN_HWTAGGING; 1121 if ((sc->vge_flags & VGE_FLAG_PMCAP) != 0) 1122 ifp->if_capabilities |= IFCAP_WOL; 1123 ifp->if_capenable = ifp->if_capabilities; 1124#ifdef DEVICE_POLLING 1125 ifp->if_capabilities |= IFCAP_POLLING; 1126#endif 1127 ifp->if_init = vge_init; 1128 IFQ_SET_MAXLEN(&ifp->if_snd, VGE_TX_DESC_CNT - 1); 1129 ifp->if_snd.ifq_drv_maxlen = VGE_TX_DESC_CNT - 1; 1130 IFQ_SET_READY(&ifp->if_snd); 1131 1132 /* 1133 * Call MI attach routine. 1134 */ 1135 ether_ifattach(ifp, eaddr); 1136 1137 /* Tell the upper layer(s) we support long frames. */ 1138 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1139 1140 /* Hook interrupt last to avoid having to lock softc */ 1141 error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE, 1142 NULL, vge_intr, sc, &sc->vge_intrhand); 1143 1144 if (error) { 1145 device_printf(dev, "couldn't set up irq\n"); 1146 ether_ifdetach(ifp); 1147 goto fail; 1148 } 1149 1150fail: 1151 if (error) 1152 vge_detach(dev); 1153 1154 return (error); 1155} 1156 1157/* 1158 * Shutdown hardware and free up resources. This can be called any 1159 * time after the mutex has been initialized. It is called in both 1160 * the error case in attach and the normal detach case so it needs 1161 * to be careful about only freeing resources that have actually been 1162 * allocated. 1163 */ 1164static int 1165vge_detach(device_t dev) 1166{ 1167 struct vge_softc *sc; 1168 struct ifnet *ifp; 1169 1170 sc = device_get_softc(dev); 1171 KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized")); 1172 ifp = sc->vge_ifp; 1173 1174#ifdef DEVICE_POLLING 1175 if (ifp->if_capenable & IFCAP_POLLING) 1176 ether_poll_deregister(ifp); 1177#endif 1178 1179 /* These should only be active if attach succeeded */ 1180 if (device_is_attached(dev)) { 1181 ether_ifdetach(ifp); 1182 VGE_LOCK(sc); 1183 vge_stop(sc); 1184 VGE_UNLOCK(sc); 1185 callout_drain(&sc->vge_watchdog); 1186 } 1187 if (sc->vge_miibus) 1188 device_delete_child(dev, sc->vge_miibus); 1189 bus_generic_detach(dev); 1190 1191 if (sc->vge_intrhand) 1192 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); 1193 if (sc->vge_irq) 1194 bus_release_resource(dev, SYS_RES_IRQ, 1195 sc->vge_flags & VGE_FLAG_MSI ? 1 : 0, sc->vge_irq); 1196 if (sc->vge_flags & VGE_FLAG_MSI) 1197 pci_release_msi(dev); 1198 if (sc->vge_res) 1199 bus_release_resource(dev, SYS_RES_MEMORY, 1200 PCIR_BAR(1), sc->vge_res); 1201 if (ifp) 1202 if_free(ifp); 1203 1204 vge_dma_free(sc); 1205 mtx_destroy(&sc->vge_mtx); 1206 1207 return (0); 1208} 1209 1210static void 1211vge_discard_rxbuf(struct vge_softc *sc, int prod) 1212{ 1213 struct vge_rxdesc *rxd; 1214 int i; 1215 1216 rxd = &sc->vge_cdata.vge_rxdesc[prod]; 1217 rxd->rx_desc->vge_sts = 0; 1218 rxd->rx_desc->vge_ctl = 0; 1219 1220 /* 1221 * Note: the manual fails to document the fact that for 1222 * proper opration, the driver needs to replentish the RX 1223 * DMA ring 4 descriptors at a time (rather than one at a 1224 * time, like most chips). We can allocate the new buffers 1225 * but we should not set the OWN bits until we're ready 1226 * to hand back 4 of them in one shot. 1227 */ 1228 if ((prod % VGE_RXCHUNK) == (VGE_RXCHUNK - 1)) { 1229 for (i = VGE_RXCHUNK; i > 0; i--) { 1230 rxd->rx_desc->vge_sts = htole32(VGE_RDSTS_OWN); 1231 rxd = rxd->rxd_prev; 1232 } 1233 sc->vge_cdata.vge_rx_commit += VGE_RXCHUNK; 1234 } 1235} 1236 1237static int 1238vge_newbuf(struct vge_softc *sc, int prod) 1239{ 1240 struct vge_rxdesc *rxd; 1241 struct mbuf *m; 1242 bus_dma_segment_t segs[1]; 1243 bus_dmamap_t map; 1244 int i, nsegs; 1245 1246 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1247 if (m == NULL) 1248 return (ENOBUFS); 1249 /* 1250 * This is part of an evil trick to deal with strict-alignment 1251 * architectures. The VIA chip requires RX buffers to be aligned 1252 * on 32-bit boundaries, but that will hose strict-alignment 1253 * architectures. To get around this, we leave some empty space 1254 * at the start of each buffer and for non-strict-alignment hosts, 1255 * we copy the buffer back two bytes to achieve word alignment. 1256 * This is slightly more efficient than allocating a new buffer, 1257 * copying the contents, and discarding the old buffer. 1258 */ 1259 m->m_len = m->m_pkthdr.len = MCLBYTES; 1260 m_adj(m, VGE_RX_BUF_ALIGN); 1261 1262 if (bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_rx_tag, 1263 sc->vge_cdata.vge_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1264 m_freem(m); 1265 return (ENOBUFS); 1266 } 1267 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1268 1269 rxd = &sc->vge_cdata.vge_rxdesc[prod]; 1270 if (rxd->rx_m != NULL) { 1271 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap, 1272 BUS_DMASYNC_POSTREAD); 1273 bus_dmamap_unload(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap); 1274 } 1275 map = rxd->rx_dmamap; 1276 rxd->rx_dmamap = sc->vge_cdata.vge_rx_sparemap; 1277 sc->vge_cdata.vge_rx_sparemap = map; 1278 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap, 1279 BUS_DMASYNC_PREREAD); 1280 rxd->rx_m = m; 1281 1282 rxd->rx_desc->vge_sts = 0; 1283 rxd->rx_desc->vge_ctl = 0; 1284 rxd->rx_desc->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 1285 rxd->rx_desc->vge_addrhi = htole32(VGE_ADDR_HI(segs[0].ds_addr) | 1286 (VGE_BUFLEN(segs[0].ds_len) << 16) | VGE_RXDESC_I); 1287 1288 /* 1289 * Note: the manual fails to document the fact that for 1290 * proper operation, the driver needs to replenish the RX 1291 * DMA ring 4 descriptors at a time (rather than one at a 1292 * time, like most chips). We can allocate the new buffers 1293 * but we should not set the OWN bits until we're ready 1294 * to hand back 4 of them in one shot. 1295 */ 1296 if ((prod % VGE_RXCHUNK) == (VGE_RXCHUNK - 1)) { 1297 for (i = VGE_RXCHUNK; i > 0; i--) { 1298 rxd->rx_desc->vge_sts = htole32(VGE_RDSTS_OWN); 1299 rxd = rxd->rxd_prev; 1300 } 1301 sc->vge_cdata.vge_rx_commit += VGE_RXCHUNK; 1302 } 1303 1304 return (0); 1305} 1306 1307static int 1308vge_tx_list_init(struct vge_softc *sc) 1309{ 1310 struct vge_ring_data *rd; 1311 struct vge_txdesc *txd; 1312 int i; 1313 1314 VGE_LOCK_ASSERT(sc); 1315 1316 sc->vge_cdata.vge_tx_prodidx = 0; 1317 sc->vge_cdata.vge_tx_considx = 0; 1318 sc->vge_cdata.vge_tx_cnt = 0; 1319 1320 rd = &sc->vge_rdata; 1321 bzero(rd->vge_tx_ring, VGE_TX_LIST_SZ); 1322 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 1323 txd = &sc->vge_cdata.vge_txdesc[i]; 1324 txd->tx_m = NULL; 1325 txd->tx_desc = &rd->vge_tx_ring[i]; 1326 } 1327 1328 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1329 sc->vge_cdata.vge_tx_ring_map, 1330 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1331 1332 return (0); 1333} 1334 1335static int 1336vge_rx_list_init(struct vge_softc *sc) 1337{ 1338 struct vge_ring_data *rd; 1339 struct vge_rxdesc *rxd; 1340 int i; 1341 1342 VGE_LOCK_ASSERT(sc); 1343 1344 sc->vge_cdata.vge_rx_prodidx = 0; 1345 sc->vge_cdata.vge_head = NULL; 1346 sc->vge_cdata.vge_tail = NULL; 1347 sc->vge_cdata.vge_rx_commit = 0; 1348 1349 rd = &sc->vge_rdata; 1350 bzero(rd->vge_rx_ring, VGE_RX_LIST_SZ); 1351 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1352 rxd = &sc->vge_cdata.vge_rxdesc[i]; 1353 rxd->rx_m = NULL; 1354 rxd->rx_desc = &rd->vge_rx_ring[i]; 1355 if (i == 0) 1356 rxd->rxd_prev = 1357 &sc->vge_cdata.vge_rxdesc[VGE_RX_DESC_CNT - 1]; 1358 else 1359 rxd->rxd_prev = &sc->vge_cdata.vge_rxdesc[i - 1]; 1360 if (vge_newbuf(sc, i) != 0) 1361 return (ENOBUFS); 1362 } 1363 1364 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, 1365 sc->vge_cdata.vge_rx_ring_map, 1366 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1367 1368 sc->vge_cdata.vge_rx_commit = 0; 1369 1370 return (0); 1371} 1372 1373static void 1374vge_freebufs(struct vge_softc *sc) 1375{ 1376 struct vge_txdesc *txd; 1377 struct vge_rxdesc *rxd; 1378 struct ifnet *ifp; 1379 int i; 1380 1381 VGE_LOCK_ASSERT(sc); 1382 1383 ifp = sc->vge_ifp; 1384 /* 1385 * Free RX and TX mbufs still in the queues. 1386 */ 1387 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1388 rxd = &sc->vge_cdata.vge_rxdesc[i]; 1389 if (rxd->rx_m != NULL) { 1390 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, 1391 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 1392 bus_dmamap_unload(sc->vge_cdata.vge_rx_tag, 1393 rxd->rx_dmamap); 1394 m_freem(rxd->rx_m); 1395 rxd->rx_m = NULL; 1396 } 1397 } 1398 1399 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 1400 txd = &sc->vge_cdata.vge_txdesc[i]; 1401 if (txd->tx_m != NULL) { 1402 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, 1403 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1404 bus_dmamap_unload(sc->vge_cdata.vge_tx_tag, 1405 txd->tx_dmamap); 1406 m_freem(txd->tx_m); 1407 txd->tx_m = NULL; 1408 ifp->if_oerrors++; 1409 } 1410 } 1411} 1412 1413#ifndef __NO_STRICT_ALIGNMENT 1414static __inline void 1415vge_fixup_rx(struct mbuf *m) 1416{ 1417 int i; 1418 uint16_t *src, *dst; 1419 1420 src = mtod(m, uint16_t *); 1421 dst = src - 1; 1422 1423 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1424 *dst++ = *src++; 1425 1426 m->m_data -= ETHER_ALIGN; 1427} 1428#endif 1429 1430/* 1431 * RX handler. We support the reception of jumbo frames that have 1432 * been fragmented across multiple 2K mbuf cluster buffers. 1433 */ 1434static int 1435vge_rxeof(struct vge_softc *sc, int count) 1436{ 1437 struct mbuf *m; 1438 struct ifnet *ifp; 1439 int prod, prog, total_len; 1440 struct vge_rxdesc *rxd; 1441 struct vge_rx_desc *cur_rx; 1442 uint32_t rxstat, rxctl; 1443 1444 VGE_LOCK_ASSERT(sc); 1445 1446 ifp = sc->vge_ifp; 1447 1448 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, 1449 sc->vge_cdata.vge_rx_ring_map, 1450 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1451 1452 prod = sc->vge_cdata.vge_rx_prodidx; 1453 for (prog = 0; count > 0 && 1454 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 1455 VGE_RX_DESC_INC(prod)) { 1456 cur_rx = &sc->vge_rdata.vge_rx_ring[prod]; 1457 rxstat = le32toh(cur_rx->vge_sts); 1458 if ((rxstat & VGE_RDSTS_OWN) != 0) 1459 break; 1460 count--; 1461 prog++; 1462 rxctl = le32toh(cur_rx->vge_ctl); 1463 total_len = VGE_RXBYTES(rxstat); 1464 rxd = &sc->vge_cdata.vge_rxdesc[prod]; 1465 m = rxd->rx_m; 1466 1467 /* 1468 * If the 'start of frame' bit is set, this indicates 1469 * either the first fragment in a multi-fragment receive, 1470 * or an intermediate fragment. Either way, we want to 1471 * accumulate the buffers. 1472 */ 1473 if ((rxstat & VGE_RXPKT_SOF) != 0) { 1474 if (vge_newbuf(sc, prod) != 0) { 1475 ifp->if_iqdrops++; 1476 VGE_CHAIN_RESET(sc); 1477 vge_discard_rxbuf(sc, prod); 1478 continue; 1479 } 1480 m->m_len = MCLBYTES - VGE_RX_BUF_ALIGN; 1481 if (sc->vge_cdata.vge_head == NULL) { 1482 sc->vge_cdata.vge_head = m; 1483 sc->vge_cdata.vge_tail = m; 1484 } else { 1485 m->m_flags &= ~M_PKTHDR; 1486 sc->vge_cdata.vge_tail->m_next = m; 1487 sc->vge_cdata.vge_tail = m; 1488 } 1489 continue; 1490 } 1491 1492 /* 1493 * Bad/error frames will have the RXOK bit cleared. 1494 * However, there's one error case we want to allow: 1495 * if a VLAN tagged frame arrives and the chip can't 1496 * match it against the CAM filter, it considers this 1497 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1498 * We don't want to drop the frame though: our VLAN 1499 * filtering is done in software. 1500 * We also want to receive bad-checksummed frames and 1501 * and frames with bad-length. 1502 */ 1503 if ((rxstat & VGE_RDSTS_RXOK) == 0 && 1504 (rxstat & (VGE_RDSTS_VIDM | VGE_RDSTS_RLERR | 1505 VGE_RDSTS_CSUMERR)) == 0) { 1506 ifp->if_ierrors++; 1507 /* 1508 * If this is part of a multi-fragment packet, 1509 * discard all the pieces. 1510 */ 1511 VGE_CHAIN_RESET(sc); 1512 vge_discard_rxbuf(sc, prod); 1513 continue; 1514 } 1515 1516 if (vge_newbuf(sc, prod) != 0) { 1517 ifp->if_iqdrops++; 1518 VGE_CHAIN_RESET(sc); 1519 vge_discard_rxbuf(sc, prod); 1520 continue; 1521 } 1522 1523 /* Chain received mbufs. */ 1524 if (sc->vge_cdata.vge_head != NULL) { 1525 m->m_len = total_len % (MCLBYTES - VGE_RX_BUF_ALIGN); 1526 /* 1527 * Special case: if there's 4 bytes or less 1528 * in this buffer, the mbuf can be discarded: 1529 * the last 4 bytes is the CRC, which we don't 1530 * care about anyway. 1531 */ 1532 if (m->m_len <= ETHER_CRC_LEN) { 1533 sc->vge_cdata.vge_tail->m_len -= 1534 (ETHER_CRC_LEN - m->m_len); 1535 m_freem(m); 1536 } else { 1537 m->m_len -= ETHER_CRC_LEN; 1538 m->m_flags &= ~M_PKTHDR; 1539 sc->vge_cdata.vge_tail->m_next = m; 1540 } 1541 m = sc->vge_cdata.vge_head; 1542 m->m_flags |= M_PKTHDR; 1543 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1544 } else { 1545 m->m_flags |= M_PKTHDR; 1546 m->m_pkthdr.len = m->m_len = 1547 (total_len - ETHER_CRC_LEN); 1548 } 1549 1550#ifndef __NO_STRICT_ALIGNMENT 1551 vge_fixup_rx(m); 1552#endif 1553 m->m_pkthdr.rcvif = ifp; 1554 1555 /* Do RX checksumming if enabled */ 1556 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 1557 (rxctl & VGE_RDCTL_FRAG) == 0) { 1558 /* Check IP header checksum */ 1559 if ((rxctl & VGE_RDCTL_IPPKT) != 0) 1560 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1561 if ((rxctl & VGE_RDCTL_IPCSUMOK) != 0) 1562 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1563 1564 /* Check TCP/UDP checksum */ 1565 if (rxctl & (VGE_RDCTL_TCPPKT | VGE_RDCTL_UDPPKT) && 1566 rxctl & VGE_RDCTL_PROTOCSUMOK) { 1567 m->m_pkthdr.csum_flags |= 1568 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1569 m->m_pkthdr.csum_data = 0xffff; 1570 } 1571 } 1572 1573 if ((rxstat & VGE_RDSTS_VTAG) != 0) { 1574 /* 1575 * The 32-bit rxctl register is stored in little-endian. 1576 * However, the 16-bit vlan tag is stored in big-endian, 1577 * so we have to byte swap it. 1578 */ 1579 m->m_pkthdr.ether_vtag = 1580 bswap16(rxctl & VGE_RDCTL_VLANID); 1581 m->m_flags |= M_VLANTAG; 1582 } 1583 1584 VGE_UNLOCK(sc); 1585 (*ifp->if_input)(ifp, m); 1586 VGE_LOCK(sc); 1587 sc->vge_cdata.vge_head = NULL; 1588 sc->vge_cdata.vge_tail = NULL; 1589 } 1590 1591 if (prog > 0) { 1592 sc->vge_cdata.vge_rx_prodidx = prod; 1593 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, 1594 sc->vge_cdata.vge_rx_ring_map, 1595 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1596 /* Update residue counter. */ 1597 if (sc->vge_cdata.vge_rx_commit != 0) { 1598 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, 1599 sc->vge_cdata.vge_rx_commit); 1600 sc->vge_cdata.vge_rx_commit = 0; 1601 } 1602 } 1603 return (prog); 1604} 1605 1606static void 1607vge_txeof(struct vge_softc *sc) 1608{ 1609 struct ifnet *ifp; 1610 struct vge_tx_desc *cur_tx; 1611 struct vge_txdesc *txd; 1612 uint32_t txstat; 1613 int cons, prod; 1614 1615 VGE_LOCK_ASSERT(sc); 1616 1617 ifp = sc->vge_ifp; 1618 1619 if (sc->vge_cdata.vge_tx_cnt == 0) 1620 return; 1621 1622 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1623 sc->vge_cdata.vge_tx_ring_map, 1624 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1625 1626 /* 1627 * Go through our tx list and free mbufs for those 1628 * frames that have been transmitted. 1629 */ 1630 cons = sc->vge_cdata.vge_tx_considx; 1631 prod = sc->vge_cdata.vge_tx_prodidx; 1632 for (; cons != prod; VGE_TX_DESC_INC(cons)) { 1633 cur_tx = &sc->vge_rdata.vge_tx_ring[cons]; 1634 txstat = le32toh(cur_tx->vge_sts); 1635 if ((txstat & VGE_TDSTS_OWN) != 0) 1636 break; 1637 sc->vge_cdata.vge_tx_cnt--; 1638 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1639 1640 txd = &sc->vge_cdata.vge_txdesc[cons]; 1641 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap, 1642 BUS_DMASYNC_POSTWRITE); 1643 bus_dmamap_unload(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap); 1644 1645 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!\n", 1646 __func__)); 1647 m_freem(txd->tx_m); 1648 txd->tx_m = NULL; 1649 txd->tx_desc->vge_frag[0].vge_addrhi = 0; 1650 } 1651 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1652 sc->vge_cdata.vge_tx_ring_map, 1653 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1654 sc->vge_cdata.vge_tx_considx = cons; 1655 if (sc->vge_cdata.vge_tx_cnt == 0) 1656 sc->vge_timer = 0; 1657} 1658 1659static void 1660vge_link_statchg(void *xsc) 1661{ 1662 struct vge_softc *sc; 1663 struct ifnet *ifp; 1664 uint8_t physts; 1665 1666 sc = xsc; 1667 ifp = sc->vge_ifp; 1668 VGE_LOCK_ASSERT(sc); 1669 1670 physts = CSR_READ_1(sc, VGE_PHYSTS0); 1671 if ((physts & VGE_PHYSTS_RESETSTS) == 0) { 1672 if ((physts & VGE_PHYSTS_LINK) == 0) { 1673 sc->vge_flags &= ~VGE_FLAG_LINK; 1674 if_link_state_change(sc->vge_ifp, 1675 LINK_STATE_DOWN); 1676 } else { 1677 sc->vge_flags |= VGE_FLAG_LINK; 1678 if_link_state_change(sc->vge_ifp, 1679 LINK_STATE_UP); 1680 CSR_WRITE_1(sc, VGE_CRC2, VGE_CR2_FDX_TXFLOWCTL_ENABLE | 1681 VGE_CR2_FDX_RXFLOWCTL_ENABLE); 1682 if ((physts & VGE_PHYSTS_FDX) != 0) { 1683 if ((physts & VGE_PHYSTS_TXFLOWCAP) != 0) 1684 CSR_WRITE_1(sc, VGE_CRS2, 1685 VGE_CR2_FDX_TXFLOWCTL_ENABLE); 1686 if ((physts & VGE_PHYSTS_RXFLOWCAP) != 0) 1687 CSR_WRITE_1(sc, VGE_CRS2, 1688 VGE_CR2_FDX_RXFLOWCTL_ENABLE); 1689 } 1690 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1691 vge_start_locked(ifp); 1692 } 1693 } 1694 /* 1695 * Restart MII auto-polling because link state change interrupt 1696 * will disable it. 1697 */ 1698 vge_miipoll_start(sc); 1699} 1700 1701#ifdef DEVICE_POLLING 1702static int 1703vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1704{ 1705 struct vge_softc *sc = ifp->if_softc; 1706 int rx_npkts = 0; 1707 1708 VGE_LOCK(sc); 1709 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1710 goto done; 1711 1712 rx_npkts = vge_rxeof(sc, count); 1713 vge_txeof(sc); 1714 1715 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1716 vge_start_locked(ifp); 1717 1718 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1719 uint32_t status; 1720 status = CSR_READ_4(sc, VGE_ISR); 1721 if (status == 0xFFFFFFFF) 1722 goto done; 1723 if (status) 1724 CSR_WRITE_4(sc, VGE_ISR, status); 1725 1726 /* 1727 * XXX check behaviour on receiver stalls. 1728 */ 1729 1730 if (status & VGE_ISR_TXDMA_STALL || 1731 status & VGE_ISR_RXDMA_STALL) { 1732 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1733 vge_init_locked(sc); 1734 } 1735 1736 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1737 vge_rxeof(sc, count); 1738 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1739 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1740 } 1741 } 1742done: 1743 VGE_UNLOCK(sc); 1744 return (rx_npkts); 1745} 1746#endif /* DEVICE_POLLING */ 1747 1748static void 1749vge_intr(void *arg) 1750{ 1751 struct vge_softc *sc; 1752 struct ifnet *ifp; 1753 uint32_t status; 1754 1755 sc = arg; 1756 VGE_LOCK(sc); 1757 1758 ifp = sc->vge_ifp; 1759 if ((sc->vge_flags & VGE_FLAG_SUSPENDED) != 0 || 1760 (ifp->if_flags & IFF_UP) == 0) { 1761 VGE_UNLOCK(sc); 1762 return; 1763 } 1764 1765#ifdef DEVICE_POLLING 1766 if (ifp->if_capenable & IFCAP_POLLING) { 1767 status = CSR_READ_4(sc, VGE_ISR); 1768 CSR_WRITE_4(sc, VGE_ISR, status); 1769 if (status != 0xFFFFFFFF && (status & VGE_ISR_LINKSTS) != 0) 1770 vge_link_statchg(sc); 1771 VGE_UNLOCK(sc); 1772 return; 1773 } 1774#endif 1775 1776 /* Disable interrupts */ 1777 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1778 status = CSR_READ_4(sc, VGE_ISR); 1779 CSR_WRITE_4(sc, VGE_ISR, status | VGE_ISR_HOLDOFF_RELOAD); 1780 /* If the card has gone away the read returns 0xffff. */ 1781 if (status == 0xFFFFFFFF || (status & VGE_INTRS) == 0) 1782 goto done; 1783 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1784 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1785 vge_rxeof(sc, VGE_RX_DESC_CNT); 1786 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1787 vge_rxeof(sc, VGE_RX_DESC_CNT); 1788 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1789 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1790 } 1791 1792 if (status & (VGE_ISR_TXOK0|VGE_ISR_TXOK_HIPRIO)) 1793 vge_txeof(sc); 1794 1795 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) { 1796 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1797 vge_init_locked(sc); 1798 } 1799 1800 if (status & VGE_ISR_LINKSTS) 1801 vge_link_statchg(sc); 1802 } 1803done: 1804 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1805 /* Re-enable interrupts */ 1806 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1807 1808 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1809 vge_start_locked(ifp); 1810 } 1811 VGE_UNLOCK(sc); 1812} 1813 1814static int 1815vge_encap(struct vge_softc *sc, struct mbuf **m_head) 1816{ 1817 struct vge_txdesc *txd; 1818 struct vge_tx_frag *frag; 1819 struct mbuf *m; 1820 bus_dma_segment_t txsegs[VGE_MAXTXSEGS]; 1821 int error, i, nsegs, padlen; 1822 uint32_t cflags; 1823 1824 VGE_LOCK_ASSERT(sc); 1825 1826 M_ASSERTPKTHDR((*m_head)); 1827 1828 /* Argh. This chip does not autopad short frames. */ 1829 if ((*m_head)->m_pkthdr.len < VGE_MIN_FRAMELEN) { 1830 m = *m_head; 1831 padlen = VGE_MIN_FRAMELEN - m->m_pkthdr.len; 1832 if (M_WRITABLE(m) == 0) { 1833 /* Get a writable copy. */ 1834 m = m_dup(*m_head, M_DONTWAIT); 1835 m_freem(*m_head); 1836 if (m == NULL) { 1837 *m_head = NULL; 1838 return (ENOBUFS); 1839 } 1840 *m_head = m; 1841 } 1842 if (M_TRAILINGSPACE(m) < padlen) { 1843 m = m_defrag(m, M_DONTWAIT); 1844 if (m == NULL) { 1845 m_freem(*m_head); 1846 *m_head = NULL; 1847 return (ENOBUFS); 1848 } 1849 } 1850 /* 1851 * Manually pad short frames, and zero the pad space 1852 * to avoid leaking data. 1853 */ 1854 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1855 m->m_pkthdr.len += padlen; 1856 m->m_len = m->m_pkthdr.len; 1857 *m_head = m; 1858 } 1859 1860 txd = &sc->vge_cdata.vge_txdesc[sc->vge_cdata.vge_tx_prodidx]; 1861 1862 error = bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_tx_tag, 1863 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1864 if (error == EFBIG) { 1865 m = m_collapse(*m_head, M_DONTWAIT, VGE_MAXTXSEGS); 1866 if (m == NULL) { 1867 m_freem(*m_head); 1868 *m_head = NULL; 1869 return (ENOMEM); 1870 } 1871 *m_head = m; 1872 error = bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_tx_tag, 1873 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1874 if (error != 0) { 1875 m_freem(*m_head); 1876 *m_head = NULL; 1877 return (error); 1878 } 1879 } else if (error != 0) 1880 return (error); 1881 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap, 1882 BUS_DMASYNC_PREWRITE); 1883 1884 m = *m_head; 1885 cflags = 0; 1886 1887 /* Configure checksum offload. */ 1888 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 1889 cflags |= VGE_TDCTL_IPCSUM; 1890 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1891 cflags |= VGE_TDCTL_TCPCSUM; 1892 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1893 cflags |= VGE_TDCTL_UDPCSUM; 1894 1895 /* Configure VLAN. */ 1896 if ((m->m_flags & M_VLANTAG) != 0) 1897 cflags |= m->m_pkthdr.ether_vtag | VGE_TDCTL_VTAG; 1898 txd->tx_desc->vge_sts = htole32(m->m_pkthdr.len << 16); 1899 /* 1900 * XXX 1901 * Velocity family seems to support TSO but no information 1902 * for MSS configuration is available. Also the number of 1903 * fragments supported by a descriptor is too small to hold 1904 * entire 64KB TCP/IP segment. Maybe VGE_TD_LS_MOF, 1905 * VGE_TD_LS_SOF and VGE_TD_LS_EOF could be used to build 1906 * longer chain of buffers but no additional information is 1907 * available. 1908 * 1909 * When telling the chip how many segments there are, we 1910 * must use nsegs + 1 instead of just nsegs. Darned if I 1911 * know why. This also means we can't use the last fragment 1912 * field of Tx descriptor. 1913 */ 1914 txd->tx_desc->vge_ctl = htole32(cflags | ((nsegs + 1) << 28) | 1915 VGE_TD_LS_NORM); 1916 for (i = 0; i < nsegs; i++) { 1917 frag = &txd->tx_desc->vge_frag[i]; 1918 frag->vge_addrlo = htole32(VGE_ADDR_LO(txsegs[i].ds_addr)); 1919 frag->vge_addrhi = htole32(VGE_ADDR_HI(txsegs[i].ds_addr) | 1920 (VGE_BUFLEN(txsegs[i].ds_len) << 16)); 1921 } 1922 1923 sc->vge_cdata.vge_tx_cnt++; 1924 VGE_TX_DESC_INC(sc->vge_cdata.vge_tx_prodidx); 1925 1926 /* 1927 * Finally request interrupt and give the first descriptor 1928 * ownership to hardware. 1929 */ 1930 txd->tx_desc->vge_ctl |= htole32(VGE_TDCTL_TIC); 1931 txd->tx_desc->vge_sts |= htole32(VGE_TDSTS_OWN); 1932 txd->tx_m = m; 1933 1934 return (0); 1935} 1936 1937/* 1938 * Main transmit routine. 1939 */ 1940 1941static void 1942vge_start(struct ifnet *ifp) 1943{ 1944 struct vge_softc *sc; 1945 1946 sc = ifp->if_softc; 1947 VGE_LOCK(sc); 1948 vge_start_locked(ifp); 1949 VGE_UNLOCK(sc); 1950} 1951 1952 1953static void 1954vge_start_locked(struct ifnet *ifp) 1955{ 1956 struct vge_softc *sc; 1957 struct vge_txdesc *txd; 1958 struct mbuf *m_head; 1959 int enq, idx; 1960 1961 sc = ifp->if_softc; 1962 1963 VGE_LOCK_ASSERT(sc); 1964 1965 if ((sc->vge_flags & VGE_FLAG_LINK) == 0 || 1966 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1967 IFF_DRV_RUNNING) 1968 return; 1969 1970 idx = sc->vge_cdata.vge_tx_prodidx; 1971 VGE_TX_DESC_DEC(idx); 1972 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1973 sc->vge_cdata.vge_tx_cnt < VGE_TX_DESC_CNT - 1; ) { 1974 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1975 if (m_head == NULL) 1976 break; 1977 /* 1978 * Pack the data into the transmit ring. If we 1979 * don't have room, set the OACTIVE flag and wait 1980 * for the NIC to drain the ring. 1981 */ 1982 if (vge_encap(sc, &m_head)) { 1983 if (m_head == NULL) 1984 break; 1985 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1986 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1987 break; 1988 } 1989 1990 txd = &sc->vge_cdata.vge_txdesc[idx]; 1991 txd->tx_desc->vge_frag[0].vge_addrhi |= htole32(VGE_TXDESC_Q); 1992 VGE_TX_DESC_INC(idx); 1993 1994 enq++; 1995 /* 1996 * If there's a BPF listener, bounce a copy of this frame 1997 * to him. 1998 */ 1999 ETHER_BPF_MTAP(ifp, m_head); 2000 } 2001 2002 if (enq > 0) { 2003 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 2004 sc->vge_cdata.vge_tx_ring_map, 2005 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2006 /* Issue a transmit command. */ 2007 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 2008 /* 2009 * Set a timeout in case the chip goes out to lunch. 2010 */ 2011 sc->vge_timer = 5; 2012 } 2013} 2014 2015static void 2016vge_init(void *xsc) 2017{ 2018 struct vge_softc *sc = xsc; 2019 2020 VGE_LOCK(sc); 2021 vge_init_locked(sc); 2022 VGE_UNLOCK(sc); 2023} 2024 2025static void 2026vge_init_locked(struct vge_softc *sc) 2027{ 2028 struct ifnet *ifp = sc->vge_ifp; 2029 struct mii_data *mii; 2030 int error, i; 2031 2032 VGE_LOCK_ASSERT(sc); 2033 mii = device_get_softc(sc->vge_miibus); 2034 2035 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2036 return; 2037 2038 /* 2039 * Cancel pending I/O and free all RX/TX buffers. 2040 */ 2041 vge_stop(sc); 2042 vge_reset(sc); 2043 vge_miipoll_start(sc); 2044 2045 /* 2046 * Initialize the RX and TX descriptors and mbufs. 2047 */ 2048 2049 error = vge_rx_list_init(sc); 2050 if (error != 0) { 2051 device_printf(sc->vge_dev, "no memory for Rx buffers.\n"); 2052 return; 2053 } 2054 vge_tx_list_init(sc); 2055 /* Clear MAC statistics. */ 2056 vge_stats_clear(sc); 2057 /* Set our station address */ 2058 for (i = 0; i < ETHER_ADDR_LEN; i++) 2059 CSR_WRITE_1(sc, VGE_PAR0 + i, IF_LLADDR(sc->vge_ifp)[i]); 2060 2061 /* 2062 * Set receive FIFO threshold. Also allow transmission and 2063 * reception of VLAN tagged frames. 2064 */ 2065 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 2066 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES); 2067 2068 /* Set DMA burst length */ 2069 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 2070 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 2071 2072 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 2073 2074 /* Set collision backoff algorithm */ 2075 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 2076 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 2077 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 2078 2079 /* Disable LPSEL field in priority resolution */ 2080 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 2081 2082 /* 2083 * Load the addresses of the DMA queues into the chip. 2084 * Note that we only use one transmit queue. 2085 */ 2086 2087 CSR_WRITE_4(sc, VGE_TXDESC_HIADDR, 2088 VGE_ADDR_HI(sc->vge_rdata.vge_tx_ring_paddr)); 2089 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 2090 VGE_ADDR_LO(sc->vge_rdata.vge_tx_ring_paddr)); 2091 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 2092 2093 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 2094 VGE_ADDR_LO(sc->vge_rdata.vge_rx_ring_paddr)); 2095 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 2096 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 2097 2098 /* Configure interrupt moderation. */ 2099 vge_intr_holdoff(sc); 2100 2101 /* Enable and wake up the RX descriptor queue */ 2102 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 2103 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 2104 2105 /* Enable the TX descriptor queue */ 2106 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 2107 2108 /* Init the cam filter. */ 2109 vge_cam_clear(sc); 2110 2111 /* Set up receiver filter. */ 2112 vge_rxfilter(sc); 2113 vge_setvlan(sc); 2114 2115 /* Enable flow control */ 2116 2117 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 2118 2119 /* Enable jumbo frame reception (if desired) */ 2120 2121 /* Start the MAC. */ 2122 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 2123 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 2124 CSR_WRITE_1(sc, VGE_CRS0, 2125 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 2126 2127#ifdef DEVICE_POLLING 2128 /* 2129 * Disable interrupts except link state change if we are polling. 2130 */ 2131 if (ifp->if_capenable & IFCAP_POLLING) { 2132 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS_POLLING); 2133 } else /* otherwise ... */ 2134#endif 2135 { 2136 /* 2137 * Enable interrupts. 2138 */ 2139 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2140 } 2141 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2142 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2143 2144 sc->vge_flags &= ~VGE_FLAG_LINK; 2145 vge_ifmedia_upd_locked(sc); 2146 2147 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2148 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2149 callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc); 2150} 2151 2152/* 2153 * Set media options. 2154 */ 2155static int 2156vge_ifmedia_upd(struct ifnet *ifp) 2157{ 2158 struct vge_softc *sc; 2159 int error; 2160 2161 sc = ifp->if_softc; 2162 VGE_LOCK(sc); 2163 error = vge_ifmedia_upd_locked(sc); 2164 VGE_UNLOCK(sc); 2165 2166 return (error); 2167} 2168 2169static int 2170vge_ifmedia_upd_locked(struct vge_softc *sc) 2171{ 2172 struct mii_data *mii; 2173 struct mii_softc *miisc; 2174 int error; 2175 2176 mii = device_get_softc(sc->vge_miibus); 2177 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2178 PHY_RESET(miisc); 2179 vge_setmedia(sc); 2180 error = mii_mediachg(mii); 2181 2182 return (error); 2183} 2184 2185/* 2186 * Report current media status. 2187 */ 2188static void 2189vge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2190{ 2191 struct vge_softc *sc; 2192 struct mii_data *mii; 2193 2194 sc = ifp->if_softc; 2195 mii = device_get_softc(sc->vge_miibus); 2196 2197 VGE_LOCK(sc); 2198 if ((ifp->if_flags & IFF_UP) == 0) { 2199 VGE_UNLOCK(sc); 2200 return; 2201 } 2202 mii_pollstat(mii); 2203 ifmr->ifm_active = mii->mii_media_active; 2204 ifmr->ifm_status = mii->mii_media_status; 2205 VGE_UNLOCK(sc); 2206} 2207 2208static void 2209vge_setmedia(struct vge_softc *sc) 2210{ 2211 struct mii_data *mii; 2212 struct ifmedia_entry *ife; 2213 2214 mii = device_get_softc(sc->vge_miibus); 2215 ife = mii->mii_media.ifm_cur; 2216 2217 /* 2218 * If the user manually selects a media mode, we need to turn 2219 * on the forced MAC mode bit in the DIAGCTL register. If the 2220 * user happens to choose a full duplex mode, we also need to 2221 * set the 'force full duplex' bit. This applies only to 2222 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2223 * mode is disabled, and in 1000baseT mode, full duplex is 2224 * always implied, so we turn on the forced mode bit but leave 2225 * the FDX bit cleared. 2226 */ 2227 2228 switch (IFM_SUBTYPE(ife->ifm_media)) { 2229 case IFM_AUTO: 2230 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2231 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2232 break; 2233 case IFM_1000_T: 2234 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2235 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2236 break; 2237 case IFM_100_TX: 2238 case IFM_10_T: 2239 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2240 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2241 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2242 } else { 2243 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2244 } 2245 break; 2246 default: 2247 device_printf(sc->vge_dev, "unknown media type: %x\n", 2248 IFM_SUBTYPE(ife->ifm_media)); 2249 break; 2250 } 2251} 2252 2253static int 2254vge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2255{ 2256 struct vge_softc *sc = ifp->if_softc; 2257 struct ifreq *ifr = (struct ifreq *) data; 2258 struct mii_data *mii; 2259 int error = 0, mask; 2260 2261 switch (command) { 2262 case SIOCSIFMTU: 2263 VGE_LOCK(sc); 2264 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > VGE_JUMBO_MTU) 2265 error = EINVAL; 2266 else if (ifp->if_mtu != ifr->ifr_mtu) { 2267 if (ifr->ifr_mtu > ETHERMTU && 2268 (sc->vge_flags & VGE_FLAG_JUMBO) == 0) 2269 error = EINVAL; 2270 else 2271 ifp->if_mtu = ifr->ifr_mtu; 2272 } 2273 VGE_UNLOCK(sc); 2274 break; 2275 case SIOCSIFFLAGS: 2276 VGE_LOCK(sc); 2277 if ((ifp->if_flags & IFF_UP) != 0) { 2278 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2279 ((ifp->if_flags ^ sc->vge_if_flags) & 2280 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2281 vge_rxfilter(sc); 2282 else 2283 vge_init_locked(sc); 2284 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2285 vge_stop(sc); 2286 sc->vge_if_flags = ifp->if_flags; 2287 VGE_UNLOCK(sc); 2288 break; 2289 case SIOCADDMULTI: 2290 case SIOCDELMULTI: 2291 VGE_LOCK(sc); 2292 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2293 vge_rxfilter(sc); 2294 VGE_UNLOCK(sc); 2295 break; 2296 case SIOCGIFMEDIA: 2297 case SIOCSIFMEDIA: 2298 mii = device_get_softc(sc->vge_miibus); 2299 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2300 break; 2301 case SIOCSIFCAP: 2302 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2303#ifdef DEVICE_POLLING 2304 if (mask & IFCAP_POLLING) { 2305 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2306 error = ether_poll_register(vge_poll, ifp); 2307 if (error) 2308 return (error); 2309 VGE_LOCK(sc); 2310 /* Disable interrupts */ 2311 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS_POLLING); 2312 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2313 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2314 ifp->if_capenable |= IFCAP_POLLING; 2315 VGE_UNLOCK(sc); 2316 } else { 2317 error = ether_poll_deregister(ifp); 2318 /* Enable interrupts. */ 2319 VGE_LOCK(sc); 2320 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2321 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2322 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2323 ifp->if_capenable &= ~IFCAP_POLLING; 2324 VGE_UNLOCK(sc); 2325 } 2326 } 2327#endif /* DEVICE_POLLING */ 2328 VGE_LOCK(sc); 2329 if ((mask & IFCAP_TXCSUM) != 0 && 2330 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2331 ifp->if_capenable ^= IFCAP_TXCSUM; 2332 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2333 ifp->if_hwassist |= VGE_CSUM_FEATURES; 2334 else 2335 ifp->if_hwassist &= ~VGE_CSUM_FEATURES; 2336 } 2337 if ((mask & IFCAP_RXCSUM) != 0 && 2338 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 2339 ifp->if_capenable ^= IFCAP_RXCSUM; 2340 if ((mask & IFCAP_WOL_UCAST) != 0 && 2341 (ifp->if_capabilities & IFCAP_WOL_UCAST) != 0) 2342 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2343 if ((mask & IFCAP_WOL_MCAST) != 0 && 2344 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2345 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2346 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2347 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2348 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2349 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2350 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2351 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2352 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2353 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) { 2354 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2355 vge_setvlan(sc); 2356 } 2357 VGE_UNLOCK(sc); 2358 VLAN_CAPABILITIES(ifp); 2359 break; 2360 default: 2361 error = ether_ioctl(ifp, command, data); 2362 break; 2363 } 2364 2365 return (error); 2366} 2367 2368static void 2369vge_watchdog(void *arg) 2370{ 2371 struct vge_softc *sc; 2372 struct ifnet *ifp; 2373 2374 sc = arg; 2375 VGE_LOCK_ASSERT(sc); 2376 vge_stats_update(sc); 2377 callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc); 2378 if (sc->vge_timer == 0 || --sc->vge_timer > 0) 2379 return; 2380 2381 ifp = sc->vge_ifp; 2382 if_printf(ifp, "watchdog timeout\n"); 2383 ifp->if_oerrors++; 2384 2385 vge_txeof(sc); 2386 vge_rxeof(sc, VGE_RX_DESC_CNT); 2387 2388 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2389 vge_init_locked(sc); 2390} 2391 2392/* 2393 * Stop the adapter and free any mbufs allocated to the 2394 * RX and TX lists. 2395 */ 2396static void 2397vge_stop(struct vge_softc *sc) 2398{ 2399 struct ifnet *ifp; 2400 2401 VGE_LOCK_ASSERT(sc); 2402 ifp = sc->vge_ifp; 2403 sc->vge_timer = 0; 2404 callout_stop(&sc->vge_watchdog); 2405 2406 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2407 2408 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2409 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2410 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2411 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2412 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2413 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2414 2415 vge_stats_update(sc); 2416 VGE_CHAIN_RESET(sc); 2417 vge_txeof(sc); 2418 vge_freebufs(sc); 2419} 2420 2421/* 2422 * Device suspend routine. Stop the interface and save some PCI 2423 * settings in case the BIOS doesn't restore them properly on 2424 * resume. 2425 */ 2426static int 2427vge_suspend(device_t dev) 2428{ 2429 struct vge_softc *sc; 2430 2431 sc = device_get_softc(dev); 2432 2433 VGE_LOCK(sc); 2434 vge_stop(sc); 2435 vge_setwol(sc); 2436 sc->vge_flags |= VGE_FLAG_SUSPENDED; 2437 VGE_UNLOCK(sc); 2438 2439 return (0); 2440} 2441 2442/* 2443 * Device resume routine. Restore some PCI settings in case the BIOS 2444 * doesn't, re-enable busmastering, and restart the interface if 2445 * appropriate. 2446 */ 2447static int 2448vge_resume(device_t dev) 2449{ 2450 struct vge_softc *sc; 2451 struct ifnet *ifp; 2452 uint16_t pmstat; 2453 2454 sc = device_get_softc(dev); 2455 VGE_LOCK(sc); 2456 if ((sc->vge_flags & VGE_FLAG_PMCAP) != 0) { 2457 /* Disable PME and clear PME status. */ 2458 pmstat = pci_read_config(sc->vge_dev, 2459 sc->vge_pmcap + PCIR_POWER_STATUS, 2); 2460 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2461 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2462 pci_write_config(sc->vge_dev, 2463 sc->vge_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2464 } 2465 } 2466 vge_clrwol(sc); 2467 /* Restart MII auto-polling. */ 2468 vge_miipoll_start(sc); 2469 ifp = sc->vge_ifp; 2470 /* Reinitialize interface if necessary. */ 2471 if ((ifp->if_flags & IFF_UP) != 0) { 2472 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2473 vge_init_locked(sc); 2474 } 2475 sc->vge_flags &= ~VGE_FLAG_SUSPENDED; 2476 VGE_UNLOCK(sc); 2477 2478 return (0); 2479} 2480 2481/* 2482 * Stop all chip I/O so that the kernel's probe routines don't 2483 * get confused by errant DMAs when rebooting. 2484 */ 2485static int 2486vge_shutdown(device_t dev) 2487{ 2488 2489 return (vge_suspend(dev)); 2490} 2491 2492#define VGE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2493 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2494 2495static void 2496vge_sysctl_node(struct vge_softc *sc) 2497{ 2498 struct sysctl_ctx_list *ctx; 2499 struct sysctl_oid_list *child, *parent; 2500 struct sysctl_oid *tree; 2501 struct vge_hw_stats *stats; 2502 2503 stats = &sc->vge_stats; 2504 ctx = device_get_sysctl_ctx(sc->vge_dev); 2505 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->vge_dev)); 2506 2507 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "int_holdoff", 2508 CTLFLAG_RW, &sc->vge_int_holdoff, 0, "interrupt holdoff"); 2509 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "rx_coal_pkt", 2510 CTLFLAG_RW, &sc->vge_rx_coal_pkt, 0, "rx coalescing packet"); 2511 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "tx_coal_pkt", 2512 CTLFLAG_RW, &sc->vge_tx_coal_pkt, 0, "tx coalescing packet"); 2513 2514 /* Pull in device tunables. */ 2515 sc->vge_int_holdoff = VGE_INT_HOLDOFF_DEFAULT; 2516 resource_int_value(device_get_name(sc->vge_dev), 2517 device_get_unit(sc->vge_dev), "int_holdoff", &sc->vge_int_holdoff); 2518 sc->vge_rx_coal_pkt = VGE_RX_COAL_PKT_DEFAULT; 2519 resource_int_value(device_get_name(sc->vge_dev), 2520 device_get_unit(sc->vge_dev), "rx_coal_pkt", &sc->vge_rx_coal_pkt); 2521 sc->vge_tx_coal_pkt = VGE_TX_COAL_PKT_DEFAULT; 2522 resource_int_value(device_get_name(sc->vge_dev), 2523 device_get_unit(sc->vge_dev), "tx_coal_pkt", &sc->vge_tx_coal_pkt); 2524 2525 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 2526 NULL, "VGE statistics"); 2527 parent = SYSCTL_CHILDREN(tree); 2528 2529 /* Rx statistics. */ 2530 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 2531 NULL, "RX MAC statistics"); 2532 child = SYSCTL_CHILDREN(tree); 2533 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames", 2534 &stats->rx_frames, "frames"); 2535 VGE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 2536 &stats->rx_good_frames, "Good frames"); 2537 VGE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 2538 &stats->rx_fifo_oflows, "FIFO overflows"); 2539 VGE_SYSCTL_STAT_ADD32(ctx, child, "runts", 2540 &stats->rx_runts, "Too short frames"); 2541 VGE_SYSCTL_STAT_ADD32(ctx, child, "runts_errs", 2542 &stats->rx_runts_errs, "Too short frames with errors"); 2543 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 2544 &stats->rx_pkts_64, "64 bytes frames"); 2545 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 2546 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 2547 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 2548 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 2549 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 2550 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 2551 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 2552 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 2553 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 2554 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 2555 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 2556 &stats->rx_pkts_1519_max, "1519 to max frames"); 2557 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max_errs", 2558 &stats->rx_pkts_1519_max_errs, "1519 to max frames with error"); 2559 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_jumbo", 2560 &stats->rx_jumbos, "Jumbo frames"); 2561 VGE_SYSCTL_STAT_ADD32(ctx, child, "crcerrs", 2562 &stats->rx_crcerrs, "CRC errors"); 2563 VGE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 2564 &stats->rx_pause_frames, "CRC errors"); 2565 VGE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 2566 &stats->rx_alignerrs, "Alignment errors"); 2567 VGE_SYSCTL_STAT_ADD32(ctx, child, "nobufs", 2568 &stats->rx_nobufs, "Frames with no buffer event"); 2569 VGE_SYSCTL_STAT_ADD32(ctx, child, "sym_errs", 2570 &stats->rx_symerrs, "Frames with symbol errors"); 2571 VGE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 2572 &stats->rx_lenerrs, "Frames with length mismatched"); 2573 2574 /* Tx statistics. */ 2575 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 2576 NULL, "TX MAC statistics"); 2577 child = SYSCTL_CHILDREN(tree); 2578 VGE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 2579 &stats->tx_good_frames, "Good frames"); 2580 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 2581 &stats->tx_pkts_64, "64 bytes frames"); 2582 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 2583 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 2584 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 2585 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 2586 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 2587 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 2588 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 2589 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 2590 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 2591 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 2592 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_jumbo", 2593 &stats->tx_jumbos, "Jumbo frames"); 2594 VGE_SYSCTL_STAT_ADD32(ctx, child, "colls", 2595 &stats->tx_colls, "Collisions"); 2596 VGE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 2597 &stats->tx_latecolls, "Late collisions"); 2598 VGE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 2599 &stats->tx_pause, "Pause frames"); 2600#ifdef VGE_ENABLE_SQEERR 2601 VGE_SYSCTL_STAT_ADD32(ctx, child, "sqeerrs", 2602 &stats->tx_sqeerrs, "SQE errors"); 2603#endif 2604 /* Clear MAC statistics. */ 2605 vge_stats_clear(sc); 2606} 2607 2608#undef VGE_SYSCTL_STAT_ADD32 2609 2610static void 2611vge_stats_clear(struct vge_softc *sc) 2612{ 2613 int i; 2614 2615 CSR_WRITE_1(sc, VGE_MIBCSR, 2616 CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_FREEZE); 2617 CSR_WRITE_1(sc, VGE_MIBCSR, 2618 CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_CLR); 2619 for (i = VGE_TIMEOUT; i > 0; i--) { 2620 DELAY(1); 2621 if ((CSR_READ_1(sc, VGE_MIBCSR) & VGE_MIBCSR_CLR) == 0) 2622 break; 2623 } 2624 if (i == 0) 2625 device_printf(sc->vge_dev, "MIB clear timed out!\n"); 2626 CSR_WRITE_1(sc, VGE_MIBCSR, CSR_READ_1(sc, VGE_MIBCSR) & 2627 ~VGE_MIBCSR_FREEZE); 2628} 2629 2630static void 2631vge_stats_update(struct vge_softc *sc) 2632{ 2633 struct vge_hw_stats *stats; 2634 struct ifnet *ifp; 2635 uint32_t mib[VGE_MIB_CNT], val; 2636 int i; 2637 2638 VGE_LOCK_ASSERT(sc); 2639 2640 stats = &sc->vge_stats; 2641 ifp = sc->vge_ifp; 2642 2643 CSR_WRITE_1(sc, VGE_MIBCSR, 2644 CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_FLUSH); 2645 for (i = VGE_TIMEOUT; i > 0; i--) { 2646 DELAY(1); 2647 if ((CSR_READ_1(sc, VGE_MIBCSR) & VGE_MIBCSR_FLUSH) == 0) 2648 break; 2649 } 2650 if (i == 0) { 2651 device_printf(sc->vge_dev, "MIB counter dump timed out!\n"); 2652 vge_stats_clear(sc); 2653 return; 2654 } 2655 2656 bzero(mib, sizeof(mib)); 2657reset_idx: 2658 /* Set MIB read index to 0. */ 2659 CSR_WRITE_1(sc, VGE_MIBCSR, 2660 CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_RINI); 2661 for (i = 0; i < VGE_MIB_CNT; i++) { 2662 val = CSR_READ_4(sc, VGE_MIBDATA); 2663 if (i != VGE_MIB_DATA_IDX(val)) { 2664 /* Reading interrupted. */ 2665 goto reset_idx; 2666 } 2667 mib[i] = val & VGE_MIB_DATA_MASK; 2668 } 2669 2670 /* Rx stats. */ 2671 stats->rx_frames += mib[VGE_MIB_RX_FRAMES]; 2672 stats->rx_good_frames += mib[VGE_MIB_RX_GOOD_FRAMES]; 2673 stats->rx_fifo_oflows += mib[VGE_MIB_RX_FIFO_OVERRUNS]; 2674 stats->rx_runts += mib[VGE_MIB_RX_RUNTS]; 2675 stats->rx_runts_errs += mib[VGE_MIB_RX_RUNTS_ERRS]; 2676 stats->rx_pkts_64 += mib[VGE_MIB_RX_PKTS_64]; 2677 stats->rx_pkts_65_127 += mib[VGE_MIB_RX_PKTS_65_127]; 2678 stats->rx_pkts_128_255 += mib[VGE_MIB_RX_PKTS_128_255]; 2679 stats->rx_pkts_256_511 += mib[VGE_MIB_RX_PKTS_256_511]; 2680 stats->rx_pkts_512_1023 += mib[VGE_MIB_RX_PKTS_512_1023]; 2681 stats->rx_pkts_1024_1518 += mib[VGE_MIB_RX_PKTS_1024_1518]; 2682 stats->rx_pkts_1519_max += mib[VGE_MIB_RX_PKTS_1519_MAX]; 2683 stats->rx_pkts_1519_max_errs += mib[VGE_MIB_RX_PKTS_1519_MAX_ERRS]; 2684 stats->rx_jumbos += mib[VGE_MIB_RX_JUMBOS]; 2685 stats->rx_crcerrs += mib[VGE_MIB_RX_CRCERRS]; 2686 stats->rx_pause_frames += mib[VGE_MIB_RX_PAUSE]; 2687 stats->rx_alignerrs += mib[VGE_MIB_RX_ALIGNERRS]; 2688 stats->rx_nobufs += mib[VGE_MIB_RX_NOBUFS]; 2689 stats->rx_symerrs += mib[VGE_MIB_RX_SYMERRS]; 2690 stats->rx_lenerrs += mib[VGE_MIB_RX_LENERRS]; 2691 2692 /* Tx stats. */ 2693 stats->tx_good_frames += mib[VGE_MIB_TX_GOOD_FRAMES]; 2694 stats->tx_pkts_64 += mib[VGE_MIB_TX_PKTS_64]; 2695 stats->tx_pkts_65_127 += mib[VGE_MIB_TX_PKTS_65_127]; 2696 stats->tx_pkts_128_255 += mib[VGE_MIB_TX_PKTS_128_255]; 2697 stats->tx_pkts_256_511 += mib[VGE_MIB_TX_PKTS_256_511]; 2698 stats->tx_pkts_512_1023 += mib[VGE_MIB_TX_PKTS_512_1023]; 2699 stats->tx_pkts_1024_1518 += mib[VGE_MIB_TX_PKTS_1024_1518]; 2700 stats->tx_jumbos += mib[VGE_MIB_TX_JUMBOS]; 2701 stats->tx_colls += mib[VGE_MIB_TX_COLLS]; 2702 stats->tx_pause += mib[VGE_MIB_TX_PAUSE]; 2703#ifdef VGE_ENABLE_SQEERR 2704 stats->tx_sqeerrs += mib[VGE_MIB_TX_SQEERRS]; 2705#endif 2706 stats->tx_latecolls += mib[VGE_MIB_TX_LATECOLLS]; 2707 2708 /* Update counters in ifnet. */ 2709 ifp->if_opackets += mib[VGE_MIB_TX_GOOD_FRAMES]; 2710 2711 ifp->if_collisions += mib[VGE_MIB_TX_COLLS] + 2712 mib[VGE_MIB_TX_LATECOLLS]; 2713 2714 ifp->if_oerrors += mib[VGE_MIB_TX_COLLS] + 2715 mib[VGE_MIB_TX_LATECOLLS]; 2716 2717 ifp->if_ipackets += mib[VGE_MIB_RX_GOOD_FRAMES]; 2718 2719 ifp->if_ierrors += mib[VGE_MIB_RX_FIFO_OVERRUNS] + 2720 mib[VGE_MIB_RX_RUNTS] + 2721 mib[VGE_MIB_RX_RUNTS_ERRS] + 2722 mib[VGE_MIB_RX_CRCERRS] + 2723 mib[VGE_MIB_RX_ALIGNERRS] + 2724 mib[VGE_MIB_RX_NOBUFS] + 2725 mib[VGE_MIB_RX_SYMERRS] + 2726 mib[VGE_MIB_RX_LENERRS]; 2727} 2728 2729static void 2730vge_intr_holdoff(struct vge_softc *sc) 2731{ 2732 uint8_t intctl; 2733 2734 VGE_LOCK_ASSERT(sc); 2735 2736 /* 2737 * Set Tx interrupt supression threshold. 2738 * It's possible to use single-shot timer in VGE_CRS1 register 2739 * in Tx path such that driver can remove most of Tx completion 2740 * interrupts. However this requires additional access to 2741 * VGE_CRS1 register to reload the timer in addintion to 2742 * activating Tx kick command. Another downside is we don't know 2743 * what single-shot timer value should be used in advance so 2744 * reclaiming transmitted mbufs could be delayed a lot which in 2745 * turn slows down Tx operation. 2746 */ 2747 CSR_WRITE_1(sc, VGE_CAMCTL, VGE_PAGESEL_TXSUPPTHR); 2748 CSR_WRITE_1(sc, VGE_TXSUPPTHR, sc->vge_tx_coal_pkt); 2749 2750 /* Set Rx interrupt suppresion threshold. */ 2751 CSR_WRITE_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 2752 CSR_WRITE_1(sc, VGE_RXSUPPTHR, sc->vge_rx_coal_pkt); 2753 2754 intctl = CSR_READ_1(sc, VGE_INTCTL1); 2755 intctl &= ~VGE_INTCTL_SC_RELOAD; 2756 intctl |= VGE_INTCTL_HC_RELOAD; 2757 if (sc->vge_tx_coal_pkt <= 0) 2758 intctl |= VGE_INTCTL_TXINTSUP_DISABLE; 2759 else 2760 intctl &= ~VGE_INTCTL_TXINTSUP_DISABLE; 2761 if (sc->vge_rx_coal_pkt <= 0) 2762 intctl |= VGE_INTCTL_RXINTSUP_DISABLE; 2763 else 2764 intctl &= ~VGE_INTCTL_RXINTSUP_DISABLE; 2765 CSR_WRITE_1(sc, VGE_INTCTL1, intctl); 2766 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_HOLDOFF); 2767 if (sc->vge_int_holdoff > 0) { 2768 /* Set interrupt holdoff timer. */ 2769 CSR_WRITE_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 2770 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 2771 VGE_INT_HOLDOFF_USEC(sc->vge_int_holdoff)); 2772 /* Enable holdoff timer. */ 2773 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 2774 } 2775} 2776 2777static void 2778vge_setlinkspeed(struct vge_softc *sc) 2779{ 2780 struct mii_data *mii; 2781 int aneg, i; 2782 2783 VGE_LOCK_ASSERT(sc); 2784 2785 mii = device_get_softc(sc->vge_miibus); 2786 mii_pollstat(mii); 2787 aneg = 0; 2788 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2789 (IFM_ACTIVE | IFM_AVALID)) { 2790 switch IFM_SUBTYPE(mii->mii_media_active) { 2791 case IFM_10_T: 2792 case IFM_100_TX: 2793 return; 2794 case IFM_1000_T: 2795 aneg++; 2796 default: 2797 break; 2798 } 2799 } 2800 /* Clear forced MAC speed/duplex configuration. */ 2801 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2802 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2803 vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_100T2CR, 0); 2804 vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_ANAR, 2805 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 2806 vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_BMCR, 2807 BMCR_AUTOEN | BMCR_STARTNEG); 2808 DELAY(1000); 2809 if (aneg != 0) { 2810 /* Poll link state until vge(4) get a 10/100 link. */ 2811 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 2812 mii_pollstat(mii); 2813 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 2814 == (IFM_ACTIVE | IFM_AVALID)) { 2815 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2816 case IFM_10_T: 2817 case IFM_100_TX: 2818 return; 2819 default: 2820 break; 2821 } 2822 } 2823 VGE_UNLOCK(sc); 2824 pause("vgelnk", hz); 2825 VGE_LOCK(sc); 2826 } 2827 if (i == MII_ANEGTICKS_GIGE) 2828 device_printf(sc->vge_dev, "establishing link failed, " 2829 "WOL may not work!"); 2830 } 2831 /* 2832 * No link, force MAC to have 100Mbps, full-duplex link. 2833 * This is the last resort and may/may not work. 2834 */ 2835 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 2836 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 2837} 2838 2839static void 2840vge_setwol(struct vge_softc *sc) 2841{ 2842 struct ifnet *ifp; 2843 uint16_t pmstat; 2844 uint8_t val; 2845 2846 VGE_LOCK_ASSERT(sc); 2847 2848 if ((sc->vge_flags & VGE_FLAG_PMCAP) == 0) { 2849 /* No PME capability, PHY power down. */ 2850 vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_BMCR, 2851 BMCR_PDOWN); 2852 vge_miipoll_stop(sc); 2853 return; 2854 } 2855 2856 ifp = sc->vge_ifp; 2857 2858 /* Clear WOL on pattern match. */ 2859 CSR_WRITE_1(sc, VGE_WOLCR0C, VGE_WOLCR0_PATTERN_ALL); 2860 /* Disable WOL on magic/unicast packet. */ 2861 CSR_WRITE_1(sc, VGE_WOLCR1C, 0x0F); 2862 CSR_WRITE_1(sc, VGE_WOLCFGC, VGE_WOLCFG_SAB | VGE_WOLCFG_SAM | 2863 VGE_WOLCFG_PMEOVR); 2864 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2865 vge_setlinkspeed(sc); 2866 val = 0; 2867 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 2868 val |= VGE_WOLCR1_UCAST; 2869 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2870 val |= VGE_WOLCR1_MAGIC; 2871 CSR_WRITE_1(sc, VGE_WOLCR1S, val); 2872 val = 0; 2873 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2874 val |= VGE_WOLCFG_SAM | VGE_WOLCFG_SAB; 2875 CSR_WRITE_1(sc, VGE_WOLCFGS, val | VGE_WOLCFG_PMEOVR); 2876 /* Disable MII auto-polling. */ 2877 vge_miipoll_stop(sc); 2878 } 2879 CSR_SETBIT_1(sc, VGE_DIAGCTL, 2880 VGE_DIAGCTL_MACFORCE | VGE_DIAGCTL_FDXFORCE); 2881 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_GMII); 2882 2883 /* Clear WOL status on pattern match. */ 2884 CSR_WRITE_1(sc, VGE_WOLSR0C, 0xFF); 2885 CSR_WRITE_1(sc, VGE_WOLSR1C, 0xFF); 2886 2887 val = CSR_READ_1(sc, VGE_PWRSTAT); 2888 val |= VGE_STICKHW_SWPTAG; 2889 CSR_WRITE_1(sc, VGE_PWRSTAT, val); 2890 /* Put hardware into sleep. */ 2891 val = CSR_READ_1(sc, VGE_PWRSTAT); 2892 val |= VGE_STICKHW_DS0 | VGE_STICKHW_DS1; 2893 CSR_WRITE_1(sc, VGE_PWRSTAT, val); 2894 /* Request PME if WOL is requested. */ 2895 pmstat = pci_read_config(sc->vge_dev, sc->vge_pmcap + 2896 PCIR_POWER_STATUS, 2); 2897 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2898 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2899 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2900 pci_write_config(sc->vge_dev, sc->vge_pmcap + PCIR_POWER_STATUS, 2901 pmstat, 2); 2902} 2903 2904static void 2905vge_clrwol(struct vge_softc *sc) 2906{ 2907 uint8_t val; 2908 2909 val = CSR_READ_1(sc, VGE_PWRSTAT); 2910 val &= ~VGE_STICKHW_SWPTAG; 2911 CSR_WRITE_1(sc, VGE_PWRSTAT, val); 2912 /* Disable WOL and clear power state indicator. */ 2913 val = CSR_READ_1(sc, VGE_PWRSTAT); 2914 val &= ~(VGE_STICKHW_DS0 | VGE_STICKHW_DS1); 2915 CSR_WRITE_1(sc, VGE_PWRSTAT, val); 2916 2917 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_GMII); 2918 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2919 2920 /* Clear WOL on pattern match. */ 2921 CSR_WRITE_1(sc, VGE_WOLCR0C, VGE_WOLCR0_PATTERN_ALL); 2922 /* Disable WOL on magic/unicast packet. */ 2923 CSR_WRITE_1(sc, VGE_WOLCR1C, 0x0F); 2924 CSR_WRITE_1(sc, VGE_WOLCFGC, VGE_WOLCFG_SAB | VGE_WOLCFG_SAM | 2925 VGE_WOLCFG_PMEOVR); 2926 /* Clear WOL status on pattern match. */ 2927 CSR_WRITE_1(sc, VGE_WOLSR0C, 0xFF); 2928 CSR_WRITE_1(sc, VGE_WOLSR1C, 0xFF); 2929} 2930