if_vge.c revision 200639
1/*- 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/vge/if_vge.c 200639 2009-12-17 18:03:05Z yongari $"); 35 36/* 37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 46 * combines a tri-speed ethernet MAC and PHY, with the following 47 * features: 48 * 49 * o Jumbo frame support up to 16K 50 * o Transmit and receive flow control 51 * o IPv4 checksum offload 52 * o VLAN tag insertion and stripping 53 * o TCP large send 54 * o 64-bit multicast hash table filter 55 * o 64 entry CAM filter 56 * o 16K RX FIFO and 48K TX FIFO memory 57 * o Interrupt moderation 58 * 59 * The VT6122 supports up to four transmit DMA queues. The descriptors 60 * in the transmit ring can address up to 7 data fragments; frames which 61 * span more than 7 data buffers must be coalesced, but in general the 62 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 63 * long. The receive descriptors address only a single buffer. 64 * 65 * There are two peculiar design issues with the VT6122. One is that 66 * receive data buffers must be aligned on a 32-bit boundary. This is 67 * not a problem where the VT6122 is used as a LOM device in x86-based 68 * systems, but on architectures that generate unaligned access traps, we 69 * have to do some copying. 70 * 71 * The other issue has to do with the way 64-bit addresses are handled. 72 * The DMA descriptors only allow you to specify 48 bits of addressing 73 * information. The remaining 16 bits are specified using one of the 74 * I/O registers. If you only have a 32-bit system, then this isn't 75 * an issue, but if you have a 64-bit system and more than 4GB of 76 * memory, you must have to make sure your network data buffers reside 77 * in the same 48-bit 'segment.' 78 * 79 * Special thanks to Ryan Fu at VIA Networking for providing documentation 80 * and sample NICs for testing. 81 */ 82 83#ifdef HAVE_KERNEL_OPTION_HEADERS 84#include "opt_device_polling.h" 85#endif 86 87#include <sys/param.h> 88#include <sys/endian.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/module.h> 94#include <sys/kernel.h> 95#include <sys/socket.h> 96#include <sys/sysctl.h> 97 98#include <net/if.h> 99#include <net/if_arp.h> 100#include <net/ethernet.h> 101#include <net/if_dl.h> 102#include <net/if_media.h> 103#include <net/if_types.h> 104#include <net/if_vlan_var.h> 105 106#include <net/bpf.h> 107 108#include <machine/bus.h> 109#include <machine/resource.h> 110#include <sys/bus.h> 111#include <sys/rman.h> 112 113#include <dev/mii/mii.h> 114#include <dev/mii/miivar.h> 115 116#include <dev/pci/pcireg.h> 117#include <dev/pci/pcivar.h> 118 119MODULE_DEPEND(vge, pci, 1, 1, 1); 120MODULE_DEPEND(vge, ether, 1, 1, 1); 121MODULE_DEPEND(vge, miibus, 1, 1, 1); 122 123/* "device miibus" required. See GENERIC if you get errors here. */ 124#include "miibus_if.h" 125 126#include <dev/vge/if_vgereg.h> 127#include <dev/vge/if_vgevar.h> 128 129#define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 130 131/* Tunables */ 132static int msi_disable = 0; 133TUNABLE_INT("hw.vge.msi_disable", &msi_disable); 134 135/* 136 * The SQE error counter of MIB seems to report bogus value. 137 * Vendor's workaround does not seem to work on PCIe based 138 * controllers. Disable it until we find better workaround. 139 */ 140#undef VGE_ENABLE_SQEERR 141 142/* 143 * Various supported device vendors/types and their names. 144 */ 145static struct vge_type vge_devs[] = { 146 { VIA_VENDORID, VIA_DEVICEID_61XX, 147 "VIA Networking Velocity Gigabit Ethernet" }, 148 { 0, 0, NULL } 149}; 150 151static int vge_attach(device_t); 152static int vge_detach(device_t); 153static int vge_probe(device_t); 154static int vge_resume(device_t); 155static int vge_shutdown(device_t); 156static int vge_suspend(device_t); 157 158static void vge_cam_clear(struct vge_softc *); 159static int vge_cam_set(struct vge_softc *, uint8_t *); 160static void vge_discard_rxbuf(struct vge_softc *, int); 161static int vge_dma_alloc(struct vge_softc *); 162static void vge_dma_free(struct vge_softc *); 163static void vge_dmamap_cb(void *, bus_dma_segment_t *, int, int); 164#ifdef VGE_EEPROM 165static void vge_eeprom_getword(struct vge_softc *, int, uint16_t *); 166#endif 167static int vge_encap(struct vge_softc *, struct mbuf **); 168#ifndef __NO_STRICT_ALIGNMENT 169static __inline void 170 vge_fixup_rx(struct mbuf *); 171#endif 172static void vge_freebufs(struct vge_softc *); 173static void vge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 174static int vge_ifmedia_upd(struct ifnet *); 175static void vge_init(void *); 176static void vge_init_locked(struct vge_softc *); 177static void vge_intr(void *); 178static void vge_intr_holdoff(struct vge_softc *); 179static int vge_ioctl(struct ifnet *, u_long, caddr_t); 180static void vge_link_statchg(void *); 181static int vge_miibus_readreg(device_t, int, int); 182static void vge_miibus_statchg(device_t); 183static int vge_miibus_writereg(device_t, int, int, int); 184static void vge_miipoll_start(struct vge_softc *); 185static void vge_miipoll_stop(struct vge_softc *); 186static int vge_newbuf(struct vge_softc *, int); 187static void vge_read_eeprom(struct vge_softc *, caddr_t, int, int, int); 188static void vge_reset(struct vge_softc *); 189static int vge_rx_list_init(struct vge_softc *); 190static int vge_rxeof(struct vge_softc *, int); 191static void vge_rxfilter(struct vge_softc *); 192static void vge_setvlan(struct vge_softc *); 193static void vge_start(struct ifnet *); 194static void vge_start_locked(struct ifnet *); 195static void vge_stats_clear(struct vge_softc *); 196static void vge_stats_update(struct vge_softc *); 197static void vge_stop(struct vge_softc *); 198static void vge_sysctl_node(struct vge_softc *); 199static int vge_tx_list_init(struct vge_softc *); 200static void vge_txeof(struct vge_softc *); 201static void vge_watchdog(void *); 202 203static device_method_t vge_methods[] = { 204 /* Device interface */ 205 DEVMETHOD(device_probe, vge_probe), 206 DEVMETHOD(device_attach, vge_attach), 207 DEVMETHOD(device_detach, vge_detach), 208 DEVMETHOD(device_suspend, vge_suspend), 209 DEVMETHOD(device_resume, vge_resume), 210 DEVMETHOD(device_shutdown, vge_shutdown), 211 212 /* bus interface */ 213 DEVMETHOD(bus_print_child, bus_generic_print_child), 214 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 215 216 /* MII interface */ 217 DEVMETHOD(miibus_readreg, vge_miibus_readreg), 218 DEVMETHOD(miibus_writereg, vge_miibus_writereg), 219 DEVMETHOD(miibus_statchg, vge_miibus_statchg), 220 221 { 0, 0 } 222}; 223 224static driver_t vge_driver = { 225 "vge", 226 vge_methods, 227 sizeof(struct vge_softc) 228}; 229 230static devclass_t vge_devclass; 231 232DRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0); 233DRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0); 234 235#ifdef VGE_EEPROM 236/* 237 * Read a word of data stored in the EEPROM at address 'addr.' 238 */ 239static void 240vge_eeprom_getword(struct vge_softc *sc, int addr, uint16_t *dest) 241{ 242 int i; 243 uint16_t word = 0; 244 245 /* 246 * Enter EEPROM embedded programming mode. In order to 247 * access the EEPROM at all, we first have to set the 248 * EELOAD bit in the CHIPCFG2 register. 249 */ 250 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 251 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 252 253 /* Select the address of the word we want to read */ 254 CSR_WRITE_1(sc, VGE_EEADDR, addr); 255 256 /* Issue read command */ 257 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 258 259 /* Wait for the done bit to be set. */ 260 for (i = 0; i < VGE_TIMEOUT; i++) { 261 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 262 break; 263 } 264 265 if (i == VGE_TIMEOUT) { 266 device_printf(sc->vge_dev, "EEPROM read timed out\n"); 267 *dest = 0; 268 return; 269 } 270 271 /* Read the result */ 272 word = CSR_READ_2(sc, VGE_EERDDAT); 273 274 /* Turn off EEPROM access mode. */ 275 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 276 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 277 278 *dest = word; 279} 280#endif 281 282/* 283 * Read a sequence of words from the EEPROM. 284 */ 285static void 286vge_read_eeprom(struct vge_softc *sc, caddr_t dest, int off, int cnt, int swap) 287{ 288 int i; 289#ifdef VGE_EEPROM 290 uint16_t word = 0, *ptr; 291 292 for (i = 0; i < cnt; i++) { 293 vge_eeprom_getword(sc, off + i, &word); 294 ptr = (uint16_t *)(dest + (i * 2)); 295 if (swap) 296 *ptr = ntohs(word); 297 else 298 *ptr = word; 299 } 300#else 301 for (i = 0; i < ETHER_ADDR_LEN; i++) 302 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 303#endif 304} 305 306static void 307vge_miipoll_stop(struct vge_softc *sc) 308{ 309 int i; 310 311 CSR_WRITE_1(sc, VGE_MIICMD, 0); 312 313 for (i = 0; i < VGE_TIMEOUT; i++) { 314 DELAY(1); 315 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 316 break; 317 } 318 319 if (i == VGE_TIMEOUT) 320 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 321} 322 323static void 324vge_miipoll_start(struct vge_softc *sc) 325{ 326 int i; 327 328 /* First, make sure we're idle. */ 329 330 CSR_WRITE_1(sc, VGE_MIICMD, 0); 331 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 332 333 for (i = 0; i < VGE_TIMEOUT; i++) { 334 DELAY(1); 335 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 336 break; 337 } 338 339 if (i == VGE_TIMEOUT) { 340 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 341 return; 342 } 343 344 /* Now enable auto poll mode. */ 345 346 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 347 348 /* And make sure it started. */ 349 350 for (i = 0; i < VGE_TIMEOUT; i++) { 351 DELAY(1); 352 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 353 break; 354 } 355 356 if (i == VGE_TIMEOUT) 357 device_printf(sc->vge_dev, "failed to start MII autopoll\n"); 358} 359 360static int 361vge_miibus_readreg(device_t dev, int phy, int reg) 362{ 363 struct vge_softc *sc; 364 int i; 365 uint16_t rval = 0; 366 367 sc = device_get_softc(dev); 368 369 if (phy != sc->vge_phyaddr) 370 return (0); 371 372 vge_miipoll_stop(sc); 373 374 /* Specify the register we want to read. */ 375 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 376 377 /* Issue read command. */ 378 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 379 380 /* Wait for the read command bit to self-clear. */ 381 for (i = 0; i < VGE_TIMEOUT; i++) { 382 DELAY(1); 383 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 384 break; 385 } 386 387 if (i == VGE_TIMEOUT) 388 device_printf(sc->vge_dev, "MII read timed out\n"); 389 else 390 rval = CSR_READ_2(sc, VGE_MIIDATA); 391 392 vge_miipoll_start(sc); 393 394 return (rval); 395} 396 397static int 398vge_miibus_writereg(device_t dev, int phy, int reg, int data) 399{ 400 struct vge_softc *sc; 401 int i, rval = 0; 402 403 sc = device_get_softc(dev); 404 405 if (phy != sc->vge_phyaddr) 406 return (0); 407 408 vge_miipoll_stop(sc); 409 410 /* Specify the register we want to write. */ 411 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 412 413 /* Specify the data we want to write. */ 414 CSR_WRITE_2(sc, VGE_MIIDATA, data); 415 416 /* Issue write command. */ 417 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 418 419 /* Wait for the write command bit to self-clear. */ 420 for (i = 0; i < VGE_TIMEOUT; i++) { 421 DELAY(1); 422 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 423 break; 424 } 425 426 if (i == VGE_TIMEOUT) { 427 device_printf(sc->vge_dev, "MII write timed out\n"); 428 rval = EIO; 429 } 430 431 vge_miipoll_start(sc); 432 433 return (rval); 434} 435 436static void 437vge_cam_clear(struct vge_softc *sc) 438{ 439 int i; 440 441 /* 442 * Turn off all the mask bits. This tells the chip 443 * that none of the entries in the CAM filter are valid. 444 * desired entries will be enabled as we fill the filter in. 445 */ 446 447 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 448 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 449 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 450 for (i = 0; i < 8; i++) 451 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 452 453 /* Clear the VLAN filter too. */ 454 455 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 456 for (i = 0; i < 8; i++) 457 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 458 459 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 460 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 461 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 462 463 sc->vge_camidx = 0; 464} 465 466static int 467vge_cam_set(struct vge_softc *sc, uint8_t *addr) 468{ 469 int i, error = 0; 470 471 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 472 return (ENOSPC); 473 474 /* Select the CAM data page. */ 475 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 476 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 477 478 /* Set the filter entry we want to update and enable writing. */ 479 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 480 481 /* Write the address to the CAM registers */ 482 for (i = 0; i < ETHER_ADDR_LEN; i++) 483 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 484 485 /* Issue a write command. */ 486 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 487 488 /* Wake for it to clear. */ 489 for (i = 0; i < VGE_TIMEOUT; i++) { 490 DELAY(1); 491 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 492 break; 493 } 494 495 if (i == VGE_TIMEOUT) { 496 device_printf(sc->vge_dev, "setting CAM filter failed\n"); 497 error = EIO; 498 goto fail; 499 } 500 501 /* Select the CAM mask page. */ 502 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 503 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 504 505 /* Set the mask bit that enables this filter. */ 506 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 507 1<<(sc->vge_camidx & 7)); 508 509 sc->vge_camidx++; 510 511fail: 512 /* Turn off access to CAM. */ 513 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 514 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 515 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 516 517 return (error); 518} 519 520static void 521vge_setvlan(struct vge_softc *sc) 522{ 523 struct ifnet *ifp; 524 uint8_t cfg; 525 526 VGE_LOCK_ASSERT(sc); 527 528 ifp = sc->vge_ifp; 529 cfg = CSR_READ_1(sc, VGE_RXCFG); 530 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 531 cfg |= VGE_VTAG_OPT2; 532 else 533 cfg &= ~VGE_VTAG_OPT2; 534 CSR_WRITE_1(sc, VGE_RXCFG, cfg); 535} 536 537/* 538 * Program the multicast filter. We use the 64-entry CAM filter 539 * for perfect filtering. If there's more than 64 multicast addresses, 540 * we use the hash filter instead. 541 */ 542static void 543vge_rxfilter(struct vge_softc *sc) 544{ 545 struct ifnet *ifp; 546 struct ifmultiaddr *ifma; 547 uint32_t h, hashes[2]; 548 uint8_t rxcfg; 549 int error = 0; 550 551 VGE_LOCK_ASSERT(sc); 552 553 /* First, zot all the multicast entries. */ 554 hashes[0] = 0; 555 hashes[1] = 0; 556 557 rxcfg = CSR_READ_1(sc, VGE_RXCTL); 558 rxcfg &= ~(VGE_RXCTL_RX_MCAST | VGE_RXCTL_RX_BCAST | 559 VGE_RXCTL_RX_PROMISC); 560 /* 561 * Always allow VLAN oversized frames and frames for 562 * this host. 563 */ 564 rxcfg |= VGE_RXCTL_RX_GIANT | VGE_RXCTL_RX_UCAST; 565 566 ifp = sc->vge_ifp; 567 if ((ifp->if_flags & IFF_BROADCAST) != 0) 568 rxcfg |= VGE_RXCTL_RX_BCAST; 569 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 570 if ((ifp->if_flags & IFF_PROMISC) != 0) 571 rxcfg |= VGE_RXCTL_RX_PROMISC; 572 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 573 hashes[0] = 0xFFFFFFFF; 574 hashes[1] = 0xFFFFFFFF; 575 } 576 goto done; 577 } 578 579 vge_cam_clear(sc); 580 /* Now program new ones */ 581 if_maddr_rlock(ifp); 582 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 583 if (ifma->ifma_addr->sa_family != AF_LINK) 584 continue; 585 error = vge_cam_set(sc, 586 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 587 if (error) 588 break; 589 } 590 591 /* If there were too many addresses, use the hash filter. */ 592 if (error) { 593 vge_cam_clear(sc); 594 595 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 596 if (ifma->ifma_addr->sa_family != AF_LINK) 597 continue; 598 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 599 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 600 if (h < 32) 601 hashes[0] |= (1 << h); 602 else 603 hashes[1] |= (1 << (h - 32)); 604 } 605 } 606 if_maddr_runlock(ifp); 607 608done: 609 if (hashes[0] != 0 || hashes[1] != 0) 610 rxcfg |= VGE_RXCTL_RX_MCAST; 611 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 612 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 613 CSR_WRITE_1(sc, VGE_RXCTL, rxcfg); 614} 615 616static void 617vge_reset(struct vge_softc *sc) 618{ 619 int i; 620 621 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 622 623 for (i = 0; i < VGE_TIMEOUT; i++) { 624 DELAY(5); 625 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 626 break; 627 } 628 629 if (i == VGE_TIMEOUT) { 630 device_printf(sc->vge_dev, "soft reset timed out\n"); 631 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 632 DELAY(2000); 633 } 634 635 DELAY(5000); 636} 637 638/* 639 * Probe for a VIA gigabit chip. Check the PCI vendor and device 640 * IDs against our list and return a device name if we find a match. 641 */ 642static int 643vge_probe(device_t dev) 644{ 645 struct vge_type *t; 646 647 t = vge_devs; 648 649 while (t->vge_name != NULL) { 650 if ((pci_get_vendor(dev) == t->vge_vid) && 651 (pci_get_device(dev) == t->vge_did)) { 652 device_set_desc(dev, t->vge_name); 653 return (BUS_PROBE_DEFAULT); 654 } 655 t++; 656 } 657 658 return (ENXIO); 659} 660 661/* 662 * Map a single buffer address. 663 */ 664 665struct vge_dmamap_arg { 666 bus_addr_t vge_busaddr; 667}; 668 669static void 670vge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 671{ 672 struct vge_dmamap_arg *ctx; 673 674 if (error != 0) 675 return; 676 677 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 678 679 ctx = (struct vge_dmamap_arg *)arg; 680 ctx->vge_busaddr = segs[0].ds_addr; 681} 682 683static int 684vge_dma_alloc(struct vge_softc *sc) 685{ 686 struct vge_dmamap_arg ctx; 687 struct vge_txdesc *txd; 688 struct vge_rxdesc *rxd; 689 bus_addr_t lowaddr, tx_ring_end, rx_ring_end; 690 int error, i; 691 692 lowaddr = BUS_SPACE_MAXADDR; 693 694again: 695 /* Create parent ring tag. */ 696 error = bus_dma_tag_create(bus_get_dma_tag(sc->vge_dev),/* parent */ 697 1, 0, /* algnmnt, boundary */ 698 lowaddr, /* lowaddr */ 699 BUS_SPACE_MAXADDR, /* highaddr */ 700 NULL, NULL, /* filter, filterarg */ 701 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 702 0, /* nsegments */ 703 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 704 0, /* flags */ 705 NULL, NULL, /* lockfunc, lockarg */ 706 &sc->vge_cdata.vge_ring_tag); 707 if (error != 0) { 708 device_printf(sc->vge_dev, 709 "could not create parent DMA tag.\n"); 710 goto fail; 711 } 712 713 /* Create tag for Tx ring. */ 714 error = bus_dma_tag_create(sc->vge_cdata.vge_ring_tag,/* parent */ 715 VGE_TX_RING_ALIGN, 0, /* algnmnt, boundary */ 716 BUS_SPACE_MAXADDR, /* lowaddr */ 717 BUS_SPACE_MAXADDR, /* highaddr */ 718 NULL, NULL, /* filter, filterarg */ 719 VGE_TX_LIST_SZ, /* maxsize */ 720 1, /* nsegments */ 721 VGE_TX_LIST_SZ, /* maxsegsize */ 722 0, /* flags */ 723 NULL, NULL, /* lockfunc, lockarg */ 724 &sc->vge_cdata.vge_tx_ring_tag); 725 if (error != 0) { 726 device_printf(sc->vge_dev, 727 "could not allocate Tx ring DMA tag.\n"); 728 goto fail; 729 } 730 731 /* Create tag for Rx ring. */ 732 error = bus_dma_tag_create(sc->vge_cdata.vge_ring_tag,/* parent */ 733 VGE_RX_RING_ALIGN, 0, /* algnmnt, boundary */ 734 BUS_SPACE_MAXADDR, /* lowaddr */ 735 BUS_SPACE_MAXADDR, /* highaddr */ 736 NULL, NULL, /* filter, filterarg */ 737 VGE_RX_LIST_SZ, /* maxsize */ 738 1, /* nsegments */ 739 VGE_RX_LIST_SZ, /* maxsegsize */ 740 0, /* flags */ 741 NULL, NULL, /* lockfunc, lockarg */ 742 &sc->vge_cdata.vge_rx_ring_tag); 743 if (error != 0) { 744 device_printf(sc->vge_dev, 745 "could not allocate Rx ring DMA tag.\n"); 746 goto fail; 747 } 748 749 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 750 error = bus_dmamem_alloc(sc->vge_cdata.vge_tx_ring_tag, 751 (void **)&sc->vge_rdata.vge_tx_ring, 752 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 753 &sc->vge_cdata.vge_tx_ring_map); 754 if (error != 0) { 755 device_printf(sc->vge_dev, 756 "could not allocate DMA'able memory for Tx ring.\n"); 757 goto fail; 758 } 759 760 ctx.vge_busaddr = 0; 761 error = bus_dmamap_load(sc->vge_cdata.vge_tx_ring_tag, 762 sc->vge_cdata.vge_tx_ring_map, sc->vge_rdata.vge_tx_ring, 763 VGE_TX_LIST_SZ, vge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 764 if (error != 0 || ctx.vge_busaddr == 0) { 765 device_printf(sc->vge_dev, 766 "could not load DMA'able memory for Tx ring.\n"); 767 goto fail; 768 } 769 sc->vge_rdata.vge_tx_ring_paddr = ctx.vge_busaddr; 770 771 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 772 error = bus_dmamem_alloc(sc->vge_cdata.vge_rx_ring_tag, 773 (void **)&sc->vge_rdata.vge_rx_ring, 774 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 775 &sc->vge_cdata.vge_rx_ring_map); 776 if (error != 0) { 777 device_printf(sc->vge_dev, 778 "could not allocate DMA'able memory for Rx ring.\n"); 779 goto fail; 780 } 781 782 ctx.vge_busaddr = 0; 783 error = bus_dmamap_load(sc->vge_cdata.vge_rx_ring_tag, 784 sc->vge_cdata.vge_rx_ring_map, sc->vge_rdata.vge_rx_ring, 785 VGE_RX_LIST_SZ, vge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 786 if (error != 0 || ctx.vge_busaddr == 0) { 787 device_printf(sc->vge_dev, 788 "could not load DMA'able memory for Rx ring.\n"); 789 goto fail; 790 } 791 sc->vge_rdata.vge_rx_ring_paddr = ctx.vge_busaddr; 792 793 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 794 tx_ring_end = sc->vge_rdata.vge_tx_ring_paddr + VGE_TX_LIST_SZ; 795 rx_ring_end = sc->vge_rdata.vge_rx_ring_paddr + VGE_RX_LIST_SZ; 796 if ((VGE_ADDR_HI(tx_ring_end) != 797 VGE_ADDR_HI(sc->vge_rdata.vge_tx_ring_paddr)) || 798 (VGE_ADDR_HI(rx_ring_end) != 799 VGE_ADDR_HI(sc->vge_rdata.vge_rx_ring_paddr)) || 800 VGE_ADDR_HI(tx_ring_end) != VGE_ADDR_HI(rx_ring_end)) { 801 device_printf(sc->vge_dev, "4GB boundary crossed, " 802 "switching to 32bit DMA address mode.\n"); 803 vge_dma_free(sc); 804 /* Limit DMA address space to 32bit and try again. */ 805 lowaddr = BUS_SPACE_MAXADDR_32BIT; 806 goto again; 807 } 808 809 /* Create parent buffer tag. */ 810 error = bus_dma_tag_create(bus_get_dma_tag(sc->vge_dev),/* parent */ 811 1, 0, /* algnmnt, boundary */ 812 VGE_BUF_DMA_MAXADDR, /* lowaddr */ 813 BUS_SPACE_MAXADDR, /* highaddr */ 814 NULL, NULL, /* filter, filterarg */ 815 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 816 0, /* nsegments */ 817 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 818 0, /* flags */ 819 NULL, NULL, /* lockfunc, lockarg */ 820 &sc->vge_cdata.vge_buffer_tag); 821 if (error != 0) { 822 device_printf(sc->vge_dev, 823 "could not create parent buffer DMA tag.\n"); 824 goto fail; 825 } 826 827 /* Create tag for Tx buffers. */ 828 error = bus_dma_tag_create(sc->vge_cdata.vge_buffer_tag,/* parent */ 829 1, 0, /* algnmnt, boundary */ 830 BUS_SPACE_MAXADDR, /* lowaddr */ 831 BUS_SPACE_MAXADDR, /* highaddr */ 832 NULL, NULL, /* filter, filterarg */ 833 MCLBYTES * VGE_MAXTXSEGS, /* maxsize */ 834 VGE_MAXTXSEGS, /* nsegments */ 835 MCLBYTES, /* maxsegsize */ 836 0, /* flags */ 837 NULL, NULL, /* lockfunc, lockarg */ 838 &sc->vge_cdata.vge_tx_tag); 839 if (error != 0) { 840 device_printf(sc->vge_dev, "could not create Tx DMA tag.\n"); 841 goto fail; 842 } 843 844 /* Create tag for Rx buffers. */ 845 error = bus_dma_tag_create(sc->vge_cdata.vge_buffer_tag,/* parent */ 846 VGE_RX_BUF_ALIGN, 0, /* algnmnt, boundary */ 847 BUS_SPACE_MAXADDR, /* lowaddr */ 848 BUS_SPACE_MAXADDR, /* highaddr */ 849 NULL, NULL, /* filter, filterarg */ 850 MCLBYTES, /* maxsize */ 851 1, /* nsegments */ 852 MCLBYTES, /* maxsegsize */ 853 0, /* flags */ 854 NULL, NULL, /* lockfunc, lockarg */ 855 &sc->vge_cdata.vge_rx_tag); 856 if (error != 0) { 857 device_printf(sc->vge_dev, "could not create Rx DMA tag.\n"); 858 goto fail; 859 } 860 861 /* Create DMA maps for Tx buffers. */ 862 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 863 txd = &sc->vge_cdata.vge_txdesc[i]; 864 txd->tx_m = NULL; 865 txd->tx_dmamap = NULL; 866 error = bus_dmamap_create(sc->vge_cdata.vge_tx_tag, 0, 867 &txd->tx_dmamap); 868 if (error != 0) { 869 device_printf(sc->vge_dev, 870 "could not create Tx dmamap.\n"); 871 goto fail; 872 } 873 } 874 /* Create DMA maps for Rx buffers. */ 875 if ((error = bus_dmamap_create(sc->vge_cdata.vge_rx_tag, 0, 876 &sc->vge_cdata.vge_rx_sparemap)) != 0) { 877 device_printf(sc->vge_dev, 878 "could not create spare Rx dmamap.\n"); 879 goto fail; 880 } 881 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 882 rxd = &sc->vge_cdata.vge_rxdesc[i]; 883 rxd->rx_m = NULL; 884 rxd->rx_dmamap = NULL; 885 error = bus_dmamap_create(sc->vge_cdata.vge_rx_tag, 0, 886 &rxd->rx_dmamap); 887 if (error != 0) { 888 device_printf(sc->vge_dev, 889 "could not create Rx dmamap.\n"); 890 goto fail; 891 } 892 } 893 894fail: 895 return (error); 896} 897 898static void 899vge_dma_free(struct vge_softc *sc) 900{ 901 struct vge_txdesc *txd; 902 struct vge_rxdesc *rxd; 903 int i; 904 905 /* Tx ring. */ 906 if (sc->vge_cdata.vge_tx_ring_tag != NULL) { 907 if (sc->vge_cdata.vge_tx_ring_map) 908 bus_dmamap_unload(sc->vge_cdata.vge_tx_ring_tag, 909 sc->vge_cdata.vge_tx_ring_map); 910 if (sc->vge_cdata.vge_tx_ring_map && 911 sc->vge_rdata.vge_tx_ring) 912 bus_dmamem_free(sc->vge_cdata.vge_tx_ring_tag, 913 sc->vge_rdata.vge_tx_ring, 914 sc->vge_cdata.vge_tx_ring_map); 915 sc->vge_rdata.vge_tx_ring = NULL; 916 sc->vge_cdata.vge_tx_ring_map = NULL; 917 bus_dma_tag_destroy(sc->vge_cdata.vge_tx_ring_tag); 918 sc->vge_cdata.vge_tx_ring_tag = NULL; 919 } 920 /* Rx ring. */ 921 if (sc->vge_cdata.vge_rx_ring_tag != NULL) { 922 if (sc->vge_cdata.vge_rx_ring_map) 923 bus_dmamap_unload(sc->vge_cdata.vge_rx_ring_tag, 924 sc->vge_cdata.vge_rx_ring_map); 925 if (sc->vge_cdata.vge_rx_ring_map && 926 sc->vge_rdata.vge_rx_ring) 927 bus_dmamem_free(sc->vge_cdata.vge_rx_ring_tag, 928 sc->vge_rdata.vge_rx_ring, 929 sc->vge_cdata.vge_rx_ring_map); 930 sc->vge_rdata.vge_rx_ring = NULL; 931 sc->vge_cdata.vge_rx_ring_map = NULL; 932 bus_dma_tag_destroy(sc->vge_cdata.vge_rx_ring_tag); 933 sc->vge_cdata.vge_rx_ring_tag = NULL; 934 } 935 /* Tx buffers. */ 936 if (sc->vge_cdata.vge_tx_tag != NULL) { 937 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 938 txd = &sc->vge_cdata.vge_txdesc[i]; 939 if (txd->tx_dmamap != NULL) { 940 bus_dmamap_destroy(sc->vge_cdata.vge_tx_tag, 941 txd->tx_dmamap); 942 txd->tx_dmamap = NULL; 943 } 944 } 945 bus_dma_tag_destroy(sc->vge_cdata.vge_tx_tag); 946 sc->vge_cdata.vge_tx_tag = NULL; 947 } 948 /* Rx buffers. */ 949 if (sc->vge_cdata.vge_rx_tag != NULL) { 950 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 951 rxd = &sc->vge_cdata.vge_rxdesc[i]; 952 if (rxd->rx_dmamap != NULL) { 953 bus_dmamap_destroy(sc->vge_cdata.vge_rx_tag, 954 rxd->rx_dmamap); 955 rxd->rx_dmamap = NULL; 956 } 957 } 958 if (sc->vge_cdata.vge_rx_sparemap != NULL) { 959 bus_dmamap_destroy(sc->vge_cdata.vge_rx_tag, 960 sc->vge_cdata.vge_rx_sparemap); 961 sc->vge_cdata.vge_rx_sparemap = NULL; 962 } 963 bus_dma_tag_destroy(sc->vge_cdata.vge_rx_tag); 964 sc->vge_cdata.vge_rx_tag = NULL; 965 } 966 967 if (sc->vge_cdata.vge_buffer_tag != NULL) { 968 bus_dma_tag_destroy(sc->vge_cdata.vge_buffer_tag); 969 sc->vge_cdata.vge_buffer_tag = NULL; 970 } 971 if (sc->vge_cdata.vge_ring_tag != NULL) { 972 bus_dma_tag_destroy(sc->vge_cdata.vge_ring_tag); 973 sc->vge_cdata.vge_ring_tag = NULL; 974 } 975} 976 977/* 978 * Attach the interface. Allocate softc structures, do ifmedia 979 * setup and ethernet/BPF attach. 980 */ 981static int 982vge_attach(device_t dev) 983{ 984 u_char eaddr[ETHER_ADDR_LEN]; 985 struct vge_softc *sc; 986 struct ifnet *ifp; 987 int error = 0, cap, i, msic, rid; 988 989 sc = device_get_softc(dev); 990 sc->vge_dev = dev; 991 992 mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 993 MTX_DEF); 994 callout_init_mtx(&sc->vge_watchdog, &sc->vge_mtx, 0); 995 996 /* 997 * Map control/status registers. 998 */ 999 pci_enable_busmaster(dev); 1000 1001 rid = PCIR_BAR(1); 1002 sc->vge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1003 RF_ACTIVE); 1004 1005 if (sc->vge_res == NULL) { 1006 device_printf(dev, "couldn't map ports/memory\n"); 1007 error = ENXIO; 1008 goto fail; 1009 } 1010 1011 if (pci_find_extcap(dev, PCIY_EXPRESS, &cap) == 0) { 1012 sc->vge_flags |= VGE_FLAG_PCIE; 1013 sc->vge_expcap = cap; 1014 } 1015 rid = 0; 1016 msic = pci_msi_count(dev); 1017 if (msi_disable == 0 && msic > 0) { 1018 msic = 1; 1019 if (pci_alloc_msi(dev, &msic) == 0) { 1020 if (msic == 1) { 1021 sc->vge_flags |= VGE_FLAG_MSI; 1022 device_printf(dev, "Using %d MSI message\n", 1023 msic); 1024 rid = 1; 1025 } else 1026 pci_release_msi(dev); 1027 } 1028 } 1029 1030 /* Allocate interrupt */ 1031 sc->vge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1032 ((sc->vge_flags & VGE_FLAG_MSI) ? 0 : RF_SHAREABLE) | RF_ACTIVE); 1033 if (sc->vge_irq == NULL) { 1034 device_printf(dev, "couldn't map interrupt\n"); 1035 error = ENXIO; 1036 goto fail; 1037 } 1038 1039 /* Reset the adapter. */ 1040 vge_reset(sc); 1041 /* Reload EEPROM. */ 1042 CSR_WRITE_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 1043 for (i = 0; i < VGE_TIMEOUT; i++) { 1044 DELAY(5); 1045 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 1046 break; 1047 } 1048 if (i == VGE_TIMEOUT) 1049 device_printf(dev, "EEPROM reload timed out\n"); 1050 /* 1051 * Clear PACPI as EEPROM reload will set the bit. Otherwise 1052 * MAC will receive magic packet which in turn confuses 1053 * controller. 1054 */ 1055 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 1056 1057 /* 1058 * Get station address from the EEPROM. 1059 */ 1060 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 1061 /* 1062 * Save configured PHY address. 1063 * It seems the PHY address of PCIe controllers just 1064 * reflects media jump strapping status so we assume the 1065 * internal PHY address of PCIe controller is at 1. 1066 */ 1067 if ((sc->vge_flags & VGE_FLAG_PCIE) != 0) 1068 sc->vge_phyaddr = 1; 1069 else 1070 sc->vge_phyaddr = CSR_READ_1(sc, VGE_MIICFG) & 1071 VGE_MIICFG_PHYADDR; 1072 vge_sysctl_node(sc); 1073 error = vge_dma_alloc(sc); 1074 if (error) 1075 goto fail; 1076 1077 ifp = sc->vge_ifp = if_alloc(IFT_ETHER); 1078 if (ifp == NULL) { 1079 device_printf(dev, "can not if_alloc()\n"); 1080 error = ENOSPC; 1081 goto fail; 1082 } 1083 1084 /* Do MII setup */ 1085 if (mii_phy_probe(dev, &sc->vge_miibus, 1086 vge_ifmedia_upd, vge_ifmedia_sts)) { 1087 device_printf(dev, "MII without any phy!\n"); 1088 error = ENXIO; 1089 goto fail; 1090 } 1091 1092 ifp->if_softc = sc; 1093 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1094 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1095 ifp->if_ioctl = vge_ioctl; 1096 ifp->if_capabilities = IFCAP_VLAN_MTU; 1097 ifp->if_start = vge_start; 1098 ifp->if_hwassist = VGE_CSUM_FEATURES; 1099 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | 1100 IFCAP_VLAN_HWTAGGING; 1101 ifp->if_capenable = ifp->if_capabilities; 1102#ifdef DEVICE_POLLING 1103 ifp->if_capabilities |= IFCAP_POLLING; 1104#endif 1105 ifp->if_init = vge_init; 1106 IFQ_SET_MAXLEN(&ifp->if_snd, VGE_TX_DESC_CNT - 1); 1107 ifp->if_snd.ifq_drv_maxlen = VGE_TX_DESC_CNT - 1; 1108 IFQ_SET_READY(&ifp->if_snd); 1109 1110 /* 1111 * Call MI attach routine. 1112 */ 1113 ether_ifattach(ifp, eaddr); 1114 1115 /* Tell the upper layer(s) we support long frames. */ 1116 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1117 1118 /* Hook interrupt last to avoid having to lock softc */ 1119 error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE, 1120 NULL, vge_intr, sc, &sc->vge_intrhand); 1121 1122 if (error) { 1123 device_printf(dev, "couldn't set up irq\n"); 1124 ether_ifdetach(ifp); 1125 goto fail; 1126 } 1127 1128fail: 1129 if (error) 1130 vge_detach(dev); 1131 1132 return (error); 1133} 1134 1135/* 1136 * Shutdown hardware and free up resources. This can be called any 1137 * time after the mutex has been initialized. It is called in both 1138 * the error case in attach and the normal detach case so it needs 1139 * to be careful about only freeing resources that have actually been 1140 * allocated. 1141 */ 1142static int 1143vge_detach(device_t dev) 1144{ 1145 struct vge_softc *sc; 1146 struct ifnet *ifp; 1147 1148 sc = device_get_softc(dev); 1149 KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized")); 1150 ifp = sc->vge_ifp; 1151 1152#ifdef DEVICE_POLLING 1153 if (ifp->if_capenable & IFCAP_POLLING) 1154 ether_poll_deregister(ifp); 1155#endif 1156 1157 /* These should only be active if attach succeeded */ 1158 if (device_is_attached(dev)) { 1159 ether_ifdetach(ifp); 1160 VGE_LOCK(sc); 1161 vge_stop(sc); 1162 VGE_UNLOCK(sc); 1163 callout_drain(&sc->vge_watchdog); 1164 } 1165 if (sc->vge_miibus) 1166 device_delete_child(dev, sc->vge_miibus); 1167 bus_generic_detach(dev); 1168 1169 if (sc->vge_intrhand) 1170 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); 1171 if (sc->vge_irq) 1172 bus_release_resource(dev, SYS_RES_IRQ, 1173 sc->vge_flags & VGE_FLAG_MSI ? 1 : 0, sc->vge_irq); 1174 if (sc->vge_flags & VGE_FLAG_MSI) 1175 pci_release_msi(dev); 1176 if (sc->vge_res) 1177 bus_release_resource(dev, SYS_RES_MEMORY, 1178 PCIR_BAR(1), sc->vge_res); 1179 if (ifp) 1180 if_free(ifp); 1181 1182 vge_dma_free(sc); 1183 mtx_destroy(&sc->vge_mtx); 1184 1185 return (0); 1186} 1187 1188static void 1189vge_discard_rxbuf(struct vge_softc *sc, int prod) 1190{ 1191 struct vge_rxdesc *rxd; 1192 int i; 1193 1194 rxd = &sc->vge_cdata.vge_rxdesc[prod]; 1195 rxd->rx_desc->vge_sts = 0; 1196 rxd->rx_desc->vge_ctl = 0; 1197 1198 /* 1199 * Note: the manual fails to document the fact that for 1200 * proper opration, the driver needs to replentish the RX 1201 * DMA ring 4 descriptors at a time (rather than one at a 1202 * time, like most chips). We can allocate the new buffers 1203 * but we should not set the OWN bits until we're ready 1204 * to hand back 4 of them in one shot. 1205 */ 1206 if ((prod % VGE_RXCHUNK) == (VGE_RXCHUNK - 1)) { 1207 for (i = VGE_RXCHUNK; i > 0; i--) { 1208 rxd->rx_desc->vge_sts = htole32(VGE_RDSTS_OWN); 1209 rxd = rxd->rxd_prev; 1210 } 1211 sc->vge_cdata.vge_rx_commit += VGE_RXCHUNK; 1212 } 1213} 1214 1215static int 1216vge_newbuf(struct vge_softc *sc, int prod) 1217{ 1218 struct vge_rxdesc *rxd; 1219 struct mbuf *m; 1220 bus_dma_segment_t segs[1]; 1221 bus_dmamap_t map; 1222 int i, nsegs; 1223 1224 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1225 if (m == NULL) 1226 return (ENOBUFS); 1227 /* 1228 * This is part of an evil trick to deal with strict-alignment 1229 * architectures. The VIA chip requires RX buffers to be aligned 1230 * on 32-bit boundaries, but that will hose strict-alignment 1231 * architectures. To get around this, we leave some empty space 1232 * at the start of each buffer and for non-strict-alignment hosts, 1233 * we copy the buffer back two bytes to achieve word alignment. 1234 * This is slightly more efficient than allocating a new buffer, 1235 * copying the contents, and discarding the old buffer. 1236 */ 1237 m->m_len = m->m_pkthdr.len = MCLBYTES; 1238 m_adj(m, VGE_RX_BUF_ALIGN); 1239 1240 if (bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_rx_tag, 1241 sc->vge_cdata.vge_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1242 m_freem(m); 1243 return (ENOBUFS); 1244 } 1245 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1246 1247 rxd = &sc->vge_cdata.vge_rxdesc[prod]; 1248 if (rxd->rx_m != NULL) { 1249 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap, 1250 BUS_DMASYNC_POSTREAD); 1251 bus_dmamap_unload(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap); 1252 } 1253 map = rxd->rx_dmamap; 1254 rxd->rx_dmamap = sc->vge_cdata.vge_rx_sparemap; 1255 sc->vge_cdata.vge_rx_sparemap = map; 1256 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap, 1257 BUS_DMASYNC_PREREAD); 1258 rxd->rx_m = m; 1259 1260 rxd->rx_desc->vge_sts = 0; 1261 rxd->rx_desc->vge_ctl = 0; 1262 rxd->rx_desc->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 1263 rxd->rx_desc->vge_addrhi = htole32(VGE_ADDR_HI(segs[0].ds_addr) | 1264 (VGE_BUFLEN(segs[0].ds_len) << 16) | VGE_RXDESC_I); 1265 1266 /* 1267 * Note: the manual fails to document the fact that for 1268 * proper operation, the driver needs to replenish the RX 1269 * DMA ring 4 descriptors at a time (rather than one at a 1270 * time, like most chips). We can allocate the new buffers 1271 * but we should not set the OWN bits until we're ready 1272 * to hand back 4 of them in one shot. 1273 */ 1274 if ((prod % VGE_RXCHUNK) == (VGE_RXCHUNK - 1)) { 1275 for (i = VGE_RXCHUNK; i > 0; i--) { 1276 rxd->rx_desc->vge_sts = htole32(VGE_RDSTS_OWN); 1277 rxd = rxd->rxd_prev; 1278 } 1279 sc->vge_cdata.vge_rx_commit += VGE_RXCHUNK; 1280 } 1281 1282 return (0); 1283} 1284 1285static int 1286vge_tx_list_init(struct vge_softc *sc) 1287{ 1288 struct vge_ring_data *rd; 1289 struct vge_txdesc *txd; 1290 int i; 1291 1292 VGE_LOCK_ASSERT(sc); 1293 1294 sc->vge_cdata.vge_tx_prodidx = 0; 1295 sc->vge_cdata.vge_tx_considx = 0; 1296 sc->vge_cdata.vge_tx_cnt = 0; 1297 1298 rd = &sc->vge_rdata; 1299 bzero(rd->vge_tx_ring, VGE_TX_LIST_SZ); 1300 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 1301 txd = &sc->vge_cdata.vge_txdesc[i]; 1302 txd->tx_m = NULL; 1303 txd->tx_desc = &rd->vge_tx_ring[i]; 1304 } 1305 1306 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1307 sc->vge_cdata.vge_tx_ring_map, 1308 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1309 1310 return (0); 1311} 1312 1313static int 1314vge_rx_list_init(struct vge_softc *sc) 1315{ 1316 struct vge_ring_data *rd; 1317 struct vge_rxdesc *rxd; 1318 int i; 1319 1320 VGE_LOCK_ASSERT(sc); 1321 1322 sc->vge_cdata.vge_rx_prodidx = 0; 1323 sc->vge_cdata.vge_head = NULL; 1324 sc->vge_cdata.vge_tail = NULL; 1325 sc->vge_cdata.vge_rx_commit = 0; 1326 1327 rd = &sc->vge_rdata; 1328 bzero(rd->vge_rx_ring, VGE_RX_LIST_SZ); 1329 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1330 rxd = &sc->vge_cdata.vge_rxdesc[i]; 1331 rxd->rx_m = NULL; 1332 rxd->rx_desc = &rd->vge_rx_ring[i]; 1333 if (i == 0) 1334 rxd->rxd_prev = 1335 &sc->vge_cdata.vge_rxdesc[VGE_RX_DESC_CNT - 1]; 1336 else 1337 rxd->rxd_prev = &sc->vge_cdata.vge_rxdesc[i - 1]; 1338 if (vge_newbuf(sc, i) != 0) 1339 return (ENOBUFS); 1340 } 1341 1342 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, 1343 sc->vge_cdata.vge_rx_ring_map, 1344 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1345 1346 sc->vge_cdata.vge_rx_commit = 0; 1347 1348 return (0); 1349} 1350 1351static void 1352vge_freebufs(struct vge_softc *sc) 1353{ 1354 struct vge_txdesc *txd; 1355 struct vge_rxdesc *rxd; 1356 struct ifnet *ifp; 1357 int i; 1358 1359 VGE_LOCK_ASSERT(sc); 1360 1361 ifp = sc->vge_ifp; 1362 /* 1363 * Free RX and TX mbufs still in the queues. 1364 */ 1365 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1366 rxd = &sc->vge_cdata.vge_rxdesc[i]; 1367 if (rxd->rx_m != NULL) { 1368 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, 1369 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 1370 bus_dmamap_unload(sc->vge_cdata.vge_rx_tag, 1371 rxd->rx_dmamap); 1372 m_freem(rxd->rx_m); 1373 rxd->rx_m = NULL; 1374 } 1375 } 1376 1377 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 1378 txd = &sc->vge_cdata.vge_txdesc[i]; 1379 if (txd->tx_m != NULL) { 1380 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, 1381 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1382 bus_dmamap_unload(sc->vge_cdata.vge_tx_tag, 1383 txd->tx_dmamap); 1384 m_freem(txd->tx_m); 1385 txd->tx_m = NULL; 1386 ifp->if_oerrors++; 1387 } 1388 } 1389} 1390 1391#ifndef __NO_STRICT_ALIGNMENT 1392static __inline void 1393vge_fixup_rx(struct mbuf *m) 1394{ 1395 int i; 1396 uint16_t *src, *dst; 1397 1398 src = mtod(m, uint16_t *); 1399 dst = src - 1; 1400 1401 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1402 *dst++ = *src++; 1403 1404 m->m_data -= ETHER_ALIGN; 1405} 1406#endif 1407 1408/* 1409 * RX handler. We support the reception of jumbo frames that have 1410 * been fragmented across multiple 2K mbuf cluster buffers. 1411 */ 1412static int 1413vge_rxeof(struct vge_softc *sc, int count) 1414{ 1415 struct mbuf *m; 1416 struct ifnet *ifp; 1417 int prod, prog, total_len; 1418 struct vge_rxdesc *rxd; 1419 struct vge_rx_desc *cur_rx; 1420 uint32_t rxstat, rxctl; 1421 1422 VGE_LOCK_ASSERT(sc); 1423 1424 ifp = sc->vge_ifp; 1425 1426 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, 1427 sc->vge_cdata.vge_rx_ring_map, 1428 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1429 1430 prod = sc->vge_cdata.vge_rx_prodidx; 1431 for (prog = 0; count > 0 && 1432 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 1433 VGE_RX_DESC_INC(prod)) { 1434 cur_rx = &sc->vge_rdata.vge_rx_ring[prod]; 1435 rxstat = le32toh(cur_rx->vge_sts); 1436 if ((rxstat & VGE_RDSTS_OWN) != 0) 1437 break; 1438 count--; 1439 prog++; 1440 rxctl = le32toh(cur_rx->vge_ctl); 1441 total_len = VGE_RXBYTES(rxstat); 1442 rxd = &sc->vge_cdata.vge_rxdesc[prod]; 1443 m = rxd->rx_m; 1444 1445 /* 1446 * If the 'start of frame' bit is set, this indicates 1447 * either the first fragment in a multi-fragment receive, 1448 * or an intermediate fragment. Either way, we want to 1449 * accumulate the buffers. 1450 */ 1451 if ((rxstat & VGE_RXPKT_SOF) != 0) { 1452 if (vge_newbuf(sc, prod) != 0) { 1453 ifp->if_iqdrops++; 1454 VGE_CHAIN_RESET(sc); 1455 vge_discard_rxbuf(sc, prod); 1456 continue; 1457 } 1458 m->m_len = MCLBYTES - VGE_RX_BUF_ALIGN; 1459 if (sc->vge_cdata.vge_head == NULL) { 1460 sc->vge_cdata.vge_head = m; 1461 sc->vge_cdata.vge_tail = m; 1462 } else { 1463 m->m_flags &= ~M_PKTHDR; 1464 sc->vge_cdata.vge_tail->m_next = m; 1465 sc->vge_cdata.vge_tail = m; 1466 } 1467 continue; 1468 } 1469 1470 /* 1471 * Bad/error frames will have the RXOK bit cleared. 1472 * However, there's one error case we want to allow: 1473 * if a VLAN tagged frame arrives and the chip can't 1474 * match it against the CAM filter, it considers this 1475 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1476 * We don't want to drop the frame though: our VLAN 1477 * filtering is done in software. 1478 * We also want to receive bad-checksummed frames and 1479 * and frames with bad-length. 1480 */ 1481 if ((rxstat & VGE_RDSTS_RXOK) == 0 && 1482 (rxstat & (VGE_RDSTS_VIDM | VGE_RDSTS_RLERR | 1483 VGE_RDSTS_CSUMERR)) == 0) { 1484 ifp->if_ierrors++; 1485 /* 1486 * If this is part of a multi-fragment packet, 1487 * discard all the pieces. 1488 */ 1489 VGE_CHAIN_RESET(sc); 1490 vge_discard_rxbuf(sc, prod); 1491 continue; 1492 } 1493 1494 if (vge_newbuf(sc, prod) != 0) { 1495 ifp->if_iqdrops++; 1496 VGE_CHAIN_RESET(sc); 1497 vge_discard_rxbuf(sc, prod); 1498 continue; 1499 } 1500 1501 /* Chain received mbufs. */ 1502 if (sc->vge_cdata.vge_head != NULL) { 1503 m->m_len = total_len % (MCLBYTES - VGE_RX_BUF_ALIGN); 1504 /* 1505 * Special case: if there's 4 bytes or less 1506 * in this buffer, the mbuf can be discarded: 1507 * the last 4 bytes is the CRC, which we don't 1508 * care about anyway. 1509 */ 1510 if (m->m_len <= ETHER_CRC_LEN) { 1511 sc->vge_cdata.vge_tail->m_len -= 1512 (ETHER_CRC_LEN - m->m_len); 1513 m_freem(m); 1514 } else { 1515 m->m_len -= ETHER_CRC_LEN; 1516 m->m_flags &= ~M_PKTHDR; 1517 sc->vge_cdata.vge_tail->m_next = m; 1518 } 1519 m = sc->vge_cdata.vge_head; 1520 m->m_flags |= M_PKTHDR; 1521 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1522 } else { 1523 m->m_flags |= M_PKTHDR; 1524 m->m_pkthdr.len = m->m_len = 1525 (total_len - ETHER_CRC_LEN); 1526 } 1527 1528#ifndef __NO_STRICT_ALIGNMENT 1529 vge_fixup_rx(m); 1530#endif 1531 m->m_pkthdr.rcvif = ifp; 1532 1533 /* Do RX checksumming if enabled */ 1534 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 1535 (rxctl & VGE_RDCTL_FRAG) == 0) { 1536 /* Check IP header checksum */ 1537 if ((rxctl & VGE_RDCTL_IPPKT) != 0) 1538 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1539 if ((rxctl & VGE_RDCTL_IPCSUMOK) != 0) 1540 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1541 1542 /* Check TCP/UDP checksum */ 1543 if (rxctl & (VGE_RDCTL_TCPPKT | VGE_RDCTL_UDPPKT) && 1544 rxctl & VGE_RDCTL_PROTOCSUMOK) { 1545 m->m_pkthdr.csum_flags |= 1546 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1547 m->m_pkthdr.csum_data = 0xffff; 1548 } 1549 } 1550 1551 if ((rxstat & VGE_RDSTS_VTAG) != 0) { 1552 /* 1553 * The 32-bit rxctl register is stored in little-endian. 1554 * However, the 16-bit vlan tag is stored in big-endian, 1555 * so we have to byte swap it. 1556 */ 1557 m->m_pkthdr.ether_vtag = 1558 bswap16(rxctl & VGE_RDCTL_VLANID); 1559 m->m_flags |= M_VLANTAG; 1560 } 1561 1562 VGE_UNLOCK(sc); 1563 (*ifp->if_input)(ifp, m); 1564 VGE_LOCK(sc); 1565 sc->vge_cdata.vge_head = NULL; 1566 sc->vge_cdata.vge_tail = NULL; 1567 } 1568 1569 if (prog > 0) { 1570 sc->vge_cdata.vge_rx_prodidx = prod; 1571 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, 1572 sc->vge_cdata.vge_rx_ring_map, 1573 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1574 /* Update residue counter. */ 1575 if (sc->vge_cdata.vge_rx_commit != 0) { 1576 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, 1577 sc->vge_cdata.vge_rx_commit); 1578 sc->vge_cdata.vge_rx_commit = 0; 1579 } 1580 } 1581 return (prog); 1582} 1583 1584static void 1585vge_txeof(struct vge_softc *sc) 1586{ 1587 struct ifnet *ifp; 1588 struct vge_tx_desc *cur_tx; 1589 struct vge_txdesc *txd; 1590 uint32_t txstat; 1591 int cons, prod; 1592 1593 VGE_LOCK_ASSERT(sc); 1594 1595 ifp = sc->vge_ifp; 1596 1597 if (sc->vge_cdata.vge_tx_cnt == 0) 1598 return; 1599 1600 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1601 sc->vge_cdata.vge_tx_ring_map, 1602 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1603 1604 /* 1605 * Go through our tx list and free mbufs for those 1606 * frames that have been transmitted. 1607 */ 1608 cons = sc->vge_cdata.vge_tx_considx; 1609 prod = sc->vge_cdata.vge_tx_prodidx; 1610 for (; cons != prod; VGE_TX_DESC_INC(cons)) { 1611 cur_tx = &sc->vge_rdata.vge_tx_ring[cons]; 1612 txstat = le32toh(cur_tx->vge_sts); 1613 if ((txstat & VGE_TDSTS_OWN) != 0) 1614 break; 1615 sc->vge_cdata.vge_tx_cnt--; 1616 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1617 1618 txd = &sc->vge_cdata.vge_txdesc[cons]; 1619 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap, 1620 BUS_DMASYNC_POSTWRITE); 1621 bus_dmamap_unload(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap); 1622 1623 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!\n", 1624 __func__)); 1625 m_freem(txd->tx_m); 1626 txd->tx_m = NULL; 1627 txd->tx_desc->vge_frag[0].vge_addrhi = 0; 1628 } 1629 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1630 sc->vge_cdata.vge_tx_ring_map, 1631 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1632 sc->vge_cdata.vge_tx_considx = cons; 1633 if (sc->vge_cdata.vge_tx_cnt == 0) 1634 sc->vge_timer = 0; 1635} 1636 1637static void 1638vge_link_statchg(void *xsc) 1639{ 1640 struct vge_softc *sc; 1641 struct ifnet *ifp; 1642 struct mii_data *mii; 1643 1644 sc = xsc; 1645 ifp = sc->vge_ifp; 1646 VGE_LOCK_ASSERT(sc); 1647 mii = device_get_softc(sc->vge_miibus); 1648 1649 mii_pollstat(mii); 1650 if ((sc->vge_flags & VGE_FLAG_LINK) != 0) { 1651 if (!(mii->mii_media_status & IFM_ACTIVE)) { 1652 sc->vge_flags &= ~VGE_FLAG_LINK; 1653 if_link_state_change(sc->vge_ifp, 1654 LINK_STATE_DOWN); 1655 } 1656 } else { 1657 if (mii->mii_media_status & IFM_ACTIVE && 1658 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1659 sc->vge_flags |= VGE_FLAG_LINK; 1660 if_link_state_change(sc->vge_ifp, 1661 LINK_STATE_UP); 1662 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1663 vge_start_locked(ifp); 1664 } 1665 } 1666} 1667 1668#ifdef DEVICE_POLLING 1669static int 1670vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1671{ 1672 struct vge_softc *sc = ifp->if_softc; 1673 int rx_npkts = 0; 1674 1675 VGE_LOCK(sc); 1676 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1677 goto done; 1678 1679 rx_npkts = vge_rxeof(sc, count); 1680 vge_txeof(sc); 1681 1682 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1683 vge_start_locked(ifp); 1684 1685 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1686 uint32_t status; 1687 status = CSR_READ_4(sc, VGE_ISR); 1688 if (status == 0xFFFFFFFF) 1689 goto done; 1690 if (status) 1691 CSR_WRITE_4(sc, VGE_ISR, status); 1692 1693 /* 1694 * XXX check behaviour on receiver stalls. 1695 */ 1696 1697 if (status & VGE_ISR_TXDMA_STALL || 1698 status & VGE_ISR_RXDMA_STALL) { 1699 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1700 vge_init_locked(sc); 1701 } 1702 1703 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1704 vge_rxeof(sc, count); 1705 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1706 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1707 } 1708 } 1709done: 1710 VGE_UNLOCK(sc); 1711 return (rx_npkts); 1712} 1713#endif /* DEVICE_POLLING */ 1714 1715static void 1716vge_intr(void *arg) 1717{ 1718 struct vge_softc *sc; 1719 struct ifnet *ifp; 1720 uint32_t status; 1721 1722 sc = arg; 1723 VGE_LOCK(sc); 1724 1725 ifp = sc->vge_ifp; 1726 if ((sc->vge_flags & VGE_FLAG_SUSPENDED) != 0 || 1727 (ifp->if_flags & IFF_UP) == 0) { 1728 VGE_UNLOCK(sc); 1729 return; 1730 } 1731 1732#ifdef DEVICE_POLLING 1733 if (ifp->if_capenable & IFCAP_POLLING) { 1734 VGE_UNLOCK(sc); 1735 return; 1736 } 1737#endif 1738 1739 /* Disable interrupts */ 1740 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1741 status = CSR_READ_4(sc, VGE_ISR); 1742 CSR_WRITE_4(sc, VGE_ISR, status | VGE_ISR_HOLDOFF_RELOAD); 1743 /* If the card has gone away the read returns 0xffff. */ 1744 if (status == 0xFFFFFFFF || (status & VGE_INTRS) == 0) 1745 goto done; 1746 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1747 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1748 vge_rxeof(sc, VGE_RX_DESC_CNT); 1749 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1750 vge_rxeof(sc, VGE_RX_DESC_CNT); 1751 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1752 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1753 } 1754 1755 if (status & (VGE_ISR_TXOK0|VGE_ISR_TXOK_HIPRIO)) 1756 vge_txeof(sc); 1757 1758 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) { 1759 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1760 vge_init_locked(sc); 1761 } 1762 1763 if (status & VGE_ISR_LINKSTS) 1764 vge_link_statchg(sc); 1765 } 1766done: 1767 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1768 /* Re-enable interrupts */ 1769 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1770 1771 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1772 vge_start_locked(ifp); 1773 } 1774 VGE_UNLOCK(sc); 1775} 1776 1777static int 1778vge_encap(struct vge_softc *sc, struct mbuf **m_head) 1779{ 1780 struct vge_txdesc *txd; 1781 struct vge_tx_frag *frag; 1782 struct mbuf *m; 1783 bus_dma_segment_t txsegs[VGE_MAXTXSEGS]; 1784 int error, i, nsegs, padlen; 1785 uint32_t cflags; 1786 1787 VGE_LOCK_ASSERT(sc); 1788 1789 M_ASSERTPKTHDR((*m_head)); 1790 1791 /* Argh. This chip does not autopad short frames. */ 1792 if ((*m_head)->m_pkthdr.len < VGE_MIN_FRAMELEN) { 1793 m = *m_head; 1794 padlen = VGE_MIN_FRAMELEN - m->m_pkthdr.len; 1795 if (M_WRITABLE(m) == 0) { 1796 /* Get a writable copy. */ 1797 m = m_dup(*m_head, M_DONTWAIT); 1798 m_freem(*m_head); 1799 if (m == NULL) { 1800 *m_head = NULL; 1801 return (ENOBUFS); 1802 } 1803 *m_head = m; 1804 } 1805 if (M_TRAILINGSPACE(m) < padlen) { 1806 m = m_defrag(m, M_DONTWAIT); 1807 if (m == NULL) { 1808 m_freem(*m_head); 1809 *m_head = NULL; 1810 return (ENOBUFS); 1811 } 1812 } 1813 /* 1814 * Manually pad short frames, and zero the pad space 1815 * to avoid leaking data. 1816 */ 1817 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1818 m->m_pkthdr.len += padlen; 1819 m->m_len = m->m_pkthdr.len; 1820 *m_head = m; 1821 } 1822 1823 txd = &sc->vge_cdata.vge_txdesc[sc->vge_cdata.vge_tx_prodidx]; 1824 1825 error = bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_tx_tag, 1826 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1827 if (error == EFBIG) { 1828 m = m_collapse(*m_head, M_DONTWAIT, VGE_MAXTXSEGS); 1829 if (m == NULL) { 1830 m_freem(*m_head); 1831 *m_head = NULL; 1832 return (ENOMEM); 1833 } 1834 *m_head = m; 1835 error = bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_tx_tag, 1836 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1837 if (error != 0) { 1838 m_freem(*m_head); 1839 *m_head = NULL; 1840 return (error); 1841 } 1842 } else if (error != 0) 1843 return (error); 1844 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap, 1845 BUS_DMASYNC_PREWRITE); 1846 1847 m = *m_head; 1848 cflags = 0; 1849 1850 /* Configure checksum offload. */ 1851 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 1852 cflags |= VGE_TDCTL_IPCSUM; 1853 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1854 cflags |= VGE_TDCTL_TCPCSUM; 1855 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1856 cflags |= VGE_TDCTL_UDPCSUM; 1857 1858 /* Configure VLAN. */ 1859 if ((m->m_flags & M_VLANTAG) != 0) 1860 cflags |= m->m_pkthdr.ether_vtag | VGE_TDCTL_VTAG; 1861 txd->tx_desc->vge_sts = htole32(m->m_pkthdr.len << 16); 1862 /* 1863 * XXX 1864 * Velocity family seems to support TSO but no information 1865 * for MSS configuration is available. Also the number of 1866 * fragments supported by a descriptor is too small to hold 1867 * entire 64KB TCP/IP segment. Maybe VGE_TD_LS_MOF, 1868 * VGE_TD_LS_SOF and VGE_TD_LS_EOF could be used to build 1869 * longer chain of buffers but no additional information is 1870 * available. 1871 * 1872 * When telling the chip how many segments there are, we 1873 * must use nsegs + 1 instead of just nsegs. Darned if I 1874 * know why. This also means we can't use the last fragment 1875 * field of Tx descriptor. 1876 */ 1877 txd->tx_desc->vge_ctl = htole32(cflags | ((nsegs + 1) << 28) | 1878 VGE_TD_LS_NORM); 1879 for (i = 0; i < nsegs; i++) { 1880 frag = &txd->tx_desc->vge_frag[i]; 1881 frag->vge_addrlo = htole32(VGE_ADDR_LO(txsegs[i].ds_addr)); 1882 frag->vge_addrhi = htole32(VGE_ADDR_HI(txsegs[i].ds_addr) | 1883 (VGE_BUFLEN(txsegs[i].ds_len) << 16)); 1884 } 1885 1886 sc->vge_cdata.vge_tx_cnt++; 1887 VGE_TX_DESC_INC(sc->vge_cdata.vge_tx_prodidx); 1888 1889 /* 1890 * Finally request interrupt and give the first descriptor 1891 * ownership to hardware. 1892 */ 1893 txd->tx_desc->vge_ctl |= htole32(VGE_TDCTL_TIC); 1894 txd->tx_desc->vge_sts |= htole32(VGE_TDSTS_OWN); 1895 txd->tx_m = m; 1896 1897 return (0); 1898} 1899 1900/* 1901 * Main transmit routine. 1902 */ 1903 1904static void 1905vge_start(struct ifnet *ifp) 1906{ 1907 struct vge_softc *sc; 1908 1909 sc = ifp->if_softc; 1910 VGE_LOCK(sc); 1911 vge_start_locked(ifp); 1912 VGE_UNLOCK(sc); 1913} 1914 1915 1916static void 1917vge_start_locked(struct ifnet *ifp) 1918{ 1919 struct vge_softc *sc; 1920 struct vge_txdesc *txd; 1921 struct mbuf *m_head; 1922 int enq, idx; 1923 1924 sc = ifp->if_softc; 1925 1926 VGE_LOCK_ASSERT(sc); 1927 1928 if ((sc->vge_flags & VGE_FLAG_LINK) == 0 || 1929 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1930 IFF_DRV_RUNNING) 1931 return; 1932 1933 idx = sc->vge_cdata.vge_tx_prodidx; 1934 VGE_TX_DESC_DEC(idx); 1935 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1936 sc->vge_cdata.vge_tx_cnt < VGE_TX_DESC_CNT - 1; ) { 1937 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1938 if (m_head == NULL) 1939 break; 1940 /* 1941 * Pack the data into the transmit ring. If we 1942 * don't have room, set the OACTIVE flag and wait 1943 * for the NIC to drain the ring. 1944 */ 1945 if (vge_encap(sc, &m_head)) { 1946 if (m_head == NULL) 1947 break; 1948 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1949 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1950 break; 1951 } 1952 1953 txd = &sc->vge_cdata.vge_txdesc[idx]; 1954 txd->tx_desc->vge_frag[0].vge_addrhi |= htole32(VGE_TXDESC_Q); 1955 VGE_TX_DESC_INC(idx); 1956 1957 enq++; 1958 /* 1959 * If there's a BPF listener, bounce a copy of this frame 1960 * to him. 1961 */ 1962 ETHER_BPF_MTAP(ifp, m_head); 1963 } 1964 1965 if (enq > 0) { 1966 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1967 sc->vge_cdata.vge_tx_ring_map, 1968 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1969 /* Issue a transmit command. */ 1970 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1971 /* 1972 * Set a timeout in case the chip goes out to lunch. 1973 */ 1974 sc->vge_timer = 5; 1975 } 1976} 1977 1978static void 1979vge_init(void *xsc) 1980{ 1981 struct vge_softc *sc = xsc; 1982 1983 VGE_LOCK(sc); 1984 vge_init_locked(sc); 1985 VGE_UNLOCK(sc); 1986} 1987 1988static void 1989vge_init_locked(struct vge_softc *sc) 1990{ 1991 struct ifnet *ifp = sc->vge_ifp; 1992 struct mii_data *mii; 1993 int error, i; 1994 1995 VGE_LOCK_ASSERT(sc); 1996 mii = device_get_softc(sc->vge_miibus); 1997 1998 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1999 return; 2000 2001 /* 2002 * Cancel pending I/O and free all RX/TX buffers. 2003 */ 2004 vge_stop(sc); 2005 vge_reset(sc); 2006 2007 /* 2008 * Initialize the RX and TX descriptors and mbufs. 2009 */ 2010 2011 error = vge_rx_list_init(sc); 2012 if (error != 0) { 2013 device_printf(sc->vge_dev, "no memory for Rx buffers.\n"); 2014 return; 2015 } 2016 vge_tx_list_init(sc); 2017 /* Clear MAC statistics. */ 2018 vge_stats_clear(sc); 2019 /* Set our station address */ 2020 for (i = 0; i < ETHER_ADDR_LEN; i++) 2021 CSR_WRITE_1(sc, VGE_PAR0 + i, IF_LLADDR(sc->vge_ifp)[i]); 2022 2023 /* 2024 * Set receive FIFO threshold. Also allow transmission and 2025 * reception of VLAN tagged frames. 2026 */ 2027 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 2028 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES); 2029 2030 /* Set DMA burst length */ 2031 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 2032 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 2033 2034 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 2035 2036 /* Set collision backoff algorithm */ 2037 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 2038 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 2039 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 2040 2041 /* Disable LPSEL field in priority resolution */ 2042 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 2043 2044 /* 2045 * Load the addresses of the DMA queues into the chip. 2046 * Note that we only use one transmit queue. 2047 */ 2048 2049 CSR_WRITE_4(sc, VGE_TXDESC_HIADDR, 2050 VGE_ADDR_HI(sc->vge_rdata.vge_tx_ring_paddr)); 2051 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 2052 VGE_ADDR_LO(sc->vge_rdata.vge_tx_ring_paddr)); 2053 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 2054 2055 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 2056 VGE_ADDR_LO(sc->vge_rdata.vge_rx_ring_paddr)); 2057 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 2058 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 2059 2060 /* Configure interrupt moderation. */ 2061 vge_intr_holdoff(sc); 2062 2063 /* Enable and wake up the RX descriptor queue */ 2064 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 2065 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 2066 2067 /* Enable the TX descriptor queue */ 2068 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 2069 2070 /* Init the cam filter. */ 2071 vge_cam_clear(sc); 2072 2073 /* Set up receiver filter. */ 2074 vge_rxfilter(sc); 2075 vge_setvlan(sc); 2076 2077 /* Enable flow control */ 2078 2079 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 2080 2081 /* Enable jumbo frame reception (if desired) */ 2082 2083 /* Start the MAC. */ 2084 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 2085 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 2086 CSR_WRITE_1(sc, VGE_CRS0, 2087 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 2088 2089#ifdef DEVICE_POLLING 2090 /* 2091 * Disable interrupts if we are polling. 2092 */ 2093 if (ifp->if_capenable & IFCAP_POLLING) { 2094 CSR_WRITE_4(sc, VGE_IMR, 0); 2095 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2096 } else /* otherwise ... */ 2097#endif 2098 { 2099 /* 2100 * Enable interrupts. 2101 */ 2102 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2103 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2104 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2105 } 2106 2107 sc->vge_flags &= ~VGE_FLAG_LINK; 2108 mii_mediachg(mii); 2109 2110 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2111 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2112 callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc); 2113} 2114 2115/* 2116 * Set media options. 2117 */ 2118static int 2119vge_ifmedia_upd(struct ifnet *ifp) 2120{ 2121 struct vge_softc *sc; 2122 struct mii_data *mii; 2123 int error; 2124 2125 sc = ifp->if_softc; 2126 VGE_LOCK(sc); 2127 mii = device_get_softc(sc->vge_miibus); 2128 error = mii_mediachg(mii); 2129 VGE_UNLOCK(sc); 2130 2131 return (error); 2132} 2133 2134/* 2135 * Report current media status. 2136 */ 2137static void 2138vge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2139{ 2140 struct vge_softc *sc; 2141 struct mii_data *mii; 2142 2143 sc = ifp->if_softc; 2144 mii = device_get_softc(sc->vge_miibus); 2145 2146 VGE_LOCK(sc); 2147 if ((ifp->if_flags & IFF_UP) == 0) { 2148 VGE_UNLOCK(sc); 2149 return; 2150 } 2151 mii_pollstat(mii); 2152 VGE_UNLOCK(sc); 2153 ifmr->ifm_active = mii->mii_media_active; 2154 ifmr->ifm_status = mii->mii_media_status; 2155} 2156 2157static void 2158vge_miibus_statchg(device_t dev) 2159{ 2160 struct vge_softc *sc; 2161 struct mii_data *mii; 2162 struct ifmedia_entry *ife; 2163 2164 sc = device_get_softc(dev); 2165 mii = device_get_softc(sc->vge_miibus); 2166 ife = mii->mii_media.ifm_cur; 2167 2168 /* 2169 * If the user manually selects a media mode, we need to turn 2170 * on the forced MAC mode bit in the DIAGCTL register. If the 2171 * user happens to choose a full duplex mode, we also need to 2172 * set the 'force full duplex' bit. This applies only to 2173 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2174 * mode is disabled, and in 1000baseT mode, full duplex is 2175 * always implied, so we turn on the forced mode bit but leave 2176 * the FDX bit cleared. 2177 */ 2178 2179 switch (IFM_SUBTYPE(ife->ifm_media)) { 2180 case IFM_AUTO: 2181 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2182 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2183 break; 2184 case IFM_1000_T: 2185 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2186 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2187 break; 2188 case IFM_100_TX: 2189 case IFM_10_T: 2190 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2191 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2192 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2193 } else { 2194 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2195 } 2196 break; 2197 default: 2198 device_printf(dev, "unknown media type: %x\n", 2199 IFM_SUBTYPE(ife->ifm_media)); 2200 break; 2201 } 2202} 2203 2204static int 2205vge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2206{ 2207 struct vge_softc *sc = ifp->if_softc; 2208 struct ifreq *ifr = (struct ifreq *) data; 2209 struct mii_data *mii; 2210 int error = 0, mask; 2211 2212 switch (command) { 2213 case SIOCSIFMTU: 2214 if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2215 error = EINVAL; 2216 ifp->if_mtu = ifr->ifr_mtu; 2217 break; 2218 case SIOCSIFFLAGS: 2219 VGE_LOCK(sc); 2220 if ((ifp->if_flags & IFF_UP) != 0) { 2221 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2222 ((ifp->if_flags ^ sc->vge_if_flags) & 2223 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2224 vge_rxfilter(sc); 2225 else 2226 vge_init_locked(sc); 2227 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2228 vge_stop(sc); 2229 sc->vge_if_flags = ifp->if_flags; 2230 VGE_UNLOCK(sc); 2231 break; 2232 case SIOCADDMULTI: 2233 case SIOCDELMULTI: 2234 VGE_LOCK(sc); 2235 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2236 vge_rxfilter(sc); 2237 VGE_UNLOCK(sc); 2238 break; 2239 case SIOCGIFMEDIA: 2240 case SIOCSIFMEDIA: 2241 mii = device_get_softc(sc->vge_miibus); 2242 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2243 break; 2244 case SIOCSIFCAP: 2245 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2246#ifdef DEVICE_POLLING 2247 if (mask & IFCAP_POLLING) { 2248 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2249 error = ether_poll_register(vge_poll, ifp); 2250 if (error) 2251 return (error); 2252 VGE_LOCK(sc); 2253 /* Disable interrupts */ 2254 CSR_WRITE_4(sc, VGE_IMR, 0); 2255 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2256 ifp->if_capenable |= IFCAP_POLLING; 2257 VGE_UNLOCK(sc); 2258 } else { 2259 error = ether_poll_deregister(ifp); 2260 /* Enable interrupts. */ 2261 VGE_LOCK(sc); 2262 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2263 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2264 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2265 ifp->if_capenable &= ~IFCAP_POLLING; 2266 VGE_UNLOCK(sc); 2267 } 2268 } 2269#endif /* DEVICE_POLLING */ 2270 VGE_LOCK(sc); 2271 if ((mask & IFCAP_TXCSUM) != 0 && 2272 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2273 ifp->if_capenable ^= IFCAP_TXCSUM; 2274 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2275 ifp->if_hwassist |= VGE_CSUM_FEATURES; 2276 else 2277 ifp->if_hwassist &= ~VGE_CSUM_FEATURES; 2278 } 2279 if ((mask & IFCAP_RXCSUM) != 0 && 2280 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 2281 ifp->if_capenable ^= IFCAP_RXCSUM; 2282 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2283 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2284 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2285 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2286 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) { 2287 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2288 vge_setvlan(sc); 2289 } 2290 VGE_UNLOCK(sc); 2291 VLAN_CAPABILITIES(ifp); 2292 break; 2293 default: 2294 error = ether_ioctl(ifp, command, data); 2295 break; 2296 } 2297 2298 return (error); 2299} 2300 2301static void 2302vge_watchdog(void *arg) 2303{ 2304 struct vge_softc *sc; 2305 struct ifnet *ifp; 2306 2307 sc = arg; 2308 VGE_LOCK_ASSERT(sc); 2309 vge_stats_update(sc); 2310 callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc); 2311 if (sc->vge_timer == 0 || --sc->vge_timer > 0) 2312 return; 2313 2314 ifp = sc->vge_ifp; 2315 if_printf(ifp, "watchdog timeout\n"); 2316 ifp->if_oerrors++; 2317 2318 vge_txeof(sc); 2319 vge_rxeof(sc, VGE_RX_DESC_CNT); 2320 2321 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2322 vge_init_locked(sc); 2323} 2324 2325/* 2326 * Stop the adapter and free any mbufs allocated to the 2327 * RX and TX lists. 2328 */ 2329static void 2330vge_stop(struct vge_softc *sc) 2331{ 2332 struct ifnet *ifp; 2333 2334 VGE_LOCK_ASSERT(sc); 2335 ifp = sc->vge_ifp; 2336 sc->vge_timer = 0; 2337 callout_stop(&sc->vge_watchdog); 2338 2339 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2340 2341 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2342 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2343 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2344 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2345 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2346 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2347 2348 vge_stats_update(sc); 2349 VGE_CHAIN_RESET(sc); 2350 vge_txeof(sc); 2351 vge_freebufs(sc); 2352} 2353 2354/* 2355 * Device suspend routine. Stop the interface and save some PCI 2356 * settings in case the BIOS doesn't restore them properly on 2357 * resume. 2358 */ 2359static int 2360vge_suspend(device_t dev) 2361{ 2362 struct vge_softc *sc; 2363 2364 sc = device_get_softc(dev); 2365 2366 VGE_LOCK(sc); 2367 vge_stop(sc); 2368 2369 sc->vge_flags |= VGE_FLAG_SUSPENDED; 2370 VGE_UNLOCK(sc); 2371 2372 return (0); 2373} 2374 2375/* 2376 * Device resume routine. Restore some PCI settings in case the BIOS 2377 * doesn't, re-enable busmastering, and restart the interface if 2378 * appropriate. 2379 */ 2380static int 2381vge_resume(device_t dev) 2382{ 2383 struct vge_softc *sc; 2384 struct ifnet *ifp; 2385 2386 sc = device_get_softc(dev); 2387 ifp = sc->vge_ifp; 2388 2389 /* reenable busmastering */ 2390 pci_enable_busmaster(dev); 2391 pci_enable_io(dev, SYS_RES_MEMORY); 2392 2393 /* reinitialize interface if necessary */ 2394 VGE_LOCK(sc); 2395 if (ifp->if_flags & IFF_UP) { 2396 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2397 vge_init_locked(sc); 2398 } 2399 sc->vge_flags &= ~VGE_FLAG_SUSPENDED; 2400 VGE_UNLOCK(sc); 2401 2402 return (0); 2403} 2404 2405/* 2406 * Stop all chip I/O so that the kernel's probe routines don't 2407 * get confused by errant DMAs when rebooting. 2408 */ 2409static int 2410vge_shutdown(device_t dev) 2411{ 2412 struct vge_softc *sc; 2413 2414 sc = device_get_softc(dev); 2415 2416 VGE_LOCK(sc); 2417 vge_stop(sc); 2418 VGE_UNLOCK(sc); 2419 2420 return (0); 2421} 2422 2423#define VGE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2424 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2425 2426static void 2427vge_sysctl_node(struct vge_softc *sc) 2428{ 2429 struct sysctl_ctx_list *ctx; 2430 struct sysctl_oid_list *child, *parent; 2431 struct sysctl_oid *tree; 2432 struct vge_hw_stats *stats; 2433 2434 stats = &sc->vge_stats; 2435 ctx = device_get_sysctl_ctx(sc->vge_dev); 2436 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->vge_dev)); 2437 2438 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "int_holdoff", 2439 CTLFLAG_RW, &sc->vge_int_holdoff, 0, "interrupt holdoff"); 2440 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "rx_coal_pkt", 2441 CTLFLAG_RW, &sc->vge_rx_coal_pkt, 0, "rx coalescing packet"); 2442 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "tx_coal_pkt", 2443 CTLFLAG_RW, &sc->vge_tx_coal_pkt, 0, "tx coalescing packet"); 2444 2445 /* Pull in device tunables. */ 2446 sc->vge_int_holdoff = VGE_INT_HOLDOFF_DEFAULT; 2447 resource_int_value(device_get_name(sc->vge_dev), 2448 device_get_unit(sc->vge_dev), "int_holdoff", &sc->vge_int_holdoff); 2449 sc->vge_rx_coal_pkt = VGE_RX_COAL_PKT_DEFAULT; 2450 resource_int_value(device_get_name(sc->vge_dev), 2451 device_get_unit(sc->vge_dev), "rx_coal_pkt", &sc->vge_rx_coal_pkt); 2452 sc->vge_tx_coal_pkt = VGE_TX_COAL_PKT_DEFAULT; 2453 resource_int_value(device_get_name(sc->vge_dev), 2454 device_get_unit(sc->vge_dev), "tx_coal_pkt", &sc->vge_tx_coal_pkt); 2455 2456 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 2457 NULL, "VGE statistics"); 2458 parent = SYSCTL_CHILDREN(tree); 2459 2460 /* Rx statistics. */ 2461 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 2462 NULL, "RX MAC statistics"); 2463 child = SYSCTL_CHILDREN(tree); 2464 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames", 2465 &stats->rx_frames, "frames"); 2466 VGE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 2467 &stats->rx_good_frames, "Good frames"); 2468 VGE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 2469 &stats->rx_fifo_oflows, "FIFO overflows"); 2470 VGE_SYSCTL_STAT_ADD32(ctx, child, "runts", 2471 &stats->rx_runts, "Too short frames"); 2472 VGE_SYSCTL_STAT_ADD32(ctx, child, "runts_errs", 2473 &stats->rx_runts_errs, "Too short frames with errors"); 2474 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 2475 &stats->rx_pkts_64, "64 bytes frames"); 2476 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 2477 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 2478 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 2479 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 2480 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 2481 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 2482 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 2483 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 2484 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 2485 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 2486 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 2487 &stats->rx_pkts_1519_max, "1519 to max frames"); 2488 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max_errs", 2489 &stats->rx_pkts_1519_max_errs, "1519 to max frames with error"); 2490 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_jumbo", 2491 &stats->rx_jumbos, "Jumbo frames"); 2492 VGE_SYSCTL_STAT_ADD32(ctx, child, "crcerrs", 2493 &stats->rx_crcerrs, "CRC errors"); 2494 VGE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 2495 &stats->rx_pause_frames, "CRC errors"); 2496 VGE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 2497 &stats->rx_alignerrs, "Alignment errors"); 2498 VGE_SYSCTL_STAT_ADD32(ctx, child, "nobufs", 2499 &stats->rx_nobufs, "Frames with no buffer event"); 2500 VGE_SYSCTL_STAT_ADD32(ctx, child, "sym_errs", 2501 &stats->rx_symerrs, "Frames with symbol errors"); 2502 VGE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 2503 &stats->rx_lenerrs, "Frames with length mismatched"); 2504 2505 /* Tx statistics. */ 2506 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 2507 NULL, "TX MAC statistics"); 2508 child = SYSCTL_CHILDREN(tree); 2509 VGE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 2510 &stats->tx_good_frames, "Good frames"); 2511 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 2512 &stats->tx_pkts_64, "64 bytes frames"); 2513 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 2514 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 2515 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 2516 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 2517 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 2518 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 2519 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 2520 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 2521 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 2522 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 2523 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_jumbo", 2524 &stats->tx_jumbos, "Jumbo frames"); 2525 VGE_SYSCTL_STAT_ADD32(ctx, child, "colls", 2526 &stats->tx_colls, "Collisions"); 2527 VGE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 2528 &stats->tx_latecolls, "Late collisions"); 2529 VGE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 2530 &stats->tx_pause, "Pause frames"); 2531#ifdef VGE_ENABLE_SQEERR 2532 VGE_SYSCTL_STAT_ADD32(ctx, child, "sqeerrs", 2533 &stats->tx_sqeerrs, "SQE errors"); 2534#endif 2535 /* Clear MAC statistics. */ 2536 vge_stats_clear(sc); 2537} 2538 2539#undef VGE_SYSCTL_STAT_ADD32 2540 2541static void 2542vge_stats_clear(struct vge_softc *sc) 2543{ 2544 int i; 2545 2546 VGE_LOCK_ASSERT(sc); 2547 2548 CSR_WRITE_1(sc, VGE_MIBCSR, 2549 CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_FREEZE); 2550 CSR_WRITE_1(sc, VGE_MIBCSR, 2551 CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_CLR); 2552 for (i = VGE_TIMEOUT; i > 0; i--) { 2553 DELAY(1); 2554 if ((CSR_READ_1(sc, VGE_MIBCSR) & VGE_MIBCSR_CLR) == 0) 2555 break; 2556 } 2557 if (i == 0) 2558 device_printf(sc->vge_dev, "MIB clear timed out!\n"); 2559 CSR_WRITE_1(sc, VGE_MIBCSR, CSR_READ_1(sc, VGE_MIBCSR) & 2560 ~VGE_MIBCSR_FREEZE); 2561} 2562 2563static void 2564vge_stats_update(struct vge_softc *sc) 2565{ 2566 struct vge_hw_stats *stats; 2567 struct ifnet *ifp; 2568 uint32_t mib[VGE_MIB_CNT], val; 2569 int i; 2570 2571 VGE_LOCK_ASSERT(sc); 2572 2573 stats = &sc->vge_stats; 2574 ifp = sc->vge_ifp; 2575 2576 CSR_WRITE_1(sc, VGE_MIBCSR, 2577 CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_FLUSH); 2578 for (i = VGE_TIMEOUT; i > 0; i--) { 2579 DELAY(1); 2580 if ((CSR_READ_1(sc, VGE_MIBCSR) & VGE_MIBCSR_FLUSH) == 0) 2581 break; 2582 } 2583 if (i == 0) { 2584 device_printf(sc->vge_dev, "MIB counter dump timed out!\n"); 2585 vge_stats_clear(sc); 2586 return; 2587 } 2588 2589 bzero(mib, sizeof(mib)); 2590reset_idx: 2591 /* Set MIB read index to 0. */ 2592 CSR_WRITE_1(sc, VGE_MIBCSR, 2593 CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_RINI); 2594 for (i = 0; i < VGE_MIB_CNT; i++) { 2595 val = CSR_READ_4(sc, VGE_MIBDATA); 2596 if (i != VGE_MIB_DATA_IDX(val)) { 2597 /* Reading interrupted. */ 2598 goto reset_idx; 2599 } 2600 mib[i] = val & VGE_MIB_DATA_MASK; 2601 } 2602 2603 /* Rx stats. */ 2604 stats->rx_frames += mib[VGE_MIB_RX_FRAMES]; 2605 stats->rx_good_frames += mib[VGE_MIB_RX_GOOD_FRAMES]; 2606 stats->rx_fifo_oflows += mib[VGE_MIB_RX_FIFO_OVERRUNS]; 2607 stats->rx_runts += mib[VGE_MIB_RX_RUNTS]; 2608 stats->rx_runts_errs += mib[VGE_MIB_RX_RUNTS_ERRS]; 2609 stats->rx_pkts_64 += mib[VGE_MIB_RX_PKTS_64]; 2610 stats->rx_pkts_65_127 += mib[VGE_MIB_RX_PKTS_65_127]; 2611 stats->rx_pkts_128_255 += mib[VGE_MIB_RX_PKTS_128_255]; 2612 stats->rx_pkts_256_511 += mib[VGE_MIB_RX_PKTS_256_511]; 2613 stats->rx_pkts_512_1023 += mib[VGE_MIB_RX_PKTS_512_1023]; 2614 stats->rx_pkts_1024_1518 += mib[VGE_MIB_RX_PKTS_1024_1518]; 2615 stats->rx_pkts_1519_max += mib[VGE_MIB_RX_PKTS_1519_MAX]; 2616 stats->rx_pkts_1519_max_errs += mib[VGE_MIB_RX_PKTS_1519_MAX_ERRS]; 2617 stats->rx_jumbos += mib[VGE_MIB_RX_JUMBOS]; 2618 stats->rx_crcerrs += mib[VGE_MIB_RX_CRCERRS]; 2619 stats->rx_pause_frames += mib[VGE_MIB_RX_PAUSE]; 2620 stats->rx_alignerrs += mib[VGE_MIB_RX_ALIGNERRS]; 2621 stats->rx_nobufs += mib[VGE_MIB_RX_NOBUFS]; 2622 stats->rx_symerrs += mib[VGE_MIB_RX_SYMERRS]; 2623 stats->rx_lenerrs += mib[VGE_MIB_RX_LENERRS]; 2624 2625 /* Tx stats. */ 2626 stats->tx_good_frames += mib[VGE_MIB_TX_GOOD_FRAMES]; 2627 stats->tx_pkts_64 += mib[VGE_MIB_TX_PKTS_64]; 2628 stats->tx_pkts_65_127 += mib[VGE_MIB_TX_PKTS_65_127]; 2629 stats->tx_pkts_128_255 += mib[VGE_MIB_TX_PKTS_128_255]; 2630 stats->tx_pkts_256_511 += mib[VGE_MIB_TX_PKTS_256_511]; 2631 stats->tx_pkts_512_1023 += mib[VGE_MIB_TX_PKTS_512_1023]; 2632 stats->tx_pkts_1024_1518 += mib[VGE_MIB_TX_PKTS_1024_1518]; 2633 stats->tx_jumbos += mib[VGE_MIB_TX_JUMBOS]; 2634 stats->tx_colls += mib[VGE_MIB_TX_COLLS]; 2635 stats->tx_pause += mib[VGE_MIB_TX_PAUSE]; 2636#ifdef VGE_ENABLE_SQEERR 2637 stats->tx_sqeerrs += mib[VGE_MIB_TX_SQEERRS]; 2638#endif 2639 stats->tx_latecolls += mib[VGE_MIB_TX_LATECOLLS]; 2640 2641 /* Update counters in ifnet. */ 2642 ifp->if_opackets += mib[VGE_MIB_TX_GOOD_FRAMES]; 2643 2644 ifp->if_collisions += mib[VGE_MIB_TX_COLLS] + 2645 mib[VGE_MIB_TX_LATECOLLS]; 2646 2647 ifp->if_oerrors += mib[VGE_MIB_TX_COLLS] + 2648 mib[VGE_MIB_TX_LATECOLLS]; 2649 2650 ifp->if_ipackets += mib[VGE_MIB_RX_GOOD_FRAMES]; 2651 2652 ifp->if_ierrors += mib[VGE_MIB_RX_FIFO_OVERRUNS] + 2653 mib[VGE_MIB_RX_RUNTS] + 2654 mib[VGE_MIB_RX_RUNTS_ERRS] + 2655 mib[VGE_MIB_RX_CRCERRS] + 2656 mib[VGE_MIB_RX_ALIGNERRS] + 2657 mib[VGE_MIB_RX_NOBUFS] + 2658 mib[VGE_MIB_RX_SYMERRS] + 2659 mib[VGE_MIB_RX_LENERRS]; 2660} 2661 2662static void 2663vge_intr_holdoff(struct vge_softc *sc) 2664{ 2665 uint8_t intctl; 2666 2667 VGE_LOCK_ASSERT(sc); 2668 2669 /* 2670 * Set Tx interrupt supression threshold. 2671 * It's possible to use single-shot timer in VGE_CRS1 register 2672 * in Tx path such that driver can remove most of Tx completion 2673 * interrupts. However this requires additional access to 2674 * VGE_CRS1 register to reload the timer in addintion to 2675 * activating Tx kick command. Another downside is we don't know 2676 * what single-shot timer value should be used in advance so 2677 * reclaiming transmitted mbufs could be delayed a lot which in 2678 * turn slows down Tx operation. 2679 */ 2680 CSR_WRITE_1(sc, VGE_CAMCTL, VGE_PAGESEL_TXSUPPTHR); 2681 CSR_WRITE_1(sc, VGE_TXSUPPTHR, sc->vge_tx_coal_pkt); 2682 2683 /* Set Rx interrupt suppresion threshold. */ 2684 CSR_WRITE_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 2685 CSR_WRITE_1(sc, VGE_RXSUPPTHR, sc->vge_rx_coal_pkt); 2686 2687 intctl = CSR_READ_1(sc, VGE_INTCTL1); 2688 intctl &= ~VGE_INTCTL_SC_RELOAD; 2689 intctl |= VGE_INTCTL_HC_RELOAD; 2690 if (sc->vge_tx_coal_pkt <= 0) 2691 intctl |= VGE_INTCTL_TXINTSUP_DISABLE; 2692 else 2693 intctl &= ~VGE_INTCTL_TXINTSUP_DISABLE; 2694 if (sc->vge_rx_coal_pkt <= 0) 2695 intctl |= VGE_INTCTL_RXINTSUP_DISABLE; 2696 else 2697 intctl &= ~VGE_INTCTL_RXINTSUP_DISABLE; 2698 CSR_WRITE_1(sc, VGE_INTCTL1, intctl); 2699 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_HOLDOFF); 2700 if (sc->vge_int_holdoff > 0) { 2701 /* Set interrupt holdoff timer. */ 2702 CSR_WRITE_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 2703 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 2704 VGE_INT_HOLDOFF_USEC(sc->vge_int_holdoff)); 2705 /* Enable holdoff timer. */ 2706 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 2707 } 2708} 2709