if_vge.c revision 200548
1/*- 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/vge/if_vge.c 200548 2009-12-14 22:00:11Z yongari $"); 35 36/* 37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 46 * combines a tri-speed ethernet MAC and PHY, with the following 47 * features: 48 * 49 * o Jumbo frame support up to 16K 50 * o Transmit and receive flow control 51 * o IPv4 checksum offload 52 * o VLAN tag insertion and stripping 53 * o TCP large send 54 * o 64-bit multicast hash table filter 55 * o 64 entry CAM filter 56 * o 16K RX FIFO and 48K TX FIFO memory 57 * o Interrupt moderation 58 * 59 * The VT6122 supports up to four transmit DMA queues. The descriptors 60 * in the transmit ring can address up to 7 data fragments; frames which 61 * span more than 7 data buffers must be coalesced, but in general the 62 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 63 * long. The receive descriptors address only a single buffer. 64 * 65 * There are two peculiar design issues with the VT6122. One is that 66 * receive data buffers must be aligned on a 32-bit boundary. This is 67 * not a problem where the VT6122 is used as a LOM device in x86-based 68 * systems, but on architectures that generate unaligned access traps, we 69 * have to do some copying. 70 * 71 * The other issue has to do with the way 64-bit addresses are handled. 72 * The DMA descriptors only allow you to specify 48 bits of addressing 73 * information. The remaining 16 bits are specified using one of the 74 * I/O registers. If you only have a 32-bit system, then this isn't 75 * an issue, but if you have a 64-bit system and more than 4GB of 76 * memory, you must have to make sure your network data buffers reside 77 * in the same 48-bit 'segment.' 78 * 79 * Special thanks to Ryan Fu at VIA Networking for providing documentation 80 * and sample NICs for testing. 81 */ 82 83#ifdef HAVE_KERNEL_OPTION_HEADERS 84#include "opt_device_polling.h" 85#endif 86 87#include <sys/param.h> 88#include <sys/endian.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/module.h> 94#include <sys/kernel.h> 95#include <sys/socket.h> 96 97#include <net/if.h> 98#include <net/if_arp.h> 99#include <net/ethernet.h> 100#include <net/if_dl.h> 101#include <net/if_media.h> 102#include <net/if_types.h> 103#include <net/if_vlan_var.h> 104 105#include <net/bpf.h> 106 107#include <machine/bus.h> 108#include <machine/resource.h> 109#include <sys/bus.h> 110#include <sys/rman.h> 111 112#include <dev/mii/mii.h> 113#include <dev/mii/miivar.h> 114 115#include <dev/pci/pcireg.h> 116#include <dev/pci/pcivar.h> 117 118MODULE_DEPEND(vge, pci, 1, 1, 1); 119MODULE_DEPEND(vge, ether, 1, 1, 1); 120MODULE_DEPEND(vge, miibus, 1, 1, 1); 121 122/* "device miibus" required. See GENERIC if you get errors here. */ 123#include "miibus_if.h" 124 125#include <dev/vge/if_vgereg.h> 126#include <dev/vge/if_vgevar.h> 127 128#define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 129 130/* Tunables */ 131static int msi_disable = 0; 132TUNABLE_INT("hw.vge.msi_disable", &msi_disable); 133 134/* 135 * Various supported device vendors/types and their names. 136 */ 137static struct vge_type vge_devs[] = { 138 { VIA_VENDORID, VIA_DEVICEID_61XX, 139 "VIA Networking Gigabit Ethernet" }, 140 { 0, 0, NULL } 141}; 142 143static int vge_attach(device_t); 144static int vge_detach(device_t); 145static int vge_probe(device_t); 146static int vge_resume(device_t); 147static int vge_shutdown(device_t); 148static int vge_suspend(device_t); 149 150static void vge_cam_clear(struct vge_softc *); 151static int vge_cam_set(struct vge_softc *, uint8_t *); 152static void vge_discard_rxbuf(struct vge_softc *, int); 153static int vge_dma_alloc(struct vge_softc *); 154static void vge_dma_free(struct vge_softc *); 155static void vge_dmamap_cb(void *, bus_dma_segment_t *, int, int); 156#ifdef VGE_EEPROM 157static void vge_eeprom_getword(struct vge_softc *, int, uint16_t *); 158#endif 159static int vge_encap(struct vge_softc *, struct mbuf **); 160#ifndef __NO_STRICT_ALIGNMENT 161static __inline void 162 vge_fixup_rx(struct mbuf *); 163#endif 164static void vge_freebufs(struct vge_softc *); 165static void vge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 166static int vge_ifmedia_upd(struct ifnet *); 167static void vge_init(void *); 168static void vge_init_locked(struct vge_softc *); 169static void vge_intr(void *); 170static int vge_ioctl(struct ifnet *, u_long, caddr_t); 171static int vge_miibus_readreg(device_t, int, int); 172static void vge_miibus_statchg(device_t); 173static int vge_miibus_writereg(device_t, int, int, int); 174static void vge_miipoll_start(struct vge_softc *); 175static void vge_miipoll_stop(struct vge_softc *); 176static int vge_newbuf(struct vge_softc *, int); 177static void vge_read_eeprom(struct vge_softc *, caddr_t, int, int, int); 178static void vge_reset(struct vge_softc *); 179static int vge_rx_list_init(struct vge_softc *); 180static int vge_rxeof(struct vge_softc *, int); 181static void vge_setmulti(struct vge_softc *); 182static void vge_start(struct ifnet *); 183static void vge_start_locked(struct ifnet *); 184static void vge_stop(struct vge_softc *); 185static void vge_tick(void *); 186static int vge_tx_list_init(struct vge_softc *); 187static void vge_txeof(struct vge_softc *); 188static void vge_watchdog(void *); 189 190static device_method_t vge_methods[] = { 191 /* Device interface */ 192 DEVMETHOD(device_probe, vge_probe), 193 DEVMETHOD(device_attach, vge_attach), 194 DEVMETHOD(device_detach, vge_detach), 195 DEVMETHOD(device_suspend, vge_suspend), 196 DEVMETHOD(device_resume, vge_resume), 197 DEVMETHOD(device_shutdown, vge_shutdown), 198 199 /* bus interface */ 200 DEVMETHOD(bus_print_child, bus_generic_print_child), 201 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 202 203 /* MII interface */ 204 DEVMETHOD(miibus_readreg, vge_miibus_readreg), 205 DEVMETHOD(miibus_writereg, vge_miibus_writereg), 206 DEVMETHOD(miibus_statchg, vge_miibus_statchg), 207 208 { 0, 0 } 209}; 210 211static driver_t vge_driver = { 212 "vge", 213 vge_methods, 214 sizeof(struct vge_softc) 215}; 216 217static devclass_t vge_devclass; 218 219DRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0); 220DRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0); 221 222#ifdef VGE_EEPROM 223/* 224 * Read a word of data stored in the EEPROM at address 'addr.' 225 */ 226static void 227vge_eeprom_getword(struct vge_softc *sc, int addr, uint16_t *dest) 228{ 229 int i; 230 uint16_t word = 0; 231 232 /* 233 * Enter EEPROM embedded programming mode. In order to 234 * access the EEPROM at all, we first have to set the 235 * EELOAD bit in the CHIPCFG2 register. 236 */ 237 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 238 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 239 240 /* Select the address of the word we want to read */ 241 CSR_WRITE_1(sc, VGE_EEADDR, addr); 242 243 /* Issue read command */ 244 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 245 246 /* Wait for the done bit to be set. */ 247 for (i = 0; i < VGE_TIMEOUT; i++) { 248 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 249 break; 250 } 251 252 if (i == VGE_TIMEOUT) { 253 device_printf(sc->vge_dev, "EEPROM read timed out\n"); 254 *dest = 0; 255 return; 256 } 257 258 /* Read the result */ 259 word = CSR_READ_2(sc, VGE_EERDDAT); 260 261 /* Turn off EEPROM access mode. */ 262 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 263 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 264 265 *dest = word; 266} 267#endif 268 269/* 270 * Read a sequence of words from the EEPROM. 271 */ 272static void 273vge_read_eeprom(struct vge_softc *sc, caddr_t dest, int off, int cnt, int swap) 274{ 275 int i; 276#ifdef VGE_EEPROM 277 uint16_t word = 0, *ptr; 278 279 for (i = 0; i < cnt; i++) { 280 vge_eeprom_getword(sc, off + i, &word); 281 ptr = (uint16_t *)(dest + (i * 2)); 282 if (swap) 283 *ptr = ntohs(word); 284 else 285 *ptr = word; 286 } 287#else 288 for (i = 0; i < ETHER_ADDR_LEN; i++) 289 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 290#endif 291} 292 293static void 294vge_miipoll_stop(struct vge_softc *sc) 295{ 296 int i; 297 298 CSR_WRITE_1(sc, VGE_MIICMD, 0); 299 300 for (i = 0; i < VGE_TIMEOUT; i++) { 301 DELAY(1); 302 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 303 break; 304 } 305 306 if (i == VGE_TIMEOUT) 307 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 308} 309 310static void 311vge_miipoll_start(struct vge_softc *sc) 312{ 313 int i; 314 315 /* First, make sure we're idle. */ 316 317 CSR_WRITE_1(sc, VGE_MIICMD, 0); 318 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 319 320 for (i = 0; i < VGE_TIMEOUT; i++) { 321 DELAY(1); 322 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 323 break; 324 } 325 326 if (i == VGE_TIMEOUT) { 327 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 328 return; 329 } 330 331 /* Now enable auto poll mode. */ 332 333 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 334 335 /* And make sure it started. */ 336 337 for (i = 0; i < VGE_TIMEOUT; i++) { 338 DELAY(1); 339 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 340 break; 341 } 342 343 if (i == VGE_TIMEOUT) 344 device_printf(sc->vge_dev, "failed to start MII autopoll\n"); 345} 346 347static int 348vge_miibus_readreg(device_t dev, int phy, int reg) 349{ 350 struct vge_softc *sc; 351 int i; 352 uint16_t rval = 0; 353 354 sc = device_get_softc(dev); 355 356 if (phy != sc->vge_phyaddr) 357 return (0); 358 359 vge_miipoll_stop(sc); 360 361 /* Specify the register we want to read. */ 362 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 363 364 /* Issue read command. */ 365 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 366 367 /* Wait for the read command bit to self-clear. */ 368 for (i = 0; i < VGE_TIMEOUT; i++) { 369 DELAY(1); 370 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 371 break; 372 } 373 374 if (i == VGE_TIMEOUT) 375 device_printf(sc->vge_dev, "MII read timed out\n"); 376 else 377 rval = CSR_READ_2(sc, VGE_MIIDATA); 378 379 vge_miipoll_start(sc); 380 381 return (rval); 382} 383 384static int 385vge_miibus_writereg(device_t dev, int phy, int reg, int data) 386{ 387 struct vge_softc *sc; 388 int i, rval = 0; 389 390 sc = device_get_softc(dev); 391 392 if (phy != sc->vge_phyaddr) 393 return (0); 394 395 vge_miipoll_stop(sc); 396 397 /* Specify the register we want to write. */ 398 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 399 400 /* Specify the data we want to write. */ 401 CSR_WRITE_2(sc, VGE_MIIDATA, data); 402 403 /* Issue write command. */ 404 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 405 406 /* Wait for the write command bit to self-clear. */ 407 for (i = 0; i < VGE_TIMEOUT; i++) { 408 DELAY(1); 409 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 410 break; 411 } 412 413 if (i == VGE_TIMEOUT) { 414 device_printf(sc->vge_dev, "MII write timed out\n"); 415 rval = EIO; 416 } 417 418 vge_miipoll_start(sc); 419 420 return (rval); 421} 422 423static void 424vge_cam_clear(struct vge_softc *sc) 425{ 426 int i; 427 428 /* 429 * Turn off all the mask bits. This tells the chip 430 * that none of the entries in the CAM filter are valid. 431 * desired entries will be enabled as we fill the filter in. 432 */ 433 434 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 435 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 436 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 437 for (i = 0; i < 8; i++) 438 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 439 440 /* Clear the VLAN filter too. */ 441 442 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 443 for (i = 0; i < 8; i++) 444 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 445 446 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 447 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 448 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 449 450 sc->vge_camidx = 0; 451} 452 453static int 454vge_cam_set(struct vge_softc *sc, uint8_t *addr) 455{ 456 int i, error = 0; 457 458 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 459 return (ENOSPC); 460 461 /* Select the CAM data page. */ 462 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 463 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 464 465 /* Set the filter entry we want to update and enable writing. */ 466 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 467 468 /* Write the address to the CAM registers */ 469 for (i = 0; i < ETHER_ADDR_LEN; i++) 470 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 471 472 /* Issue a write command. */ 473 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 474 475 /* Wake for it to clear. */ 476 for (i = 0; i < VGE_TIMEOUT; i++) { 477 DELAY(1); 478 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 479 break; 480 } 481 482 if (i == VGE_TIMEOUT) { 483 device_printf(sc->vge_dev, "setting CAM filter failed\n"); 484 error = EIO; 485 goto fail; 486 } 487 488 /* Select the CAM mask page. */ 489 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 490 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 491 492 /* Set the mask bit that enables this filter. */ 493 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 494 1<<(sc->vge_camidx & 7)); 495 496 sc->vge_camidx++; 497 498fail: 499 /* Turn off access to CAM. */ 500 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 501 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 502 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 503 504 return (error); 505} 506 507/* 508 * Program the multicast filter. We use the 64-entry CAM filter 509 * for perfect filtering. If there's more than 64 multicast addresses, 510 * we use the hash filter instead. 511 */ 512static void 513vge_setmulti(struct vge_softc *sc) 514{ 515 struct ifnet *ifp; 516 int error = 0/*, h = 0*/; 517 struct ifmultiaddr *ifma; 518 uint32_t h, hashes[2] = { 0, 0 }; 519 520 VGE_LOCK_ASSERT(sc); 521 522 ifp = sc->vge_ifp; 523 524 /* First, zot all the multicast entries. */ 525 vge_cam_clear(sc); 526 CSR_WRITE_4(sc, VGE_MAR0, 0); 527 CSR_WRITE_4(sc, VGE_MAR1, 0); 528 529 /* 530 * If the user wants allmulti or promisc mode, enable reception 531 * of all multicast frames. 532 */ 533 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 534 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 535 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 536 return; 537 } 538 539 /* Now program new ones */ 540 if_maddr_rlock(ifp); 541 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 542 if (ifma->ifma_addr->sa_family != AF_LINK) 543 continue; 544 error = vge_cam_set(sc, 545 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 546 if (error) 547 break; 548 } 549 550 /* If there were too many addresses, use the hash filter. */ 551 if (error) { 552 vge_cam_clear(sc); 553 554 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 555 if (ifma->ifma_addr->sa_family != AF_LINK) 556 continue; 557 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 558 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 559 if (h < 32) 560 hashes[0] |= (1 << h); 561 else 562 hashes[1] |= (1 << (h - 32)); 563 } 564 565 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 566 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 567 } 568 if_maddr_runlock(ifp); 569} 570 571static void 572vge_reset(struct vge_softc *sc) 573{ 574 int i; 575 576 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 577 578 for (i = 0; i < VGE_TIMEOUT; i++) { 579 DELAY(5); 580 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 581 break; 582 } 583 584 if (i == VGE_TIMEOUT) { 585 device_printf(sc->vge_dev, "soft reset timed out\n"); 586 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 587 DELAY(2000); 588 } 589 590 DELAY(5000); 591} 592 593/* 594 * Probe for a VIA gigabit chip. Check the PCI vendor and device 595 * IDs against our list and return a device name if we find a match. 596 */ 597static int 598vge_probe(device_t dev) 599{ 600 struct vge_type *t; 601 602 t = vge_devs; 603 604 while (t->vge_name != NULL) { 605 if ((pci_get_vendor(dev) == t->vge_vid) && 606 (pci_get_device(dev) == t->vge_did)) { 607 device_set_desc(dev, t->vge_name); 608 return (BUS_PROBE_DEFAULT); 609 } 610 t++; 611 } 612 613 return (ENXIO); 614} 615 616/* 617 * Map a single buffer address. 618 */ 619 620struct vge_dmamap_arg { 621 bus_addr_t vge_busaddr; 622}; 623 624static void 625vge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 626{ 627 struct vge_dmamap_arg *ctx; 628 629 if (error != 0) 630 return; 631 632 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 633 634 ctx = (struct vge_dmamap_arg *)arg; 635 ctx->vge_busaddr = segs[0].ds_addr; 636} 637 638static int 639vge_dma_alloc(struct vge_softc *sc) 640{ 641 struct vge_dmamap_arg ctx; 642 struct vge_txdesc *txd; 643 struct vge_rxdesc *rxd; 644 bus_addr_t lowaddr, tx_ring_end, rx_ring_end; 645 int error, i; 646 647 lowaddr = BUS_SPACE_MAXADDR; 648 649again: 650 /* Create parent ring tag. */ 651 error = bus_dma_tag_create(bus_get_dma_tag(sc->vge_dev),/* parent */ 652 1, 0, /* algnmnt, boundary */ 653 lowaddr, /* lowaddr */ 654 BUS_SPACE_MAXADDR, /* highaddr */ 655 NULL, NULL, /* filter, filterarg */ 656 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 657 0, /* nsegments */ 658 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 659 0, /* flags */ 660 NULL, NULL, /* lockfunc, lockarg */ 661 &sc->vge_cdata.vge_ring_tag); 662 if (error != 0) { 663 device_printf(sc->vge_dev, 664 "could not create parent DMA tag.\n"); 665 goto fail; 666 } 667 668 /* Create tag for Tx ring. */ 669 error = bus_dma_tag_create(sc->vge_cdata.vge_ring_tag,/* parent */ 670 VGE_TX_RING_ALIGN, 0, /* algnmnt, boundary */ 671 BUS_SPACE_MAXADDR, /* lowaddr */ 672 BUS_SPACE_MAXADDR, /* highaddr */ 673 NULL, NULL, /* filter, filterarg */ 674 VGE_TX_LIST_SZ, /* maxsize */ 675 1, /* nsegments */ 676 VGE_TX_LIST_SZ, /* maxsegsize */ 677 0, /* flags */ 678 NULL, NULL, /* lockfunc, lockarg */ 679 &sc->vge_cdata.vge_tx_ring_tag); 680 if (error != 0) { 681 device_printf(sc->vge_dev, 682 "could not allocate Tx ring DMA tag.\n"); 683 goto fail; 684 } 685 686 /* Create tag for Rx ring. */ 687 error = bus_dma_tag_create(sc->vge_cdata.vge_ring_tag,/* parent */ 688 VGE_RX_RING_ALIGN, 0, /* algnmnt, boundary */ 689 BUS_SPACE_MAXADDR, /* lowaddr */ 690 BUS_SPACE_MAXADDR, /* highaddr */ 691 NULL, NULL, /* filter, filterarg */ 692 VGE_RX_LIST_SZ, /* maxsize */ 693 1, /* nsegments */ 694 VGE_RX_LIST_SZ, /* maxsegsize */ 695 0, /* flags */ 696 NULL, NULL, /* lockfunc, lockarg */ 697 &sc->vge_cdata.vge_rx_ring_tag); 698 if (error != 0) { 699 device_printf(sc->vge_dev, 700 "could not allocate Rx ring DMA tag.\n"); 701 goto fail; 702 } 703 704 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 705 error = bus_dmamem_alloc(sc->vge_cdata.vge_tx_ring_tag, 706 (void **)&sc->vge_rdata.vge_tx_ring, 707 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 708 &sc->vge_cdata.vge_tx_ring_map); 709 if (error != 0) { 710 device_printf(sc->vge_dev, 711 "could not allocate DMA'able memory for Tx ring.\n"); 712 goto fail; 713 } 714 715 ctx.vge_busaddr = 0; 716 error = bus_dmamap_load(sc->vge_cdata.vge_tx_ring_tag, 717 sc->vge_cdata.vge_tx_ring_map, sc->vge_rdata.vge_tx_ring, 718 VGE_TX_LIST_SZ, vge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 719 if (error != 0 || ctx.vge_busaddr == 0) { 720 device_printf(sc->vge_dev, 721 "could not load DMA'able memory for Tx ring.\n"); 722 goto fail; 723 } 724 sc->vge_rdata.vge_tx_ring_paddr = ctx.vge_busaddr; 725 726 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 727 error = bus_dmamem_alloc(sc->vge_cdata.vge_rx_ring_tag, 728 (void **)&sc->vge_rdata.vge_rx_ring, 729 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 730 &sc->vge_cdata.vge_rx_ring_map); 731 if (error != 0) { 732 device_printf(sc->vge_dev, 733 "could not allocate DMA'able memory for Rx ring.\n"); 734 goto fail; 735 } 736 737 ctx.vge_busaddr = 0; 738 error = bus_dmamap_load(sc->vge_cdata.vge_rx_ring_tag, 739 sc->vge_cdata.vge_rx_ring_map, sc->vge_rdata.vge_rx_ring, 740 VGE_RX_LIST_SZ, vge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 741 if (error != 0 || ctx.vge_busaddr == 0) { 742 device_printf(sc->vge_dev, 743 "could not load DMA'able memory for Rx ring.\n"); 744 goto fail; 745 } 746 sc->vge_rdata.vge_rx_ring_paddr = ctx.vge_busaddr; 747 748 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 749 tx_ring_end = sc->vge_rdata.vge_tx_ring_paddr + VGE_TX_LIST_SZ; 750 rx_ring_end = sc->vge_rdata.vge_rx_ring_paddr + VGE_RX_LIST_SZ; 751 if ((VGE_ADDR_HI(tx_ring_end) != 752 VGE_ADDR_HI(sc->vge_rdata.vge_tx_ring_paddr)) || 753 (VGE_ADDR_HI(rx_ring_end) != 754 VGE_ADDR_HI(sc->vge_rdata.vge_rx_ring_paddr)) || 755 VGE_ADDR_HI(tx_ring_end) != VGE_ADDR_HI(rx_ring_end)) { 756 device_printf(sc->vge_dev, "4GB boundary crossed, " 757 "switching to 32bit DMA address mode.\n"); 758 vge_dma_free(sc); 759 /* Limit DMA address space to 32bit and try again. */ 760 lowaddr = BUS_SPACE_MAXADDR_32BIT; 761 goto again; 762 } 763 764 /* Create parent buffer tag. */ 765 error = bus_dma_tag_create(bus_get_dma_tag(sc->vge_dev),/* parent */ 766 1, 0, /* algnmnt, boundary */ 767 VGE_BUF_DMA_MAXADDR, /* lowaddr */ 768 BUS_SPACE_MAXADDR, /* highaddr */ 769 NULL, NULL, /* filter, filterarg */ 770 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 771 0, /* nsegments */ 772 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 773 0, /* flags */ 774 NULL, NULL, /* lockfunc, lockarg */ 775 &sc->vge_cdata.vge_buffer_tag); 776 if (error != 0) { 777 device_printf(sc->vge_dev, 778 "could not create parent buffer DMA tag.\n"); 779 goto fail; 780 } 781 782 /* Create tag for Tx buffers. */ 783 error = bus_dma_tag_create(sc->vge_cdata.vge_buffer_tag,/* parent */ 784 1, 0, /* algnmnt, boundary */ 785 BUS_SPACE_MAXADDR, /* lowaddr */ 786 BUS_SPACE_MAXADDR, /* highaddr */ 787 NULL, NULL, /* filter, filterarg */ 788 MCLBYTES * VGE_MAXTXSEGS, /* maxsize */ 789 VGE_MAXTXSEGS, /* nsegments */ 790 MCLBYTES, /* maxsegsize */ 791 0, /* flags */ 792 NULL, NULL, /* lockfunc, lockarg */ 793 &sc->vge_cdata.vge_tx_tag); 794 if (error != 0) { 795 device_printf(sc->vge_dev, "could not create Tx DMA tag.\n"); 796 goto fail; 797 } 798 799 /* Create tag for Rx buffers. */ 800 error = bus_dma_tag_create(sc->vge_cdata.vge_buffer_tag,/* parent */ 801 VGE_RX_BUF_ALIGN, 0, /* algnmnt, boundary */ 802 BUS_SPACE_MAXADDR, /* lowaddr */ 803 BUS_SPACE_MAXADDR, /* highaddr */ 804 NULL, NULL, /* filter, filterarg */ 805 MCLBYTES, /* maxsize */ 806 1, /* nsegments */ 807 MCLBYTES, /* maxsegsize */ 808 0, /* flags */ 809 NULL, NULL, /* lockfunc, lockarg */ 810 &sc->vge_cdata.vge_rx_tag); 811 if (error != 0) { 812 device_printf(sc->vge_dev, "could not create Rx DMA tag.\n"); 813 goto fail; 814 } 815 816 /* Create DMA maps for Tx buffers. */ 817 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 818 txd = &sc->vge_cdata.vge_txdesc[i]; 819 txd->tx_m = NULL; 820 txd->tx_dmamap = NULL; 821 error = bus_dmamap_create(sc->vge_cdata.vge_tx_tag, 0, 822 &txd->tx_dmamap); 823 if (error != 0) { 824 device_printf(sc->vge_dev, 825 "could not create Tx dmamap.\n"); 826 goto fail; 827 } 828 } 829 /* Create DMA maps for Rx buffers. */ 830 if ((error = bus_dmamap_create(sc->vge_cdata.vge_rx_tag, 0, 831 &sc->vge_cdata.vge_rx_sparemap)) != 0) { 832 device_printf(sc->vge_dev, 833 "could not create spare Rx dmamap.\n"); 834 goto fail; 835 } 836 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 837 rxd = &sc->vge_cdata.vge_rxdesc[i]; 838 rxd->rx_m = NULL; 839 rxd->rx_dmamap = NULL; 840 error = bus_dmamap_create(sc->vge_cdata.vge_rx_tag, 0, 841 &rxd->rx_dmamap); 842 if (error != 0) { 843 device_printf(sc->vge_dev, 844 "could not create Rx dmamap.\n"); 845 goto fail; 846 } 847 } 848 849fail: 850 return (error); 851} 852 853static void 854vge_dma_free(struct vge_softc *sc) 855{ 856 struct vge_txdesc *txd; 857 struct vge_rxdesc *rxd; 858 int i; 859 860 /* Tx ring. */ 861 if (sc->vge_cdata.vge_tx_ring_tag != NULL) { 862 if (sc->vge_cdata.vge_tx_ring_map) 863 bus_dmamap_unload(sc->vge_cdata.vge_tx_ring_tag, 864 sc->vge_cdata.vge_tx_ring_map); 865 if (sc->vge_cdata.vge_tx_ring_map && 866 sc->vge_rdata.vge_tx_ring) 867 bus_dmamem_free(sc->vge_cdata.vge_tx_ring_tag, 868 sc->vge_rdata.vge_tx_ring, 869 sc->vge_cdata.vge_tx_ring_map); 870 sc->vge_rdata.vge_tx_ring = NULL; 871 sc->vge_cdata.vge_tx_ring_map = NULL; 872 bus_dma_tag_destroy(sc->vge_cdata.vge_tx_ring_tag); 873 sc->vge_cdata.vge_tx_ring_tag = NULL; 874 } 875 /* Rx ring. */ 876 if (sc->vge_cdata.vge_rx_ring_tag != NULL) { 877 if (sc->vge_cdata.vge_rx_ring_map) 878 bus_dmamap_unload(sc->vge_cdata.vge_rx_ring_tag, 879 sc->vge_cdata.vge_rx_ring_map); 880 if (sc->vge_cdata.vge_rx_ring_map && 881 sc->vge_rdata.vge_rx_ring) 882 bus_dmamem_free(sc->vge_cdata.vge_rx_ring_tag, 883 sc->vge_rdata.vge_rx_ring, 884 sc->vge_cdata.vge_rx_ring_map); 885 sc->vge_rdata.vge_rx_ring = NULL; 886 sc->vge_cdata.vge_rx_ring_map = NULL; 887 bus_dma_tag_destroy(sc->vge_cdata.vge_rx_ring_tag); 888 sc->vge_cdata.vge_rx_ring_tag = NULL; 889 } 890 /* Tx buffers. */ 891 if (sc->vge_cdata.vge_tx_tag != NULL) { 892 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 893 txd = &sc->vge_cdata.vge_txdesc[i]; 894 if (txd->tx_dmamap != NULL) { 895 bus_dmamap_destroy(sc->vge_cdata.vge_tx_tag, 896 txd->tx_dmamap); 897 txd->tx_dmamap = NULL; 898 } 899 } 900 bus_dma_tag_destroy(sc->vge_cdata.vge_tx_tag); 901 sc->vge_cdata.vge_tx_tag = NULL; 902 } 903 /* Rx buffers. */ 904 if (sc->vge_cdata.vge_rx_tag != NULL) { 905 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 906 rxd = &sc->vge_cdata.vge_rxdesc[i]; 907 if (rxd->rx_dmamap != NULL) { 908 bus_dmamap_destroy(sc->vge_cdata.vge_rx_tag, 909 rxd->rx_dmamap); 910 rxd->rx_dmamap = NULL; 911 } 912 } 913 if (sc->vge_cdata.vge_rx_sparemap != NULL) { 914 bus_dmamap_destroy(sc->vge_cdata.vge_rx_tag, 915 sc->vge_cdata.vge_rx_sparemap); 916 sc->vge_cdata.vge_rx_sparemap = NULL; 917 } 918 bus_dma_tag_destroy(sc->vge_cdata.vge_rx_tag); 919 sc->vge_cdata.vge_rx_tag = NULL; 920 } 921 922 if (sc->vge_cdata.vge_buffer_tag != NULL) { 923 bus_dma_tag_destroy(sc->vge_cdata.vge_buffer_tag); 924 sc->vge_cdata.vge_buffer_tag = NULL; 925 } 926 if (sc->vge_cdata.vge_ring_tag != NULL) { 927 bus_dma_tag_destroy(sc->vge_cdata.vge_ring_tag); 928 sc->vge_cdata.vge_ring_tag = NULL; 929 } 930} 931 932/* 933 * Attach the interface. Allocate softc structures, do ifmedia 934 * setup and ethernet/BPF attach. 935 */ 936static int 937vge_attach(device_t dev) 938{ 939 u_char eaddr[ETHER_ADDR_LEN]; 940 struct vge_softc *sc; 941 struct ifnet *ifp; 942 int error = 0, cap, i, msic, rid; 943 944 sc = device_get_softc(dev); 945 sc->vge_dev = dev; 946 947 mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 948 MTX_DEF); 949 callout_init_mtx(&sc->vge_watchdog, &sc->vge_mtx, 0); 950 951 /* 952 * Map control/status registers. 953 */ 954 pci_enable_busmaster(dev); 955 956 rid = PCIR_BAR(1); 957 sc->vge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 958 RF_ACTIVE); 959 960 if (sc->vge_res == NULL) { 961 device_printf(dev, "couldn't map ports/memory\n"); 962 error = ENXIO; 963 goto fail; 964 } 965 966 if (pci_find_extcap(dev, PCIY_EXPRESS, &cap) == 0) { 967 sc->vge_flags |= VGE_FLAG_PCIE; 968 sc->vge_expcap = cap; 969 } 970 rid = 0; 971 msic = pci_msi_count(dev); 972 if (msi_disable == 0 && msic > 0) { 973 msic = 1; 974 if (pci_alloc_msi(dev, &msic) == 0) { 975 if (msic == 1) { 976 sc->vge_flags |= VGE_FLAG_MSI; 977 device_printf(dev, "Using %d MSI message\n", 978 msic); 979 rid = 1; 980 } else 981 pci_release_msi(dev); 982 } 983 } 984 985 /* Allocate interrupt */ 986 sc->vge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 987 ((sc->vge_flags & VGE_FLAG_MSI) ? 0 : RF_SHAREABLE) | RF_ACTIVE); 988 if (sc->vge_irq == NULL) { 989 device_printf(dev, "couldn't map interrupt\n"); 990 error = ENXIO; 991 goto fail; 992 } 993 994 /* Reset the adapter. */ 995 vge_reset(sc); 996 /* Reload EEPROM. */ 997 CSR_WRITE_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 998 for (i = 0; i < VGE_TIMEOUT; i++) { 999 DELAY(5); 1000 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 1001 break; 1002 } 1003 if (i == VGE_TIMEOUT) 1004 device_printf(dev, "EEPROM reload timed out\n"); 1005 /* 1006 * Clear PACPI as EEPROM reload will set the bit. Otherwise 1007 * MAC will receive magic packet which in turn confuses 1008 * controller. 1009 */ 1010 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 1011 1012 /* 1013 * Get station address from the EEPROM. 1014 */ 1015 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 1016 /* 1017 * Save configured PHY address. 1018 * It seems the PHY address of PCIe controllers just 1019 * reflects media jump strapping status so we assume the 1020 * internal PHY address of PCIe controller is at 1. 1021 */ 1022 if ((sc->vge_flags & VGE_FLAG_PCIE) != 0) 1023 sc->vge_phyaddr = 1; 1024 else 1025 sc->vge_phyaddr = CSR_READ_1(sc, VGE_MIICFG) & 1026 VGE_MIICFG_PHYADDR; 1027 error = vge_dma_alloc(sc); 1028 if (error) 1029 goto fail; 1030 1031 ifp = sc->vge_ifp = if_alloc(IFT_ETHER); 1032 if (ifp == NULL) { 1033 device_printf(dev, "can not if_alloc()\n"); 1034 error = ENOSPC; 1035 goto fail; 1036 } 1037 1038 /* Do MII setup */ 1039 if (mii_phy_probe(dev, &sc->vge_miibus, 1040 vge_ifmedia_upd, vge_ifmedia_sts)) { 1041 device_printf(dev, "MII without any phy!\n"); 1042 error = ENXIO; 1043 goto fail; 1044 } 1045 1046 ifp->if_softc = sc; 1047 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1048 ifp->if_mtu = ETHERMTU; 1049 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1050 ifp->if_ioctl = vge_ioctl; 1051 ifp->if_capabilities = IFCAP_VLAN_MTU; 1052 ifp->if_start = vge_start; 1053 ifp->if_hwassist = VGE_CSUM_FEATURES; 1054 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1055 ifp->if_capenable = ifp->if_capabilities; 1056#ifdef DEVICE_POLLING 1057 ifp->if_capabilities |= IFCAP_POLLING; 1058#endif 1059 ifp->if_init = vge_init; 1060 IFQ_SET_MAXLEN(&ifp->if_snd, VGE_TX_DESC_CNT - 1); 1061 ifp->if_snd.ifq_drv_maxlen = VGE_TX_DESC_CNT - 1; 1062 IFQ_SET_READY(&ifp->if_snd); 1063 1064 /* 1065 * Call MI attach routine. 1066 */ 1067 ether_ifattach(ifp, eaddr); 1068 1069 /* Hook interrupt last to avoid having to lock softc */ 1070 error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE, 1071 NULL, vge_intr, sc, &sc->vge_intrhand); 1072 1073 if (error) { 1074 device_printf(dev, "couldn't set up irq\n"); 1075 ether_ifdetach(ifp); 1076 goto fail; 1077 } 1078 1079fail: 1080 if (error) 1081 vge_detach(dev); 1082 1083 return (error); 1084} 1085 1086/* 1087 * Shutdown hardware and free up resources. This can be called any 1088 * time after the mutex has been initialized. It is called in both 1089 * the error case in attach and the normal detach case so it needs 1090 * to be careful about only freeing resources that have actually been 1091 * allocated. 1092 */ 1093static int 1094vge_detach(device_t dev) 1095{ 1096 struct vge_softc *sc; 1097 struct ifnet *ifp; 1098 1099 sc = device_get_softc(dev); 1100 KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized")); 1101 ifp = sc->vge_ifp; 1102 1103#ifdef DEVICE_POLLING 1104 if (ifp->if_capenable & IFCAP_POLLING) 1105 ether_poll_deregister(ifp); 1106#endif 1107 1108 /* These should only be active if attach succeeded */ 1109 if (device_is_attached(dev)) { 1110 ether_ifdetach(ifp); 1111 VGE_LOCK(sc); 1112 vge_stop(sc); 1113 VGE_UNLOCK(sc); 1114 callout_drain(&sc->vge_watchdog); 1115 } 1116 if (sc->vge_miibus) 1117 device_delete_child(dev, sc->vge_miibus); 1118 bus_generic_detach(dev); 1119 1120 if (sc->vge_intrhand) 1121 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); 1122 if (sc->vge_irq) 1123 bus_release_resource(dev, SYS_RES_IRQ, 1124 sc->vge_flags & VGE_FLAG_MSI ? 1 : 0, sc->vge_irq); 1125 if (sc->vge_flags & VGE_FLAG_MSI) 1126 pci_release_msi(dev); 1127 if (sc->vge_res) 1128 bus_release_resource(dev, SYS_RES_MEMORY, 1129 PCIR_BAR(1), sc->vge_res); 1130 if (ifp) 1131 if_free(ifp); 1132 1133 vge_dma_free(sc); 1134 mtx_destroy(&sc->vge_mtx); 1135 1136 return (0); 1137} 1138 1139static void 1140vge_discard_rxbuf(struct vge_softc *sc, int prod) 1141{ 1142 struct vge_rxdesc *rxd; 1143 int i; 1144 1145 rxd = &sc->vge_cdata.vge_rxdesc[prod]; 1146 rxd->rx_desc->vge_sts = 0; 1147 rxd->rx_desc->vge_ctl = 0; 1148 1149 /* 1150 * Note: the manual fails to document the fact that for 1151 * proper opration, the driver needs to replentish the RX 1152 * DMA ring 4 descriptors at a time (rather than one at a 1153 * time, like most chips). We can allocate the new buffers 1154 * but we should not set the OWN bits until we're ready 1155 * to hand back 4 of them in one shot. 1156 */ 1157 if ((prod % VGE_RXCHUNK) == (VGE_RXCHUNK - 1)) { 1158 for (i = VGE_RXCHUNK; i > 0; i--) { 1159 rxd->rx_desc->vge_sts = htole32(VGE_RDSTS_OWN); 1160 rxd = rxd->rxd_prev; 1161 } 1162 sc->vge_cdata.vge_rx_commit += VGE_RXCHUNK; 1163 } 1164} 1165 1166static int 1167vge_newbuf(struct vge_softc *sc, int prod) 1168{ 1169 struct vge_rxdesc *rxd; 1170 struct mbuf *m; 1171 bus_dma_segment_t segs[1]; 1172 bus_dmamap_t map; 1173 int i, nsegs; 1174 1175 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1176 if (m == NULL) 1177 return (ENOBUFS); 1178 /* 1179 * This is part of an evil trick to deal with strict-alignment 1180 * architectures. The VIA chip requires RX buffers to be aligned 1181 * on 32-bit boundaries, but that will hose strict-alignment 1182 * architectures. To get around this, we leave some empty space 1183 * at the start of each buffer and for non-strict-alignment hosts, 1184 * we copy the buffer back two bytes to achieve word alignment. 1185 * This is slightly more efficient than allocating a new buffer, 1186 * copying the contents, and discarding the old buffer. 1187 */ 1188 m->m_len = m->m_pkthdr.len = MCLBYTES; 1189 m_adj(m, VGE_RX_BUF_ALIGN); 1190 1191 if (bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_rx_tag, 1192 sc->vge_cdata.vge_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1193 m_freem(m); 1194 return (ENOBUFS); 1195 } 1196 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1197 1198 rxd = &sc->vge_cdata.vge_rxdesc[prod]; 1199 if (rxd->rx_m != NULL) { 1200 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap, 1201 BUS_DMASYNC_POSTREAD); 1202 bus_dmamap_unload(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap); 1203 } 1204 map = rxd->rx_dmamap; 1205 rxd->rx_dmamap = sc->vge_cdata.vge_rx_sparemap; 1206 sc->vge_cdata.vge_rx_sparemap = map; 1207 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap, 1208 BUS_DMASYNC_PREREAD); 1209 rxd->rx_m = m; 1210 1211 rxd->rx_desc->vge_sts = 0; 1212 rxd->rx_desc->vge_ctl = 0; 1213 rxd->rx_desc->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 1214 rxd->rx_desc->vge_addrhi = htole32(VGE_ADDR_HI(segs[0].ds_addr) | 1215 (VGE_BUFLEN(segs[0].ds_len) << 16) | VGE_RXDESC_I); 1216 1217 /* 1218 * Note: the manual fails to document the fact that for 1219 * proper operation, the driver needs to replenish the RX 1220 * DMA ring 4 descriptors at a time (rather than one at a 1221 * time, like most chips). We can allocate the new buffers 1222 * but we should not set the OWN bits until we're ready 1223 * to hand back 4 of them in one shot. 1224 */ 1225 if ((prod % VGE_RXCHUNK) == (VGE_RXCHUNK - 1)) { 1226 for (i = VGE_RXCHUNK; i > 0; i--) { 1227 rxd->rx_desc->vge_sts = htole32(VGE_RDSTS_OWN); 1228 rxd = rxd->rxd_prev; 1229 } 1230 sc->vge_cdata.vge_rx_commit += VGE_RXCHUNK; 1231 } 1232 1233 return (0); 1234} 1235 1236static int 1237vge_tx_list_init(struct vge_softc *sc) 1238{ 1239 struct vge_ring_data *rd; 1240 struct vge_txdesc *txd; 1241 int i; 1242 1243 VGE_LOCK_ASSERT(sc); 1244 1245 sc->vge_cdata.vge_tx_prodidx = 0; 1246 sc->vge_cdata.vge_tx_considx = 0; 1247 sc->vge_cdata.vge_tx_cnt = 0; 1248 1249 rd = &sc->vge_rdata; 1250 bzero(rd->vge_tx_ring, VGE_TX_LIST_SZ); 1251 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 1252 txd = &sc->vge_cdata.vge_txdesc[i]; 1253 txd->tx_m = NULL; 1254 txd->tx_desc = &rd->vge_tx_ring[i]; 1255 } 1256 1257 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1258 sc->vge_cdata.vge_tx_ring_map, 1259 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1260 1261 return (0); 1262} 1263 1264static int 1265vge_rx_list_init(struct vge_softc *sc) 1266{ 1267 struct vge_ring_data *rd; 1268 struct vge_rxdesc *rxd; 1269 int i; 1270 1271 VGE_LOCK_ASSERT(sc); 1272 1273 sc->vge_cdata.vge_rx_prodidx = 0; 1274 sc->vge_cdata.vge_head = NULL; 1275 sc->vge_cdata.vge_tail = NULL; 1276 sc->vge_cdata.vge_rx_commit = 0; 1277 1278 rd = &sc->vge_rdata; 1279 bzero(rd->vge_rx_ring, VGE_RX_LIST_SZ); 1280 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1281 rxd = &sc->vge_cdata.vge_rxdesc[i]; 1282 rxd->rx_m = NULL; 1283 rxd->rx_desc = &rd->vge_rx_ring[i]; 1284 if (i == 0) 1285 rxd->rxd_prev = 1286 &sc->vge_cdata.vge_rxdesc[VGE_RX_DESC_CNT - 1]; 1287 else 1288 rxd->rxd_prev = &sc->vge_cdata.vge_rxdesc[i - 1]; 1289 if (vge_newbuf(sc, i) != 0) 1290 return (ENOBUFS); 1291 } 1292 1293 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, 1294 sc->vge_cdata.vge_rx_ring_map, 1295 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1296 1297 sc->vge_cdata.vge_rx_commit = 0; 1298 1299 return (0); 1300} 1301 1302static void 1303vge_freebufs(struct vge_softc *sc) 1304{ 1305 struct vge_txdesc *txd; 1306 struct vge_rxdesc *rxd; 1307 struct ifnet *ifp; 1308 int i; 1309 1310 VGE_LOCK_ASSERT(sc); 1311 1312 ifp = sc->vge_ifp; 1313 /* 1314 * Free RX and TX mbufs still in the queues. 1315 */ 1316 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1317 rxd = &sc->vge_cdata.vge_rxdesc[i]; 1318 if (rxd->rx_m != NULL) { 1319 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, 1320 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 1321 bus_dmamap_unload(sc->vge_cdata.vge_rx_tag, 1322 rxd->rx_dmamap); 1323 m_freem(rxd->rx_m); 1324 rxd->rx_m = NULL; 1325 } 1326 } 1327 1328 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 1329 txd = &sc->vge_cdata.vge_txdesc[i]; 1330 if (txd->tx_m != NULL) { 1331 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, 1332 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1333 bus_dmamap_unload(sc->vge_cdata.vge_tx_tag, 1334 txd->tx_dmamap); 1335 m_freem(txd->tx_m); 1336 txd->tx_m = NULL; 1337 ifp->if_oerrors++; 1338 } 1339 } 1340} 1341 1342#ifndef __NO_STRICT_ALIGNMENT 1343static __inline void 1344vge_fixup_rx(struct mbuf *m) 1345{ 1346 int i; 1347 uint16_t *src, *dst; 1348 1349 src = mtod(m, uint16_t *); 1350 dst = src - 1; 1351 1352 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1353 *dst++ = *src++; 1354 1355 m->m_data -= ETHER_ALIGN; 1356} 1357#endif 1358 1359/* 1360 * RX handler. We support the reception of jumbo frames that have 1361 * been fragmented across multiple 2K mbuf cluster buffers. 1362 */ 1363static int 1364vge_rxeof(struct vge_softc *sc, int count) 1365{ 1366 struct mbuf *m; 1367 struct ifnet *ifp; 1368 int prod, prog, total_len; 1369 struct vge_rxdesc *rxd; 1370 struct vge_rx_desc *cur_rx; 1371 uint32_t rxstat, rxctl; 1372 1373 VGE_LOCK_ASSERT(sc); 1374 1375 ifp = sc->vge_ifp; 1376 1377 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, 1378 sc->vge_cdata.vge_rx_ring_map, 1379 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1380 1381 prod = sc->vge_cdata.vge_rx_prodidx; 1382 for (prog = 0; count > 0 && 1383 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 1384 VGE_RX_DESC_INC(prod)) { 1385 cur_rx = &sc->vge_rdata.vge_rx_ring[prod]; 1386 rxstat = le32toh(cur_rx->vge_sts); 1387 if ((rxstat & VGE_RDSTS_OWN) != 0) 1388 break; 1389 count--; 1390 prog++; 1391 rxctl = le32toh(cur_rx->vge_ctl); 1392 total_len = VGE_RXBYTES(rxstat); 1393 rxd = &sc->vge_cdata.vge_rxdesc[prod]; 1394 m = rxd->rx_m; 1395 1396 /* 1397 * If the 'start of frame' bit is set, this indicates 1398 * either the first fragment in a multi-fragment receive, 1399 * or an intermediate fragment. Either way, we want to 1400 * accumulate the buffers. 1401 */ 1402 if ((rxstat & VGE_RXPKT_SOF) != 0) { 1403 if (vge_newbuf(sc, prod) != 0) { 1404 ifp->if_iqdrops++; 1405 VGE_CHAIN_RESET(sc); 1406 vge_discard_rxbuf(sc, prod); 1407 continue; 1408 } 1409 m->m_len = MCLBYTES - VGE_RX_BUF_ALIGN; 1410 if (sc->vge_cdata.vge_head == NULL) { 1411 sc->vge_cdata.vge_head = m; 1412 sc->vge_cdata.vge_tail = m; 1413 } else { 1414 m->m_flags &= ~M_PKTHDR; 1415 sc->vge_cdata.vge_tail->m_next = m; 1416 sc->vge_cdata.vge_tail = m; 1417 } 1418 continue; 1419 } 1420 1421 /* 1422 * Bad/error frames will have the RXOK bit cleared. 1423 * However, there's one error case we want to allow: 1424 * if a VLAN tagged frame arrives and the chip can't 1425 * match it against the CAM filter, it considers this 1426 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1427 * We don't want to drop the frame though: our VLAN 1428 * filtering is done in software. 1429 * We also want to receive bad-checksummed frames and 1430 * and frames with bad-length. 1431 */ 1432 if ((rxstat & VGE_RDSTS_RXOK) == 0 && 1433 (rxstat & (VGE_RDSTS_VIDM | VGE_RDSTS_RLERR | 1434 VGE_RDSTS_CSUMERR)) == 0) { 1435 ifp->if_ierrors++; 1436 /* 1437 * If this is part of a multi-fragment packet, 1438 * discard all the pieces. 1439 */ 1440 VGE_CHAIN_RESET(sc); 1441 vge_discard_rxbuf(sc, prod); 1442 continue; 1443 } 1444 1445 if (vge_newbuf(sc, prod) != 0) { 1446 ifp->if_iqdrops++; 1447 VGE_CHAIN_RESET(sc); 1448 vge_discard_rxbuf(sc, prod); 1449 continue; 1450 } 1451 1452 /* Chain received mbufs. */ 1453 if (sc->vge_cdata.vge_head != NULL) { 1454 m->m_len = total_len % (MCLBYTES - VGE_RX_BUF_ALIGN); 1455 /* 1456 * Special case: if there's 4 bytes or less 1457 * in this buffer, the mbuf can be discarded: 1458 * the last 4 bytes is the CRC, which we don't 1459 * care about anyway. 1460 */ 1461 if (m->m_len <= ETHER_CRC_LEN) { 1462 sc->vge_cdata.vge_tail->m_len -= 1463 (ETHER_CRC_LEN - m->m_len); 1464 m_freem(m); 1465 } else { 1466 m->m_len -= ETHER_CRC_LEN; 1467 m->m_flags &= ~M_PKTHDR; 1468 sc->vge_cdata.vge_tail->m_next = m; 1469 } 1470 m = sc->vge_cdata.vge_head; 1471 m->m_flags |= M_PKTHDR; 1472 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1473 } else { 1474 m->m_flags |= M_PKTHDR; 1475 m->m_pkthdr.len = m->m_len = 1476 (total_len - ETHER_CRC_LEN); 1477 } 1478 1479#ifndef __NO_STRICT_ALIGNMENT 1480 vge_fixup_rx(m); 1481#endif 1482 m->m_pkthdr.rcvif = ifp; 1483 1484 /* Do RX checksumming if enabled */ 1485 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 1486 (rxctl & VGE_RDCTL_FRAG) == 0) { 1487 /* Check IP header checksum */ 1488 if ((rxctl & VGE_RDCTL_IPPKT) != 0) 1489 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1490 if ((rxctl & VGE_RDCTL_IPCSUMOK) != 0) 1491 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1492 1493 /* Check TCP/UDP checksum */ 1494 if (rxctl & (VGE_RDCTL_TCPPKT | VGE_RDCTL_UDPPKT) && 1495 rxctl & VGE_RDCTL_PROTOCSUMOK) { 1496 m->m_pkthdr.csum_flags |= 1497 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1498 m->m_pkthdr.csum_data = 0xffff; 1499 } 1500 } 1501 1502 if ((rxstat & VGE_RDSTS_VTAG) != 0) { 1503 /* 1504 * The 32-bit rxctl register is stored in little-endian. 1505 * However, the 16-bit vlan tag is stored in big-endian, 1506 * so we have to byte swap it. 1507 */ 1508 m->m_pkthdr.ether_vtag = 1509 bswap16(rxctl & VGE_RDCTL_VLANID); 1510 m->m_flags |= M_VLANTAG; 1511 } 1512 1513 VGE_UNLOCK(sc); 1514 (*ifp->if_input)(ifp, m); 1515 VGE_LOCK(sc); 1516 sc->vge_cdata.vge_head = NULL; 1517 sc->vge_cdata.vge_tail = NULL; 1518 } 1519 1520 if (prog > 0) { 1521 sc->vge_cdata.vge_rx_prodidx = prod; 1522 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, 1523 sc->vge_cdata.vge_rx_ring_map, 1524 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1525 /* Update residue counter. */ 1526 if (sc->vge_cdata.vge_rx_commit != 0) { 1527 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, 1528 sc->vge_cdata.vge_rx_commit); 1529 sc->vge_cdata.vge_rx_commit = 0; 1530 } 1531 } 1532 return (prog); 1533} 1534 1535static void 1536vge_txeof(struct vge_softc *sc) 1537{ 1538 struct ifnet *ifp; 1539 struct vge_tx_desc *cur_tx; 1540 struct vge_txdesc *txd; 1541 uint32_t txstat; 1542 int cons, prod; 1543 1544 VGE_LOCK_ASSERT(sc); 1545 1546 ifp = sc->vge_ifp; 1547 1548 if (sc->vge_cdata.vge_tx_cnt == 0) 1549 return; 1550 1551 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1552 sc->vge_cdata.vge_tx_ring_map, 1553 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1554 1555 /* 1556 * Go through our tx list and free mbufs for those 1557 * frames that have been transmitted. 1558 */ 1559 cons = sc->vge_cdata.vge_tx_considx; 1560 prod = sc->vge_cdata.vge_tx_prodidx; 1561 for (; cons != prod; VGE_TX_DESC_INC(cons)) { 1562 cur_tx = &sc->vge_rdata.vge_tx_ring[cons]; 1563 txstat = le32toh(cur_tx->vge_sts); 1564 if ((txstat & VGE_TDSTS_OWN) != 0) 1565 break; 1566 sc->vge_cdata.vge_tx_cnt--; 1567 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1568 1569 txd = &sc->vge_cdata.vge_txdesc[cons]; 1570 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap, 1571 BUS_DMASYNC_POSTWRITE); 1572 bus_dmamap_unload(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap); 1573 1574 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!\n", 1575 __func__)); 1576 m_freem(txd->tx_m); 1577 txd->tx_m = NULL; 1578 txd->tx_desc->vge_frag[0].vge_addrhi = 0; 1579 } 1580 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1581 sc->vge_cdata.vge_tx_ring_map, 1582 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1583 sc->vge_cdata.vge_tx_considx = cons; 1584 if (sc->vge_cdata.vge_tx_cnt == 0) 1585 sc->vge_timer = 0; 1586 else { 1587 /* 1588 * If not all descriptors have been released reaped yet, 1589 * reload the timer so that we will eventually get another 1590 * interrupt that will cause us to re-enter this routine. 1591 * This is done in case the transmitter has gone idle. 1592 */ 1593 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1594 } 1595} 1596 1597static void 1598vge_tick(void *xsc) 1599{ 1600 struct vge_softc *sc; 1601 struct ifnet *ifp; 1602 struct mii_data *mii; 1603 1604 sc = xsc; 1605 ifp = sc->vge_ifp; 1606 VGE_LOCK_ASSERT(sc); 1607 mii = device_get_softc(sc->vge_miibus); 1608 1609 mii_tick(mii); 1610 if ((sc->vge_flags & VGE_FLAG_LINK) != 0) { 1611 if (!(mii->mii_media_status & IFM_ACTIVE)) { 1612 sc->vge_flags &= ~VGE_FLAG_LINK; 1613 if_link_state_change(sc->vge_ifp, 1614 LINK_STATE_DOWN); 1615 } 1616 } else { 1617 if (mii->mii_media_status & IFM_ACTIVE && 1618 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1619 sc->vge_flags |= VGE_FLAG_LINK; 1620 if_link_state_change(sc->vge_ifp, 1621 LINK_STATE_UP); 1622 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1623 vge_start_locked(ifp); 1624 } 1625 } 1626} 1627 1628#ifdef DEVICE_POLLING 1629static int 1630vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1631{ 1632 struct vge_softc *sc = ifp->if_softc; 1633 int rx_npkts = 0; 1634 1635 VGE_LOCK(sc); 1636 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1637 goto done; 1638 1639 rx_npkts = vge_rxeof(sc, count); 1640 vge_txeof(sc); 1641 1642 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1643 vge_start_locked(ifp); 1644 1645 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1646 uint32_t status; 1647 status = CSR_READ_4(sc, VGE_ISR); 1648 if (status == 0xFFFFFFFF) 1649 goto done; 1650 if (status) 1651 CSR_WRITE_4(sc, VGE_ISR, status); 1652 1653 /* 1654 * XXX check behaviour on receiver stalls. 1655 */ 1656 1657 if (status & VGE_ISR_TXDMA_STALL || 1658 status & VGE_ISR_RXDMA_STALL) { 1659 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1660 vge_init_locked(sc); 1661 } 1662 1663 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1664 vge_rxeof(sc, count); 1665 ifp->if_ierrors++; 1666 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1667 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1668 } 1669 } 1670done: 1671 VGE_UNLOCK(sc); 1672 return (rx_npkts); 1673} 1674#endif /* DEVICE_POLLING */ 1675 1676static void 1677vge_intr(void *arg) 1678{ 1679 struct vge_softc *sc; 1680 struct ifnet *ifp; 1681 uint32_t status; 1682 1683 sc = arg; 1684 1685 if (sc->suspended) { 1686 return; 1687 } 1688 1689 VGE_LOCK(sc); 1690 ifp = sc->vge_ifp; 1691 1692 if (!(ifp->if_flags & IFF_UP)) { 1693 VGE_UNLOCK(sc); 1694 return; 1695 } 1696 1697#ifdef DEVICE_POLLING 1698 if (ifp->if_capenable & IFCAP_POLLING) { 1699 VGE_UNLOCK(sc); 1700 return; 1701 } 1702#endif 1703 1704 /* Disable interrupts */ 1705 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1706 1707 for (;;) { 1708 1709 status = CSR_READ_4(sc, VGE_ISR); 1710 /* If the card has gone away the read returns 0xffff. */ 1711 if (status == 0xFFFFFFFF) 1712 break; 1713 1714 if (status) 1715 CSR_WRITE_4(sc, VGE_ISR, status); 1716 1717 if ((status & VGE_INTRS) == 0) 1718 break; 1719 1720 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1721 vge_rxeof(sc, VGE_RX_DESC_CNT); 1722 1723 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1724 vge_rxeof(sc, VGE_RX_DESC_CNT); 1725 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1726 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1727 } 1728 1729 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1730 vge_txeof(sc); 1731 1732 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) { 1733 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1734 vge_init_locked(sc); 1735 } 1736 1737 if (status & VGE_ISR_LINKSTS) 1738 vge_tick(sc); 1739 } 1740 1741 /* Re-enable interrupts */ 1742 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1743 1744 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1745 vge_start_locked(ifp); 1746 1747 VGE_UNLOCK(sc); 1748} 1749 1750static int 1751vge_encap(struct vge_softc *sc, struct mbuf **m_head) 1752{ 1753 struct vge_txdesc *txd; 1754 struct vge_tx_frag *frag; 1755 struct mbuf *m; 1756 bus_dma_segment_t txsegs[VGE_MAXTXSEGS]; 1757 int error, i, nsegs, padlen; 1758 uint32_t cflags; 1759 1760 VGE_LOCK_ASSERT(sc); 1761 1762 M_ASSERTPKTHDR((*m_head)); 1763 1764 /* Argh. This chip does not autopad short frames. */ 1765 if ((*m_head)->m_pkthdr.len < VGE_MIN_FRAMELEN) { 1766 m = *m_head; 1767 padlen = VGE_MIN_FRAMELEN - m->m_pkthdr.len; 1768 if (M_WRITABLE(m) == 0) { 1769 /* Get a writable copy. */ 1770 m = m_dup(*m_head, M_DONTWAIT); 1771 m_freem(*m_head); 1772 if (m == NULL) { 1773 *m_head = NULL; 1774 return (ENOBUFS); 1775 } 1776 *m_head = m; 1777 } 1778 if (M_TRAILINGSPACE(m) < padlen) { 1779 m = m_defrag(m, M_DONTWAIT); 1780 if (m == NULL) { 1781 m_freem(*m_head); 1782 *m_head = NULL; 1783 return (ENOBUFS); 1784 } 1785 } 1786 /* 1787 * Manually pad short frames, and zero the pad space 1788 * to avoid leaking data. 1789 */ 1790 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1791 m->m_pkthdr.len += padlen; 1792 m->m_len = m->m_pkthdr.len; 1793 *m_head = m; 1794 } 1795 1796 txd = &sc->vge_cdata.vge_txdesc[sc->vge_cdata.vge_tx_prodidx]; 1797 1798 error = bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_tx_tag, 1799 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1800 if (error == EFBIG) { 1801 m = m_collapse(*m_head, M_DONTWAIT, VGE_MAXTXSEGS); 1802 if (m == NULL) { 1803 m_freem(*m_head); 1804 *m_head = NULL; 1805 return (ENOMEM); 1806 } 1807 *m_head = m; 1808 error = bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_tx_tag, 1809 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1810 if (error != 0) { 1811 m_freem(*m_head); 1812 *m_head = NULL; 1813 return (error); 1814 } 1815 } else if (error != 0) 1816 return (error); 1817 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap, 1818 BUS_DMASYNC_PREWRITE); 1819 1820 m = *m_head; 1821 cflags = 0; 1822 1823 /* Configure checksum offload. */ 1824 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 1825 cflags |= VGE_TDCTL_IPCSUM; 1826 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1827 cflags |= VGE_TDCTL_TCPCSUM; 1828 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1829 cflags |= VGE_TDCTL_UDPCSUM; 1830 1831 /* Configure VLAN. */ 1832 if ((m->m_flags & M_VLANTAG) != 0) 1833 cflags |= m->m_pkthdr.ether_vtag | VGE_TDCTL_VTAG; 1834 txd->tx_desc->vge_sts = htole32(m->m_pkthdr.len << 16); 1835 /* 1836 * XXX 1837 * Velocity family seems to support TSO but no information 1838 * for MSS configuration is available. Also the number of 1839 * fragments supported by a descriptor is too small to hold 1840 * entire 64KB TCP/IP segment. Maybe VGE_TD_LS_MOF, 1841 * VGE_TD_LS_SOF and VGE_TD_LS_EOF could be used to build 1842 * longer chain of buffers but no additional information is 1843 * available. 1844 * 1845 * When telling the chip how many segments there are, we 1846 * must use nsegs + 1 instead of just nsegs. Darned if I 1847 * know why. This also means we can't use the last fragment 1848 * field of Tx descriptor. 1849 */ 1850 txd->tx_desc->vge_ctl = htole32(cflags | ((nsegs + 1) << 28) | 1851 VGE_TD_LS_NORM); 1852 for (i = 0; i < nsegs; i++) { 1853 frag = &txd->tx_desc->vge_frag[i]; 1854 frag->vge_addrlo = htole32(VGE_ADDR_LO(txsegs[i].ds_addr)); 1855 frag->vge_addrhi = htole32(VGE_ADDR_HI(txsegs[i].ds_addr) | 1856 (VGE_BUFLEN(txsegs[i].ds_len) << 16)); 1857 } 1858 1859 sc->vge_cdata.vge_tx_cnt++; 1860 VGE_TX_DESC_INC(sc->vge_cdata.vge_tx_prodidx); 1861 1862 /* 1863 * Finally request interrupt and give the first descriptor 1864 * ownership to hardware. 1865 */ 1866 txd->tx_desc->vge_ctl |= htole32(VGE_TDCTL_TIC); 1867 txd->tx_desc->vge_sts |= htole32(VGE_TDSTS_OWN); 1868 txd->tx_m = m; 1869 1870 return (0); 1871} 1872 1873/* 1874 * Main transmit routine. 1875 */ 1876 1877static void 1878vge_start(struct ifnet *ifp) 1879{ 1880 struct vge_softc *sc; 1881 1882 sc = ifp->if_softc; 1883 VGE_LOCK(sc); 1884 vge_start_locked(ifp); 1885 VGE_UNLOCK(sc); 1886} 1887 1888 1889static void 1890vge_start_locked(struct ifnet *ifp) 1891{ 1892 struct vge_softc *sc; 1893 struct vge_txdesc *txd; 1894 struct mbuf *m_head; 1895 int enq, idx; 1896 1897 sc = ifp->if_softc; 1898 1899 VGE_LOCK_ASSERT(sc); 1900 1901 if ((sc->vge_flags & VGE_FLAG_LINK) == 0 || 1902 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1903 IFF_DRV_RUNNING) 1904 return; 1905 1906 idx = sc->vge_cdata.vge_tx_prodidx; 1907 VGE_TX_DESC_DEC(idx); 1908 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1909 sc->vge_cdata.vge_tx_cnt < VGE_TX_DESC_CNT - 1; ) { 1910 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1911 if (m_head == NULL) 1912 break; 1913 /* 1914 * Pack the data into the transmit ring. If we 1915 * don't have room, set the OACTIVE flag and wait 1916 * for the NIC to drain the ring. 1917 */ 1918 if (vge_encap(sc, &m_head)) { 1919 if (m_head == NULL) 1920 break; 1921 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1922 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1923 break; 1924 } 1925 1926 txd = &sc->vge_cdata.vge_txdesc[idx]; 1927 txd->tx_desc->vge_frag[0].vge_addrhi |= htole32(VGE_TXDESC_Q); 1928 VGE_TX_DESC_INC(idx); 1929 1930 enq++; 1931 /* 1932 * If there's a BPF listener, bounce a copy of this frame 1933 * to him. 1934 */ 1935 ETHER_BPF_MTAP(ifp, m_head); 1936 } 1937 1938 if (enq > 0) { 1939 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1940 sc->vge_cdata.vge_tx_ring_map, 1941 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1942 /* Issue a transmit command. */ 1943 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1944 /* 1945 * Use the countdown timer for interrupt moderation. 1946 * 'TX done' interrupts are disabled. Instead, we reset the 1947 * countdown timer, which will begin counting until it hits 1948 * the value in the SSTIMER register, and then trigger an 1949 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1950 * the timer count is reloaded. Only when the transmitter 1951 * is idle will the timer hit 0 and an interrupt fire. 1952 */ 1953 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1954 1955 /* 1956 * Set a timeout in case the chip goes out to lunch. 1957 */ 1958 sc->vge_timer = 5; 1959 } 1960} 1961 1962static void 1963vge_init(void *xsc) 1964{ 1965 struct vge_softc *sc = xsc; 1966 1967 VGE_LOCK(sc); 1968 vge_init_locked(sc); 1969 VGE_UNLOCK(sc); 1970} 1971 1972static void 1973vge_init_locked(struct vge_softc *sc) 1974{ 1975 struct ifnet *ifp = sc->vge_ifp; 1976 struct mii_data *mii; 1977 int error, i; 1978 1979 VGE_LOCK_ASSERT(sc); 1980 mii = device_get_softc(sc->vge_miibus); 1981 1982 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1983 return; 1984 1985 /* 1986 * Cancel pending I/O and free all RX/TX buffers. 1987 */ 1988 vge_stop(sc); 1989 vge_reset(sc); 1990 1991 /* 1992 * Initialize the RX and TX descriptors and mbufs. 1993 */ 1994 1995 error = vge_rx_list_init(sc); 1996 if (error != 0) { 1997 device_printf(sc->vge_dev, "no memory for Rx buffers.\n"); 1998 return; 1999 } 2000 vge_tx_list_init(sc); 2001 2002 /* Set our station address */ 2003 for (i = 0; i < ETHER_ADDR_LEN; i++) 2004 CSR_WRITE_1(sc, VGE_PAR0 + i, IF_LLADDR(sc->vge_ifp)[i]); 2005 2006 /* 2007 * Set receive FIFO threshold. Also allow transmission and 2008 * reception of VLAN tagged frames. 2009 */ 2010 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 2011 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 2012 2013 /* Set DMA burst length */ 2014 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 2015 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 2016 2017 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 2018 2019 /* Set collision backoff algorithm */ 2020 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 2021 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 2022 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 2023 2024 /* Disable LPSEL field in priority resolution */ 2025 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 2026 2027 /* 2028 * Load the addresses of the DMA queues into the chip. 2029 * Note that we only use one transmit queue. 2030 */ 2031 2032 CSR_WRITE_4(sc, VGE_TXDESC_HIADDR, 2033 VGE_ADDR_HI(sc->vge_rdata.vge_tx_ring_paddr)); 2034 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 2035 VGE_ADDR_LO(sc->vge_rdata.vge_tx_ring_paddr)); 2036 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 2037 2038 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 2039 VGE_ADDR_LO(sc->vge_rdata.vge_rx_ring_paddr)); 2040 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 2041 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 2042 2043 /* Enable and wake up the RX descriptor queue */ 2044 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 2045 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 2046 2047 /* Enable the TX descriptor queue */ 2048 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 2049 2050 /* Set up the receive filter -- allow large frames for VLANs. */ 2051 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 2052 2053 /* If we want promiscuous mode, set the allframes bit. */ 2054 if (ifp->if_flags & IFF_PROMISC) { 2055 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 2056 } 2057 2058 /* Set capture broadcast bit to capture broadcast frames. */ 2059 if (ifp->if_flags & IFF_BROADCAST) { 2060 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 2061 } 2062 2063 /* Set multicast bit to capture multicast frames. */ 2064 if (ifp->if_flags & IFF_MULTICAST) { 2065 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 2066 } 2067 2068 /* Init the cam filter. */ 2069 vge_cam_clear(sc); 2070 2071 /* Init the multicast filter. */ 2072 vge_setmulti(sc); 2073 2074 /* Enable flow control */ 2075 2076 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 2077 2078 /* Enable jumbo frame reception (if desired) */ 2079 2080 /* Start the MAC. */ 2081 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 2082 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 2083 CSR_WRITE_1(sc, VGE_CRS0, 2084 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 2085 2086 /* 2087 * Configure one-shot timer for microsecond 2088 * resolution and load it for 500 usecs. 2089 */ 2090 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 2091 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 2092 2093 /* 2094 * Configure interrupt moderation for receive. Enable 2095 * the holdoff counter and load it, and set the RX 2096 * suppression count to the number of descriptors we 2097 * want to allow before triggering an interrupt. 2098 * The holdoff timer is in units of 20 usecs. 2099 */ 2100 2101#ifdef notyet 2102 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 2103 /* Select the interrupt holdoff timer page. */ 2104 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2105 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 2106 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 2107 2108 /* Enable use of the holdoff timer. */ 2109 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 2110 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 2111 2112 /* Select the RX suppression threshold page. */ 2113 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2114 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 2115 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 2116 2117 /* Restore the page select bits. */ 2118 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2119 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 2120#endif 2121 2122#ifdef DEVICE_POLLING 2123 /* 2124 * Disable interrupts if we are polling. 2125 */ 2126 if (ifp->if_capenable & IFCAP_POLLING) { 2127 CSR_WRITE_4(sc, VGE_IMR, 0); 2128 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2129 } else /* otherwise ... */ 2130#endif 2131 { 2132 /* 2133 * Enable interrupts. 2134 */ 2135 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2136 CSR_WRITE_4(sc, VGE_ISR, 0); 2137 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2138 } 2139 2140 sc->vge_flags &= ~VGE_FLAG_LINK; 2141 mii_mediachg(mii); 2142 2143 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2144 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2145 callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc); 2146} 2147 2148/* 2149 * Set media options. 2150 */ 2151static int 2152vge_ifmedia_upd(struct ifnet *ifp) 2153{ 2154 struct vge_softc *sc; 2155 struct mii_data *mii; 2156 2157 sc = ifp->if_softc; 2158 VGE_LOCK(sc); 2159 mii = device_get_softc(sc->vge_miibus); 2160 mii_mediachg(mii); 2161 VGE_UNLOCK(sc); 2162 2163 return (0); 2164} 2165 2166/* 2167 * Report current media status. 2168 */ 2169static void 2170vge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2171{ 2172 struct vge_softc *sc; 2173 struct mii_data *mii; 2174 2175 sc = ifp->if_softc; 2176 mii = device_get_softc(sc->vge_miibus); 2177 2178 VGE_LOCK(sc); 2179 mii_pollstat(mii); 2180 VGE_UNLOCK(sc); 2181 ifmr->ifm_active = mii->mii_media_active; 2182 ifmr->ifm_status = mii->mii_media_status; 2183} 2184 2185static void 2186vge_miibus_statchg(device_t dev) 2187{ 2188 struct vge_softc *sc; 2189 struct mii_data *mii; 2190 struct ifmedia_entry *ife; 2191 2192 sc = device_get_softc(dev); 2193 mii = device_get_softc(sc->vge_miibus); 2194 ife = mii->mii_media.ifm_cur; 2195 2196 /* 2197 * If the user manually selects a media mode, we need to turn 2198 * on the forced MAC mode bit in the DIAGCTL register. If the 2199 * user happens to choose a full duplex mode, we also need to 2200 * set the 'force full duplex' bit. This applies only to 2201 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2202 * mode is disabled, and in 1000baseT mode, full duplex is 2203 * always implied, so we turn on the forced mode bit but leave 2204 * the FDX bit cleared. 2205 */ 2206 2207 switch (IFM_SUBTYPE(ife->ifm_media)) { 2208 case IFM_AUTO: 2209 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2210 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2211 break; 2212 case IFM_1000_T: 2213 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2214 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2215 break; 2216 case IFM_100_TX: 2217 case IFM_10_T: 2218 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2219 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2220 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2221 } else { 2222 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2223 } 2224 break; 2225 default: 2226 device_printf(dev, "unknown media type: %x\n", 2227 IFM_SUBTYPE(ife->ifm_media)); 2228 break; 2229 } 2230} 2231 2232static int 2233vge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2234{ 2235 struct vge_softc *sc = ifp->if_softc; 2236 struct ifreq *ifr = (struct ifreq *) data; 2237 struct mii_data *mii; 2238 int error = 0; 2239 2240 switch (command) { 2241 case SIOCSIFMTU: 2242 if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2243 error = EINVAL; 2244 ifp->if_mtu = ifr->ifr_mtu; 2245 break; 2246 case SIOCSIFFLAGS: 2247 VGE_LOCK(sc); 2248 if (ifp->if_flags & IFF_UP) { 2249 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2250 ifp->if_flags & IFF_PROMISC && 2251 !(sc->vge_if_flags & IFF_PROMISC)) { 2252 CSR_SETBIT_1(sc, VGE_RXCTL, 2253 VGE_RXCTL_RX_PROMISC); 2254 vge_setmulti(sc); 2255 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2256 !(ifp->if_flags & IFF_PROMISC) && 2257 sc->vge_if_flags & IFF_PROMISC) { 2258 CSR_CLRBIT_1(sc, VGE_RXCTL, 2259 VGE_RXCTL_RX_PROMISC); 2260 vge_setmulti(sc); 2261 } else 2262 vge_init_locked(sc); 2263 } else { 2264 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2265 vge_stop(sc); 2266 } 2267 sc->vge_if_flags = ifp->if_flags; 2268 VGE_UNLOCK(sc); 2269 break; 2270 case SIOCADDMULTI: 2271 case SIOCDELMULTI: 2272 VGE_LOCK(sc); 2273 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2274 vge_setmulti(sc); 2275 VGE_UNLOCK(sc); 2276 break; 2277 case SIOCGIFMEDIA: 2278 case SIOCSIFMEDIA: 2279 mii = device_get_softc(sc->vge_miibus); 2280 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2281 break; 2282 case SIOCSIFCAP: 2283 { 2284 int mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2285#ifdef DEVICE_POLLING 2286 if (mask & IFCAP_POLLING) { 2287 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2288 error = ether_poll_register(vge_poll, ifp); 2289 if (error) 2290 return (error); 2291 VGE_LOCK(sc); 2292 /* Disable interrupts */ 2293 CSR_WRITE_4(sc, VGE_IMR, 0); 2294 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2295 ifp->if_capenable |= IFCAP_POLLING; 2296 VGE_UNLOCK(sc); 2297 } else { 2298 error = ether_poll_deregister(ifp); 2299 /* Enable interrupts. */ 2300 VGE_LOCK(sc); 2301 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2302 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2303 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2304 ifp->if_capenable &= ~IFCAP_POLLING; 2305 VGE_UNLOCK(sc); 2306 } 2307 } 2308#endif /* DEVICE_POLLING */ 2309 VGE_LOCK(sc); 2310 if ((mask & IFCAP_TXCSUM) != 0 && 2311 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2312 ifp->if_capenable ^= IFCAP_TXCSUM; 2313 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2314 ifp->if_hwassist |= VGE_CSUM_FEATURES; 2315 else 2316 ifp->if_hwassist &= ~VGE_CSUM_FEATURES; 2317 } 2318 if ((mask & IFCAP_RXCSUM) != 0 && 2319 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 2320 ifp->if_capenable ^= IFCAP_RXCSUM; 2321 VGE_UNLOCK(sc); 2322 } 2323 break; 2324 default: 2325 error = ether_ioctl(ifp, command, data); 2326 break; 2327 } 2328 2329 return (error); 2330} 2331 2332static void 2333vge_watchdog(void *arg) 2334{ 2335 struct vge_softc *sc; 2336 struct ifnet *ifp; 2337 2338 sc = arg; 2339 VGE_LOCK_ASSERT(sc); 2340 callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc); 2341 if (sc->vge_timer == 0 || --sc->vge_timer > 0) 2342 return; 2343 2344 ifp = sc->vge_ifp; 2345 if_printf(ifp, "watchdog timeout\n"); 2346 ifp->if_oerrors++; 2347 2348 vge_txeof(sc); 2349 vge_rxeof(sc, VGE_RX_DESC_CNT); 2350 2351 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2352 vge_init_locked(sc); 2353} 2354 2355/* 2356 * Stop the adapter and free any mbufs allocated to the 2357 * RX and TX lists. 2358 */ 2359static void 2360vge_stop(struct vge_softc *sc) 2361{ 2362 struct ifnet *ifp; 2363 2364 VGE_LOCK_ASSERT(sc); 2365 ifp = sc->vge_ifp; 2366 sc->vge_timer = 0; 2367 callout_stop(&sc->vge_watchdog); 2368 2369 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2370 2371 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2372 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2373 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2374 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2375 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2376 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2377 2378 VGE_CHAIN_RESET(sc); 2379 vge_txeof(sc); 2380 vge_freebufs(sc); 2381} 2382 2383/* 2384 * Device suspend routine. Stop the interface and save some PCI 2385 * settings in case the BIOS doesn't restore them properly on 2386 * resume. 2387 */ 2388static int 2389vge_suspend(device_t dev) 2390{ 2391 struct vge_softc *sc; 2392 2393 sc = device_get_softc(dev); 2394 2395 VGE_LOCK(sc); 2396 vge_stop(sc); 2397 2398 sc->suspended = 1; 2399 VGE_UNLOCK(sc); 2400 2401 return (0); 2402} 2403 2404/* 2405 * Device resume routine. Restore some PCI settings in case the BIOS 2406 * doesn't, re-enable busmastering, and restart the interface if 2407 * appropriate. 2408 */ 2409static int 2410vge_resume(device_t dev) 2411{ 2412 struct vge_softc *sc; 2413 struct ifnet *ifp; 2414 2415 sc = device_get_softc(dev); 2416 ifp = sc->vge_ifp; 2417 2418 /* reenable busmastering */ 2419 pci_enable_busmaster(dev); 2420 pci_enable_io(dev, SYS_RES_MEMORY); 2421 2422 /* reinitialize interface if necessary */ 2423 VGE_LOCK(sc); 2424 if (ifp->if_flags & IFF_UP) { 2425 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2426 vge_init_locked(sc); 2427 } 2428 sc->suspended = 0; 2429 VGE_UNLOCK(sc); 2430 2431 return (0); 2432} 2433 2434/* 2435 * Stop all chip I/O so that the kernel's probe routines don't 2436 * get confused by errant DMAs when rebooting. 2437 */ 2438static int 2439vge_shutdown(device_t dev) 2440{ 2441 struct vge_softc *sc; 2442 2443 sc = device_get_softc(dev); 2444 2445 VGE_LOCK(sc); 2446 vge_stop(sc); 2447 VGE_UNLOCK(sc); 2448 2449 return (0); 2450} 2451