if_vge.c revision 200532
1/*- 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/vge/if_vge.c 200532 2009-12-14 19:49:20Z yongari $"); 35 36/* 37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 46 * combines a tri-speed ethernet MAC and PHY, with the following 47 * features: 48 * 49 * o Jumbo frame support up to 16K 50 * o Transmit and receive flow control 51 * o IPv4 checksum offload 52 * o VLAN tag insertion and stripping 53 * o TCP large send 54 * o 64-bit multicast hash table filter 55 * o 64 entry CAM filter 56 * o 16K RX FIFO and 48K TX FIFO memory 57 * o Interrupt moderation 58 * 59 * The VT6122 supports up to four transmit DMA queues. The descriptors 60 * in the transmit ring can address up to 7 data fragments; frames which 61 * span more than 7 data buffers must be coalesced, but in general the 62 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 63 * long. The receive descriptors address only a single buffer. 64 * 65 * There are two peculiar design issues with the VT6122. One is that 66 * receive data buffers must be aligned on a 32-bit boundary. This is 67 * not a problem where the VT6122 is used as a LOM device in x86-based 68 * systems, but on architectures that generate unaligned access traps, we 69 * have to do some copying. 70 * 71 * The other issue has to do with the way 64-bit addresses are handled. 72 * The DMA descriptors only allow you to specify 48 bits of addressing 73 * information. The remaining 16 bits are specified using one of the 74 * I/O registers. If you only have a 32-bit system, then this isn't 75 * an issue, but if you have a 64-bit system and more than 4GB of 76 * memory, you must have to make sure your network data buffers reside 77 * in the same 48-bit 'segment.' 78 * 79 * Special thanks to Ryan Fu at VIA Networking for providing documentation 80 * and sample NICs for testing. 81 */ 82 83#ifdef HAVE_KERNEL_OPTION_HEADERS 84#include "opt_device_polling.h" 85#endif 86 87#include <sys/param.h> 88#include <sys/endian.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/module.h> 94#include <sys/kernel.h> 95#include <sys/socket.h> 96 97#include <net/if.h> 98#include <net/if_arp.h> 99#include <net/ethernet.h> 100#include <net/if_dl.h> 101#include <net/if_media.h> 102#include <net/if_types.h> 103#include <net/if_vlan_var.h> 104 105#include <net/bpf.h> 106 107#include <machine/bus.h> 108#include <machine/resource.h> 109#include <sys/bus.h> 110#include <sys/rman.h> 111 112#include <dev/mii/mii.h> 113#include <dev/mii/miivar.h> 114 115#include <dev/pci/pcireg.h> 116#include <dev/pci/pcivar.h> 117 118MODULE_DEPEND(vge, pci, 1, 1, 1); 119MODULE_DEPEND(vge, ether, 1, 1, 1); 120MODULE_DEPEND(vge, miibus, 1, 1, 1); 121 122/* "device miibus" required. See GENERIC if you get errors here. */ 123#include "miibus_if.h" 124 125#include <dev/vge/if_vgereg.h> 126#include <dev/vge/if_vgevar.h> 127 128#define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 129 130/* 131 * Various supported device vendors/types and their names. 132 */ 133static struct vge_type vge_devs[] = { 134 { VIA_VENDORID, VIA_DEVICEID_61XX, 135 "VIA Networking Gigabit Ethernet" }, 136 { 0, 0, NULL } 137}; 138 139static int vge_probe (device_t); 140static int vge_attach (device_t); 141static int vge_detach (device_t); 142 143static int vge_encap (struct vge_softc *, struct mbuf **); 144 145static void vge_dmamap_cb (void *, bus_dma_segment_t *, int, int); 146static int vge_dma_alloc (struct vge_softc *); 147static void vge_dma_free (struct vge_softc *); 148static void vge_discard_rxbuf (struct vge_softc *, int); 149static int vge_newbuf (struct vge_softc *, int); 150static int vge_rx_list_init (struct vge_softc *); 151static int vge_tx_list_init (struct vge_softc *); 152static void vge_freebufs (struct vge_softc *); 153#ifndef __NO_STRICT_ALIGNMENT 154static __inline void vge_fixup_rx 155 (struct mbuf *); 156#endif 157static int vge_rxeof (struct vge_softc *, int); 158static void vge_txeof (struct vge_softc *); 159static void vge_intr (void *); 160static void vge_tick (void *); 161static void vge_start (struct ifnet *); 162static void vge_start_locked (struct ifnet *); 163static int vge_ioctl (struct ifnet *, u_long, caddr_t); 164static void vge_init (void *); 165static void vge_init_locked (struct vge_softc *); 166static void vge_stop (struct vge_softc *); 167static void vge_watchdog (void *); 168static int vge_suspend (device_t); 169static int vge_resume (device_t); 170static int vge_shutdown (device_t); 171static int vge_ifmedia_upd (struct ifnet *); 172static void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 173 174#ifdef VGE_EEPROM 175static void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 176#endif 177static void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 178 179static void vge_miipoll_start (struct vge_softc *); 180static void vge_miipoll_stop (struct vge_softc *); 181static int vge_miibus_readreg (device_t, int, int); 182static int vge_miibus_writereg (device_t, int, int, int); 183static void vge_miibus_statchg (device_t); 184 185static void vge_cam_clear (struct vge_softc *); 186static int vge_cam_set (struct vge_softc *, uint8_t *); 187static void vge_setmulti (struct vge_softc *); 188static void vge_reset (struct vge_softc *); 189 190static device_method_t vge_methods[] = { 191 /* Device interface */ 192 DEVMETHOD(device_probe, vge_probe), 193 DEVMETHOD(device_attach, vge_attach), 194 DEVMETHOD(device_detach, vge_detach), 195 DEVMETHOD(device_suspend, vge_suspend), 196 DEVMETHOD(device_resume, vge_resume), 197 DEVMETHOD(device_shutdown, vge_shutdown), 198 199 /* bus interface */ 200 DEVMETHOD(bus_print_child, bus_generic_print_child), 201 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 202 203 /* MII interface */ 204 DEVMETHOD(miibus_readreg, vge_miibus_readreg), 205 DEVMETHOD(miibus_writereg, vge_miibus_writereg), 206 DEVMETHOD(miibus_statchg, vge_miibus_statchg), 207 208 { 0, 0 } 209}; 210 211static driver_t vge_driver = { 212 "vge", 213 vge_methods, 214 sizeof(struct vge_softc) 215}; 216 217static devclass_t vge_devclass; 218 219DRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0); 220DRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0); 221 222#ifdef VGE_EEPROM 223/* 224 * Read a word of data stored in the EEPROM at address 'addr.' 225 */ 226static void 227vge_eeprom_getword(struct vge_softc *sc, int addr, u_int16_t *dest) 228{ 229 int i; 230 u_int16_t word = 0; 231 232 /* 233 * Enter EEPROM embedded programming mode. In order to 234 * access the EEPROM at all, we first have to set the 235 * EELOAD bit in the CHIPCFG2 register. 236 */ 237 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 238 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 239 240 /* Select the address of the word we want to read */ 241 CSR_WRITE_1(sc, VGE_EEADDR, addr); 242 243 /* Issue read command */ 244 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 245 246 /* Wait for the done bit to be set. */ 247 for (i = 0; i < VGE_TIMEOUT; i++) { 248 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 249 break; 250 } 251 252 if (i == VGE_TIMEOUT) { 253 device_printf(sc->vge_dev, "EEPROM read timed out\n"); 254 *dest = 0; 255 return; 256 } 257 258 /* Read the result */ 259 word = CSR_READ_2(sc, VGE_EERDDAT); 260 261 /* Turn off EEPROM access mode. */ 262 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 263 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 264 265 *dest = word; 266} 267#endif 268 269/* 270 * Read a sequence of words from the EEPROM. 271 */ 272static void 273vge_read_eeprom(struct vge_softc *sc, caddr_t dest, int off, int cnt, int swap) 274{ 275 int i; 276#ifdef VGE_EEPROM 277 u_int16_t word = 0, *ptr; 278 279 for (i = 0; i < cnt; i++) { 280 vge_eeprom_getword(sc, off + i, &word); 281 ptr = (u_int16_t *)(dest + (i * 2)); 282 if (swap) 283 *ptr = ntohs(word); 284 else 285 *ptr = word; 286 } 287#else 288 for (i = 0; i < ETHER_ADDR_LEN; i++) 289 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 290#endif 291} 292 293static void 294vge_miipoll_stop(struct vge_softc *sc) 295{ 296 int i; 297 298 CSR_WRITE_1(sc, VGE_MIICMD, 0); 299 300 for (i = 0; i < VGE_TIMEOUT; i++) { 301 DELAY(1); 302 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 303 break; 304 } 305 306 if (i == VGE_TIMEOUT) 307 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 308} 309 310static void 311vge_miipoll_start(struct vge_softc *sc) 312{ 313 int i; 314 315 /* First, make sure we're idle. */ 316 317 CSR_WRITE_1(sc, VGE_MIICMD, 0); 318 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 319 320 for (i = 0; i < VGE_TIMEOUT; i++) { 321 DELAY(1); 322 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 323 break; 324 } 325 326 if (i == VGE_TIMEOUT) { 327 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 328 return; 329 } 330 331 /* Now enable auto poll mode. */ 332 333 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 334 335 /* And make sure it started. */ 336 337 for (i = 0; i < VGE_TIMEOUT; i++) { 338 DELAY(1); 339 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 340 break; 341 } 342 343 if (i == VGE_TIMEOUT) 344 device_printf(sc->vge_dev, "failed to start MII autopoll\n"); 345} 346 347static int 348vge_miibus_readreg(device_t dev, int phy, int reg) 349{ 350 struct vge_softc *sc; 351 int i; 352 u_int16_t rval = 0; 353 354 sc = device_get_softc(dev); 355 356 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 357 return(0); 358 359 vge_miipoll_stop(sc); 360 361 /* Specify the register we want to read. */ 362 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 363 364 /* Issue read command. */ 365 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 366 367 /* Wait for the read command bit to self-clear. */ 368 for (i = 0; i < VGE_TIMEOUT; i++) { 369 DELAY(1); 370 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 371 break; 372 } 373 374 if (i == VGE_TIMEOUT) 375 device_printf(sc->vge_dev, "MII read timed out\n"); 376 else 377 rval = CSR_READ_2(sc, VGE_MIIDATA); 378 379 vge_miipoll_start(sc); 380 381 return (rval); 382} 383 384static int 385vge_miibus_writereg(device_t dev, int phy, int reg, int data) 386{ 387 struct vge_softc *sc; 388 int i, rval = 0; 389 390 sc = device_get_softc(dev); 391 392 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 393 return(0); 394 395 vge_miipoll_stop(sc); 396 397 /* Specify the register we want to write. */ 398 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 399 400 /* Specify the data we want to write. */ 401 CSR_WRITE_2(sc, VGE_MIIDATA, data); 402 403 /* Issue write command. */ 404 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 405 406 /* Wait for the write command bit to self-clear. */ 407 for (i = 0; i < VGE_TIMEOUT; i++) { 408 DELAY(1); 409 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 410 break; 411 } 412 413 if (i == VGE_TIMEOUT) { 414 device_printf(sc->vge_dev, "MII write timed out\n"); 415 rval = EIO; 416 } 417 418 vge_miipoll_start(sc); 419 420 return (rval); 421} 422 423static void 424vge_cam_clear(struct vge_softc *sc) 425{ 426 int i; 427 428 /* 429 * Turn off all the mask bits. This tells the chip 430 * that none of the entries in the CAM filter are valid. 431 * desired entries will be enabled as we fill the filter in. 432 */ 433 434 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 435 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 436 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 437 for (i = 0; i < 8; i++) 438 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 439 440 /* Clear the VLAN filter too. */ 441 442 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 443 for (i = 0; i < 8; i++) 444 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 445 446 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 447 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 448 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 449 450 sc->vge_camidx = 0; 451} 452 453static int 454vge_cam_set(struct vge_softc *sc, uint8_t *addr) 455{ 456 int i, error = 0; 457 458 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 459 return(ENOSPC); 460 461 /* Select the CAM data page. */ 462 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 463 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 464 465 /* Set the filter entry we want to update and enable writing. */ 466 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 467 468 /* Write the address to the CAM registers */ 469 for (i = 0; i < ETHER_ADDR_LEN; i++) 470 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 471 472 /* Issue a write command. */ 473 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 474 475 /* Wake for it to clear. */ 476 for (i = 0; i < VGE_TIMEOUT; i++) { 477 DELAY(1); 478 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 479 break; 480 } 481 482 if (i == VGE_TIMEOUT) { 483 device_printf(sc->vge_dev, "setting CAM filter failed\n"); 484 error = EIO; 485 goto fail; 486 } 487 488 /* Select the CAM mask page. */ 489 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 490 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 491 492 /* Set the mask bit that enables this filter. */ 493 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 494 1<<(sc->vge_camidx & 7)); 495 496 sc->vge_camidx++; 497 498fail: 499 /* Turn off access to CAM. */ 500 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 501 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 502 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 503 504 return (error); 505} 506 507/* 508 * Program the multicast filter. We use the 64-entry CAM filter 509 * for perfect filtering. If there's more than 64 multicast addresses, 510 * we use the hash filter instead. 511 */ 512static void 513vge_setmulti(struct vge_softc *sc) 514{ 515 struct ifnet *ifp; 516 int error = 0/*, h = 0*/; 517 struct ifmultiaddr *ifma; 518 u_int32_t h, hashes[2] = { 0, 0 }; 519 520 VGE_LOCK_ASSERT(sc); 521 522 ifp = sc->vge_ifp; 523 524 /* First, zot all the multicast entries. */ 525 vge_cam_clear(sc); 526 CSR_WRITE_4(sc, VGE_MAR0, 0); 527 CSR_WRITE_4(sc, VGE_MAR1, 0); 528 529 /* 530 * If the user wants allmulti or promisc mode, enable reception 531 * of all multicast frames. 532 */ 533 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 534 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 535 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 536 return; 537 } 538 539 /* Now program new ones */ 540 if_maddr_rlock(ifp); 541 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 542 if (ifma->ifma_addr->sa_family != AF_LINK) 543 continue; 544 error = vge_cam_set(sc, 545 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 546 if (error) 547 break; 548 } 549 550 /* If there were too many addresses, use the hash filter. */ 551 if (error) { 552 vge_cam_clear(sc); 553 554 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 555 if (ifma->ifma_addr->sa_family != AF_LINK) 556 continue; 557 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 558 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 559 if (h < 32) 560 hashes[0] |= (1 << h); 561 else 562 hashes[1] |= (1 << (h - 32)); 563 } 564 565 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 566 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 567 } 568 if_maddr_runlock(ifp); 569} 570 571static void 572vge_reset(struct vge_softc *sc) 573{ 574 int i; 575 576 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 577 578 for (i = 0; i < VGE_TIMEOUT; i++) { 579 DELAY(5); 580 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 581 break; 582 } 583 584 if (i == VGE_TIMEOUT) { 585 device_printf(sc->vge_dev, "soft reset timed out"); 586 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 587 DELAY(2000); 588 } 589 590 DELAY(5000); 591 592 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 593 594 for (i = 0; i < VGE_TIMEOUT; i++) { 595 DELAY(5); 596 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 597 break; 598 } 599 600 if (i == VGE_TIMEOUT) { 601 device_printf(sc->vge_dev, "EEPROM reload timed out\n"); 602 return; 603 } 604 605 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 606} 607 608/* 609 * Probe for a VIA gigabit chip. Check the PCI vendor and device 610 * IDs against our list and return a device name if we find a match. 611 */ 612static int 613vge_probe(device_t dev) 614{ 615 struct vge_type *t; 616 617 t = vge_devs; 618 619 while (t->vge_name != NULL) { 620 if ((pci_get_vendor(dev) == t->vge_vid) && 621 (pci_get_device(dev) == t->vge_did)) { 622 device_set_desc(dev, t->vge_name); 623 return (BUS_PROBE_DEFAULT); 624 } 625 t++; 626 } 627 628 return (ENXIO); 629} 630 631/* 632 * Map a single buffer address. 633 */ 634 635struct vge_dmamap_arg { 636 bus_addr_t vge_busaddr; 637}; 638 639static void 640vge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 641{ 642 struct vge_dmamap_arg *ctx; 643 644 if (error != 0) 645 return; 646 647 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 648 649 ctx = (struct vge_dmamap_arg *)arg; 650 ctx->vge_busaddr = segs[0].ds_addr; 651} 652 653static int 654vge_dma_alloc(struct vge_softc *sc) 655{ 656 struct vge_dmamap_arg ctx; 657 struct vge_txdesc *txd; 658 struct vge_rxdesc *rxd; 659 bus_addr_t lowaddr, tx_ring_end, rx_ring_end; 660 int error, i; 661 662 lowaddr = BUS_SPACE_MAXADDR; 663 664again: 665 /* Create parent ring tag. */ 666 error = bus_dma_tag_create(bus_get_dma_tag(sc->vge_dev),/* parent */ 667 1, 0, /* algnmnt, boundary */ 668 lowaddr, /* lowaddr */ 669 BUS_SPACE_MAXADDR, /* highaddr */ 670 NULL, NULL, /* filter, filterarg */ 671 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 672 0, /* nsegments */ 673 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 674 0, /* flags */ 675 NULL, NULL, /* lockfunc, lockarg */ 676 &sc->vge_cdata.vge_ring_tag); 677 if (error != 0) { 678 device_printf(sc->vge_dev, 679 "could not create parent DMA tag.\n"); 680 goto fail; 681 } 682 683 /* Create tag for Tx ring. */ 684 error = bus_dma_tag_create(sc->vge_cdata.vge_ring_tag,/* parent */ 685 VGE_TX_RING_ALIGN, 0, /* algnmnt, boundary */ 686 BUS_SPACE_MAXADDR, /* lowaddr */ 687 BUS_SPACE_MAXADDR, /* highaddr */ 688 NULL, NULL, /* filter, filterarg */ 689 VGE_TX_LIST_SZ, /* maxsize */ 690 1, /* nsegments */ 691 VGE_TX_LIST_SZ, /* maxsegsize */ 692 0, /* flags */ 693 NULL, NULL, /* lockfunc, lockarg */ 694 &sc->vge_cdata.vge_tx_ring_tag); 695 if (error != 0) { 696 device_printf(sc->vge_dev, 697 "could not allocate Tx ring DMA tag.\n"); 698 goto fail; 699 } 700 701 /* Create tag for Rx ring. */ 702 error = bus_dma_tag_create(sc->vge_cdata.vge_ring_tag,/* parent */ 703 VGE_RX_RING_ALIGN, 0, /* algnmnt, boundary */ 704 BUS_SPACE_MAXADDR, /* lowaddr */ 705 BUS_SPACE_MAXADDR, /* highaddr */ 706 NULL, NULL, /* filter, filterarg */ 707 VGE_RX_LIST_SZ, /* maxsize */ 708 1, /* nsegments */ 709 VGE_RX_LIST_SZ, /* maxsegsize */ 710 0, /* flags */ 711 NULL, NULL, /* lockfunc, lockarg */ 712 &sc->vge_cdata.vge_rx_ring_tag); 713 if (error != 0) { 714 device_printf(sc->vge_dev, 715 "could not allocate Rx ring DMA tag.\n"); 716 goto fail; 717 } 718 719 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 720 error = bus_dmamem_alloc(sc->vge_cdata.vge_tx_ring_tag, 721 (void **)&sc->vge_rdata.vge_tx_ring, 722 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 723 &sc->vge_cdata.vge_tx_ring_map); 724 if (error != 0) { 725 device_printf(sc->vge_dev, 726 "could not allocate DMA'able memory for Tx ring.\n"); 727 goto fail; 728 } 729 730 ctx.vge_busaddr = 0; 731 error = bus_dmamap_load(sc->vge_cdata.vge_tx_ring_tag, 732 sc->vge_cdata.vge_tx_ring_map, sc->vge_rdata.vge_tx_ring, 733 VGE_TX_LIST_SZ, vge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 734 if (error != 0 || ctx.vge_busaddr == 0) { 735 device_printf(sc->vge_dev, 736 "could not load DMA'able memory for Tx ring.\n"); 737 goto fail; 738 } 739 sc->vge_rdata.vge_tx_ring_paddr = ctx.vge_busaddr; 740 741 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 742 error = bus_dmamem_alloc(sc->vge_cdata.vge_rx_ring_tag, 743 (void **)&sc->vge_rdata.vge_rx_ring, 744 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 745 &sc->vge_cdata.vge_rx_ring_map); 746 if (error != 0) { 747 device_printf(sc->vge_dev, 748 "could not allocate DMA'able memory for Rx ring.\n"); 749 goto fail; 750 } 751 752 ctx.vge_busaddr = 0; 753 error = bus_dmamap_load(sc->vge_cdata.vge_rx_ring_tag, 754 sc->vge_cdata.vge_rx_ring_map, sc->vge_rdata.vge_rx_ring, 755 VGE_RX_LIST_SZ, vge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 756 if (error != 0 || ctx.vge_busaddr == 0) { 757 device_printf(sc->vge_dev, 758 "could not load DMA'able memory for Rx ring.\n"); 759 goto fail; 760 } 761 sc->vge_rdata.vge_rx_ring_paddr = ctx.vge_busaddr; 762 763 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 764 tx_ring_end = sc->vge_rdata.vge_tx_ring_paddr + VGE_TX_LIST_SZ; 765 rx_ring_end = sc->vge_rdata.vge_rx_ring_paddr + VGE_RX_LIST_SZ; 766 if ((VGE_ADDR_HI(tx_ring_end) != 767 VGE_ADDR_HI(sc->vge_rdata.vge_tx_ring_paddr)) || 768 (VGE_ADDR_HI(rx_ring_end) != 769 VGE_ADDR_HI(sc->vge_rdata.vge_rx_ring_paddr)) || 770 VGE_ADDR_HI(tx_ring_end) != VGE_ADDR_HI(rx_ring_end)) { 771 device_printf(sc->vge_dev, "4GB boundary crossed, " 772 "switching to 32bit DMA address mode.\n"); 773 vge_dma_free(sc); 774 /* Limit DMA address space to 32bit and try again. */ 775 lowaddr = BUS_SPACE_MAXADDR_32BIT; 776 goto again; 777 } 778 779 /* Create parent buffer tag. */ 780 error = bus_dma_tag_create(bus_get_dma_tag(sc->vge_dev),/* parent */ 781 1, 0, /* algnmnt, boundary */ 782 VGE_BUF_DMA_MAXADDR, /* lowaddr */ 783 BUS_SPACE_MAXADDR, /* highaddr */ 784 NULL, NULL, /* filter, filterarg */ 785 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 786 0, /* nsegments */ 787 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 788 0, /* flags */ 789 NULL, NULL, /* lockfunc, lockarg */ 790 &sc->vge_cdata.vge_buffer_tag); 791 if (error != 0) { 792 device_printf(sc->vge_dev, 793 "could not create parent buffer DMA tag.\n"); 794 goto fail; 795 } 796 797 /* Create tag for Tx buffers. */ 798 error = bus_dma_tag_create(sc->vge_cdata.vge_buffer_tag,/* parent */ 799 1, 0, /* algnmnt, boundary */ 800 BUS_SPACE_MAXADDR, /* lowaddr */ 801 BUS_SPACE_MAXADDR, /* highaddr */ 802 NULL, NULL, /* filter, filterarg */ 803 MCLBYTES * VGE_MAXTXSEGS, /* maxsize */ 804 VGE_MAXTXSEGS, /* nsegments */ 805 MCLBYTES, /* maxsegsize */ 806 0, /* flags */ 807 NULL, NULL, /* lockfunc, lockarg */ 808 &sc->vge_cdata.vge_tx_tag); 809 if (error != 0) { 810 device_printf(sc->vge_dev, "could not create Tx DMA tag.\n"); 811 goto fail; 812 } 813 814 /* Create tag for Rx buffers. */ 815 error = bus_dma_tag_create(sc->vge_cdata.vge_buffer_tag,/* parent */ 816 VGE_RX_BUF_ALIGN, 0, /* algnmnt, boundary */ 817 BUS_SPACE_MAXADDR, /* lowaddr */ 818 BUS_SPACE_MAXADDR, /* highaddr */ 819 NULL, NULL, /* filter, filterarg */ 820 MCLBYTES, /* maxsize */ 821 1, /* nsegments */ 822 MCLBYTES, /* maxsegsize */ 823 0, /* flags */ 824 NULL, NULL, /* lockfunc, lockarg */ 825 &sc->vge_cdata.vge_rx_tag); 826 if (error != 0) { 827 device_printf(sc->vge_dev, "could not create Rx DMA tag.\n"); 828 goto fail; 829 } 830 831 /* Create DMA maps for Tx buffers. */ 832 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 833 txd = &sc->vge_cdata.vge_txdesc[i]; 834 txd->tx_m = NULL; 835 txd->tx_dmamap = NULL; 836 error = bus_dmamap_create(sc->vge_cdata.vge_tx_tag, 0, 837 &txd->tx_dmamap); 838 if (error != 0) { 839 device_printf(sc->vge_dev, 840 "could not create Tx dmamap.\n"); 841 goto fail; 842 } 843 } 844 /* Create DMA maps for Rx buffers. */ 845 if ((error = bus_dmamap_create(sc->vge_cdata.vge_rx_tag, 0, 846 &sc->vge_cdata.vge_rx_sparemap)) != 0) { 847 device_printf(sc->vge_dev, 848 "could not create spare Rx dmamap.\n"); 849 goto fail; 850 } 851 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 852 rxd = &sc->vge_cdata.vge_rxdesc[i]; 853 rxd->rx_m = NULL; 854 rxd->rx_dmamap = NULL; 855 error = bus_dmamap_create(sc->vge_cdata.vge_rx_tag, 0, 856 &rxd->rx_dmamap); 857 if (error != 0) { 858 device_printf(sc->vge_dev, 859 "could not create Rx dmamap.\n"); 860 goto fail; 861 } 862 } 863 864fail: 865 return (error); 866} 867 868static void 869vge_dma_free(struct vge_softc *sc) 870{ 871 struct vge_txdesc *txd; 872 struct vge_rxdesc *rxd; 873 int i; 874 875 /* Tx ring. */ 876 if (sc->vge_cdata.vge_tx_ring_tag != NULL) { 877 if (sc->vge_cdata.vge_tx_ring_map) 878 bus_dmamap_unload(sc->vge_cdata.vge_tx_ring_tag, 879 sc->vge_cdata.vge_tx_ring_map); 880 if (sc->vge_cdata.vge_tx_ring_map && 881 sc->vge_rdata.vge_tx_ring) 882 bus_dmamem_free(sc->vge_cdata.vge_tx_ring_tag, 883 sc->vge_rdata.vge_tx_ring, 884 sc->vge_cdata.vge_tx_ring_map); 885 sc->vge_rdata.vge_tx_ring = NULL; 886 sc->vge_cdata.vge_tx_ring_map = NULL; 887 bus_dma_tag_destroy(sc->vge_cdata.vge_tx_ring_tag); 888 sc->vge_cdata.vge_tx_ring_tag = NULL; 889 } 890 /* Rx ring. */ 891 if (sc->vge_cdata.vge_rx_ring_tag != NULL) { 892 if (sc->vge_cdata.vge_rx_ring_map) 893 bus_dmamap_unload(sc->vge_cdata.vge_rx_ring_tag, 894 sc->vge_cdata.vge_rx_ring_map); 895 if (sc->vge_cdata.vge_rx_ring_map && 896 sc->vge_rdata.vge_rx_ring) 897 bus_dmamem_free(sc->vge_cdata.vge_rx_ring_tag, 898 sc->vge_rdata.vge_rx_ring, 899 sc->vge_cdata.vge_rx_ring_map); 900 sc->vge_rdata.vge_rx_ring = NULL; 901 sc->vge_cdata.vge_rx_ring_map = NULL; 902 bus_dma_tag_destroy(sc->vge_cdata.vge_rx_ring_tag); 903 sc->vge_cdata.vge_rx_ring_tag = NULL; 904 } 905 /* Tx buffers. */ 906 if (sc->vge_cdata.vge_tx_tag != NULL) { 907 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 908 txd = &sc->vge_cdata.vge_txdesc[i]; 909 if (txd->tx_dmamap != NULL) { 910 bus_dmamap_destroy(sc->vge_cdata.vge_tx_tag, 911 txd->tx_dmamap); 912 txd->tx_dmamap = NULL; 913 } 914 } 915 bus_dma_tag_destroy(sc->vge_cdata.vge_tx_tag); 916 sc->vge_cdata.vge_tx_tag = NULL; 917 } 918 /* Rx buffers. */ 919 if (sc->vge_cdata.vge_rx_tag != NULL) { 920 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 921 rxd = &sc->vge_cdata.vge_rxdesc[i]; 922 if (rxd->rx_dmamap != NULL) { 923 bus_dmamap_destroy(sc->vge_cdata.vge_rx_tag, 924 rxd->rx_dmamap); 925 rxd->rx_dmamap = NULL; 926 } 927 } 928 if (sc->vge_cdata.vge_rx_sparemap != NULL) { 929 bus_dmamap_destroy(sc->vge_cdata.vge_rx_tag, 930 sc->vge_cdata.vge_rx_sparemap); 931 sc->vge_cdata.vge_rx_sparemap = NULL; 932 } 933 bus_dma_tag_destroy(sc->vge_cdata.vge_rx_tag); 934 sc->vge_cdata.vge_rx_tag = NULL; 935 } 936 937 if (sc->vge_cdata.vge_buffer_tag != NULL) { 938 bus_dma_tag_destroy(sc->vge_cdata.vge_buffer_tag); 939 sc->vge_cdata.vge_buffer_tag = NULL; 940 } 941 if (sc->vge_cdata.vge_ring_tag != NULL) { 942 bus_dma_tag_destroy(sc->vge_cdata.vge_ring_tag); 943 sc->vge_cdata.vge_ring_tag = NULL; 944 } 945} 946 947/* 948 * Attach the interface. Allocate softc structures, do ifmedia 949 * setup and ethernet/BPF attach. 950 */ 951static int 952vge_attach(device_t dev) 953{ 954 u_char eaddr[ETHER_ADDR_LEN]; 955 struct vge_softc *sc; 956 struct ifnet *ifp; 957 int error = 0, rid; 958 959 sc = device_get_softc(dev); 960 sc->vge_dev = dev; 961 962 mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 963 MTX_DEF); 964 callout_init_mtx(&sc->vge_watchdog, &sc->vge_mtx, 0); 965 966 /* 967 * Map control/status registers. 968 */ 969 pci_enable_busmaster(dev); 970 971 rid = PCIR_BAR(1); 972 sc->vge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 973 RF_ACTIVE); 974 975 if (sc->vge_res == NULL) { 976 device_printf(dev, "couldn't map ports/memory\n"); 977 error = ENXIO; 978 goto fail; 979 } 980 981 /* Allocate interrupt */ 982 rid = 0; 983 sc->vge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 984 RF_SHAREABLE | RF_ACTIVE); 985 986 if (sc->vge_irq == NULL) { 987 device_printf(dev, "couldn't map interrupt\n"); 988 error = ENXIO; 989 goto fail; 990 } 991 992 /* Reset the adapter. */ 993 vge_reset(sc); 994 995 /* 996 * Get station address from the EEPROM. 997 */ 998 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 999 1000 error = vge_dma_alloc(sc); 1001 if (error) 1002 goto fail; 1003 1004 ifp = sc->vge_ifp = if_alloc(IFT_ETHER); 1005 if (ifp == NULL) { 1006 device_printf(dev, "can not if_alloc()\n"); 1007 error = ENOSPC; 1008 goto fail; 1009 } 1010 1011 /* Do MII setup */ 1012 if (mii_phy_probe(dev, &sc->vge_miibus, 1013 vge_ifmedia_upd, vge_ifmedia_sts)) { 1014 device_printf(dev, "MII without any phy!\n"); 1015 error = ENXIO; 1016 goto fail; 1017 } 1018 1019 ifp->if_softc = sc; 1020 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1021 ifp->if_mtu = ETHERMTU; 1022 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1023 ifp->if_ioctl = vge_ioctl; 1024 ifp->if_capabilities = IFCAP_VLAN_MTU; 1025 ifp->if_start = vge_start; 1026 ifp->if_hwassist = VGE_CSUM_FEATURES; 1027 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1028 ifp->if_capenable = ifp->if_capabilities; 1029#ifdef DEVICE_POLLING 1030 ifp->if_capabilities |= IFCAP_POLLING; 1031#endif 1032 ifp->if_init = vge_init; 1033 IFQ_SET_MAXLEN(&ifp->if_snd, VGE_IFQ_MAXLEN); 1034 ifp->if_snd.ifq_drv_maxlen = VGE_IFQ_MAXLEN; 1035 IFQ_SET_READY(&ifp->if_snd); 1036 1037 /* 1038 * Call MI attach routine. 1039 */ 1040 ether_ifattach(ifp, eaddr); 1041 1042 /* Hook interrupt last to avoid having to lock softc */ 1043 error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE, 1044 NULL, vge_intr, sc, &sc->vge_intrhand); 1045 1046 if (error) { 1047 device_printf(dev, "couldn't set up irq\n"); 1048 ether_ifdetach(ifp); 1049 goto fail; 1050 } 1051 1052fail: 1053 if (error) 1054 vge_detach(dev); 1055 1056 return (error); 1057} 1058 1059/* 1060 * Shutdown hardware and free up resources. This can be called any 1061 * time after the mutex has been initialized. It is called in both 1062 * the error case in attach and the normal detach case so it needs 1063 * to be careful about only freeing resources that have actually been 1064 * allocated. 1065 */ 1066static int 1067vge_detach(device_t dev) 1068{ 1069 struct vge_softc *sc; 1070 struct ifnet *ifp; 1071 1072 sc = device_get_softc(dev); 1073 KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized")); 1074 ifp = sc->vge_ifp; 1075 1076#ifdef DEVICE_POLLING 1077 if (ifp->if_capenable & IFCAP_POLLING) 1078 ether_poll_deregister(ifp); 1079#endif 1080 1081 /* These should only be active if attach succeeded */ 1082 if (device_is_attached(dev)) { 1083 ether_ifdetach(ifp); 1084 VGE_LOCK(sc); 1085 vge_stop(sc); 1086 VGE_UNLOCK(sc); 1087 callout_drain(&sc->vge_watchdog); 1088 } 1089 if (sc->vge_miibus) 1090 device_delete_child(dev, sc->vge_miibus); 1091 bus_generic_detach(dev); 1092 1093 if (sc->vge_intrhand) 1094 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); 1095 if (sc->vge_irq) 1096 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vge_irq); 1097 if (sc->vge_res) 1098 bus_release_resource(dev, SYS_RES_MEMORY, 1099 PCIR_BAR(1), sc->vge_res); 1100 if (ifp) 1101 if_free(ifp); 1102 1103 vge_dma_free(sc); 1104 mtx_destroy(&sc->vge_mtx); 1105 1106 return (0); 1107} 1108 1109static void 1110vge_discard_rxbuf(struct vge_softc *sc, int prod) 1111{ 1112 struct vge_rxdesc *rxd; 1113 int i; 1114 1115 rxd = &sc->vge_cdata.vge_rxdesc[prod]; 1116 rxd->rx_desc->vge_sts = 0; 1117 rxd->rx_desc->vge_ctl = 0; 1118 1119 /* 1120 * Note: the manual fails to document the fact that for 1121 * proper opration, the driver needs to replentish the RX 1122 * DMA ring 4 descriptors at a time (rather than one at a 1123 * time, like most chips). We can allocate the new buffers 1124 * but we should not set the OWN bits until we're ready 1125 * to hand back 4 of them in one shot. 1126 */ 1127 if ((prod % VGE_RXCHUNK) == (VGE_RXCHUNK - 1)) { 1128 for (i = VGE_RXCHUNK; i > 0; i--) { 1129 rxd->rx_desc->vge_sts = htole32(VGE_RDSTS_OWN); 1130 rxd = rxd->rxd_prev; 1131 } 1132 sc->vge_cdata.vge_rx_commit += VGE_RXCHUNK; 1133 } 1134} 1135 1136static int 1137vge_newbuf(struct vge_softc *sc, int prod) 1138{ 1139 struct vge_rxdesc *rxd; 1140 struct mbuf *m; 1141 bus_dma_segment_t segs[1]; 1142 bus_dmamap_t map; 1143 int i, nsegs; 1144 1145 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1146 if (m == NULL) 1147 return (ENOBUFS); 1148 /* 1149 * This is part of an evil trick to deal with strict-alignment 1150 * architectures. The VIA chip requires RX buffers to be aligned 1151 * on 32-bit boundaries, but that will hose strict-alignment 1152 * architectures. To get around this, we leave some empty space 1153 * at the start of each buffer and for non-strict-alignment hosts, 1154 * we copy the buffer back two bytes to achieve word alignment. 1155 * This is slightly more efficient than allocating a new buffer, 1156 * copying the contents, and discarding the old buffer. 1157 */ 1158 m->m_len = m->m_pkthdr.len = MCLBYTES; 1159 m_adj(m, VGE_RX_BUF_ALIGN); 1160 1161 if (bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_rx_tag, 1162 sc->vge_cdata.vge_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1163 m_freem(m); 1164 return (ENOBUFS); 1165 } 1166 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1167 1168 rxd = &sc->vge_cdata.vge_rxdesc[prod]; 1169 if (rxd->rx_m != NULL) { 1170 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap, 1171 BUS_DMASYNC_POSTREAD); 1172 bus_dmamap_unload(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap); 1173 } 1174 map = rxd->rx_dmamap; 1175 rxd->rx_dmamap = sc->vge_cdata.vge_rx_sparemap; 1176 sc->vge_cdata.vge_rx_sparemap = map; 1177 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap, 1178 BUS_DMASYNC_PREREAD); 1179 rxd->rx_m = m; 1180 1181 rxd->rx_desc->vge_sts = 0; 1182 rxd->rx_desc->vge_ctl = 0; 1183 rxd->rx_desc->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 1184 rxd->rx_desc->vge_addrhi = htole32(VGE_ADDR_HI(segs[0].ds_addr) | 1185 (VGE_BUFLEN(segs[0].ds_len) << 16) | VGE_RXDESC_I); 1186 1187 /* 1188 * Note: the manual fails to document the fact that for 1189 * proper operation, the driver needs to replenish the RX 1190 * DMA ring 4 descriptors at a time (rather than one at a 1191 * time, like most chips). We can allocate the new buffers 1192 * but we should not set the OWN bits until we're ready 1193 * to hand back 4 of them in one shot. 1194 */ 1195 if ((prod % VGE_RXCHUNK) == (VGE_RXCHUNK - 1)) { 1196 for (i = VGE_RXCHUNK; i > 0; i--) { 1197 rxd->rx_desc->vge_sts = htole32(VGE_RDSTS_OWN); 1198 rxd = rxd->rxd_prev; 1199 } 1200 sc->vge_cdata.vge_rx_commit += VGE_RXCHUNK; 1201 } 1202 1203 return (0); 1204} 1205 1206static int 1207vge_tx_list_init(struct vge_softc *sc) 1208{ 1209 struct vge_ring_data *rd; 1210 struct vge_txdesc *txd; 1211 int i; 1212 1213 VGE_LOCK_ASSERT(sc); 1214 1215 sc->vge_cdata.vge_tx_prodidx = 0; 1216 sc->vge_cdata.vge_tx_considx = 0; 1217 sc->vge_cdata.vge_tx_cnt = 0; 1218 1219 rd = &sc->vge_rdata; 1220 bzero(rd->vge_tx_ring, VGE_TX_LIST_SZ); 1221 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 1222 txd = &sc->vge_cdata.vge_txdesc[i]; 1223 txd->tx_m = NULL; 1224 txd->tx_desc = &rd->vge_tx_ring[i]; 1225 } 1226 1227 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1228 sc->vge_cdata.vge_tx_ring_map, 1229 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1230 1231 return (0); 1232} 1233 1234static int 1235vge_rx_list_init(struct vge_softc *sc) 1236{ 1237 struct vge_ring_data *rd; 1238 struct vge_rxdesc *rxd; 1239 int i; 1240 1241 VGE_LOCK_ASSERT(sc); 1242 1243 sc->vge_cdata.vge_rx_prodidx = 0; 1244 sc->vge_cdata.vge_head = NULL; 1245 sc->vge_cdata.vge_tail = NULL; 1246 sc->vge_cdata.vge_rx_commit = 0; 1247 1248 rd = &sc->vge_rdata; 1249 bzero(rd->vge_rx_ring, VGE_RX_LIST_SZ); 1250 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1251 rxd = &sc->vge_cdata.vge_rxdesc[i]; 1252 rxd->rx_m = NULL; 1253 rxd->rx_desc = &rd->vge_rx_ring[i]; 1254 if (i == 0) 1255 rxd->rxd_prev = 1256 &sc->vge_cdata.vge_rxdesc[VGE_RX_DESC_CNT - 1]; 1257 else 1258 rxd->rxd_prev = &sc->vge_cdata.vge_rxdesc[i - 1]; 1259 if (vge_newbuf(sc, i) != 0) 1260 return (ENOBUFS); 1261 } 1262 1263 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, 1264 sc->vge_cdata.vge_rx_ring_map, 1265 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1266 1267 sc->vge_cdata.vge_rx_commit = 0; 1268 1269 return (0); 1270} 1271 1272static void 1273vge_freebufs(struct vge_softc *sc) 1274{ 1275 struct vge_txdesc *txd; 1276 struct vge_rxdesc *rxd; 1277 struct ifnet *ifp; 1278 int i; 1279 1280 VGE_LOCK_ASSERT(sc); 1281 1282 ifp = sc->vge_ifp; 1283 /* 1284 * Free RX and TX mbufs still in the queues. 1285 */ 1286 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1287 rxd = &sc->vge_cdata.vge_rxdesc[i]; 1288 if (rxd->rx_m != NULL) { 1289 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, 1290 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 1291 bus_dmamap_unload(sc->vge_cdata.vge_rx_tag, 1292 rxd->rx_dmamap); 1293 m_freem(rxd->rx_m); 1294 rxd->rx_m = NULL; 1295 } 1296 } 1297 1298 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 1299 txd = &sc->vge_cdata.vge_txdesc[i]; 1300 if (txd->tx_m != NULL) { 1301 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, 1302 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1303 bus_dmamap_unload(sc->vge_cdata.vge_tx_tag, 1304 txd->tx_dmamap); 1305 m_freem(txd->tx_m); 1306 txd->tx_m = NULL; 1307 ifp->if_oerrors++; 1308 } 1309 } 1310} 1311 1312#ifndef __NO_STRICT_ALIGNMENT 1313static __inline void 1314vge_fixup_rx(struct mbuf *m) 1315{ 1316 int i; 1317 uint16_t *src, *dst; 1318 1319 src = mtod(m, uint16_t *); 1320 dst = src - 1; 1321 1322 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1323 *dst++ = *src++; 1324 1325 m->m_data -= ETHER_ALIGN; 1326} 1327#endif 1328 1329/* 1330 * RX handler. We support the reception of jumbo frames that have 1331 * been fragmented across multiple 2K mbuf cluster buffers. 1332 */ 1333static int 1334vge_rxeof(struct vge_softc *sc, int count) 1335{ 1336 struct mbuf *m; 1337 struct ifnet *ifp; 1338 int prod, prog, total_len; 1339 struct vge_rxdesc *rxd; 1340 struct vge_rx_desc *cur_rx; 1341 uint32_t rxstat, rxctl; 1342 1343 VGE_LOCK_ASSERT(sc); 1344 1345 ifp = sc->vge_ifp; 1346 1347 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, 1348 sc->vge_cdata.vge_rx_ring_map, 1349 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1350 1351 prod = sc->vge_cdata.vge_rx_prodidx; 1352 for (prog = 0; count > 0 && 1353 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 1354 VGE_RX_DESC_INC(prod)) { 1355 cur_rx = &sc->vge_rdata.vge_rx_ring[prod]; 1356 rxstat = le32toh(cur_rx->vge_sts); 1357 if ((rxstat & VGE_RDSTS_OWN) != 0) 1358 break; 1359 count--; 1360 prog++; 1361 rxctl = le32toh(cur_rx->vge_ctl); 1362 total_len = VGE_RXBYTES(rxstat); 1363 rxd = &sc->vge_cdata.vge_rxdesc[prod]; 1364 m = rxd->rx_m; 1365 1366 /* 1367 * If the 'start of frame' bit is set, this indicates 1368 * either the first fragment in a multi-fragment receive, 1369 * or an intermediate fragment. Either way, we want to 1370 * accumulate the buffers. 1371 */ 1372 if ((rxstat & VGE_RXPKT_SOF) != 0) { 1373 if (vge_newbuf(sc, prod) != 0) { 1374 ifp->if_iqdrops++; 1375 VGE_CHAIN_RESET(sc); 1376 vge_discard_rxbuf(sc, prod); 1377 continue; 1378 } 1379 m->m_len = MCLBYTES - VGE_RX_BUF_ALIGN; 1380 if (sc->vge_cdata.vge_head == NULL) { 1381 sc->vge_cdata.vge_head = m; 1382 sc->vge_cdata.vge_tail = m; 1383 } else { 1384 m->m_flags &= ~M_PKTHDR; 1385 sc->vge_cdata.vge_tail->m_next = m; 1386 sc->vge_cdata.vge_tail = m; 1387 } 1388 continue; 1389 } 1390 1391 /* 1392 * Bad/error frames will have the RXOK bit cleared. 1393 * However, there's one error case we want to allow: 1394 * if a VLAN tagged frame arrives and the chip can't 1395 * match it against the CAM filter, it considers this 1396 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1397 * We don't want to drop the frame though: our VLAN 1398 * filtering is done in software. 1399 * We also want to receive bad-checksummed frames and 1400 * and frames with bad-length. 1401 */ 1402 if ((rxstat & VGE_RDSTS_RXOK) == 0 && 1403 (rxstat & (VGE_RDSTS_VIDM | VGE_RDSTS_RLERR | 1404 VGE_RDSTS_CSUMERR)) == 0) { 1405 ifp->if_ierrors++; 1406 /* 1407 * If this is part of a multi-fragment packet, 1408 * discard all the pieces. 1409 */ 1410 VGE_CHAIN_RESET(sc); 1411 vge_discard_rxbuf(sc, prod); 1412 continue; 1413 } 1414 1415 if (vge_newbuf(sc, prod) != 0) { 1416 ifp->if_iqdrops++; 1417 VGE_CHAIN_RESET(sc); 1418 vge_discard_rxbuf(sc, prod); 1419 continue; 1420 } 1421 1422 /* Chain received mbufs. */ 1423 if (sc->vge_cdata.vge_head != NULL) { 1424 m->m_len = total_len % (MCLBYTES - VGE_RX_BUF_ALIGN); 1425 /* 1426 * Special case: if there's 4 bytes or less 1427 * in this buffer, the mbuf can be discarded: 1428 * the last 4 bytes is the CRC, which we don't 1429 * care about anyway. 1430 */ 1431 if (m->m_len <= ETHER_CRC_LEN) { 1432 sc->vge_cdata.vge_tail->m_len -= 1433 (ETHER_CRC_LEN - m->m_len); 1434 m_freem(m); 1435 } else { 1436 m->m_len -= ETHER_CRC_LEN; 1437 m->m_flags &= ~M_PKTHDR; 1438 sc->vge_cdata.vge_tail->m_next = m; 1439 } 1440 m = sc->vge_cdata.vge_head; 1441 m->m_flags |= M_PKTHDR; 1442 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1443 } else { 1444 m->m_flags |= M_PKTHDR; 1445 m->m_pkthdr.len = m->m_len = 1446 (total_len - ETHER_CRC_LEN); 1447 } 1448 1449#ifndef __NO_STRICT_ALIGNMENT 1450 vge_fixup_rx(m); 1451#endif 1452 m->m_pkthdr.rcvif = ifp; 1453 1454 /* Do RX checksumming if enabled */ 1455 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 1456 (rxctl & VGE_RDCTL_FRAG) == 0) { 1457 /* Check IP header checksum */ 1458 if ((rxctl & VGE_RDCTL_IPPKT) != 0) 1459 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1460 if ((rxctl & VGE_RDCTL_IPCSUMOK) != 0) 1461 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1462 1463 /* Check TCP/UDP checksum */ 1464 if (rxctl & (VGE_RDCTL_TCPPKT | VGE_RDCTL_UDPPKT) && 1465 rxctl & VGE_RDCTL_PROTOCSUMOK) { 1466 m->m_pkthdr.csum_flags |= 1467 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1468 m->m_pkthdr.csum_data = 0xffff; 1469 } 1470 } 1471 1472 if ((rxstat & VGE_RDSTS_VTAG) != 0) { 1473 /* 1474 * The 32-bit rxctl register is stored in little-endian. 1475 * However, the 16-bit vlan tag is stored in big-endian, 1476 * so we have to byte swap it. 1477 */ 1478 m->m_pkthdr.ether_vtag = 1479 bswap16(rxctl & VGE_RDCTL_VLANID); 1480 m->m_flags |= M_VLANTAG; 1481 } 1482 1483 VGE_UNLOCK(sc); 1484 (*ifp->if_input)(ifp, m); 1485 VGE_LOCK(sc); 1486 sc->vge_cdata.vge_head = NULL; 1487 sc->vge_cdata.vge_tail = NULL; 1488 } 1489 1490 if (prog > 0) { 1491 sc->vge_cdata.vge_rx_prodidx = prod; 1492 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, 1493 sc->vge_cdata.vge_rx_ring_map, 1494 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1495 /* Update residue counter. */ 1496 if (sc->vge_cdata.vge_rx_commit != 0) { 1497 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, 1498 sc->vge_cdata.vge_rx_commit); 1499 sc->vge_cdata.vge_rx_commit = 0; 1500 } 1501 } 1502 return (prog); 1503} 1504 1505static void 1506vge_txeof(struct vge_softc *sc) 1507{ 1508 struct ifnet *ifp; 1509 struct vge_tx_desc *cur_tx; 1510 struct vge_txdesc *txd; 1511 uint32_t txstat; 1512 int cons, prod; 1513 1514 VGE_LOCK_ASSERT(sc); 1515 1516 ifp = sc->vge_ifp; 1517 1518 if (sc->vge_cdata.vge_tx_cnt == 0) 1519 return; 1520 1521 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1522 sc->vge_cdata.vge_tx_ring_map, 1523 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1524 1525 /* 1526 * Go through our tx list and free mbufs for those 1527 * frames that have been transmitted. 1528 */ 1529 cons = sc->vge_cdata.vge_tx_considx; 1530 prod = sc->vge_cdata.vge_tx_prodidx; 1531 for (; cons != prod; VGE_TX_DESC_INC(cons)) { 1532 cur_tx = &sc->vge_rdata.vge_tx_ring[cons]; 1533 txstat = le32toh(cur_tx->vge_sts); 1534 if ((txstat & VGE_TDSTS_OWN) != 0) 1535 break; 1536 sc->vge_cdata.vge_tx_cnt--; 1537 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1538 1539 txd = &sc->vge_cdata.vge_txdesc[cons]; 1540 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap, 1541 BUS_DMASYNC_POSTWRITE); 1542 bus_dmamap_unload(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap); 1543 1544 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!\n", 1545 __func__)); 1546 m_freem(txd->tx_m); 1547 txd->tx_m = NULL; 1548 txd->tx_desc->vge_frag[0].vge_addrhi = 0; 1549 } 1550 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1551 sc->vge_cdata.vge_tx_ring_map, 1552 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1553 sc->vge_cdata.vge_tx_considx = cons; 1554 if (sc->vge_cdata.vge_tx_cnt == 0) 1555 sc->vge_timer = 0; 1556 else { 1557 /* 1558 * If not all descriptors have been released reaped yet, 1559 * reload the timer so that we will eventually get another 1560 * interrupt that will cause us to re-enter this routine. 1561 * This is done in case the transmitter has gone idle. 1562 */ 1563 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1564 } 1565} 1566 1567static void 1568vge_tick(void *xsc) 1569{ 1570 struct vge_softc *sc; 1571 struct ifnet *ifp; 1572 struct mii_data *mii; 1573 1574 sc = xsc; 1575 ifp = sc->vge_ifp; 1576 VGE_LOCK_ASSERT(sc); 1577 mii = device_get_softc(sc->vge_miibus); 1578 1579 mii_tick(mii); 1580 if (sc->vge_link) { 1581 if (!(mii->mii_media_status & IFM_ACTIVE)) { 1582 sc->vge_link = 0; 1583 if_link_state_change(sc->vge_ifp, 1584 LINK_STATE_DOWN); 1585 } 1586 } else { 1587 if (mii->mii_media_status & IFM_ACTIVE && 1588 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1589 sc->vge_link = 1; 1590 if_link_state_change(sc->vge_ifp, 1591 LINK_STATE_UP); 1592 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1593 vge_start_locked(ifp); 1594 } 1595 } 1596} 1597 1598#ifdef DEVICE_POLLING 1599static int 1600vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1601{ 1602 struct vge_softc *sc = ifp->if_softc; 1603 int rx_npkts = 0; 1604 1605 VGE_LOCK(sc); 1606 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1607 goto done; 1608 1609 rx_npkts = vge_rxeof(sc, count); 1610 vge_txeof(sc); 1611 1612 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1613 vge_start_locked(ifp); 1614 1615 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1616 u_int32_t status; 1617 status = CSR_READ_4(sc, VGE_ISR); 1618 if (status == 0xFFFFFFFF) 1619 goto done; 1620 if (status) 1621 CSR_WRITE_4(sc, VGE_ISR, status); 1622 1623 /* 1624 * XXX check behaviour on receiver stalls. 1625 */ 1626 1627 if (status & VGE_ISR_TXDMA_STALL || 1628 status & VGE_ISR_RXDMA_STALL) { 1629 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1630 vge_init_locked(sc); 1631 } 1632 1633 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1634 vge_rxeof(sc, count); 1635 ifp->if_ierrors++; 1636 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1637 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1638 } 1639 } 1640done: 1641 VGE_UNLOCK(sc); 1642 return (rx_npkts); 1643} 1644#endif /* DEVICE_POLLING */ 1645 1646static void 1647vge_intr(void *arg) 1648{ 1649 struct vge_softc *sc; 1650 struct ifnet *ifp; 1651 u_int32_t status; 1652 1653 sc = arg; 1654 1655 if (sc->suspended) { 1656 return; 1657 } 1658 1659 VGE_LOCK(sc); 1660 ifp = sc->vge_ifp; 1661 1662 if (!(ifp->if_flags & IFF_UP)) { 1663 VGE_UNLOCK(sc); 1664 return; 1665 } 1666 1667#ifdef DEVICE_POLLING 1668 if (ifp->if_capenable & IFCAP_POLLING) { 1669 VGE_UNLOCK(sc); 1670 return; 1671 } 1672#endif 1673 1674 /* Disable interrupts */ 1675 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1676 1677 for (;;) { 1678 1679 status = CSR_READ_4(sc, VGE_ISR); 1680 /* If the card has gone away the read returns 0xffff. */ 1681 if (status == 0xFFFFFFFF) 1682 break; 1683 1684 if (status) 1685 CSR_WRITE_4(sc, VGE_ISR, status); 1686 1687 if ((status & VGE_INTRS) == 0) 1688 break; 1689 1690 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1691 vge_rxeof(sc, VGE_RX_DESC_CNT); 1692 1693 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1694 vge_rxeof(sc, VGE_RX_DESC_CNT); 1695 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1696 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1697 } 1698 1699 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1700 vge_txeof(sc); 1701 1702 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) { 1703 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1704 vge_init_locked(sc); 1705 } 1706 1707 if (status & VGE_ISR_LINKSTS) 1708 vge_tick(sc); 1709 } 1710 1711 /* Re-enable interrupts */ 1712 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1713 1714 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1715 vge_start_locked(ifp); 1716 1717 VGE_UNLOCK(sc); 1718} 1719 1720static int 1721vge_encap(struct vge_softc *sc, struct mbuf **m_head) 1722{ 1723 struct vge_txdesc *txd; 1724 struct vge_tx_frag *frag; 1725 struct mbuf *m; 1726 bus_dma_segment_t txsegs[VGE_MAXTXSEGS]; 1727 int error, i, nsegs, padlen; 1728 uint32_t cflags; 1729 1730 VGE_LOCK_ASSERT(sc); 1731 1732 M_ASSERTPKTHDR((*m_head)); 1733 1734 /* Argh. This chip does not autopad short frames. */ 1735 if ((*m_head)->m_pkthdr.len < VGE_MIN_FRAMELEN) { 1736 m = *m_head; 1737 padlen = VGE_MIN_FRAMELEN - m->m_pkthdr.len; 1738 if (M_WRITABLE(m) == 0) { 1739 /* Get a writable copy. */ 1740 m = m_dup(*m_head, M_DONTWAIT); 1741 m_freem(*m_head); 1742 if (m == NULL) { 1743 *m_head = NULL; 1744 return (ENOBUFS); 1745 } 1746 *m_head = m; 1747 } 1748 if (M_TRAILINGSPACE(m) < padlen) { 1749 m = m_defrag(m, M_DONTWAIT); 1750 if (m == NULL) { 1751 m_freem(*m_head); 1752 *m_head = NULL; 1753 return (ENOBUFS); 1754 } 1755 } 1756 /* 1757 * Manually pad short frames, and zero the pad space 1758 * to avoid leaking data. 1759 */ 1760 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1761 m->m_pkthdr.len += padlen; 1762 m->m_len = m->m_pkthdr.len; 1763 *m_head = m; 1764 } 1765 1766 txd = &sc->vge_cdata.vge_txdesc[sc->vge_cdata.vge_tx_prodidx]; 1767 1768 error = bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_tx_tag, 1769 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1770 if (error == EFBIG) { 1771 m = m_collapse(*m_head, M_DONTWAIT, VGE_MAXTXSEGS); 1772 if (m == NULL) { 1773 m_freem(*m_head); 1774 *m_head = NULL; 1775 return (ENOMEM); 1776 } 1777 *m_head = m; 1778 error = bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_tx_tag, 1779 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1780 if (error != 0) { 1781 m_freem(*m_head); 1782 *m_head = NULL; 1783 return (error); 1784 } 1785 } else if (error != 0) 1786 return (error); 1787 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap, 1788 BUS_DMASYNC_PREWRITE); 1789 1790 m = *m_head; 1791 cflags = 0; 1792 1793 /* Configure checksum offload. */ 1794 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 1795 cflags |= VGE_TDCTL_IPCSUM; 1796 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1797 cflags |= VGE_TDCTL_TCPCSUM; 1798 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1799 cflags |= VGE_TDCTL_UDPCSUM; 1800 1801 /* Configure VLAN. */ 1802 if ((m->m_flags & M_VLANTAG) != 0) 1803 cflags |= m->m_pkthdr.ether_vtag | VGE_TDCTL_VTAG; 1804 txd->tx_desc->vge_sts = htole32(m->m_pkthdr.len << 16); 1805 /* 1806 * XXX 1807 * Velocity family seems to support TSO but no information 1808 * for MSS configuration is available. Also the number of 1809 * fragments supported by a descriptor is too small to hold 1810 * entire 64KB TCP/IP segment. Maybe VGE_TD_LS_MOF, 1811 * VGE_TD_LS_SOF and VGE_TD_LS_EOF could be used to build 1812 * longer chain of buffers but no additional information is 1813 * available. 1814 * 1815 * When telling the chip how many segments there are, we 1816 * must use nsegs + 1 instead of just nsegs. Darned if I 1817 * know why. This also means we can't use the last fragment 1818 * field of Tx descriptor. 1819 */ 1820 txd->tx_desc->vge_ctl = htole32(cflags | ((nsegs + 1) << 28) | 1821 VGE_TD_LS_NORM); 1822 for (i = 0; i < nsegs; i++) { 1823 frag = &txd->tx_desc->vge_frag[i]; 1824 frag->vge_addrlo = htole32(VGE_ADDR_LO(txsegs[i].ds_addr)); 1825 frag->vge_addrhi = htole32(VGE_ADDR_HI(txsegs[i].ds_addr) | 1826 (VGE_BUFLEN(txsegs[i].ds_len) << 16)); 1827 } 1828 1829 sc->vge_cdata.vge_tx_cnt++; 1830 VGE_TX_DESC_INC(sc->vge_cdata.vge_tx_prodidx); 1831 1832 /* 1833 * Finally request interrupt and give the first descriptor 1834 * ownership to hardware. 1835 */ 1836 txd->tx_desc->vge_ctl |= htole32(VGE_TDCTL_TIC); 1837 txd->tx_desc->vge_sts |= htole32(VGE_TDSTS_OWN); 1838 txd->tx_m = m; 1839 1840 return (0); 1841} 1842 1843/* 1844 * Main transmit routine. 1845 */ 1846 1847static void 1848vge_start(struct ifnet *ifp) 1849{ 1850 struct vge_softc *sc; 1851 1852 sc = ifp->if_softc; 1853 VGE_LOCK(sc); 1854 vge_start_locked(ifp); 1855 VGE_UNLOCK(sc); 1856} 1857 1858 1859static void 1860vge_start_locked(struct ifnet *ifp) 1861{ 1862 struct vge_softc *sc; 1863 struct vge_txdesc *txd; 1864 struct mbuf *m_head; 1865 int enq, idx; 1866 1867 sc = ifp->if_softc; 1868 1869 VGE_LOCK_ASSERT(sc); 1870 1871 if (sc->vge_link == 0 || 1872 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1873 IFF_DRV_RUNNING) 1874 return; 1875 1876 idx = sc->vge_cdata.vge_tx_prodidx; 1877 VGE_TX_DESC_DEC(idx); 1878 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1879 sc->vge_cdata.vge_tx_cnt < VGE_TX_DESC_CNT - 1; ) { 1880 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1881 if (m_head == NULL) 1882 break; 1883 /* 1884 * Pack the data into the transmit ring. If we 1885 * don't have room, set the OACTIVE flag and wait 1886 * for the NIC to drain the ring. 1887 */ 1888 if (vge_encap(sc, &m_head)) { 1889 if (m_head == NULL) 1890 break; 1891 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1892 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1893 break; 1894 } 1895 1896 txd = &sc->vge_cdata.vge_txdesc[idx]; 1897 txd->tx_desc->vge_frag[0].vge_addrhi |= htole32(VGE_TXDESC_Q); 1898 VGE_TX_DESC_INC(idx); 1899 1900 enq++; 1901 /* 1902 * If there's a BPF listener, bounce a copy of this frame 1903 * to him. 1904 */ 1905 ETHER_BPF_MTAP(ifp, m_head); 1906 } 1907 1908 if (enq > 0) { 1909 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1910 sc->vge_cdata.vge_tx_ring_map, 1911 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1912 /* Issue a transmit command. */ 1913 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1914 /* 1915 * Use the countdown timer for interrupt moderation. 1916 * 'TX done' interrupts are disabled. Instead, we reset the 1917 * countdown timer, which will begin counting until it hits 1918 * the value in the SSTIMER register, and then trigger an 1919 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1920 * the timer count is reloaded. Only when the transmitter 1921 * is idle will the timer hit 0 and an interrupt fire. 1922 */ 1923 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1924 1925 /* 1926 * Set a timeout in case the chip goes out to lunch. 1927 */ 1928 sc->vge_timer = 5; 1929 } 1930} 1931 1932static void 1933vge_init(void *xsc) 1934{ 1935 struct vge_softc *sc = xsc; 1936 1937 VGE_LOCK(sc); 1938 vge_init_locked(sc); 1939 VGE_UNLOCK(sc); 1940} 1941 1942static void 1943vge_init_locked(struct vge_softc *sc) 1944{ 1945 struct ifnet *ifp = sc->vge_ifp; 1946 struct mii_data *mii; 1947 int error, i; 1948 1949 VGE_LOCK_ASSERT(sc); 1950 mii = device_get_softc(sc->vge_miibus); 1951 1952 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1953 return; 1954 1955 /* 1956 * Cancel pending I/O and free all RX/TX buffers. 1957 */ 1958 vge_stop(sc); 1959 vge_reset(sc); 1960 1961 /* 1962 * Initialize the RX and TX descriptors and mbufs. 1963 */ 1964 1965 error = vge_rx_list_init(sc); 1966 if (error != 0) { 1967 device_printf(sc->vge_dev, "no memory for Rx buffers.\n"); 1968 return; 1969 } 1970 vge_tx_list_init(sc); 1971 1972 /* Set our station address */ 1973 for (i = 0; i < ETHER_ADDR_LEN; i++) 1974 CSR_WRITE_1(sc, VGE_PAR0 + i, IF_LLADDR(sc->vge_ifp)[i]); 1975 1976 /* 1977 * Set receive FIFO threshold. Also allow transmission and 1978 * reception of VLAN tagged frames. 1979 */ 1980 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1981 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1982 1983 /* Set DMA burst length */ 1984 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1985 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1986 1987 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1988 1989 /* Set collision backoff algorithm */ 1990 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1991 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1992 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1993 1994 /* Disable LPSEL field in priority resolution */ 1995 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1996 1997 /* 1998 * Load the addresses of the DMA queues into the chip. 1999 * Note that we only use one transmit queue. 2000 */ 2001 2002 CSR_WRITE_4(sc, VGE_TXDESC_HIADDR, 2003 VGE_ADDR_HI(sc->vge_rdata.vge_tx_ring_paddr)); 2004 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 2005 VGE_ADDR_LO(sc->vge_rdata.vge_tx_ring_paddr)); 2006 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 2007 2008 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 2009 VGE_ADDR_LO(sc->vge_rdata.vge_rx_ring_paddr)); 2010 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 2011 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 2012 2013 /* Enable and wake up the RX descriptor queue */ 2014 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 2015 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 2016 2017 /* Enable the TX descriptor queue */ 2018 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 2019 2020 /* Set up the receive filter -- allow large frames for VLANs. */ 2021 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 2022 2023 /* If we want promiscuous mode, set the allframes bit. */ 2024 if (ifp->if_flags & IFF_PROMISC) { 2025 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 2026 } 2027 2028 /* Set capture broadcast bit to capture broadcast frames. */ 2029 if (ifp->if_flags & IFF_BROADCAST) { 2030 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 2031 } 2032 2033 /* Set multicast bit to capture multicast frames. */ 2034 if (ifp->if_flags & IFF_MULTICAST) { 2035 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 2036 } 2037 2038 /* Init the cam filter. */ 2039 vge_cam_clear(sc); 2040 2041 /* Init the multicast filter. */ 2042 vge_setmulti(sc); 2043 2044 /* Enable flow control */ 2045 2046 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 2047 2048 /* Enable jumbo frame reception (if desired) */ 2049 2050 /* Start the MAC. */ 2051 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 2052 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 2053 CSR_WRITE_1(sc, VGE_CRS0, 2054 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 2055 2056 /* 2057 * Configure one-shot timer for microsecond 2058 * resolution and load it for 500 usecs. 2059 */ 2060 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 2061 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 2062 2063 /* 2064 * Configure interrupt moderation for receive. Enable 2065 * the holdoff counter and load it, and set the RX 2066 * suppression count to the number of descriptors we 2067 * want to allow before triggering an interrupt. 2068 * The holdoff timer is in units of 20 usecs. 2069 */ 2070 2071#ifdef notyet 2072 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 2073 /* Select the interrupt holdoff timer page. */ 2074 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2075 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 2076 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 2077 2078 /* Enable use of the holdoff timer. */ 2079 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 2080 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 2081 2082 /* Select the RX suppression threshold page. */ 2083 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2084 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 2085 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 2086 2087 /* Restore the page select bits. */ 2088 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2089 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 2090#endif 2091 2092#ifdef DEVICE_POLLING 2093 /* 2094 * Disable interrupts if we are polling. 2095 */ 2096 if (ifp->if_capenable & IFCAP_POLLING) { 2097 CSR_WRITE_4(sc, VGE_IMR, 0); 2098 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2099 } else /* otherwise ... */ 2100#endif 2101 { 2102 /* 2103 * Enable interrupts. 2104 */ 2105 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2106 CSR_WRITE_4(sc, VGE_ISR, 0); 2107 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2108 } 2109 2110 mii_mediachg(mii); 2111 2112 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2113 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2114 callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc); 2115 2116 sc->vge_link = 0; 2117} 2118 2119/* 2120 * Set media options. 2121 */ 2122static int 2123vge_ifmedia_upd(struct ifnet *ifp) 2124{ 2125 struct vge_softc *sc; 2126 struct mii_data *mii; 2127 2128 sc = ifp->if_softc; 2129 VGE_LOCK(sc); 2130 mii = device_get_softc(sc->vge_miibus); 2131 mii_mediachg(mii); 2132 VGE_UNLOCK(sc); 2133 2134 return (0); 2135} 2136 2137/* 2138 * Report current media status. 2139 */ 2140static void 2141vge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2142{ 2143 struct vge_softc *sc; 2144 struct mii_data *mii; 2145 2146 sc = ifp->if_softc; 2147 mii = device_get_softc(sc->vge_miibus); 2148 2149 VGE_LOCK(sc); 2150 mii_pollstat(mii); 2151 VGE_UNLOCK(sc); 2152 ifmr->ifm_active = mii->mii_media_active; 2153 ifmr->ifm_status = mii->mii_media_status; 2154} 2155 2156static void 2157vge_miibus_statchg(device_t dev) 2158{ 2159 struct vge_softc *sc; 2160 struct mii_data *mii; 2161 struct ifmedia_entry *ife; 2162 2163 sc = device_get_softc(dev); 2164 mii = device_get_softc(sc->vge_miibus); 2165 ife = mii->mii_media.ifm_cur; 2166 2167 /* 2168 * If the user manually selects a media mode, we need to turn 2169 * on the forced MAC mode bit in the DIAGCTL register. If the 2170 * user happens to choose a full duplex mode, we also need to 2171 * set the 'force full duplex' bit. This applies only to 2172 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2173 * mode is disabled, and in 1000baseT mode, full duplex is 2174 * always implied, so we turn on the forced mode bit but leave 2175 * the FDX bit cleared. 2176 */ 2177 2178 switch (IFM_SUBTYPE(ife->ifm_media)) { 2179 case IFM_AUTO: 2180 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2181 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2182 break; 2183 case IFM_1000_T: 2184 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2185 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2186 break; 2187 case IFM_100_TX: 2188 case IFM_10_T: 2189 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2190 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2191 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2192 } else { 2193 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2194 } 2195 break; 2196 default: 2197 device_printf(dev, "unknown media type: %x\n", 2198 IFM_SUBTYPE(ife->ifm_media)); 2199 break; 2200 } 2201} 2202 2203static int 2204vge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2205{ 2206 struct vge_softc *sc = ifp->if_softc; 2207 struct ifreq *ifr = (struct ifreq *) data; 2208 struct mii_data *mii; 2209 int error = 0; 2210 2211 switch (command) { 2212 case SIOCSIFMTU: 2213 if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2214 error = EINVAL; 2215 ifp->if_mtu = ifr->ifr_mtu; 2216 break; 2217 case SIOCSIFFLAGS: 2218 VGE_LOCK(sc); 2219 if (ifp->if_flags & IFF_UP) { 2220 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2221 ifp->if_flags & IFF_PROMISC && 2222 !(sc->vge_if_flags & IFF_PROMISC)) { 2223 CSR_SETBIT_1(sc, VGE_RXCTL, 2224 VGE_RXCTL_RX_PROMISC); 2225 vge_setmulti(sc); 2226 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2227 !(ifp->if_flags & IFF_PROMISC) && 2228 sc->vge_if_flags & IFF_PROMISC) { 2229 CSR_CLRBIT_1(sc, VGE_RXCTL, 2230 VGE_RXCTL_RX_PROMISC); 2231 vge_setmulti(sc); 2232 } else 2233 vge_init_locked(sc); 2234 } else { 2235 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2236 vge_stop(sc); 2237 } 2238 sc->vge_if_flags = ifp->if_flags; 2239 VGE_UNLOCK(sc); 2240 break; 2241 case SIOCADDMULTI: 2242 case SIOCDELMULTI: 2243 VGE_LOCK(sc); 2244 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2245 vge_setmulti(sc); 2246 VGE_UNLOCK(sc); 2247 break; 2248 case SIOCGIFMEDIA: 2249 case SIOCSIFMEDIA: 2250 mii = device_get_softc(sc->vge_miibus); 2251 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2252 break; 2253 case SIOCSIFCAP: 2254 { 2255 int mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2256#ifdef DEVICE_POLLING 2257 if (mask & IFCAP_POLLING) { 2258 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2259 error = ether_poll_register(vge_poll, ifp); 2260 if (error) 2261 return(error); 2262 VGE_LOCK(sc); 2263 /* Disable interrupts */ 2264 CSR_WRITE_4(sc, VGE_IMR, 0); 2265 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2266 ifp->if_capenable |= IFCAP_POLLING; 2267 VGE_UNLOCK(sc); 2268 } else { 2269 error = ether_poll_deregister(ifp); 2270 /* Enable interrupts. */ 2271 VGE_LOCK(sc); 2272 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2273 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2274 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2275 ifp->if_capenable &= ~IFCAP_POLLING; 2276 VGE_UNLOCK(sc); 2277 } 2278 } 2279#endif /* DEVICE_POLLING */ 2280 VGE_LOCK(sc); 2281 if ((mask & IFCAP_TXCSUM) != 0 && 2282 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2283 ifp->if_capenable ^= IFCAP_TXCSUM; 2284 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2285 ifp->if_hwassist |= VGE_CSUM_FEATURES; 2286 else 2287 ifp->if_hwassist &= ~VGE_CSUM_FEATURES; 2288 } 2289 if ((mask & IFCAP_RXCSUM) != 0 && 2290 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 2291 ifp->if_capenable ^= IFCAP_RXCSUM; 2292 VGE_UNLOCK(sc); 2293 } 2294 break; 2295 default: 2296 error = ether_ioctl(ifp, command, data); 2297 break; 2298 } 2299 2300 return (error); 2301} 2302 2303static void 2304vge_watchdog(void *arg) 2305{ 2306 struct vge_softc *sc; 2307 struct ifnet *ifp; 2308 2309 sc = arg; 2310 VGE_LOCK_ASSERT(sc); 2311 callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc); 2312 if (sc->vge_timer == 0 || --sc->vge_timer > 0) 2313 return; 2314 2315 ifp = sc->vge_ifp; 2316 if_printf(ifp, "watchdog timeout\n"); 2317 ifp->if_oerrors++; 2318 2319 vge_txeof(sc); 2320 vge_rxeof(sc, VGE_RX_DESC_CNT); 2321 2322 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2323 vge_init_locked(sc); 2324} 2325 2326/* 2327 * Stop the adapter and free any mbufs allocated to the 2328 * RX and TX lists. 2329 */ 2330static void 2331vge_stop(struct vge_softc *sc) 2332{ 2333 struct ifnet *ifp; 2334 2335 VGE_LOCK_ASSERT(sc); 2336 ifp = sc->vge_ifp; 2337 sc->vge_timer = 0; 2338 callout_stop(&sc->vge_watchdog); 2339 2340 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2341 2342 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2343 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2344 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2345 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2346 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2347 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2348 2349 VGE_CHAIN_RESET(sc); 2350 vge_txeof(sc); 2351 vge_freebufs(sc); 2352} 2353 2354/* 2355 * Device suspend routine. Stop the interface and save some PCI 2356 * settings in case the BIOS doesn't restore them properly on 2357 * resume. 2358 */ 2359static int 2360vge_suspend(device_t dev) 2361{ 2362 struct vge_softc *sc; 2363 2364 sc = device_get_softc(dev); 2365 2366 VGE_LOCK(sc); 2367 vge_stop(sc); 2368 2369 sc->suspended = 1; 2370 VGE_UNLOCK(sc); 2371 2372 return (0); 2373} 2374 2375/* 2376 * Device resume routine. Restore some PCI settings in case the BIOS 2377 * doesn't, re-enable busmastering, and restart the interface if 2378 * appropriate. 2379 */ 2380static int 2381vge_resume(device_t dev) 2382{ 2383 struct vge_softc *sc; 2384 struct ifnet *ifp; 2385 2386 sc = device_get_softc(dev); 2387 ifp = sc->vge_ifp; 2388 2389 /* reenable busmastering */ 2390 pci_enable_busmaster(dev); 2391 pci_enable_io(dev, SYS_RES_MEMORY); 2392 2393 /* reinitialize interface if necessary */ 2394 VGE_LOCK(sc); 2395 if (ifp->if_flags & IFF_UP) { 2396 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2397 vge_init_locked(sc); 2398 } 2399 sc->suspended = 0; 2400 VGE_UNLOCK(sc); 2401 2402 return (0); 2403} 2404 2405/* 2406 * Stop all chip I/O so that the kernel's probe routines don't 2407 * get confused by errant DMAs when rebooting. 2408 */ 2409static int 2410vge_shutdown(device_t dev) 2411{ 2412 struct vge_softc *sc; 2413 2414 sc = device_get_softc(dev); 2415 2416 VGE_LOCK(sc); 2417 vge_stop(sc); 2418 VGE_UNLOCK(sc); 2419 2420 return (0); 2421} 2422