if_vge.c revision 199414
1/*- 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/vge/if_vge.c 199414 2009-11-17 18:22:14Z jhb $"); 35 36/* 37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 46 * combines a tri-speed ethernet MAC and PHY, with the following 47 * features: 48 * 49 * o Jumbo frame support up to 16K 50 * o Transmit and receive flow control 51 * o IPv4 checksum offload 52 * o VLAN tag insertion and stripping 53 * o TCP large send 54 * o 64-bit multicast hash table filter 55 * o 64 entry CAM filter 56 * o 16K RX FIFO and 48K TX FIFO memory 57 * o Interrupt moderation 58 * 59 * The VT6122 supports up to four transmit DMA queues. The descriptors 60 * in the transmit ring can address up to 7 data fragments; frames which 61 * span more than 7 data buffers must be coalesced, but in general the 62 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 63 * long. The receive descriptors address only a single buffer. 64 * 65 * There are two peculiar design issues with the VT6122. One is that 66 * receive data buffers must be aligned on a 32-bit boundary. This is 67 * not a problem where the VT6122 is used as a LOM device in x86-based 68 * systems, but on architectures that generate unaligned access traps, we 69 * have to do some copying. 70 * 71 * The other issue has to do with the way 64-bit addresses are handled. 72 * The DMA descriptors only allow you to specify 48 bits of addressing 73 * information. The remaining 16 bits are specified using one of the 74 * I/O registers. If you only have a 32-bit system, then this isn't 75 * an issue, but if you have a 64-bit system and more than 4GB of 76 * memory, you must have to make sure your network data buffers reside 77 * in the same 48-bit 'segment.' 78 * 79 * Special thanks to Ryan Fu at VIA Networking for providing documentation 80 * and sample NICs for testing. 81 */ 82 83#ifdef HAVE_KERNEL_OPTION_HEADERS 84#include "opt_device_polling.h" 85#endif 86 87#include <sys/param.h> 88#include <sys/endian.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/module.h> 94#include <sys/kernel.h> 95#include <sys/socket.h> 96#include <sys/taskqueue.h> 97 98#include <net/if.h> 99#include <net/if_arp.h> 100#include <net/ethernet.h> 101#include <net/if_dl.h> 102#include <net/if_media.h> 103#include <net/if_types.h> 104#include <net/if_vlan_var.h> 105 106#include <net/bpf.h> 107 108#include <machine/bus.h> 109#include <machine/resource.h> 110#include <sys/bus.h> 111#include <sys/rman.h> 112 113#include <dev/mii/mii.h> 114#include <dev/mii/miivar.h> 115 116#include <dev/pci/pcireg.h> 117#include <dev/pci/pcivar.h> 118 119MODULE_DEPEND(vge, pci, 1, 1, 1); 120MODULE_DEPEND(vge, ether, 1, 1, 1); 121MODULE_DEPEND(vge, miibus, 1, 1, 1); 122 123/* "device miibus" required. See GENERIC if you get errors here. */ 124#include "miibus_if.h" 125 126#include <dev/vge/if_vgereg.h> 127#include <dev/vge/if_vgevar.h> 128 129#define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 130 131/* 132 * Various supported device vendors/types and their names. 133 */ 134static struct vge_type vge_devs[] = { 135 { VIA_VENDORID, VIA_DEVICEID_61XX, 136 "VIA Networking Gigabit Ethernet" }, 137 { 0, 0, NULL } 138}; 139 140static int vge_probe (device_t); 141static int vge_attach (device_t); 142static int vge_detach (device_t); 143 144static int vge_encap (struct vge_softc *, struct mbuf *, int); 145 146static void vge_dma_map_addr (void *, bus_dma_segment_t *, int, int); 147static void vge_dma_map_rx_desc (void *, bus_dma_segment_t *, int, 148 bus_size_t, int); 149static void vge_dma_map_tx_desc (void *, bus_dma_segment_t *, int, 150 bus_size_t, int); 151static int vge_allocmem (device_t, struct vge_softc *); 152static int vge_newbuf (struct vge_softc *, int, struct mbuf *); 153static int vge_rx_list_init (struct vge_softc *); 154static int vge_tx_list_init (struct vge_softc *); 155#ifdef VGE_FIXUP_RX 156static __inline void vge_fixup_rx 157 (struct mbuf *); 158#endif 159static int vge_rxeof (struct vge_softc *); 160static void vge_txeof (struct vge_softc *); 161static void vge_intr (void *); 162static void vge_tick (void *); 163static void vge_tx_task (void *, int); 164static void vge_start (struct ifnet *); 165static int vge_ioctl (struct ifnet *, u_long, caddr_t); 166static void vge_init (void *); 167static void vge_stop (struct vge_softc *); 168static void vge_watchdog (struct ifnet *); 169static int vge_suspend (device_t); 170static int vge_resume (device_t); 171static int vge_shutdown (device_t); 172static int vge_ifmedia_upd (struct ifnet *); 173static void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 174 175#ifdef VGE_EEPROM 176static void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 177#endif 178static void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 179 180static void vge_miipoll_start (struct vge_softc *); 181static void vge_miipoll_stop (struct vge_softc *); 182static int vge_miibus_readreg (device_t, int, int); 183static int vge_miibus_writereg (device_t, int, int, int); 184static void vge_miibus_statchg (device_t); 185 186static void vge_cam_clear (struct vge_softc *); 187static int vge_cam_set (struct vge_softc *, uint8_t *); 188static void vge_setmulti (struct vge_softc *); 189static void vge_reset (struct vge_softc *); 190 191#define VGE_PCI_LOIO 0x10 192#define VGE_PCI_LOMEM 0x14 193 194static device_method_t vge_methods[] = { 195 /* Device interface */ 196 DEVMETHOD(device_probe, vge_probe), 197 DEVMETHOD(device_attach, vge_attach), 198 DEVMETHOD(device_detach, vge_detach), 199 DEVMETHOD(device_suspend, vge_suspend), 200 DEVMETHOD(device_resume, vge_resume), 201 DEVMETHOD(device_shutdown, vge_shutdown), 202 203 /* bus interface */ 204 DEVMETHOD(bus_print_child, bus_generic_print_child), 205 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 206 207 /* MII interface */ 208 DEVMETHOD(miibus_readreg, vge_miibus_readreg), 209 DEVMETHOD(miibus_writereg, vge_miibus_writereg), 210 DEVMETHOD(miibus_statchg, vge_miibus_statchg), 211 212 { 0, 0 } 213}; 214 215static driver_t vge_driver = { 216 "vge", 217 vge_methods, 218 sizeof(struct vge_softc) 219}; 220 221static devclass_t vge_devclass; 222 223DRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0); 224DRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0); 225 226#ifdef VGE_EEPROM 227/* 228 * Read a word of data stored in the EEPROM at address 'addr.' 229 */ 230static void 231vge_eeprom_getword(sc, addr, dest) 232 struct vge_softc *sc; 233 int addr; 234 u_int16_t *dest; 235{ 236 register int i; 237 u_int16_t word = 0; 238 239 /* 240 * Enter EEPROM embedded programming mode. In order to 241 * access the EEPROM at all, we first have to set the 242 * EELOAD bit in the CHIPCFG2 register. 243 */ 244 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 245 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 246 247 /* Select the address of the word we want to read */ 248 CSR_WRITE_1(sc, VGE_EEADDR, addr); 249 250 /* Issue read command */ 251 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 252 253 /* Wait for the done bit to be set. */ 254 for (i = 0; i < VGE_TIMEOUT; i++) { 255 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 256 break; 257 } 258 259 if (i == VGE_TIMEOUT) { 260 device_printf(sc->vge_dev, "EEPROM read timed out\n"); 261 *dest = 0; 262 return; 263 } 264 265 /* Read the result */ 266 word = CSR_READ_2(sc, VGE_EERDDAT); 267 268 /* Turn off EEPROM access mode. */ 269 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 270 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 271 272 *dest = word; 273 274 return; 275} 276#endif 277 278/* 279 * Read a sequence of words from the EEPROM. 280 */ 281static void 282vge_read_eeprom(sc, dest, off, cnt, swap) 283 struct vge_softc *sc; 284 caddr_t dest; 285 int off; 286 int cnt; 287 int swap; 288{ 289 int i; 290#ifdef VGE_EEPROM 291 u_int16_t word = 0, *ptr; 292 293 for (i = 0; i < cnt; i++) { 294 vge_eeprom_getword(sc, off + i, &word); 295 ptr = (u_int16_t *)(dest + (i * 2)); 296 if (swap) 297 *ptr = ntohs(word); 298 else 299 *ptr = word; 300 } 301#else 302 for (i = 0; i < ETHER_ADDR_LEN; i++) 303 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 304#endif 305} 306 307static void 308vge_miipoll_stop(sc) 309 struct vge_softc *sc; 310{ 311 int i; 312 313 CSR_WRITE_1(sc, VGE_MIICMD, 0); 314 315 for (i = 0; i < VGE_TIMEOUT; i++) { 316 DELAY(1); 317 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 318 break; 319 } 320 321 if (i == VGE_TIMEOUT) 322 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 323 324 return; 325} 326 327static void 328vge_miipoll_start(sc) 329 struct vge_softc *sc; 330{ 331 int i; 332 333 /* First, make sure we're idle. */ 334 335 CSR_WRITE_1(sc, VGE_MIICMD, 0); 336 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 337 338 for (i = 0; i < VGE_TIMEOUT; i++) { 339 DELAY(1); 340 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 341 break; 342 } 343 344 if (i == VGE_TIMEOUT) { 345 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 346 return; 347 } 348 349 /* Now enable auto poll mode. */ 350 351 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 352 353 /* And make sure it started. */ 354 355 for (i = 0; i < VGE_TIMEOUT; i++) { 356 DELAY(1); 357 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 358 break; 359 } 360 361 if (i == VGE_TIMEOUT) 362 device_printf(sc->vge_dev, "failed to start MII autopoll\n"); 363 364 return; 365} 366 367static int 368vge_miibus_readreg(dev, phy, reg) 369 device_t dev; 370 int phy, reg; 371{ 372 struct vge_softc *sc; 373 int i; 374 u_int16_t rval = 0; 375 376 sc = device_get_softc(dev); 377 378 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 379 return(0); 380 381 VGE_LOCK(sc); 382 vge_miipoll_stop(sc); 383 384 /* Specify the register we want to read. */ 385 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 386 387 /* Issue read command. */ 388 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 389 390 /* Wait for the read command bit to self-clear. */ 391 for (i = 0; i < VGE_TIMEOUT; i++) { 392 DELAY(1); 393 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 394 break; 395 } 396 397 if (i == VGE_TIMEOUT) 398 device_printf(sc->vge_dev, "MII read timed out\n"); 399 else 400 rval = CSR_READ_2(sc, VGE_MIIDATA); 401 402 vge_miipoll_start(sc); 403 VGE_UNLOCK(sc); 404 405 return (rval); 406} 407 408static int 409vge_miibus_writereg(dev, phy, reg, data) 410 device_t dev; 411 int phy, reg, data; 412{ 413 struct vge_softc *sc; 414 int i, rval = 0; 415 416 sc = device_get_softc(dev); 417 418 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 419 return(0); 420 421 VGE_LOCK(sc); 422 vge_miipoll_stop(sc); 423 424 /* Specify the register we want to write. */ 425 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 426 427 /* Specify the data we want to write. */ 428 CSR_WRITE_2(sc, VGE_MIIDATA, data); 429 430 /* Issue write command. */ 431 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 432 433 /* Wait for the write command bit to self-clear. */ 434 for (i = 0; i < VGE_TIMEOUT; i++) { 435 DELAY(1); 436 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 437 break; 438 } 439 440 if (i == VGE_TIMEOUT) { 441 device_printf(sc->vge_dev, "MII write timed out\n"); 442 rval = EIO; 443 } 444 445 vge_miipoll_start(sc); 446 VGE_UNLOCK(sc); 447 448 return (rval); 449} 450 451static void 452vge_cam_clear(sc) 453 struct vge_softc *sc; 454{ 455 int i; 456 457 /* 458 * Turn off all the mask bits. This tells the chip 459 * that none of the entries in the CAM filter are valid. 460 * desired entries will be enabled as we fill the filter in. 461 */ 462 463 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 464 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 465 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 466 for (i = 0; i < 8; i++) 467 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 468 469 /* Clear the VLAN filter too. */ 470 471 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 472 for (i = 0; i < 8; i++) 473 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 474 475 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 476 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 477 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 478 479 sc->vge_camidx = 0; 480 481 return; 482} 483 484static int 485vge_cam_set(sc, addr) 486 struct vge_softc *sc; 487 uint8_t *addr; 488{ 489 int i, error = 0; 490 491 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 492 return(ENOSPC); 493 494 /* Select the CAM data page. */ 495 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 496 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 497 498 /* Set the filter entry we want to update and enable writing. */ 499 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 500 501 /* Write the address to the CAM registers */ 502 for (i = 0; i < ETHER_ADDR_LEN; i++) 503 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 504 505 /* Issue a write command. */ 506 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 507 508 /* Wake for it to clear. */ 509 for (i = 0; i < VGE_TIMEOUT; i++) { 510 DELAY(1); 511 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 512 break; 513 } 514 515 if (i == VGE_TIMEOUT) { 516 device_printf(sc->vge_dev, "setting CAM filter failed\n"); 517 error = EIO; 518 goto fail; 519 } 520 521 /* Select the CAM mask page. */ 522 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 523 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 524 525 /* Set the mask bit that enables this filter. */ 526 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 527 1<<(sc->vge_camidx & 7)); 528 529 sc->vge_camidx++; 530 531fail: 532 /* Turn off access to CAM. */ 533 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 534 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 535 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 536 537 return (error); 538} 539 540/* 541 * Program the multicast filter. We use the 64-entry CAM filter 542 * for perfect filtering. If there's more than 64 multicast addresses, 543 * we use the hash filter insted. 544 */ 545static void 546vge_setmulti(sc) 547 struct vge_softc *sc; 548{ 549 struct ifnet *ifp; 550 int error = 0/*, h = 0*/; 551 struct ifmultiaddr *ifma; 552 u_int32_t h, hashes[2] = { 0, 0 }; 553 554 ifp = sc->vge_ifp; 555 556 /* First, zot all the multicast entries. */ 557 vge_cam_clear(sc); 558 CSR_WRITE_4(sc, VGE_MAR0, 0); 559 CSR_WRITE_4(sc, VGE_MAR1, 0); 560 561 /* 562 * If the user wants allmulti or promisc mode, enable reception 563 * of all multicast frames. 564 */ 565 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 566 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 567 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 568 return; 569 } 570 571 /* Now program new ones */ 572 if_maddr_rlock(ifp); 573 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 574 if (ifma->ifma_addr->sa_family != AF_LINK) 575 continue; 576 error = vge_cam_set(sc, 577 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 578 if (error) 579 break; 580 } 581 582 /* If there were too many addresses, use the hash filter. */ 583 if (error) { 584 vge_cam_clear(sc); 585 586 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 587 if (ifma->ifma_addr->sa_family != AF_LINK) 588 continue; 589 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 590 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 591 if (h < 32) 592 hashes[0] |= (1 << h); 593 else 594 hashes[1] |= (1 << (h - 32)); 595 } 596 597 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 598 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 599 } 600 if_maddr_runlock(ifp); 601 602 return; 603} 604 605static void 606vge_reset(sc) 607 struct vge_softc *sc; 608{ 609 register int i; 610 611 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 612 613 for (i = 0; i < VGE_TIMEOUT; i++) { 614 DELAY(5); 615 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 616 break; 617 } 618 619 if (i == VGE_TIMEOUT) { 620 device_printf(sc->vge_dev, "soft reset timed out"); 621 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 622 DELAY(2000); 623 } 624 625 DELAY(5000); 626 627 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 628 629 for (i = 0; i < VGE_TIMEOUT; i++) { 630 DELAY(5); 631 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 632 break; 633 } 634 635 if (i == VGE_TIMEOUT) { 636 device_printf(sc->vge_dev, "EEPROM reload timed out\n"); 637 return; 638 } 639 640 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 641 642 return; 643} 644 645/* 646 * Probe for a VIA gigabit chip. Check the PCI vendor and device 647 * IDs against our list and return a device name if we find a match. 648 */ 649static int 650vge_probe(dev) 651 device_t dev; 652{ 653 struct vge_type *t; 654 655 t = vge_devs; 656 657 while (t->vge_name != NULL) { 658 if ((pci_get_vendor(dev) == t->vge_vid) && 659 (pci_get_device(dev) == t->vge_did)) { 660 device_set_desc(dev, t->vge_name); 661 return (BUS_PROBE_DEFAULT); 662 } 663 t++; 664 } 665 666 return (ENXIO); 667} 668 669static void 670vge_dma_map_rx_desc(arg, segs, nseg, mapsize, error) 671 void *arg; 672 bus_dma_segment_t *segs; 673 int nseg; 674 bus_size_t mapsize; 675 int error; 676{ 677 678 struct vge_dmaload_arg *ctx; 679 struct vge_rx_desc *d = NULL; 680 681 if (error) 682 return; 683 684 ctx = arg; 685 686 /* Signal error to caller if there's too many segments */ 687 if (nseg > ctx->vge_maxsegs) { 688 ctx->vge_maxsegs = 0; 689 return; 690 } 691 692 /* 693 * Map the segment array into descriptors. 694 */ 695 696 d = &ctx->sc->vge_ldata.vge_rx_list[ctx->vge_idx]; 697 698 /* If this descriptor is still owned by the chip, bail. */ 699 700 if (le32toh(d->vge_sts) & VGE_RDSTS_OWN) { 701 device_printf(ctx->sc->vge_dev, 702 "tried to map busy descriptor\n"); 703 ctx->vge_maxsegs = 0; 704 return; 705 } 706 707 d->vge_buflen = htole16(VGE_BUFLEN(segs[0].ds_len) | VGE_RXDESC_I); 708 d->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 709 d->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 710 d->vge_sts = 0; 711 d->vge_ctl = 0; 712 713 ctx->vge_maxsegs = 1; 714 715 return; 716} 717 718static void 719vge_dma_map_tx_desc(arg, segs, nseg, mapsize, error) 720 void *arg; 721 bus_dma_segment_t *segs; 722 int nseg; 723 bus_size_t mapsize; 724 int error; 725{ 726 struct vge_dmaload_arg *ctx; 727 struct vge_tx_desc *d = NULL; 728 struct vge_tx_frag *f; 729 int i = 0; 730 731 if (error) 732 return; 733 734 ctx = arg; 735 736 /* Signal error to caller if there's too many segments */ 737 if (nseg > ctx->vge_maxsegs) { 738 ctx->vge_maxsegs = 0; 739 return; 740 } 741 742 /* Map the segment array into descriptors. */ 743 744 d = &ctx->sc->vge_ldata.vge_tx_list[ctx->vge_idx]; 745 746 /* If this descriptor is still owned by the chip, bail. */ 747 748 if (le32toh(d->vge_sts) & VGE_TDSTS_OWN) { 749 ctx->vge_maxsegs = 0; 750 return; 751 } 752 753 for (i = 0; i < nseg; i++) { 754 f = &d->vge_frag[i]; 755 f->vge_buflen = htole16(VGE_BUFLEN(segs[i].ds_len)); 756 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[i].ds_addr)); 757 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[i].ds_addr) & 0xFFFF); 758 } 759 760 /* Argh. This chip does not autopad short frames */ 761 762 if (ctx->vge_m0->m_pkthdr.len < VGE_MIN_FRAMELEN) { 763 f = &d->vge_frag[i]; 764 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 765 ctx->vge_m0->m_pkthdr.len)); 766 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 767 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 768 ctx->vge_m0->m_pkthdr.len = VGE_MIN_FRAMELEN; 769 i++; 770 } 771 772 /* 773 * When telling the chip how many segments there are, we 774 * must use nsegs + 1 instead of just nsegs. Darned if I 775 * know why. 776 */ 777 i++; 778 779 d->vge_sts = ctx->vge_m0->m_pkthdr.len << 16; 780 d->vge_ctl = ctx->vge_flags|(i << 28)|VGE_TD_LS_NORM; 781 782 if (ctx->vge_m0->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 783 d->vge_ctl |= VGE_TDCTL_JUMBO; 784 785 ctx->vge_maxsegs = nseg; 786 787 return; 788} 789 790/* 791 * Map a single buffer address. 792 */ 793 794static void 795vge_dma_map_addr(arg, segs, nseg, error) 796 void *arg; 797 bus_dma_segment_t *segs; 798 int nseg; 799 int error; 800{ 801 bus_addr_t *addr; 802 803 if (error) 804 return; 805 806 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 807 addr = arg; 808 *addr = segs->ds_addr; 809 810 return; 811} 812 813static int 814vge_allocmem(dev, sc) 815 device_t dev; 816 struct vge_softc *sc; 817{ 818 int error; 819 int nseg; 820 int i; 821 822 /* 823 * Allocate map for RX mbufs. 824 */ 825 nseg = 32; 826 error = bus_dma_tag_create(sc->vge_parent_tag, ETHER_ALIGN, 0, 827 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 828 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 829 NULL, NULL, &sc->vge_ldata.vge_mtag); 830 if (error) { 831 device_printf(dev, "could not allocate dma tag\n"); 832 return (ENOMEM); 833 } 834 835 /* 836 * Allocate map for TX descriptor list. 837 */ 838 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 839 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 840 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 841 NULL, NULL, &sc->vge_ldata.vge_tx_list_tag); 842 if (error) { 843 device_printf(dev, "could not allocate dma tag\n"); 844 return (ENOMEM); 845 } 846 847 /* Allocate DMA'able memory for the TX ring */ 848 849 error = bus_dmamem_alloc(sc->vge_ldata.vge_tx_list_tag, 850 (void **)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 851 &sc->vge_ldata.vge_tx_list_map); 852 if (error) 853 return (ENOMEM); 854 855 /* Load the map for the TX ring. */ 856 857 error = bus_dmamap_load(sc->vge_ldata.vge_tx_list_tag, 858 sc->vge_ldata.vge_tx_list_map, sc->vge_ldata.vge_tx_list, 859 VGE_TX_LIST_SZ, vge_dma_map_addr, 860 &sc->vge_ldata.vge_tx_list_addr, BUS_DMA_NOWAIT); 861 862 /* Create DMA maps for TX buffers */ 863 864 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 865 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 866 &sc->vge_ldata.vge_tx_dmamap[i]); 867 if (error) { 868 device_printf(dev, "can't create DMA map for TX\n"); 869 return (ENOMEM); 870 } 871 } 872 873 /* 874 * Allocate map for RX descriptor list. 875 */ 876 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 877 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 878 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 879 NULL, NULL, &sc->vge_ldata.vge_rx_list_tag); 880 if (error) { 881 device_printf(dev, "could not allocate dma tag\n"); 882 return (ENOMEM); 883 } 884 885 /* Allocate DMA'able memory for the RX ring */ 886 887 error = bus_dmamem_alloc(sc->vge_ldata.vge_rx_list_tag, 888 (void **)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 889 &sc->vge_ldata.vge_rx_list_map); 890 if (error) 891 return (ENOMEM); 892 893 /* Load the map for the RX ring. */ 894 895 error = bus_dmamap_load(sc->vge_ldata.vge_rx_list_tag, 896 sc->vge_ldata.vge_rx_list_map, sc->vge_ldata.vge_rx_list, 897 VGE_TX_LIST_SZ, vge_dma_map_addr, 898 &sc->vge_ldata.vge_rx_list_addr, BUS_DMA_NOWAIT); 899 900 /* Create DMA maps for RX buffers */ 901 902 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 903 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 904 &sc->vge_ldata.vge_rx_dmamap[i]); 905 if (error) { 906 device_printf(dev, "can't create DMA map for RX\n"); 907 return (ENOMEM); 908 } 909 } 910 911 return (0); 912} 913 914/* 915 * Attach the interface. Allocate softc structures, do ifmedia 916 * setup and ethernet/BPF attach. 917 */ 918static int 919vge_attach(dev) 920 device_t dev; 921{ 922 u_char eaddr[ETHER_ADDR_LEN]; 923 struct vge_softc *sc; 924 struct ifnet *ifp; 925 int unit, error = 0, rid; 926 927 sc = device_get_softc(dev); 928 unit = device_get_unit(dev); 929 sc->vge_dev = dev; 930 931 mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 932 MTX_DEF | MTX_RECURSE); 933 /* 934 * Map control/status registers. 935 */ 936 pci_enable_busmaster(dev); 937 938 rid = VGE_PCI_LOMEM; 939 sc->vge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 940 0, ~0, 1, RF_ACTIVE); 941 942 if (sc->vge_res == NULL) { 943 printf ("vge%d: couldn't map ports/memory\n", unit); 944 error = ENXIO; 945 goto fail; 946 } 947 948 /* Allocate interrupt */ 949 rid = 0; 950 sc->vge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 951 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE); 952 953 if (sc->vge_irq == NULL) { 954 printf("vge%d: couldn't map interrupt\n", unit); 955 error = ENXIO; 956 goto fail; 957 } 958 959 /* Reset the adapter. */ 960 vge_reset(sc); 961 962 /* 963 * Get station address from the EEPROM. 964 */ 965 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 966 967 /* 968 * Allocate the parent bus DMA tag appropriate for PCI. 969 */ 970#define VGE_NSEG_NEW 32 971 error = bus_dma_tag_create(NULL, /* parent */ 972 1, 0, /* alignment, boundary */ 973 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 974 BUS_SPACE_MAXADDR, /* highaddr */ 975 NULL, NULL, /* filter, filterarg */ 976 MAXBSIZE, VGE_NSEG_NEW, /* maxsize, nsegments */ 977 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 978 BUS_DMA_ALLOCNOW, /* flags */ 979 NULL, NULL, /* lockfunc, lockarg */ 980 &sc->vge_parent_tag); 981 if (error) 982 goto fail; 983 984 error = vge_allocmem(dev, sc); 985 986 if (error) 987 goto fail; 988 989 ifp = sc->vge_ifp = if_alloc(IFT_ETHER); 990 if (ifp == NULL) { 991 device_printf(dev, "can not if_alloc()\n"); 992 error = ENOSPC; 993 goto fail; 994 } 995 996 /* Do MII setup */ 997 if (mii_phy_probe(dev, &sc->vge_miibus, 998 vge_ifmedia_upd, vge_ifmedia_sts)) { 999 device_printf(dev, "MII without any phy!\n"); 1000 error = ENXIO; 1001 goto fail; 1002 } 1003 1004 ifp->if_softc = sc; 1005 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1006 ifp->if_mtu = ETHERMTU; 1007 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1008 ifp->if_ioctl = vge_ioctl; 1009 ifp->if_capabilities = IFCAP_VLAN_MTU; 1010 ifp->if_start = vge_start; 1011 ifp->if_hwassist = VGE_CSUM_FEATURES; 1012 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1013 ifp->if_capenable = ifp->if_capabilities; 1014#ifdef DEVICE_POLLING 1015 ifp->if_capabilities |= IFCAP_POLLING; 1016#endif 1017 ifp->if_watchdog = vge_watchdog; 1018 ifp->if_init = vge_init; 1019 IFQ_SET_MAXLEN(&ifp->if_snd, VGE_IFQ_MAXLEN); 1020 ifp->if_snd.ifq_drv_maxlen = VGE_IFQ_MAXLEN; 1021 IFQ_SET_READY(&ifp->if_snd); 1022 1023 TASK_INIT(&sc->vge_txtask, 0, vge_tx_task, ifp); 1024 1025 /* 1026 * Call MI attach routine. 1027 */ 1028 ether_ifattach(ifp, eaddr); 1029 1030 /* Hook interrupt last to avoid having to lock softc */ 1031 error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE, 1032 NULL, vge_intr, sc, &sc->vge_intrhand); 1033 1034 if (error) { 1035 printf("vge%d: couldn't set up irq\n", unit); 1036 ether_ifdetach(ifp); 1037 goto fail; 1038 } 1039 1040fail: 1041 if (error) 1042 vge_detach(dev); 1043 1044 return (error); 1045} 1046 1047/* 1048 * Shutdown hardware and free up resources. This can be called any 1049 * time after the mutex has been initialized. It is called in both 1050 * the error case in attach and the normal detach case so it needs 1051 * to be careful about only freeing resources that have actually been 1052 * allocated. 1053 */ 1054static int 1055vge_detach(dev) 1056 device_t dev; 1057{ 1058 struct vge_softc *sc; 1059 struct ifnet *ifp; 1060 int i; 1061 1062 sc = device_get_softc(dev); 1063 KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized")); 1064 ifp = sc->vge_ifp; 1065 1066#ifdef DEVICE_POLLING 1067 if (ifp->if_capenable & IFCAP_POLLING) 1068 ether_poll_deregister(ifp); 1069#endif 1070 1071 /* These should only be active if attach succeeded */ 1072 if (device_is_attached(dev)) { 1073 vge_stop(sc); 1074 /* 1075 * Force off the IFF_UP flag here, in case someone 1076 * still had a BPF descriptor attached to this 1077 * interface. If they do, ether_ifattach() will cause 1078 * the BPF code to try and clear the promisc mode 1079 * flag, which will bubble down to vge_ioctl(), 1080 * which will try to call vge_init() again. This will 1081 * turn the NIC back on and restart the MII ticker, 1082 * which will panic the system when the kernel tries 1083 * to invoke the vge_tick() function that isn't there 1084 * anymore. 1085 */ 1086 ifp->if_flags &= ~IFF_UP; 1087 ether_ifdetach(ifp); 1088 } 1089 if (sc->vge_miibus) 1090 device_delete_child(dev, sc->vge_miibus); 1091 bus_generic_detach(dev); 1092 1093 if (sc->vge_intrhand) 1094 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); 1095 if (sc->vge_irq) 1096 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vge_irq); 1097 if (sc->vge_res) 1098 bus_release_resource(dev, SYS_RES_MEMORY, 1099 VGE_PCI_LOMEM, sc->vge_res); 1100 if (ifp) 1101 if_free(ifp); 1102 1103 /* Unload and free the RX DMA ring memory and map */ 1104 1105 if (sc->vge_ldata.vge_rx_list_tag) { 1106 bus_dmamap_unload(sc->vge_ldata.vge_rx_list_tag, 1107 sc->vge_ldata.vge_rx_list_map); 1108 bus_dmamem_free(sc->vge_ldata.vge_rx_list_tag, 1109 sc->vge_ldata.vge_rx_list, 1110 sc->vge_ldata.vge_rx_list_map); 1111 bus_dma_tag_destroy(sc->vge_ldata.vge_rx_list_tag); 1112 } 1113 1114 /* Unload and free the TX DMA ring memory and map */ 1115 1116 if (sc->vge_ldata.vge_tx_list_tag) { 1117 bus_dmamap_unload(sc->vge_ldata.vge_tx_list_tag, 1118 sc->vge_ldata.vge_tx_list_map); 1119 bus_dmamem_free(sc->vge_ldata.vge_tx_list_tag, 1120 sc->vge_ldata.vge_tx_list, 1121 sc->vge_ldata.vge_tx_list_map); 1122 bus_dma_tag_destroy(sc->vge_ldata.vge_tx_list_tag); 1123 } 1124 1125 /* Destroy all the RX and TX buffer maps */ 1126 1127 if (sc->vge_ldata.vge_mtag) { 1128 for (i = 0; i < VGE_TX_DESC_CNT; i++) 1129 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1130 sc->vge_ldata.vge_tx_dmamap[i]); 1131 for (i = 0; i < VGE_RX_DESC_CNT; i++) 1132 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1133 sc->vge_ldata.vge_rx_dmamap[i]); 1134 bus_dma_tag_destroy(sc->vge_ldata.vge_mtag); 1135 } 1136 1137 if (sc->vge_parent_tag) 1138 bus_dma_tag_destroy(sc->vge_parent_tag); 1139 1140 mtx_destroy(&sc->vge_mtx); 1141 1142 return (0); 1143} 1144 1145static int 1146vge_newbuf(sc, idx, m) 1147 struct vge_softc *sc; 1148 int idx; 1149 struct mbuf *m; 1150{ 1151 struct vge_dmaload_arg arg; 1152 struct mbuf *n = NULL; 1153 int i, error; 1154 1155 if (m == NULL) { 1156 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1157 if (n == NULL) 1158 return (ENOBUFS); 1159 m = n; 1160 } else 1161 m->m_data = m->m_ext.ext_buf; 1162 1163 1164#ifdef VGE_FIXUP_RX 1165 /* 1166 * This is part of an evil trick to deal with non-x86 platforms. 1167 * The VIA chip requires RX buffers to be aligned on 32-bit 1168 * boundaries, but that will hose non-x86 machines. To get around 1169 * this, we leave some empty space at the start of each buffer 1170 * and for non-x86 hosts, we copy the buffer back two bytes 1171 * to achieve word alignment. This is slightly more efficient 1172 * than allocating a new buffer, copying the contents, and 1173 * discarding the old buffer. 1174 */ 1175 m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_ETHER_ALIGN; 1176 m_adj(m, VGE_ETHER_ALIGN); 1177#else 1178 m->m_len = m->m_pkthdr.len = MCLBYTES; 1179#endif 1180 1181 arg.sc = sc; 1182 arg.vge_idx = idx; 1183 arg.vge_maxsegs = 1; 1184 arg.vge_flags = 0; 1185 1186 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, 1187 sc->vge_ldata.vge_rx_dmamap[idx], m, vge_dma_map_rx_desc, 1188 &arg, BUS_DMA_NOWAIT); 1189 if (error || arg.vge_maxsegs != 1) { 1190 if (n != NULL) 1191 m_freem(n); 1192 return (ENOMEM); 1193 } 1194 1195 /* 1196 * Note: the manual fails to document the fact that for 1197 * proper opration, the driver needs to replentish the RX 1198 * DMA ring 4 descriptors at a time (rather than one at a 1199 * time, like most chips). We can allocate the new buffers 1200 * but we should not set the OWN bits until we're ready 1201 * to hand back 4 of them in one shot. 1202 */ 1203 1204#define VGE_RXCHUNK 4 1205 sc->vge_rx_consumed++; 1206 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 1207 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 1208 sc->vge_ldata.vge_rx_list[i].vge_sts |= 1209 htole32(VGE_RDSTS_OWN); 1210 sc->vge_rx_consumed = 0; 1211 } 1212 1213 sc->vge_ldata.vge_rx_mbuf[idx] = m; 1214 1215 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1216 sc->vge_ldata.vge_rx_dmamap[idx], 1217 BUS_DMASYNC_PREREAD); 1218 1219 return (0); 1220} 1221 1222static int 1223vge_tx_list_init(sc) 1224 struct vge_softc *sc; 1225{ 1226 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 1227 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 1228 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 1229 1230 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1231 sc->vge_ldata.vge_tx_list_map, BUS_DMASYNC_PREWRITE); 1232 sc->vge_ldata.vge_tx_prodidx = 0; 1233 sc->vge_ldata.vge_tx_considx = 0; 1234 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 1235 1236 return (0); 1237} 1238 1239static int 1240vge_rx_list_init(sc) 1241 struct vge_softc *sc; 1242{ 1243 int i; 1244 1245 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 1246 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 1247 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 1248 1249 sc->vge_rx_consumed = 0; 1250 1251 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1252 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 1253 return (ENOBUFS); 1254 } 1255 1256 /* Flush the RX descriptors */ 1257 1258 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1259 sc->vge_ldata.vge_rx_list_map, 1260 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1261 1262 sc->vge_ldata.vge_rx_prodidx = 0; 1263 sc->vge_rx_consumed = 0; 1264 sc->vge_head = sc->vge_tail = NULL; 1265 1266 return (0); 1267} 1268 1269#ifdef VGE_FIXUP_RX 1270static __inline void 1271vge_fixup_rx(m) 1272 struct mbuf *m; 1273{ 1274 int i; 1275 uint16_t *src, *dst; 1276 1277 src = mtod(m, uint16_t *); 1278 dst = src - 1; 1279 1280 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1281 *dst++ = *src++; 1282 1283 m->m_data -= ETHER_ALIGN; 1284 1285 return; 1286} 1287#endif 1288 1289/* 1290 * RX handler. We support the reception of jumbo frames that have 1291 * been fragmented across multiple 2K mbuf cluster buffers. 1292 */ 1293static int 1294vge_rxeof(sc) 1295 struct vge_softc *sc; 1296{ 1297 struct mbuf *m; 1298 struct ifnet *ifp; 1299 int i, total_len; 1300 int lim = 0; 1301 struct vge_rx_desc *cur_rx; 1302 u_int32_t rxstat, rxctl; 1303 1304 VGE_LOCK_ASSERT(sc); 1305 ifp = sc->vge_ifp; 1306 i = sc->vge_ldata.vge_rx_prodidx; 1307 1308 /* Invalidate the descriptor memory */ 1309 1310 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1311 sc->vge_ldata.vge_rx_list_map, 1312 BUS_DMASYNC_POSTREAD); 1313 1314 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 1315 1316#ifdef DEVICE_POLLING 1317 if (ifp->if_capenable & IFCAP_POLLING) { 1318 if (sc->rxcycles <= 0) 1319 break; 1320 sc->rxcycles--; 1321 } 1322#endif 1323 1324 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1325 m = sc->vge_ldata.vge_rx_mbuf[i]; 1326 total_len = VGE_RXBYTES(cur_rx); 1327 rxstat = le32toh(cur_rx->vge_sts); 1328 rxctl = le32toh(cur_rx->vge_ctl); 1329 1330 /* Invalidate the RX mbuf and unload its map */ 1331 1332 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1333 sc->vge_ldata.vge_rx_dmamap[i], 1334 BUS_DMASYNC_POSTWRITE); 1335 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1336 sc->vge_ldata.vge_rx_dmamap[i]); 1337 1338 /* 1339 * If the 'start of frame' bit is set, this indicates 1340 * either the first fragment in a multi-fragment receive, 1341 * or an intermediate fragment. Either way, we want to 1342 * accumulate the buffers. 1343 */ 1344 if (rxstat & VGE_RXPKT_SOF) { 1345 m->m_len = MCLBYTES - VGE_ETHER_ALIGN; 1346 if (sc->vge_head == NULL) 1347 sc->vge_head = sc->vge_tail = m; 1348 else { 1349 m->m_flags &= ~M_PKTHDR; 1350 sc->vge_tail->m_next = m; 1351 sc->vge_tail = m; 1352 } 1353 vge_newbuf(sc, i, NULL); 1354 VGE_RX_DESC_INC(i); 1355 continue; 1356 } 1357 1358 /* 1359 * Bad/error frames will have the RXOK bit cleared. 1360 * However, there's one error case we want to allow: 1361 * if a VLAN tagged frame arrives and the chip can't 1362 * match it against the CAM filter, it considers this 1363 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1364 * We don't want to drop the frame though: our VLAN 1365 * filtering is done in software. 1366 */ 1367 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1368 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1369 ifp->if_ierrors++; 1370 /* 1371 * If this is part of a multi-fragment packet, 1372 * discard all the pieces. 1373 */ 1374 if (sc->vge_head != NULL) { 1375 m_freem(sc->vge_head); 1376 sc->vge_head = sc->vge_tail = NULL; 1377 } 1378 vge_newbuf(sc, i, m); 1379 VGE_RX_DESC_INC(i); 1380 continue; 1381 } 1382 1383 /* 1384 * If allocating a replacement mbuf fails, 1385 * reload the current one. 1386 */ 1387 1388 if (vge_newbuf(sc, i, NULL)) { 1389 ifp->if_ierrors++; 1390 if (sc->vge_head != NULL) { 1391 m_freem(sc->vge_head); 1392 sc->vge_head = sc->vge_tail = NULL; 1393 } 1394 vge_newbuf(sc, i, m); 1395 VGE_RX_DESC_INC(i); 1396 continue; 1397 } 1398 1399 VGE_RX_DESC_INC(i); 1400 1401 if (sc->vge_head != NULL) { 1402 m->m_len = total_len % (MCLBYTES - VGE_ETHER_ALIGN); 1403 /* 1404 * Special case: if there's 4 bytes or less 1405 * in this buffer, the mbuf can be discarded: 1406 * the last 4 bytes is the CRC, which we don't 1407 * care about anyway. 1408 */ 1409 if (m->m_len <= ETHER_CRC_LEN) { 1410 sc->vge_tail->m_len -= 1411 (ETHER_CRC_LEN - m->m_len); 1412 m_freem(m); 1413 } else { 1414 m->m_len -= ETHER_CRC_LEN; 1415 m->m_flags &= ~M_PKTHDR; 1416 sc->vge_tail->m_next = m; 1417 } 1418 m = sc->vge_head; 1419 sc->vge_head = sc->vge_tail = NULL; 1420 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1421 } else 1422 m->m_pkthdr.len = m->m_len = 1423 (total_len - ETHER_CRC_LEN); 1424 1425#ifdef VGE_FIXUP_RX 1426 vge_fixup_rx(m); 1427#endif 1428 ifp->if_ipackets++; 1429 m->m_pkthdr.rcvif = ifp; 1430 1431 /* Do RX checksumming if enabled */ 1432 if (ifp->if_capenable & IFCAP_RXCSUM) { 1433 1434 /* Check IP header checksum */ 1435 if (rxctl & VGE_RDCTL_IPPKT) 1436 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1437 if (rxctl & VGE_RDCTL_IPCSUMOK) 1438 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1439 1440 /* Check TCP/UDP checksum */ 1441 if (rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT) && 1442 rxctl & VGE_RDCTL_PROTOCSUMOK) { 1443 m->m_pkthdr.csum_flags |= 1444 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1445 m->m_pkthdr.csum_data = 0xffff; 1446 } 1447 } 1448 1449 if (rxstat & VGE_RDSTS_VTAG) { 1450 /* 1451 * The 32-bit rxctl register is stored in little-endian. 1452 * However, the 16-bit vlan tag is stored in big-endian, 1453 * so we have to byte swap it. 1454 */ 1455 m->m_pkthdr.ether_vtag = 1456 bswap16(rxctl & VGE_RDCTL_VLANID); 1457 m->m_flags |= M_VLANTAG; 1458 } 1459 1460 VGE_UNLOCK(sc); 1461 (*ifp->if_input)(ifp, m); 1462 VGE_LOCK(sc); 1463 1464 lim++; 1465 if (lim == VGE_RX_DESC_CNT) 1466 break; 1467 1468 } 1469 1470 /* Flush the RX DMA ring */ 1471 1472 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1473 sc->vge_ldata.vge_rx_list_map, 1474 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1475 1476 sc->vge_ldata.vge_rx_prodidx = i; 1477 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1478 1479 1480 return (lim); 1481} 1482 1483static void 1484vge_txeof(sc) 1485 struct vge_softc *sc; 1486{ 1487 struct ifnet *ifp; 1488 u_int32_t txstat; 1489 int idx; 1490 1491 ifp = sc->vge_ifp; 1492 idx = sc->vge_ldata.vge_tx_considx; 1493 1494 /* Invalidate the TX descriptor list */ 1495 1496 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1497 sc->vge_ldata.vge_tx_list_map, 1498 BUS_DMASYNC_POSTREAD); 1499 1500 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1501 1502 txstat = le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1503 if (txstat & VGE_TDSTS_OWN) 1504 break; 1505 1506 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1507 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1508 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1509 sc->vge_ldata.vge_tx_dmamap[idx]); 1510 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1511 ifp->if_collisions++; 1512 if (txstat & VGE_TDSTS_TXERR) 1513 ifp->if_oerrors++; 1514 else 1515 ifp->if_opackets++; 1516 1517 sc->vge_ldata.vge_tx_free++; 1518 VGE_TX_DESC_INC(idx); 1519 } 1520 1521 /* No changes made to the TX ring, so no flush needed */ 1522 1523 if (idx != sc->vge_ldata.vge_tx_considx) { 1524 sc->vge_ldata.vge_tx_considx = idx; 1525 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1526 ifp->if_timer = 0; 1527 } 1528 1529 /* 1530 * If not all descriptors have been released reaped yet, 1531 * reload the timer so that we will eventually get another 1532 * interrupt that will cause us to re-enter this routine. 1533 * This is done in case the transmitter has gone idle. 1534 */ 1535 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) { 1536 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1537 } 1538 1539 return; 1540} 1541 1542static void 1543vge_tick(xsc) 1544 void *xsc; 1545{ 1546 struct vge_softc *sc; 1547 struct ifnet *ifp; 1548 struct mii_data *mii; 1549 1550 sc = xsc; 1551 ifp = sc->vge_ifp; 1552 VGE_LOCK(sc); 1553 mii = device_get_softc(sc->vge_miibus); 1554 1555 mii_tick(mii); 1556 if (sc->vge_link) { 1557 if (!(mii->mii_media_status & IFM_ACTIVE)) { 1558 sc->vge_link = 0; 1559 if_link_state_change(sc->vge_ifp, 1560 LINK_STATE_DOWN); 1561 } 1562 } else { 1563 if (mii->mii_media_status & IFM_ACTIVE && 1564 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1565 sc->vge_link = 1; 1566 if_link_state_change(sc->vge_ifp, 1567 LINK_STATE_UP); 1568 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1569 taskqueue_enqueue(taskqueue_swi, 1570 &sc->vge_txtask); 1571 } 1572 } 1573 1574 VGE_UNLOCK(sc); 1575 1576 return; 1577} 1578 1579#ifdef DEVICE_POLLING 1580static int 1581vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1582{ 1583 struct vge_softc *sc = ifp->if_softc; 1584 int rx_npkts = 0; 1585 1586 VGE_LOCK(sc); 1587 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1588 goto done; 1589 1590 sc->rxcycles = count; 1591 rx_npkts = vge_rxeof(sc); 1592 vge_txeof(sc); 1593 1594 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1595 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1596 1597 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1598 u_int32_t status; 1599 status = CSR_READ_4(sc, VGE_ISR); 1600 if (status == 0xFFFFFFFF) 1601 goto done; 1602 if (status) 1603 CSR_WRITE_4(sc, VGE_ISR, status); 1604 1605 /* 1606 * XXX check behaviour on receiver stalls. 1607 */ 1608 1609 if (status & VGE_ISR_TXDMA_STALL || 1610 status & VGE_ISR_RXDMA_STALL) 1611 vge_init(sc); 1612 1613 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1614 vge_rxeof(sc); 1615 ifp->if_ierrors++; 1616 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1617 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1618 } 1619 } 1620done: 1621 VGE_UNLOCK(sc); 1622 return (rx_npkts); 1623} 1624#endif /* DEVICE_POLLING */ 1625 1626static void 1627vge_intr(arg) 1628 void *arg; 1629{ 1630 struct vge_softc *sc; 1631 struct ifnet *ifp; 1632 u_int32_t status; 1633 1634 sc = arg; 1635 1636 if (sc->suspended) { 1637 return; 1638 } 1639 1640 VGE_LOCK(sc); 1641 ifp = sc->vge_ifp; 1642 1643 if (!(ifp->if_flags & IFF_UP)) { 1644 VGE_UNLOCK(sc); 1645 return; 1646 } 1647 1648#ifdef DEVICE_POLLING 1649 if (ifp->if_capenable & IFCAP_POLLING) { 1650 VGE_UNLOCK(sc); 1651 return; 1652 } 1653#endif 1654 1655 /* Disable interrupts */ 1656 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1657 1658 for (;;) { 1659 1660 status = CSR_READ_4(sc, VGE_ISR); 1661 /* If the card has gone away the read returns 0xffff. */ 1662 if (status == 0xFFFFFFFF) 1663 break; 1664 1665 if (status) 1666 CSR_WRITE_4(sc, VGE_ISR, status); 1667 1668 if ((status & VGE_INTRS) == 0) 1669 break; 1670 1671 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1672 vge_rxeof(sc); 1673 1674 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1675 vge_rxeof(sc); 1676 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1677 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1678 } 1679 1680 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1681 vge_txeof(sc); 1682 1683 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1684 vge_init(sc); 1685 1686 if (status & VGE_ISR_LINKSTS) 1687 vge_tick(sc); 1688 } 1689 1690 /* Re-enable interrupts */ 1691 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1692 1693 VGE_UNLOCK(sc); 1694 1695 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1696 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1697 1698 return; 1699} 1700 1701static int 1702vge_encap(sc, m_head, idx) 1703 struct vge_softc *sc; 1704 struct mbuf *m_head; 1705 int idx; 1706{ 1707 struct mbuf *m_new = NULL; 1708 struct vge_dmaload_arg arg; 1709 bus_dmamap_t map; 1710 int error; 1711 1712 if (sc->vge_ldata.vge_tx_free <= 2) 1713 return (EFBIG); 1714 1715 arg.vge_flags = 0; 1716 1717 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1718 arg.vge_flags |= VGE_TDCTL_IPCSUM; 1719 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1720 arg.vge_flags |= VGE_TDCTL_TCPCSUM; 1721 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1722 arg.vge_flags |= VGE_TDCTL_UDPCSUM; 1723 1724 arg.sc = sc; 1725 arg.vge_idx = idx; 1726 arg.vge_m0 = m_head; 1727 arg.vge_maxsegs = VGE_TX_FRAGS; 1728 1729 map = sc->vge_ldata.vge_tx_dmamap[idx]; 1730 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1731 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1732 1733 if (error && error != EFBIG) { 1734 if_printf(sc->vge_ifp, "can't map mbuf (error %d)\n", error); 1735 return (ENOBUFS); 1736 } 1737 1738 /* Too many segments to map, coalesce into a single mbuf */ 1739 1740 if (error || arg.vge_maxsegs == 0) { 1741 m_new = m_defrag(m_head, M_DONTWAIT); 1742 if (m_new == NULL) 1743 return (1); 1744 else 1745 m_head = m_new; 1746 1747 arg.sc = sc; 1748 arg.vge_m0 = m_head; 1749 arg.vge_idx = idx; 1750 arg.vge_maxsegs = 1; 1751 1752 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1753 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1754 if (error) { 1755 if_printf(sc->vge_ifp, "can't map mbuf (error %d)\n", 1756 error); 1757 return (EFBIG); 1758 } 1759 } 1760 1761 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1762 sc->vge_ldata.vge_tx_free--; 1763 1764 /* 1765 * Set up hardware VLAN tagging. 1766 */ 1767 1768 if (m_head->m_flags & M_VLANTAG) 1769 sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1770 htole32(m_head->m_pkthdr.ether_vtag | VGE_TDCTL_VTAG); 1771 1772 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1773 1774 return (0); 1775} 1776 1777static void 1778vge_tx_task(arg, npending) 1779 void *arg; 1780 int npending; 1781{ 1782 struct ifnet *ifp; 1783 1784 ifp = arg; 1785 vge_start(ifp); 1786 1787 return; 1788} 1789 1790/* 1791 * Main transmit routine. 1792 */ 1793 1794static void 1795vge_start(ifp) 1796 struct ifnet *ifp; 1797{ 1798 struct vge_softc *sc; 1799 struct mbuf *m_head = NULL; 1800 int idx, pidx = 0; 1801 1802 sc = ifp->if_softc; 1803 VGE_LOCK(sc); 1804 1805 if (!sc->vge_link || ifp->if_drv_flags & IFF_DRV_OACTIVE) { 1806 VGE_UNLOCK(sc); 1807 return; 1808 } 1809 1810 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 1811 VGE_UNLOCK(sc); 1812 return; 1813 } 1814 1815 idx = sc->vge_ldata.vge_tx_prodidx; 1816 1817 pidx = idx - 1; 1818 if (pidx < 0) 1819 pidx = VGE_TX_DESC_CNT - 1; 1820 1821 1822 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1823 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1824 if (m_head == NULL) 1825 break; 1826 1827 if (vge_encap(sc, m_head, idx)) { 1828 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1829 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1830 break; 1831 } 1832 1833 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1834 htole16(VGE_TXDESC_Q); 1835 1836 pidx = idx; 1837 VGE_TX_DESC_INC(idx); 1838 1839 /* 1840 * If there's a BPF listener, bounce a copy of this frame 1841 * to him. 1842 */ 1843 ETHER_BPF_MTAP(ifp, m_head); 1844 } 1845 1846 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1847 VGE_UNLOCK(sc); 1848 return; 1849 } 1850 1851 /* Flush the TX descriptors */ 1852 1853 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1854 sc->vge_ldata.vge_tx_list_map, 1855 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1856 1857 /* Issue a transmit command. */ 1858 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1859 1860 sc->vge_ldata.vge_tx_prodidx = idx; 1861 1862 /* 1863 * Use the countdown timer for interrupt moderation. 1864 * 'TX done' interrupts are disabled. Instead, we reset the 1865 * countdown timer, which will begin counting until it hits 1866 * the value in the SSTIMER register, and then trigger an 1867 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1868 * the timer count is reloaded. Only when the transmitter 1869 * is idle will the timer hit 0 and an interrupt fire. 1870 */ 1871 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1872 1873 VGE_UNLOCK(sc); 1874 1875 /* 1876 * Set a timeout in case the chip goes out to lunch. 1877 */ 1878 ifp->if_timer = 5; 1879 1880 return; 1881} 1882 1883static void 1884vge_init(xsc) 1885 void *xsc; 1886{ 1887 struct vge_softc *sc = xsc; 1888 struct ifnet *ifp = sc->vge_ifp; 1889 struct mii_data *mii; 1890 int i; 1891 1892 VGE_LOCK(sc); 1893 mii = device_get_softc(sc->vge_miibus); 1894 1895 /* 1896 * Cancel pending I/O and free all RX/TX buffers. 1897 */ 1898 vge_stop(sc); 1899 vge_reset(sc); 1900 1901 /* 1902 * Initialize the RX and TX descriptors and mbufs. 1903 */ 1904 1905 vge_rx_list_init(sc); 1906 vge_tx_list_init(sc); 1907 1908 /* Set our station address */ 1909 for (i = 0; i < ETHER_ADDR_LEN; i++) 1910 CSR_WRITE_1(sc, VGE_PAR0 + i, IF_LLADDR(sc->vge_ifp)[i]); 1911 1912 /* 1913 * Set receive FIFO threshold. Also allow transmission and 1914 * reception of VLAN tagged frames. 1915 */ 1916 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1917 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1918 1919 /* Set DMA burst length */ 1920 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1921 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1922 1923 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1924 1925 /* Set collision backoff algorithm */ 1926 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1927 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1928 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1929 1930 /* Disable LPSEL field in priority resolution */ 1931 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1932 1933 /* 1934 * Load the addresses of the DMA queues into the chip. 1935 * Note that we only use one transmit queue. 1936 */ 1937 1938 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 1939 VGE_ADDR_LO(sc->vge_ldata.vge_tx_list_addr)); 1940 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 1941 1942 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 1943 VGE_ADDR_LO(sc->vge_ldata.vge_rx_list_addr)); 1944 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 1945 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 1946 1947 /* Enable and wake up the RX descriptor queue */ 1948 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1949 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1950 1951 /* Enable the TX descriptor queue */ 1952 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1953 1954 /* Set up the receive filter -- allow large frames for VLANs. */ 1955 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 1956 1957 /* If we want promiscuous mode, set the allframes bit. */ 1958 if (ifp->if_flags & IFF_PROMISC) { 1959 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1960 } 1961 1962 /* Set capture broadcast bit to capture broadcast frames. */ 1963 if (ifp->if_flags & IFF_BROADCAST) { 1964 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1965 } 1966 1967 /* Set multicast bit to capture multicast frames. */ 1968 if (ifp->if_flags & IFF_MULTICAST) { 1969 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1970 } 1971 1972 /* Init the cam filter. */ 1973 vge_cam_clear(sc); 1974 1975 /* Init the multicast filter. */ 1976 vge_setmulti(sc); 1977 1978 /* Enable flow control */ 1979 1980 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1981 1982 /* Enable jumbo frame reception (if desired) */ 1983 1984 /* Start the MAC. */ 1985 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1986 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1987 CSR_WRITE_1(sc, VGE_CRS0, 1988 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1989 1990 /* 1991 * Configure one-shot timer for microsecond 1992 * resulution and load it for 500 usecs. 1993 */ 1994 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1995 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1996 1997 /* 1998 * Configure interrupt moderation for receive. Enable 1999 * the holdoff counter and load it, and set the RX 2000 * suppression count to the number of descriptors we 2001 * want to allow before triggering an interrupt. 2002 * The holdoff timer is in units of 20 usecs. 2003 */ 2004 2005#ifdef notyet 2006 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 2007 /* Select the interrupt holdoff timer page. */ 2008 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2009 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 2010 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 2011 2012 /* Enable use of the holdoff timer. */ 2013 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 2014 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 2015 2016 /* Select the RX suppression threshold page. */ 2017 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2018 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 2019 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 2020 2021 /* Restore the page select bits. */ 2022 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2023 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 2024#endif 2025 2026#ifdef DEVICE_POLLING 2027 /* 2028 * Disable interrupts if we are polling. 2029 */ 2030 if (ifp->if_capenable & IFCAP_POLLING) { 2031 CSR_WRITE_4(sc, VGE_IMR, 0); 2032 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2033 } else /* otherwise ... */ 2034#endif 2035 { 2036 /* 2037 * Enable interrupts. 2038 */ 2039 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2040 CSR_WRITE_4(sc, VGE_ISR, 0); 2041 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2042 } 2043 2044 mii_mediachg(mii); 2045 2046 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2047 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2048 2049 sc->vge_if_flags = 0; 2050 sc->vge_link = 0; 2051 2052 VGE_UNLOCK(sc); 2053 2054 return; 2055} 2056 2057/* 2058 * Set media options. 2059 */ 2060static int 2061vge_ifmedia_upd(ifp) 2062 struct ifnet *ifp; 2063{ 2064 struct vge_softc *sc; 2065 struct mii_data *mii; 2066 2067 sc = ifp->if_softc; 2068 VGE_LOCK(sc); 2069 mii = device_get_softc(sc->vge_miibus); 2070 mii_mediachg(mii); 2071 VGE_UNLOCK(sc); 2072 2073 return (0); 2074} 2075 2076/* 2077 * Report current media status. 2078 */ 2079static void 2080vge_ifmedia_sts(ifp, ifmr) 2081 struct ifnet *ifp; 2082 struct ifmediareq *ifmr; 2083{ 2084 struct vge_softc *sc; 2085 struct mii_data *mii; 2086 2087 sc = ifp->if_softc; 2088 mii = device_get_softc(sc->vge_miibus); 2089 2090 mii_pollstat(mii); 2091 ifmr->ifm_active = mii->mii_media_active; 2092 ifmr->ifm_status = mii->mii_media_status; 2093 2094 return; 2095} 2096 2097static void 2098vge_miibus_statchg(dev) 2099 device_t dev; 2100{ 2101 struct vge_softc *sc; 2102 struct mii_data *mii; 2103 struct ifmedia_entry *ife; 2104 2105 sc = device_get_softc(dev); 2106 mii = device_get_softc(sc->vge_miibus); 2107 ife = mii->mii_media.ifm_cur; 2108 2109 /* 2110 * If the user manually selects a media mode, we need to turn 2111 * on the forced MAC mode bit in the DIAGCTL register. If the 2112 * user happens to choose a full duplex mode, we also need to 2113 * set the 'force full duplex' bit. This applies only to 2114 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2115 * mode is disabled, and in 1000baseT mode, full duplex is 2116 * always implied, so we turn on the forced mode bit but leave 2117 * the FDX bit cleared. 2118 */ 2119 2120 switch (IFM_SUBTYPE(ife->ifm_media)) { 2121 case IFM_AUTO: 2122 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2123 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2124 break; 2125 case IFM_1000_T: 2126 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2127 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2128 break; 2129 case IFM_100_TX: 2130 case IFM_10_T: 2131 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2132 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2133 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2134 } else { 2135 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2136 } 2137 break; 2138 default: 2139 device_printf(dev, "unknown media type: %x\n", 2140 IFM_SUBTYPE(ife->ifm_media)); 2141 break; 2142 } 2143 2144 return; 2145} 2146 2147static int 2148vge_ioctl(ifp, command, data) 2149 struct ifnet *ifp; 2150 u_long command; 2151 caddr_t data; 2152{ 2153 struct vge_softc *sc = ifp->if_softc; 2154 struct ifreq *ifr = (struct ifreq *) data; 2155 struct mii_data *mii; 2156 int error = 0; 2157 2158 switch (command) { 2159 case SIOCSIFMTU: 2160 if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2161 error = EINVAL; 2162 ifp->if_mtu = ifr->ifr_mtu; 2163 break; 2164 case SIOCSIFFLAGS: 2165 if (ifp->if_flags & IFF_UP) { 2166 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2167 ifp->if_flags & IFF_PROMISC && 2168 !(sc->vge_if_flags & IFF_PROMISC)) { 2169 CSR_SETBIT_1(sc, VGE_RXCTL, 2170 VGE_RXCTL_RX_PROMISC); 2171 vge_setmulti(sc); 2172 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2173 !(ifp->if_flags & IFF_PROMISC) && 2174 sc->vge_if_flags & IFF_PROMISC) { 2175 CSR_CLRBIT_1(sc, VGE_RXCTL, 2176 VGE_RXCTL_RX_PROMISC); 2177 vge_setmulti(sc); 2178 } else 2179 vge_init(sc); 2180 } else { 2181 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2182 vge_stop(sc); 2183 } 2184 sc->vge_if_flags = ifp->if_flags; 2185 break; 2186 case SIOCADDMULTI: 2187 case SIOCDELMULTI: 2188 vge_setmulti(sc); 2189 break; 2190 case SIOCGIFMEDIA: 2191 case SIOCSIFMEDIA: 2192 mii = device_get_softc(sc->vge_miibus); 2193 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2194 break; 2195 case SIOCSIFCAP: 2196 { 2197 int mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2198#ifdef DEVICE_POLLING 2199 if (mask & IFCAP_POLLING) { 2200 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2201 error = ether_poll_register(vge_poll, ifp); 2202 if (error) 2203 return(error); 2204 VGE_LOCK(sc); 2205 /* Disable interrupts */ 2206 CSR_WRITE_4(sc, VGE_IMR, 0); 2207 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2208 ifp->if_capenable |= IFCAP_POLLING; 2209 VGE_UNLOCK(sc); 2210 } else { 2211 error = ether_poll_deregister(ifp); 2212 /* Enable interrupts. */ 2213 VGE_LOCK(sc); 2214 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2215 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2216 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2217 ifp->if_capenable &= ~IFCAP_POLLING; 2218 VGE_UNLOCK(sc); 2219 } 2220 } 2221#endif /* DEVICE_POLLING */ 2222 if ((mask & IFCAP_TXCSUM) != 0 && 2223 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2224 ifp->if_capenable ^= IFCAP_TXCSUM; 2225 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2226 ifp->if_hwassist |= VGE_CSUM_FEATURES; 2227 else 2228 ifp->if_hwassist &= ~VGE_CSUM_FEATURES; 2229 } 2230 if ((mask & IFCAP_RXCSUM) != 0 && 2231 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 2232 ifp->if_capenable ^= IFCAP_RXCSUM; 2233 } 2234 break; 2235 default: 2236 error = ether_ioctl(ifp, command, data); 2237 break; 2238 } 2239 2240 return (error); 2241} 2242 2243static void 2244vge_watchdog(ifp) 2245 struct ifnet *ifp; 2246{ 2247 struct vge_softc *sc; 2248 2249 sc = ifp->if_softc; 2250 VGE_LOCK(sc); 2251 if_printf(ifp, "watchdog timeout\n"); 2252 ifp->if_oerrors++; 2253 2254 vge_txeof(sc); 2255 vge_rxeof(sc); 2256 2257 vge_init(sc); 2258 2259 VGE_UNLOCK(sc); 2260 2261 return; 2262} 2263 2264/* 2265 * Stop the adapter and free any mbufs allocated to the 2266 * RX and TX lists. 2267 */ 2268static void 2269vge_stop(sc) 2270 struct vge_softc *sc; 2271{ 2272 register int i; 2273 struct ifnet *ifp; 2274 2275 VGE_LOCK(sc); 2276 ifp = sc->vge_ifp; 2277 ifp->if_timer = 0; 2278 2279 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2280 2281 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2282 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2283 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2284 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2285 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2286 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2287 2288 if (sc->vge_head != NULL) { 2289 m_freem(sc->vge_head); 2290 sc->vge_head = sc->vge_tail = NULL; 2291 } 2292 2293 /* Free the TX list buffers. */ 2294 2295 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 2296 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 2297 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2298 sc->vge_ldata.vge_tx_dmamap[i]); 2299 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 2300 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 2301 } 2302 } 2303 2304 /* Free the RX list buffers. */ 2305 2306 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 2307 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 2308 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2309 sc->vge_ldata.vge_rx_dmamap[i]); 2310 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 2311 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 2312 } 2313 } 2314 2315 VGE_UNLOCK(sc); 2316 2317 return; 2318} 2319 2320/* 2321 * Device suspend routine. Stop the interface and save some PCI 2322 * settings in case the BIOS doesn't restore them properly on 2323 * resume. 2324 */ 2325static int 2326vge_suspend(dev) 2327 device_t dev; 2328{ 2329 struct vge_softc *sc; 2330 2331 sc = device_get_softc(dev); 2332 2333 vge_stop(sc); 2334 2335 sc->suspended = 1; 2336 2337 return (0); 2338} 2339 2340/* 2341 * Device resume routine. Restore some PCI settings in case the BIOS 2342 * doesn't, re-enable busmastering, and restart the interface if 2343 * appropriate. 2344 */ 2345static int 2346vge_resume(dev) 2347 device_t dev; 2348{ 2349 struct vge_softc *sc; 2350 struct ifnet *ifp; 2351 2352 sc = device_get_softc(dev); 2353 ifp = sc->vge_ifp; 2354 2355 /* reenable busmastering */ 2356 pci_enable_busmaster(dev); 2357 pci_enable_io(dev, SYS_RES_MEMORY); 2358 2359 /* reinitialize interface if necessary */ 2360 if (ifp->if_flags & IFF_UP) 2361 vge_init(sc); 2362 2363 sc->suspended = 0; 2364 2365 return (0); 2366} 2367 2368/* 2369 * Stop all chip I/O so that the kernel's probe routines don't 2370 * get confused by errant DMAs when rebooting. 2371 */ 2372static int 2373vge_shutdown(dev) 2374 device_t dev; 2375{ 2376 struct vge_softc *sc; 2377 2378 sc = device_get_softc(dev); 2379 2380 vge_stop(sc); 2381 2382 return (0); 2383} 2384