if_vge.c revision 150789
1/*- 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/vge/if_vge.c 150789 2005-10-01 18:56:19Z glebius $"); 35 36/* 37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 46 * combines a tri-speed ethernet MAC and PHY, with the following 47 * features: 48 * 49 * o Jumbo frame support up to 16K 50 * o Transmit and receive flow control 51 * o IPv4 checksum offload 52 * o VLAN tag insertion and stripping 53 * o TCP large send 54 * o 64-bit multicast hash table filter 55 * o 64 entry CAM filter 56 * o 16K RX FIFO and 48K TX FIFO memory 57 * o Interrupt moderation 58 * 59 * The VT6122 supports up to four transmit DMA queues. The descriptors 60 * in the transmit ring can address up to 7 data fragments; frames which 61 * span more than 7 data buffers must be coalesced, but in general the 62 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 63 * long. The receive descriptors address only a single buffer. 64 * 65 * There are two peculiar design issues with the VT6122. One is that 66 * receive data buffers must be aligned on a 32-bit boundary. This is 67 * not a problem where the VT6122 is used as a LOM device in x86-based 68 * systems, but on architectures that generate unaligned access traps, we 69 * have to do some copying. 70 * 71 * The other issue has to do with the way 64-bit addresses are handled. 72 * The DMA descriptors only allow you to specify 48 bits of addressing 73 * information. The remaining 16 bits are specified using one of the 74 * I/O registers. If you only have a 32-bit system, then this isn't 75 * an issue, but if you have a 64-bit system and more than 4GB of 76 * memory, you must have to make sure your network data buffers reside 77 * in the same 48-bit 'segment.' 78 * 79 * Special thanks to Ryan Fu at VIA Networking for providing documentation 80 * and sample NICs for testing. 81 */ 82 83#include <sys/param.h> 84#include <sys/endian.h> 85#include <sys/systm.h> 86#include <sys/sockio.h> 87#include <sys/mbuf.h> 88#include <sys/malloc.h> 89#include <sys/module.h> 90#include <sys/kernel.h> 91#include <sys/socket.h> 92#include <sys/taskqueue.h> 93 94#include <net/if.h> 95#include <net/if_arp.h> 96#include <net/ethernet.h> 97#include <net/if_dl.h> 98#include <net/if_media.h> 99#include <net/if_types.h> 100#include <net/if_vlan_var.h> 101 102#include <net/bpf.h> 103 104#include <machine/bus.h> 105#include <machine/resource.h> 106#include <sys/bus.h> 107#include <sys/rman.h> 108 109#include <dev/mii/mii.h> 110#include <dev/mii/miivar.h> 111 112#include <dev/pci/pcireg.h> 113#include <dev/pci/pcivar.h> 114 115MODULE_DEPEND(vge, pci, 1, 1, 1); 116MODULE_DEPEND(vge, ether, 1, 1, 1); 117MODULE_DEPEND(vge, miibus, 1, 1, 1); 118 119/* "controller miibus0" required. See GENERIC if you get errors here. */ 120#include "miibus_if.h" 121 122#include <dev/vge/if_vgereg.h> 123#include <dev/vge/if_vgevar.h> 124 125#define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 126 127/* 128 * Various supported device vendors/types and their names. 129 */ 130static struct vge_type vge_devs[] = { 131 { VIA_VENDORID, VIA_DEVICEID_61XX, 132 "VIA Networking Gigabit Ethernet" }, 133 { 0, 0, NULL } 134}; 135 136static int vge_probe (device_t); 137static int vge_attach (device_t); 138static int vge_detach (device_t); 139 140static int vge_encap (struct vge_softc *, struct mbuf *, int); 141 142static void vge_dma_map_addr (void *, bus_dma_segment_t *, int, int); 143static void vge_dma_map_rx_desc (void *, bus_dma_segment_t *, int, 144 bus_size_t, int); 145static void vge_dma_map_tx_desc (void *, bus_dma_segment_t *, int, 146 bus_size_t, int); 147static int vge_allocmem (device_t, struct vge_softc *); 148static int vge_newbuf (struct vge_softc *, int, struct mbuf *); 149static int vge_rx_list_init (struct vge_softc *); 150static int vge_tx_list_init (struct vge_softc *); 151#ifdef VGE_FIXUP_RX 152static __inline void vge_fixup_rx 153 (struct mbuf *); 154#endif 155static void vge_rxeof (struct vge_softc *); 156static void vge_txeof (struct vge_softc *); 157static void vge_intr (void *); 158static void vge_tick (void *); 159static void vge_tx_task (void *, int); 160static void vge_start (struct ifnet *); 161static int vge_ioctl (struct ifnet *, u_long, caddr_t); 162static void vge_init (void *); 163static void vge_stop (struct vge_softc *); 164static void vge_watchdog (struct ifnet *); 165static int vge_suspend (device_t); 166static int vge_resume (device_t); 167static void vge_shutdown (device_t); 168static int vge_ifmedia_upd (struct ifnet *); 169static void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 170 171#ifdef VGE_EEPROM 172static void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 173#endif 174static void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 175 176static void vge_miipoll_start (struct vge_softc *); 177static void vge_miipoll_stop (struct vge_softc *); 178static int vge_miibus_readreg (device_t, int, int); 179static int vge_miibus_writereg (device_t, int, int, int); 180static void vge_miibus_statchg (device_t); 181 182static void vge_cam_clear (struct vge_softc *); 183static int vge_cam_set (struct vge_softc *, uint8_t *); 184#if __FreeBSD_version < 502113 185static uint32_t vge_mchash (uint8_t *); 186#endif 187static void vge_setmulti (struct vge_softc *); 188static void vge_reset (struct vge_softc *); 189 190#define VGE_PCI_LOIO 0x10 191#define VGE_PCI_LOMEM 0x14 192 193static device_method_t vge_methods[] = { 194 /* Device interface */ 195 DEVMETHOD(device_probe, vge_probe), 196 DEVMETHOD(device_attach, vge_attach), 197 DEVMETHOD(device_detach, vge_detach), 198 DEVMETHOD(device_suspend, vge_suspend), 199 DEVMETHOD(device_resume, vge_resume), 200 DEVMETHOD(device_shutdown, vge_shutdown), 201 202 /* bus interface */ 203 DEVMETHOD(bus_print_child, bus_generic_print_child), 204 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 205 206 /* MII interface */ 207 DEVMETHOD(miibus_readreg, vge_miibus_readreg), 208 DEVMETHOD(miibus_writereg, vge_miibus_writereg), 209 DEVMETHOD(miibus_statchg, vge_miibus_statchg), 210 211 { 0, 0 } 212}; 213 214static driver_t vge_driver = { 215 "vge", 216 vge_methods, 217 sizeof(struct vge_softc) 218}; 219 220static devclass_t vge_devclass; 221 222DRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0); 223DRIVER_MODULE(vge, cardbus, vge_driver, vge_devclass, 0, 0); 224DRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0); 225 226#ifdef VGE_EEPROM 227/* 228 * Read a word of data stored in the EEPROM at address 'addr.' 229 */ 230static void 231vge_eeprom_getword(sc, addr, dest) 232 struct vge_softc *sc; 233 int addr; 234 u_int16_t *dest; 235{ 236 register int i; 237 u_int16_t word = 0; 238 239 /* 240 * Enter EEPROM embedded programming mode. In order to 241 * access the EEPROM at all, we first have to set the 242 * EELOAD bit in the CHIPCFG2 register. 243 */ 244 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 245 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 246 247 /* Select the address of the word we want to read */ 248 CSR_WRITE_1(sc, VGE_EEADDR, addr); 249 250 /* Issue read command */ 251 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 252 253 /* Wait for the done bit to be set. */ 254 for (i = 0; i < VGE_TIMEOUT; i++) { 255 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 256 break; 257 } 258 259 if (i == VGE_TIMEOUT) { 260 device_printf(sc->vge_dev, "EEPROM read timed out\n"); 261 *dest = 0; 262 return; 263 } 264 265 /* Read the result */ 266 word = CSR_READ_2(sc, VGE_EERDDAT); 267 268 /* Turn off EEPROM access mode. */ 269 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 270 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 271 272 *dest = word; 273 274 return; 275} 276#endif 277 278/* 279 * Read a sequence of words from the EEPROM. 280 */ 281static void 282vge_read_eeprom(sc, dest, off, cnt, swap) 283 struct vge_softc *sc; 284 caddr_t dest; 285 int off; 286 int cnt; 287 int swap; 288{ 289 int i; 290#ifdef VGE_EEPROM 291 u_int16_t word = 0, *ptr; 292 293 for (i = 0; i < cnt; i++) { 294 vge_eeprom_getword(sc, off + i, &word); 295 ptr = (u_int16_t *)(dest + (i * 2)); 296 if (swap) 297 *ptr = ntohs(word); 298 else 299 *ptr = word; 300 } 301#else 302 for (i = 0; i < ETHER_ADDR_LEN; i++) 303 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 304#endif 305} 306 307static void 308vge_miipoll_stop(sc) 309 struct vge_softc *sc; 310{ 311 int i; 312 313 CSR_WRITE_1(sc, VGE_MIICMD, 0); 314 315 for (i = 0; i < VGE_TIMEOUT; i++) { 316 DELAY(1); 317 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 318 break; 319 } 320 321 if (i == VGE_TIMEOUT) 322 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 323 324 return; 325} 326 327static void 328vge_miipoll_start(sc) 329 struct vge_softc *sc; 330{ 331 int i; 332 333 /* First, make sure we're idle. */ 334 335 CSR_WRITE_1(sc, VGE_MIICMD, 0); 336 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 337 338 for (i = 0; i < VGE_TIMEOUT; i++) { 339 DELAY(1); 340 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 341 break; 342 } 343 344 if (i == VGE_TIMEOUT) { 345 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 346 return; 347 } 348 349 /* Now enable auto poll mode. */ 350 351 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 352 353 /* And make sure it started. */ 354 355 for (i = 0; i < VGE_TIMEOUT; i++) { 356 DELAY(1); 357 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 358 break; 359 } 360 361 if (i == VGE_TIMEOUT) 362 device_printf(sc->vge_dev, "failed to start MII autopoll\n"); 363 364 return; 365} 366 367static int 368vge_miibus_readreg(dev, phy, reg) 369 device_t dev; 370 int phy, reg; 371{ 372 struct vge_softc *sc; 373 int i; 374 u_int16_t rval = 0; 375 376 sc = device_get_softc(dev); 377 378 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 379 return(0); 380 381 VGE_LOCK(sc); 382 vge_miipoll_stop(sc); 383 384 /* Specify the register we want to read. */ 385 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 386 387 /* Issue read command. */ 388 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 389 390 /* Wait for the read command bit to self-clear. */ 391 for (i = 0; i < VGE_TIMEOUT; i++) { 392 DELAY(1); 393 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 394 break; 395 } 396 397 if (i == VGE_TIMEOUT) 398 device_printf(sc->vge_dev, "MII read timed out\n"); 399 else 400 rval = CSR_READ_2(sc, VGE_MIIDATA); 401 402 vge_miipoll_start(sc); 403 VGE_UNLOCK(sc); 404 405 return (rval); 406} 407 408static int 409vge_miibus_writereg(dev, phy, reg, data) 410 device_t dev; 411 int phy, reg, data; 412{ 413 struct vge_softc *sc; 414 int i, rval = 0; 415 416 sc = device_get_softc(dev); 417 418 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 419 return(0); 420 421 VGE_LOCK(sc); 422 vge_miipoll_stop(sc); 423 424 /* Specify the register we want to write. */ 425 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 426 427 /* Specify the data we want to write. */ 428 CSR_WRITE_2(sc, VGE_MIIDATA, data); 429 430 /* Issue write command. */ 431 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 432 433 /* Wait for the write command bit to self-clear. */ 434 for (i = 0; i < VGE_TIMEOUT; i++) { 435 DELAY(1); 436 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 437 break; 438 } 439 440 if (i == VGE_TIMEOUT) { 441 device_printf(sc->vge_dev, "MII write timed out\n"); 442 rval = EIO; 443 } 444 445 vge_miipoll_start(sc); 446 VGE_UNLOCK(sc); 447 448 return (rval); 449} 450 451static void 452vge_cam_clear(sc) 453 struct vge_softc *sc; 454{ 455 int i; 456 457 /* 458 * Turn off all the mask bits. This tells the chip 459 * that none of the entries in the CAM filter are valid. 460 * desired entries will be enabled as we fill the filter in. 461 */ 462 463 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 464 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 465 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 466 for (i = 0; i < 8; i++) 467 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 468 469 /* Clear the VLAN filter too. */ 470 471 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 472 for (i = 0; i < 8; i++) 473 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 474 475 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 476 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 477 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 478 479 sc->vge_camidx = 0; 480 481 return; 482} 483 484static int 485vge_cam_set(sc, addr) 486 struct vge_softc *sc; 487 uint8_t *addr; 488{ 489 int i, error = 0; 490 491 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 492 return(ENOSPC); 493 494 /* Select the CAM data page. */ 495 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 496 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 497 498 /* Set the filter entry we want to update and enable writing. */ 499 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 500 501 /* Write the address to the CAM registers */ 502 for (i = 0; i < ETHER_ADDR_LEN; i++) 503 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 504 505 /* Issue a write command. */ 506 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 507 508 /* Wake for it to clear. */ 509 for (i = 0; i < VGE_TIMEOUT; i++) { 510 DELAY(1); 511 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 512 break; 513 } 514 515 if (i == VGE_TIMEOUT) { 516 device_printf(sc->vge_dev, "setting CAM filter failed\n"); 517 error = EIO; 518 goto fail; 519 } 520 521 /* Select the CAM mask page. */ 522 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 523 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 524 525 /* Set the mask bit that enables this filter. */ 526 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 527 1<<(sc->vge_camidx & 7)); 528 529 sc->vge_camidx++; 530 531fail: 532 /* Turn off access to CAM. */ 533 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 534 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 535 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 536 537 return (error); 538} 539 540#if __FreeBSD_version < 502113 541static uint32_t 542vge_mchash(addr) 543 uint8_t *addr; 544{ 545 uint32_t crc, carry; 546 int idx, bit; 547 uint8_t data; 548 549 /* Compute CRC for the address value. */ 550 crc = 0xFFFFFFFF; /* initial value */ 551 552 for (idx = 0; idx < 6; idx++) { 553 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 554 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 555 crc <<= 1; 556 if (carry) 557 crc = (crc ^ 0x04c11db6) | carry; 558 } 559 } 560 561 return(crc); 562} 563#endif 564 565/* 566 * Program the multicast filter. We use the 64-entry CAM filter 567 * for perfect filtering. If there's more than 64 multicast addresses, 568 * we use the hash filter insted. 569 */ 570static void 571vge_setmulti(sc) 572 struct vge_softc *sc; 573{ 574 struct ifnet *ifp; 575 int error = 0/*, h = 0*/; 576 struct ifmultiaddr *ifma; 577 u_int32_t h, hashes[2] = { 0, 0 }; 578 579 ifp = sc->vge_ifp; 580 581 /* First, zot all the multicast entries. */ 582 vge_cam_clear(sc); 583 CSR_WRITE_4(sc, VGE_MAR0, 0); 584 CSR_WRITE_4(sc, VGE_MAR1, 0); 585 586 /* 587 * If the user wants allmulti or promisc mode, enable reception 588 * of all multicast frames. 589 */ 590 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 591 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 592 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 593 return; 594 } 595 596 /* Now program new ones */ 597 IF_ADDR_LOCK(ifp); 598 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 599 if (ifma->ifma_addr->sa_family != AF_LINK) 600 continue; 601 error = vge_cam_set(sc, 602 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 603 if (error) 604 break; 605 } 606 607 /* If there were too many addresses, use the hash filter. */ 608 if (error) { 609 vge_cam_clear(sc); 610 611 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 612 if (ifma->ifma_addr->sa_family != AF_LINK) 613 continue; 614#if __FreeBSD_version < 502113 615 h = vge_mchash(LLADDR((struct sockaddr_dl *) 616 ifma->ifma_addr)) >> 26; 617#else 618 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 619 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 620#endif 621 if (h < 32) 622 hashes[0] |= (1 << h); 623 else 624 hashes[1] |= (1 << (h - 32)); 625 } 626 627 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 628 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 629 } 630 IF_ADDR_UNLOCK(ifp); 631 632 return; 633} 634 635static void 636vge_reset(sc) 637 struct vge_softc *sc; 638{ 639 register int i; 640 641 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 642 643 for (i = 0; i < VGE_TIMEOUT; i++) { 644 DELAY(5); 645 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 646 break; 647 } 648 649 if (i == VGE_TIMEOUT) { 650 device_printf(sc->vge_dev, "soft reset timed out"); 651 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 652 DELAY(2000); 653 } 654 655 DELAY(5000); 656 657 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 658 659 for (i = 0; i < VGE_TIMEOUT; i++) { 660 DELAY(5); 661 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 662 break; 663 } 664 665 if (i == VGE_TIMEOUT) { 666 device_printf(sc->vge_dev, "EEPROM reload timed out\n"); 667 return; 668 } 669 670 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 671 672 return; 673} 674 675/* 676 * Probe for a VIA gigabit chip. Check the PCI vendor and device 677 * IDs against our list and return a device name if we find a match. 678 */ 679static int 680vge_probe(dev) 681 device_t dev; 682{ 683 struct vge_type *t; 684 struct vge_softc *sc; 685 686 t = vge_devs; 687 sc = device_get_softc(dev); 688 689 while (t->vge_name != NULL) { 690 if ((pci_get_vendor(dev) == t->vge_vid) && 691 (pci_get_device(dev) == t->vge_did)) { 692 device_set_desc(dev, t->vge_name); 693 return (BUS_PROBE_DEFAULT); 694 } 695 t++; 696 } 697 698 return (ENXIO); 699} 700 701static void 702vge_dma_map_rx_desc(arg, segs, nseg, mapsize, error) 703 void *arg; 704 bus_dma_segment_t *segs; 705 int nseg; 706 bus_size_t mapsize; 707 int error; 708{ 709 710 struct vge_dmaload_arg *ctx; 711 struct vge_rx_desc *d = NULL; 712 713 if (error) 714 return; 715 716 ctx = arg; 717 718 /* Signal error to caller if there's too many segments */ 719 if (nseg > ctx->vge_maxsegs) { 720 ctx->vge_maxsegs = 0; 721 return; 722 } 723 724 /* 725 * Map the segment array into descriptors. 726 */ 727 728 d = &ctx->sc->vge_ldata.vge_rx_list[ctx->vge_idx]; 729 730 /* If this descriptor is still owned by the chip, bail. */ 731 732 if (le32toh(d->vge_sts) & VGE_RDSTS_OWN) { 733 device_printf(ctx->sc->vge_dev, 734 "tried to map busy descriptor\n"); 735 ctx->vge_maxsegs = 0; 736 return; 737 } 738 739 d->vge_buflen = htole16(VGE_BUFLEN(segs[0].ds_len) | VGE_RXDESC_I); 740 d->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 741 d->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 742 d->vge_sts = 0; 743 d->vge_ctl = 0; 744 745 ctx->vge_maxsegs = 1; 746 747 return; 748} 749 750static void 751vge_dma_map_tx_desc(arg, segs, nseg, mapsize, error) 752 void *arg; 753 bus_dma_segment_t *segs; 754 int nseg; 755 bus_size_t mapsize; 756 int error; 757{ 758 struct vge_dmaload_arg *ctx; 759 struct vge_tx_desc *d = NULL; 760 struct vge_tx_frag *f; 761 int i = 0; 762 763 if (error) 764 return; 765 766 ctx = arg; 767 768 /* Signal error to caller if there's too many segments */ 769 if (nseg > ctx->vge_maxsegs) { 770 ctx->vge_maxsegs = 0; 771 return; 772 } 773 774 /* Map the segment array into descriptors. */ 775 776 d = &ctx->sc->vge_ldata.vge_tx_list[ctx->vge_idx]; 777 778 /* If this descriptor is still owned by the chip, bail. */ 779 780 if (le32toh(d->vge_sts) & VGE_TDSTS_OWN) { 781 ctx->vge_maxsegs = 0; 782 return; 783 } 784 785 for (i = 0; i < nseg; i++) { 786 f = &d->vge_frag[i]; 787 f->vge_buflen = htole16(VGE_BUFLEN(segs[i].ds_len)); 788 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[i].ds_addr)); 789 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[i].ds_addr) & 0xFFFF); 790 } 791 792 /* Argh. This chip does not autopad short frames */ 793 794 if (ctx->vge_m0->m_pkthdr.len < VGE_MIN_FRAMELEN) { 795 f = &d->vge_frag[i]; 796 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 797 ctx->vge_m0->m_pkthdr.len)); 798 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 799 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 800 ctx->vge_m0->m_pkthdr.len = VGE_MIN_FRAMELEN; 801 i++; 802 } 803 804 /* 805 * When telling the chip how many segments there are, we 806 * must use nsegs + 1 instead of just nsegs. Darned if I 807 * know why. 808 */ 809 i++; 810 811 d->vge_sts = ctx->vge_m0->m_pkthdr.len << 16; 812 d->vge_ctl = ctx->vge_flags|(i << 28)|VGE_TD_LS_NORM; 813 814 if (ctx->vge_m0->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 815 d->vge_ctl |= VGE_TDCTL_JUMBO; 816 817 ctx->vge_maxsegs = nseg; 818 819 return; 820} 821 822/* 823 * Map a single buffer address. 824 */ 825 826static void 827vge_dma_map_addr(arg, segs, nseg, error) 828 void *arg; 829 bus_dma_segment_t *segs; 830 int nseg; 831 int error; 832{ 833 bus_addr_t *addr; 834 835 if (error) 836 return; 837 838 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 839 addr = arg; 840 *addr = segs->ds_addr; 841 842 return; 843} 844 845static int 846vge_allocmem(dev, sc) 847 device_t dev; 848 struct vge_softc *sc; 849{ 850 int error; 851 int nseg; 852 int i; 853 854 /* 855 * Allocate map for RX mbufs. 856 */ 857 nseg = 32; 858 error = bus_dma_tag_create(sc->vge_parent_tag, ETHER_ALIGN, 0, 859 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 860 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 861 NULL, NULL, &sc->vge_ldata.vge_mtag); 862 if (error) { 863 device_printf(dev, "could not allocate dma tag\n"); 864 return (ENOMEM); 865 } 866 867 /* 868 * Allocate map for TX descriptor list. 869 */ 870 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 871 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 872 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 873 NULL, NULL, &sc->vge_ldata.vge_tx_list_tag); 874 if (error) { 875 device_printf(dev, "could not allocate dma tag\n"); 876 return (ENOMEM); 877 } 878 879 /* Allocate DMA'able memory for the TX ring */ 880 881 error = bus_dmamem_alloc(sc->vge_ldata.vge_tx_list_tag, 882 (void **)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 883 &sc->vge_ldata.vge_tx_list_map); 884 if (error) 885 return (ENOMEM); 886 887 /* Load the map for the TX ring. */ 888 889 error = bus_dmamap_load(sc->vge_ldata.vge_tx_list_tag, 890 sc->vge_ldata.vge_tx_list_map, sc->vge_ldata.vge_tx_list, 891 VGE_TX_LIST_SZ, vge_dma_map_addr, 892 &sc->vge_ldata.vge_tx_list_addr, BUS_DMA_NOWAIT); 893 894 /* Create DMA maps for TX buffers */ 895 896 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 897 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 898 &sc->vge_ldata.vge_tx_dmamap[i]); 899 if (error) { 900 device_printf(dev, "can't create DMA map for TX\n"); 901 return (ENOMEM); 902 } 903 } 904 905 /* 906 * Allocate map for RX descriptor list. 907 */ 908 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 909 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 910 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 911 NULL, NULL, &sc->vge_ldata.vge_rx_list_tag); 912 if (error) { 913 device_printf(dev, "could not allocate dma tag\n"); 914 return (ENOMEM); 915 } 916 917 /* Allocate DMA'able memory for the RX ring */ 918 919 error = bus_dmamem_alloc(sc->vge_ldata.vge_rx_list_tag, 920 (void **)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 921 &sc->vge_ldata.vge_rx_list_map); 922 if (error) 923 return (ENOMEM); 924 925 /* Load the map for the RX ring. */ 926 927 error = bus_dmamap_load(sc->vge_ldata.vge_rx_list_tag, 928 sc->vge_ldata.vge_rx_list_map, sc->vge_ldata.vge_rx_list, 929 VGE_TX_LIST_SZ, vge_dma_map_addr, 930 &sc->vge_ldata.vge_rx_list_addr, BUS_DMA_NOWAIT); 931 932 /* Create DMA maps for RX buffers */ 933 934 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 935 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 936 &sc->vge_ldata.vge_rx_dmamap[i]); 937 if (error) { 938 device_printf(dev, "can't create DMA map for RX\n"); 939 return (ENOMEM); 940 } 941 } 942 943 return (0); 944} 945 946/* 947 * Attach the interface. Allocate softc structures, do ifmedia 948 * setup and ethernet/BPF attach. 949 */ 950static int 951vge_attach(dev) 952 device_t dev; 953{ 954 u_char eaddr[ETHER_ADDR_LEN]; 955 struct vge_softc *sc; 956 struct ifnet *ifp; 957 int unit, error = 0, rid; 958 959 sc = device_get_softc(dev); 960 unit = device_get_unit(dev); 961 sc->vge_dev = dev; 962 963 mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 964 MTX_DEF | MTX_RECURSE); 965 /* 966 * Map control/status registers. 967 */ 968 pci_enable_busmaster(dev); 969 970 rid = VGE_PCI_LOMEM; 971 sc->vge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 972 0, ~0, 1, RF_ACTIVE); 973 974 if (sc->vge_res == NULL) { 975 printf ("vge%d: couldn't map ports/memory\n", unit); 976 error = ENXIO; 977 goto fail; 978 } 979 980 sc->vge_btag = rman_get_bustag(sc->vge_res); 981 sc->vge_bhandle = rman_get_bushandle(sc->vge_res); 982 983 /* Allocate interrupt */ 984 rid = 0; 985 sc->vge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 986 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE); 987 988 if (sc->vge_irq == NULL) { 989 printf("vge%d: couldn't map interrupt\n", unit); 990 error = ENXIO; 991 goto fail; 992 } 993 994 /* Reset the adapter. */ 995 vge_reset(sc); 996 997 /* 998 * Get station address from the EEPROM. 999 */ 1000 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 1001 1002 sc->vge_unit = unit; 1003 1004#if __FreeBSD_version < 502113 1005 printf("vge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1006#endif 1007 1008 /* 1009 * Allocate the parent bus DMA tag appropriate for PCI. 1010 */ 1011#define VGE_NSEG_NEW 32 1012 error = bus_dma_tag_create(NULL, /* parent */ 1013 1, 0, /* alignment, boundary */ 1014 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1015 BUS_SPACE_MAXADDR, /* highaddr */ 1016 NULL, NULL, /* filter, filterarg */ 1017 MAXBSIZE, VGE_NSEG_NEW, /* maxsize, nsegments */ 1018 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1019 BUS_DMA_ALLOCNOW, /* flags */ 1020 NULL, NULL, /* lockfunc, lockarg */ 1021 &sc->vge_parent_tag); 1022 if (error) 1023 goto fail; 1024 1025 error = vge_allocmem(dev, sc); 1026 1027 if (error) 1028 goto fail; 1029 1030 ifp = sc->vge_ifp = if_alloc(IFT_ETHER); 1031 if (ifp == NULL) { 1032 printf("vge%d: can not if_alloc()\n", sc->vge_unit); 1033 error = ENOSPC; 1034 goto fail; 1035 } 1036 1037 /* Do MII setup */ 1038 if (mii_phy_probe(dev, &sc->vge_miibus, 1039 vge_ifmedia_upd, vge_ifmedia_sts)) { 1040 printf("vge%d: MII without any phy!\n", sc->vge_unit); 1041 error = ENXIO; 1042 goto fail; 1043 } 1044 1045 ifp->if_softc = sc; 1046 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1047 ifp->if_mtu = ETHERMTU; 1048 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1049 ifp->if_ioctl = vge_ioctl; 1050 ifp->if_capabilities = IFCAP_VLAN_MTU; 1051 ifp->if_start = vge_start; 1052 ifp->if_hwassist = VGE_CSUM_FEATURES; 1053 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1054 ifp->if_capenable = ifp->if_capabilities; 1055#ifdef DEVICE_POLLING 1056 ifp->if_capabilities |= IFCAP_POLLING; 1057#endif 1058 ifp->if_watchdog = vge_watchdog; 1059 ifp->if_init = vge_init; 1060 ifp->if_baudrate = 1000000000; 1061 ifp->if_snd.ifq_maxlen = VGE_IFQ_MAXLEN; 1062 1063 TASK_INIT(&sc->vge_txtask, 0, vge_tx_task, ifp); 1064 1065 /* 1066 * Call MI attach routine. 1067 */ 1068 ether_ifattach(ifp, eaddr); 1069 1070 /* Hook interrupt last to avoid having to lock softc */ 1071 error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE, 1072 vge_intr, sc, &sc->vge_intrhand); 1073 1074 if (error) { 1075 printf("vge%d: couldn't set up irq\n", unit); 1076 ether_ifdetach(ifp); 1077 goto fail; 1078 } 1079 1080fail: 1081 if (error) 1082 vge_detach(dev); 1083 1084 return (error); 1085} 1086 1087/* 1088 * Shutdown hardware and free up resources. This can be called any 1089 * time after the mutex has been initialized. It is called in both 1090 * the error case in attach and the normal detach case so it needs 1091 * to be careful about only freeing resources that have actually been 1092 * allocated. 1093 */ 1094static int 1095vge_detach(dev) 1096 device_t dev; 1097{ 1098 struct vge_softc *sc; 1099 struct ifnet *ifp; 1100 int i; 1101 1102 sc = device_get_softc(dev); 1103 KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized")); 1104 ifp = sc->vge_ifp; 1105 1106#ifdef DEVICE_POLLING 1107 if (ifp->if_capenable & IFCAP_POLLING) 1108 ether_poll_deregister(ifp); 1109#endif 1110 1111 /* These should only be active if attach succeeded */ 1112 if (device_is_attached(dev)) { 1113 vge_stop(sc); 1114 /* 1115 * Force off the IFF_UP flag here, in case someone 1116 * still had a BPF descriptor attached to this 1117 * interface. If they do, ether_ifattach() will cause 1118 * the BPF code to try and clear the promisc mode 1119 * flag, which will bubble down to vge_ioctl(), 1120 * which will try to call vge_init() again. This will 1121 * turn the NIC back on and restart the MII ticker, 1122 * which will panic the system when the kernel tries 1123 * to invoke the vge_tick() function that isn't there 1124 * anymore. 1125 */ 1126 ifp->if_flags &= ~IFF_UP; 1127 ether_ifdetach(ifp); 1128 } 1129 if (sc->vge_miibus) 1130 device_delete_child(dev, sc->vge_miibus); 1131 bus_generic_detach(dev); 1132 1133 if (sc->vge_intrhand) 1134 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); 1135 if (sc->vge_irq) 1136 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vge_irq); 1137 if (sc->vge_res) 1138 bus_release_resource(dev, SYS_RES_MEMORY, 1139 VGE_PCI_LOMEM, sc->vge_res); 1140 if (ifp) 1141 if_free(ifp); 1142 1143 /* Unload and free the RX DMA ring memory and map */ 1144 1145 if (sc->vge_ldata.vge_rx_list_tag) { 1146 bus_dmamap_unload(sc->vge_ldata.vge_rx_list_tag, 1147 sc->vge_ldata.vge_rx_list_map); 1148 bus_dmamem_free(sc->vge_ldata.vge_rx_list_tag, 1149 sc->vge_ldata.vge_rx_list, 1150 sc->vge_ldata.vge_rx_list_map); 1151 bus_dma_tag_destroy(sc->vge_ldata.vge_rx_list_tag); 1152 } 1153 1154 /* Unload and free the TX DMA ring memory and map */ 1155 1156 if (sc->vge_ldata.vge_tx_list_tag) { 1157 bus_dmamap_unload(sc->vge_ldata.vge_tx_list_tag, 1158 sc->vge_ldata.vge_tx_list_map); 1159 bus_dmamem_free(sc->vge_ldata.vge_tx_list_tag, 1160 sc->vge_ldata.vge_tx_list, 1161 sc->vge_ldata.vge_tx_list_map); 1162 bus_dma_tag_destroy(sc->vge_ldata.vge_tx_list_tag); 1163 } 1164 1165 /* Destroy all the RX and TX buffer maps */ 1166 1167 if (sc->vge_ldata.vge_mtag) { 1168 for (i = 0; i < VGE_TX_DESC_CNT; i++) 1169 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1170 sc->vge_ldata.vge_tx_dmamap[i]); 1171 for (i = 0; i < VGE_RX_DESC_CNT; i++) 1172 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1173 sc->vge_ldata.vge_rx_dmamap[i]); 1174 bus_dma_tag_destroy(sc->vge_ldata.vge_mtag); 1175 } 1176 1177 if (sc->vge_parent_tag) 1178 bus_dma_tag_destroy(sc->vge_parent_tag); 1179 1180 mtx_destroy(&sc->vge_mtx); 1181 1182 return (0); 1183} 1184 1185static int 1186vge_newbuf(sc, idx, m) 1187 struct vge_softc *sc; 1188 int idx; 1189 struct mbuf *m; 1190{ 1191 struct vge_dmaload_arg arg; 1192 struct mbuf *n = NULL; 1193 int i, error; 1194 1195 if (m == NULL) { 1196 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1197 if (n == NULL) 1198 return (ENOBUFS); 1199 m = n; 1200 } else 1201 m->m_data = m->m_ext.ext_buf; 1202 1203 1204#ifdef VGE_FIXUP_RX 1205 /* 1206 * This is part of an evil trick to deal with non-x86 platforms. 1207 * The VIA chip requires RX buffers to be aligned on 32-bit 1208 * boundaries, but that will hose non-x86 machines. To get around 1209 * this, we leave some empty space at the start of each buffer 1210 * and for non-x86 hosts, we copy the buffer back two bytes 1211 * to achieve word alignment. This is slightly more efficient 1212 * than allocating a new buffer, copying the contents, and 1213 * discarding the old buffer. 1214 */ 1215 m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_ETHER_ALIGN; 1216 m_adj(m, VGE_ETHER_ALIGN); 1217#else 1218 m->m_len = m->m_pkthdr.len = MCLBYTES; 1219#endif 1220 1221 arg.sc = sc; 1222 arg.vge_idx = idx; 1223 arg.vge_maxsegs = 1; 1224 arg.vge_flags = 0; 1225 1226 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, 1227 sc->vge_ldata.vge_rx_dmamap[idx], m, vge_dma_map_rx_desc, 1228 &arg, BUS_DMA_NOWAIT); 1229 if (error || arg.vge_maxsegs != 1) { 1230 if (n != NULL) 1231 m_freem(n); 1232 return (ENOMEM); 1233 } 1234 1235 /* 1236 * Note: the manual fails to document the fact that for 1237 * proper opration, the driver needs to replentish the RX 1238 * DMA ring 4 descriptors at a time (rather than one at a 1239 * time, like most chips). We can allocate the new buffers 1240 * but we should not set the OWN bits until we're ready 1241 * to hand back 4 of them in one shot. 1242 */ 1243 1244#define VGE_RXCHUNK 4 1245 sc->vge_rx_consumed++; 1246 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 1247 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 1248 sc->vge_ldata.vge_rx_list[i].vge_sts |= 1249 htole32(VGE_RDSTS_OWN); 1250 sc->vge_rx_consumed = 0; 1251 } 1252 1253 sc->vge_ldata.vge_rx_mbuf[idx] = m; 1254 1255 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1256 sc->vge_ldata.vge_rx_dmamap[idx], 1257 BUS_DMASYNC_PREREAD); 1258 1259 return (0); 1260} 1261 1262static int 1263vge_tx_list_init(sc) 1264 struct vge_softc *sc; 1265{ 1266 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 1267 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 1268 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 1269 1270 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1271 sc->vge_ldata.vge_tx_list_map, BUS_DMASYNC_PREWRITE); 1272 sc->vge_ldata.vge_tx_prodidx = 0; 1273 sc->vge_ldata.vge_tx_considx = 0; 1274 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 1275 1276 return (0); 1277} 1278 1279static int 1280vge_rx_list_init(sc) 1281 struct vge_softc *sc; 1282{ 1283 int i; 1284 1285 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 1286 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 1287 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 1288 1289 sc->vge_rx_consumed = 0; 1290 1291 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1292 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 1293 return (ENOBUFS); 1294 } 1295 1296 /* Flush the RX descriptors */ 1297 1298 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1299 sc->vge_ldata.vge_rx_list_map, 1300 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1301 1302 sc->vge_ldata.vge_rx_prodidx = 0; 1303 sc->vge_rx_consumed = 0; 1304 sc->vge_head = sc->vge_tail = NULL; 1305 1306 return (0); 1307} 1308 1309#ifdef VGE_FIXUP_RX 1310static __inline void 1311vge_fixup_rx(m) 1312 struct mbuf *m; 1313{ 1314 int i; 1315 uint16_t *src, *dst; 1316 1317 src = mtod(m, uint16_t *); 1318 dst = src - 1; 1319 1320 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1321 *dst++ = *src++; 1322 1323 m->m_data -= ETHER_ALIGN; 1324 1325 return; 1326} 1327#endif 1328 1329/* 1330 * RX handler. We support the reception of jumbo frames that have 1331 * been fragmented across multiple 2K mbuf cluster buffers. 1332 */ 1333static void 1334vge_rxeof(sc) 1335 struct vge_softc *sc; 1336{ 1337 struct mbuf *m; 1338 struct ifnet *ifp; 1339 int i, total_len; 1340 int lim = 0; 1341 struct vge_rx_desc *cur_rx; 1342 u_int32_t rxstat, rxctl; 1343 1344 VGE_LOCK_ASSERT(sc); 1345 ifp = sc->vge_ifp; 1346 i = sc->vge_ldata.vge_rx_prodidx; 1347 1348 /* Invalidate the descriptor memory */ 1349 1350 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1351 sc->vge_ldata.vge_rx_list_map, 1352 BUS_DMASYNC_POSTREAD); 1353 1354 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 1355 1356#ifdef DEVICE_POLLING 1357 if (ifp->if_capenable & IFCAP_POLLING) { 1358 if (sc->rxcycles <= 0) 1359 break; 1360 sc->rxcycles--; 1361 } 1362#endif 1363 1364 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1365 m = sc->vge_ldata.vge_rx_mbuf[i]; 1366 total_len = VGE_RXBYTES(cur_rx); 1367 rxstat = le32toh(cur_rx->vge_sts); 1368 rxctl = le32toh(cur_rx->vge_ctl); 1369 1370 /* Invalidate the RX mbuf and unload its map */ 1371 1372 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1373 sc->vge_ldata.vge_rx_dmamap[i], 1374 BUS_DMASYNC_POSTWRITE); 1375 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1376 sc->vge_ldata.vge_rx_dmamap[i]); 1377 1378 /* 1379 * If the 'start of frame' bit is set, this indicates 1380 * either the first fragment in a multi-fragment receive, 1381 * or an intermediate fragment. Either way, we want to 1382 * accumulate the buffers. 1383 */ 1384 if (rxstat & VGE_RXPKT_SOF) { 1385 m->m_len = MCLBYTES - VGE_ETHER_ALIGN; 1386 if (sc->vge_head == NULL) 1387 sc->vge_head = sc->vge_tail = m; 1388 else { 1389 m->m_flags &= ~M_PKTHDR; 1390 sc->vge_tail->m_next = m; 1391 sc->vge_tail = m; 1392 } 1393 vge_newbuf(sc, i, NULL); 1394 VGE_RX_DESC_INC(i); 1395 continue; 1396 } 1397 1398 /* 1399 * Bad/error frames will have the RXOK bit cleared. 1400 * However, there's one error case we want to allow: 1401 * if a VLAN tagged frame arrives and the chip can't 1402 * match it against the CAM filter, it considers this 1403 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1404 * We don't want to drop the frame though: our VLAN 1405 * filtering is done in software. 1406 */ 1407 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1408 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1409 ifp->if_ierrors++; 1410 /* 1411 * If this is part of a multi-fragment packet, 1412 * discard all the pieces. 1413 */ 1414 if (sc->vge_head != NULL) { 1415 m_freem(sc->vge_head); 1416 sc->vge_head = sc->vge_tail = NULL; 1417 } 1418 vge_newbuf(sc, i, m); 1419 VGE_RX_DESC_INC(i); 1420 continue; 1421 } 1422 1423 /* 1424 * If allocating a replacement mbuf fails, 1425 * reload the current one. 1426 */ 1427 1428 if (vge_newbuf(sc, i, NULL)) { 1429 ifp->if_ierrors++; 1430 if (sc->vge_head != NULL) { 1431 m_freem(sc->vge_head); 1432 sc->vge_head = sc->vge_tail = NULL; 1433 } 1434 vge_newbuf(sc, i, m); 1435 VGE_RX_DESC_INC(i); 1436 continue; 1437 } 1438 1439 VGE_RX_DESC_INC(i); 1440 1441 if (sc->vge_head != NULL) { 1442 m->m_len = total_len % (MCLBYTES - VGE_ETHER_ALIGN); 1443 /* 1444 * Special case: if there's 4 bytes or less 1445 * in this buffer, the mbuf can be discarded: 1446 * the last 4 bytes is the CRC, which we don't 1447 * care about anyway. 1448 */ 1449 if (m->m_len <= ETHER_CRC_LEN) { 1450 sc->vge_tail->m_len -= 1451 (ETHER_CRC_LEN - m->m_len); 1452 m_freem(m); 1453 } else { 1454 m->m_len -= ETHER_CRC_LEN; 1455 m->m_flags &= ~M_PKTHDR; 1456 sc->vge_tail->m_next = m; 1457 } 1458 m = sc->vge_head; 1459 sc->vge_head = sc->vge_tail = NULL; 1460 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1461 } else 1462 m->m_pkthdr.len = m->m_len = 1463 (total_len - ETHER_CRC_LEN); 1464 1465#ifdef VGE_FIXUP_RX 1466 vge_fixup_rx(m); 1467#endif 1468 ifp->if_ipackets++; 1469 m->m_pkthdr.rcvif = ifp; 1470 1471 /* Do RX checksumming if enabled */ 1472 if (ifp->if_capenable & IFCAP_RXCSUM) { 1473 1474 /* Check IP header checksum */ 1475 if (rxctl & VGE_RDCTL_IPPKT) 1476 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1477 if (rxctl & VGE_RDCTL_IPCSUMOK) 1478 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1479 1480 /* Check TCP/UDP checksum */ 1481 if (rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT) && 1482 rxctl & VGE_RDCTL_PROTOCSUMOK) { 1483 m->m_pkthdr.csum_flags |= 1484 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1485 m->m_pkthdr.csum_data = 0xffff; 1486 } 1487 } 1488 1489 if (rxstat & VGE_RDSTS_VTAG) 1490 VLAN_INPUT_TAG(ifp, m, 1491 ntohs((rxctl & VGE_RDCTL_VLANID)), continue); 1492 1493 VGE_UNLOCK(sc); 1494 (*ifp->if_input)(ifp, m); 1495 VGE_LOCK(sc); 1496 1497 lim++; 1498 if (lim == VGE_RX_DESC_CNT) 1499 break; 1500 1501 } 1502 1503 /* Flush the RX DMA ring */ 1504 1505 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1506 sc->vge_ldata.vge_rx_list_map, 1507 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1508 1509 sc->vge_ldata.vge_rx_prodidx = i; 1510 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1511 1512 1513 return; 1514} 1515 1516static void 1517vge_txeof(sc) 1518 struct vge_softc *sc; 1519{ 1520 struct ifnet *ifp; 1521 u_int32_t txstat; 1522 int idx; 1523 1524 ifp = sc->vge_ifp; 1525 idx = sc->vge_ldata.vge_tx_considx; 1526 1527 /* Invalidate the TX descriptor list */ 1528 1529 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1530 sc->vge_ldata.vge_tx_list_map, 1531 BUS_DMASYNC_POSTREAD); 1532 1533 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1534 1535 txstat = le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1536 if (txstat & VGE_TDSTS_OWN) 1537 break; 1538 1539 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1540 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1541 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1542 sc->vge_ldata.vge_tx_dmamap[idx]); 1543 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1544 ifp->if_collisions++; 1545 if (txstat & VGE_TDSTS_TXERR) 1546 ifp->if_oerrors++; 1547 else 1548 ifp->if_opackets++; 1549 1550 sc->vge_ldata.vge_tx_free++; 1551 VGE_TX_DESC_INC(idx); 1552 } 1553 1554 /* No changes made to the TX ring, so no flush needed */ 1555 1556 if (idx != sc->vge_ldata.vge_tx_considx) { 1557 sc->vge_ldata.vge_tx_considx = idx; 1558 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1559 ifp->if_timer = 0; 1560 } 1561 1562 /* 1563 * If not all descriptors have been released reaped yet, 1564 * reload the timer so that we will eventually get another 1565 * interrupt that will cause us to re-enter this routine. 1566 * This is done in case the transmitter has gone idle. 1567 */ 1568 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) { 1569 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1570 } 1571 1572 return; 1573} 1574 1575static void 1576vge_tick(xsc) 1577 void *xsc; 1578{ 1579 struct vge_softc *sc; 1580 struct ifnet *ifp; 1581 struct mii_data *mii; 1582 1583 sc = xsc; 1584 ifp = sc->vge_ifp; 1585 VGE_LOCK(sc); 1586 mii = device_get_softc(sc->vge_miibus); 1587 1588 mii_tick(mii); 1589 if (sc->vge_link) { 1590 if (!(mii->mii_media_status & IFM_ACTIVE)) { 1591 sc->vge_link = 0; 1592 if_link_state_change(sc->vge_ifp, 1593 LINK_STATE_DOWN); 1594 } 1595 } else { 1596 if (mii->mii_media_status & IFM_ACTIVE && 1597 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1598 sc->vge_link = 1; 1599 if_link_state_change(sc->vge_ifp, 1600 LINK_STATE_UP); 1601#if __FreeBSD_version < 502114 1602 if (ifp->if_snd.ifq_head != NULL) 1603#else 1604 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1605#endif 1606 taskqueue_enqueue(taskqueue_swi, 1607 &sc->vge_txtask); 1608 } 1609 } 1610 1611 VGE_UNLOCK(sc); 1612 1613 return; 1614} 1615 1616#ifdef DEVICE_POLLING 1617static void 1618vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1619{ 1620 struct vge_softc *sc = ifp->if_softc; 1621 1622 VGE_LOCK(sc); 1623 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1624 goto done; 1625 1626 sc->rxcycles = count; 1627 vge_rxeof(sc); 1628 vge_txeof(sc); 1629 1630#if __FreeBSD_version < 502114 1631 if (ifp->if_snd.ifq_head != NULL) 1632#else 1633 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1634#endif 1635 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1636 1637 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1638 u_int32_t status; 1639 status = CSR_READ_4(sc, VGE_ISR); 1640 if (status == 0xFFFFFFFF) 1641 goto done; 1642 if (status) 1643 CSR_WRITE_4(sc, VGE_ISR, status); 1644 1645 /* 1646 * XXX check behaviour on receiver stalls. 1647 */ 1648 1649 if (status & VGE_ISR_TXDMA_STALL || 1650 status & VGE_ISR_RXDMA_STALL) 1651 vge_init(sc); 1652 1653 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1654 vge_rxeof(sc); 1655 ifp->if_ierrors++; 1656 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1657 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1658 } 1659 } 1660done: 1661 VGE_UNLOCK(sc); 1662} 1663#endif /* DEVICE_POLLING */ 1664 1665static void 1666vge_intr(arg) 1667 void *arg; 1668{ 1669 struct vge_softc *sc; 1670 struct ifnet *ifp; 1671 u_int32_t status; 1672 1673 sc = arg; 1674 1675 if (sc->suspended) { 1676 return; 1677 } 1678 1679 VGE_LOCK(sc); 1680 ifp = sc->vge_ifp; 1681 1682 if (!(ifp->if_flags & IFF_UP)) { 1683 VGE_UNLOCK(sc); 1684 return; 1685 } 1686 1687#ifdef DEVICE_POLLING 1688 if (ifp->if_capenable & IFCAP_POLLING) { 1689 VGE_UNLOCK(sc); 1690 return; 1691 } 1692#endif 1693 1694 /* Disable interrupts */ 1695 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1696 1697 for (;;) { 1698 1699 status = CSR_READ_4(sc, VGE_ISR); 1700 /* If the card has gone away the read returns 0xffff. */ 1701 if (status == 0xFFFFFFFF) 1702 break; 1703 1704 if (status) 1705 CSR_WRITE_4(sc, VGE_ISR, status); 1706 1707 if ((status & VGE_INTRS) == 0) 1708 break; 1709 1710 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1711 vge_rxeof(sc); 1712 1713 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1714 vge_rxeof(sc); 1715 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1716 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1717 } 1718 1719 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1720 vge_txeof(sc); 1721 1722 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1723 vge_init(sc); 1724 1725 if (status & VGE_ISR_LINKSTS) 1726 vge_tick(sc); 1727 } 1728 1729 /* Re-enable interrupts */ 1730 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1731 1732 VGE_UNLOCK(sc); 1733 1734#if __FreeBSD_version < 502114 1735 if (ifp->if_snd.ifq_head != NULL) 1736#else 1737 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1738#endif 1739 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1740 1741 return; 1742} 1743 1744static int 1745vge_encap(sc, m_head, idx) 1746 struct vge_softc *sc; 1747 struct mbuf *m_head; 1748 int idx; 1749{ 1750 struct mbuf *m_new = NULL; 1751 struct vge_dmaload_arg arg; 1752 bus_dmamap_t map; 1753 int error; 1754 struct m_tag *mtag; 1755 1756 if (sc->vge_ldata.vge_tx_free <= 2) 1757 return (EFBIG); 1758 1759 arg.vge_flags = 0; 1760 1761 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1762 arg.vge_flags |= VGE_TDCTL_IPCSUM; 1763 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1764 arg.vge_flags |= VGE_TDCTL_TCPCSUM; 1765 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1766 arg.vge_flags |= VGE_TDCTL_UDPCSUM; 1767 1768 arg.sc = sc; 1769 arg.vge_idx = idx; 1770 arg.vge_m0 = m_head; 1771 arg.vge_maxsegs = VGE_TX_FRAGS; 1772 1773 map = sc->vge_ldata.vge_tx_dmamap[idx]; 1774 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1775 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1776 1777 if (error && error != EFBIG) { 1778 printf("vge%d: can't map mbuf (error %d)\n", 1779 sc->vge_unit, error); 1780 return (ENOBUFS); 1781 } 1782 1783 /* Too many segments to map, coalesce into a single mbuf */ 1784 1785 if (error || arg.vge_maxsegs == 0) { 1786 m_new = m_defrag(m_head, M_DONTWAIT); 1787 if (m_new == NULL) 1788 return (1); 1789 else 1790 m_head = m_new; 1791 1792 arg.sc = sc; 1793 arg.vge_m0 = m_head; 1794 arg.vge_idx = idx; 1795 arg.vge_maxsegs = 1; 1796 1797 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1798 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1799 if (error) { 1800 printf("vge%d: can't map mbuf (error %d)\n", 1801 sc->vge_unit, error); 1802 return (EFBIG); 1803 } 1804 } 1805 1806 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1807 sc->vge_ldata.vge_tx_free--; 1808 1809 /* 1810 * Set up hardware VLAN tagging. 1811 */ 1812 1813 mtag = VLAN_OUTPUT_TAG(sc->vge_ifp, m_head); 1814 if (mtag != NULL) 1815 sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1816 htole32(htons(VLAN_TAG_VALUE(mtag)) | VGE_TDCTL_VTAG); 1817 1818 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1819 1820 return (0); 1821} 1822 1823static void 1824vge_tx_task(arg, npending) 1825 void *arg; 1826 int npending; 1827{ 1828 struct ifnet *ifp; 1829 1830 ifp = arg; 1831 vge_start(ifp); 1832 1833 return; 1834} 1835 1836/* 1837 * Main transmit routine. 1838 */ 1839 1840static void 1841vge_start(ifp) 1842 struct ifnet *ifp; 1843{ 1844 struct vge_softc *sc; 1845 struct mbuf *m_head = NULL; 1846 int idx, pidx = 0; 1847 1848 sc = ifp->if_softc; 1849 VGE_LOCK(sc); 1850 1851 if (!sc->vge_link || ifp->if_drv_flags & IFF_DRV_OACTIVE) { 1852 VGE_UNLOCK(sc); 1853 return; 1854 } 1855 1856#if __FreeBSD_version < 502114 1857 if (ifp->if_snd.ifq_head == NULL) { 1858#else 1859 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 1860#endif 1861 VGE_UNLOCK(sc); 1862 return; 1863 } 1864 1865 idx = sc->vge_ldata.vge_tx_prodidx; 1866 1867 pidx = idx - 1; 1868 if (pidx < 0) 1869 pidx = VGE_TX_DESC_CNT - 1; 1870 1871 1872 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1873#if __FreeBSD_version < 502114 1874 IF_DEQUEUE(&ifp->if_snd, m_head); 1875#else 1876 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1877#endif 1878 if (m_head == NULL) 1879 break; 1880 1881 if (vge_encap(sc, m_head, idx)) { 1882#if __FreeBSD_version >= 502114 1883 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1884#else 1885 IF_PREPEND(&ifp->if_snd, m_head); 1886#endif 1887 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1888 break; 1889 } 1890 1891 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1892 htole16(VGE_TXDESC_Q); 1893 1894 pidx = idx; 1895 VGE_TX_DESC_INC(idx); 1896 1897 /* 1898 * If there's a BPF listener, bounce a copy of this frame 1899 * to him. 1900 */ 1901 BPF_MTAP(ifp, m_head); 1902 } 1903 1904 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1905 VGE_UNLOCK(sc); 1906 return; 1907 } 1908 1909 /* Flush the TX descriptors */ 1910 1911 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1912 sc->vge_ldata.vge_tx_list_map, 1913 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1914 1915 /* Issue a transmit command. */ 1916 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1917 1918 sc->vge_ldata.vge_tx_prodidx = idx; 1919 1920 /* 1921 * Use the countdown timer for interrupt moderation. 1922 * 'TX done' interrupts are disabled. Instead, we reset the 1923 * countdown timer, which will begin counting until it hits 1924 * the value in the SSTIMER register, and then trigger an 1925 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1926 * the timer count is reloaded. Only when the transmitter 1927 * is idle will the timer hit 0 and an interrupt fire. 1928 */ 1929 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1930 1931 VGE_UNLOCK(sc); 1932 1933 /* 1934 * Set a timeout in case the chip goes out to lunch. 1935 */ 1936 ifp->if_timer = 5; 1937 1938 return; 1939} 1940 1941static void 1942vge_init(xsc) 1943 void *xsc; 1944{ 1945 struct vge_softc *sc = xsc; 1946 struct ifnet *ifp = sc->vge_ifp; 1947 struct mii_data *mii; 1948 int i; 1949 1950 VGE_LOCK(sc); 1951 mii = device_get_softc(sc->vge_miibus); 1952 1953 /* 1954 * Cancel pending I/O and free all RX/TX buffers. 1955 */ 1956 vge_stop(sc); 1957 vge_reset(sc); 1958 1959 /* 1960 * Initialize the RX and TX descriptors and mbufs. 1961 */ 1962 1963 vge_rx_list_init(sc); 1964 vge_tx_list_init(sc); 1965 1966 /* Set our station address */ 1967 for (i = 0; i < ETHER_ADDR_LEN; i++) 1968 CSR_WRITE_1(sc, VGE_PAR0 + i, IFP2ENADDR(sc->vge_ifp)[i]); 1969 1970 /* 1971 * Set receive FIFO threshold. Also allow transmission and 1972 * reception of VLAN tagged frames. 1973 */ 1974 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1975 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1976 1977 /* Set DMA burst length */ 1978 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1979 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1980 1981 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1982 1983 /* Set collision backoff algorithm */ 1984 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1985 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1986 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1987 1988 /* Disable LPSEL field in priority resolution */ 1989 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1990 1991 /* 1992 * Load the addresses of the DMA queues into the chip. 1993 * Note that we only use one transmit queue. 1994 */ 1995 1996 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 1997 VGE_ADDR_LO(sc->vge_ldata.vge_tx_list_addr)); 1998 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 1999 2000 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 2001 VGE_ADDR_LO(sc->vge_ldata.vge_rx_list_addr)); 2002 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 2003 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 2004 2005 /* Enable and wake up the RX descriptor queue */ 2006 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 2007 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 2008 2009 /* Enable the TX descriptor queue */ 2010 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 2011 2012 /* Set up the receive filter -- allow large frames for VLANs. */ 2013 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 2014 2015 /* If we want promiscuous mode, set the allframes bit. */ 2016 if (ifp->if_flags & IFF_PROMISC) { 2017 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 2018 } 2019 2020 /* Set capture broadcast bit to capture broadcast frames. */ 2021 if (ifp->if_flags & IFF_BROADCAST) { 2022 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 2023 } 2024 2025 /* Set multicast bit to capture multicast frames. */ 2026 if (ifp->if_flags & IFF_MULTICAST) { 2027 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 2028 } 2029 2030 /* Init the cam filter. */ 2031 vge_cam_clear(sc); 2032 2033 /* Init the multicast filter. */ 2034 vge_setmulti(sc); 2035 2036 /* Enable flow control */ 2037 2038 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 2039 2040 /* Enable jumbo frame reception (if desired) */ 2041 2042 /* Start the MAC. */ 2043 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 2044 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 2045 CSR_WRITE_1(sc, VGE_CRS0, 2046 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 2047 2048 /* 2049 * Configure one-shot timer for microsecond 2050 * resulution and load it for 500 usecs. 2051 */ 2052 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 2053 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 2054 2055 /* 2056 * Configure interrupt moderation for receive. Enable 2057 * the holdoff counter and load it, and set the RX 2058 * suppression count to the number of descriptors we 2059 * want to allow before triggering an interrupt. 2060 * The holdoff timer is in units of 20 usecs. 2061 */ 2062 2063#ifdef notyet 2064 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 2065 /* Select the interrupt holdoff timer page. */ 2066 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2067 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 2068 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 2069 2070 /* Enable use of the holdoff timer. */ 2071 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 2072 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 2073 2074 /* Select the RX suppression threshold page. */ 2075 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2076 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 2077 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 2078 2079 /* Restore the page select bits. */ 2080 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2081 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 2082#endif 2083 2084#ifdef DEVICE_POLLING 2085 /* 2086 * Disable interrupts if we are polling. 2087 */ 2088 if (ifp->if_capenable & IFCAP_POLLING) { 2089 CSR_WRITE_4(sc, VGE_IMR, 0); 2090 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2091 } else /* otherwise ... */ 2092#endif 2093 { 2094 /* 2095 * Enable interrupts. 2096 */ 2097 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2098 CSR_WRITE_4(sc, VGE_ISR, 0); 2099 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2100 } 2101 2102 mii_mediachg(mii); 2103 2104 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2105 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2106 2107 sc->vge_if_flags = 0; 2108 sc->vge_link = 0; 2109 2110 VGE_UNLOCK(sc); 2111 2112 return; 2113} 2114 2115/* 2116 * Set media options. 2117 */ 2118static int 2119vge_ifmedia_upd(ifp) 2120 struct ifnet *ifp; 2121{ 2122 struct vge_softc *sc; 2123 struct mii_data *mii; 2124 2125 sc = ifp->if_softc; 2126 mii = device_get_softc(sc->vge_miibus); 2127 mii_mediachg(mii); 2128 2129 return (0); 2130} 2131 2132/* 2133 * Report current media status. 2134 */ 2135static void 2136vge_ifmedia_sts(ifp, ifmr) 2137 struct ifnet *ifp; 2138 struct ifmediareq *ifmr; 2139{ 2140 struct vge_softc *sc; 2141 struct mii_data *mii; 2142 2143 sc = ifp->if_softc; 2144 mii = device_get_softc(sc->vge_miibus); 2145 2146 mii_pollstat(mii); 2147 ifmr->ifm_active = mii->mii_media_active; 2148 ifmr->ifm_status = mii->mii_media_status; 2149 2150 return; 2151} 2152 2153static void 2154vge_miibus_statchg(dev) 2155 device_t dev; 2156{ 2157 struct vge_softc *sc; 2158 struct mii_data *mii; 2159 struct ifmedia_entry *ife; 2160 2161 sc = device_get_softc(dev); 2162 mii = device_get_softc(sc->vge_miibus); 2163 ife = mii->mii_media.ifm_cur; 2164 2165 /* 2166 * If the user manually selects a media mode, we need to turn 2167 * on the forced MAC mode bit in the DIAGCTL register. If the 2168 * user happens to choose a full duplex mode, we also need to 2169 * set the 'force full duplex' bit. This applies only to 2170 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2171 * mode is disabled, and in 1000baseT mode, full duplex is 2172 * always implied, so we turn on the forced mode bit but leave 2173 * the FDX bit cleared. 2174 */ 2175 2176 switch (IFM_SUBTYPE(ife->ifm_media)) { 2177 case IFM_AUTO: 2178 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2179 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2180 break; 2181 case IFM_1000_T: 2182 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2183 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2184 break; 2185 case IFM_100_TX: 2186 case IFM_10_T: 2187 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2188 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2189 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2190 } else { 2191 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2192 } 2193 break; 2194 default: 2195 device_printf(dev, "unknown media type: %x\n", 2196 IFM_SUBTYPE(ife->ifm_media)); 2197 break; 2198 } 2199 2200 return; 2201} 2202 2203static int 2204vge_ioctl(ifp, command, data) 2205 struct ifnet *ifp; 2206 u_long command; 2207 caddr_t data; 2208{ 2209 struct vge_softc *sc = ifp->if_softc; 2210 struct ifreq *ifr = (struct ifreq *) data; 2211 struct mii_data *mii; 2212 int error = 0; 2213 2214 switch (command) { 2215 case SIOCSIFMTU: 2216 if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2217 error = EINVAL; 2218 ifp->if_mtu = ifr->ifr_mtu; 2219 break; 2220 case SIOCSIFFLAGS: 2221 if (ifp->if_flags & IFF_UP) { 2222 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2223 ifp->if_flags & IFF_PROMISC && 2224 !(sc->vge_if_flags & IFF_PROMISC)) { 2225 CSR_SETBIT_1(sc, VGE_RXCTL, 2226 VGE_RXCTL_RX_PROMISC); 2227 vge_setmulti(sc); 2228 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2229 !(ifp->if_flags & IFF_PROMISC) && 2230 sc->vge_if_flags & IFF_PROMISC) { 2231 CSR_CLRBIT_1(sc, VGE_RXCTL, 2232 VGE_RXCTL_RX_PROMISC); 2233 vge_setmulti(sc); 2234 } else 2235 vge_init(sc); 2236 } else { 2237 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2238 vge_stop(sc); 2239 } 2240 sc->vge_if_flags = ifp->if_flags; 2241 break; 2242 case SIOCADDMULTI: 2243 case SIOCDELMULTI: 2244 vge_setmulti(sc); 2245 break; 2246 case SIOCGIFMEDIA: 2247 case SIOCSIFMEDIA: 2248 mii = device_get_softc(sc->vge_miibus); 2249 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2250 break; 2251 case SIOCSIFCAP: 2252 { 2253 int mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2254#ifdef DEVICE_POLLING 2255 if (mask & IFCAP_POLLING) { 2256 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2257 error = ether_poll_register(vge_poll, ifp); 2258 if (error) 2259 return(error); 2260 VGE_LOCK(sc); 2261 /* Disable interrupts */ 2262 CSR_WRITE_4(sc, VGE_IMR, 0); 2263 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2264 ifp->if_capenable |= IFCAP_POLLING; 2265 VGE_UNLOCK(sc); 2266 } else { 2267 error = ether_poll_deregister(ifp); 2268 /* Enable interrupts. */ 2269 VGE_LOCK(sc); 2270 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2271 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2272 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2273 ifp->if_capenable &= ~IFCAP_POLLING; 2274 VGE_UNLOCK(sc); 2275 } 2276 } 2277#endif /* DEVICE_POLLING */ 2278 if (mask & IFCAP_HWCSUM) { 2279 ifp->if_capenable |= ifr->ifr_reqcap & (IFCAP_HWCSUM); 2280 if (ifp->if_capenable & IFCAP_TXCSUM) 2281 ifp->if_hwassist = VGE_CSUM_FEATURES; 2282 else 2283 ifp->if_hwassist = 0; 2284 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2285 vge_init(sc); 2286 } 2287 } 2288 break; 2289 default: 2290 error = ether_ioctl(ifp, command, data); 2291 break; 2292 } 2293 2294 return (error); 2295} 2296 2297static void 2298vge_watchdog(ifp) 2299 struct ifnet *ifp; 2300{ 2301 struct vge_softc *sc; 2302 2303 sc = ifp->if_softc; 2304 VGE_LOCK(sc); 2305 printf("vge%d: watchdog timeout\n", sc->vge_unit); 2306 ifp->if_oerrors++; 2307 2308 vge_txeof(sc); 2309 vge_rxeof(sc); 2310 2311 vge_init(sc); 2312 2313 VGE_UNLOCK(sc); 2314 2315 return; 2316} 2317 2318/* 2319 * Stop the adapter and free any mbufs allocated to the 2320 * RX and TX lists. 2321 */ 2322static void 2323vge_stop(sc) 2324 struct vge_softc *sc; 2325{ 2326 register int i; 2327 struct ifnet *ifp; 2328 2329 VGE_LOCK(sc); 2330 ifp = sc->vge_ifp; 2331 ifp->if_timer = 0; 2332 2333 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2334 2335 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2336 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2337 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2338 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2339 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2340 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2341 2342 if (sc->vge_head != NULL) { 2343 m_freem(sc->vge_head); 2344 sc->vge_head = sc->vge_tail = NULL; 2345 } 2346 2347 /* Free the TX list buffers. */ 2348 2349 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 2350 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 2351 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2352 sc->vge_ldata.vge_tx_dmamap[i]); 2353 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 2354 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 2355 } 2356 } 2357 2358 /* Free the RX list buffers. */ 2359 2360 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 2361 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 2362 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2363 sc->vge_ldata.vge_rx_dmamap[i]); 2364 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 2365 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 2366 } 2367 } 2368 2369 VGE_UNLOCK(sc); 2370 2371 return; 2372} 2373 2374/* 2375 * Device suspend routine. Stop the interface and save some PCI 2376 * settings in case the BIOS doesn't restore them properly on 2377 * resume. 2378 */ 2379static int 2380vge_suspend(dev) 2381 device_t dev; 2382{ 2383 struct vge_softc *sc; 2384 2385 sc = device_get_softc(dev); 2386 2387 vge_stop(sc); 2388 2389 sc->suspended = 1; 2390 2391 return (0); 2392} 2393 2394/* 2395 * Device resume routine. Restore some PCI settings in case the BIOS 2396 * doesn't, re-enable busmastering, and restart the interface if 2397 * appropriate. 2398 */ 2399static int 2400vge_resume(dev) 2401 device_t dev; 2402{ 2403 struct vge_softc *sc; 2404 struct ifnet *ifp; 2405 2406 sc = device_get_softc(dev); 2407 ifp = sc->vge_ifp; 2408 2409 /* reenable busmastering */ 2410 pci_enable_busmaster(dev); 2411 pci_enable_io(dev, SYS_RES_MEMORY); 2412 2413 /* reinitialize interface if necessary */ 2414 if (ifp->if_flags & IFF_UP) 2415 vge_init(sc); 2416 2417 sc->suspended = 0; 2418 2419 return (0); 2420} 2421 2422/* 2423 * Stop all chip I/O so that the kernel's probe routines don't 2424 * get confused by errant DMAs when rebooting. 2425 */ 2426static void 2427vge_shutdown(dev) 2428 device_t dev; 2429{ 2430 struct vge_softc *sc; 2431 2432 sc = device_get_softc(dev); 2433 2434 vge_stop(sc); 2435} 2436