if_vge.c revision 147256
1/*- 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/vge/if_vge.c 147256 2005-06-10 16:49:24Z brooks $"); 35 36/* 37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 46 * combines a tri-speed ethernet MAC and PHY, with the following 47 * features: 48 * 49 * o Jumbo frame support up to 16K 50 * o Transmit and receive flow control 51 * o IPv4 checksum offload 52 * o VLAN tag insertion and stripping 53 * o TCP large send 54 * o 64-bit multicast hash table filter 55 * o 64 entry CAM filter 56 * o 16K RX FIFO and 48K TX FIFO memory 57 * o Interrupt moderation 58 * 59 * The VT6122 supports up to four transmit DMA queues. The descriptors 60 * in the transmit ring can address up to 7 data fragments; frames which 61 * span more than 7 data buffers must be coalesced, but in general the 62 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 63 * long. The receive descriptors address only a single buffer. 64 * 65 * There are two peculiar design issues with the VT6122. One is that 66 * receive data buffers must be aligned on a 32-bit boundary. This is 67 * not a problem where the VT6122 is used as a LOM device in x86-based 68 * systems, but on architectures that generate unaligned access traps, we 69 * have to do some copying. 70 * 71 * The other issue has to do with the way 64-bit addresses are handled. 72 * The DMA descriptors only allow you to specify 48 bits of addressing 73 * information. The remaining 16 bits are specified using one of the 74 * I/O registers. If you only have a 32-bit system, then this isn't 75 * an issue, but if you have a 64-bit system and more than 4GB of 76 * memory, you must have to make sure your network data buffers reside 77 * in the same 48-bit 'segment.' 78 * 79 * Special thanks to Ryan Fu at VIA Networking for providing documentation 80 * and sample NICs for testing. 81 */ 82 83#include <sys/param.h> 84#include <sys/endian.h> 85#include <sys/systm.h> 86#include <sys/sockio.h> 87#include <sys/mbuf.h> 88#include <sys/malloc.h> 89#include <sys/module.h> 90#include <sys/kernel.h> 91#include <sys/socket.h> 92#include <sys/taskqueue.h> 93 94#include <net/if.h> 95#include <net/if_arp.h> 96#include <net/ethernet.h> 97#include <net/if_dl.h> 98#include <net/if_media.h> 99#include <net/if_types.h> 100#include <net/if_vlan_var.h> 101 102#include <net/bpf.h> 103 104#include <machine/bus.h> 105#include <machine/resource.h> 106#include <sys/bus.h> 107#include <sys/rman.h> 108 109#include <dev/mii/mii.h> 110#include <dev/mii/miivar.h> 111 112#include <dev/pci/pcireg.h> 113#include <dev/pci/pcivar.h> 114 115MODULE_DEPEND(vge, pci, 1, 1, 1); 116MODULE_DEPEND(vge, ether, 1, 1, 1); 117MODULE_DEPEND(vge, miibus, 1, 1, 1); 118 119/* "controller miibus0" required. See GENERIC if you get errors here. */ 120#include "miibus_if.h" 121 122#include <dev/vge/if_vgereg.h> 123#include <dev/vge/if_vgevar.h> 124 125#define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 126 127/* 128 * Various supported device vendors/types and their names. 129 */ 130static struct vge_type vge_devs[] = { 131 { VIA_VENDORID, VIA_DEVICEID_61XX, 132 "VIA Networking Gigabit Ethernet" }, 133 { 0, 0, NULL } 134}; 135 136static int vge_probe (device_t); 137static int vge_attach (device_t); 138static int vge_detach (device_t); 139 140static int vge_encap (struct vge_softc *, struct mbuf *, int); 141 142static void vge_dma_map_addr (void *, bus_dma_segment_t *, int, int); 143static void vge_dma_map_rx_desc (void *, bus_dma_segment_t *, int, 144 bus_size_t, int); 145static void vge_dma_map_tx_desc (void *, bus_dma_segment_t *, int, 146 bus_size_t, int); 147static int vge_allocmem (device_t, struct vge_softc *); 148static int vge_newbuf (struct vge_softc *, int, struct mbuf *); 149static int vge_rx_list_init (struct vge_softc *); 150static int vge_tx_list_init (struct vge_softc *); 151#ifdef VGE_FIXUP_RX 152static __inline void vge_fixup_rx 153 (struct mbuf *); 154#endif 155static void vge_rxeof (struct vge_softc *); 156static void vge_txeof (struct vge_softc *); 157static void vge_intr (void *); 158static void vge_tick (void *); 159static void vge_tx_task (void *, int); 160static void vge_start (struct ifnet *); 161static int vge_ioctl (struct ifnet *, u_long, caddr_t); 162static void vge_init (void *); 163static void vge_stop (struct vge_softc *); 164static void vge_watchdog (struct ifnet *); 165static int vge_suspend (device_t); 166static int vge_resume (device_t); 167static void vge_shutdown (device_t); 168static int vge_ifmedia_upd (struct ifnet *); 169static void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 170 171#ifdef VGE_EEPROM 172static void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 173#endif 174static void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 175 176static void vge_miipoll_start (struct vge_softc *); 177static void vge_miipoll_stop (struct vge_softc *); 178static int vge_miibus_readreg (device_t, int, int); 179static int vge_miibus_writereg (device_t, int, int, int); 180static void vge_miibus_statchg (device_t); 181 182static void vge_cam_clear (struct vge_softc *); 183static int vge_cam_set (struct vge_softc *, uint8_t *); 184#if __FreeBSD_version < 502113 185static uint32_t vge_mchash (uint8_t *); 186#endif 187static void vge_setmulti (struct vge_softc *); 188static void vge_reset (struct vge_softc *); 189 190#define VGE_PCI_LOIO 0x10 191#define VGE_PCI_LOMEM 0x14 192 193static device_method_t vge_methods[] = { 194 /* Device interface */ 195 DEVMETHOD(device_probe, vge_probe), 196 DEVMETHOD(device_attach, vge_attach), 197 DEVMETHOD(device_detach, vge_detach), 198 DEVMETHOD(device_suspend, vge_suspend), 199 DEVMETHOD(device_resume, vge_resume), 200 DEVMETHOD(device_shutdown, vge_shutdown), 201 202 /* bus interface */ 203 DEVMETHOD(bus_print_child, bus_generic_print_child), 204 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 205 206 /* MII interface */ 207 DEVMETHOD(miibus_readreg, vge_miibus_readreg), 208 DEVMETHOD(miibus_writereg, vge_miibus_writereg), 209 DEVMETHOD(miibus_statchg, vge_miibus_statchg), 210 211 { 0, 0 } 212}; 213 214static driver_t vge_driver = { 215 "vge", 216 vge_methods, 217 sizeof(struct vge_softc) 218}; 219 220static devclass_t vge_devclass; 221 222DRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0); 223DRIVER_MODULE(vge, cardbus, vge_driver, vge_devclass, 0, 0); 224DRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0); 225 226#ifdef VGE_EEPROM 227/* 228 * Read a word of data stored in the EEPROM at address 'addr.' 229 */ 230static void 231vge_eeprom_getword(sc, addr, dest) 232 struct vge_softc *sc; 233 int addr; 234 u_int16_t *dest; 235{ 236 register int i; 237 u_int16_t word = 0; 238 239 /* 240 * Enter EEPROM embedded programming mode. In order to 241 * access the EEPROM at all, we first have to set the 242 * EELOAD bit in the CHIPCFG2 register. 243 */ 244 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 245 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 246 247 /* Select the address of the word we want to read */ 248 CSR_WRITE_1(sc, VGE_EEADDR, addr); 249 250 /* Issue read command */ 251 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 252 253 /* Wait for the done bit to be set. */ 254 for (i = 0; i < VGE_TIMEOUT; i++) { 255 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 256 break; 257 } 258 259 if (i == VGE_TIMEOUT) { 260 device_printf(sc->vge_dev, "EEPROM read timed out\n"); 261 *dest = 0; 262 return; 263 } 264 265 /* Read the result */ 266 word = CSR_READ_2(sc, VGE_EERDDAT); 267 268 /* Turn off EEPROM access mode. */ 269 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 270 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 271 272 *dest = word; 273 274 return; 275} 276#endif 277 278/* 279 * Read a sequence of words from the EEPROM. 280 */ 281static void 282vge_read_eeprom(sc, dest, off, cnt, swap) 283 struct vge_softc *sc; 284 caddr_t dest; 285 int off; 286 int cnt; 287 int swap; 288{ 289 int i; 290#ifdef VGE_EEPROM 291 u_int16_t word = 0, *ptr; 292 293 for (i = 0; i < cnt; i++) { 294 vge_eeprom_getword(sc, off + i, &word); 295 ptr = (u_int16_t *)(dest + (i * 2)); 296 if (swap) 297 *ptr = ntohs(word); 298 else 299 *ptr = word; 300 } 301#else 302 for (i = 0; i < ETHER_ADDR_LEN; i++) 303 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 304#endif 305} 306 307static void 308vge_miipoll_stop(sc) 309 struct vge_softc *sc; 310{ 311 int i; 312 313 CSR_WRITE_1(sc, VGE_MIICMD, 0); 314 315 for (i = 0; i < VGE_TIMEOUT; i++) { 316 DELAY(1); 317 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 318 break; 319 } 320 321 if (i == VGE_TIMEOUT) 322 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 323 324 return; 325} 326 327static void 328vge_miipoll_start(sc) 329 struct vge_softc *sc; 330{ 331 int i; 332 333 /* First, make sure we're idle. */ 334 335 CSR_WRITE_1(sc, VGE_MIICMD, 0); 336 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 337 338 for (i = 0; i < VGE_TIMEOUT; i++) { 339 DELAY(1); 340 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 341 break; 342 } 343 344 if (i == VGE_TIMEOUT) { 345 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 346 return; 347 } 348 349 /* Now enable auto poll mode. */ 350 351 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 352 353 /* And make sure it started. */ 354 355 for (i = 0; i < VGE_TIMEOUT; i++) { 356 DELAY(1); 357 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 358 break; 359 } 360 361 if (i == VGE_TIMEOUT) 362 device_printf(sc->vge_dev, "failed to start MII autopoll\n"); 363 364 return; 365} 366 367static int 368vge_miibus_readreg(dev, phy, reg) 369 device_t dev; 370 int phy, reg; 371{ 372 struct vge_softc *sc; 373 int i; 374 u_int16_t rval = 0; 375 376 sc = device_get_softc(dev); 377 378 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 379 return(0); 380 381 VGE_LOCK(sc); 382 vge_miipoll_stop(sc); 383 384 /* Specify the register we want to read. */ 385 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 386 387 /* Issue read command. */ 388 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 389 390 /* Wait for the read command bit to self-clear. */ 391 for (i = 0; i < VGE_TIMEOUT; i++) { 392 DELAY(1); 393 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 394 break; 395 } 396 397 if (i == VGE_TIMEOUT) 398 device_printf(sc->vge_dev, "MII read timed out\n"); 399 else 400 rval = CSR_READ_2(sc, VGE_MIIDATA); 401 402 vge_miipoll_start(sc); 403 VGE_UNLOCK(sc); 404 405 return (rval); 406} 407 408static int 409vge_miibus_writereg(dev, phy, reg, data) 410 device_t dev; 411 int phy, reg, data; 412{ 413 struct vge_softc *sc; 414 int i, rval = 0; 415 416 sc = device_get_softc(dev); 417 418 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 419 return(0); 420 421 VGE_LOCK(sc); 422 vge_miipoll_stop(sc); 423 424 /* Specify the register we want to write. */ 425 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 426 427 /* Specify the data we want to write. */ 428 CSR_WRITE_2(sc, VGE_MIIDATA, data); 429 430 /* Issue write command. */ 431 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 432 433 /* Wait for the write command bit to self-clear. */ 434 for (i = 0; i < VGE_TIMEOUT; i++) { 435 DELAY(1); 436 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 437 break; 438 } 439 440 if (i == VGE_TIMEOUT) { 441 device_printf(sc->vge_dev, "MII write timed out\n"); 442 rval = EIO; 443 } 444 445 vge_miipoll_start(sc); 446 VGE_UNLOCK(sc); 447 448 return (rval); 449} 450 451static void 452vge_cam_clear(sc) 453 struct vge_softc *sc; 454{ 455 int i; 456 457 /* 458 * Turn off all the mask bits. This tells the chip 459 * that none of the entries in the CAM filter are valid. 460 * desired entries will be enabled as we fill the filter in. 461 */ 462 463 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 464 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 465 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 466 for (i = 0; i < 8; i++) 467 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 468 469 /* Clear the VLAN filter too. */ 470 471 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 472 for (i = 0; i < 8; i++) 473 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 474 475 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 476 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 477 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 478 479 sc->vge_camidx = 0; 480 481 return; 482} 483 484static int 485vge_cam_set(sc, addr) 486 struct vge_softc *sc; 487 uint8_t *addr; 488{ 489 int i, error = 0; 490 491 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 492 return(ENOSPC); 493 494 /* Select the CAM data page. */ 495 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 496 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 497 498 /* Set the filter entry we want to update and enable writing. */ 499 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 500 501 /* Write the address to the CAM registers */ 502 for (i = 0; i < ETHER_ADDR_LEN; i++) 503 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 504 505 /* Issue a write command. */ 506 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 507 508 /* Wake for it to clear. */ 509 for (i = 0; i < VGE_TIMEOUT; i++) { 510 DELAY(1); 511 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 512 break; 513 } 514 515 if (i == VGE_TIMEOUT) { 516 device_printf(sc->vge_dev, "setting CAM filter failed\n"); 517 error = EIO; 518 goto fail; 519 } 520 521 /* Select the CAM mask page. */ 522 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 523 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 524 525 /* Set the mask bit that enables this filter. */ 526 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 527 1<<(sc->vge_camidx & 7)); 528 529 sc->vge_camidx++; 530 531fail: 532 /* Turn off access to CAM. */ 533 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 534 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 535 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 536 537 return (error); 538} 539 540#if __FreeBSD_version < 502113 541static uint32_t 542vge_mchash(addr) 543 uint8_t *addr; 544{ 545 uint32_t crc, carry; 546 int idx, bit; 547 uint8_t data; 548 549 /* Compute CRC for the address value. */ 550 crc = 0xFFFFFFFF; /* initial value */ 551 552 for (idx = 0; idx < 6; idx++) { 553 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 554 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 555 crc <<= 1; 556 if (carry) 557 crc = (crc ^ 0x04c11db6) | carry; 558 } 559 } 560 561 return(crc); 562} 563#endif 564 565/* 566 * Program the multicast filter. We use the 64-entry CAM filter 567 * for perfect filtering. If there's more than 64 multicast addresses, 568 * we use the hash filter insted. 569 */ 570static void 571vge_setmulti(sc) 572 struct vge_softc *sc; 573{ 574 struct ifnet *ifp; 575 int error = 0/*, h = 0*/; 576 struct ifmultiaddr *ifma; 577 u_int32_t h, hashes[2] = { 0, 0 }; 578 579 ifp = sc->vge_ifp; 580 581 /* First, zot all the multicast entries. */ 582 vge_cam_clear(sc); 583 CSR_WRITE_4(sc, VGE_MAR0, 0); 584 CSR_WRITE_4(sc, VGE_MAR1, 0); 585 586 /* 587 * If the user wants allmulti or promisc mode, enable reception 588 * of all multicast frames. 589 */ 590 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 591 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 592 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 593 return; 594 } 595 596 /* Now program new ones */ 597 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 598 if (ifma->ifma_addr->sa_family != AF_LINK) 599 continue; 600 error = vge_cam_set(sc, 601 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 602 if (error) 603 break; 604 } 605 606 /* If there were too many addresses, use the hash filter. */ 607 if (error) { 608 vge_cam_clear(sc); 609 610 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 611 if (ifma->ifma_addr->sa_family != AF_LINK) 612 continue; 613#if __FreeBSD_version < 502113 614 h = vge_mchash(LLADDR((struct sockaddr_dl *) 615 ifma->ifma_addr)) >> 26; 616#else 617 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 618 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 619#endif 620 if (h < 32) 621 hashes[0] |= (1 << h); 622 else 623 hashes[1] |= (1 << (h - 32)); 624 } 625 626 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 627 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 628 } 629 630 return; 631} 632 633static void 634vge_reset(sc) 635 struct vge_softc *sc; 636{ 637 register int i; 638 639 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 640 641 for (i = 0; i < VGE_TIMEOUT; i++) { 642 DELAY(5); 643 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 644 break; 645 } 646 647 if (i == VGE_TIMEOUT) { 648 device_printf(sc->vge_dev, "soft reset timed out"); 649 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 650 DELAY(2000); 651 } 652 653 DELAY(5000); 654 655 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 656 657 for (i = 0; i < VGE_TIMEOUT; i++) { 658 DELAY(5); 659 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 660 break; 661 } 662 663 if (i == VGE_TIMEOUT) { 664 device_printf(sc->vge_dev, "EEPROM reload timed out\n"); 665 return; 666 } 667 668 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 669 670 return; 671} 672 673/* 674 * Probe for a VIA gigabit chip. Check the PCI vendor and device 675 * IDs against our list and return a device name if we find a match. 676 */ 677static int 678vge_probe(dev) 679 device_t dev; 680{ 681 struct vge_type *t; 682 struct vge_softc *sc; 683 684 t = vge_devs; 685 sc = device_get_softc(dev); 686 687 while (t->vge_name != NULL) { 688 if ((pci_get_vendor(dev) == t->vge_vid) && 689 (pci_get_device(dev) == t->vge_did)) { 690 device_set_desc(dev, t->vge_name); 691 return (BUS_PROBE_DEFAULT); 692 } 693 t++; 694 } 695 696 return (ENXIO); 697} 698 699static void 700vge_dma_map_rx_desc(arg, segs, nseg, mapsize, error) 701 void *arg; 702 bus_dma_segment_t *segs; 703 int nseg; 704 bus_size_t mapsize; 705 int error; 706{ 707 708 struct vge_dmaload_arg *ctx; 709 struct vge_rx_desc *d = NULL; 710 711 if (error) 712 return; 713 714 ctx = arg; 715 716 /* Signal error to caller if there's too many segments */ 717 if (nseg > ctx->vge_maxsegs) { 718 ctx->vge_maxsegs = 0; 719 return; 720 } 721 722 /* 723 * Map the segment array into descriptors. 724 */ 725 726 d = &ctx->sc->vge_ldata.vge_rx_list[ctx->vge_idx]; 727 728 /* If this descriptor is still owned by the chip, bail. */ 729 730 if (le32toh(d->vge_sts) & VGE_RDSTS_OWN) { 731 device_printf(ctx->sc->vge_dev, 732 "tried to map busy descriptor\n"); 733 ctx->vge_maxsegs = 0; 734 return; 735 } 736 737 d->vge_buflen = htole16(VGE_BUFLEN(segs[0].ds_len) | VGE_RXDESC_I); 738 d->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 739 d->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 740 d->vge_sts = 0; 741 d->vge_ctl = 0; 742 743 ctx->vge_maxsegs = 1; 744 745 return; 746} 747 748static void 749vge_dma_map_tx_desc(arg, segs, nseg, mapsize, error) 750 void *arg; 751 bus_dma_segment_t *segs; 752 int nseg; 753 bus_size_t mapsize; 754 int error; 755{ 756 struct vge_dmaload_arg *ctx; 757 struct vge_tx_desc *d = NULL; 758 struct vge_tx_frag *f; 759 int i = 0; 760 761 if (error) 762 return; 763 764 ctx = arg; 765 766 /* Signal error to caller if there's too many segments */ 767 if (nseg > ctx->vge_maxsegs) { 768 ctx->vge_maxsegs = 0; 769 return; 770 } 771 772 /* Map the segment array into descriptors. */ 773 774 d = &ctx->sc->vge_ldata.vge_tx_list[ctx->vge_idx]; 775 776 /* If this descriptor is still owned by the chip, bail. */ 777 778 if (le32toh(d->vge_sts) & VGE_TDSTS_OWN) { 779 ctx->vge_maxsegs = 0; 780 return; 781 } 782 783 for (i = 0; i < nseg; i++) { 784 f = &d->vge_frag[i]; 785 f->vge_buflen = htole16(VGE_BUFLEN(segs[i].ds_len)); 786 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[i].ds_addr)); 787 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[i].ds_addr) & 0xFFFF); 788 } 789 790 /* Argh. This chip does not autopad short frames */ 791 792 if (ctx->vge_m0->m_pkthdr.len < VGE_MIN_FRAMELEN) { 793 f = &d->vge_frag[i]; 794 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 795 ctx->vge_m0->m_pkthdr.len)); 796 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 797 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 798 ctx->vge_m0->m_pkthdr.len = VGE_MIN_FRAMELEN; 799 i++; 800 } 801 802 /* 803 * When telling the chip how many segments there are, we 804 * must use nsegs + 1 instead of just nsegs. Darned if I 805 * know why. 806 */ 807 i++; 808 809 d->vge_sts = ctx->vge_m0->m_pkthdr.len << 16; 810 d->vge_ctl = ctx->vge_flags|(i << 28)|VGE_TD_LS_NORM; 811 812 if (ctx->vge_m0->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 813 d->vge_ctl |= VGE_TDCTL_JUMBO; 814 815 ctx->vge_maxsegs = nseg; 816 817 return; 818} 819 820/* 821 * Map a single buffer address. 822 */ 823 824static void 825vge_dma_map_addr(arg, segs, nseg, error) 826 void *arg; 827 bus_dma_segment_t *segs; 828 int nseg; 829 int error; 830{ 831 bus_addr_t *addr; 832 833 if (error) 834 return; 835 836 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 837 addr = arg; 838 *addr = segs->ds_addr; 839 840 return; 841} 842 843static int 844vge_allocmem(dev, sc) 845 device_t dev; 846 struct vge_softc *sc; 847{ 848 int error; 849 int nseg; 850 int i; 851 852 /* 853 * Allocate map for RX mbufs. 854 */ 855 nseg = 32; 856 error = bus_dma_tag_create(sc->vge_parent_tag, ETHER_ALIGN, 0, 857 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 858 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 859 NULL, NULL, &sc->vge_ldata.vge_mtag); 860 if (error) { 861 device_printf(dev, "could not allocate dma tag\n"); 862 return (ENOMEM); 863 } 864 865 /* 866 * Allocate map for TX descriptor list. 867 */ 868 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 869 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 870 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 871 NULL, NULL, &sc->vge_ldata.vge_tx_list_tag); 872 if (error) { 873 device_printf(dev, "could not allocate dma tag\n"); 874 return (ENOMEM); 875 } 876 877 /* Allocate DMA'able memory for the TX ring */ 878 879 error = bus_dmamem_alloc(sc->vge_ldata.vge_tx_list_tag, 880 (void **)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 881 &sc->vge_ldata.vge_tx_list_map); 882 if (error) 883 return (ENOMEM); 884 885 /* Load the map for the TX ring. */ 886 887 error = bus_dmamap_load(sc->vge_ldata.vge_tx_list_tag, 888 sc->vge_ldata.vge_tx_list_map, sc->vge_ldata.vge_tx_list, 889 VGE_TX_LIST_SZ, vge_dma_map_addr, 890 &sc->vge_ldata.vge_tx_list_addr, BUS_DMA_NOWAIT); 891 892 /* Create DMA maps for TX buffers */ 893 894 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 895 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 896 &sc->vge_ldata.vge_tx_dmamap[i]); 897 if (error) { 898 device_printf(dev, "can't create DMA map for TX\n"); 899 return (ENOMEM); 900 } 901 } 902 903 /* 904 * Allocate map for RX descriptor list. 905 */ 906 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 907 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 908 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 909 NULL, NULL, &sc->vge_ldata.vge_rx_list_tag); 910 if (error) { 911 device_printf(dev, "could not allocate dma tag\n"); 912 return (ENOMEM); 913 } 914 915 /* Allocate DMA'able memory for the RX ring */ 916 917 error = bus_dmamem_alloc(sc->vge_ldata.vge_rx_list_tag, 918 (void **)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 919 &sc->vge_ldata.vge_rx_list_map); 920 if (error) 921 return (ENOMEM); 922 923 /* Load the map for the RX ring. */ 924 925 error = bus_dmamap_load(sc->vge_ldata.vge_rx_list_tag, 926 sc->vge_ldata.vge_rx_list_map, sc->vge_ldata.vge_rx_list, 927 VGE_TX_LIST_SZ, vge_dma_map_addr, 928 &sc->vge_ldata.vge_rx_list_addr, BUS_DMA_NOWAIT); 929 930 /* Create DMA maps for RX buffers */ 931 932 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 933 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 934 &sc->vge_ldata.vge_rx_dmamap[i]); 935 if (error) { 936 device_printf(dev, "can't create DMA map for RX\n"); 937 return (ENOMEM); 938 } 939 } 940 941 return (0); 942} 943 944/* 945 * Attach the interface. Allocate softc structures, do ifmedia 946 * setup and ethernet/BPF attach. 947 */ 948static int 949vge_attach(dev) 950 device_t dev; 951{ 952 u_char eaddr[ETHER_ADDR_LEN]; 953 struct vge_softc *sc; 954 struct ifnet *ifp; 955 int unit, error = 0, rid; 956 957 sc = device_get_softc(dev); 958 unit = device_get_unit(dev); 959 sc->vge_dev = dev; 960 961 mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 962 MTX_DEF | MTX_RECURSE); 963 /* 964 * Map control/status registers. 965 */ 966 pci_enable_busmaster(dev); 967 968 rid = VGE_PCI_LOMEM; 969 sc->vge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 970 0, ~0, 1, RF_ACTIVE); 971 972 if (sc->vge_res == NULL) { 973 printf ("vge%d: couldn't map ports/memory\n", unit); 974 error = ENXIO; 975 goto fail; 976 } 977 978 sc->vge_btag = rman_get_bustag(sc->vge_res); 979 sc->vge_bhandle = rman_get_bushandle(sc->vge_res); 980 981 /* Allocate interrupt */ 982 rid = 0; 983 sc->vge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 984 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE); 985 986 if (sc->vge_irq == NULL) { 987 printf("vge%d: couldn't map interrupt\n", unit); 988 error = ENXIO; 989 goto fail; 990 } 991 992 /* Reset the adapter. */ 993 vge_reset(sc); 994 995 /* 996 * Get station address from the EEPROM. 997 */ 998 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 999 1000 sc->vge_unit = unit; 1001 1002#if __FreeBSD_version < 502113 1003 printf("vge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1004#endif 1005 1006 /* 1007 * Allocate the parent bus DMA tag appropriate for PCI. 1008 */ 1009#define VGE_NSEG_NEW 32 1010 error = bus_dma_tag_create(NULL, /* parent */ 1011 1, 0, /* alignment, boundary */ 1012 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1013 BUS_SPACE_MAXADDR, /* highaddr */ 1014 NULL, NULL, /* filter, filterarg */ 1015 MAXBSIZE, VGE_NSEG_NEW, /* maxsize, nsegments */ 1016 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1017 BUS_DMA_ALLOCNOW, /* flags */ 1018 NULL, NULL, /* lockfunc, lockarg */ 1019 &sc->vge_parent_tag); 1020 if (error) 1021 goto fail; 1022 1023 error = vge_allocmem(dev, sc); 1024 1025 if (error) 1026 goto fail; 1027 1028 /* Do MII setup */ 1029 if (mii_phy_probe(dev, &sc->vge_miibus, 1030 vge_ifmedia_upd, vge_ifmedia_sts)) { 1031 printf("vge%d: MII without any phy!\n", sc->vge_unit); 1032 error = ENXIO; 1033 goto fail; 1034 } 1035 1036 ifp = sc->vge_ifp = if_alloc(IFT_ETHER); 1037 if (ifp == NULL) { 1038 printf("vge%d: can not if_alloc()\n", sc->vge_unit); 1039 error = ENOSPC; 1040 goto fail; 1041 } 1042 ifp->if_softc = sc; 1043 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1044 ifp->if_mtu = ETHERMTU; 1045 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1046 ifp->if_ioctl = vge_ioctl; 1047 ifp->if_capabilities = IFCAP_VLAN_MTU; 1048 ifp->if_start = vge_start; 1049 ifp->if_hwassist = VGE_CSUM_FEATURES; 1050 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1051#ifdef DEVICE_POLLING 1052#ifdef IFCAP_POLLING 1053 ifp->if_capabilities |= IFCAP_POLLING; 1054#endif 1055#endif 1056 ifp->if_watchdog = vge_watchdog; 1057 ifp->if_init = vge_init; 1058 ifp->if_baudrate = 1000000000; 1059 ifp->if_snd.ifq_maxlen = VGE_IFQ_MAXLEN; 1060 ifp->if_capenable = ifp->if_capabilities; 1061 1062 TASK_INIT(&sc->vge_txtask, 0, vge_tx_task, ifp); 1063 1064 /* 1065 * Call MI attach routine. 1066 */ 1067 ether_ifattach(ifp, eaddr); 1068 1069 /* Hook interrupt last to avoid having to lock softc */ 1070 error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE, 1071 vge_intr, sc, &sc->vge_intrhand); 1072 1073 if (error) { 1074 printf("vge%d: couldn't set up irq\n", unit); 1075 ether_ifdetach(ifp); 1076 goto fail; 1077 } 1078 1079fail: 1080 if (error) 1081 vge_detach(dev); 1082 1083 return (error); 1084} 1085 1086/* 1087 * Shutdown hardware and free up resources. This can be called any 1088 * time after the mutex has been initialized. It is called in both 1089 * the error case in attach and the normal detach case so it needs 1090 * to be careful about only freeing resources that have actually been 1091 * allocated. 1092 */ 1093static int 1094vge_detach(dev) 1095 device_t dev; 1096{ 1097 struct vge_softc *sc; 1098 struct ifnet *ifp; 1099 int i; 1100 1101 sc = device_get_softc(dev); 1102 KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized")); 1103 ifp = sc->vge_ifp; 1104 1105 /* These should only be active if attach succeeded */ 1106 if (device_is_attached(dev)) { 1107 vge_stop(sc); 1108 /* 1109 * Force off the IFF_UP flag here, in case someone 1110 * still had a BPF descriptor attached to this 1111 * interface. If they do, ether_ifattach() will cause 1112 * the BPF code to try and clear the promisc mode 1113 * flag, which will bubble down to vge_ioctl(), 1114 * which will try to call vge_init() again. This will 1115 * turn the NIC back on and restart the MII ticker, 1116 * which will panic the system when the kernel tries 1117 * to invoke the vge_tick() function that isn't there 1118 * anymore. 1119 */ 1120 ifp->if_flags &= ~IFF_UP; 1121 ether_ifdetach(ifp); 1122 if_free(ifp); 1123 } 1124 if (sc->vge_miibus) 1125 device_delete_child(dev, sc->vge_miibus); 1126 bus_generic_detach(dev); 1127 1128 if (sc->vge_intrhand) 1129 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); 1130 if (sc->vge_irq) 1131 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vge_irq); 1132 if (sc->vge_res) 1133 bus_release_resource(dev, SYS_RES_MEMORY, 1134 VGE_PCI_LOMEM, sc->vge_res); 1135 1136 /* Unload and free the RX DMA ring memory and map */ 1137 1138 if (sc->vge_ldata.vge_rx_list_tag) { 1139 bus_dmamap_unload(sc->vge_ldata.vge_rx_list_tag, 1140 sc->vge_ldata.vge_rx_list_map); 1141 bus_dmamem_free(sc->vge_ldata.vge_rx_list_tag, 1142 sc->vge_ldata.vge_rx_list, 1143 sc->vge_ldata.vge_rx_list_map); 1144 bus_dma_tag_destroy(sc->vge_ldata.vge_rx_list_tag); 1145 } 1146 1147 /* Unload and free the TX DMA ring memory and map */ 1148 1149 if (sc->vge_ldata.vge_tx_list_tag) { 1150 bus_dmamap_unload(sc->vge_ldata.vge_tx_list_tag, 1151 sc->vge_ldata.vge_tx_list_map); 1152 bus_dmamem_free(sc->vge_ldata.vge_tx_list_tag, 1153 sc->vge_ldata.vge_tx_list, 1154 sc->vge_ldata.vge_tx_list_map); 1155 bus_dma_tag_destroy(sc->vge_ldata.vge_tx_list_tag); 1156 } 1157 1158 /* Destroy all the RX and TX buffer maps */ 1159 1160 if (sc->vge_ldata.vge_mtag) { 1161 for (i = 0; i < VGE_TX_DESC_CNT; i++) 1162 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1163 sc->vge_ldata.vge_tx_dmamap[i]); 1164 for (i = 0; i < VGE_RX_DESC_CNT; i++) 1165 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1166 sc->vge_ldata.vge_rx_dmamap[i]); 1167 bus_dma_tag_destroy(sc->vge_ldata.vge_mtag); 1168 } 1169 1170 if (sc->vge_parent_tag) 1171 bus_dma_tag_destroy(sc->vge_parent_tag); 1172 1173 mtx_destroy(&sc->vge_mtx); 1174 1175 return (0); 1176} 1177 1178static int 1179vge_newbuf(sc, idx, m) 1180 struct vge_softc *sc; 1181 int idx; 1182 struct mbuf *m; 1183{ 1184 struct vge_dmaload_arg arg; 1185 struct mbuf *n = NULL; 1186 int i, error; 1187 1188 if (m == NULL) { 1189 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1190 if (n == NULL) 1191 return (ENOBUFS); 1192 m = n; 1193 } else 1194 m->m_data = m->m_ext.ext_buf; 1195 1196 1197#ifdef VGE_FIXUP_RX 1198 /* 1199 * This is part of an evil trick to deal with non-x86 platforms. 1200 * The VIA chip requires RX buffers to be aligned on 32-bit 1201 * boundaries, but that will hose non-x86 machines. To get around 1202 * this, we leave some empty space at the start of each buffer 1203 * and for non-x86 hosts, we copy the buffer back two bytes 1204 * to achieve word alignment. This is slightly more efficient 1205 * than allocating a new buffer, copying the contents, and 1206 * discarding the old buffer. 1207 */ 1208 m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_ETHER_ALIGN; 1209 m_adj(m, VGE_ETHER_ALIGN); 1210#else 1211 m->m_len = m->m_pkthdr.len = MCLBYTES; 1212#endif 1213 1214 arg.sc = sc; 1215 arg.vge_idx = idx; 1216 arg.vge_maxsegs = 1; 1217 arg.vge_flags = 0; 1218 1219 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, 1220 sc->vge_ldata.vge_rx_dmamap[idx], m, vge_dma_map_rx_desc, 1221 &arg, BUS_DMA_NOWAIT); 1222 if (error || arg.vge_maxsegs != 1) { 1223 if (n != NULL) 1224 m_freem(n); 1225 return (ENOMEM); 1226 } 1227 1228 /* 1229 * Note: the manual fails to document the fact that for 1230 * proper opration, the driver needs to replentish the RX 1231 * DMA ring 4 descriptors at a time (rather than one at a 1232 * time, like most chips). We can allocate the new buffers 1233 * but we should not set the OWN bits until we're ready 1234 * to hand back 4 of them in one shot. 1235 */ 1236 1237#define VGE_RXCHUNK 4 1238 sc->vge_rx_consumed++; 1239 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 1240 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 1241 sc->vge_ldata.vge_rx_list[i].vge_sts |= 1242 htole32(VGE_RDSTS_OWN); 1243 sc->vge_rx_consumed = 0; 1244 } 1245 1246 sc->vge_ldata.vge_rx_mbuf[idx] = m; 1247 1248 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1249 sc->vge_ldata.vge_rx_dmamap[idx], 1250 BUS_DMASYNC_PREREAD); 1251 1252 return (0); 1253} 1254 1255static int 1256vge_tx_list_init(sc) 1257 struct vge_softc *sc; 1258{ 1259 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 1260 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 1261 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 1262 1263 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1264 sc->vge_ldata.vge_tx_list_map, BUS_DMASYNC_PREWRITE); 1265 sc->vge_ldata.vge_tx_prodidx = 0; 1266 sc->vge_ldata.vge_tx_considx = 0; 1267 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 1268 1269 return (0); 1270} 1271 1272static int 1273vge_rx_list_init(sc) 1274 struct vge_softc *sc; 1275{ 1276 int i; 1277 1278 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 1279 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 1280 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 1281 1282 sc->vge_rx_consumed = 0; 1283 1284 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1285 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 1286 return (ENOBUFS); 1287 } 1288 1289 /* Flush the RX descriptors */ 1290 1291 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1292 sc->vge_ldata.vge_rx_list_map, 1293 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1294 1295 sc->vge_ldata.vge_rx_prodidx = 0; 1296 sc->vge_rx_consumed = 0; 1297 sc->vge_head = sc->vge_tail = NULL; 1298 1299 return (0); 1300} 1301 1302#ifdef VGE_FIXUP_RX 1303static __inline void 1304vge_fixup_rx(m) 1305 struct mbuf *m; 1306{ 1307 int i; 1308 uint16_t *src, *dst; 1309 1310 src = mtod(m, uint16_t *); 1311 dst = src - 1; 1312 1313 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1314 *dst++ = *src++; 1315 1316 m->m_data -= ETHER_ALIGN; 1317 1318 return; 1319} 1320#endif 1321 1322/* 1323 * RX handler. We support the reception of jumbo frames that have 1324 * been fragmented across multiple 2K mbuf cluster buffers. 1325 */ 1326static void 1327vge_rxeof(sc) 1328 struct vge_softc *sc; 1329{ 1330 struct mbuf *m; 1331 struct ifnet *ifp; 1332 int i, total_len; 1333 int lim = 0; 1334 struct vge_rx_desc *cur_rx; 1335 u_int32_t rxstat, rxctl; 1336 1337 VGE_LOCK_ASSERT(sc); 1338 ifp = sc->vge_ifp; 1339 i = sc->vge_ldata.vge_rx_prodidx; 1340 1341 /* Invalidate the descriptor memory */ 1342 1343 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1344 sc->vge_ldata.vge_rx_list_map, 1345 BUS_DMASYNC_POSTREAD); 1346 1347 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 1348 1349#ifdef DEVICE_POLLING 1350 if (ifp->if_flags & IFF_POLLING) { 1351 if (sc->rxcycles <= 0) 1352 break; 1353 sc->rxcycles--; 1354 } 1355#endif /* DEVICE_POLLING */ 1356 1357 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1358 m = sc->vge_ldata.vge_rx_mbuf[i]; 1359 total_len = VGE_RXBYTES(cur_rx); 1360 rxstat = le32toh(cur_rx->vge_sts); 1361 rxctl = le32toh(cur_rx->vge_ctl); 1362 1363 /* Invalidate the RX mbuf and unload its map */ 1364 1365 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1366 sc->vge_ldata.vge_rx_dmamap[i], 1367 BUS_DMASYNC_POSTWRITE); 1368 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1369 sc->vge_ldata.vge_rx_dmamap[i]); 1370 1371 /* 1372 * If the 'start of frame' bit is set, this indicates 1373 * either the first fragment in a multi-fragment receive, 1374 * or an intermediate fragment. Either way, we want to 1375 * accumulate the buffers. 1376 */ 1377 if (rxstat & VGE_RXPKT_SOF) { 1378 m->m_len = MCLBYTES - VGE_ETHER_ALIGN; 1379 if (sc->vge_head == NULL) 1380 sc->vge_head = sc->vge_tail = m; 1381 else { 1382 m->m_flags &= ~M_PKTHDR; 1383 sc->vge_tail->m_next = m; 1384 sc->vge_tail = m; 1385 } 1386 vge_newbuf(sc, i, NULL); 1387 VGE_RX_DESC_INC(i); 1388 continue; 1389 } 1390 1391 /* 1392 * Bad/error frames will have the RXOK bit cleared. 1393 * However, there's one error case we want to allow: 1394 * if a VLAN tagged frame arrives and the chip can't 1395 * match it against the CAM filter, it considers this 1396 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1397 * We don't want to drop the frame though: our VLAN 1398 * filtering is done in software. 1399 */ 1400 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1401 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1402 ifp->if_ierrors++; 1403 /* 1404 * If this is part of a multi-fragment packet, 1405 * discard all the pieces. 1406 */ 1407 if (sc->vge_head != NULL) { 1408 m_freem(sc->vge_head); 1409 sc->vge_head = sc->vge_tail = NULL; 1410 } 1411 vge_newbuf(sc, i, m); 1412 VGE_RX_DESC_INC(i); 1413 continue; 1414 } 1415 1416 /* 1417 * If allocating a replacement mbuf fails, 1418 * reload the current one. 1419 */ 1420 1421 if (vge_newbuf(sc, i, NULL)) { 1422 ifp->if_ierrors++; 1423 if (sc->vge_head != NULL) { 1424 m_freem(sc->vge_head); 1425 sc->vge_head = sc->vge_tail = NULL; 1426 } 1427 vge_newbuf(sc, i, m); 1428 VGE_RX_DESC_INC(i); 1429 continue; 1430 } 1431 1432 VGE_RX_DESC_INC(i); 1433 1434 if (sc->vge_head != NULL) { 1435 m->m_len = total_len % (MCLBYTES - VGE_ETHER_ALIGN); 1436 /* 1437 * Special case: if there's 4 bytes or less 1438 * in this buffer, the mbuf can be discarded: 1439 * the last 4 bytes is the CRC, which we don't 1440 * care about anyway. 1441 */ 1442 if (m->m_len <= ETHER_CRC_LEN) { 1443 sc->vge_tail->m_len -= 1444 (ETHER_CRC_LEN - m->m_len); 1445 m_freem(m); 1446 } else { 1447 m->m_len -= ETHER_CRC_LEN; 1448 m->m_flags &= ~M_PKTHDR; 1449 sc->vge_tail->m_next = m; 1450 } 1451 m = sc->vge_head; 1452 sc->vge_head = sc->vge_tail = NULL; 1453 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1454 } else 1455 m->m_pkthdr.len = m->m_len = 1456 (total_len - ETHER_CRC_LEN); 1457 1458#ifdef VGE_FIXUP_RX 1459 vge_fixup_rx(m); 1460#endif 1461 ifp->if_ipackets++; 1462 m->m_pkthdr.rcvif = ifp; 1463 1464 /* Do RX checksumming if enabled */ 1465 if (ifp->if_capenable & IFCAP_RXCSUM) { 1466 1467 /* Check IP header checksum */ 1468 if (rxctl & VGE_RDCTL_IPPKT) 1469 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1470 if (rxctl & VGE_RDCTL_IPCSUMOK) 1471 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1472 1473 /* Check TCP/UDP checksum */ 1474 if (rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT) && 1475 rxctl & VGE_RDCTL_PROTOCSUMOK) { 1476 m->m_pkthdr.csum_flags |= 1477 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1478 m->m_pkthdr.csum_data = 0xffff; 1479 } 1480 } 1481 1482 if (rxstat & VGE_RDSTS_VTAG) 1483 VLAN_INPUT_TAG(ifp, m, 1484 ntohs((rxctl & VGE_RDCTL_VLANID)), continue); 1485 1486 VGE_UNLOCK(sc); 1487 (*ifp->if_input)(ifp, m); 1488 VGE_LOCK(sc); 1489 1490 lim++; 1491 if (lim == VGE_RX_DESC_CNT) 1492 break; 1493 1494 } 1495 1496 /* Flush the RX DMA ring */ 1497 1498 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1499 sc->vge_ldata.vge_rx_list_map, 1500 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1501 1502 sc->vge_ldata.vge_rx_prodidx = i; 1503 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1504 1505 1506 return; 1507} 1508 1509static void 1510vge_txeof(sc) 1511 struct vge_softc *sc; 1512{ 1513 struct ifnet *ifp; 1514 u_int32_t txstat; 1515 int idx; 1516 1517 ifp = sc->vge_ifp; 1518 idx = sc->vge_ldata.vge_tx_considx; 1519 1520 /* Invalidate the TX descriptor list */ 1521 1522 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1523 sc->vge_ldata.vge_tx_list_map, 1524 BUS_DMASYNC_POSTREAD); 1525 1526 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1527 1528 txstat = le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1529 if (txstat & VGE_TDSTS_OWN) 1530 break; 1531 1532 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1533 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1534 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1535 sc->vge_ldata.vge_tx_dmamap[idx]); 1536 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1537 ifp->if_collisions++; 1538 if (txstat & VGE_TDSTS_TXERR) 1539 ifp->if_oerrors++; 1540 else 1541 ifp->if_opackets++; 1542 1543 sc->vge_ldata.vge_tx_free++; 1544 VGE_TX_DESC_INC(idx); 1545 } 1546 1547 /* No changes made to the TX ring, so no flush needed */ 1548 1549 if (idx != sc->vge_ldata.vge_tx_considx) { 1550 sc->vge_ldata.vge_tx_considx = idx; 1551 ifp->if_flags &= ~IFF_OACTIVE; 1552 ifp->if_timer = 0; 1553 } 1554 1555 /* 1556 * If not all descriptors have been released reaped yet, 1557 * reload the timer so that we will eventually get another 1558 * interrupt that will cause us to re-enter this routine. 1559 * This is done in case the transmitter has gone idle. 1560 */ 1561 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) { 1562 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1563 } 1564 1565 return; 1566} 1567 1568static void 1569vge_tick(xsc) 1570 void *xsc; 1571{ 1572 struct vge_softc *sc; 1573 struct ifnet *ifp; 1574 struct mii_data *mii; 1575 1576 sc = xsc; 1577 ifp = sc->vge_ifp; 1578 VGE_LOCK(sc); 1579 mii = device_get_softc(sc->vge_miibus); 1580 1581 mii_tick(mii); 1582 if (sc->vge_link) { 1583 if (!(mii->mii_media_status & IFM_ACTIVE)) { 1584 sc->vge_link = 0; 1585 if_link_state_change(sc->vge_ifp, 1586 LINK_STATE_DOWN); 1587 } 1588 } else { 1589 if (mii->mii_media_status & IFM_ACTIVE && 1590 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1591 sc->vge_link = 1; 1592 if_link_state_change(sc->vge_ifp, 1593 LINK_STATE_UP); 1594#if __FreeBSD_version < 502114 1595 if (ifp->if_snd.ifq_head != NULL) 1596#else 1597 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1598#endif 1599 taskqueue_enqueue(taskqueue_swi, 1600 &sc->vge_txtask); 1601 } 1602 } 1603 1604 VGE_UNLOCK(sc); 1605 1606 return; 1607} 1608 1609#ifdef DEVICE_POLLING 1610static void 1611vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1612{ 1613 struct vge_softc *sc = ifp->if_softc; 1614 1615 VGE_LOCK(sc); 1616#ifdef IFCAP_POLLING 1617 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1618 ether_poll_deregister(ifp); 1619 cmd = POLL_DEREGISTER; 1620 } 1621#endif 1622 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1623 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1624 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 1625 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1626 goto done; 1627 } 1628 1629 sc->rxcycles = count; 1630 vge_rxeof(sc); 1631 vge_txeof(sc); 1632 1633#if __FreeBSD_version < 502114 1634 if (ifp->if_snd.ifq_head != NULL) 1635#else 1636 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1637#endif 1638 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1639 1640 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1641 u_int32_t status; 1642 status = CSR_READ_4(sc, VGE_ISR); 1643 if (status == 0xFFFFFFFF) 1644 goto done; 1645 if (status) 1646 CSR_WRITE_4(sc, VGE_ISR, status); 1647 1648 /* 1649 * XXX check behaviour on receiver stalls. 1650 */ 1651 1652 if (status & VGE_ISR_TXDMA_STALL || 1653 status & VGE_ISR_RXDMA_STALL) 1654 vge_init(sc); 1655 1656 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1657 vge_rxeof(sc); 1658 ifp->if_ierrors++; 1659 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1660 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1661 } 1662 } 1663done: 1664 VGE_UNLOCK(sc); 1665} 1666#endif /* DEVICE_POLLING */ 1667 1668static void 1669vge_intr(arg) 1670 void *arg; 1671{ 1672 struct vge_softc *sc; 1673 struct ifnet *ifp; 1674 u_int32_t status; 1675 1676 sc = arg; 1677 1678 if (sc->suspended) { 1679 return; 1680 } 1681 1682 VGE_LOCK(sc); 1683 ifp = sc->vge_ifp; 1684 1685 if (!(ifp->if_flags & IFF_UP)) { 1686 VGE_UNLOCK(sc); 1687 return; 1688 } 1689 1690#ifdef DEVICE_POLLING 1691 if (ifp->if_flags & IFF_POLLING) 1692 goto done; 1693 if ( 1694#ifdef IFCAP_POLLING 1695 (ifp->if_capenable & IFCAP_POLLING) && 1696#endif 1697 ether_poll_register(vge_poll, ifp)) { /* ok, disable interrupts */ 1698 CSR_WRITE_4(sc, VGE_IMR, 0); 1699 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1700 vge_poll(ifp, 0, 1); 1701 goto done; 1702 } 1703 1704#endif /* DEVICE_POLLING */ 1705 1706 /* Disable interrupts */ 1707 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1708 1709 for (;;) { 1710 1711 status = CSR_READ_4(sc, VGE_ISR); 1712 /* If the card has gone away the read returns 0xffff. */ 1713 if (status == 0xFFFFFFFF) 1714 break; 1715 1716 if (status) 1717 CSR_WRITE_4(sc, VGE_ISR, status); 1718 1719 if ((status & VGE_INTRS) == 0) 1720 break; 1721 1722 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1723 vge_rxeof(sc); 1724 1725 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1726 vge_rxeof(sc); 1727 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1728 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1729 } 1730 1731 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1732 vge_txeof(sc); 1733 1734 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1735 vge_init(sc); 1736 1737 if (status & VGE_ISR_LINKSTS) 1738 vge_tick(sc); 1739 } 1740 1741 /* Re-enable interrupts */ 1742 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1743 1744#ifdef DEVICE_POLLING 1745done: 1746#endif 1747 VGE_UNLOCK(sc); 1748 1749#if __FreeBSD_version < 502114 1750 if (ifp->if_snd.ifq_head != NULL) 1751#else 1752 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1753#endif 1754 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1755 1756 return; 1757} 1758 1759static int 1760vge_encap(sc, m_head, idx) 1761 struct vge_softc *sc; 1762 struct mbuf *m_head; 1763 int idx; 1764{ 1765 struct mbuf *m_new = NULL; 1766 struct vge_dmaload_arg arg; 1767 bus_dmamap_t map; 1768 int error; 1769 struct m_tag *mtag; 1770 1771 if (sc->vge_ldata.vge_tx_free <= 2) 1772 return (EFBIG); 1773 1774 arg.vge_flags = 0; 1775 1776 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1777 arg.vge_flags |= VGE_TDCTL_IPCSUM; 1778 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1779 arg.vge_flags |= VGE_TDCTL_TCPCSUM; 1780 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1781 arg.vge_flags |= VGE_TDCTL_UDPCSUM; 1782 1783 arg.sc = sc; 1784 arg.vge_idx = idx; 1785 arg.vge_m0 = m_head; 1786 arg.vge_maxsegs = VGE_TX_FRAGS; 1787 1788 map = sc->vge_ldata.vge_tx_dmamap[idx]; 1789 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1790 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1791 1792 if (error && error != EFBIG) { 1793 printf("vge%d: can't map mbuf (error %d)\n", 1794 sc->vge_unit, error); 1795 return (ENOBUFS); 1796 } 1797 1798 /* Too many segments to map, coalesce into a single mbuf */ 1799 1800 if (error || arg.vge_maxsegs == 0) { 1801 m_new = m_defrag(m_head, M_DONTWAIT); 1802 if (m_new == NULL) 1803 return (1); 1804 else 1805 m_head = m_new; 1806 1807 arg.sc = sc; 1808 arg.vge_m0 = m_head; 1809 arg.vge_idx = idx; 1810 arg.vge_maxsegs = 1; 1811 1812 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1813 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1814 if (error) { 1815 printf("vge%d: can't map mbuf (error %d)\n", 1816 sc->vge_unit, error); 1817 return (EFBIG); 1818 } 1819 } 1820 1821 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1822 sc->vge_ldata.vge_tx_free--; 1823 1824 /* 1825 * Set up hardware VLAN tagging. 1826 */ 1827 1828 mtag = VLAN_OUTPUT_TAG(sc->vge_ifp, m_head); 1829 if (mtag != NULL) 1830 sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1831 htole32(htons(VLAN_TAG_VALUE(mtag)) | VGE_TDCTL_VTAG); 1832 1833 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1834 1835 return (0); 1836} 1837 1838static void 1839vge_tx_task(arg, npending) 1840 void *arg; 1841 int npending; 1842{ 1843 struct ifnet *ifp; 1844 1845 ifp = arg; 1846 vge_start(ifp); 1847 1848 return; 1849} 1850 1851/* 1852 * Main transmit routine. 1853 */ 1854 1855static void 1856vge_start(ifp) 1857 struct ifnet *ifp; 1858{ 1859 struct vge_softc *sc; 1860 struct mbuf *m_head = NULL; 1861 int idx, pidx = 0; 1862 1863 sc = ifp->if_softc; 1864 VGE_LOCK(sc); 1865 1866 if (!sc->vge_link || ifp->if_flags & IFF_OACTIVE) { 1867 VGE_UNLOCK(sc); 1868 return; 1869 } 1870 1871#if __FreeBSD_version < 502114 1872 if (ifp->if_snd.ifq_head == NULL) { 1873#else 1874 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 1875#endif 1876 VGE_UNLOCK(sc); 1877 return; 1878 } 1879 1880 idx = sc->vge_ldata.vge_tx_prodidx; 1881 1882 pidx = idx - 1; 1883 if (pidx < 0) 1884 pidx = VGE_TX_DESC_CNT - 1; 1885 1886 1887 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1888#if __FreeBSD_version < 502114 1889 IF_DEQUEUE(&ifp->if_snd, m_head); 1890#else 1891 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1892#endif 1893 if (m_head == NULL) 1894 break; 1895 1896 if (vge_encap(sc, m_head, idx)) { 1897#if __FreeBSD_version >= 502114 1898 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1899#else 1900 IF_PREPEND(&ifp->if_snd, m_head); 1901#endif 1902 ifp->if_flags |= IFF_OACTIVE; 1903 break; 1904 } 1905 1906 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1907 htole16(VGE_TXDESC_Q); 1908 1909 pidx = idx; 1910 VGE_TX_DESC_INC(idx); 1911 1912 /* 1913 * If there's a BPF listener, bounce a copy of this frame 1914 * to him. 1915 */ 1916 BPF_MTAP(ifp, m_head); 1917 } 1918 1919 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1920 VGE_UNLOCK(sc); 1921 return; 1922 } 1923 1924 /* Flush the TX descriptors */ 1925 1926 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1927 sc->vge_ldata.vge_tx_list_map, 1928 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1929 1930 /* Issue a transmit command. */ 1931 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1932 1933 sc->vge_ldata.vge_tx_prodidx = idx; 1934 1935 /* 1936 * Use the countdown timer for interrupt moderation. 1937 * 'TX done' interrupts are disabled. Instead, we reset the 1938 * countdown timer, which will begin counting until it hits 1939 * the value in the SSTIMER register, and then trigger an 1940 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1941 * the timer count is reloaded. Only when the transmitter 1942 * is idle will the timer hit 0 and an interrupt fire. 1943 */ 1944 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1945 1946 VGE_UNLOCK(sc); 1947 1948 /* 1949 * Set a timeout in case the chip goes out to lunch. 1950 */ 1951 ifp->if_timer = 5; 1952 1953 return; 1954} 1955 1956static void 1957vge_init(xsc) 1958 void *xsc; 1959{ 1960 struct vge_softc *sc = xsc; 1961 struct ifnet *ifp = sc->vge_ifp; 1962 struct mii_data *mii; 1963 int i; 1964 1965 VGE_LOCK(sc); 1966 mii = device_get_softc(sc->vge_miibus); 1967 1968 /* 1969 * Cancel pending I/O and free all RX/TX buffers. 1970 */ 1971 vge_stop(sc); 1972 vge_reset(sc); 1973 1974 /* 1975 * Initialize the RX and TX descriptors and mbufs. 1976 */ 1977 1978 vge_rx_list_init(sc); 1979 vge_tx_list_init(sc); 1980 1981 /* Set our station address */ 1982 for (i = 0; i < ETHER_ADDR_LEN; i++) 1983 CSR_WRITE_1(sc, VGE_PAR0 + i, IFP2ENADDR(sc->vge_ifp)[i]); 1984 1985 /* 1986 * Set receive FIFO threshold. Also allow transmission and 1987 * reception of VLAN tagged frames. 1988 */ 1989 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1990 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1991 1992 /* Set DMA burst length */ 1993 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1994 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1995 1996 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1997 1998 /* Set collision backoff algorithm */ 1999 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 2000 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 2001 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 2002 2003 /* Disable LPSEL field in priority resolution */ 2004 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 2005 2006 /* 2007 * Load the addresses of the DMA queues into the chip. 2008 * Note that we only use one transmit queue. 2009 */ 2010 2011 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 2012 VGE_ADDR_LO(sc->vge_ldata.vge_tx_list_addr)); 2013 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 2014 2015 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 2016 VGE_ADDR_LO(sc->vge_ldata.vge_rx_list_addr)); 2017 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 2018 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 2019 2020 /* Enable and wake up the RX descriptor queue */ 2021 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 2022 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 2023 2024 /* Enable the TX descriptor queue */ 2025 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 2026 2027 /* Set up the receive filter -- allow large frames for VLANs. */ 2028 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 2029 2030 /* If we want promiscuous mode, set the allframes bit. */ 2031 if (ifp->if_flags & IFF_PROMISC) { 2032 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 2033 } 2034 2035 /* Set capture broadcast bit to capture broadcast frames. */ 2036 if (ifp->if_flags & IFF_BROADCAST) { 2037 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 2038 } 2039 2040 /* Set multicast bit to capture multicast frames. */ 2041 if (ifp->if_flags & IFF_MULTICAST) { 2042 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 2043 } 2044 2045 /* Init the cam filter. */ 2046 vge_cam_clear(sc); 2047 2048 /* Init the multicast filter. */ 2049 vge_setmulti(sc); 2050 2051 /* Enable flow control */ 2052 2053 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 2054 2055 /* Enable jumbo frame reception (if desired) */ 2056 2057 /* Start the MAC. */ 2058 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 2059 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 2060 CSR_WRITE_1(sc, VGE_CRS0, 2061 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 2062 2063 /* 2064 * Configure one-shot timer for microsecond 2065 * resulution and load it for 500 usecs. 2066 */ 2067 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 2068 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 2069 2070 /* 2071 * Configure interrupt moderation for receive. Enable 2072 * the holdoff counter and load it, and set the RX 2073 * suppression count to the number of descriptors we 2074 * want to allow before triggering an interrupt. 2075 * The holdoff timer is in units of 20 usecs. 2076 */ 2077 2078#ifdef notyet 2079 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 2080 /* Select the interrupt holdoff timer page. */ 2081 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2082 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 2083 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 2084 2085 /* Enable use of the holdoff timer. */ 2086 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 2087 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 2088 2089 /* Select the RX suppression threshold page. */ 2090 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2091 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 2092 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 2093 2094 /* Restore the page select bits. */ 2095 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2096 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 2097#endif 2098 2099#ifdef DEVICE_POLLING 2100 /* 2101 * Disable interrupts if we are polling. 2102 */ 2103 if (ifp->if_flags & IFF_POLLING) { 2104 CSR_WRITE_4(sc, VGE_IMR, 0); 2105 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2106 } else /* otherwise ... */ 2107#endif /* DEVICE_POLLING */ 2108 { 2109 /* 2110 * Enable interrupts. 2111 */ 2112 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2113 CSR_WRITE_4(sc, VGE_ISR, 0); 2114 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2115 } 2116 2117 mii_mediachg(mii); 2118 2119 ifp->if_flags |= IFF_RUNNING; 2120 ifp->if_flags &= ~IFF_OACTIVE; 2121 2122 sc->vge_if_flags = 0; 2123 sc->vge_link = 0; 2124 2125 VGE_UNLOCK(sc); 2126 2127 return; 2128} 2129 2130/* 2131 * Set media options. 2132 */ 2133static int 2134vge_ifmedia_upd(ifp) 2135 struct ifnet *ifp; 2136{ 2137 struct vge_softc *sc; 2138 struct mii_data *mii; 2139 2140 sc = ifp->if_softc; 2141 mii = device_get_softc(sc->vge_miibus); 2142 mii_mediachg(mii); 2143 2144 return (0); 2145} 2146 2147/* 2148 * Report current media status. 2149 */ 2150static void 2151vge_ifmedia_sts(ifp, ifmr) 2152 struct ifnet *ifp; 2153 struct ifmediareq *ifmr; 2154{ 2155 struct vge_softc *sc; 2156 struct mii_data *mii; 2157 2158 sc = ifp->if_softc; 2159 mii = device_get_softc(sc->vge_miibus); 2160 2161 mii_pollstat(mii); 2162 ifmr->ifm_active = mii->mii_media_active; 2163 ifmr->ifm_status = mii->mii_media_status; 2164 2165 return; 2166} 2167 2168static void 2169vge_miibus_statchg(dev) 2170 device_t dev; 2171{ 2172 struct vge_softc *sc; 2173 struct mii_data *mii; 2174 struct ifmedia_entry *ife; 2175 2176 sc = device_get_softc(dev); 2177 mii = device_get_softc(sc->vge_miibus); 2178 ife = mii->mii_media.ifm_cur; 2179 2180 /* 2181 * If the user manually selects a media mode, we need to turn 2182 * on the forced MAC mode bit in the DIAGCTL register. If the 2183 * user happens to choose a full duplex mode, we also need to 2184 * set the 'force full duplex' bit. This applies only to 2185 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2186 * mode is disabled, and in 1000baseT mode, full duplex is 2187 * always implied, so we turn on the forced mode bit but leave 2188 * the FDX bit cleared. 2189 */ 2190 2191 switch (IFM_SUBTYPE(ife->ifm_media)) { 2192 case IFM_AUTO: 2193 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2194 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2195 break; 2196 case IFM_1000_T: 2197 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2198 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2199 break; 2200 case IFM_100_TX: 2201 case IFM_10_T: 2202 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2203 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2204 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2205 } else { 2206 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2207 } 2208 break; 2209 default: 2210 device_printf(dev, "unknown media type: %x\n", 2211 IFM_SUBTYPE(ife->ifm_media)); 2212 break; 2213 } 2214 2215 return; 2216} 2217 2218static int 2219vge_ioctl(ifp, command, data) 2220 struct ifnet *ifp; 2221 u_long command; 2222 caddr_t data; 2223{ 2224 struct vge_softc *sc = ifp->if_softc; 2225 struct ifreq *ifr = (struct ifreq *) data; 2226 struct mii_data *mii; 2227 int error = 0; 2228 2229 switch (command) { 2230 case SIOCSIFMTU: 2231 if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2232 error = EINVAL; 2233 ifp->if_mtu = ifr->ifr_mtu; 2234 break; 2235 case SIOCSIFFLAGS: 2236 if (ifp->if_flags & IFF_UP) { 2237 if (ifp->if_flags & IFF_RUNNING && 2238 ifp->if_flags & IFF_PROMISC && 2239 !(sc->vge_if_flags & IFF_PROMISC)) { 2240 CSR_SETBIT_1(sc, VGE_RXCTL, 2241 VGE_RXCTL_RX_PROMISC); 2242 vge_setmulti(sc); 2243 } else if (ifp->if_flags & IFF_RUNNING && 2244 !(ifp->if_flags & IFF_PROMISC) && 2245 sc->vge_if_flags & IFF_PROMISC) { 2246 CSR_CLRBIT_1(sc, VGE_RXCTL, 2247 VGE_RXCTL_RX_PROMISC); 2248 vge_setmulti(sc); 2249 } else 2250 vge_init(sc); 2251 } else { 2252 if (ifp->if_flags & IFF_RUNNING) 2253 vge_stop(sc); 2254 } 2255 sc->vge_if_flags = ifp->if_flags; 2256 break; 2257 case SIOCADDMULTI: 2258 case SIOCDELMULTI: 2259 vge_setmulti(sc); 2260 break; 2261 case SIOCGIFMEDIA: 2262 case SIOCSIFMEDIA: 2263 mii = device_get_softc(sc->vge_miibus); 2264 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2265 break; 2266 case SIOCSIFCAP: 2267#ifdef IFCAP_POLLING 2268 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_POLLING); 2269#else 2270 ifp->if_capenable &= ~(IFCAP_HWCSUM); 2271#endif 2272 ifp->if_capenable |= 2273#ifdef IFCAP_POLLING 2274 ifr->ifr_reqcap & (IFCAP_HWCSUM | IFCAP_POLLING); 2275#else 2276 ifr->ifr_reqcap & (IFCAP_HWCSUM); 2277#endif 2278 if (ifp->if_capenable & IFCAP_TXCSUM) 2279 ifp->if_hwassist = VGE_CSUM_FEATURES; 2280 else 2281 ifp->if_hwassist = 0; 2282 if (ifp->if_flags & IFF_RUNNING) 2283 vge_init(sc); 2284 break; 2285 default: 2286 error = ether_ioctl(ifp, command, data); 2287 break; 2288 } 2289 2290 return (error); 2291} 2292 2293static void 2294vge_watchdog(ifp) 2295 struct ifnet *ifp; 2296{ 2297 struct vge_softc *sc; 2298 2299 sc = ifp->if_softc; 2300 VGE_LOCK(sc); 2301 printf("vge%d: watchdog timeout\n", sc->vge_unit); 2302 ifp->if_oerrors++; 2303 2304 vge_txeof(sc); 2305 vge_rxeof(sc); 2306 2307 vge_init(sc); 2308 2309 VGE_UNLOCK(sc); 2310 2311 return; 2312} 2313 2314/* 2315 * Stop the adapter and free any mbufs allocated to the 2316 * RX and TX lists. 2317 */ 2318static void 2319vge_stop(sc) 2320 struct vge_softc *sc; 2321{ 2322 register int i; 2323 struct ifnet *ifp; 2324 2325 VGE_LOCK(sc); 2326 ifp = sc->vge_ifp; 2327 ifp->if_timer = 0; 2328 2329 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2330#ifdef DEVICE_POLLING 2331 ether_poll_deregister(ifp); 2332#endif /* DEVICE_POLLING */ 2333 2334 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2335 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2336 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2337 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2338 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2339 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2340 2341 if (sc->vge_head != NULL) { 2342 m_freem(sc->vge_head); 2343 sc->vge_head = sc->vge_tail = NULL; 2344 } 2345 2346 /* Free the TX list buffers. */ 2347 2348 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 2349 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 2350 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2351 sc->vge_ldata.vge_tx_dmamap[i]); 2352 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 2353 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 2354 } 2355 } 2356 2357 /* Free the RX list buffers. */ 2358 2359 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 2360 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 2361 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2362 sc->vge_ldata.vge_rx_dmamap[i]); 2363 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 2364 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 2365 } 2366 } 2367 2368 VGE_UNLOCK(sc); 2369 2370 return; 2371} 2372 2373/* 2374 * Device suspend routine. Stop the interface and save some PCI 2375 * settings in case the BIOS doesn't restore them properly on 2376 * resume. 2377 */ 2378static int 2379vge_suspend(dev) 2380 device_t dev; 2381{ 2382 struct vge_softc *sc; 2383 2384 sc = device_get_softc(dev); 2385 2386 vge_stop(sc); 2387 2388 sc->suspended = 1; 2389 2390 return (0); 2391} 2392 2393/* 2394 * Device resume routine. Restore some PCI settings in case the BIOS 2395 * doesn't, re-enable busmastering, and restart the interface if 2396 * appropriate. 2397 */ 2398static int 2399vge_resume(dev) 2400 device_t dev; 2401{ 2402 struct vge_softc *sc; 2403 struct ifnet *ifp; 2404 2405 sc = device_get_softc(dev); 2406 ifp = sc->vge_ifp; 2407 2408 /* reenable busmastering */ 2409 pci_enable_busmaster(dev); 2410 pci_enable_io(dev, SYS_RES_MEMORY); 2411 2412 /* reinitialize interface if necessary */ 2413 if (ifp->if_flags & IFF_UP) 2414 vge_init(sc); 2415 2416 sc->suspended = 0; 2417 2418 return (0); 2419} 2420 2421/* 2422 * Stop all chip I/O so that the kernel's probe routines don't 2423 * get confused by errant DMAs when rebooting. 2424 */ 2425static void 2426vge_shutdown(dev) 2427 device_t dev; 2428{ 2429 struct vge_softc *sc; 2430 2431 sc = device_get_softc(dev); 2432 2433 vge_stop(sc); 2434} 2435