if_vge.c revision 147027
1/*- 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/vge/if_vge.c 147027 2005-06-05 22:45:19Z imp $"); 35 36/* 37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 46 * combines a tri-speed ethernet MAC and PHY, with the following 47 * features: 48 * 49 * o Jumbo frame support up to 16K 50 * o Transmit and receive flow control 51 * o IPv4 checksum offload 52 * o VLAN tag insertion and stripping 53 * o TCP large send 54 * o 64-bit multicast hash table filter 55 * o 64 entry CAM filter 56 * o 16K RX FIFO and 48K TX FIFO memory 57 * o Interrupt moderation 58 * 59 * The VT6122 supports up to four transmit DMA queues. The descriptors 60 * in the transmit ring can address up to 7 data fragments; frames which 61 * span more than 7 data buffers must be coalesced, but in general the 62 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 63 * long. The receive descriptors address only a single buffer. 64 * 65 * There are two peculiar design issues with the VT6122. One is that 66 * receive data buffers must be aligned on a 32-bit boundary. This is 67 * not a problem where the VT6122 is used as a LOM device in x86-based 68 * systems, but on architectures that generate unaligned access traps, we 69 * have to do some copying. 70 * 71 * The other issue has to do with the way 64-bit addresses are handled. 72 * The DMA descriptors only allow you to specify 48 bits of addressing 73 * information. The remaining 16 bits are specified using one of the 74 * I/O registers. If you only have a 32-bit system, then this isn't 75 * an issue, but if you have a 64-bit system and more than 4GB of 76 * memory, you must have to make sure your network data buffers reside 77 * in the same 48-bit 'segment.' 78 * 79 * Special thanks to Ryan Fu at VIA Networking for providing documentation 80 * and sample NICs for testing. 81 */ 82 83#include <sys/param.h> 84#include <sys/endian.h> 85#include <sys/systm.h> 86#include <sys/sockio.h> 87#include <sys/mbuf.h> 88#include <sys/malloc.h> 89#include <sys/module.h> 90#include <sys/kernel.h> 91#include <sys/socket.h> 92#include <sys/taskqueue.h> 93 94#include <net/if.h> 95#include <net/if_arp.h> 96#include <net/ethernet.h> 97#include <net/if_dl.h> 98#include <net/if_media.h> 99#include <net/if_vlan_var.h> 100 101#include <net/bpf.h> 102 103#include <machine/bus.h> 104#include <machine/resource.h> 105#include <sys/bus.h> 106#include <sys/rman.h> 107 108#include <dev/mii/mii.h> 109#include <dev/mii/miivar.h> 110 111#include <dev/pci/pcireg.h> 112#include <dev/pci/pcivar.h> 113 114MODULE_DEPEND(vge, pci, 1, 1, 1); 115MODULE_DEPEND(vge, ether, 1, 1, 1); 116MODULE_DEPEND(vge, miibus, 1, 1, 1); 117 118/* "controller miibus0" required. See GENERIC if you get errors here. */ 119#include "miibus_if.h" 120 121#include <dev/vge/if_vgereg.h> 122#include <dev/vge/if_vgevar.h> 123 124#define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 125 126/* 127 * Various supported device vendors/types and their names. 128 */ 129static struct vge_type vge_devs[] = { 130 { VIA_VENDORID, VIA_DEVICEID_61XX, 131 "VIA Networking Gigabit Ethernet" }, 132 { 0, 0, NULL } 133}; 134 135static int vge_probe (device_t); 136static int vge_attach (device_t); 137static int vge_detach (device_t); 138 139static int vge_encap (struct vge_softc *, struct mbuf *, int); 140 141static void vge_dma_map_addr (void *, bus_dma_segment_t *, int, int); 142static void vge_dma_map_rx_desc (void *, bus_dma_segment_t *, int, 143 bus_size_t, int); 144static void vge_dma_map_tx_desc (void *, bus_dma_segment_t *, int, 145 bus_size_t, int); 146static int vge_allocmem (device_t, struct vge_softc *); 147static int vge_newbuf (struct vge_softc *, int, struct mbuf *); 148static int vge_rx_list_init (struct vge_softc *); 149static int vge_tx_list_init (struct vge_softc *); 150#ifdef VGE_FIXUP_RX 151static __inline void vge_fixup_rx 152 (struct mbuf *); 153#endif 154static void vge_rxeof (struct vge_softc *); 155static void vge_txeof (struct vge_softc *); 156static void vge_intr (void *); 157static void vge_tick (void *); 158static void vge_tx_task (void *, int); 159static void vge_start (struct ifnet *); 160static int vge_ioctl (struct ifnet *, u_long, caddr_t); 161static void vge_init (void *); 162static void vge_stop (struct vge_softc *); 163static void vge_watchdog (struct ifnet *); 164static int vge_suspend (device_t); 165static int vge_resume (device_t); 166static void vge_shutdown (device_t); 167static int vge_ifmedia_upd (struct ifnet *); 168static void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 169 170#ifdef VGE_EEPROM 171static void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 172#endif 173static void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 174 175static void vge_miipoll_start (struct vge_softc *); 176static void vge_miipoll_stop (struct vge_softc *); 177static int vge_miibus_readreg (device_t, int, int); 178static int vge_miibus_writereg (device_t, int, int, int); 179static void vge_miibus_statchg (device_t); 180 181static void vge_cam_clear (struct vge_softc *); 182static int vge_cam_set (struct vge_softc *, uint8_t *); 183#if __FreeBSD_version < 502113 184static uint32_t vge_mchash (uint8_t *); 185#endif 186static void vge_setmulti (struct vge_softc *); 187static void vge_reset (struct vge_softc *); 188 189#define VGE_PCI_LOIO 0x10 190#define VGE_PCI_LOMEM 0x14 191 192static device_method_t vge_methods[] = { 193 /* Device interface */ 194 DEVMETHOD(device_probe, vge_probe), 195 DEVMETHOD(device_attach, vge_attach), 196 DEVMETHOD(device_detach, vge_detach), 197 DEVMETHOD(device_suspend, vge_suspend), 198 DEVMETHOD(device_resume, vge_resume), 199 DEVMETHOD(device_shutdown, vge_shutdown), 200 201 /* bus interface */ 202 DEVMETHOD(bus_print_child, bus_generic_print_child), 203 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 204 205 /* MII interface */ 206 DEVMETHOD(miibus_readreg, vge_miibus_readreg), 207 DEVMETHOD(miibus_writereg, vge_miibus_writereg), 208 DEVMETHOD(miibus_statchg, vge_miibus_statchg), 209 210 { 0, 0 } 211}; 212 213static driver_t vge_driver = { 214 "vge", 215 vge_methods, 216 sizeof(struct vge_softc) 217}; 218 219static devclass_t vge_devclass; 220 221DRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0); 222DRIVER_MODULE(vge, cardbus, vge_driver, vge_devclass, 0, 0); 223DRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0); 224 225#ifdef VGE_EEPROM 226/* 227 * Read a word of data stored in the EEPROM at address 'addr.' 228 */ 229static void 230vge_eeprom_getword(sc, addr, dest) 231 struct vge_softc *sc; 232 int addr; 233 u_int16_t *dest; 234{ 235 register int i; 236 u_int16_t word = 0; 237 238 /* 239 * Enter EEPROM embedded programming mode. In order to 240 * access the EEPROM at all, we first have to set the 241 * EELOAD bit in the CHIPCFG2 register. 242 */ 243 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 244 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 245 246 /* Select the address of the word we want to read */ 247 CSR_WRITE_1(sc, VGE_EEADDR, addr); 248 249 /* Issue read command */ 250 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 251 252 /* Wait for the done bit to be set. */ 253 for (i = 0; i < VGE_TIMEOUT; i++) { 254 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 255 break; 256 } 257 258 if (i == VGE_TIMEOUT) { 259 device_printf(sc->vge_dev, "EEPROM read timed out\n"); 260 *dest = 0; 261 return; 262 } 263 264 /* Read the result */ 265 word = CSR_READ_2(sc, VGE_EERDDAT); 266 267 /* Turn off EEPROM access mode. */ 268 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 269 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 270 271 *dest = word; 272 273 return; 274} 275#endif 276 277/* 278 * Read a sequence of words from the EEPROM. 279 */ 280static void 281vge_read_eeprom(sc, dest, off, cnt, swap) 282 struct vge_softc *sc; 283 caddr_t dest; 284 int off; 285 int cnt; 286 int swap; 287{ 288 int i; 289#ifdef VGE_EEPROM 290 u_int16_t word = 0, *ptr; 291 292 for (i = 0; i < cnt; i++) { 293 vge_eeprom_getword(sc, off + i, &word); 294 ptr = (u_int16_t *)(dest + (i * 2)); 295 if (swap) 296 *ptr = ntohs(word); 297 else 298 *ptr = word; 299 } 300#else 301 for (i = 0; i < ETHER_ADDR_LEN; i++) 302 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 303#endif 304} 305 306static void 307vge_miipoll_stop(sc) 308 struct vge_softc *sc; 309{ 310 int i; 311 312 CSR_WRITE_1(sc, VGE_MIICMD, 0); 313 314 for (i = 0; i < VGE_TIMEOUT; i++) { 315 DELAY(1); 316 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 317 break; 318 } 319 320 if (i == VGE_TIMEOUT) 321 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 322 323 return; 324} 325 326static void 327vge_miipoll_start(sc) 328 struct vge_softc *sc; 329{ 330 int i; 331 332 /* First, make sure we're idle. */ 333 334 CSR_WRITE_1(sc, VGE_MIICMD, 0); 335 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 336 337 for (i = 0; i < VGE_TIMEOUT; i++) { 338 DELAY(1); 339 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 340 break; 341 } 342 343 if (i == VGE_TIMEOUT) { 344 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 345 return; 346 } 347 348 /* Now enable auto poll mode. */ 349 350 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 351 352 /* And make sure it started. */ 353 354 for (i = 0; i < VGE_TIMEOUT; i++) { 355 DELAY(1); 356 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 357 break; 358 } 359 360 if (i == VGE_TIMEOUT) 361 device_printf(sc->vge_dev, "failed to start MII autopoll\n"); 362 363 return; 364} 365 366static int 367vge_miibus_readreg(dev, phy, reg) 368 device_t dev; 369 int phy, reg; 370{ 371 struct vge_softc *sc; 372 int i; 373 u_int16_t rval = 0; 374 375 sc = device_get_softc(dev); 376 377 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 378 return(0); 379 380 VGE_LOCK(sc); 381 vge_miipoll_stop(sc); 382 383 /* Specify the register we want to read. */ 384 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 385 386 /* Issue read command. */ 387 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 388 389 /* Wait for the read command bit to self-clear. */ 390 for (i = 0; i < VGE_TIMEOUT; i++) { 391 DELAY(1); 392 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 393 break; 394 } 395 396 if (i == VGE_TIMEOUT) 397 device_printf(sc->vge_dev, "MII read timed out\n"); 398 else 399 rval = CSR_READ_2(sc, VGE_MIIDATA); 400 401 vge_miipoll_start(sc); 402 VGE_UNLOCK(sc); 403 404 return (rval); 405} 406 407static int 408vge_miibus_writereg(dev, phy, reg, data) 409 device_t dev; 410 int phy, reg, data; 411{ 412 struct vge_softc *sc; 413 int i, rval = 0; 414 415 sc = device_get_softc(dev); 416 417 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 418 return(0); 419 420 VGE_LOCK(sc); 421 vge_miipoll_stop(sc); 422 423 /* Specify the register we want to write. */ 424 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 425 426 /* Specify the data we want to write. */ 427 CSR_WRITE_2(sc, VGE_MIIDATA, data); 428 429 /* Issue write command. */ 430 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 431 432 /* Wait for the write command bit to self-clear. */ 433 for (i = 0; i < VGE_TIMEOUT; i++) { 434 DELAY(1); 435 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 436 break; 437 } 438 439 if (i == VGE_TIMEOUT) { 440 device_printf(sc->vge_dev, "MII write timed out\n"); 441 rval = EIO; 442 } 443 444 vge_miipoll_start(sc); 445 VGE_UNLOCK(sc); 446 447 return (rval); 448} 449 450static void 451vge_cam_clear(sc) 452 struct vge_softc *sc; 453{ 454 int i; 455 456 /* 457 * Turn off all the mask bits. This tells the chip 458 * that none of the entries in the CAM filter are valid. 459 * desired entries will be enabled as we fill the filter in. 460 */ 461 462 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 463 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 464 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 465 for (i = 0; i < 8; i++) 466 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 467 468 /* Clear the VLAN filter too. */ 469 470 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 471 for (i = 0; i < 8; i++) 472 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 473 474 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 475 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 476 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 477 478 sc->vge_camidx = 0; 479 480 return; 481} 482 483static int 484vge_cam_set(sc, addr) 485 struct vge_softc *sc; 486 uint8_t *addr; 487{ 488 int i, error = 0; 489 490 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 491 return(ENOSPC); 492 493 /* Select the CAM data page. */ 494 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 495 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 496 497 /* Set the filter entry we want to update and enable writing. */ 498 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 499 500 /* Write the address to the CAM registers */ 501 for (i = 0; i < ETHER_ADDR_LEN; i++) 502 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 503 504 /* Issue a write command. */ 505 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 506 507 /* Wake for it to clear. */ 508 for (i = 0; i < VGE_TIMEOUT; i++) { 509 DELAY(1); 510 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 511 break; 512 } 513 514 if (i == VGE_TIMEOUT) { 515 device_printf(sc->vge_dev, "setting CAM filter failed\n"); 516 error = EIO; 517 goto fail; 518 } 519 520 /* Select the CAM mask page. */ 521 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 522 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 523 524 /* Set the mask bit that enables this filter. */ 525 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 526 1<<(sc->vge_camidx & 7)); 527 528 sc->vge_camidx++; 529 530fail: 531 /* Turn off access to CAM. */ 532 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 533 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 534 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 535 536 return (error); 537} 538 539#if __FreeBSD_version < 502113 540static uint32_t 541vge_mchash(addr) 542 uint8_t *addr; 543{ 544 uint32_t crc, carry; 545 int idx, bit; 546 uint8_t data; 547 548 /* Compute CRC for the address value. */ 549 crc = 0xFFFFFFFF; /* initial value */ 550 551 for (idx = 0; idx < 6; idx++) { 552 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 553 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 554 crc <<= 1; 555 if (carry) 556 crc = (crc ^ 0x04c11db6) | carry; 557 } 558 } 559 560 return(crc); 561} 562#endif 563 564/* 565 * Program the multicast filter. We use the 64-entry CAM filter 566 * for perfect filtering. If there's more than 64 multicast addresses, 567 * we use the hash filter insted. 568 */ 569static void 570vge_setmulti(sc) 571 struct vge_softc *sc; 572{ 573 struct ifnet *ifp; 574 int error = 0/*, h = 0*/; 575 struct ifmultiaddr *ifma; 576 u_int32_t h, hashes[2] = { 0, 0 }; 577 578 ifp = &sc->arpcom.ac_if; 579 580 /* First, zot all the multicast entries. */ 581 vge_cam_clear(sc); 582 CSR_WRITE_4(sc, VGE_MAR0, 0); 583 CSR_WRITE_4(sc, VGE_MAR1, 0); 584 585 /* 586 * If the user wants allmulti or promisc mode, enable reception 587 * of all multicast frames. 588 */ 589 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 590 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 591 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 592 return; 593 } 594 595 /* Now program new ones */ 596 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 597 if (ifma->ifma_addr->sa_family != AF_LINK) 598 continue; 599 error = vge_cam_set(sc, 600 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 601 if (error) 602 break; 603 } 604 605 /* If there were too many addresses, use the hash filter. */ 606 if (error) { 607 vge_cam_clear(sc); 608 609 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 610 if (ifma->ifma_addr->sa_family != AF_LINK) 611 continue; 612#if __FreeBSD_version < 502113 613 h = vge_mchash(LLADDR((struct sockaddr_dl *) 614 ifma->ifma_addr)) >> 26; 615#else 616 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 617 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 618#endif 619 if (h < 32) 620 hashes[0] |= (1 << h); 621 else 622 hashes[1] |= (1 << (h - 32)); 623 } 624 625 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 626 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 627 } 628 629 return; 630} 631 632static void 633vge_reset(sc) 634 struct vge_softc *sc; 635{ 636 register int i; 637 638 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 639 640 for (i = 0; i < VGE_TIMEOUT; i++) { 641 DELAY(5); 642 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 643 break; 644 } 645 646 if (i == VGE_TIMEOUT) { 647 device_printf(sc->vge_dev, "soft reset timed out"); 648 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 649 DELAY(2000); 650 } 651 652 DELAY(5000); 653 654 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 655 656 for (i = 0; i < VGE_TIMEOUT; i++) { 657 DELAY(5); 658 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 659 break; 660 } 661 662 if (i == VGE_TIMEOUT) { 663 device_printf(sc->vge_dev, "EEPROM reload timed out\n"); 664 return; 665 } 666 667 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 668 669 return; 670} 671 672/* 673 * Probe for a VIA gigabit chip. Check the PCI vendor and device 674 * IDs against our list and return a device name if we find a match. 675 */ 676static int 677vge_probe(dev) 678 device_t dev; 679{ 680 struct vge_type *t; 681 struct vge_softc *sc; 682 683 t = vge_devs; 684 sc = device_get_softc(dev); 685 686 while (t->vge_name != NULL) { 687 if ((pci_get_vendor(dev) == t->vge_vid) && 688 (pci_get_device(dev) == t->vge_did)) { 689 device_set_desc(dev, t->vge_name); 690 return (BUS_PROBE_DEFAULT); 691 } 692 t++; 693 } 694 695 return (ENXIO); 696} 697 698static void 699vge_dma_map_rx_desc(arg, segs, nseg, mapsize, error) 700 void *arg; 701 bus_dma_segment_t *segs; 702 int nseg; 703 bus_size_t mapsize; 704 int error; 705{ 706 707 struct vge_dmaload_arg *ctx; 708 struct vge_rx_desc *d = NULL; 709 710 if (error) 711 return; 712 713 ctx = arg; 714 715 /* Signal error to caller if there's too many segments */ 716 if (nseg > ctx->vge_maxsegs) { 717 ctx->vge_maxsegs = 0; 718 return; 719 } 720 721 /* 722 * Map the segment array into descriptors. 723 */ 724 725 d = &ctx->sc->vge_ldata.vge_rx_list[ctx->vge_idx]; 726 727 /* If this descriptor is still owned by the chip, bail. */ 728 729 if (le32toh(d->vge_sts) & VGE_RDSTS_OWN) { 730 device_printf(ctx->sc->vge_dev, 731 "tried to map busy descriptor\n"); 732 ctx->vge_maxsegs = 0; 733 return; 734 } 735 736 d->vge_buflen = htole16(VGE_BUFLEN(segs[0].ds_len) | VGE_RXDESC_I); 737 d->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 738 d->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 739 d->vge_sts = 0; 740 d->vge_ctl = 0; 741 742 ctx->vge_maxsegs = 1; 743 744 return; 745} 746 747static void 748vge_dma_map_tx_desc(arg, segs, nseg, mapsize, error) 749 void *arg; 750 bus_dma_segment_t *segs; 751 int nseg; 752 bus_size_t mapsize; 753 int error; 754{ 755 struct vge_dmaload_arg *ctx; 756 struct vge_tx_desc *d = NULL; 757 struct vge_tx_frag *f; 758 int i = 0; 759 760 if (error) 761 return; 762 763 ctx = arg; 764 765 /* Signal error to caller if there's too many segments */ 766 if (nseg > ctx->vge_maxsegs) { 767 ctx->vge_maxsegs = 0; 768 return; 769 } 770 771 /* Map the segment array into descriptors. */ 772 773 d = &ctx->sc->vge_ldata.vge_tx_list[ctx->vge_idx]; 774 775 /* If this descriptor is still owned by the chip, bail. */ 776 777 if (le32toh(d->vge_sts) & VGE_TDSTS_OWN) { 778 ctx->vge_maxsegs = 0; 779 return; 780 } 781 782 for (i = 0; i < nseg; i++) { 783 f = &d->vge_frag[i]; 784 f->vge_buflen = htole16(VGE_BUFLEN(segs[i].ds_len)); 785 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[i].ds_addr)); 786 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[i].ds_addr) & 0xFFFF); 787 } 788 789 /* Argh. This chip does not autopad short frames */ 790 791 if (ctx->vge_m0->m_pkthdr.len < VGE_MIN_FRAMELEN) { 792 f = &d->vge_frag[i]; 793 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 794 ctx->vge_m0->m_pkthdr.len)); 795 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 796 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 797 ctx->vge_m0->m_pkthdr.len = VGE_MIN_FRAMELEN; 798 i++; 799 } 800 801 /* 802 * When telling the chip how many segments there are, we 803 * must use nsegs + 1 instead of just nsegs. Darned if I 804 * know why. 805 */ 806 i++; 807 808 d->vge_sts = ctx->vge_m0->m_pkthdr.len << 16; 809 d->vge_ctl = ctx->vge_flags|(i << 28)|VGE_TD_LS_NORM; 810 811 if (ctx->vge_m0->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 812 d->vge_ctl |= VGE_TDCTL_JUMBO; 813 814 ctx->vge_maxsegs = nseg; 815 816 return; 817} 818 819/* 820 * Map a single buffer address. 821 */ 822 823static void 824vge_dma_map_addr(arg, segs, nseg, error) 825 void *arg; 826 bus_dma_segment_t *segs; 827 int nseg; 828 int error; 829{ 830 bus_addr_t *addr; 831 832 if (error) 833 return; 834 835 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 836 addr = arg; 837 *addr = segs->ds_addr; 838 839 return; 840} 841 842static int 843vge_allocmem(dev, sc) 844 device_t dev; 845 struct vge_softc *sc; 846{ 847 int error; 848 int nseg; 849 int i; 850 851 /* 852 * Allocate map for RX mbufs. 853 */ 854 nseg = 32; 855 error = bus_dma_tag_create(sc->vge_parent_tag, ETHER_ALIGN, 0, 856 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 857 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 858 NULL, NULL, &sc->vge_ldata.vge_mtag); 859 if (error) { 860 device_printf(dev, "could not allocate dma tag\n"); 861 return (ENOMEM); 862 } 863 864 /* 865 * Allocate map for TX descriptor list. 866 */ 867 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 868 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 869 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 870 NULL, NULL, &sc->vge_ldata.vge_tx_list_tag); 871 if (error) { 872 device_printf(dev, "could not allocate dma tag\n"); 873 return (ENOMEM); 874 } 875 876 /* Allocate DMA'able memory for the TX ring */ 877 878 error = bus_dmamem_alloc(sc->vge_ldata.vge_tx_list_tag, 879 (void **)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 880 &sc->vge_ldata.vge_tx_list_map); 881 if (error) 882 return (ENOMEM); 883 884 /* Load the map for the TX ring. */ 885 886 error = bus_dmamap_load(sc->vge_ldata.vge_tx_list_tag, 887 sc->vge_ldata.vge_tx_list_map, sc->vge_ldata.vge_tx_list, 888 VGE_TX_LIST_SZ, vge_dma_map_addr, 889 &sc->vge_ldata.vge_tx_list_addr, BUS_DMA_NOWAIT); 890 891 /* Create DMA maps for TX buffers */ 892 893 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 894 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 895 &sc->vge_ldata.vge_tx_dmamap[i]); 896 if (error) { 897 device_printf(dev, "can't create DMA map for TX\n"); 898 return (ENOMEM); 899 } 900 } 901 902 /* 903 * Allocate map for RX descriptor list. 904 */ 905 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 906 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 907 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 908 NULL, NULL, &sc->vge_ldata.vge_rx_list_tag); 909 if (error) { 910 device_printf(dev, "could not allocate dma tag\n"); 911 return (ENOMEM); 912 } 913 914 /* Allocate DMA'able memory for the RX ring */ 915 916 error = bus_dmamem_alloc(sc->vge_ldata.vge_rx_list_tag, 917 (void **)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 918 &sc->vge_ldata.vge_rx_list_map); 919 if (error) 920 return (ENOMEM); 921 922 /* Load the map for the RX ring. */ 923 924 error = bus_dmamap_load(sc->vge_ldata.vge_rx_list_tag, 925 sc->vge_ldata.vge_rx_list_map, sc->vge_ldata.vge_rx_list, 926 VGE_TX_LIST_SZ, vge_dma_map_addr, 927 &sc->vge_ldata.vge_rx_list_addr, BUS_DMA_NOWAIT); 928 929 /* Create DMA maps for RX buffers */ 930 931 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 932 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 933 &sc->vge_ldata.vge_rx_dmamap[i]); 934 if (error) { 935 device_printf(dev, "can't create DMA map for RX\n"); 936 return (ENOMEM); 937 } 938 } 939 940 return (0); 941} 942 943/* 944 * Attach the interface. Allocate softc structures, do ifmedia 945 * setup and ethernet/BPF attach. 946 */ 947static int 948vge_attach(dev) 949 device_t dev; 950{ 951 u_char eaddr[ETHER_ADDR_LEN]; 952 struct vge_softc *sc; 953 struct ifnet *ifp; 954 int unit, error = 0, rid; 955 956 sc = device_get_softc(dev); 957 unit = device_get_unit(dev); 958 sc->vge_dev = dev; 959 960 mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 961 MTX_DEF | MTX_RECURSE); 962 /* 963 * Map control/status registers. 964 */ 965 pci_enable_busmaster(dev); 966 967 rid = VGE_PCI_LOMEM; 968 sc->vge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 969 0, ~0, 1, RF_ACTIVE); 970 971 if (sc->vge_res == NULL) { 972 printf ("vge%d: couldn't map ports/memory\n", unit); 973 error = ENXIO; 974 goto fail; 975 } 976 977 sc->vge_btag = rman_get_bustag(sc->vge_res); 978 sc->vge_bhandle = rman_get_bushandle(sc->vge_res); 979 980 /* Allocate interrupt */ 981 rid = 0; 982 sc->vge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 983 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE); 984 985 if (sc->vge_irq == NULL) { 986 printf("vge%d: couldn't map interrupt\n", unit); 987 error = ENXIO; 988 goto fail; 989 } 990 991 /* Reset the adapter. */ 992 vge_reset(sc); 993 994 /* 995 * Get station address from the EEPROM. 996 */ 997 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 998 999 sc->vge_unit = unit; 1000 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1001 1002#if __FreeBSD_version < 502113 1003 printf("vge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1004#endif 1005 1006 /* 1007 * Allocate the parent bus DMA tag appropriate for PCI. 1008 */ 1009#define VGE_NSEG_NEW 32 1010 error = bus_dma_tag_create(NULL, /* parent */ 1011 1, 0, /* alignment, boundary */ 1012 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1013 BUS_SPACE_MAXADDR, /* highaddr */ 1014 NULL, NULL, /* filter, filterarg */ 1015 MAXBSIZE, VGE_NSEG_NEW, /* maxsize, nsegments */ 1016 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1017 BUS_DMA_ALLOCNOW, /* flags */ 1018 NULL, NULL, /* lockfunc, lockarg */ 1019 &sc->vge_parent_tag); 1020 if (error) 1021 goto fail; 1022 1023 error = vge_allocmem(dev, sc); 1024 1025 if (error) 1026 goto fail; 1027 1028 /* Do MII setup */ 1029 if (mii_phy_probe(dev, &sc->vge_miibus, 1030 vge_ifmedia_upd, vge_ifmedia_sts)) { 1031 printf("vge%d: MII without any phy!\n", sc->vge_unit); 1032 error = ENXIO; 1033 goto fail; 1034 } 1035 1036 ifp = &sc->arpcom.ac_if; 1037 ifp->if_softc = sc; 1038 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1039 ifp->if_mtu = ETHERMTU; 1040 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1041 ifp->if_ioctl = vge_ioctl; 1042 ifp->if_capabilities = IFCAP_VLAN_MTU; 1043 ifp->if_start = vge_start; 1044 ifp->if_hwassist = VGE_CSUM_FEATURES; 1045 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1046#ifdef DEVICE_POLLING 1047#ifdef IFCAP_POLLING 1048 ifp->if_capabilities |= IFCAP_POLLING; 1049#endif 1050#endif 1051 ifp->if_watchdog = vge_watchdog; 1052 ifp->if_init = vge_init; 1053 ifp->if_baudrate = 1000000000; 1054 ifp->if_snd.ifq_maxlen = VGE_IFQ_MAXLEN; 1055 ifp->if_capenable = ifp->if_capabilities; 1056 1057 TASK_INIT(&sc->vge_txtask, 0, vge_tx_task, ifp); 1058 1059 /* 1060 * Call MI attach routine. 1061 */ 1062 ether_ifattach(ifp, eaddr); 1063 1064 /* Hook interrupt last to avoid having to lock softc */ 1065 error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE, 1066 vge_intr, sc, &sc->vge_intrhand); 1067 1068 if (error) { 1069 printf("vge%d: couldn't set up irq\n", unit); 1070 ether_ifdetach(ifp); 1071 goto fail; 1072 } 1073 1074fail: 1075 if (error) 1076 vge_detach(dev); 1077 1078 return (error); 1079} 1080 1081/* 1082 * Shutdown hardware and free up resources. This can be called any 1083 * time after the mutex has been initialized. It is called in both 1084 * the error case in attach and the normal detach case so it needs 1085 * to be careful about only freeing resources that have actually been 1086 * allocated. 1087 */ 1088static int 1089vge_detach(dev) 1090 device_t dev; 1091{ 1092 struct vge_softc *sc; 1093 struct ifnet *ifp; 1094 int i; 1095 1096 sc = device_get_softc(dev); 1097 KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized")); 1098 ifp = &sc->arpcom.ac_if; 1099 1100 /* These should only be active if attach succeeded */ 1101 if (device_is_attached(dev)) { 1102 vge_stop(sc); 1103 /* 1104 * Force off the IFF_UP flag here, in case someone 1105 * still had a BPF descriptor attached to this 1106 * interface. If they do, ether_ifattach() will cause 1107 * the BPF code to try and clear the promisc mode 1108 * flag, which will bubble down to vge_ioctl(), 1109 * which will try to call vge_init() again. This will 1110 * turn the NIC back on and restart the MII ticker, 1111 * which will panic the system when the kernel tries 1112 * to invoke the vge_tick() function that isn't there 1113 * anymore. 1114 */ 1115 ifp->if_flags &= ~IFF_UP; 1116 ether_ifdetach(ifp); 1117 } 1118 if (sc->vge_miibus) 1119 device_delete_child(dev, sc->vge_miibus); 1120 bus_generic_detach(dev); 1121 1122 if (sc->vge_intrhand) 1123 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); 1124 if (sc->vge_irq) 1125 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vge_irq); 1126 if (sc->vge_res) 1127 bus_release_resource(dev, SYS_RES_MEMORY, 1128 VGE_PCI_LOMEM, sc->vge_res); 1129 1130 /* Unload and free the RX DMA ring memory and map */ 1131 1132 if (sc->vge_ldata.vge_rx_list_tag) { 1133 bus_dmamap_unload(sc->vge_ldata.vge_rx_list_tag, 1134 sc->vge_ldata.vge_rx_list_map); 1135 bus_dmamem_free(sc->vge_ldata.vge_rx_list_tag, 1136 sc->vge_ldata.vge_rx_list, 1137 sc->vge_ldata.vge_rx_list_map); 1138 bus_dma_tag_destroy(sc->vge_ldata.vge_rx_list_tag); 1139 } 1140 1141 /* Unload and free the TX DMA ring memory and map */ 1142 1143 if (sc->vge_ldata.vge_tx_list_tag) { 1144 bus_dmamap_unload(sc->vge_ldata.vge_tx_list_tag, 1145 sc->vge_ldata.vge_tx_list_map); 1146 bus_dmamem_free(sc->vge_ldata.vge_tx_list_tag, 1147 sc->vge_ldata.vge_tx_list, 1148 sc->vge_ldata.vge_tx_list_map); 1149 bus_dma_tag_destroy(sc->vge_ldata.vge_tx_list_tag); 1150 } 1151 1152 /* Destroy all the RX and TX buffer maps */ 1153 1154 if (sc->vge_ldata.vge_mtag) { 1155 for (i = 0; i < VGE_TX_DESC_CNT; i++) 1156 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1157 sc->vge_ldata.vge_tx_dmamap[i]); 1158 for (i = 0; i < VGE_RX_DESC_CNT; i++) 1159 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1160 sc->vge_ldata.vge_rx_dmamap[i]); 1161 bus_dma_tag_destroy(sc->vge_ldata.vge_mtag); 1162 } 1163 1164 if (sc->vge_parent_tag) 1165 bus_dma_tag_destroy(sc->vge_parent_tag); 1166 1167 mtx_destroy(&sc->vge_mtx); 1168 1169 return (0); 1170} 1171 1172static int 1173vge_newbuf(sc, idx, m) 1174 struct vge_softc *sc; 1175 int idx; 1176 struct mbuf *m; 1177{ 1178 struct vge_dmaload_arg arg; 1179 struct mbuf *n = NULL; 1180 int i, error; 1181 1182 if (m == NULL) { 1183 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1184 if (n == NULL) 1185 return (ENOBUFS); 1186 m = n; 1187 } else 1188 m->m_data = m->m_ext.ext_buf; 1189 1190 1191#ifdef VGE_FIXUP_RX 1192 /* 1193 * This is part of an evil trick to deal with non-x86 platforms. 1194 * The VIA chip requires RX buffers to be aligned on 32-bit 1195 * boundaries, but that will hose non-x86 machines. To get around 1196 * this, we leave some empty space at the start of each buffer 1197 * and for non-x86 hosts, we copy the buffer back two bytes 1198 * to achieve word alignment. This is slightly more efficient 1199 * than allocating a new buffer, copying the contents, and 1200 * discarding the old buffer. 1201 */ 1202 m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_ETHER_ALIGN; 1203 m_adj(m, VGE_ETHER_ALIGN); 1204#else 1205 m->m_len = m->m_pkthdr.len = MCLBYTES; 1206#endif 1207 1208 arg.sc = sc; 1209 arg.vge_idx = idx; 1210 arg.vge_maxsegs = 1; 1211 arg.vge_flags = 0; 1212 1213 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, 1214 sc->vge_ldata.vge_rx_dmamap[idx], m, vge_dma_map_rx_desc, 1215 &arg, BUS_DMA_NOWAIT); 1216 if (error || arg.vge_maxsegs != 1) { 1217 if (n != NULL) 1218 m_freem(n); 1219 return (ENOMEM); 1220 } 1221 1222 /* 1223 * Note: the manual fails to document the fact that for 1224 * proper opration, the driver needs to replentish the RX 1225 * DMA ring 4 descriptors at a time (rather than one at a 1226 * time, like most chips). We can allocate the new buffers 1227 * but we should not set the OWN bits until we're ready 1228 * to hand back 4 of them in one shot. 1229 */ 1230 1231#define VGE_RXCHUNK 4 1232 sc->vge_rx_consumed++; 1233 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 1234 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 1235 sc->vge_ldata.vge_rx_list[i].vge_sts |= 1236 htole32(VGE_RDSTS_OWN); 1237 sc->vge_rx_consumed = 0; 1238 } 1239 1240 sc->vge_ldata.vge_rx_mbuf[idx] = m; 1241 1242 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1243 sc->vge_ldata.vge_rx_dmamap[idx], 1244 BUS_DMASYNC_PREREAD); 1245 1246 return (0); 1247} 1248 1249static int 1250vge_tx_list_init(sc) 1251 struct vge_softc *sc; 1252{ 1253 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 1254 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 1255 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 1256 1257 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1258 sc->vge_ldata.vge_tx_list_map, BUS_DMASYNC_PREWRITE); 1259 sc->vge_ldata.vge_tx_prodidx = 0; 1260 sc->vge_ldata.vge_tx_considx = 0; 1261 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 1262 1263 return (0); 1264} 1265 1266static int 1267vge_rx_list_init(sc) 1268 struct vge_softc *sc; 1269{ 1270 int i; 1271 1272 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 1273 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 1274 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 1275 1276 sc->vge_rx_consumed = 0; 1277 1278 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1279 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 1280 return (ENOBUFS); 1281 } 1282 1283 /* Flush the RX descriptors */ 1284 1285 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1286 sc->vge_ldata.vge_rx_list_map, 1287 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1288 1289 sc->vge_ldata.vge_rx_prodidx = 0; 1290 sc->vge_rx_consumed = 0; 1291 sc->vge_head = sc->vge_tail = NULL; 1292 1293 return (0); 1294} 1295 1296#ifdef VGE_FIXUP_RX 1297static __inline void 1298vge_fixup_rx(m) 1299 struct mbuf *m; 1300{ 1301 int i; 1302 uint16_t *src, *dst; 1303 1304 src = mtod(m, uint16_t *); 1305 dst = src - 1; 1306 1307 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1308 *dst++ = *src++; 1309 1310 m->m_data -= ETHER_ALIGN; 1311 1312 return; 1313} 1314#endif 1315 1316/* 1317 * RX handler. We support the reception of jumbo frames that have 1318 * been fragmented across multiple 2K mbuf cluster buffers. 1319 */ 1320static void 1321vge_rxeof(sc) 1322 struct vge_softc *sc; 1323{ 1324 struct mbuf *m; 1325 struct ifnet *ifp; 1326 int i, total_len; 1327 int lim = 0; 1328 struct vge_rx_desc *cur_rx; 1329 u_int32_t rxstat, rxctl; 1330 1331 VGE_LOCK_ASSERT(sc); 1332 ifp = &sc->arpcom.ac_if; 1333 i = sc->vge_ldata.vge_rx_prodidx; 1334 1335 /* Invalidate the descriptor memory */ 1336 1337 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1338 sc->vge_ldata.vge_rx_list_map, 1339 BUS_DMASYNC_POSTREAD); 1340 1341 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 1342 1343#ifdef DEVICE_POLLING 1344 if (ifp->if_flags & IFF_POLLING) { 1345 if (sc->rxcycles <= 0) 1346 break; 1347 sc->rxcycles--; 1348 } 1349#endif /* DEVICE_POLLING */ 1350 1351 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1352 m = sc->vge_ldata.vge_rx_mbuf[i]; 1353 total_len = VGE_RXBYTES(cur_rx); 1354 rxstat = le32toh(cur_rx->vge_sts); 1355 rxctl = le32toh(cur_rx->vge_ctl); 1356 1357 /* Invalidate the RX mbuf and unload its map */ 1358 1359 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1360 sc->vge_ldata.vge_rx_dmamap[i], 1361 BUS_DMASYNC_POSTWRITE); 1362 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1363 sc->vge_ldata.vge_rx_dmamap[i]); 1364 1365 /* 1366 * If the 'start of frame' bit is set, this indicates 1367 * either the first fragment in a multi-fragment receive, 1368 * or an intermediate fragment. Either way, we want to 1369 * accumulate the buffers. 1370 */ 1371 if (rxstat & VGE_RXPKT_SOF) { 1372 m->m_len = MCLBYTES - VGE_ETHER_ALIGN; 1373 if (sc->vge_head == NULL) 1374 sc->vge_head = sc->vge_tail = m; 1375 else { 1376 m->m_flags &= ~M_PKTHDR; 1377 sc->vge_tail->m_next = m; 1378 sc->vge_tail = m; 1379 } 1380 vge_newbuf(sc, i, NULL); 1381 VGE_RX_DESC_INC(i); 1382 continue; 1383 } 1384 1385 /* 1386 * Bad/error frames will have the RXOK bit cleared. 1387 * However, there's one error case we want to allow: 1388 * if a VLAN tagged frame arrives and the chip can't 1389 * match it against the CAM filter, it considers this 1390 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1391 * We don't want to drop the frame though: our VLAN 1392 * filtering is done in software. 1393 */ 1394 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1395 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1396 ifp->if_ierrors++; 1397 /* 1398 * If this is part of a multi-fragment packet, 1399 * discard all the pieces. 1400 */ 1401 if (sc->vge_head != NULL) { 1402 m_freem(sc->vge_head); 1403 sc->vge_head = sc->vge_tail = NULL; 1404 } 1405 vge_newbuf(sc, i, m); 1406 VGE_RX_DESC_INC(i); 1407 continue; 1408 } 1409 1410 /* 1411 * If allocating a replacement mbuf fails, 1412 * reload the current one. 1413 */ 1414 1415 if (vge_newbuf(sc, i, NULL)) { 1416 ifp->if_ierrors++; 1417 if (sc->vge_head != NULL) { 1418 m_freem(sc->vge_head); 1419 sc->vge_head = sc->vge_tail = NULL; 1420 } 1421 vge_newbuf(sc, i, m); 1422 VGE_RX_DESC_INC(i); 1423 continue; 1424 } 1425 1426 VGE_RX_DESC_INC(i); 1427 1428 if (sc->vge_head != NULL) { 1429 m->m_len = total_len % (MCLBYTES - VGE_ETHER_ALIGN); 1430 /* 1431 * Special case: if there's 4 bytes or less 1432 * in this buffer, the mbuf can be discarded: 1433 * the last 4 bytes is the CRC, which we don't 1434 * care about anyway. 1435 */ 1436 if (m->m_len <= ETHER_CRC_LEN) { 1437 sc->vge_tail->m_len -= 1438 (ETHER_CRC_LEN - m->m_len); 1439 m_freem(m); 1440 } else { 1441 m->m_len -= ETHER_CRC_LEN; 1442 m->m_flags &= ~M_PKTHDR; 1443 sc->vge_tail->m_next = m; 1444 } 1445 m = sc->vge_head; 1446 sc->vge_head = sc->vge_tail = NULL; 1447 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1448 } else 1449 m->m_pkthdr.len = m->m_len = 1450 (total_len - ETHER_CRC_LEN); 1451 1452#ifdef VGE_FIXUP_RX 1453 vge_fixup_rx(m); 1454#endif 1455 ifp->if_ipackets++; 1456 m->m_pkthdr.rcvif = ifp; 1457 1458 /* Do RX checksumming if enabled */ 1459 if (ifp->if_capenable & IFCAP_RXCSUM) { 1460 1461 /* Check IP header checksum */ 1462 if (rxctl & VGE_RDCTL_IPPKT) 1463 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1464 if (rxctl & VGE_RDCTL_IPCSUMOK) 1465 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1466 1467 /* Check TCP/UDP checksum */ 1468 if (rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT) && 1469 rxctl & VGE_RDCTL_PROTOCSUMOK) { 1470 m->m_pkthdr.csum_flags |= 1471 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1472 m->m_pkthdr.csum_data = 0xffff; 1473 } 1474 } 1475 1476 if (rxstat & VGE_RDSTS_VTAG) 1477 VLAN_INPUT_TAG(ifp, m, 1478 ntohs((rxctl & VGE_RDCTL_VLANID)), continue); 1479 1480 VGE_UNLOCK(sc); 1481 (*ifp->if_input)(ifp, m); 1482 VGE_LOCK(sc); 1483 1484 lim++; 1485 if (lim == VGE_RX_DESC_CNT) 1486 break; 1487 1488 } 1489 1490 /* Flush the RX DMA ring */ 1491 1492 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1493 sc->vge_ldata.vge_rx_list_map, 1494 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1495 1496 sc->vge_ldata.vge_rx_prodidx = i; 1497 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1498 1499 1500 return; 1501} 1502 1503static void 1504vge_txeof(sc) 1505 struct vge_softc *sc; 1506{ 1507 struct ifnet *ifp; 1508 u_int32_t txstat; 1509 int idx; 1510 1511 ifp = &sc->arpcom.ac_if; 1512 idx = sc->vge_ldata.vge_tx_considx; 1513 1514 /* Invalidate the TX descriptor list */ 1515 1516 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1517 sc->vge_ldata.vge_tx_list_map, 1518 BUS_DMASYNC_POSTREAD); 1519 1520 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1521 1522 txstat = le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1523 if (txstat & VGE_TDSTS_OWN) 1524 break; 1525 1526 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1527 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1528 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1529 sc->vge_ldata.vge_tx_dmamap[idx]); 1530 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1531 ifp->if_collisions++; 1532 if (txstat & VGE_TDSTS_TXERR) 1533 ifp->if_oerrors++; 1534 else 1535 ifp->if_opackets++; 1536 1537 sc->vge_ldata.vge_tx_free++; 1538 VGE_TX_DESC_INC(idx); 1539 } 1540 1541 /* No changes made to the TX ring, so no flush needed */ 1542 1543 if (idx != sc->vge_ldata.vge_tx_considx) { 1544 sc->vge_ldata.vge_tx_considx = idx; 1545 ifp->if_flags &= ~IFF_OACTIVE; 1546 ifp->if_timer = 0; 1547 } 1548 1549 /* 1550 * If not all descriptors have been released reaped yet, 1551 * reload the timer so that we will eventually get another 1552 * interrupt that will cause us to re-enter this routine. 1553 * This is done in case the transmitter has gone idle. 1554 */ 1555 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) { 1556 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1557 } 1558 1559 return; 1560} 1561 1562static void 1563vge_tick(xsc) 1564 void *xsc; 1565{ 1566 struct vge_softc *sc; 1567 struct ifnet *ifp; 1568 struct mii_data *mii; 1569 1570 sc = xsc; 1571 ifp = &sc->arpcom.ac_if; 1572 VGE_LOCK(sc); 1573 mii = device_get_softc(sc->vge_miibus); 1574 1575 mii_tick(mii); 1576 if (sc->vge_link) { 1577 if (!(mii->mii_media_status & IFM_ACTIVE)) { 1578 sc->vge_link = 0; 1579 if_link_state_change(&sc->arpcom.ac_if, 1580 LINK_STATE_DOWN); 1581 } 1582 } else { 1583 if (mii->mii_media_status & IFM_ACTIVE && 1584 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1585 sc->vge_link = 1; 1586 if_link_state_change(&sc->arpcom.ac_if, 1587 LINK_STATE_UP); 1588#if __FreeBSD_version < 502114 1589 if (ifp->if_snd.ifq_head != NULL) 1590#else 1591 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1592#endif 1593 taskqueue_enqueue(taskqueue_swi, 1594 &sc->vge_txtask); 1595 } 1596 } 1597 1598 VGE_UNLOCK(sc); 1599 1600 return; 1601} 1602 1603#ifdef DEVICE_POLLING 1604static void 1605vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1606{ 1607 struct vge_softc *sc = ifp->if_softc; 1608 1609 VGE_LOCK(sc); 1610#ifdef IFCAP_POLLING 1611 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1612 ether_poll_deregister(ifp); 1613 cmd = POLL_DEREGISTER; 1614 } 1615#endif 1616 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1617 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1618 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 1619 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1620 goto done; 1621 } 1622 1623 sc->rxcycles = count; 1624 vge_rxeof(sc); 1625 vge_txeof(sc); 1626 1627#if __FreeBSD_version < 502114 1628 if (ifp->if_snd.ifq_head != NULL) 1629#else 1630 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1631#endif 1632 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1633 1634 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1635 u_int32_t status; 1636 status = CSR_READ_4(sc, VGE_ISR); 1637 if (status == 0xFFFFFFFF) 1638 goto done; 1639 if (status) 1640 CSR_WRITE_4(sc, VGE_ISR, status); 1641 1642 /* 1643 * XXX check behaviour on receiver stalls. 1644 */ 1645 1646 if (status & VGE_ISR_TXDMA_STALL || 1647 status & VGE_ISR_RXDMA_STALL) 1648 vge_init(sc); 1649 1650 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1651 vge_rxeof(sc); 1652 ifp->if_ierrors++; 1653 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1654 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1655 } 1656 } 1657done: 1658 VGE_UNLOCK(sc); 1659} 1660#endif /* DEVICE_POLLING */ 1661 1662static void 1663vge_intr(arg) 1664 void *arg; 1665{ 1666 struct vge_softc *sc; 1667 struct ifnet *ifp; 1668 u_int32_t status; 1669 1670 sc = arg; 1671 1672 if (sc->suspended) { 1673 return; 1674 } 1675 1676 VGE_LOCK(sc); 1677 ifp = &sc->arpcom.ac_if; 1678 1679 if (!(ifp->if_flags & IFF_UP)) { 1680 VGE_UNLOCK(sc); 1681 return; 1682 } 1683 1684#ifdef DEVICE_POLLING 1685 if (ifp->if_flags & IFF_POLLING) 1686 goto done; 1687 if ( 1688#ifdef IFCAP_POLLING 1689 (ifp->if_capenable & IFCAP_POLLING) && 1690#endif 1691 ether_poll_register(vge_poll, ifp)) { /* ok, disable interrupts */ 1692 CSR_WRITE_4(sc, VGE_IMR, 0); 1693 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1694 vge_poll(ifp, 0, 1); 1695 goto done; 1696 } 1697 1698#endif /* DEVICE_POLLING */ 1699 1700 /* Disable interrupts */ 1701 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1702 1703 for (;;) { 1704 1705 status = CSR_READ_4(sc, VGE_ISR); 1706 /* If the card has gone away the read returns 0xffff. */ 1707 if (status == 0xFFFFFFFF) 1708 break; 1709 1710 if (status) 1711 CSR_WRITE_4(sc, VGE_ISR, status); 1712 1713 if ((status & VGE_INTRS) == 0) 1714 break; 1715 1716 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1717 vge_rxeof(sc); 1718 1719 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1720 vge_rxeof(sc); 1721 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1722 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1723 } 1724 1725 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1726 vge_txeof(sc); 1727 1728 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1729 vge_init(sc); 1730 1731 if (status & VGE_ISR_LINKSTS) 1732 vge_tick(sc); 1733 } 1734 1735 /* Re-enable interrupts */ 1736 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1737 1738#ifdef DEVICE_POLLING 1739done: 1740#endif 1741 VGE_UNLOCK(sc); 1742 1743#if __FreeBSD_version < 502114 1744 if (ifp->if_snd.ifq_head != NULL) 1745#else 1746 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1747#endif 1748 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1749 1750 return; 1751} 1752 1753static int 1754vge_encap(sc, m_head, idx) 1755 struct vge_softc *sc; 1756 struct mbuf *m_head; 1757 int idx; 1758{ 1759 struct mbuf *m_new = NULL; 1760 struct vge_dmaload_arg arg; 1761 bus_dmamap_t map; 1762 int error; 1763 struct m_tag *mtag; 1764 1765 if (sc->vge_ldata.vge_tx_free <= 2) 1766 return (EFBIG); 1767 1768 arg.vge_flags = 0; 1769 1770 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1771 arg.vge_flags |= VGE_TDCTL_IPCSUM; 1772 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1773 arg.vge_flags |= VGE_TDCTL_TCPCSUM; 1774 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1775 arg.vge_flags |= VGE_TDCTL_UDPCSUM; 1776 1777 arg.sc = sc; 1778 arg.vge_idx = idx; 1779 arg.vge_m0 = m_head; 1780 arg.vge_maxsegs = VGE_TX_FRAGS; 1781 1782 map = sc->vge_ldata.vge_tx_dmamap[idx]; 1783 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1784 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1785 1786 if (error && error != EFBIG) { 1787 printf("vge%d: can't map mbuf (error %d)\n", 1788 sc->vge_unit, error); 1789 return (ENOBUFS); 1790 } 1791 1792 /* Too many segments to map, coalesce into a single mbuf */ 1793 1794 if (error || arg.vge_maxsegs == 0) { 1795 m_new = m_defrag(m_head, M_DONTWAIT); 1796 if (m_new == NULL) 1797 return (1); 1798 else 1799 m_head = m_new; 1800 1801 arg.sc = sc; 1802 arg.vge_m0 = m_head; 1803 arg.vge_idx = idx; 1804 arg.vge_maxsegs = 1; 1805 1806 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1807 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1808 if (error) { 1809 printf("vge%d: can't map mbuf (error %d)\n", 1810 sc->vge_unit, error); 1811 return (EFBIG); 1812 } 1813 } 1814 1815 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1816 sc->vge_ldata.vge_tx_free--; 1817 1818 /* 1819 * Set up hardware VLAN tagging. 1820 */ 1821 1822 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); 1823 if (mtag != NULL) 1824 sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1825 htole32(htons(VLAN_TAG_VALUE(mtag)) | VGE_TDCTL_VTAG); 1826 1827 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1828 1829 return (0); 1830} 1831 1832static void 1833vge_tx_task(arg, npending) 1834 void *arg; 1835 int npending; 1836{ 1837 struct ifnet *ifp; 1838 1839 ifp = arg; 1840 vge_start(ifp); 1841 1842 return; 1843} 1844 1845/* 1846 * Main transmit routine. 1847 */ 1848 1849static void 1850vge_start(ifp) 1851 struct ifnet *ifp; 1852{ 1853 struct vge_softc *sc; 1854 struct mbuf *m_head = NULL; 1855 int idx, pidx = 0; 1856 1857 sc = ifp->if_softc; 1858 VGE_LOCK(sc); 1859 1860 if (!sc->vge_link || ifp->if_flags & IFF_OACTIVE) { 1861 VGE_UNLOCK(sc); 1862 return; 1863 } 1864 1865#if __FreeBSD_version < 502114 1866 if (ifp->if_snd.ifq_head == NULL) { 1867#else 1868 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 1869#endif 1870 VGE_UNLOCK(sc); 1871 return; 1872 } 1873 1874 idx = sc->vge_ldata.vge_tx_prodidx; 1875 1876 pidx = idx - 1; 1877 if (pidx < 0) 1878 pidx = VGE_TX_DESC_CNT - 1; 1879 1880 1881 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1882#if __FreeBSD_version < 502114 1883 IF_DEQUEUE(&ifp->if_snd, m_head); 1884#else 1885 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1886#endif 1887 if (m_head == NULL) 1888 break; 1889 1890 if (vge_encap(sc, m_head, idx)) { 1891#if __FreeBSD_version >= 502114 1892 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1893#else 1894 IF_PREPEND(&ifp->if_snd, m_head); 1895#endif 1896 ifp->if_flags |= IFF_OACTIVE; 1897 break; 1898 } 1899 1900 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1901 htole16(VGE_TXDESC_Q); 1902 1903 pidx = idx; 1904 VGE_TX_DESC_INC(idx); 1905 1906 /* 1907 * If there's a BPF listener, bounce a copy of this frame 1908 * to him. 1909 */ 1910 BPF_MTAP(ifp, m_head); 1911 } 1912 1913 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1914 VGE_UNLOCK(sc); 1915 return; 1916 } 1917 1918 /* Flush the TX descriptors */ 1919 1920 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1921 sc->vge_ldata.vge_tx_list_map, 1922 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1923 1924 /* Issue a transmit command. */ 1925 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1926 1927 sc->vge_ldata.vge_tx_prodidx = idx; 1928 1929 /* 1930 * Use the countdown timer for interrupt moderation. 1931 * 'TX done' interrupts are disabled. Instead, we reset the 1932 * countdown timer, which will begin counting until it hits 1933 * the value in the SSTIMER register, and then trigger an 1934 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1935 * the timer count is reloaded. Only when the transmitter 1936 * is idle will the timer hit 0 and an interrupt fire. 1937 */ 1938 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1939 1940 VGE_UNLOCK(sc); 1941 1942 /* 1943 * Set a timeout in case the chip goes out to lunch. 1944 */ 1945 ifp->if_timer = 5; 1946 1947 return; 1948} 1949 1950static void 1951vge_init(xsc) 1952 void *xsc; 1953{ 1954 struct vge_softc *sc = xsc; 1955 struct ifnet *ifp = &sc->arpcom.ac_if; 1956 struct mii_data *mii; 1957 int i; 1958 1959 VGE_LOCK(sc); 1960 mii = device_get_softc(sc->vge_miibus); 1961 1962 /* 1963 * Cancel pending I/O and free all RX/TX buffers. 1964 */ 1965 vge_stop(sc); 1966 vge_reset(sc); 1967 1968 /* 1969 * Initialize the RX and TX descriptors and mbufs. 1970 */ 1971 1972 vge_rx_list_init(sc); 1973 vge_tx_list_init(sc); 1974 1975 /* Set our station address */ 1976 for (i = 0; i < ETHER_ADDR_LEN; i++) 1977 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1978 1979 /* 1980 * Set receive FIFO threshold. Also allow transmission and 1981 * reception of VLAN tagged frames. 1982 */ 1983 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1984 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1985 1986 /* Set DMA burst length */ 1987 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1988 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1989 1990 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1991 1992 /* Set collision backoff algorithm */ 1993 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1994 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1995 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1996 1997 /* Disable LPSEL field in priority resolution */ 1998 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1999 2000 /* 2001 * Load the addresses of the DMA queues into the chip. 2002 * Note that we only use one transmit queue. 2003 */ 2004 2005 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 2006 VGE_ADDR_LO(sc->vge_ldata.vge_tx_list_addr)); 2007 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 2008 2009 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 2010 VGE_ADDR_LO(sc->vge_ldata.vge_rx_list_addr)); 2011 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 2012 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 2013 2014 /* Enable and wake up the RX descriptor queue */ 2015 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 2016 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 2017 2018 /* Enable the TX descriptor queue */ 2019 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 2020 2021 /* Set up the receive filter -- allow large frames for VLANs. */ 2022 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 2023 2024 /* If we want promiscuous mode, set the allframes bit. */ 2025 if (ifp->if_flags & IFF_PROMISC) { 2026 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 2027 } 2028 2029 /* Set capture broadcast bit to capture broadcast frames. */ 2030 if (ifp->if_flags & IFF_BROADCAST) { 2031 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 2032 } 2033 2034 /* Set multicast bit to capture multicast frames. */ 2035 if (ifp->if_flags & IFF_MULTICAST) { 2036 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 2037 } 2038 2039 /* Init the cam filter. */ 2040 vge_cam_clear(sc); 2041 2042 /* Init the multicast filter. */ 2043 vge_setmulti(sc); 2044 2045 /* Enable flow control */ 2046 2047 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 2048 2049 /* Enable jumbo frame reception (if desired) */ 2050 2051 /* Start the MAC. */ 2052 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 2053 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 2054 CSR_WRITE_1(sc, VGE_CRS0, 2055 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 2056 2057 /* 2058 * Configure one-shot timer for microsecond 2059 * resulution and load it for 500 usecs. 2060 */ 2061 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 2062 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 2063 2064 /* 2065 * Configure interrupt moderation for receive. Enable 2066 * the holdoff counter and load it, and set the RX 2067 * suppression count to the number of descriptors we 2068 * want to allow before triggering an interrupt. 2069 * The holdoff timer is in units of 20 usecs. 2070 */ 2071 2072#ifdef notyet 2073 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 2074 /* Select the interrupt holdoff timer page. */ 2075 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2076 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 2077 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 2078 2079 /* Enable use of the holdoff timer. */ 2080 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 2081 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 2082 2083 /* Select the RX suppression threshold page. */ 2084 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2085 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 2086 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 2087 2088 /* Restore the page select bits. */ 2089 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2090 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 2091#endif 2092 2093#ifdef DEVICE_POLLING 2094 /* 2095 * Disable interrupts if we are polling. 2096 */ 2097 if (ifp->if_flags & IFF_POLLING) { 2098 CSR_WRITE_4(sc, VGE_IMR, 0); 2099 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2100 } else /* otherwise ... */ 2101#endif /* DEVICE_POLLING */ 2102 { 2103 /* 2104 * Enable interrupts. 2105 */ 2106 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2107 CSR_WRITE_4(sc, VGE_ISR, 0); 2108 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2109 } 2110 2111 mii_mediachg(mii); 2112 2113 ifp->if_flags |= IFF_RUNNING; 2114 ifp->if_flags &= ~IFF_OACTIVE; 2115 2116 sc->vge_if_flags = 0; 2117 sc->vge_link = 0; 2118 2119 VGE_UNLOCK(sc); 2120 2121 return; 2122} 2123 2124/* 2125 * Set media options. 2126 */ 2127static int 2128vge_ifmedia_upd(ifp) 2129 struct ifnet *ifp; 2130{ 2131 struct vge_softc *sc; 2132 struct mii_data *mii; 2133 2134 sc = ifp->if_softc; 2135 mii = device_get_softc(sc->vge_miibus); 2136 mii_mediachg(mii); 2137 2138 return (0); 2139} 2140 2141/* 2142 * Report current media status. 2143 */ 2144static void 2145vge_ifmedia_sts(ifp, ifmr) 2146 struct ifnet *ifp; 2147 struct ifmediareq *ifmr; 2148{ 2149 struct vge_softc *sc; 2150 struct mii_data *mii; 2151 2152 sc = ifp->if_softc; 2153 mii = device_get_softc(sc->vge_miibus); 2154 2155 mii_pollstat(mii); 2156 ifmr->ifm_active = mii->mii_media_active; 2157 ifmr->ifm_status = mii->mii_media_status; 2158 2159 return; 2160} 2161 2162static void 2163vge_miibus_statchg(dev) 2164 device_t dev; 2165{ 2166 struct vge_softc *sc; 2167 struct mii_data *mii; 2168 struct ifmedia_entry *ife; 2169 2170 sc = device_get_softc(dev); 2171 mii = device_get_softc(sc->vge_miibus); 2172 ife = mii->mii_media.ifm_cur; 2173 2174 /* 2175 * If the user manually selects a media mode, we need to turn 2176 * on the forced MAC mode bit in the DIAGCTL register. If the 2177 * user happens to choose a full duplex mode, we also need to 2178 * set the 'force full duplex' bit. This applies only to 2179 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2180 * mode is disabled, and in 1000baseT mode, full duplex is 2181 * always implied, so we turn on the forced mode bit but leave 2182 * the FDX bit cleared. 2183 */ 2184 2185 switch (IFM_SUBTYPE(ife->ifm_media)) { 2186 case IFM_AUTO: 2187 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2188 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2189 break; 2190 case IFM_1000_T: 2191 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2192 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2193 break; 2194 case IFM_100_TX: 2195 case IFM_10_T: 2196 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2197 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2198 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2199 } else { 2200 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2201 } 2202 break; 2203 default: 2204 device_printf(dev, "unknown media type: %x\n", 2205 IFM_SUBTYPE(ife->ifm_media)); 2206 break; 2207 } 2208 2209 return; 2210} 2211 2212static int 2213vge_ioctl(ifp, command, data) 2214 struct ifnet *ifp; 2215 u_long command; 2216 caddr_t data; 2217{ 2218 struct vge_softc *sc = ifp->if_softc; 2219 struct ifreq *ifr = (struct ifreq *) data; 2220 struct mii_data *mii; 2221 int error = 0; 2222 2223 switch (command) { 2224 case SIOCSIFMTU: 2225 if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2226 error = EINVAL; 2227 ifp->if_mtu = ifr->ifr_mtu; 2228 break; 2229 case SIOCSIFFLAGS: 2230 if (ifp->if_flags & IFF_UP) { 2231 if (ifp->if_flags & IFF_RUNNING && 2232 ifp->if_flags & IFF_PROMISC && 2233 !(sc->vge_if_flags & IFF_PROMISC)) { 2234 CSR_SETBIT_1(sc, VGE_RXCTL, 2235 VGE_RXCTL_RX_PROMISC); 2236 vge_setmulti(sc); 2237 } else if (ifp->if_flags & IFF_RUNNING && 2238 !(ifp->if_flags & IFF_PROMISC) && 2239 sc->vge_if_flags & IFF_PROMISC) { 2240 CSR_CLRBIT_1(sc, VGE_RXCTL, 2241 VGE_RXCTL_RX_PROMISC); 2242 vge_setmulti(sc); 2243 } else 2244 vge_init(sc); 2245 } else { 2246 if (ifp->if_flags & IFF_RUNNING) 2247 vge_stop(sc); 2248 } 2249 sc->vge_if_flags = ifp->if_flags; 2250 break; 2251 case SIOCADDMULTI: 2252 case SIOCDELMULTI: 2253 vge_setmulti(sc); 2254 break; 2255 case SIOCGIFMEDIA: 2256 case SIOCSIFMEDIA: 2257 mii = device_get_softc(sc->vge_miibus); 2258 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2259 break; 2260 case SIOCSIFCAP: 2261#ifdef IFCAP_POLLING 2262 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_POLLING); 2263#else 2264 ifp->if_capenable &= ~(IFCAP_HWCSUM); 2265#endif 2266 ifp->if_capenable |= 2267#ifdef IFCAP_POLLING 2268 ifr->ifr_reqcap & (IFCAP_HWCSUM | IFCAP_POLLING); 2269#else 2270 ifr->ifr_reqcap & (IFCAP_HWCSUM); 2271#endif 2272 if (ifp->if_capenable & IFCAP_TXCSUM) 2273 ifp->if_hwassist = VGE_CSUM_FEATURES; 2274 else 2275 ifp->if_hwassist = 0; 2276 if (ifp->if_flags & IFF_RUNNING) 2277 vge_init(sc); 2278 break; 2279 default: 2280 error = ether_ioctl(ifp, command, data); 2281 break; 2282 } 2283 2284 return (error); 2285} 2286 2287static void 2288vge_watchdog(ifp) 2289 struct ifnet *ifp; 2290{ 2291 struct vge_softc *sc; 2292 2293 sc = ifp->if_softc; 2294 VGE_LOCK(sc); 2295 printf("vge%d: watchdog timeout\n", sc->vge_unit); 2296 ifp->if_oerrors++; 2297 2298 vge_txeof(sc); 2299 vge_rxeof(sc); 2300 2301 vge_init(sc); 2302 2303 VGE_UNLOCK(sc); 2304 2305 return; 2306} 2307 2308/* 2309 * Stop the adapter and free any mbufs allocated to the 2310 * RX and TX lists. 2311 */ 2312static void 2313vge_stop(sc) 2314 struct vge_softc *sc; 2315{ 2316 register int i; 2317 struct ifnet *ifp; 2318 2319 VGE_LOCK(sc); 2320 ifp = &sc->arpcom.ac_if; 2321 ifp->if_timer = 0; 2322 2323 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2324#ifdef DEVICE_POLLING 2325 ether_poll_deregister(ifp); 2326#endif /* DEVICE_POLLING */ 2327 2328 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2329 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2330 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2331 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2332 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2333 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2334 2335 if (sc->vge_head != NULL) { 2336 m_freem(sc->vge_head); 2337 sc->vge_head = sc->vge_tail = NULL; 2338 } 2339 2340 /* Free the TX list buffers. */ 2341 2342 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 2343 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 2344 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2345 sc->vge_ldata.vge_tx_dmamap[i]); 2346 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 2347 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 2348 } 2349 } 2350 2351 /* Free the RX list buffers. */ 2352 2353 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 2354 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 2355 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2356 sc->vge_ldata.vge_rx_dmamap[i]); 2357 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 2358 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 2359 } 2360 } 2361 2362 VGE_UNLOCK(sc); 2363 2364 return; 2365} 2366 2367/* 2368 * Device suspend routine. Stop the interface and save some PCI 2369 * settings in case the BIOS doesn't restore them properly on 2370 * resume. 2371 */ 2372static int 2373vge_suspend(dev) 2374 device_t dev; 2375{ 2376 struct vge_softc *sc; 2377 int i; 2378 2379 sc = device_get_softc(dev); 2380 2381 vge_stop(sc); 2382 2383 sc->suspended = 1; 2384 2385 return (0); 2386} 2387 2388/* 2389 * Device resume routine. Restore some PCI settings in case the BIOS 2390 * doesn't, re-enable busmastering, and restart the interface if 2391 * appropriate. 2392 */ 2393static int 2394vge_resume(dev) 2395 device_t dev; 2396{ 2397 struct vge_softc *sc; 2398 struct ifnet *ifp; 2399 int i; 2400 2401 sc = device_get_softc(dev); 2402 ifp = &sc->arpcom.ac_if; 2403 2404 /* reenable busmastering */ 2405 pci_enable_busmaster(dev); 2406 pci_enable_io(dev, SYS_RES_MEMORY); 2407 2408 /* reinitialize interface if necessary */ 2409 if (ifp->if_flags & IFF_UP) 2410 vge_init(sc); 2411 2412 sc->suspended = 0; 2413 2414 return (0); 2415} 2416 2417/* 2418 * Stop all chip I/O so that the kernel's probe routines don't 2419 * get confused by errant DMAs when rebooting. 2420 */ 2421static void 2422vge_shutdown(dev) 2423 device_t dev; 2424{ 2425 struct vge_softc *sc; 2426 2427 sc = device_get_softc(dev); 2428 2429 vge_stop(sc); 2430} 2431