if_vge.c revision 200519
1139749Simp/*- 2135048Swpaul * Copyright (c) 2004 3135048Swpaul * Bill Paul <wpaul@windriver.com>. All rights reserved. 4135048Swpaul * 5135048Swpaul * Redistribution and use in source and binary forms, with or without 6135048Swpaul * modification, are permitted provided that the following conditions 7135048Swpaul * are met: 8135048Swpaul * 1. Redistributions of source code must retain the above copyright 9135048Swpaul * notice, this list of conditions and the following disclaimer. 10135048Swpaul * 2. Redistributions in binary form must reproduce the above copyright 11135048Swpaul * notice, this list of conditions and the following disclaimer in the 12135048Swpaul * documentation and/or other materials provided with the distribution. 13135048Swpaul * 3. All advertising materials mentioning features or use of this software 14135048Swpaul * must display the following acknowledgement: 15135048Swpaul * This product includes software developed by Bill Paul. 16135048Swpaul * 4. Neither the name of the author nor the names of any co-contributors 17135048Swpaul * may be used to endorse or promote products derived from this software 18135048Swpaul * without specific prior written permission. 19135048Swpaul * 20135048Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21135048Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22135048Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23135048Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24135048Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25135048Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26135048Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27135048Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28135048Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29135048Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30135048Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 31135048Swpaul */ 32135048Swpaul 33135048Swpaul#include <sys/cdefs.h> 34135048Swpaul__FBSDID("$FreeBSD: head/sys/dev/vge/if_vge.c 200519 2009-12-14 17:53:10Z yongari $"); 35135048Swpaul 36135048Swpaul/* 37135048Swpaul * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 38135048Swpaul * 39135048Swpaul * Written by Bill Paul <wpaul@windriver.com> 40135048Swpaul * Senior Networking Software Engineer 41135048Swpaul * Wind River Systems 42135048Swpaul */ 43135048Swpaul 44135048Swpaul/* 45135048Swpaul * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 46135048Swpaul * combines a tri-speed ethernet MAC and PHY, with the following 47135048Swpaul * features: 48135048Swpaul * 49135048Swpaul * o Jumbo frame support up to 16K 50135048Swpaul * o Transmit and receive flow control 51135048Swpaul * o IPv4 checksum offload 52135048Swpaul * o VLAN tag insertion and stripping 53135048Swpaul * o TCP large send 54135048Swpaul * o 64-bit multicast hash table filter 55135048Swpaul * o 64 entry CAM filter 56135048Swpaul * o 16K RX FIFO and 48K TX FIFO memory 57135048Swpaul * o Interrupt moderation 58135048Swpaul * 59135048Swpaul * The VT6122 supports up to four transmit DMA queues. The descriptors 60135048Swpaul * in the transmit ring can address up to 7 data fragments; frames which 61135048Swpaul * span more than 7 data buffers must be coalesced, but in general the 62135048Swpaul * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 63135048Swpaul * long. The receive descriptors address only a single buffer. 64135048Swpaul * 65135048Swpaul * There are two peculiar design issues with the VT6122. One is that 66135048Swpaul * receive data buffers must be aligned on a 32-bit boundary. This is 67135048Swpaul * not a problem where the VT6122 is used as a LOM device in x86-based 68135048Swpaul * systems, but on architectures that generate unaligned access traps, we 69135048Swpaul * have to do some copying. 70135048Swpaul * 71135048Swpaul * The other issue has to do with the way 64-bit addresses are handled. 72135048Swpaul * The DMA descriptors only allow you to specify 48 bits of addressing 73135048Swpaul * information. The remaining 16 bits are specified using one of the 74135048Swpaul * I/O registers. If you only have a 32-bit system, then this isn't 75135048Swpaul * an issue, but if you have a 64-bit system and more than 4GB of 76135048Swpaul * memory, you must have to make sure your network data buffers reside 77135048Swpaul * in the same 48-bit 'segment.' 78135048Swpaul * 79135048Swpaul * Special thanks to Ryan Fu at VIA Networking for providing documentation 80135048Swpaul * and sample NICs for testing. 81135048Swpaul */ 82135048Swpaul 83150968Sglebius#ifdef HAVE_KERNEL_OPTION_HEADERS 84150968Sglebius#include "opt_device_polling.h" 85150968Sglebius#endif 86150968Sglebius 87135048Swpaul#include <sys/param.h> 88135048Swpaul#include <sys/endian.h> 89135048Swpaul#include <sys/systm.h> 90135048Swpaul#include <sys/sockio.h> 91135048Swpaul#include <sys/mbuf.h> 92135048Swpaul#include <sys/malloc.h> 93135048Swpaul#include <sys/module.h> 94135048Swpaul#include <sys/kernel.h> 95135048Swpaul#include <sys/socket.h> 96135048Swpaul 97135048Swpaul#include <net/if.h> 98135048Swpaul#include <net/if_arp.h> 99135048Swpaul#include <net/ethernet.h> 100135048Swpaul#include <net/if_dl.h> 101135048Swpaul#include <net/if_media.h> 102147256Sbrooks#include <net/if_types.h> 103135048Swpaul#include <net/if_vlan_var.h> 104135048Swpaul 105135048Swpaul#include <net/bpf.h> 106135048Swpaul 107135048Swpaul#include <machine/bus.h> 108135048Swpaul#include <machine/resource.h> 109135048Swpaul#include <sys/bus.h> 110135048Swpaul#include <sys/rman.h> 111135048Swpaul 112135048Swpaul#include <dev/mii/mii.h> 113135048Swpaul#include <dev/mii/miivar.h> 114135048Swpaul 115135048Swpaul#include <dev/pci/pcireg.h> 116135048Swpaul#include <dev/pci/pcivar.h> 117135048Swpaul 118135048SwpaulMODULE_DEPEND(vge, pci, 1, 1, 1); 119135048SwpaulMODULE_DEPEND(vge, ether, 1, 1, 1); 120135048SwpaulMODULE_DEPEND(vge, miibus, 1, 1, 1); 121135048Swpaul 122151545Simp/* "device miibus" required. See GENERIC if you get errors here. */ 123135048Swpaul#include "miibus_if.h" 124135048Swpaul 125135048Swpaul#include <dev/vge/if_vgereg.h> 126135048Swpaul#include <dev/vge/if_vgevar.h> 127135048Swpaul 128135048Swpaul#define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 129135048Swpaul 130135048Swpaul/* 131135048Swpaul * Various supported device vendors/types and their names. 132135048Swpaul */ 133135048Swpaulstatic struct vge_type vge_devs[] = { 134135048Swpaul { VIA_VENDORID, VIA_DEVICEID_61XX, 135135048Swpaul "VIA Networking Gigabit Ethernet" }, 136135048Swpaul { 0, 0, NULL } 137135048Swpaul}; 138135048Swpaul 139135048Swpaulstatic int vge_probe (device_t); 140135048Swpaulstatic int vge_attach (device_t); 141135048Swpaulstatic int vge_detach (device_t); 142135048Swpaul 143135048Swpaulstatic int vge_encap (struct vge_softc *, struct mbuf *, int); 144135048Swpaul 145135048Swpaulstatic void vge_dma_map_addr (void *, bus_dma_segment_t *, int, int); 146135048Swpaulstatic void vge_dma_map_rx_desc (void *, bus_dma_segment_t *, int, 147135048Swpaul bus_size_t, int); 148135048Swpaulstatic void vge_dma_map_tx_desc (void *, bus_dma_segment_t *, int, 149135048Swpaul bus_size_t, int); 150135048Swpaulstatic int vge_allocmem (device_t, struct vge_softc *); 151135048Swpaulstatic int vge_newbuf (struct vge_softc *, int, struct mbuf *); 152135048Swpaulstatic int vge_rx_list_init (struct vge_softc *); 153135048Swpaulstatic int vge_tx_list_init (struct vge_softc *); 154135048Swpaul#ifdef VGE_FIXUP_RX 155135048Swpaulstatic __inline void vge_fixup_rx 156135048Swpaul (struct mbuf *); 157135048Swpaul#endif 158193096Sattiliostatic int vge_rxeof (struct vge_softc *); 159135048Swpaulstatic void vge_txeof (struct vge_softc *); 160135048Swpaulstatic void vge_intr (void *); 161135048Swpaulstatic void vge_tick (void *); 162135048Swpaulstatic void vge_start (struct ifnet *); 163199543Sjhbstatic void vge_start_locked (struct ifnet *); 164135048Swpaulstatic int vge_ioctl (struct ifnet *, u_long, caddr_t); 165135048Swpaulstatic void vge_init (void *); 166199543Sjhbstatic void vge_init_locked (struct vge_softc *); 167135048Swpaulstatic void vge_stop (struct vge_softc *); 168199543Sjhbstatic void vge_watchdog (void *); 169135048Swpaulstatic int vge_suspend (device_t); 170135048Swpaulstatic int vge_resume (device_t); 171173839Syongaristatic int vge_shutdown (device_t); 172135048Swpaulstatic int vge_ifmedia_upd (struct ifnet *); 173135048Swpaulstatic void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 174135048Swpaul 175145520Swpaul#ifdef VGE_EEPROM 176135048Swpaulstatic void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 177145520Swpaul#endif 178135048Swpaulstatic void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 179135048Swpaul 180135048Swpaulstatic void vge_miipoll_start (struct vge_softc *); 181135048Swpaulstatic void vge_miipoll_stop (struct vge_softc *); 182135048Swpaulstatic int vge_miibus_readreg (device_t, int, int); 183135048Swpaulstatic int vge_miibus_writereg (device_t, int, int, int); 184135048Swpaulstatic void vge_miibus_statchg (device_t); 185135048Swpaul 186135048Swpaulstatic void vge_cam_clear (struct vge_softc *); 187135048Swpaulstatic int vge_cam_set (struct vge_softc *, uint8_t *); 188135048Swpaulstatic void vge_setmulti (struct vge_softc *); 189135048Swpaulstatic void vge_reset (struct vge_softc *); 190135048Swpaul 191135048Swpaul#define VGE_PCI_LOIO 0x10 192135048Swpaul#define VGE_PCI_LOMEM 0x14 193135048Swpaul 194135048Swpaulstatic device_method_t vge_methods[] = { 195135048Swpaul /* Device interface */ 196135048Swpaul DEVMETHOD(device_probe, vge_probe), 197135048Swpaul DEVMETHOD(device_attach, vge_attach), 198135048Swpaul DEVMETHOD(device_detach, vge_detach), 199135048Swpaul DEVMETHOD(device_suspend, vge_suspend), 200135048Swpaul DEVMETHOD(device_resume, vge_resume), 201135048Swpaul DEVMETHOD(device_shutdown, vge_shutdown), 202135048Swpaul 203135048Swpaul /* bus interface */ 204135048Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 205135048Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 206135048Swpaul 207135048Swpaul /* MII interface */ 208135048Swpaul DEVMETHOD(miibus_readreg, vge_miibus_readreg), 209135048Swpaul DEVMETHOD(miibus_writereg, vge_miibus_writereg), 210135048Swpaul DEVMETHOD(miibus_statchg, vge_miibus_statchg), 211135048Swpaul 212135048Swpaul { 0, 0 } 213135048Swpaul}; 214135048Swpaul 215135048Swpaulstatic driver_t vge_driver = { 216135048Swpaul "vge", 217135048Swpaul vge_methods, 218135048Swpaul sizeof(struct vge_softc) 219135048Swpaul}; 220135048Swpaul 221135048Swpaulstatic devclass_t vge_devclass; 222135048Swpaul 223135048SwpaulDRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0); 224135048SwpaulDRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0); 225135048Swpaul 226145520Swpaul#ifdef VGE_EEPROM 227135048Swpaul/* 228135048Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 229135048Swpaul */ 230135048Swpaulstatic void 231135048Swpaulvge_eeprom_getword(sc, addr, dest) 232135048Swpaul struct vge_softc *sc; 233135048Swpaul int addr; 234135048Swpaul u_int16_t *dest; 235135048Swpaul{ 236200519Syongari int i; 237135048Swpaul u_int16_t word = 0; 238135048Swpaul 239135048Swpaul /* 240135048Swpaul * Enter EEPROM embedded programming mode. In order to 241135048Swpaul * access the EEPROM at all, we first have to set the 242135048Swpaul * EELOAD bit in the CHIPCFG2 register. 243135048Swpaul */ 244135048Swpaul CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 245135048Swpaul CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 246135048Swpaul 247135048Swpaul /* Select the address of the word we want to read */ 248135048Swpaul CSR_WRITE_1(sc, VGE_EEADDR, addr); 249135048Swpaul 250135048Swpaul /* Issue read command */ 251135048Swpaul CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 252135048Swpaul 253135048Swpaul /* Wait for the done bit to be set. */ 254135048Swpaul for (i = 0; i < VGE_TIMEOUT; i++) { 255135048Swpaul if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 256135048Swpaul break; 257135048Swpaul } 258135048Swpaul 259135048Swpaul if (i == VGE_TIMEOUT) { 260135048Swpaul device_printf(sc->vge_dev, "EEPROM read timed out\n"); 261135048Swpaul *dest = 0; 262135048Swpaul return; 263135048Swpaul } 264135048Swpaul 265135048Swpaul /* Read the result */ 266135048Swpaul word = CSR_READ_2(sc, VGE_EERDDAT); 267135048Swpaul 268135048Swpaul /* Turn off EEPROM access mode. */ 269135048Swpaul CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 270135048Swpaul CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 271135048Swpaul 272135048Swpaul *dest = word; 273135048Swpaul 274135048Swpaul return; 275135048Swpaul} 276145520Swpaul#endif 277135048Swpaul 278135048Swpaul/* 279135048Swpaul * Read a sequence of words from the EEPROM. 280135048Swpaul */ 281135048Swpaulstatic void 282135048Swpaulvge_read_eeprom(sc, dest, off, cnt, swap) 283135048Swpaul struct vge_softc *sc; 284135048Swpaul caddr_t dest; 285135048Swpaul int off; 286135048Swpaul int cnt; 287135048Swpaul int swap; 288135048Swpaul{ 289135048Swpaul int i; 290145520Swpaul#ifdef VGE_EEPROM 291135048Swpaul u_int16_t word = 0, *ptr; 292135048Swpaul 293135048Swpaul for (i = 0; i < cnt; i++) { 294135048Swpaul vge_eeprom_getword(sc, off + i, &word); 295135048Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 296135048Swpaul if (swap) 297135048Swpaul *ptr = ntohs(word); 298135048Swpaul else 299135048Swpaul *ptr = word; 300135048Swpaul } 301145520Swpaul#else 302145520Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 303145520Swpaul dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 304145520Swpaul#endif 305135048Swpaul} 306135048Swpaul 307135048Swpaulstatic void 308135048Swpaulvge_miipoll_stop(sc) 309135048Swpaul struct vge_softc *sc; 310135048Swpaul{ 311135048Swpaul int i; 312135048Swpaul 313135048Swpaul CSR_WRITE_1(sc, VGE_MIICMD, 0); 314135048Swpaul 315135048Swpaul for (i = 0; i < VGE_TIMEOUT; i++) { 316135048Swpaul DELAY(1); 317135048Swpaul if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 318135048Swpaul break; 319135048Swpaul } 320135048Swpaul 321135048Swpaul if (i == VGE_TIMEOUT) 322135048Swpaul device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 323135048Swpaul 324135048Swpaul return; 325135048Swpaul} 326135048Swpaul 327135048Swpaulstatic void 328135048Swpaulvge_miipoll_start(sc) 329135048Swpaul struct vge_softc *sc; 330135048Swpaul{ 331135048Swpaul int i; 332135048Swpaul 333135048Swpaul /* First, make sure we're idle. */ 334135048Swpaul 335135048Swpaul CSR_WRITE_1(sc, VGE_MIICMD, 0); 336135048Swpaul CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 337135048Swpaul 338135048Swpaul for (i = 0; i < VGE_TIMEOUT; i++) { 339135048Swpaul DELAY(1); 340135048Swpaul if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 341135048Swpaul break; 342135048Swpaul } 343135048Swpaul 344135048Swpaul if (i == VGE_TIMEOUT) { 345135048Swpaul device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 346135048Swpaul return; 347135048Swpaul } 348135048Swpaul 349135048Swpaul /* Now enable auto poll mode. */ 350135048Swpaul 351135048Swpaul CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 352135048Swpaul 353135048Swpaul /* And make sure it started. */ 354135048Swpaul 355135048Swpaul for (i = 0; i < VGE_TIMEOUT; i++) { 356135048Swpaul DELAY(1); 357135048Swpaul if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 358135048Swpaul break; 359135048Swpaul } 360135048Swpaul 361135048Swpaul if (i == VGE_TIMEOUT) 362135048Swpaul device_printf(sc->vge_dev, "failed to start MII autopoll\n"); 363135048Swpaul 364135048Swpaul return; 365135048Swpaul} 366135048Swpaul 367135048Swpaulstatic int 368135048Swpaulvge_miibus_readreg(dev, phy, reg) 369135048Swpaul device_t dev; 370135048Swpaul int phy, reg; 371135048Swpaul{ 372135048Swpaul struct vge_softc *sc; 373135048Swpaul int i; 374135048Swpaul u_int16_t rval = 0; 375135048Swpaul 376135048Swpaul sc = device_get_softc(dev); 377135048Swpaul 378135048Swpaul if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 379135048Swpaul return(0); 380135048Swpaul 381135048Swpaul vge_miipoll_stop(sc); 382135048Swpaul 383135048Swpaul /* Specify the register we want to read. */ 384135048Swpaul CSR_WRITE_1(sc, VGE_MIIADDR, reg); 385135048Swpaul 386135048Swpaul /* Issue read command. */ 387135048Swpaul CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 388135048Swpaul 389135048Swpaul /* Wait for the read command bit to self-clear. */ 390135048Swpaul for (i = 0; i < VGE_TIMEOUT; i++) { 391135048Swpaul DELAY(1); 392135048Swpaul if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 393135048Swpaul break; 394135048Swpaul } 395135048Swpaul 396135048Swpaul if (i == VGE_TIMEOUT) 397135048Swpaul device_printf(sc->vge_dev, "MII read timed out\n"); 398135048Swpaul else 399135048Swpaul rval = CSR_READ_2(sc, VGE_MIIDATA); 400135048Swpaul 401135048Swpaul vge_miipoll_start(sc); 402135048Swpaul 403135048Swpaul return (rval); 404135048Swpaul} 405135048Swpaul 406135048Swpaulstatic int 407135048Swpaulvge_miibus_writereg(dev, phy, reg, data) 408135048Swpaul device_t dev; 409135048Swpaul int phy, reg, data; 410135048Swpaul{ 411135048Swpaul struct vge_softc *sc; 412135048Swpaul int i, rval = 0; 413135048Swpaul 414135048Swpaul sc = device_get_softc(dev); 415135048Swpaul 416135048Swpaul if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 417135048Swpaul return(0); 418135048Swpaul 419135048Swpaul vge_miipoll_stop(sc); 420135048Swpaul 421135048Swpaul /* Specify the register we want to write. */ 422135048Swpaul CSR_WRITE_1(sc, VGE_MIIADDR, reg); 423135048Swpaul 424135048Swpaul /* Specify the data we want to write. */ 425135048Swpaul CSR_WRITE_2(sc, VGE_MIIDATA, data); 426135048Swpaul 427135048Swpaul /* Issue write command. */ 428135048Swpaul CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 429135048Swpaul 430135048Swpaul /* Wait for the write command bit to self-clear. */ 431135048Swpaul for (i = 0; i < VGE_TIMEOUT; i++) { 432135048Swpaul DELAY(1); 433135048Swpaul if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 434135048Swpaul break; 435135048Swpaul } 436135048Swpaul 437135048Swpaul if (i == VGE_TIMEOUT) { 438135048Swpaul device_printf(sc->vge_dev, "MII write timed out\n"); 439135048Swpaul rval = EIO; 440135048Swpaul } 441135048Swpaul 442135048Swpaul vge_miipoll_start(sc); 443135048Swpaul 444135048Swpaul return (rval); 445135048Swpaul} 446135048Swpaul 447135048Swpaulstatic void 448135048Swpaulvge_cam_clear(sc) 449135048Swpaul struct vge_softc *sc; 450135048Swpaul{ 451135048Swpaul int i; 452135048Swpaul 453135048Swpaul /* 454135048Swpaul * Turn off all the mask bits. This tells the chip 455135048Swpaul * that none of the entries in the CAM filter are valid. 456135048Swpaul * desired entries will be enabled as we fill the filter in. 457135048Swpaul */ 458135048Swpaul 459135048Swpaul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 460135048Swpaul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 461135048Swpaul CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 462135048Swpaul for (i = 0; i < 8; i++) 463135048Swpaul CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 464135048Swpaul 465135048Swpaul /* Clear the VLAN filter too. */ 466135048Swpaul 467135048Swpaul CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 468135048Swpaul for (i = 0; i < 8; i++) 469135048Swpaul CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 470135048Swpaul 471135048Swpaul CSR_WRITE_1(sc, VGE_CAMADDR, 0); 472135048Swpaul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 473135048Swpaul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 474135048Swpaul 475135048Swpaul sc->vge_camidx = 0; 476135048Swpaul 477135048Swpaul return; 478135048Swpaul} 479135048Swpaul 480135048Swpaulstatic int 481135048Swpaulvge_cam_set(sc, addr) 482135048Swpaul struct vge_softc *sc; 483135048Swpaul uint8_t *addr; 484135048Swpaul{ 485135048Swpaul int i, error = 0; 486135048Swpaul 487135048Swpaul if (sc->vge_camidx == VGE_CAM_MAXADDRS) 488135048Swpaul return(ENOSPC); 489135048Swpaul 490135048Swpaul /* Select the CAM data page. */ 491135048Swpaul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 492135048Swpaul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 493135048Swpaul 494135048Swpaul /* Set the filter entry we want to update and enable writing. */ 495135048Swpaul CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 496135048Swpaul 497135048Swpaul /* Write the address to the CAM registers */ 498135048Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 499135048Swpaul CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 500135048Swpaul 501135048Swpaul /* Issue a write command. */ 502135048Swpaul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 503135048Swpaul 504135048Swpaul /* Wake for it to clear. */ 505135048Swpaul for (i = 0; i < VGE_TIMEOUT; i++) { 506135048Swpaul DELAY(1); 507135048Swpaul if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 508135048Swpaul break; 509135048Swpaul } 510135048Swpaul 511135048Swpaul if (i == VGE_TIMEOUT) { 512135048Swpaul device_printf(sc->vge_dev, "setting CAM filter failed\n"); 513135048Swpaul error = EIO; 514135048Swpaul goto fail; 515135048Swpaul } 516135048Swpaul 517135048Swpaul /* Select the CAM mask page. */ 518135048Swpaul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 519135048Swpaul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 520135048Swpaul 521135048Swpaul /* Set the mask bit that enables this filter. */ 522135048Swpaul CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 523135048Swpaul 1<<(sc->vge_camidx & 7)); 524135048Swpaul 525135048Swpaul sc->vge_camidx++; 526135048Swpaul 527135048Swpaulfail: 528135048Swpaul /* Turn off access to CAM. */ 529135048Swpaul CSR_WRITE_1(sc, VGE_CAMADDR, 0); 530135048Swpaul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 531135048Swpaul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 532135048Swpaul 533135048Swpaul return (error); 534135048Swpaul} 535135048Swpaul 536135048Swpaul/* 537135048Swpaul * Program the multicast filter. We use the 64-entry CAM filter 538135048Swpaul * for perfect filtering. If there's more than 64 multicast addresses, 539135048Swpaul * we use the hash filter insted. 540135048Swpaul */ 541135048Swpaulstatic void 542135048Swpaulvge_setmulti(sc) 543135048Swpaul struct vge_softc *sc; 544135048Swpaul{ 545135048Swpaul struct ifnet *ifp; 546135048Swpaul int error = 0/*, h = 0*/; 547135048Swpaul struct ifmultiaddr *ifma; 548135048Swpaul u_int32_t h, hashes[2] = { 0, 0 }; 549135048Swpaul 550147256Sbrooks ifp = sc->vge_ifp; 551135048Swpaul 552135048Swpaul /* First, zot all the multicast entries. */ 553135048Swpaul vge_cam_clear(sc); 554135048Swpaul CSR_WRITE_4(sc, VGE_MAR0, 0); 555135048Swpaul CSR_WRITE_4(sc, VGE_MAR1, 0); 556135048Swpaul 557135048Swpaul /* 558135048Swpaul * If the user wants allmulti or promisc mode, enable reception 559135048Swpaul * of all multicast frames. 560135048Swpaul */ 561135048Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 562135048Swpaul CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 563135048Swpaul CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 564135048Swpaul return; 565135048Swpaul } 566135048Swpaul 567135048Swpaul /* Now program new ones */ 568195049Srwatson if_maddr_rlock(ifp); 569135048Swpaul TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 570135048Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 571135048Swpaul continue; 572135048Swpaul error = vge_cam_set(sc, 573135048Swpaul LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 574135048Swpaul if (error) 575135048Swpaul break; 576135048Swpaul } 577135048Swpaul 578135048Swpaul /* If there were too many addresses, use the hash filter. */ 579135048Swpaul if (error) { 580135048Swpaul vge_cam_clear(sc); 581135048Swpaul 582135048Swpaul TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 583135048Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 584135048Swpaul continue; 585135048Swpaul h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 586135048Swpaul ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 587135048Swpaul if (h < 32) 588135048Swpaul hashes[0] |= (1 << h); 589135048Swpaul else 590135048Swpaul hashes[1] |= (1 << (h - 32)); 591135048Swpaul } 592135048Swpaul 593135048Swpaul CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 594135048Swpaul CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 595135048Swpaul } 596195049Srwatson if_maddr_runlock(ifp); 597135048Swpaul 598135048Swpaul return; 599135048Swpaul} 600135048Swpaul 601135048Swpaulstatic void 602135048Swpaulvge_reset(sc) 603135048Swpaul struct vge_softc *sc; 604135048Swpaul{ 605200519Syongari int i; 606135048Swpaul 607135048Swpaul CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 608135048Swpaul 609135048Swpaul for (i = 0; i < VGE_TIMEOUT; i++) { 610135048Swpaul DELAY(5); 611135048Swpaul if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 612135048Swpaul break; 613135048Swpaul } 614135048Swpaul 615135048Swpaul if (i == VGE_TIMEOUT) { 616135048Swpaul device_printf(sc->vge_dev, "soft reset timed out"); 617135048Swpaul CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 618135048Swpaul DELAY(2000); 619135048Swpaul } 620135048Swpaul 621135048Swpaul DELAY(5000); 622135048Swpaul 623135048Swpaul CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 624135048Swpaul 625135048Swpaul for (i = 0; i < VGE_TIMEOUT; i++) { 626135048Swpaul DELAY(5); 627135048Swpaul if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 628135048Swpaul break; 629135048Swpaul } 630135048Swpaul 631135048Swpaul if (i == VGE_TIMEOUT) { 632135048Swpaul device_printf(sc->vge_dev, "EEPROM reload timed out\n"); 633135048Swpaul return; 634135048Swpaul } 635135048Swpaul 636135048Swpaul CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 637135048Swpaul 638135048Swpaul return; 639135048Swpaul} 640135048Swpaul 641135048Swpaul/* 642135048Swpaul * Probe for a VIA gigabit chip. Check the PCI vendor and device 643135048Swpaul * IDs against our list and return a device name if we find a match. 644135048Swpaul */ 645135048Swpaulstatic int 646135048Swpaulvge_probe(dev) 647135048Swpaul device_t dev; 648135048Swpaul{ 649135048Swpaul struct vge_type *t; 650135048Swpaul 651135048Swpaul t = vge_devs; 652135048Swpaul 653135048Swpaul while (t->vge_name != NULL) { 654135048Swpaul if ((pci_get_vendor(dev) == t->vge_vid) && 655135048Swpaul (pci_get_device(dev) == t->vge_did)) { 656135048Swpaul device_set_desc(dev, t->vge_name); 657142880Simp return (BUS_PROBE_DEFAULT); 658135048Swpaul } 659135048Swpaul t++; 660135048Swpaul } 661135048Swpaul 662135048Swpaul return (ENXIO); 663135048Swpaul} 664135048Swpaul 665135048Swpaulstatic void 666135048Swpaulvge_dma_map_rx_desc(arg, segs, nseg, mapsize, error) 667135048Swpaul void *arg; 668135048Swpaul bus_dma_segment_t *segs; 669135048Swpaul int nseg; 670135048Swpaul bus_size_t mapsize; 671135048Swpaul int error; 672135048Swpaul{ 673135048Swpaul 674135048Swpaul struct vge_dmaload_arg *ctx; 675135048Swpaul struct vge_rx_desc *d = NULL; 676135048Swpaul 677135048Swpaul if (error) 678135048Swpaul return; 679135048Swpaul 680135048Swpaul ctx = arg; 681135048Swpaul 682135048Swpaul /* Signal error to caller if there's too many segments */ 683135048Swpaul if (nseg > ctx->vge_maxsegs) { 684135048Swpaul ctx->vge_maxsegs = 0; 685135048Swpaul return; 686135048Swpaul } 687135048Swpaul 688135048Swpaul /* 689135048Swpaul * Map the segment array into descriptors. 690135048Swpaul */ 691135048Swpaul 692135048Swpaul d = &ctx->sc->vge_ldata.vge_rx_list[ctx->vge_idx]; 693135048Swpaul 694135048Swpaul /* If this descriptor is still owned by the chip, bail. */ 695135048Swpaul 696135048Swpaul if (le32toh(d->vge_sts) & VGE_RDSTS_OWN) { 697135048Swpaul device_printf(ctx->sc->vge_dev, 698135048Swpaul "tried to map busy descriptor\n"); 699135048Swpaul ctx->vge_maxsegs = 0; 700135048Swpaul return; 701135048Swpaul } 702135048Swpaul 703135048Swpaul d->vge_buflen = htole16(VGE_BUFLEN(segs[0].ds_len) | VGE_RXDESC_I); 704135048Swpaul d->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 705135048Swpaul d->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 706135048Swpaul d->vge_sts = 0; 707135048Swpaul d->vge_ctl = 0; 708135048Swpaul 709135048Swpaul ctx->vge_maxsegs = 1; 710135048Swpaul 711135048Swpaul return; 712135048Swpaul} 713135048Swpaul 714135048Swpaulstatic void 715135048Swpaulvge_dma_map_tx_desc(arg, segs, nseg, mapsize, error) 716135048Swpaul void *arg; 717135048Swpaul bus_dma_segment_t *segs; 718135048Swpaul int nseg; 719135048Swpaul bus_size_t mapsize; 720135048Swpaul int error; 721135048Swpaul{ 722135048Swpaul struct vge_dmaload_arg *ctx; 723135048Swpaul struct vge_tx_desc *d = NULL; 724135048Swpaul struct vge_tx_frag *f; 725135048Swpaul int i = 0; 726135048Swpaul 727135048Swpaul if (error) 728135048Swpaul return; 729135048Swpaul 730135048Swpaul ctx = arg; 731135048Swpaul 732135048Swpaul /* Signal error to caller if there's too many segments */ 733135048Swpaul if (nseg > ctx->vge_maxsegs) { 734135048Swpaul ctx->vge_maxsegs = 0; 735135048Swpaul return; 736135048Swpaul } 737135048Swpaul 738135048Swpaul /* Map the segment array into descriptors. */ 739135048Swpaul 740135048Swpaul d = &ctx->sc->vge_ldata.vge_tx_list[ctx->vge_idx]; 741135048Swpaul 742135048Swpaul /* If this descriptor is still owned by the chip, bail. */ 743135048Swpaul 744135048Swpaul if (le32toh(d->vge_sts) & VGE_TDSTS_OWN) { 745135048Swpaul ctx->vge_maxsegs = 0; 746135048Swpaul return; 747135048Swpaul } 748135048Swpaul 749135048Swpaul for (i = 0; i < nseg; i++) { 750135048Swpaul f = &d->vge_frag[i]; 751135048Swpaul f->vge_buflen = htole16(VGE_BUFLEN(segs[i].ds_len)); 752135048Swpaul f->vge_addrlo = htole32(VGE_ADDR_LO(segs[i].ds_addr)); 753135048Swpaul f->vge_addrhi = htole16(VGE_ADDR_HI(segs[i].ds_addr) & 0xFFFF); 754135048Swpaul } 755135048Swpaul 756135048Swpaul /* Argh. This chip does not autopad short frames */ 757135048Swpaul 758135048Swpaul if (ctx->vge_m0->m_pkthdr.len < VGE_MIN_FRAMELEN) { 759135048Swpaul f = &d->vge_frag[i]; 760135048Swpaul f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 761135048Swpaul ctx->vge_m0->m_pkthdr.len)); 762135048Swpaul f->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 763135048Swpaul f->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 764135048Swpaul ctx->vge_m0->m_pkthdr.len = VGE_MIN_FRAMELEN; 765135048Swpaul i++; 766135048Swpaul } 767135048Swpaul 768135048Swpaul /* 769135048Swpaul * When telling the chip how many segments there are, we 770135048Swpaul * must use nsegs + 1 instead of just nsegs. Darned if I 771135048Swpaul * know why. 772135048Swpaul */ 773135048Swpaul i++; 774135048Swpaul 775135048Swpaul d->vge_sts = ctx->vge_m0->m_pkthdr.len << 16; 776135048Swpaul d->vge_ctl = ctx->vge_flags|(i << 28)|VGE_TD_LS_NORM; 777135048Swpaul 778135048Swpaul if (ctx->vge_m0->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 779135048Swpaul d->vge_ctl |= VGE_TDCTL_JUMBO; 780135048Swpaul 781135048Swpaul ctx->vge_maxsegs = nseg; 782135048Swpaul 783135048Swpaul return; 784135048Swpaul} 785135048Swpaul 786135048Swpaul/* 787135048Swpaul * Map a single buffer address. 788135048Swpaul */ 789135048Swpaul 790135048Swpaulstatic void 791135048Swpaulvge_dma_map_addr(arg, segs, nseg, error) 792135048Swpaul void *arg; 793135048Swpaul bus_dma_segment_t *segs; 794135048Swpaul int nseg; 795135048Swpaul int error; 796135048Swpaul{ 797135048Swpaul bus_addr_t *addr; 798135048Swpaul 799135048Swpaul if (error) 800135048Swpaul return; 801135048Swpaul 802135048Swpaul KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 803135048Swpaul addr = arg; 804135048Swpaul *addr = segs->ds_addr; 805135048Swpaul 806135048Swpaul return; 807135048Swpaul} 808135048Swpaul 809135048Swpaulstatic int 810135048Swpaulvge_allocmem(dev, sc) 811135048Swpaul device_t dev; 812135048Swpaul struct vge_softc *sc; 813135048Swpaul{ 814135048Swpaul int error; 815135048Swpaul int nseg; 816135048Swpaul int i; 817135048Swpaul 818135048Swpaul /* 819135048Swpaul * Allocate map for RX mbufs. 820135048Swpaul */ 821135048Swpaul nseg = 32; 822135048Swpaul error = bus_dma_tag_create(sc->vge_parent_tag, ETHER_ALIGN, 0, 823135048Swpaul BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 824135048Swpaul NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 825135048Swpaul NULL, NULL, &sc->vge_ldata.vge_mtag); 826135048Swpaul if (error) { 827135048Swpaul device_printf(dev, "could not allocate dma tag\n"); 828135048Swpaul return (ENOMEM); 829135048Swpaul } 830135048Swpaul 831135048Swpaul /* 832135048Swpaul * Allocate map for TX descriptor list. 833135048Swpaul */ 834135048Swpaul error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 835135048Swpaul 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 836135048Swpaul NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 837135048Swpaul NULL, NULL, &sc->vge_ldata.vge_tx_list_tag); 838135048Swpaul if (error) { 839135048Swpaul device_printf(dev, "could not allocate dma tag\n"); 840135048Swpaul return (ENOMEM); 841135048Swpaul } 842135048Swpaul 843135048Swpaul /* Allocate DMA'able memory for the TX ring */ 844135048Swpaul 845135048Swpaul error = bus_dmamem_alloc(sc->vge_ldata.vge_tx_list_tag, 846135048Swpaul (void **)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 847135048Swpaul &sc->vge_ldata.vge_tx_list_map); 848135048Swpaul if (error) 849135048Swpaul return (ENOMEM); 850135048Swpaul 851135048Swpaul /* Load the map for the TX ring. */ 852135048Swpaul 853135048Swpaul error = bus_dmamap_load(sc->vge_ldata.vge_tx_list_tag, 854135048Swpaul sc->vge_ldata.vge_tx_list_map, sc->vge_ldata.vge_tx_list, 855135048Swpaul VGE_TX_LIST_SZ, vge_dma_map_addr, 856135048Swpaul &sc->vge_ldata.vge_tx_list_addr, BUS_DMA_NOWAIT); 857135048Swpaul 858135048Swpaul /* Create DMA maps for TX buffers */ 859135048Swpaul 860135048Swpaul for (i = 0; i < VGE_TX_DESC_CNT; i++) { 861135048Swpaul error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 862135048Swpaul &sc->vge_ldata.vge_tx_dmamap[i]); 863135048Swpaul if (error) { 864135048Swpaul device_printf(dev, "can't create DMA map for TX\n"); 865135048Swpaul return (ENOMEM); 866135048Swpaul } 867135048Swpaul } 868135048Swpaul 869135048Swpaul /* 870135048Swpaul * Allocate map for RX descriptor list. 871135048Swpaul */ 872135048Swpaul error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 873135048Swpaul 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 874135048Swpaul NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 875135048Swpaul NULL, NULL, &sc->vge_ldata.vge_rx_list_tag); 876135048Swpaul if (error) { 877135048Swpaul device_printf(dev, "could not allocate dma tag\n"); 878135048Swpaul return (ENOMEM); 879135048Swpaul } 880135048Swpaul 881135048Swpaul /* Allocate DMA'able memory for the RX ring */ 882135048Swpaul 883135048Swpaul error = bus_dmamem_alloc(sc->vge_ldata.vge_rx_list_tag, 884135048Swpaul (void **)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 885135048Swpaul &sc->vge_ldata.vge_rx_list_map); 886135048Swpaul if (error) 887135048Swpaul return (ENOMEM); 888135048Swpaul 889135048Swpaul /* Load the map for the RX ring. */ 890135048Swpaul 891135048Swpaul error = bus_dmamap_load(sc->vge_ldata.vge_rx_list_tag, 892135048Swpaul sc->vge_ldata.vge_rx_list_map, sc->vge_ldata.vge_rx_list, 893135048Swpaul VGE_TX_LIST_SZ, vge_dma_map_addr, 894135048Swpaul &sc->vge_ldata.vge_rx_list_addr, BUS_DMA_NOWAIT); 895135048Swpaul 896135048Swpaul /* Create DMA maps for RX buffers */ 897135048Swpaul 898135048Swpaul for (i = 0; i < VGE_RX_DESC_CNT; i++) { 899135048Swpaul error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 900135048Swpaul &sc->vge_ldata.vge_rx_dmamap[i]); 901135048Swpaul if (error) { 902135048Swpaul device_printf(dev, "can't create DMA map for RX\n"); 903135048Swpaul return (ENOMEM); 904135048Swpaul } 905135048Swpaul } 906135048Swpaul 907135048Swpaul return (0); 908135048Swpaul} 909135048Swpaul 910135048Swpaul/* 911135048Swpaul * Attach the interface. Allocate softc structures, do ifmedia 912135048Swpaul * setup and ethernet/BPF attach. 913135048Swpaul */ 914135048Swpaulstatic int 915135048Swpaulvge_attach(dev) 916135048Swpaul device_t dev; 917135048Swpaul{ 918135048Swpaul u_char eaddr[ETHER_ADDR_LEN]; 919135048Swpaul struct vge_softc *sc; 920135048Swpaul struct ifnet *ifp; 921135048Swpaul int unit, error = 0, rid; 922135048Swpaul 923135048Swpaul sc = device_get_softc(dev); 924135048Swpaul unit = device_get_unit(dev); 925135048Swpaul sc->vge_dev = dev; 926135048Swpaul 927135048Swpaul mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 928199543Sjhb MTX_DEF); 929199543Sjhb callout_init_mtx(&sc->vge_watchdog, &sc->vge_mtx, 0); 930199543Sjhb 931135048Swpaul /* 932135048Swpaul * Map control/status registers. 933135048Swpaul */ 934135048Swpaul pci_enable_busmaster(dev); 935135048Swpaul 936135048Swpaul rid = VGE_PCI_LOMEM; 937135048Swpaul sc->vge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 938135048Swpaul 0, ~0, 1, RF_ACTIVE); 939135048Swpaul 940135048Swpaul if (sc->vge_res == NULL) { 941135048Swpaul printf ("vge%d: couldn't map ports/memory\n", unit); 942135048Swpaul error = ENXIO; 943135048Swpaul goto fail; 944135048Swpaul } 945135048Swpaul 946135048Swpaul /* Allocate interrupt */ 947135048Swpaul rid = 0; 948135048Swpaul sc->vge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 949135048Swpaul 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE); 950135048Swpaul 951135048Swpaul if (sc->vge_irq == NULL) { 952135048Swpaul printf("vge%d: couldn't map interrupt\n", unit); 953135048Swpaul error = ENXIO; 954135048Swpaul goto fail; 955135048Swpaul } 956135048Swpaul 957135048Swpaul /* Reset the adapter. */ 958135048Swpaul vge_reset(sc); 959135048Swpaul 960135048Swpaul /* 961135048Swpaul * Get station address from the EEPROM. 962135048Swpaul */ 963135048Swpaul vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 964135048Swpaul 965135048Swpaul /* 966135048Swpaul * Allocate the parent bus DMA tag appropriate for PCI. 967135048Swpaul */ 968135048Swpaul#define VGE_NSEG_NEW 32 969135048Swpaul error = bus_dma_tag_create(NULL, /* parent */ 970135048Swpaul 1, 0, /* alignment, boundary */ 971135048Swpaul BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 972135048Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 973135048Swpaul NULL, NULL, /* filter, filterarg */ 974135048Swpaul MAXBSIZE, VGE_NSEG_NEW, /* maxsize, nsegments */ 975135048Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 976135048Swpaul BUS_DMA_ALLOCNOW, /* flags */ 977135048Swpaul NULL, NULL, /* lockfunc, lockarg */ 978135048Swpaul &sc->vge_parent_tag); 979135048Swpaul if (error) 980135048Swpaul goto fail; 981135048Swpaul 982135048Swpaul error = vge_allocmem(dev, sc); 983135048Swpaul 984135048Swpaul if (error) 985135048Swpaul goto fail; 986135048Swpaul 987147291Sbrooks ifp = sc->vge_ifp = if_alloc(IFT_ETHER); 988147291Sbrooks if (ifp == NULL) { 989198987Sjhb device_printf(dev, "can not if_alloc()\n"); 990147291Sbrooks error = ENOSPC; 991147291Sbrooks goto fail; 992147291Sbrooks } 993147291Sbrooks 994135048Swpaul /* Do MII setup */ 995135048Swpaul if (mii_phy_probe(dev, &sc->vge_miibus, 996135048Swpaul vge_ifmedia_upd, vge_ifmedia_sts)) { 997198987Sjhb device_printf(dev, "MII without any phy!\n"); 998135048Swpaul error = ENXIO; 999135048Swpaul goto fail; 1000135048Swpaul } 1001135048Swpaul 1002135048Swpaul ifp->if_softc = sc; 1003135048Swpaul if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1004135048Swpaul ifp->if_mtu = ETHERMTU; 1005135048Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1006135048Swpaul ifp->if_ioctl = vge_ioctl; 1007135048Swpaul ifp->if_capabilities = IFCAP_VLAN_MTU; 1008135048Swpaul ifp->if_start = vge_start; 1009135048Swpaul ifp->if_hwassist = VGE_CSUM_FEATURES; 1010135048Swpaul ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1011150789Sglebius ifp->if_capenable = ifp->if_capabilities; 1012135048Swpaul#ifdef DEVICE_POLLING 1013135048Swpaul ifp->if_capabilities |= IFCAP_POLLING; 1014135048Swpaul#endif 1015135048Swpaul ifp->if_init = vge_init; 1016166865Sbrueffer IFQ_SET_MAXLEN(&ifp->if_snd, VGE_IFQ_MAXLEN); 1017166865Sbrueffer ifp->if_snd.ifq_drv_maxlen = VGE_IFQ_MAXLEN; 1018166865Sbrueffer IFQ_SET_READY(&ifp->if_snd); 1019135048Swpaul 1020135048Swpaul /* 1021135048Swpaul * Call MI attach routine. 1022135048Swpaul */ 1023135048Swpaul ether_ifattach(ifp, eaddr); 1024135048Swpaul 1025135048Swpaul /* Hook interrupt last to avoid having to lock softc */ 1026135048Swpaul error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE, 1027166901Spiso NULL, vge_intr, sc, &sc->vge_intrhand); 1028135048Swpaul 1029135048Swpaul if (error) { 1030135048Swpaul printf("vge%d: couldn't set up irq\n", unit); 1031135048Swpaul ether_ifdetach(ifp); 1032135048Swpaul goto fail; 1033135048Swpaul } 1034135048Swpaul 1035135048Swpaulfail: 1036135048Swpaul if (error) 1037135048Swpaul vge_detach(dev); 1038135048Swpaul 1039135048Swpaul return (error); 1040135048Swpaul} 1041135048Swpaul 1042135048Swpaul/* 1043135048Swpaul * Shutdown hardware and free up resources. This can be called any 1044135048Swpaul * time after the mutex has been initialized. It is called in both 1045135048Swpaul * the error case in attach and the normal detach case so it needs 1046135048Swpaul * to be careful about only freeing resources that have actually been 1047135048Swpaul * allocated. 1048135048Swpaul */ 1049135048Swpaulstatic int 1050135048Swpaulvge_detach(dev) 1051135048Swpaul device_t dev; 1052135048Swpaul{ 1053135048Swpaul struct vge_softc *sc; 1054135048Swpaul struct ifnet *ifp; 1055135048Swpaul int i; 1056135048Swpaul 1057135048Swpaul sc = device_get_softc(dev); 1058135048Swpaul KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized")); 1059147256Sbrooks ifp = sc->vge_ifp; 1060135048Swpaul 1061150789Sglebius#ifdef DEVICE_POLLING 1062150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) 1063150789Sglebius ether_poll_deregister(ifp); 1064150789Sglebius#endif 1065150789Sglebius 1066135048Swpaul /* These should only be active if attach succeeded */ 1067135048Swpaul if (device_is_attached(dev)) { 1068199543Sjhb ether_ifdetach(ifp); 1069199543Sjhb VGE_LOCK(sc); 1070135048Swpaul vge_stop(sc); 1071199543Sjhb VGE_UNLOCK(sc); 1072199543Sjhb callout_drain(&sc->vge_watchdog); 1073150215Sru } 1074135048Swpaul if (sc->vge_miibus) 1075135048Swpaul device_delete_child(dev, sc->vge_miibus); 1076135048Swpaul bus_generic_detach(dev); 1077135048Swpaul 1078135048Swpaul if (sc->vge_intrhand) 1079135048Swpaul bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); 1080135048Swpaul if (sc->vge_irq) 1081135048Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vge_irq); 1082135048Swpaul if (sc->vge_res) 1083135048Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 1084135048Swpaul VGE_PCI_LOMEM, sc->vge_res); 1085150306Simp if (ifp) 1086150306Simp if_free(ifp); 1087135048Swpaul 1088135048Swpaul /* Unload and free the RX DMA ring memory and map */ 1089135048Swpaul 1090135048Swpaul if (sc->vge_ldata.vge_rx_list_tag) { 1091135048Swpaul bus_dmamap_unload(sc->vge_ldata.vge_rx_list_tag, 1092135048Swpaul sc->vge_ldata.vge_rx_list_map); 1093135048Swpaul bus_dmamem_free(sc->vge_ldata.vge_rx_list_tag, 1094135048Swpaul sc->vge_ldata.vge_rx_list, 1095135048Swpaul sc->vge_ldata.vge_rx_list_map); 1096135048Swpaul bus_dma_tag_destroy(sc->vge_ldata.vge_rx_list_tag); 1097135048Swpaul } 1098135048Swpaul 1099135048Swpaul /* Unload and free the TX DMA ring memory and map */ 1100135048Swpaul 1101135048Swpaul if (sc->vge_ldata.vge_tx_list_tag) { 1102135048Swpaul bus_dmamap_unload(sc->vge_ldata.vge_tx_list_tag, 1103135048Swpaul sc->vge_ldata.vge_tx_list_map); 1104135048Swpaul bus_dmamem_free(sc->vge_ldata.vge_tx_list_tag, 1105135048Swpaul sc->vge_ldata.vge_tx_list, 1106135048Swpaul sc->vge_ldata.vge_tx_list_map); 1107135048Swpaul bus_dma_tag_destroy(sc->vge_ldata.vge_tx_list_tag); 1108135048Swpaul } 1109135048Swpaul 1110135048Swpaul /* Destroy all the RX and TX buffer maps */ 1111135048Swpaul 1112135048Swpaul if (sc->vge_ldata.vge_mtag) { 1113135048Swpaul for (i = 0; i < VGE_TX_DESC_CNT; i++) 1114135048Swpaul bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1115135048Swpaul sc->vge_ldata.vge_tx_dmamap[i]); 1116135048Swpaul for (i = 0; i < VGE_RX_DESC_CNT; i++) 1117135048Swpaul bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1118135048Swpaul sc->vge_ldata.vge_rx_dmamap[i]); 1119135048Swpaul bus_dma_tag_destroy(sc->vge_ldata.vge_mtag); 1120135048Swpaul } 1121135048Swpaul 1122135048Swpaul if (sc->vge_parent_tag) 1123135048Swpaul bus_dma_tag_destroy(sc->vge_parent_tag); 1124135048Swpaul 1125135048Swpaul mtx_destroy(&sc->vge_mtx); 1126135048Swpaul 1127135048Swpaul return (0); 1128135048Swpaul} 1129135048Swpaul 1130135048Swpaulstatic int 1131135048Swpaulvge_newbuf(sc, idx, m) 1132135048Swpaul struct vge_softc *sc; 1133135048Swpaul int idx; 1134135048Swpaul struct mbuf *m; 1135135048Swpaul{ 1136135048Swpaul struct vge_dmaload_arg arg; 1137135048Swpaul struct mbuf *n = NULL; 1138135048Swpaul int i, error; 1139135048Swpaul 1140135048Swpaul if (m == NULL) { 1141135048Swpaul n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1142135048Swpaul if (n == NULL) 1143135048Swpaul return (ENOBUFS); 1144135048Swpaul m = n; 1145135048Swpaul } else 1146135048Swpaul m->m_data = m->m_ext.ext_buf; 1147135048Swpaul 1148135048Swpaul 1149135048Swpaul#ifdef VGE_FIXUP_RX 1150135048Swpaul /* 1151135048Swpaul * This is part of an evil trick to deal with non-x86 platforms. 1152135048Swpaul * The VIA chip requires RX buffers to be aligned on 32-bit 1153135048Swpaul * boundaries, but that will hose non-x86 machines. To get around 1154135048Swpaul * this, we leave some empty space at the start of each buffer 1155135048Swpaul * and for non-x86 hosts, we copy the buffer back two bytes 1156135048Swpaul * to achieve word alignment. This is slightly more efficient 1157135048Swpaul * than allocating a new buffer, copying the contents, and 1158135048Swpaul * discarding the old buffer. 1159135048Swpaul */ 1160135048Swpaul m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_ETHER_ALIGN; 1161135048Swpaul m_adj(m, VGE_ETHER_ALIGN); 1162135048Swpaul#else 1163135048Swpaul m->m_len = m->m_pkthdr.len = MCLBYTES; 1164135048Swpaul#endif 1165135048Swpaul 1166135048Swpaul arg.sc = sc; 1167135048Swpaul arg.vge_idx = idx; 1168135048Swpaul arg.vge_maxsegs = 1; 1169135048Swpaul arg.vge_flags = 0; 1170135048Swpaul 1171135048Swpaul error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, 1172135048Swpaul sc->vge_ldata.vge_rx_dmamap[idx], m, vge_dma_map_rx_desc, 1173135048Swpaul &arg, BUS_DMA_NOWAIT); 1174135048Swpaul if (error || arg.vge_maxsegs != 1) { 1175135048Swpaul if (n != NULL) 1176135048Swpaul m_freem(n); 1177135048Swpaul return (ENOMEM); 1178135048Swpaul } 1179135048Swpaul 1180135048Swpaul /* 1181135048Swpaul * Note: the manual fails to document the fact that for 1182135048Swpaul * proper opration, the driver needs to replentish the RX 1183135048Swpaul * DMA ring 4 descriptors at a time (rather than one at a 1184135048Swpaul * time, like most chips). We can allocate the new buffers 1185135048Swpaul * but we should not set the OWN bits until we're ready 1186135048Swpaul * to hand back 4 of them in one shot. 1187135048Swpaul */ 1188135048Swpaul 1189135048Swpaul#define VGE_RXCHUNK 4 1190135048Swpaul sc->vge_rx_consumed++; 1191135048Swpaul if (sc->vge_rx_consumed == VGE_RXCHUNK) { 1192135048Swpaul for (i = idx; i != idx - sc->vge_rx_consumed; i--) 1193135048Swpaul sc->vge_ldata.vge_rx_list[i].vge_sts |= 1194135048Swpaul htole32(VGE_RDSTS_OWN); 1195135048Swpaul sc->vge_rx_consumed = 0; 1196135048Swpaul } 1197135048Swpaul 1198135048Swpaul sc->vge_ldata.vge_rx_mbuf[idx] = m; 1199135048Swpaul 1200135048Swpaul bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1201135048Swpaul sc->vge_ldata.vge_rx_dmamap[idx], 1202135048Swpaul BUS_DMASYNC_PREREAD); 1203135048Swpaul 1204135048Swpaul return (0); 1205135048Swpaul} 1206135048Swpaul 1207135048Swpaulstatic int 1208135048Swpaulvge_tx_list_init(sc) 1209135048Swpaul struct vge_softc *sc; 1210135048Swpaul{ 1211135048Swpaul bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 1212135048Swpaul bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 1213135048Swpaul (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 1214135048Swpaul 1215135048Swpaul bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1216135048Swpaul sc->vge_ldata.vge_tx_list_map, BUS_DMASYNC_PREWRITE); 1217135048Swpaul sc->vge_ldata.vge_tx_prodidx = 0; 1218135048Swpaul sc->vge_ldata.vge_tx_considx = 0; 1219135048Swpaul sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 1220135048Swpaul 1221135048Swpaul return (0); 1222135048Swpaul} 1223135048Swpaul 1224135048Swpaulstatic int 1225135048Swpaulvge_rx_list_init(sc) 1226135048Swpaul struct vge_softc *sc; 1227135048Swpaul{ 1228135048Swpaul int i; 1229135048Swpaul 1230135048Swpaul bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 1231135048Swpaul bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 1232135048Swpaul (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 1233135048Swpaul 1234135048Swpaul sc->vge_rx_consumed = 0; 1235135048Swpaul 1236135048Swpaul for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1237135048Swpaul if (vge_newbuf(sc, i, NULL) == ENOBUFS) 1238135048Swpaul return (ENOBUFS); 1239135048Swpaul } 1240135048Swpaul 1241135048Swpaul /* Flush the RX descriptors */ 1242135048Swpaul 1243135048Swpaul bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1244135048Swpaul sc->vge_ldata.vge_rx_list_map, 1245135048Swpaul BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1246135048Swpaul 1247135048Swpaul sc->vge_ldata.vge_rx_prodidx = 0; 1248135048Swpaul sc->vge_rx_consumed = 0; 1249135048Swpaul sc->vge_head = sc->vge_tail = NULL; 1250135048Swpaul 1251135048Swpaul return (0); 1252135048Swpaul} 1253135048Swpaul 1254135048Swpaul#ifdef VGE_FIXUP_RX 1255135048Swpaulstatic __inline void 1256135048Swpaulvge_fixup_rx(m) 1257135048Swpaul struct mbuf *m; 1258135048Swpaul{ 1259135048Swpaul int i; 1260135048Swpaul uint16_t *src, *dst; 1261135048Swpaul 1262135048Swpaul src = mtod(m, uint16_t *); 1263135048Swpaul dst = src - 1; 1264135048Swpaul 1265135048Swpaul for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1266135048Swpaul *dst++ = *src++; 1267135048Swpaul 1268135048Swpaul m->m_data -= ETHER_ALIGN; 1269135048Swpaul 1270135048Swpaul return; 1271135048Swpaul} 1272135048Swpaul#endif 1273135048Swpaul 1274135048Swpaul/* 1275135048Swpaul * RX handler. We support the reception of jumbo frames that have 1276135048Swpaul * been fragmented across multiple 2K mbuf cluster buffers. 1277135048Swpaul */ 1278193096Sattiliostatic int 1279135048Swpaulvge_rxeof(sc) 1280135048Swpaul struct vge_softc *sc; 1281135048Swpaul{ 1282135048Swpaul struct mbuf *m; 1283135048Swpaul struct ifnet *ifp; 1284135048Swpaul int i, total_len; 1285135048Swpaul int lim = 0; 1286135048Swpaul struct vge_rx_desc *cur_rx; 1287135048Swpaul u_int32_t rxstat, rxctl; 1288135048Swpaul 1289135048Swpaul VGE_LOCK_ASSERT(sc); 1290147256Sbrooks ifp = sc->vge_ifp; 1291135048Swpaul i = sc->vge_ldata.vge_rx_prodidx; 1292135048Swpaul 1293135048Swpaul /* Invalidate the descriptor memory */ 1294135048Swpaul 1295135048Swpaul bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1296135048Swpaul sc->vge_ldata.vge_rx_list_map, 1297135048Swpaul BUS_DMASYNC_POSTREAD); 1298135048Swpaul 1299135048Swpaul while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 1300135048Swpaul 1301135048Swpaul#ifdef DEVICE_POLLING 1302150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) { 1303135048Swpaul if (sc->rxcycles <= 0) 1304135048Swpaul break; 1305135048Swpaul sc->rxcycles--; 1306135048Swpaul } 1307150789Sglebius#endif 1308135048Swpaul 1309135048Swpaul cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1310135048Swpaul m = sc->vge_ldata.vge_rx_mbuf[i]; 1311135048Swpaul total_len = VGE_RXBYTES(cur_rx); 1312135048Swpaul rxstat = le32toh(cur_rx->vge_sts); 1313135048Swpaul rxctl = le32toh(cur_rx->vge_ctl); 1314135048Swpaul 1315135048Swpaul /* Invalidate the RX mbuf and unload its map */ 1316135048Swpaul 1317135048Swpaul bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1318135048Swpaul sc->vge_ldata.vge_rx_dmamap[i], 1319135048Swpaul BUS_DMASYNC_POSTWRITE); 1320135048Swpaul bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1321135048Swpaul sc->vge_ldata.vge_rx_dmamap[i]); 1322135048Swpaul 1323135048Swpaul /* 1324135048Swpaul * If the 'start of frame' bit is set, this indicates 1325135048Swpaul * either the first fragment in a multi-fragment receive, 1326135048Swpaul * or an intermediate fragment. Either way, we want to 1327135048Swpaul * accumulate the buffers. 1328135048Swpaul */ 1329135048Swpaul if (rxstat & VGE_RXPKT_SOF) { 1330135048Swpaul m->m_len = MCLBYTES - VGE_ETHER_ALIGN; 1331135048Swpaul if (sc->vge_head == NULL) 1332135048Swpaul sc->vge_head = sc->vge_tail = m; 1333135048Swpaul else { 1334135048Swpaul m->m_flags &= ~M_PKTHDR; 1335135048Swpaul sc->vge_tail->m_next = m; 1336135048Swpaul sc->vge_tail = m; 1337135048Swpaul } 1338135048Swpaul vge_newbuf(sc, i, NULL); 1339135048Swpaul VGE_RX_DESC_INC(i); 1340135048Swpaul continue; 1341135048Swpaul } 1342135048Swpaul 1343135048Swpaul /* 1344135048Swpaul * Bad/error frames will have the RXOK bit cleared. 1345135048Swpaul * However, there's one error case we want to allow: 1346135048Swpaul * if a VLAN tagged frame arrives and the chip can't 1347135048Swpaul * match it against the CAM filter, it considers this 1348135048Swpaul * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1349135048Swpaul * We don't want to drop the frame though: our VLAN 1350135048Swpaul * filtering is done in software. 1351135048Swpaul */ 1352135048Swpaul if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1353135048Swpaul && !(rxstat & VGE_RDSTS_CSUMERR)) { 1354135048Swpaul ifp->if_ierrors++; 1355135048Swpaul /* 1356135048Swpaul * If this is part of a multi-fragment packet, 1357135048Swpaul * discard all the pieces. 1358135048Swpaul */ 1359135048Swpaul if (sc->vge_head != NULL) { 1360135048Swpaul m_freem(sc->vge_head); 1361135048Swpaul sc->vge_head = sc->vge_tail = NULL; 1362135048Swpaul } 1363135048Swpaul vge_newbuf(sc, i, m); 1364135048Swpaul VGE_RX_DESC_INC(i); 1365135048Swpaul continue; 1366135048Swpaul } 1367135048Swpaul 1368135048Swpaul /* 1369135048Swpaul * If allocating a replacement mbuf fails, 1370135048Swpaul * reload the current one. 1371135048Swpaul */ 1372135048Swpaul 1373135048Swpaul if (vge_newbuf(sc, i, NULL)) { 1374135048Swpaul ifp->if_ierrors++; 1375135048Swpaul if (sc->vge_head != NULL) { 1376135048Swpaul m_freem(sc->vge_head); 1377135048Swpaul sc->vge_head = sc->vge_tail = NULL; 1378135048Swpaul } 1379135048Swpaul vge_newbuf(sc, i, m); 1380135048Swpaul VGE_RX_DESC_INC(i); 1381135048Swpaul continue; 1382135048Swpaul } 1383135048Swpaul 1384135048Swpaul VGE_RX_DESC_INC(i); 1385135048Swpaul 1386135048Swpaul if (sc->vge_head != NULL) { 1387135048Swpaul m->m_len = total_len % (MCLBYTES - VGE_ETHER_ALIGN); 1388135048Swpaul /* 1389135048Swpaul * Special case: if there's 4 bytes or less 1390135048Swpaul * in this buffer, the mbuf can be discarded: 1391135048Swpaul * the last 4 bytes is the CRC, which we don't 1392135048Swpaul * care about anyway. 1393135048Swpaul */ 1394135048Swpaul if (m->m_len <= ETHER_CRC_LEN) { 1395135048Swpaul sc->vge_tail->m_len -= 1396135048Swpaul (ETHER_CRC_LEN - m->m_len); 1397135048Swpaul m_freem(m); 1398135048Swpaul } else { 1399135048Swpaul m->m_len -= ETHER_CRC_LEN; 1400135048Swpaul m->m_flags &= ~M_PKTHDR; 1401135048Swpaul sc->vge_tail->m_next = m; 1402135048Swpaul } 1403135048Swpaul m = sc->vge_head; 1404135048Swpaul sc->vge_head = sc->vge_tail = NULL; 1405135048Swpaul m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1406135048Swpaul } else 1407135048Swpaul m->m_pkthdr.len = m->m_len = 1408135048Swpaul (total_len - ETHER_CRC_LEN); 1409135048Swpaul 1410135048Swpaul#ifdef VGE_FIXUP_RX 1411135048Swpaul vge_fixup_rx(m); 1412135048Swpaul#endif 1413135048Swpaul ifp->if_ipackets++; 1414135048Swpaul m->m_pkthdr.rcvif = ifp; 1415135048Swpaul 1416135048Swpaul /* Do RX checksumming if enabled */ 1417135048Swpaul if (ifp->if_capenable & IFCAP_RXCSUM) { 1418135048Swpaul 1419135048Swpaul /* Check IP header checksum */ 1420135048Swpaul if (rxctl & VGE_RDCTL_IPPKT) 1421135048Swpaul m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1422135048Swpaul if (rxctl & VGE_RDCTL_IPCSUMOK) 1423135048Swpaul m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1424135048Swpaul 1425135048Swpaul /* Check TCP/UDP checksum */ 1426135048Swpaul if (rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT) && 1427135048Swpaul rxctl & VGE_RDCTL_PROTOCSUMOK) { 1428135048Swpaul m->m_pkthdr.csum_flags |= 1429135048Swpaul CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1430135048Swpaul m->m_pkthdr.csum_data = 0xffff; 1431135048Swpaul } 1432135048Swpaul } 1433135048Swpaul 1434153512Sglebius if (rxstat & VGE_RDSTS_VTAG) { 1435164776Sru /* 1436164776Sru * The 32-bit rxctl register is stored in little-endian. 1437164776Sru * However, the 16-bit vlan tag is stored in big-endian, 1438164776Sru * so we have to byte swap it. 1439164776Sru */ 1440162375Sandre m->m_pkthdr.ether_vtag = 1441164776Sru bswap16(rxctl & VGE_RDCTL_VLANID); 1442162375Sandre m->m_flags |= M_VLANTAG; 1443153512Sglebius } 1444135048Swpaul 1445135048Swpaul VGE_UNLOCK(sc); 1446135048Swpaul (*ifp->if_input)(ifp, m); 1447135048Swpaul VGE_LOCK(sc); 1448135048Swpaul 1449135048Swpaul lim++; 1450135048Swpaul if (lim == VGE_RX_DESC_CNT) 1451135048Swpaul break; 1452135048Swpaul 1453135048Swpaul } 1454135048Swpaul 1455135048Swpaul /* Flush the RX DMA ring */ 1456135048Swpaul 1457135048Swpaul bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1458135048Swpaul sc->vge_ldata.vge_rx_list_map, 1459135048Swpaul BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1460135048Swpaul 1461135048Swpaul sc->vge_ldata.vge_rx_prodidx = i; 1462135048Swpaul CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1463135048Swpaul 1464135048Swpaul 1465193096Sattilio return (lim); 1466135048Swpaul} 1467135048Swpaul 1468135048Swpaulstatic void 1469135048Swpaulvge_txeof(sc) 1470135048Swpaul struct vge_softc *sc; 1471135048Swpaul{ 1472135048Swpaul struct ifnet *ifp; 1473135048Swpaul u_int32_t txstat; 1474135048Swpaul int idx; 1475135048Swpaul 1476147256Sbrooks ifp = sc->vge_ifp; 1477135048Swpaul idx = sc->vge_ldata.vge_tx_considx; 1478135048Swpaul 1479135048Swpaul /* Invalidate the TX descriptor list */ 1480135048Swpaul 1481135048Swpaul bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1482135048Swpaul sc->vge_ldata.vge_tx_list_map, 1483135048Swpaul BUS_DMASYNC_POSTREAD); 1484135048Swpaul 1485135048Swpaul while (idx != sc->vge_ldata.vge_tx_prodidx) { 1486135048Swpaul 1487135048Swpaul txstat = le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1488135048Swpaul if (txstat & VGE_TDSTS_OWN) 1489135048Swpaul break; 1490135048Swpaul 1491135048Swpaul m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1492135048Swpaul sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1493135048Swpaul bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1494135048Swpaul sc->vge_ldata.vge_tx_dmamap[idx]); 1495135048Swpaul if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1496135048Swpaul ifp->if_collisions++; 1497135048Swpaul if (txstat & VGE_TDSTS_TXERR) 1498135048Swpaul ifp->if_oerrors++; 1499135048Swpaul else 1500135048Swpaul ifp->if_opackets++; 1501135048Swpaul 1502135048Swpaul sc->vge_ldata.vge_tx_free++; 1503135048Swpaul VGE_TX_DESC_INC(idx); 1504135048Swpaul } 1505135048Swpaul 1506135048Swpaul /* No changes made to the TX ring, so no flush needed */ 1507135048Swpaul 1508135048Swpaul if (idx != sc->vge_ldata.vge_tx_considx) { 1509135048Swpaul sc->vge_ldata.vge_tx_considx = idx; 1510148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1511199543Sjhb sc->vge_timer = 0; 1512135048Swpaul } 1513135048Swpaul 1514135048Swpaul /* 1515135048Swpaul * If not all descriptors have been released reaped yet, 1516135048Swpaul * reload the timer so that we will eventually get another 1517135048Swpaul * interrupt that will cause us to re-enter this routine. 1518135048Swpaul * This is done in case the transmitter has gone idle. 1519135048Swpaul */ 1520135048Swpaul if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) { 1521135048Swpaul CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1522135048Swpaul } 1523135048Swpaul 1524135048Swpaul return; 1525135048Swpaul} 1526135048Swpaul 1527135048Swpaulstatic void 1528135048Swpaulvge_tick(xsc) 1529135048Swpaul void *xsc; 1530135048Swpaul{ 1531135048Swpaul struct vge_softc *sc; 1532135048Swpaul struct ifnet *ifp; 1533135048Swpaul struct mii_data *mii; 1534135048Swpaul 1535135048Swpaul sc = xsc; 1536147256Sbrooks ifp = sc->vge_ifp; 1537199543Sjhb VGE_LOCK_ASSERT(sc); 1538135048Swpaul mii = device_get_softc(sc->vge_miibus); 1539135048Swpaul 1540135048Swpaul mii_tick(mii); 1541135048Swpaul if (sc->vge_link) { 1542135048Swpaul if (!(mii->mii_media_status & IFM_ACTIVE)) { 1543135048Swpaul sc->vge_link = 0; 1544147256Sbrooks if_link_state_change(sc->vge_ifp, 1545145521Swpaul LINK_STATE_DOWN); 1546135048Swpaul } 1547135048Swpaul } else { 1548135048Swpaul if (mii->mii_media_status & IFM_ACTIVE && 1549135048Swpaul IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1550135048Swpaul sc->vge_link = 1; 1551147256Sbrooks if_link_state_change(sc->vge_ifp, 1552145521Swpaul LINK_STATE_UP); 1553135048Swpaul if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1554199543Sjhb vge_start_locked(ifp); 1555135048Swpaul } 1556135048Swpaul } 1557135048Swpaul 1558135048Swpaul return; 1559135048Swpaul} 1560135048Swpaul 1561135048Swpaul#ifdef DEVICE_POLLING 1562193096Sattiliostatic int 1563135048Swpaulvge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1564135048Swpaul{ 1565135048Swpaul struct vge_softc *sc = ifp->if_softc; 1566193096Sattilio int rx_npkts = 0; 1567135048Swpaul 1568135048Swpaul VGE_LOCK(sc); 1569150789Sglebius if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1570135048Swpaul goto done; 1571135048Swpaul 1572135048Swpaul sc->rxcycles = count; 1573193096Sattilio rx_npkts = vge_rxeof(sc); 1574135048Swpaul vge_txeof(sc); 1575135048Swpaul 1576135048Swpaul if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1577199543Sjhb vge_start_locked(ifp); 1578135048Swpaul 1579135048Swpaul if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1580135048Swpaul u_int32_t status; 1581135048Swpaul status = CSR_READ_4(sc, VGE_ISR); 1582135048Swpaul if (status == 0xFFFFFFFF) 1583135048Swpaul goto done; 1584135048Swpaul if (status) 1585135048Swpaul CSR_WRITE_4(sc, VGE_ISR, status); 1586135048Swpaul 1587135048Swpaul /* 1588135048Swpaul * XXX check behaviour on receiver stalls. 1589135048Swpaul */ 1590135048Swpaul 1591135048Swpaul if (status & VGE_ISR_TXDMA_STALL || 1592135048Swpaul status & VGE_ISR_RXDMA_STALL) 1593199543Sjhb vge_init_locked(sc); 1594135048Swpaul 1595135048Swpaul if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1596135048Swpaul vge_rxeof(sc); 1597135048Swpaul ifp->if_ierrors++; 1598135048Swpaul CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1599135048Swpaul CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1600135048Swpaul } 1601135048Swpaul } 1602135048Swpauldone: 1603135048Swpaul VGE_UNLOCK(sc); 1604193096Sattilio return (rx_npkts); 1605135048Swpaul} 1606135048Swpaul#endif /* DEVICE_POLLING */ 1607135048Swpaul 1608135048Swpaulstatic void 1609135048Swpaulvge_intr(arg) 1610135048Swpaul void *arg; 1611135048Swpaul{ 1612135048Swpaul struct vge_softc *sc; 1613135048Swpaul struct ifnet *ifp; 1614135048Swpaul u_int32_t status; 1615135048Swpaul 1616135048Swpaul sc = arg; 1617135048Swpaul 1618135048Swpaul if (sc->suspended) { 1619135048Swpaul return; 1620135048Swpaul } 1621135048Swpaul 1622135048Swpaul VGE_LOCK(sc); 1623147256Sbrooks ifp = sc->vge_ifp; 1624135048Swpaul 1625135048Swpaul if (!(ifp->if_flags & IFF_UP)) { 1626135048Swpaul VGE_UNLOCK(sc); 1627135048Swpaul return; 1628135048Swpaul } 1629135048Swpaul 1630135048Swpaul#ifdef DEVICE_POLLING 1631150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) { 1632150789Sglebius VGE_UNLOCK(sc); 1633150789Sglebius return; 1634150789Sglebius } 1635135048Swpaul#endif 1636135048Swpaul 1637135048Swpaul /* Disable interrupts */ 1638135048Swpaul CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1639135048Swpaul 1640135048Swpaul for (;;) { 1641135048Swpaul 1642135048Swpaul status = CSR_READ_4(sc, VGE_ISR); 1643135048Swpaul /* If the card has gone away the read returns 0xffff. */ 1644135048Swpaul if (status == 0xFFFFFFFF) 1645135048Swpaul break; 1646135048Swpaul 1647135048Swpaul if (status) 1648135048Swpaul CSR_WRITE_4(sc, VGE_ISR, status); 1649135048Swpaul 1650135048Swpaul if ((status & VGE_INTRS) == 0) 1651135048Swpaul break; 1652135048Swpaul 1653135048Swpaul if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1654135048Swpaul vge_rxeof(sc); 1655135048Swpaul 1656135048Swpaul if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1657135048Swpaul vge_rxeof(sc); 1658135048Swpaul CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1659135048Swpaul CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1660135048Swpaul } 1661135048Swpaul 1662135048Swpaul if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1663135048Swpaul vge_txeof(sc); 1664135048Swpaul 1665135048Swpaul if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1666199543Sjhb vge_init_locked(sc); 1667135048Swpaul 1668135048Swpaul if (status & VGE_ISR_LINKSTS) 1669135048Swpaul vge_tick(sc); 1670135048Swpaul } 1671135048Swpaul 1672135048Swpaul /* Re-enable interrupts */ 1673135048Swpaul CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1674135048Swpaul 1675199543Sjhb if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1676199543Sjhb vge_start_locked(ifp); 1677199543Sjhb 1678135048Swpaul VGE_UNLOCK(sc); 1679135048Swpaul 1680135048Swpaul return; 1681135048Swpaul} 1682135048Swpaul 1683135048Swpaulstatic int 1684135048Swpaulvge_encap(sc, m_head, idx) 1685135048Swpaul struct vge_softc *sc; 1686135048Swpaul struct mbuf *m_head; 1687135048Swpaul int idx; 1688135048Swpaul{ 1689135048Swpaul struct mbuf *m_new = NULL; 1690135048Swpaul struct vge_dmaload_arg arg; 1691135048Swpaul bus_dmamap_t map; 1692135048Swpaul int error; 1693135048Swpaul 1694135048Swpaul if (sc->vge_ldata.vge_tx_free <= 2) 1695135048Swpaul return (EFBIG); 1696135048Swpaul 1697135048Swpaul arg.vge_flags = 0; 1698135048Swpaul 1699135048Swpaul if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1700135048Swpaul arg.vge_flags |= VGE_TDCTL_IPCSUM; 1701135048Swpaul if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1702135048Swpaul arg.vge_flags |= VGE_TDCTL_TCPCSUM; 1703135048Swpaul if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1704135048Swpaul arg.vge_flags |= VGE_TDCTL_UDPCSUM; 1705135048Swpaul 1706135048Swpaul arg.sc = sc; 1707135048Swpaul arg.vge_idx = idx; 1708135048Swpaul arg.vge_m0 = m_head; 1709135048Swpaul arg.vge_maxsegs = VGE_TX_FRAGS; 1710135048Swpaul 1711135048Swpaul map = sc->vge_ldata.vge_tx_dmamap[idx]; 1712135048Swpaul error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1713135048Swpaul m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1714135048Swpaul 1715135048Swpaul if (error && error != EFBIG) { 1716198987Sjhb if_printf(sc->vge_ifp, "can't map mbuf (error %d)\n", error); 1717135048Swpaul return (ENOBUFS); 1718135048Swpaul } 1719135048Swpaul 1720135048Swpaul /* Too many segments to map, coalesce into a single mbuf */ 1721135048Swpaul 1722135048Swpaul if (error || arg.vge_maxsegs == 0) { 1723135048Swpaul m_new = m_defrag(m_head, M_DONTWAIT); 1724135048Swpaul if (m_new == NULL) 1725135048Swpaul return (1); 1726135048Swpaul else 1727135048Swpaul m_head = m_new; 1728135048Swpaul 1729135048Swpaul arg.sc = sc; 1730135048Swpaul arg.vge_m0 = m_head; 1731135048Swpaul arg.vge_idx = idx; 1732135048Swpaul arg.vge_maxsegs = 1; 1733135048Swpaul 1734135048Swpaul error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1735135048Swpaul m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1736135048Swpaul if (error) { 1737198987Sjhb if_printf(sc->vge_ifp, "can't map mbuf (error %d)\n", 1738198987Sjhb error); 1739135048Swpaul return (EFBIG); 1740135048Swpaul } 1741135048Swpaul } 1742135048Swpaul 1743135048Swpaul sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1744135048Swpaul sc->vge_ldata.vge_tx_free--; 1745135048Swpaul 1746135048Swpaul /* 1747135048Swpaul * Set up hardware VLAN tagging. 1748135048Swpaul */ 1749135048Swpaul 1750162375Sandre if (m_head->m_flags & M_VLANTAG) 1751135048Swpaul sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1752164776Sru htole32(m_head->m_pkthdr.ether_vtag | VGE_TDCTL_VTAG); 1753135048Swpaul 1754135048Swpaul sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1755135048Swpaul 1756135048Swpaul return (0); 1757135048Swpaul} 1758135048Swpaul 1759135048Swpaul/* 1760135048Swpaul * Main transmit routine. 1761135048Swpaul */ 1762135048Swpaul 1763135048Swpaulstatic void 1764135048Swpaulvge_start(ifp) 1765135048Swpaul struct ifnet *ifp; 1766135048Swpaul{ 1767135048Swpaul struct vge_softc *sc; 1768199543Sjhb 1769199543Sjhb sc = ifp->if_softc; 1770199543Sjhb VGE_LOCK(sc); 1771199543Sjhb vge_start_locked(ifp); 1772199543Sjhb VGE_UNLOCK(sc); 1773199543Sjhb} 1774199543Sjhb 1775199543Sjhbstatic void 1776199543Sjhbvge_start_locked(ifp) 1777199543Sjhb struct ifnet *ifp; 1778199543Sjhb{ 1779199543Sjhb struct vge_softc *sc; 1780135048Swpaul struct mbuf *m_head = NULL; 1781135048Swpaul int idx, pidx = 0; 1782135048Swpaul 1783135048Swpaul sc = ifp->if_softc; 1784199543Sjhb VGE_LOCK_ASSERT(sc); 1785135048Swpaul 1786199543Sjhb if (!sc->vge_link || ifp->if_drv_flags & IFF_DRV_OACTIVE) 1787135048Swpaul return; 1788135048Swpaul 1789199543Sjhb if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1790135048Swpaul return; 1791135048Swpaul 1792135048Swpaul idx = sc->vge_ldata.vge_tx_prodidx; 1793135048Swpaul 1794135048Swpaul pidx = idx - 1; 1795135048Swpaul if (pidx < 0) 1796135048Swpaul pidx = VGE_TX_DESC_CNT - 1; 1797135048Swpaul 1798135048Swpaul 1799135048Swpaul while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1800135048Swpaul IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1801135048Swpaul if (m_head == NULL) 1802135048Swpaul break; 1803135048Swpaul 1804135048Swpaul if (vge_encap(sc, m_head, idx)) { 1805135048Swpaul IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1806148887Srwatson ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1807135048Swpaul break; 1808135048Swpaul } 1809135048Swpaul 1810135048Swpaul sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1811135048Swpaul htole16(VGE_TXDESC_Q); 1812135048Swpaul 1813135048Swpaul pidx = idx; 1814135048Swpaul VGE_TX_DESC_INC(idx); 1815135048Swpaul 1816135048Swpaul /* 1817135048Swpaul * If there's a BPF listener, bounce a copy of this frame 1818135048Swpaul * to him. 1819135048Swpaul */ 1820167190Scsjp ETHER_BPF_MTAP(ifp, m_head); 1821135048Swpaul } 1822135048Swpaul 1823199543Sjhb if (idx == sc->vge_ldata.vge_tx_prodidx) 1824135048Swpaul return; 1825135048Swpaul 1826135048Swpaul /* Flush the TX descriptors */ 1827135048Swpaul 1828135048Swpaul bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1829135048Swpaul sc->vge_ldata.vge_tx_list_map, 1830135048Swpaul BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1831135048Swpaul 1832135048Swpaul /* Issue a transmit command. */ 1833135048Swpaul CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1834135048Swpaul 1835135048Swpaul sc->vge_ldata.vge_tx_prodidx = idx; 1836135048Swpaul 1837135048Swpaul /* 1838135048Swpaul * Use the countdown timer for interrupt moderation. 1839135048Swpaul * 'TX done' interrupts are disabled. Instead, we reset the 1840135048Swpaul * countdown timer, which will begin counting until it hits 1841135048Swpaul * the value in the SSTIMER register, and then trigger an 1842135048Swpaul * interrupt. Each time we set the TIMER0_ENABLE bit, the 1843135048Swpaul * the timer count is reloaded. Only when the transmitter 1844135048Swpaul * is idle will the timer hit 0 and an interrupt fire. 1845135048Swpaul */ 1846135048Swpaul CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1847135048Swpaul 1848135048Swpaul /* 1849135048Swpaul * Set a timeout in case the chip goes out to lunch. 1850135048Swpaul */ 1851199543Sjhb sc->vge_timer = 5; 1852135048Swpaul 1853135048Swpaul return; 1854135048Swpaul} 1855135048Swpaul 1856135048Swpaulstatic void 1857135048Swpaulvge_init(xsc) 1858135048Swpaul void *xsc; 1859135048Swpaul{ 1860135048Swpaul struct vge_softc *sc = xsc; 1861199543Sjhb 1862199543Sjhb VGE_LOCK(sc); 1863199543Sjhb vge_init_locked(sc); 1864199543Sjhb VGE_UNLOCK(sc); 1865199543Sjhb} 1866199543Sjhb 1867199543Sjhbstatic void 1868199543Sjhbvge_init_locked(struct vge_softc *sc) 1869199543Sjhb{ 1870147256Sbrooks struct ifnet *ifp = sc->vge_ifp; 1871135048Swpaul struct mii_data *mii; 1872135048Swpaul int i; 1873135048Swpaul 1874199543Sjhb VGE_LOCK_ASSERT(sc); 1875135048Swpaul mii = device_get_softc(sc->vge_miibus); 1876135048Swpaul 1877135048Swpaul /* 1878135048Swpaul * Cancel pending I/O and free all RX/TX buffers. 1879135048Swpaul */ 1880135048Swpaul vge_stop(sc); 1881135048Swpaul vge_reset(sc); 1882135048Swpaul 1883135048Swpaul /* 1884135048Swpaul * Initialize the RX and TX descriptors and mbufs. 1885135048Swpaul */ 1886135048Swpaul 1887135048Swpaul vge_rx_list_init(sc); 1888135048Swpaul vge_tx_list_init(sc); 1889135048Swpaul 1890135048Swpaul /* Set our station address */ 1891135048Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 1892152315Sru CSR_WRITE_1(sc, VGE_PAR0 + i, IF_LLADDR(sc->vge_ifp)[i]); 1893135048Swpaul 1894135048Swpaul /* 1895135048Swpaul * Set receive FIFO threshold. Also allow transmission and 1896135048Swpaul * reception of VLAN tagged frames. 1897135048Swpaul */ 1898135048Swpaul CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1899135048Swpaul CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1900135048Swpaul 1901135048Swpaul /* Set DMA burst length */ 1902135048Swpaul CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1903135048Swpaul CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1904135048Swpaul 1905135048Swpaul CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1906135048Swpaul 1907135048Swpaul /* Set collision backoff algorithm */ 1908135048Swpaul CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1909135048Swpaul VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1910135048Swpaul CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1911135048Swpaul 1912135048Swpaul /* Disable LPSEL field in priority resolution */ 1913135048Swpaul CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1914135048Swpaul 1915135048Swpaul /* 1916135048Swpaul * Load the addresses of the DMA queues into the chip. 1917135048Swpaul * Note that we only use one transmit queue. 1918135048Swpaul */ 1919135048Swpaul 1920135048Swpaul CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 1921135048Swpaul VGE_ADDR_LO(sc->vge_ldata.vge_tx_list_addr)); 1922135048Swpaul CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 1923135048Swpaul 1924135048Swpaul CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 1925135048Swpaul VGE_ADDR_LO(sc->vge_ldata.vge_rx_list_addr)); 1926135048Swpaul CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 1927135048Swpaul CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 1928135048Swpaul 1929135048Swpaul /* Enable and wake up the RX descriptor queue */ 1930135048Swpaul CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1931135048Swpaul CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1932135048Swpaul 1933135048Swpaul /* Enable the TX descriptor queue */ 1934135048Swpaul CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1935135048Swpaul 1936135048Swpaul /* Set up the receive filter -- allow large frames for VLANs. */ 1937135048Swpaul CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 1938135048Swpaul 1939135048Swpaul /* If we want promiscuous mode, set the allframes bit. */ 1940135048Swpaul if (ifp->if_flags & IFF_PROMISC) { 1941135048Swpaul CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1942135048Swpaul } 1943135048Swpaul 1944135048Swpaul /* Set capture broadcast bit to capture broadcast frames. */ 1945135048Swpaul if (ifp->if_flags & IFF_BROADCAST) { 1946135048Swpaul CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1947135048Swpaul } 1948135048Swpaul 1949135048Swpaul /* Set multicast bit to capture multicast frames. */ 1950135048Swpaul if (ifp->if_flags & IFF_MULTICAST) { 1951135048Swpaul CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1952135048Swpaul } 1953135048Swpaul 1954135048Swpaul /* Init the cam filter. */ 1955135048Swpaul vge_cam_clear(sc); 1956135048Swpaul 1957135048Swpaul /* Init the multicast filter. */ 1958135048Swpaul vge_setmulti(sc); 1959135048Swpaul 1960135048Swpaul /* Enable flow control */ 1961135048Swpaul 1962135048Swpaul CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1963135048Swpaul 1964135048Swpaul /* Enable jumbo frame reception (if desired) */ 1965135048Swpaul 1966135048Swpaul /* Start the MAC. */ 1967135048Swpaul CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1968135048Swpaul CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1969135048Swpaul CSR_WRITE_1(sc, VGE_CRS0, 1970135048Swpaul VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1971135048Swpaul 1972135048Swpaul /* 1973135048Swpaul * Configure one-shot timer for microsecond 1974135048Swpaul * resulution and load it for 500 usecs. 1975135048Swpaul */ 1976135048Swpaul CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1977135048Swpaul CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1978135048Swpaul 1979135048Swpaul /* 1980135048Swpaul * Configure interrupt moderation for receive. Enable 1981135048Swpaul * the holdoff counter and load it, and set the RX 1982135048Swpaul * suppression count to the number of descriptors we 1983135048Swpaul * want to allow before triggering an interrupt. 1984135048Swpaul * The holdoff timer is in units of 20 usecs. 1985135048Swpaul */ 1986135048Swpaul 1987135048Swpaul#ifdef notyet 1988135048Swpaul CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 1989135048Swpaul /* Select the interrupt holdoff timer page. */ 1990135048Swpaul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1991135048Swpaul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 1992135048Swpaul CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 1993135048Swpaul 1994135048Swpaul /* Enable use of the holdoff timer. */ 1995135048Swpaul CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 1996135048Swpaul CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 1997135048Swpaul 1998135048Swpaul /* Select the RX suppression threshold page. */ 1999135048Swpaul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2000135048Swpaul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 2001135048Swpaul CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 2002135048Swpaul 2003135048Swpaul /* Restore the page select bits. */ 2004135048Swpaul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2005135048Swpaul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 2006135048Swpaul#endif 2007135048Swpaul 2008135048Swpaul#ifdef DEVICE_POLLING 2009135048Swpaul /* 2010135048Swpaul * Disable interrupts if we are polling. 2011135048Swpaul */ 2012150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) { 2013135048Swpaul CSR_WRITE_4(sc, VGE_IMR, 0); 2014135048Swpaul CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2015135048Swpaul } else /* otherwise ... */ 2016150789Sglebius#endif 2017135048Swpaul { 2018135048Swpaul /* 2019135048Swpaul * Enable interrupts. 2020135048Swpaul */ 2021135048Swpaul CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2022135048Swpaul CSR_WRITE_4(sc, VGE_ISR, 0); 2023135048Swpaul CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2024135048Swpaul } 2025135048Swpaul 2026135048Swpaul mii_mediachg(mii); 2027135048Swpaul 2028148887Srwatson ifp->if_drv_flags |= IFF_DRV_RUNNING; 2029148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2030199543Sjhb callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc); 2031135048Swpaul 2032135048Swpaul sc->vge_if_flags = 0; 2033135048Swpaul sc->vge_link = 0; 2034135048Swpaul 2035135048Swpaul return; 2036135048Swpaul} 2037135048Swpaul 2038135048Swpaul/* 2039135048Swpaul * Set media options. 2040135048Swpaul */ 2041135048Swpaulstatic int 2042135048Swpaulvge_ifmedia_upd(ifp) 2043135048Swpaul struct ifnet *ifp; 2044135048Swpaul{ 2045135048Swpaul struct vge_softc *sc; 2046135048Swpaul struct mii_data *mii; 2047135048Swpaul 2048135048Swpaul sc = ifp->if_softc; 2049161995Smr VGE_LOCK(sc); 2050135048Swpaul mii = device_get_softc(sc->vge_miibus); 2051135048Swpaul mii_mediachg(mii); 2052161995Smr VGE_UNLOCK(sc); 2053135048Swpaul 2054135048Swpaul return (0); 2055135048Swpaul} 2056135048Swpaul 2057135048Swpaul/* 2058135048Swpaul * Report current media status. 2059135048Swpaul */ 2060135048Swpaulstatic void 2061135048Swpaulvge_ifmedia_sts(ifp, ifmr) 2062135048Swpaul struct ifnet *ifp; 2063135048Swpaul struct ifmediareq *ifmr; 2064135048Swpaul{ 2065135048Swpaul struct vge_softc *sc; 2066135048Swpaul struct mii_data *mii; 2067135048Swpaul 2068135048Swpaul sc = ifp->if_softc; 2069135048Swpaul mii = device_get_softc(sc->vge_miibus); 2070135048Swpaul 2071199543Sjhb VGE_LOCK(sc); 2072135048Swpaul mii_pollstat(mii); 2073199543Sjhb VGE_UNLOCK(sc); 2074135048Swpaul ifmr->ifm_active = mii->mii_media_active; 2075135048Swpaul ifmr->ifm_status = mii->mii_media_status; 2076135048Swpaul 2077135048Swpaul return; 2078135048Swpaul} 2079135048Swpaul 2080135048Swpaulstatic void 2081135048Swpaulvge_miibus_statchg(dev) 2082135048Swpaul device_t dev; 2083135048Swpaul{ 2084135048Swpaul struct vge_softc *sc; 2085135048Swpaul struct mii_data *mii; 2086135048Swpaul struct ifmedia_entry *ife; 2087135048Swpaul 2088135048Swpaul sc = device_get_softc(dev); 2089135048Swpaul mii = device_get_softc(sc->vge_miibus); 2090135048Swpaul ife = mii->mii_media.ifm_cur; 2091135048Swpaul 2092135048Swpaul /* 2093135048Swpaul * If the user manually selects a media mode, we need to turn 2094135048Swpaul * on the forced MAC mode bit in the DIAGCTL register. If the 2095135048Swpaul * user happens to choose a full duplex mode, we also need to 2096135048Swpaul * set the 'force full duplex' bit. This applies only to 2097135048Swpaul * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2098135048Swpaul * mode is disabled, and in 1000baseT mode, full duplex is 2099135048Swpaul * always implied, so we turn on the forced mode bit but leave 2100135048Swpaul * the FDX bit cleared. 2101135048Swpaul */ 2102135048Swpaul 2103135048Swpaul switch (IFM_SUBTYPE(ife->ifm_media)) { 2104135048Swpaul case IFM_AUTO: 2105135048Swpaul CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2106135048Swpaul CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2107135048Swpaul break; 2108135048Swpaul case IFM_1000_T: 2109135048Swpaul CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2110135048Swpaul CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2111135048Swpaul break; 2112135048Swpaul case IFM_100_TX: 2113135048Swpaul case IFM_10_T: 2114135048Swpaul CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2115135048Swpaul if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2116135048Swpaul CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2117135048Swpaul } else { 2118135048Swpaul CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2119135048Swpaul } 2120135048Swpaul break; 2121135048Swpaul default: 2122135048Swpaul device_printf(dev, "unknown media type: %x\n", 2123135048Swpaul IFM_SUBTYPE(ife->ifm_media)); 2124135048Swpaul break; 2125135048Swpaul } 2126135048Swpaul 2127135048Swpaul return; 2128135048Swpaul} 2129135048Swpaul 2130135048Swpaulstatic int 2131135048Swpaulvge_ioctl(ifp, command, data) 2132135048Swpaul struct ifnet *ifp; 2133135048Swpaul u_long command; 2134135048Swpaul caddr_t data; 2135135048Swpaul{ 2136135048Swpaul struct vge_softc *sc = ifp->if_softc; 2137135048Swpaul struct ifreq *ifr = (struct ifreq *) data; 2138135048Swpaul struct mii_data *mii; 2139135048Swpaul int error = 0; 2140135048Swpaul 2141135048Swpaul switch (command) { 2142135048Swpaul case SIOCSIFMTU: 2143135048Swpaul if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2144135048Swpaul error = EINVAL; 2145135048Swpaul ifp->if_mtu = ifr->ifr_mtu; 2146135048Swpaul break; 2147135048Swpaul case SIOCSIFFLAGS: 2148199543Sjhb VGE_LOCK(sc); 2149135048Swpaul if (ifp->if_flags & IFF_UP) { 2150148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2151135048Swpaul ifp->if_flags & IFF_PROMISC && 2152135048Swpaul !(sc->vge_if_flags & IFF_PROMISC)) { 2153135048Swpaul CSR_SETBIT_1(sc, VGE_RXCTL, 2154135048Swpaul VGE_RXCTL_RX_PROMISC); 2155135048Swpaul vge_setmulti(sc); 2156148887Srwatson } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2157135048Swpaul !(ifp->if_flags & IFF_PROMISC) && 2158135048Swpaul sc->vge_if_flags & IFF_PROMISC) { 2159135048Swpaul CSR_CLRBIT_1(sc, VGE_RXCTL, 2160135048Swpaul VGE_RXCTL_RX_PROMISC); 2161135048Swpaul vge_setmulti(sc); 2162135048Swpaul } else 2163199543Sjhb vge_init_locked(sc); 2164135048Swpaul } else { 2165148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2166135048Swpaul vge_stop(sc); 2167135048Swpaul } 2168135048Swpaul sc->vge_if_flags = ifp->if_flags; 2169199543Sjhb VGE_UNLOCK(sc); 2170135048Swpaul break; 2171135048Swpaul case SIOCADDMULTI: 2172135048Swpaul case SIOCDELMULTI: 2173199543Sjhb VGE_LOCK(sc); 2174135048Swpaul vge_setmulti(sc); 2175199543Sjhb VGE_UNLOCK(sc); 2176135048Swpaul break; 2177135048Swpaul case SIOCGIFMEDIA: 2178135048Swpaul case SIOCSIFMEDIA: 2179135048Swpaul mii = device_get_softc(sc->vge_miibus); 2180135048Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2181135048Swpaul break; 2182135048Swpaul case SIOCSIFCAP: 2183150789Sglebius { 2184150789Sglebius int mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2185150789Sglebius#ifdef DEVICE_POLLING 2186150789Sglebius if (mask & IFCAP_POLLING) { 2187150789Sglebius if (ifr->ifr_reqcap & IFCAP_POLLING) { 2188150789Sglebius error = ether_poll_register(vge_poll, ifp); 2189150789Sglebius if (error) 2190150789Sglebius return(error); 2191150789Sglebius VGE_LOCK(sc); 2192150789Sglebius /* Disable interrupts */ 2193150789Sglebius CSR_WRITE_4(sc, VGE_IMR, 0); 2194150789Sglebius CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2195150789Sglebius ifp->if_capenable |= IFCAP_POLLING; 2196150789Sglebius VGE_UNLOCK(sc); 2197150789Sglebius } else { 2198150789Sglebius error = ether_poll_deregister(ifp); 2199150789Sglebius /* Enable interrupts. */ 2200150789Sglebius VGE_LOCK(sc); 2201150789Sglebius CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2202150789Sglebius CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2203150789Sglebius CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2204150789Sglebius ifp->if_capenable &= ~IFCAP_POLLING; 2205150789Sglebius VGE_UNLOCK(sc); 2206150789Sglebius } 2207150789Sglebius } 2208150789Sglebius#endif /* DEVICE_POLLING */ 2209199543Sjhb VGE_LOCK(sc); 2210184908Syongari if ((mask & IFCAP_TXCSUM) != 0 && 2211184908Syongari (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2212184908Syongari ifp->if_capenable ^= IFCAP_TXCSUM; 2213184908Syongari if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2214184908Syongari ifp->if_hwassist |= VGE_CSUM_FEATURES; 2215150789Sglebius else 2216184908Syongari ifp->if_hwassist &= ~VGE_CSUM_FEATURES; 2217150789Sglebius } 2218184908Syongari if ((mask & IFCAP_RXCSUM) != 0 && 2219184908Syongari (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 2220184908Syongari ifp->if_capenable ^= IFCAP_RXCSUM; 2221199543Sjhb VGE_UNLOCK(sc); 2222150789Sglebius } 2223135048Swpaul break; 2224135048Swpaul default: 2225135048Swpaul error = ether_ioctl(ifp, command, data); 2226135048Swpaul break; 2227135048Swpaul } 2228135048Swpaul 2229135048Swpaul return (error); 2230135048Swpaul} 2231135048Swpaul 2232135048Swpaulstatic void 2233199543Sjhbvge_watchdog(void *arg) 2234135048Swpaul{ 2235199543Sjhb struct vge_softc *sc; 2236199543Sjhb struct ifnet *ifp; 2237135048Swpaul 2238199543Sjhb sc = arg; 2239199543Sjhb VGE_LOCK_ASSERT(sc); 2240199543Sjhb callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc); 2241199543Sjhb if (sc->vge_timer == 0 || --sc->vge_timer > 0) 2242199543Sjhb return; 2243199543Sjhb 2244199543Sjhb ifp = sc->vge_ifp; 2245198987Sjhb if_printf(ifp, "watchdog timeout\n"); 2246135048Swpaul ifp->if_oerrors++; 2247135048Swpaul 2248135048Swpaul vge_txeof(sc); 2249135048Swpaul vge_rxeof(sc); 2250135048Swpaul 2251199543Sjhb vge_init_locked(sc); 2252135048Swpaul 2253135048Swpaul return; 2254135048Swpaul} 2255135048Swpaul 2256135048Swpaul/* 2257135048Swpaul * Stop the adapter and free any mbufs allocated to the 2258135048Swpaul * RX and TX lists. 2259135048Swpaul */ 2260135048Swpaulstatic void 2261135048Swpaulvge_stop(sc) 2262135048Swpaul struct vge_softc *sc; 2263135048Swpaul{ 2264200519Syongari int i; 2265135048Swpaul struct ifnet *ifp; 2266135048Swpaul 2267199543Sjhb VGE_LOCK_ASSERT(sc); 2268147256Sbrooks ifp = sc->vge_ifp; 2269199543Sjhb sc->vge_timer = 0; 2270199543Sjhb callout_stop(&sc->vge_watchdog); 2271135048Swpaul 2272148887Srwatson ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2273135048Swpaul 2274135048Swpaul CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2275135048Swpaul CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2276135048Swpaul CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2277135048Swpaul CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2278135048Swpaul CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2279135048Swpaul CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2280135048Swpaul 2281135048Swpaul if (sc->vge_head != NULL) { 2282135048Swpaul m_freem(sc->vge_head); 2283135048Swpaul sc->vge_head = sc->vge_tail = NULL; 2284135048Swpaul } 2285135048Swpaul 2286135048Swpaul /* Free the TX list buffers. */ 2287135048Swpaul 2288135048Swpaul for (i = 0; i < VGE_TX_DESC_CNT; i++) { 2289135048Swpaul if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 2290135048Swpaul bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2291135048Swpaul sc->vge_ldata.vge_tx_dmamap[i]); 2292135048Swpaul m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 2293135048Swpaul sc->vge_ldata.vge_tx_mbuf[i] = NULL; 2294135048Swpaul } 2295135048Swpaul } 2296135048Swpaul 2297135048Swpaul /* Free the RX list buffers. */ 2298135048Swpaul 2299135048Swpaul for (i = 0; i < VGE_RX_DESC_CNT; i++) { 2300135048Swpaul if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 2301135048Swpaul bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2302135048Swpaul sc->vge_ldata.vge_rx_dmamap[i]); 2303135048Swpaul m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 2304135048Swpaul sc->vge_ldata.vge_rx_mbuf[i] = NULL; 2305135048Swpaul } 2306135048Swpaul } 2307135048Swpaul 2308135048Swpaul return; 2309135048Swpaul} 2310135048Swpaul 2311135048Swpaul/* 2312135048Swpaul * Device suspend routine. Stop the interface and save some PCI 2313135048Swpaul * settings in case the BIOS doesn't restore them properly on 2314135048Swpaul * resume. 2315135048Swpaul */ 2316135048Swpaulstatic int 2317135048Swpaulvge_suspend(dev) 2318135048Swpaul device_t dev; 2319135048Swpaul{ 2320135048Swpaul struct vge_softc *sc; 2321135048Swpaul 2322135048Swpaul sc = device_get_softc(dev); 2323135048Swpaul 2324199543Sjhb VGE_LOCK(sc); 2325135048Swpaul vge_stop(sc); 2326135048Swpaul 2327135048Swpaul sc->suspended = 1; 2328199543Sjhb VGE_UNLOCK(sc); 2329135048Swpaul 2330135048Swpaul return (0); 2331135048Swpaul} 2332135048Swpaul 2333135048Swpaul/* 2334135048Swpaul * Device resume routine. Restore some PCI settings in case the BIOS 2335135048Swpaul * doesn't, re-enable busmastering, and restart the interface if 2336135048Swpaul * appropriate. 2337135048Swpaul */ 2338135048Swpaulstatic int 2339135048Swpaulvge_resume(dev) 2340135048Swpaul device_t dev; 2341135048Swpaul{ 2342135048Swpaul struct vge_softc *sc; 2343135048Swpaul struct ifnet *ifp; 2344135048Swpaul 2345135048Swpaul sc = device_get_softc(dev); 2346147256Sbrooks ifp = sc->vge_ifp; 2347135048Swpaul 2348135048Swpaul /* reenable busmastering */ 2349135048Swpaul pci_enable_busmaster(dev); 2350135048Swpaul pci_enable_io(dev, SYS_RES_MEMORY); 2351135048Swpaul 2352135048Swpaul /* reinitialize interface if necessary */ 2353199543Sjhb VGE_LOCK(sc); 2354135048Swpaul if (ifp->if_flags & IFF_UP) 2355199543Sjhb vge_init_locked(sc); 2356135048Swpaul 2357135048Swpaul sc->suspended = 0; 2358199543Sjhb VGE_UNLOCK(sc); 2359135048Swpaul 2360135048Swpaul return (0); 2361135048Swpaul} 2362135048Swpaul 2363135048Swpaul/* 2364135048Swpaul * Stop all chip I/O so that the kernel's probe routines don't 2365135048Swpaul * get confused by errant DMAs when rebooting. 2366135048Swpaul */ 2367173839Syongaristatic int 2368135048Swpaulvge_shutdown(dev) 2369135048Swpaul device_t dev; 2370135048Swpaul{ 2371135048Swpaul struct vge_softc *sc; 2372135048Swpaul 2373135048Swpaul sc = device_get_softc(dev); 2374135048Swpaul 2375199543Sjhb VGE_LOCK(sc); 2376135048Swpaul vge_stop(sc); 2377199543Sjhb VGE_UNLOCK(sc); 2378173839Syongari 2379173839Syongari return (0); 2380135048Swpaul} 2381