if_vge.c revision 184908
1139749Simp/*- 2135048Swpaul * Copyright (c) 2004 3135048Swpaul * Bill Paul <wpaul@windriver.com>. All rights reserved. 4135048Swpaul * 5135048Swpaul * Redistribution and use in source and binary forms, with or without 6135048Swpaul * modification, are permitted provided that the following conditions 7135048Swpaul * are met: 8135048Swpaul * 1. Redistributions of source code must retain the above copyright 9135048Swpaul * notice, this list of conditions and the following disclaimer. 10135048Swpaul * 2. Redistributions in binary form must reproduce the above copyright 11135048Swpaul * notice, this list of conditions and the following disclaimer in the 12135048Swpaul * documentation and/or other materials provided with the distribution. 13135048Swpaul * 3. All advertising materials mentioning features or use of this software 14135048Swpaul * must display the following acknowledgement: 15135048Swpaul * This product includes software developed by Bill Paul. 16135048Swpaul * 4. Neither the name of the author nor the names of any co-contributors 17135048Swpaul * may be used to endorse or promote products derived from this software 18135048Swpaul * without specific prior written permission. 19135048Swpaul * 20135048Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21135048Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22135048Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23135048Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24135048Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25135048Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26135048Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27135048Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28135048Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29135048Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30135048Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 31135048Swpaul */ 32135048Swpaul 33135048Swpaul#include <sys/cdefs.h> 34135048Swpaul__FBSDID("$FreeBSD: head/sys/dev/vge/if_vge.c 184908 2008-11-13 04:11:01Z yongari $"); 35135048Swpaul 36135048Swpaul/* 37135048Swpaul * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 38135048Swpaul * 39135048Swpaul * Written by Bill Paul <wpaul@windriver.com> 40135048Swpaul * Senior Networking Software Engineer 41135048Swpaul * Wind River Systems 42135048Swpaul */ 43135048Swpaul 44135048Swpaul/* 45135048Swpaul * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 46135048Swpaul * combines a tri-speed ethernet MAC and PHY, with the following 47135048Swpaul * features: 48135048Swpaul * 49135048Swpaul * o Jumbo frame support up to 16K 50135048Swpaul * o Transmit and receive flow control 51135048Swpaul * o IPv4 checksum offload 52135048Swpaul * o VLAN tag insertion and stripping 53135048Swpaul * o TCP large send 54135048Swpaul * o 64-bit multicast hash table filter 55135048Swpaul * o 64 entry CAM filter 56135048Swpaul * o 16K RX FIFO and 48K TX FIFO memory 57135048Swpaul * o Interrupt moderation 58135048Swpaul * 59135048Swpaul * The VT6122 supports up to four transmit DMA queues. The descriptors 60135048Swpaul * in the transmit ring can address up to 7 data fragments; frames which 61135048Swpaul * span more than 7 data buffers must be coalesced, but in general the 62135048Swpaul * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 63135048Swpaul * long. The receive descriptors address only a single buffer. 64135048Swpaul * 65135048Swpaul * There are two peculiar design issues with the VT6122. One is that 66135048Swpaul * receive data buffers must be aligned on a 32-bit boundary. This is 67135048Swpaul * not a problem where the VT6122 is used as a LOM device in x86-based 68135048Swpaul * systems, but on architectures that generate unaligned access traps, we 69135048Swpaul * have to do some copying. 70135048Swpaul * 71135048Swpaul * The other issue has to do with the way 64-bit addresses are handled. 72135048Swpaul * The DMA descriptors only allow you to specify 48 bits of addressing 73135048Swpaul * information. The remaining 16 bits are specified using one of the 74135048Swpaul * I/O registers. If you only have a 32-bit system, then this isn't 75135048Swpaul * an issue, but if you have a 64-bit system and more than 4GB of 76135048Swpaul * memory, you must have to make sure your network data buffers reside 77135048Swpaul * in the same 48-bit 'segment.' 78135048Swpaul * 79135048Swpaul * Special thanks to Ryan Fu at VIA Networking for providing documentation 80135048Swpaul * and sample NICs for testing. 81135048Swpaul */ 82135048Swpaul 83150968Sglebius#ifdef HAVE_KERNEL_OPTION_HEADERS 84150968Sglebius#include "opt_device_polling.h" 85150968Sglebius#endif 86150968Sglebius 87135048Swpaul#include <sys/param.h> 88135048Swpaul#include <sys/endian.h> 89135048Swpaul#include <sys/systm.h> 90135048Swpaul#include <sys/sockio.h> 91135048Swpaul#include <sys/mbuf.h> 92135048Swpaul#include <sys/malloc.h> 93135048Swpaul#include <sys/module.h> 94135048Swpaul#include <sys/kernel.h> 95135048Swpaul#include <sys/socket.h> 96135048Swpaul#include <sys/taskqueue.h> 97135048Swpaul 98135048Swpaul#include <net/if.h> 99135048Swpaul#include <net/if_arp.h> 100135048Swpaul#include <net/ethernet.h> 101135048Swpaul#include <net/if_dl.h> 102135048Swpaul#include <net/if_media.h> 103147256Sbrooks#include <net/if_types.h> 104135048Swpaul#include <net/if_vlan_var.h> 105135048Swpaul 106135048Swpaul#include <net/bpf.h> 107135048Swpaul 108135048Swpaul#include <machine/bus.h> 109135048Swpaul#include <machine/resource.h> 110135048Swpaul#include <sys/bus.h> 111135048Swpaul#include <sys/rman.h> 112135048Swpaul 113135048Swpaul#include <dev/mii/mii.h> 114135048Swpaul#include <dev/mii/miivar.h> 115135048Swpaul 116135048Swpaul#include <dev/pci/pcireg.h> 117135048Swpaul#include <dev/pci/pcivar.h> 118135048Swpaul 119135048SwpaulMODULE_DEPEND(vge, pci, 1, 1, 1); 120135048SwpaulMODULE_DEPEND(vge, ether, 1, 1, 1); 121135048SwpaulMODULE_DEPEND(vge, miibus, 1, 1, 1); 122135048Swpaul 123151545Simp/* "device miibus" required. See GENERIC if you get errors here. */ 124135048Swpaul#include "miibus_if.h" 125135048Swpaul 126135048Swpaul#include <dev/vge/if_vgereg.h> 127135048Swpaul#include <dev/vge/if_vgevar.h> 128135048Swpaul 129135048Swpaul#define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 130135048Swpaul 131135048Swpaul/* 132135048Swpaul * Various supported device vendors/types and their names. 133135048Swpaul */ 134135048Swpaulstatic struct vge_type vge_devs[] = { 135135048Swpaul { VIA_VENDORID, VIA_DEVICEID_61XX, 136135048Swpaul "VIA Networking Gigabit Ethernet" }, 137135048Swpaul { 0, 0, NULL } 138135048Swpaul}; 139135048Swpaul 140135048Swpaulstatic int vge_probe (device_t); 141135048Swpaulstatic int vge_attach (device_t); 142135048Swpaulstatic int vge_detach (device_t); 143135048Swpaul 144135048Swpaulstatic int vge_encap (struct vge_softc *, struct mbuf *, int); 145135048Swpaul 146135048Swpaulstatic void vge_dma_map_addr (void *, bus_dma_segment_t *, int, int); 147135048Swpaulstatic void vge_dma_map_rx_desc (void *, bus_dma_segment_t *, int, 148135048Swpaul bus_size_t, int); 149135048Swpaulstatic void vge_dma_map_tx_desc (void *, bus_dma_segment_t *, int, 150135048Swpaul bus_size_t, int); 151135048Swpaulstatic int vge_allocmem (device_t, struct vge_softc *); 152135048Swpaulstatic int vge_newbuf (struct vge_softc *, int, struct mbuf *); 153135048Swpaulstatic int vge_rx_list_init (struct vge_softc *); 154135048Swpaulstatic int vge_tx_list_init (struct vge_softc *); 155135048Swpaul#ifdef VGE_FIXUP_RX 156135048Swpaulstatic __inline void vge_fixup_rx 157135048Swpaul (struct mbuf *); 158135048Swpaul#endif 159135048Swpaulstatic void vge_rxeof (struct vge_softc *); 160135048Swpaulstatic void vge_txeof (struct vge_softc *); 161135048Swpaulstatic void vge_intr (void *); 162135048Swpaulstatic void vge_tick (void *); 163135048Swpaulstatic void vge_tx_task (void *, int); 164135048Swpaulstatic void vge_start (struct ifnet *); 165135048Swpaulstatic int vge_ioctl (struct ifnet *, u_long, caddr_t); 166135048Swpaulstatic void vge_init (void *); 167135048Swpaulstatic void vge_stop (struct vge_softc *); 168135048Swpaulstatic void vge_watchdog (struct ifnet *); 169135048Swpaulstatic int vge_suspend (device_t); 170135048Swpaulstatic int vge_resume (device_t); 171173839Syongaristatic int vge_shutdown (device_t); 172135048Swpaulstatic int vge_ifmedia_upd (struct ifnet *); 173135048Swpaulstatic void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 174135048Swpaul 175145520Swpaul#ifdef VGE_EEPROM 176135048Swpaulstatic void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 177145520Swpaul#endif 178135048Swpaulstatic void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 179135048Swpaul 180135048Swpaulstatic void vge_miipoll_start (struct vge_softc *); 181135048Swpaulstatic void vge_miipoll_stop (struct vge_softc *); 182135048Swpaulstatic int vge_miibus_readreg (device_t, int, int); 183135048Swpaulstatic int vge_miibus_writereg (device_t, int, int, int); 184135048Swpaulstatic void vge_miibus_statchg (device_t); 185135048Swpaul 186135048Swpaulstatic void vge_cam_clear (struct vge_softc *); 187135048Swpaulstatic int vge_cam_set (struct vge_softc *, uint8_t *); 188135048Swpaulstatic void vge_setmulti (struct vge_softc *); 189135048Swpaulstatic void vge_reset (struct vge_softc *); 190135048Swpaul 191135048Swpaul#define VGE_PCI_LOIO 0x10 192135048Swpaul#define VGE_PCI_LOMEM 0x14 193135048Swpaul 194135048Swpaulstatic device_method_t vge_methods[] = { 195135048Swpaul /* Device interface */ 196135048Swpaul DEVMETHOD(device_probe, vge_probe), 197135048Swpaul DEVMETHOD(device_attach, vge_attach), 198135048Swpaul DEVMETHOD(device_detach, vge_detach), 199135048Swpaul DEVMETHOD(device_suspend, vge_suspend), 200135048Swpaul DEVMETHOD(device_resume, vge_resume), 201135048Swpaul DEVMETHOD(device_shutdown, vge_shutdown), 202135048Swpaul 203135048Swpaul /* bus interface */ 204135048Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 205135048Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 206135048Swpaul 207135048Swpaul /* MII interface */ 208135048Swpaul DEVMETHOD(miibus_readreg, vge_miibus_readreg), 209135048Swpaul DEVMETHOD(miibus_writereg, vge_miibus_writereg), 210135048Swpaul DEVMETHOD(miibus_statchg, vge_miibus_statchg), 211135048Swpaul 212135048Swpaul { 0, 0 } 213135048Swpaul}; 214135048Swpaul 215135048Swpaulstatic driver_t vge_driver = { 216135048Swpaul "vge", 217135048Swpaul vge_methods, 218135048Swpaul sizeof(struct vge_softc) 219135048Swpaul}; 220135048Swpaul 221135048Swpaulstatic devclass_t vge_devclass; 222135048Swpaul 223135048SwpaulDRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0); 224135048SwpaulDRIVER_MODULE(vge, cardbus, vge_driver, vge_devclass, 0, 0); 225135048SwpaulDRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0); 226135048Swpaul 227145520Swpaul#ifdef VGE_EEPROM 228135048Swpaul/* 229135048Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 230135048Swpaul */ 231135048Swpaulstatic void 232135048Swpaulvge_eeprom_getword(sc, addr, dest) 233135048Swpaul struct vge_softc *sc; 234135048Swpaul int addr; 235135048Swpaul u_int16_t *dest; 236135048Swpaul{ 237135048Swpaul register int i; 238135048Swpaul u_int16_t word = 0; 239135048Swpaul 240135048Swpaul /* 241135048Swpaul * Enter EEPROM embedded programming mode. In order to 242135048Swpaul * access the EEPROM at all, we first have to set the 243135048Swpaul * EELOAD bit in the CHIPCFG2 register. 244135048Swpaul */ 245135048Swpaul CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 246135048Swpaul CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 247135048Swpaul 248135048Swpaul /* Select the address of the word we want to read */ 249135048Swpaul CSR_WRITE_1(sc, VGE_EEADDR, addr); 250135048Swpaul 251135048Swpaul /* Issue read command */ 252135048Swpaul CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 253135048Swpaul 254135048Swpaul /* Wait for the done bit to be set. */ 255135048Swpaul for (i = 0; i < VGE_TIMEOUT; i++) { 256135048Swpaul if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 257135048Swpaul break; 258135048Swpaul } 259135048Swpaul 260135048Swpaul if (i == VGE_TIMEOUT) { 261135048Swpaul device_printf(sc->vge_dev, "EEPROM read timed out\n"); 262135048Swpaul *dest = 0; 263135048Swpaul return; 264135048Swpaul } 265135048Swpaul 266135048Swpaul /* Read the result */ 267135048Swpaul word = CSR_READ_2(sc, VGE_EERDDAT); 268135048Swpaul 269135048Swpaul /* Turn off EEPROM access mode. */ 270135048Swpaul CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 271135048Swpaul CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 272135048Swpaul 273135048Swpaul *dest = word; 274135048Swpaul 275135048Swpaul return; 276135048Swpaul} 277145520Swpaul#endif 278135048Swpaul 279135048Swpaul/* 280135048Swpaul * Read a sequence of words from the EEPROM. 281135048Swpaul */ 282135048Swpaulstatic void 283135048Swpaulvge_read_eeprom(sc, dest, off, cnt, swap) 284135048Swpaul struct vge_softc *sc; 285135048Swpaul caddr_t dest; 286135048Swpaul int off; 287135048Swpaul int cnt; 288135048Swpaul int swap; 289135048Swpaul{ 290135048Swpaul int i; 291145520Swpaul#ifdef VGE_EEPROM 292135048Swpaul u_int16_t word = 0, *ptr; 293135048Swpaul 294135048Swpaul for (i = 0; i < cnt; i++) { 295135048Swpaul vge_eeprom_getword(sc, off + i, &word); 296135048Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 297135048Swpaul if (swap) 298135048Swpaul *ptr = ntohs(word); 299135048Swpaul else 300135048Swpaul *ptr = word; 301135048Swpaul } 302145520Swpaul#else 303145520Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 304145520Swpaul dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 305145520Swpaul#endif 306135048Swpaul} 307135048Swpaul 308135048Swpaulstatic void 309135048Swpaulvge_miipoll_stop(sc) 310135048Swpaul struct vge_softc *sc; 311135048Swpaul{ 312135048Swpaul int i; 313135048Swpaul 314135048Swpaul CSR_WRITE_1(sc, VGE_MIICMD, 0); 315135048Swpaul 316135048Swpaul for (i = 0; i < VGE_TIMEOUT; i++) { 317135048Swpaul DELAY(1); 318135048Swpaul if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 319135048Swpaul break; 320135048Swpaul } 321135048Swpaul 322135048Swpaul if (i == VGE_TIMEOUT) 323135048Swpaul device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 324135048Swpaul 325135048Swpaul return; 326135048Swpaul} 327135048Swpaul 328135048Swpaulstatic void 329135048Swpaulvge_miipoll_start(sc) 330135048Swpaul struct vge_softc *sc; 331135048Swpaul{ 332135048Swpaul int i; 333135048Swpaul 334135048Swpaul /* First, make sure we're idle. */ 335135048Swpaul 336135048Swpaul CSR_WRITE_1(sc, VGE_MIICMD, 0); 337135048Swpaul CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 338135048Swpaul 339135048Swpaul for (i = 0; i < VGE_TIMEOUT; i++) { 340135048Swpaul DELAY(1); 341135048Swpaul if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 342135048Swpaul break; 343135048Swpaul } 344135048Swpaul 345135048Swpaul if (i == VGE_TIMEOUT) { 346135048Swpaul device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 347135048Swpaul return; 348135048Swpaul } 349135048Swpaul 350135048Swpaul /* Now enable auto poll mode. */ 351135048Swpaul 352135048Swpaul CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 353135048Swpaul 354135048Swpaul /* And make sure it started. */ 355135048Swpaul 356135048Swpaul for (i = 0; i < VGE_TIMEOUT; i++) { 357135048Swpaul DELAY(1); 358135048Swpaul if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 359135048Swpaul break; 360135048Swpaul } 361135048Swpaul 362135048Swpaul if (i == VGE_TIMEOUT) 363135048Swpaul device_printf(sc->vge_dev, "failed to start MII autopoll\n"); 364135048Swpaul 365135048Swpaul return; 366135048Swpaul} 367135048Swpaul 368135048Swpaulstatic int 369135048Swpaulvge_miibus_readreg(dev, phy, reg) 370135048Swpaul device_t dev; 371135048Swpaul int phy, reg; 372135048Swpaul{ 373135048Swpaul struct vge_softc *sc; 374135048Swpaul int i; 375135048Swpaul u_int16_t rval = 0; 376135048Swpaul 377135048Swpaul sc = device_get_softc(dev); 378135048Swpaul 379135048Swpaul if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 380135048Swpaul return(0); 381135048Swpaul 382135048Swpaul VGE_LOCK(sc); 383135048Swpaul vge_miipoll_stop(sc); 384135048Swpaul 385135048Swpaul /* Specify the register we want to read. */ 386135048Swpaul CSR_WRITE_1(sc, VGE_MIIADDR, reg); 387135048Swpaul 388135048Swpaul /* Issue read command. */ 389135048Swpaul CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 390135048Swpaul 391135048Swpaul /* Wait for the read command bit to self-clear. */ 392135048Swpaul for (i = 0; i < VGE_TIMEOUT; i++) { 393135048Swpaul DELAY(1); 394135048Swpaul if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 395135048Swpaul break; 396135048Swpaul } 397135048Swpaul 398135048Swpaul if (i == VGE_TIMEOUT) 399135048Swpaul device_printf(sc->vge_dev, "MII read timed out\n"); 400135048Swpaul else 401135048Swpaul rval = CSR_READ_2(sc, VGE_MIIDATA); 402135048Swpaul 403135048Swpaul vge_miipoll_start(sc); 404135048Swpaul VGE_UNLOCK(sc); 405135048Swpaul 406135048Swpaul return (rval); 407135048Swpaul} 408135048Swpaul 409135048Swpaulstatic int 410135048Swpaulvge_miibus_writereg(dev, phy, reg, data) 411135048Swpaul device_t dev; 412135048Swpaul int phy, reg, data; 413135048Swpaul{ 414135048Swpaul struct vge_softc *sc; 415135048Swpaul int i, rval = 0; 416135048Swpaul 417135048Swpaul sc = device_get_softc(dev); 418135048Swpaul 419135048Swpaul if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 420135048Swpaul return(0); 421135048Swpaul 422135048Swpaul VGE_LOCK(sc); 423135048Swpaul vge_miipoll_stop(sc); 424135048Swpaul 425135048Swpaul /* Specify the register we want to write. */ 426135048Swpaul CSR_WRITE_1(sc, VGE_MIIADDR, reg); 427135048Swpaul 428135048Swpaul /* Specify the data we want to write. */ 429135048Swpaul CSR_WRITE_2(sc, VGE_MIIDATA, data); 430135048Swpaul 431135048Swpaul /* Issue write command. */ 432135048Swpaul CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 433135048Swpaul 434135048Swpaul /* Wait for the write command bit to self-clear. */ 435135048Swpaul for (i = 0; i < VGE_TIMEOUT; i++) { 436135048Swpaul DELAY(1); 437135048Swpaul if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 438135048Swpaul break; 439135048Swpaul } 440135048Swpaul 441135048Swpaul if (i == VGE_TIMEOUT) { 442135048Swpaul device_printf(sc->vge_dev, "MII write timed out\n"); 443135048Swpaul rval = EIO; 444135048Swpaul } 445135048Swpaul 446135048Swpaul vge_miipoll_start(sc); 447135048Swpaul VGE_UNLOCK(sc); 448135048Swpaul 449135048Swpaul return (rval); 450135048Swpaul} 451135048Swpaul 452135048Swpaulstatic void 453135048Swpaulvge_cam_clear(sc) 454135048Swpaul struct vge_softc *sc; 455135048Swpaul{ 456135048Swpaul int i; 457135048Swpaul 458135048Swpaul /* 459135048Swpaul * Turn off all the mask bits. This tells the chip 460135048Swpaul * that none of the entries in the CAM filter are valid. 461135048Swpaul * desired entries will be enabled as we fill the filter in. 462135048Swpaul */ 463135048Swpaul 464135048Swpaul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 465135048Swpaul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 466135048Swpaul CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 467135048Swpaul for (i = 0; i < 8; i++) 468135048Swpaul CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 469135048Swpaul 470135048Swpaul /* Clear the VLAN filter too. */ 471135048Swpaul 472135048Swpaul CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 473135048Swpaul for (i = 0; i < 8; i++) 474135048Swpaul CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 475135048Swpaul 476135048Swpaul CSR_WRITE_1(sc, VGE_CAMADDR, 0); 477135048Swpaul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 478135048Swpaul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 479135048Swpaul 480135048Swpaul sc->vge_camidx = 0; 481135048Swpaul 482135048Swpaul return; 483135048Swpaul} 484135048Swpaul 485135048Swpaulstatic int 486135048Swpaulvge_cam_set(sc, addr) 487135048Swpaul struct vge_softc *sc; 488135048Swpaul uint8_t *addr; 489135048Swpaul{ 490135048Swpaul int i, error = 0; 491135048Swpaul 492135048Swpaul if (sc->vge_camidx == VGE_CAM_MAXADDRS) 493135048Swpaul return(ENOSPC); 494135048Swpaul 495135048Swpaul /* Select the CAM data page. */ 496135048Swpaul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 497135048Swpaul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 498135048Swpaul 499135048Swpaul /* Set the filter entry we want to update and enable writing. */ 500135048Swpaul CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 501135048Swpaul 502135048Swpaul /* Write the address to the CAM registers */ 503135048Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 504135048Swpaul CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 505135048Swpaul 506135048Swpaul /* Issue a write command. */ 507135048Swpaul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 508135048Swpaul 509135048Swpaul /* Wake for it to clear. */ 510135048Swpaul for (i = 0; i < VGE_TIMEOUT; i++) { 511135048Swpaul DELAY(1); 512135048Swpaul if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 513135048Swpaul break; 514135048Swpaul } 515135048Swpaul 516135048Swpaul if (i == VGE_TIMEOUT) { 517135048Swpaul device_printf(sc->vge_dev, "setting CAM filter failed\n"); 518135048Swpaul error = EIO; 519135048Swpaul goto fail; 520135048Swpaul } 521135048Swpaul 522135048Swpaul /* Select the CAM mask page. */ 523135048Swpaul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 524135048Swpaul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 525135048Swpaul 526135048Swpaul /* Set the mask bit that enables this filter. */ 527135048Swpaul CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 528135048Swpaul 1<<(sc->vge_camidx & 7)); 529135048Swpaul 530135048Swpaul sc->vge_camidx++; 531135048Swpaul 532135048Swpaulfail: 533135048Swpaul /* Turn off access to CAM. */ 534135048Swpaul CSR_WRITE_1(sc, VGE_CAMADDR, 0); 535135048Swpaul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 536135048Swpaul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 537135048Swpaul 538135048Swpaul return (error); 539135048Swpaul} 540135048Swpaul 541135048Swpaul/* 542135048Swpaul * Program the multicast filter. We use the 64-entry CAM filter 543135048Swpaul * for perfect filtering. If there's more than 64 multicast addresses, 544135048Swpaul * we use the hash filter insted. 545135048Swpaul */ 546135048Swpaulstatic void 547135048Swpaulvge_setmulti(sc) 548135048Swpaul struct vge_softc *sc; 549135048Swpaul{ 550135048Swpaul struct ifnet *ifp; 551135048Swpaul int error = 0/*, h = 0*/; 552135048Swpaul struct ifmultiaddr *ifma; 553135048Swpaul u_int32_t h, hashes[2] = { 0, 0 }; 554135048Swpaul 555147256Sbrooks ifp = sc->vge_ifp; 556135048Swpaul 557135048Swpaul /* First, zot all the multicast entries. */ 558135048Swpaul vge_cam_clear(sc); 559135048Swpaul CSR_WRITE_4(sc, VGE_MAR0, 0); 560135048Swpaul CSR_WRITE_4(sc, VGE_MAR1, 0); 561135048Swpaul 562135048Swpaul /* 563135048Swpaul * If the user wants allmulti or promisc mode, enable reception 564135048Swpaul * of all multicast frames. 565135048Swpaul */ 566135048Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 567135048Swpaul CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 568135048Swpaul CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 569135048Swpaul return; 570135048Swpaul } 571135048Swpaul 572135048Swpaul /* Now program new ones */ 573148654Srwatson IF_ADDR_LOCK(ifp); 574135048Swpaul TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 575135048Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 576135048Swpaul continue; 577135048Swpaul error = vge_cam_set(sc, 578135048Swpaul LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 579135048Swpaul if (error) 580135048Swpaul break; 581135048Swpaul } 582135048Swpaul 583135048Swpaul /* If there were too many addresses, use the hash filter. */ 584135048Swpaul if (error) { 585135048Swpaul vge_cam_clear(sc); 586135048Swpaul 587135048Swpaul TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 588135048Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 589135048Swpaul continue; 590135048Swpaul h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 591135048Swpaul ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 592135048Swpaul if (h < 32) 593135048Swpaul hashes[0] |= (1 << h); 594135048Swpaul else 595135048Swpaul hashes[1] |= (1 << (h - 32)); 596135048Swpaul } 597135048Swpaul 598135048Swpaul CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 599135048Swpaul CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 600135048Swpaul } 601148654Srwatson IF_ADDR_UNLOCK(ifp); 602135048Swpaul 603135048Swpaul return; 604135048Swpaul} 605135048Swpaul 606135048Swpaulstatic void 607135048Swpaulvge_reset(sc) 608135048Swpaul struct vge_softc *sc; 609135048Swpaul{ 610135048Swpaul register int i; 611135048Swpaul 612135048Swpaul CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 613135048Swpaul 614135048Swpaul for (i = 0; i < VGE_TIMEOUT; i++) { 615135048Swpaul DELAY(5); 616135048Swpaul if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 617135048Swpaul break; 618135048Swpaul } 619135048Swpaul 620135048Swpaul if (i == VGE_TIMEOUT) { 621135048Swpaul device_printf(sc->vge_dev, "soft reset timed out"); 622135048Swpaul CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 623135048Swpaul DELAY(2000); 624135048Swpaul } 625135048Swpaul 626135048Swpaul DELAY(5000); 627135048Swpaul 628135048Swpaul CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 629135048Swpaul 630135048Swpaul for (i = 0; i < VGE_TIMEOUT; i++) { 631135048Swpaul DELAY(5); 632135048Swpaul if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 633135048Swpaul break; 634135048Swpaul } 635135048Swpaul 636135048Swpaul if (i == VGE_TIMEOUT) { 637135048Swpaul device_printf(sc->vge_dev, "EEPROM reload timed out\n"); 638135048Swpaul return; 639135048Swpaul } 640135048Swpaul 641135048Swpaul CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 642135048Swpaul 643135048Swpaul return; 644135048Swpaul} 645135048Swpaul 646135048Swpaul/* 647135048Swpaul * Probe for a VIA gigabit chip. Check the PCI vendor and device 648135048Swpaul * IDs against our list and return a device name if we find a match. 649135048Swpaul */ 650135048Swpaulstatic int 651135048Swpaulvge_probe(dev) 652135048Swpaul device_t dev; 653135048Swpaul{ 654135048Swpaul struct vge_type *t; 655135048Swpaul struct vge_softc *sc; 656135048Swpaul 657135048Swpaul t = vge_devs; 658135048Swpaul sc = device_get_softc(dev); 659135048Swpaul 660135048Swpaul while (t->vge_name != NULL) { 661135048Swpaul if ((pci_get_vendor(dev) == t->vge_vid) && 662135048Swpaul (pci_get_device(dev) == t->vge_did)) { 663135048Swpaul device_set_desc(dev, t->vge_name); 664142880Simp return (BUS_PROBE_DEFAULT); 665135048Swpaul } 666135048Swpaul t++; 667135048Swpaul } 668135048Swpaul 669135048Swpaul return (ENXIO); 670135048Swpaul} 671135048Swpaul 672135048Swpaulstatic void 673135048Swpaulvge_dma_map_rx_desc(arg, segs, nseg, mapsize, error) 674135048Swpaul void *arg; 675135048Swpaul bus_dma_segment_t *segs; 676135048Swpaul int nseg; 677135048Swpaul bus_size_t mapsize; 678135048Swpaul int error; 679135048Swpaul{ 680135048Swpaul 681135048Swpaul struct vge_dmaload_arg *ctx; 682135048Swpaul struct vge_rx_desc *d = NULL; 683135048Swpaul 684135048Swpaul if (error) 685135048Swpaul return; 686135048Swpaul 687135048Swpaul ctx = arg; 688135048Swpaul 689135048Swpaul /* Signal error to caller if there's too many segments */ 690135048Swpaul if (nseg > ctx->vge_maxsegs) { 691135048Swpaul ctx->vge_maxsegs = 0; 692135048Swpaul return; 693135048Swpaul } 694135048Swpaul 695135048Swpaul /* 696135048Swpaul * Map the segment array into descriptors. 697135048Swpaul */ 698135048Swpaul 699135048Swpaul d = &ctx->sc->vge_ldata.vge_rx_list[ctx->vge_idx]; 700135048Swpaul 701135048Swpaul /* If this descriptor is still owned by the chip, bail. */ 702135048Swpaul 703135048Swpaul if (le32toh(d->vge_sts) & VGE_RDSTS_OWN) { 704135048Swpaul device_printf(ctx->sc->vge_dev, 705135048Swpaul "tried to map busy descriptor\n"); 706135048Swpaul ctx->vge_maxsegs = 0; 707135048Swpaul return; 708135048Swpaul } 709135048Swpaul 710135048Swpaul d->vge_buflen = htole16(VGE_BUFLEN(segs[0].ds_len) | VGE_RXDESC_I); 711135048Swpaul d->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 712135048Swpaul d->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 713135048Swpaul d->vge_sts = 0; 714135048Swpaul d->vge_ctl = 0; 715135048Swpaul 716135048Swpaul ctx->vge_maxsegs = 1; 717135048Swpaul 718135048Swpaul return; 719135048Swpaul} 720135048Swpaul 721135048Swpaulstatic void 722135048Swpaulvge_dma_map_tx_desc(arg, segs, nseg, mapsize, error) 723135048Swpaul void *arg; 724135048Swpaul bus_dma_segment_t *segs; 725135048Swpaul int nseg; 726135048Swpaul bus_size_t mapsize; 727135048Swpaul int error; 728135048Swpaul{ 729135048Swpaul struct vge_dmaload_arg *ctx; 730135048Swpaul struct vge_tx_desc *d = NULL; 731135048Swpaul struct vge_tx_frag *f; 732135048Swpaul int i = 0; 733135048Swpaul 734135048Swpaul if (error) 735135048Swpaul return; 736135048Swpaul 737135048Swpaul ctx = arg; 738135048Swpaul 739135048Swpaul /* Signal error to caller if there's too many segments */ 740135048Swpaul if (nseg > ctx->vge_maxsegs) { 741135048Swpaul ctx->vge_maxsegs = 0; 742135048Swpaul return; 743135048Swpaul } 744135048Swpaul 745135048Swpaul /* Map the segment array into descriptors. */ 746135048Swpaul 747135048Swpaul d = &ctx->sc->vge_ldata.vge_tx_list[ctx->vge_idx]; 748135048Swpaul 749135048Swpaul /* If this descriptor is still owned by the chip, bail. */ 750135048Swpaul 751135048Swpaul if (le32toh(d->vge_sts) & VGE_TDSTS_OWN) { 752135048Swpaul ctx->vge_maxsegs = 0; 753135048Swpaul return; 754135048Swpaul } 755135048Swpaul 756135048Swpaul for (i = 0; i < nseg; i++) { 757135048Swpaul f = &d->vge_frag[i]; 758135048Swpaul f->vge_buflen = htole16(VGE_BUFLEN(segs[i].ds_len)); 759135048Swpaul f->vge_addrlo = htole32(VGE_ADDR_LO(segs[i].ds_addr)); 760135048Swpaul f->vge_addrhi = htole16(VGE_ADDR_HI(segs[i].ds_addr) & 0xFFFF); 761135048Swpaul } 762135048Swpaul 763135048Swpaul /* Argh. This chip does not autopad short frames */ 764135048Swpaul 765135048Swpaul if (ctx->vge_m0->m_pkthdr.len < VGE_MIN_FRAMELEN) { 766135048Swpaul f = &d->vge_frag[i]; 767135048Swpaul f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 768135048Swpaul ctx->vge_m0->m_pkthdr.len)); 769135048Swpaul f->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 770135048Swpaul f->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 771135048Swpaul ctx->vge_m0->m_pkthdr.len = VGE_MIN_FRAMELEN; 772135048Swpaul i++; 773135048Swpaul } 774135048Swpaul 775135048Swpaul /* 776135048Swpaul * When telling the chip how many segments there are, we 777135048Swpaul * must use nsegs + 1 instead of just nsegs. Darned if I 778135048Swpaul * know why. 779135048Swpaul */ 780135048Swpaul i++; 781135048Swpaul 782135048Swpaul d->vge_sts = ctx->vge_m0->m_pkthdr.len << 16; 783135048Swpaul d->vge_ctl = ctx->vge_flags|(i << 28)|VGE_TD_LS_NORM; 784135048Swpaul 785135048Swpaul if (ctx->vge_m0->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 786135048Swpaul d->vge_ctl |= VGE_TDCTL_JUMBO; 787135048Swpaul 788135048Swpaul ctx->vge_maxsegs = nseg; 789135048Swpaul 790135048Swpaul return; 791135048Swpaul} 792135048Swpaul 793135048Swpaul/* 794135048Swpaul * Map a single buffer address. 795135048Swpaul */ 796135048Swpaul 797135048Swpaulstatic void 798135048Swpaulvge_dma_map_addr(arg, segs, nseg, error) 799135048Swpaul void *arg; 800135048Swpaul bus_dma_segment_t *segs; 801135048Swpaul int nseg; 802135048Swpaul int error; 803135048Swpaul{ 804135048Swpaul bus_addr_t *addr; 805135048Swpaul 806135048Swpaul if (error) 807135048Swpaul return; 808135048Swpaul 809135048Swpaul KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 810135048Swpaul addr = arg; 811135048Swpaul *addr = segs->ds_addr; 812135048Swpaul 813135048Swpaul return; 814135048Swpaul} 815135048Swpaul 816135048Swpaulstatic int 817135048Swpaulvge_allocmem(dev, sc) 818135048Swpaul device_t dev; 819135048Swpaul struct vge_softc *sc; 820135048Swpaul{ 821135048Swpaul int error; 822135048Swpaul int nseg; 823135048Swpaul int i; 824135048Swpaul 825135048Swpaul /* 826135048Swpaul * Allocate map for RX mbufs. 827135048Swpaul */ 828135048Swpaul nseg = 32; 829135048Swpaul error = bus_dma_tag_create(sc->vge_parent_tag, ETHER_ALIGN, 0, 830135048Swpaul BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 831135048Swpaul NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 832135048Swpaul NULL, NULL, &sc->vge_ldata.vge_mtag); 833135048Swpaul if (error) { 834135048Swpaul device_printf(dev, "could not allocate dma tag\n"); 835135048Swpaul return (ENOMEM); 836135048Swpaul } 837135048Swpaul 838135048Swpaul /* 839135048Swpaul * Allocate map for TX descriptor list. 840135048Swpaul */ 841135048Swpaul error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 842135048Swpaul 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 843135048Swpaul NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 844135048Swpaul NULL, NULL, &sc->vge_ldata.vge_tx_list_tag); 845135048Swpaul if (error) { 846135048Swpaul device_printf(dev, "could not allocate dma tag\n"); 847135048Swpaul return (ENOMEM); 848135048Swpaul } 849135048Swpaul 850135048Swpaul /* Allocate DMA'able memory for the TX ring */ 851135048Swpaul 852135048Swpaul error = bus_dmamem_alloc(sc->vge_ldata.vge_tx_list_tag, 853135048Swpaul (void **)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 854135048Swpaul &sc->vge_ldata.vge_tx_list_map); 855135048Swpaul if (error) 856135048Swpaul return (ENOMEM); 857135048Swpaul 858135048Swpaul /* Load the map for the TX ring. */ 859135048Swpaul 860135048Swpaul error = bus_dmamap_load(sc->vge_ldata.vge_tx_list_tag, 861135048Swpaul sc->vge_ldata.vge_tx_list_map, sc->vge_ldata.vge_tx_list, 862135048Swpaul VGE_TX_LIST_SZ, vge_dma_map_addr, 863135048Swpaul &sc->vge_ldata.vge_tx_list_addr, BUS_DMA_NOWAIT); 864135048Swpaul 865135048Swpaul /* Create DMA maps for TX buffers */ 866135048Swpaul 867135048Swpaul for (i = 0; i < VGE_TX_DESC_CNT; i++) { 868135048Swpaul error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 869135048Swpaul &sc->vge_ldata.vge_tx_dmamap[i]); 870135048Swpaul if (error) { 871135048Swpaul device_printf(dev, "can't create DMA map for TX\n"); 872135048Swpaul return (ENOMEM); 873135048Swpaul } 874135048Swpaul } 875135048Swpaul 876135048Swpaul /* 877135048Swpaul * Allocate map for RX descriptor list. 878135048Swpaul */ 879135048Swpaul error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 880135048Swpaul 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 881135048Swpaul NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 882135048Swpaul NULL, NULL, &sc->vge_ldata.vge_rx_list_tag); 883135048Swpaul if (error) { 884135048Swpaul device_printf(dev, "could not allocate dma tag\n"); 885135048Swpaul return (ENOMEM); 886135048Swpaul } 887135048Swpaul 888135048Swpaul /* Allocate DMA'able memory for the RX ring */ 889135048Swpaul 890135048Swpaul error = bus_dmamem_alloc(sc->vge_ldata.vge_rx_list_tag, 891135048Swpaul (void **)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 892135048Swpaul &sc->vge_ldata.vge_rx_list_map); 893135048Swpaul if (error) 894135048Swpaul return (ENOMEM); 895135048Swpaul 896135048Swpaul /* Load the map for the RX ring. */ 897135048Swpaul 898135048Swpaul error = bus_dmamap_load(sc->vge_ldata.vge_rx_list_tag, 899135048Swpaul sc->vge_ldata.vge_rx_list_map, sc->vge_ldata.vge_rx_list, 900135048Swpaul VGE_TX_LIST_SZ, vge_dma_map_addr, 901135048Swpaul &sc->vge_ldata.vge_rx_list_addr, BUS_DMA_NOWAIT); 902135048Swpaul 903135048Swpaul /* Create DMA maps for RX buffers */ 904135048Swpaul 905135048Swpaul for (i = 0; i < VGE_RX_DESC_CNT; i++) { 906135048Swpaul error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 907135048Swpaul &sc->vge_ldata.vge_rx_dmamap[i]); 908135048Swpaul if (error) { 909135048Swpaul device_printf(dev, "can't create DMA map for RX\n"); 910135048Swpaul return (ENOMEM); 911135048Swpaul } 912135048Swpaul } 913135048Swpaul 914135048Swpaul return (0); 915135048Swpaul} 916135048Swpaul 917135048Swpaul/* 918135048Swpaul * Attach the interface. Allocate softc structures, do ifmedia 919135048Swpaul * setup and ethernet/BPF attach. 920135048Swpaul */ 921135048Swpaulstatic int 922135048Swpaulvge_attach(dev) 923135048Swpaul device_t dev; 924135048Swpaul{ 925135048Swpaul u_char eaddr[ETHER_ADDR_LEN]; 926135048Swpaul struct vge_softc *sc; 927135048Swpaul struct ifnet *ifp; 928135048Swpaul int unit, error = 0, rid; 929135048Swpaul 930135048Swpaul sc = device_get_softc(dev); 931135048Swpaul unit = device_get_unit(dev); 932135048Swpaul sc->vge_dev = dev; 933135048Swpaul 934135048Swpaul mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 935135048Swpaul MTX_DEF | MTX_RECURSE); 936135048Swpaul /* 937135048Swpaul * Map control/status registers. 938135048Swpaul */ 939135048Swpaul pci_enable_busmaster(dev); 940135048Swpaul 941135048Swpaul rid = VGE_PCI_LOMEM; 942135048Swpaul sc->vge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 943135048Swpaul 0, ~0, 1, RF_ACTIVE); 944135048Swpaul 945135048Swpaul if (sc->vge_res == NULL) { 946135048Swpaul printf ("vge%d: couldn't map ports/memory\n", unit); 947135048Swpaul error = ENXIO; 948135048Swpaul goto fail; 949135048Swpaul } 950135048Swpaul 951135048Swpaul sc->vge_btag = rman_get_bustag(sc->vge_res); 952135048Swpaul sc->vge_bhandle = rman_get_bushandle(sc->vge_res); 953135048Swpaul 954135048Swpaul /* Allocate interrupt */ 955135048Swpaul rid = 0; 956135048Swpaul sc->vge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 957135048Swpaul 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE); 958135048Swpaul 959135048Swpaul if (sc->vge_irq == NULL) { 960135048Swpaul printf("vge%d: couldn't map interrupt\n", unit); 961135048Swpaul error = ENXIO; 962135048Swpaul goto fail; 963135048Swpaul } 964135048Swpaul 965135048Swpaul /* Reset the adapter. */ 966135048Swpaul vge_reset(sc); 967135048Swpaul 968135048Swpaul /* 969135048Swpaul * Get station address from the EEPROM. 970135048Swpaul */ 971135048Swpaul vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 972135048Swpaul 973135048Swpaul sc->vge_unit = unit; 974135048Swpaul 975135048Swpaul /* 976135048Swpaul * Allocate the parent bus DMA tag appropriate for PCI. 977135048Swpaul */ 978135048Swpaul#define VGE_NSEG_NEW 32 979135048Swpaul error = bus_dma_tag_create(NULL, /* parent */ 980135048Swpaul 1, 0, /* alignment, boundary */ 981135048Swpaul BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 982135048Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 983135048Swpaul NULL, NULL, /* filter, filterarg */ 984135048Swpaul MAXBSIZE, VGE_NSEG_NEW, /* maxsize, nsegments */ 985135048Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 986135048Swpaul BUS_DMA_ALLOCNOW, /* flags */ 987135048Swpaul NULL, NULL, /* lockfunc, lockarg */ 988135048Swpaul &sc->vge_parent_tag); 989135048Swpaul if (error) 990135048Swpaul goto fail; 991135048Swpaul 992135048Swpaul error = vge_allocmem(dev, sc); 993135048Swpaul 994135048Swpaul if (error) 995135048Swpaul goto fail; 996135048Swpaul 997147291Sbrooks ifp = sc->vge_ifp = if_alloc(IFT_ETHER); 998147291Sbrooks if (ifp == NULL) { 999147291Sbrooks printf("vge%d: can not if_alloc()\n", sc->vge_unit); 1000147291Sbrooks error = ENOSPC; 1001147291Sbrooks goto fail; 1002147291Sbrooks } 1003147291Sbrooks 1004135048Swpaul /* Do MII setup */ 1005135048Swpaul if (mii_phy_probe(dev, &sc->vge_miibus, 1006135048Swpaul vge_ifmedia_upd, vge_ifmedia_sts)) { 1007135048Swpaul printf("vge%d: MII without any phy!\n", sc->vge_unit); 1008135048Swpaul error = ENXIO; 1009135048Swpaul goto fail; 1010135048Swpaul } 1011135048Swpaul 1012135048Swpaul ifp->if_softc = sc; 1013135048Swpaul if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1014135048Swpaul ifp->if_mtu = ETHERMTU; 1015135048Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1016135048Swpaul ifp->if_ioctl = vge_ioctl; 1017135048Swpaul ifp->if_capabilities = IFCAP_VLAN_MTU; 1018135048Swpaul ifp->if_start = vge_start; 1019135048Swpaul ifp->if_hwassist = VGE_CSUM_FEATURES; 1020135048Swpaul ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1021150789Sglebius ifp->if_capenable = ifp->if_capabilities; 1022135048Swpaul#ifdef DEVICE_POLLING 1023135048Swpaul ifp->if_capabilities |= IFCAP_POLLING; 1024135048Swpaul#endif 1025135048Swpaul ifp->if_watchdog = vge_watchdog; 1026135048Swpaul ifp->if_init = vge_init; 1027166865Sbrueffer IFQ_SET_MAXLEN(&ifp->if_snd, VGE_IFQ_MAXLEN); 1028166865Sbrueffer ifp->if_snd.ifq_drv_maxlen = VGE_IFQ_MAXLEN; 1029166865Sbrueffer IFQ_SET_READY(&ifp->if_snd); 1030135048Swpaul 1031135048Swpaul TASK_INIT(&sc->vge_txtask, 0, vge_tx_task, ifp); 1032135048Swpaul 1033135048Swpaul /* 1034135048Swpaul * Call MI attach routine. 1035135048Swpaul */ 1036135048Swpaul ether_ifattach(ifp, eaddr); 1037135048Swpaul 1038135048Swpaul /* Hook interrupt last to avoid having to lock softc */ 1039135048Swpaul error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE, 1040166901Spiso NULL, vge_intr, sc, &sc->vge_intrhand); 1041135048Swpaul 1042135048Swpaul if (error) { 1043135048Swpaul printf("vge%d: couldn't set up irq\n", unit); 1044135048Swpaul ether_ifdetach(ifp); 1045135048Swpaul goto fail; 1046135048Swpaul } 1047135048Swpaul 1048135048Swpaulfail: 1049135048Swpaul if (error) 1050135048Swpaul vge_detach(dev); 1051135048Swpaul 1052135048Swpaul return (error); 1053135048Swpaul} 1054135048Swpaul 1055135048Swpaul/* 1056135048Swpaul * Shutdown hardware and free up resources. This can be called any 1057135048Swpaul * time after the mutex has been initialized. It is called in both 1058135048Swpaul * the error case in attach and the normal detach case so it needs 1059135048Swpaul * to be careful about only freeing resources that have actually been 1060135048Swpaul * allocated. 1061135048Swpaul */ 1062135048Swpaulstatic int 1063135048Swpaulvge_detach(dev) 1064135048Swpaul device_t dev; 1065135048Swpaul{ 1066135048Swpaul struct vge_softc *sc; 1067135048Swpaul struct ifnet *ifp; 1068135048Swpaul int i; 1069135048Swpaul 1070135048Swpaul sc = device_get_softc(dev); 1071135048Swpaul KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized")); 1072147256Sbrooks ifp = sc->vge_ifp; 1073135048Swpaul 1074150789Sglebius#ifdef DEVICE_POLLING 1075150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) 1076150789Sglebius ether_poll_deregister(ifp); 1077150789Sglebius#endif 1078150789Sglebius 1079135048Swpaul /* These should only be active if attach succeeded */ 1080135048Swpaul if (device_is_attached(dev)) { 1081135048Swpaul vge_stop(sc); 1082135048Swpaul /* 1083135048Swpaul * Force off the IFF_UP flag here, in case someone 1084135048Swpaul * still had a BPF descriptor attached to this 1085135048Swpaul * interface. If they do, ether_ifattach() will cause 1086135048Swpaul * the BPF code to try and clear the promisc mode 1087135048Swpaul * flag, which will bubble down to vge_ioctl(), 1088135048Swpaul * which will try to call vge_init() again. This will 1089135048Swpaul * turn the NIC back on and restart the MII ticker, 1090135048Swpaul * which will panic the system when the kernel tries 1091135048Swpaul * to invoke the vge_tick() function that isn't there 1092135048Swpaul * anymore. 1093135048Swpaul */ 1094135048Swpaul ifp->if_flags &= ~IFF_UP; 1095135048Swpaul ether_ifdetach(ifp); 1096150215Sru } 1097135048Swpaul if (sc->vge_miibus) 1098135048Swpaul device_delete_child(dev, sc->vge_miibus); 1099135048Swpaul bus_generic_detach(dev); 1100135048Swpaul 1101135048Swpaul if (sc->vge_intrhand) 1102135048Swpaul bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); 1103135048Swpaul if (sc->vge_irq) 1104135048Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vge_irq); 1105135048Swpaul if (sc->vge_res) 1106135048Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 1107135048Swpaul VGE_PCI_LOMEM, sc->vge_res); 1108150306Simp if (ifp) 1109150306Simp if_free(ifp); 1110135048Swpaul 1111135048Swpaul /* Unload and free the RX DMA ring memory and map */ 1112135048Swpaul 1113135048Swpaul if (sc->vge_ldata.vge_rx_list_tag) { 1114135048Swpaul bus_dmamap_unload(sc->vge_ldata.vge_rx_list_tag, 1115135048Swpaul sc->vge_ldata.vge_rx_list_map); 1116135048Swpaul bus_dmamem_free(sc->vge_ldata.vge_rx_list_tag, 1117135048Swpaul sc->vge_ldata.vge_rx_list, 1118135048Swpaul sc->vge_ldata.vge_rx_list_map); 1119135048Swpaul bus_dma_tag_destroy(sc->vge_ldata.vge_rx_list_tag); 1120135048Swpaul } 1121135048Swpaul 1122135048Swpaul /* Unload and free the TX DMA ring memory and map */ 1123135048Swpaul 1124135048Swpaul if (sc->vge_ldata.vge_tx_list_tag) { 1125135048Swpaul bus_dmamap_unload(sc->vge_ldata.vge_tx_list_tag, 1126135048Swpaul sc->vge_ldata.vge_tx_list_map); 1127135048Swpaul bus_dmamem_free(sc->vge_ldata.vge_tx_list_tag, 1128135048Swpaul sc->vge_ldata.vge_tx_list, 1129135048Swpaul sc->vge_ldata.vge_tx_list_map); 1130135048Swpaul bus_dma_tag_destroy(sc->vge_ldata.vge_tx_list_tag); 1131135048Swpaul } 1132135048Swpaul 1133135048Swpaul /* Destroy all the RX and TX buffer maps */ 1134135048Swpaul 1135135048Swpaul if (sc->vge_ldata.vge_mtag) { 1136135048Swpaul for (i = 0; i < VGE_TX_DESC_CNT; i++) 1137135048Swpaul bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1138135048Swpaul sc->vge_ldata.vge_tx_dmamap[i]); 1139135048Swpaul for (i = 0; i < VGE_RX_DESC_CNT; i++) 1140135048Swpaul bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1141135048Swpaul sc->vge_ldata.vge_rx_dmamap[i]); 1142135048Swpaul bus_dma_tag_destroy(sc->vge_ldata.vge_mtag); 1143135048Swpaul } 1144135048Swpaul 1145135048Swpaul if (sc->vge_parent_tag) 1146135048Swpaul bus_dma_tag_destroy(sc->vge_parent_tag); 1147135048Swpaul 1148135048Swpaul mtx_destroy(&sc->vge_mtx); 1149135048Swpaul 1150135048Swpaul return (0); 1151135048Swpaul} 1152135048Swpaul 1153135048Swpaulstatic int 1154135048Swpaulvge_newbuf(sc, idx, m) 1155135048Swpaul struct vge_softc *sc; 1156135048Swpaul int idx; 1157135048Swpaul struct mbuf *m; 1158135048Swpaul{ 1159135048Swpaul struct vge_dmaload_arg arg; 1160135048Swpaul struct mbuf *n = NULL; 1161135048Swpaul int i, error; 1162135048Swpaul 1163135048Swpaul if (m == NULL) { 1164135048Swpaul n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1165135048Swpaul if (n == NULL) 1166135048Swpaul return (ENOBUFS); 1167135048Swpaul m = n; 1168135048Swpaul } else 1169135048Swpaul m->m_data = m->m_ext.ext_buf; 1170135048Swpaul 1171135048Swpaul 1172135048Swpaul#ifdef VGE_FIXUP_RX 1173135048Swpaul /* 1174135048Swpaul * This is part of an evil trick to deal with non-x86 platforms. 1175135048Swpaul * The VIA chip requires RX buffers to be aligned on 32-bit 1176135048Swpaul * boundaries, but that will hose non-x86 machines. To get around 1177135048Swpaul * this, we leave some empty space at the start of each buffer 1178135048Swpaul * and for non-x86 hosts, we copy the buffer back two bytes 1179135048Swpaul * to achieve word alignment. This is slightly more efficient 1180135048Swpaul * than allocating a new buffer, copying the contents, and 1181135048Swpaul * discarding the old buffer. 1182135048Swpaul */ 1183135048Swpaul m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_ETHER_ALIGN; 1184135048Swpaul m_adj(m, VGE_ETHER_ALIGN); 1185135048Swpaul#else 1186135048Swpaul m->m_len = m->m_pkthdr.len = MCLBYTES; 1187135048Swpaul#endif 1188135048Swpaul 1189135048Swpaul arg.sc = sc; 1190135048Swpaul arg.vge_idx = idx; 1191135048Swpaul arg.vge_maxsegs = 1; 1192135048Swpaul arg.vge_flags = 0; 1193135048Swpaul 1194135048Swpaul error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, 1195135048Swpaul sc->vge_ldata.vge_rx_dmamap[idx], m, vge_dma_map_rx_desc, 1196135048Swpaul &arg, BUS_DMA_NOWAIT); 1197135048Swpaul if (error || arg.vge_maxsegs != 1) { 1198135048Swpaul if (n != NULL) 1199135048Swpaul m_freem(n); 1200135048Swpaul return (ENOMEM); 1201135048Swpaul } 1202135048Swpaul 1203135048Swpaul /* 1204135048Swpaul * Note: the manual fails to document the fact that for 1205135048Swpaul * proper opration, the driver needs to replentish the RX 1206135048Swpaul * DMA ring 4 descriptors at a time (rather than one at a 1207135048Swpaul * time, like most chips). We can allocate the new buffers 1208135048Swpaul * but we should not set the OWN bits until we're ready 1209135048Swpaul * to hand back 4 of them in one shot. 1210135048Swpaul */ 1211135048Swpaul 1212135048Swpaul#define VGE_RXCHUNK 4 1213135048Swpaul sc->vge_rx_consumed++; 1214135048Swpaul if (sc->vge_rx_consumed == VGE_RXCHUNK) { 1215135048Swpaul for (i = idx; i != idx - sc->vge_rx_consumed; i--) 1216135048Swpaul sc->vge_ldata.vge_rx_list[i].vge_sts |= 1217135048Swpaul htole32(VGE_RDSTS_OWN); 1218135048Swpaul sc->vge_rx_consumed = 0; 1219135048Swpaul } 1220135048Swpaul 1221135048Swpaul sc->vge_ldata.vge_rx_mbuf[idx] = m; 1222135048Swpaul 1223135048Swpaul bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1224135048Swpaul sc->vge_ldata.vge_rx_dmamap[idx], 1225135048Swpaul BUS_DMASYNC_PREREAD); 1226135048Swpaul 1227135048Swpaul return (0); 1228135048Swpaul} 1229135048Swpaul 1230135048Swpaulstatic int 1231135048Swpaulvge_tx_list_init(sc) 1232135048Swpaul struct vge_softc *sc; 1233135048Swpaul{ 1234135048Swpaul bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 1235135048Swpaul bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 1236135048Swpaul (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 1237135048Swpaul 1238135048Swpaul bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1239135048Swpaul sc->vge_ldata.vge_tx_list_map, BUS_DMASYNC_PREWRITE); 1240135048Swpaul sc->vge_ldata.vge_tx_prodidx = 0; 1241135048Swpaul sc->vge_ldata.vge_tx_considx = 0; 1242135048Swpaul sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 1243135048Swpaul 1244135048Swpaul return (0); 1245135048Swpaul} 1246135048Swpaul 1247135048Swpaulstatic int 1248135048Swpaulvge_rx_list_init(sc) 1249135048Swpaul struct vge_softc *sc; 1250135048Swpaul{ 1251135048Swpaul int i; 1252135048Swpaul 1253135048Swpaul bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 1254135048Swpaul bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 1255135048Swpaul (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 1256135048Swpaul 1257135048Swpaul sc->vge_rx_consumed = 0; 1258135048Swpaul 1259135048Swpaul for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1260135048Swpaul if (vge_newbuf(sc, i, NULL) == ENOBUFS) 1261135048Swpaul return (ENOBUFS); 1262135048Swpaul } 1263135048Swpaul 1264135048Swpaul /* Flush the RX descriptors */ 1265135048Swpaul 1266135048Swpaul bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1267135048Swpaul sc->vge_ldata.vge_rx_list_map, 1268135048Swpaul BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1269135048Swpaul 1270135048Swpaul sc->vge_ldata.vge_rx_prodidx = 0; 1271135048Swpaul sc->vge_rx_consumed = 0; 1272135048Swpaul sc->vge_head = sc->vge_tail = NULL; 1273135048Swpaul 1274135048Swpaul return (0); 1275135048Swpaul} 1276135048Swpaul 1277135048Swpaul#ifdef VGE_FIXUP_RX 1278135048Swpaulstatic __inline void 1279135048Swpaulvge_fixup_rx(m) 1280135048Swpaul struct mbuf *m; 1281135048Swpaul{ 1282135048Swpaul int i; 1283135048Swpaul uint16_t *src, *dst; 1284135048Swpaul 1285135048Swpaul src = mtod(m, uint16_t *); 1286135048Swpaul dst = src - 1; 1287135048Swpaul 1288135048Swpaul for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1289135048Swpaul *dst++ = *src++; 1290135048Swpaul 1291135048Swpaul m->m_data -= ETHER_ALIGN; 1292135048Swpaul 1293135048Swpaul return; 1294135048Swpaul} 1295135048Swpaul#endif 1296135048Swpaul 1297135048Swpaul/* 1298135048Swpaul * RX handler. We support the reception of jumbo frames that have 1299135048Swpaul * been fragmented across multiple 2K mbuf cluster buffers. 1300135048Swpaul */ 1301135048Swpaulstatic void 1302135048Swpaulvge_rxeof(sc) 1303135048Swpaul struct vge_softc *sc; 1304135048Swpaul{ 1305135048Swpaul struct mbuf *m; 1306135048Swpaul struct ifnet *ifp; 1307135048Swpaul int i, total_len; 1308135048Swpaul int lim = 0; 1309135048Swpaul struct vge_rx_desc *cur_rx; 1310135048Swpaul u_int32_t rxstat, rxctl; 1311135048Swpaul 1312135048Swpaul VGE_LOCK_ASSERT(sc); 1313147256Sbrooks ifp = sc->vge_ifp; 1314135048Swpaul i = sc->vge_ldata.vge_rx_prodidx; 1315135048Swpaul 1316135048Swpaul /* Invalidate the descriptor memory */ 1317135048Swpaul 1318135048Swpaul bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1319135048Swpaul sc->vge_ldata.vge_rx_list_map, 1320135048Swpaul BUS_DMASYNC_POSTREAD); 1321135048Swpaul 1322135048Swpaul while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 1323135048Swpaul 1324135048Swpaul#ifdef DEVICE_POLLING 1325150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) { 1326135048Swpaul if (sc->rxcycles <= 0) 1327135048Swpaul break; 1328135048Swpaul sc->rxcycles--; 1329135048Swpaul } 1330150789Sglebius#endif 1331135048Swpaul 1332135048Swpaul cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1333135048Swpaul m = sc->vge_ldata.vge_rx_mbuf[i]; 1334135048Swpaul total_len = VGE_RXBYTES(cur_rx); 1335135048Swpaul rxstat = le32toh(cur_rx->vge_sts); 1336135048Swpaul rxctl = le32toh(cur_rx->vge_ctl); 1337135048Swpaul 1338135048Swpaul /* Invalidate the RX mbuf and unload its map */ 1339135048Swpaul 1340135048Swpaul bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1341135048Swpaul sc->vge_ldata.vge_rx_dmamap[i], 1342135048Swpaul BUS_DMASYNC_POSTWRITE); 1343135048Swpaul bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1344135048Swpaul sc->vge_ldata.vge_rx_dmamap[i]); 1345135048Swpaul 1346135048Swpaul /* 1347135048Swpaul * If the 'start of frame' bit is set, this indicates 1348135048Swpaul * either the first fragment in a multi-fragment receive, 1349135048Swpaul * or an intermediate fragment. Either way, we want to 1350135048Swpaul * accumulate the buffers. 1351135048Swpaul */ 1352135048Swpaul if (rxstat & VGE_RXPKT_SOF) { 1353135048Swpaul m->m_len = MCLBYTES - VGE_ETHER_ALIGN; 1354135048Swpaul if (sc->vge_head == NULL) 1355135048Swpaul sc->vge_head = sc->vge_tail = m; 1356135048Swpaul else { 1357135048Swpaul m->m_flags &= ~M_PKTHDR; 1358135048Swpaul sc->vge_tail->m_next = m; 1359135048Swpaul sc->vge_tail = m; 1360135048Swpaul } 1361135048Swpaul vge_newbuf(sc, i, NULL); 1362135048Swpaul VGE_RX_DESC_INC(i); 1363135048Swpaul continue; 1364135048Swpaul } 1365135048Swpaul 1366135048Swpaul /* 1367135048Swpaul * Bad/error frames will have the RXOK bit cleared. 1368135048Swpaul * However, there's one error case we want to allow: 1369135048Swpaul * if a VLAN tagged frame arrives and the chip can't 1370135048Swpaul * match it against the CAM filter, it considers this 1371135048Swpaul * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1372135048Swpaul * We don't want to drop the frame though: our VLAN 1373135048Swpaul * filtering is done in software. 1374135048Swpaul */ 1375135048Swpaul if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1376135048Swpaul && !(rxstat & VGE_RDSTS_CSUMERR)) { 1377135048Swpaul ifp->if_ierrors++; 1378135048Swpaul /* 1379135048Swpaul * If this is part of a multi-fragment packet, 1380135048Swpaul * discard all the pieces. 1381135048Swpaul */ 1382135048Swpaul if (sc->vge_head != NULL) { 1383135048Swpaul m_freem(sc->vge_head); 1384135048Swpaul sc->vge_head = sc->vge_tail = NULL; 1385135048Swpaul } 1386135048Swpaul vge_newbuf(sc, i, m); 1387135048Swpaul VGE_RX_DESC_INC(i); 1388135048Swpaul continue; 1389135048Swpaul } 1390135048Swpaul 1391135048Swpaul /* 1392135048Swpaul * If allocating a replacement mbuf fails, 1393135048Swpaul * reload the current one. 1394135048Swpaul */ 1395135048Swpaul 1396135048Swpaul if (vge_newbuf(sc, i, NULL)) { 1397135048Swpaul ifp->if_ierrors++; 1398135048Swpaul if (sc->vge_head != NULL) { 1399135048Swpaul m_freem(sc->vge_head); 1400135048Swpaul sc->vge_head = sc->vge_tail = NULL; 1401135048Swpaul } 1402135048Swpaul vge_newbuf(sc, i, m); 1403135048Swpaul VGE_RX_DESC_INC(i); 1404135048Swpaul continue; 1405135048Swpaul } 1406135048Swpaul 1407135048Swpaul VGE_RX_DESC_INC(i); 1408135048Swpaul 1409135048Swpaul if (sc->vge_head != NULL) { 1410135048Swpaul m->m_len = total_len % (MCLBYTES - VGE_ETHER_ALIGN); 1411135048Swpaul /* 1412135048Swpaul * Special case: if there's 4 bytes or less 1413135048Swpaul * in this buffer, the mbuf can be discarded: 1414135048Swpaul * the last 4 bytes is the CRC, which we don't 1415135048Swpaul * care about anyway. 1416135048Swpaul */ 1417135048Swpaul if (m->m_len <= ETHER_CRC_LEN) { 1418135048Swpaul sc->vge_tail->m_len -= 1419135048Swpaul (ETHER_CRC_LEN - m->m_len); 1420135048Swpaul m_freem(m); 1421135048Swpaul } else { 1422135048Swpaul m->m_len -= ETHER_CRC_LEN; 1423135048Swpaul m->m_flags &= ~M_PKTHDR; 1424135048Swpaul sc->vge_tail->m_next = m; 1425135048Swpaul } 1426135048Swpaul m = sc->vge_head; 1427135048Swpaul sc->vge_head = sc->vge_tail = NULL; 1428135048Swpaul m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1429135048Swpaul } else 1430135048Swpaul m->m_pkthdr.len = m->m_len = 1431135048Swpaul (total_len - ETHER_CRC_LEN); 1432135048Swpaul 1433135048Swpaul#ifdef VGE_FIXUP_RX 1434135048Swpaul vge_fixup_rx(m); 1435135048Swpaul#endif 1436135048Swpaul ifp->if_ipackets++; 1437135048Swpaul m->m_pkthdr.rcvif = ifp; 1438135048Swpaul 1439135048Swpaul /* Do RX checksumming if enabled */ 1440135048Swpaul if (ifp->if_capenable & IFCAP_RXCSUM) { 1441135048Swpaul 1442135048Swpaul /* Check IP header checksum */ 1443135048Swpaul if (rxctl & VGE_RDCTL_IPPKT) 1444135048Swpaul m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1445135048Swpaul if (rxctl & VGE_RDCTL_IPCSUMOK) 1446135048Swpaul m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1447135048Swpaul 1448135048Swpaul /* Check TCP/UDP checksum */ 1449135048Swpaul if (rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT) && 1450135048Swpaul rxctl & VGE_RDCTL_PROTOCSUMOK) { 1451135048Swpaul m->m_pkthdr.csum_flags |= 1452135048Swpaul CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1453135048Swpaul m->m_pkthdr.csum_data = 0xffff; 1454135048Swpaul } 1455135048Swpaul } 1456135048Swpaul 1457153512Sglebius if (rxstat & VGE_RDSTS_VTAG) { 1458164776Sru /* 1459164776Sru * The 32-bit rxctl register is stored in little-endian. 1460164776Sru * However, the 16-bit vlan tag is stored in big-endian, 1461164776Sru * so we have to byte swap it. 1462164776Sru */ 1463162375Sandre m->m_pkthdr.ether_vtag = 1464164776Sru bswap16(rxctl & VGE_RDCTL_VLANID); 1465162375Sandre m->m_flags |= M_VLANTAG; 1466153512Sglebius } 1467135048Swpaul 1468135048Swpaul VGE_UNLOCK(sc); 1469135048Swpaul (*ifp->if_input)(ifp, m); 1470135048Swpaul VGE_LOCK(sc); 1471135048Swpaul 1472135048Swpaul lim++; 1473135048Swpaul if (lim == VGE_RX_DESC_CNT) 1474135048Swpaul break; 1475135048Swpaul 1476135048Swpaul } 1477135048Swpaul 1478135048Swpaul /* Flush the RX DMA ring */ 1479135048Swpaul 1480135048Swpaul bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1481135048Swpaul sc->vge_ldata.vge_rx_list_map, 1482135048Swpaul BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1483135048Swpaul 1484135048Swpaul sc->vge_ldata.vge_rx_prodidx = i; 1485135048Swpaul CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1486135048Swpaul 1487135048Swpaul 1488135048Swpaul return; 1489135048Swpaul} 1490135048Swpaul 1491135048Swpaulstatic void 1492135048Swpaulvge_txeof(sc) 1493135048Swpaul struct vge_softc *sc; 1494135048Swpaul{ 1495135048Swpaul struct ifnet *ifp; 1496135048Swpaul u_int32_t txstat; 1497135048Swpaul int idx; 1498135048Swpaul 1499147256Sbrooks ifp = sc->vge_ifp; 1500135048Swpaul idx = sc->vge_ldata.vge_tx_considx; 1501135048Swpaul 1502135048Swpaul /* Invalidate the TX descriptor list */ 1503135048Swpaul 1504135048Swpaul bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1505135048Swpaul sc->vge_ldata.vge_tx_list_map, 1506135048Swpaul BUS_DMASYNC_POSTREAD); 1507135048Swpaul 1508135048Swpaul while (idx != sc->vge_ldata.vge_tx_prodidx) { 1509135048Swpaul 1510135048Swpaul txstat = le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1511135048Swpaul if (txstat & VGE_TDSTS_OWN) 1512135048Swpaul break; 1513135048Swpaul 1514135048Swpaul m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1515135048Swpaul sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1516135048Swpaul bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1517135048Swpaul sc->vge_ldata.vge_tx_dmamap[idx]); 1518135048Swpaul if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1519135048Swpaul ifp->if_collisions++; 1520135048Swpaul if (txstat & VGE_TDSTS_TXERR) 1521135048Swpaul ifp->if_oerrors++; 1522135048Swpaul else 1523135048Swpaul ifp->if_opackets++; 1524135048Swpaul 1525135048Swpaul sc->vge_ldata.vge_tx_free++; 1526135048Swpaul VGE_TX_DESC_INC(idx); 1527135048Swpaul } 1528135048Swpaul 1529135048Swpaul /* No changes made to the TX ring, so no flush needed */ 1530135048Swpaul 1531135048Swpaul if (idx != sc->vge_ldata.vge_tx_considx) { 1532135048Swpaul sc->vge_ldata.vge_tx_considx = idx; 1533148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1534135048Swpaul ifp->if_timer = 0; 1535135048Swpaul } 1536135048Swpaul 1537135048Swpaul /* 1538135048Swpaul * If not all descriptors have been released reaped yet, 1539135048Swpaul * reload the timer so that we will eventually get another 1540135048Swpaul * interrupt that will cause us to re-enter this routine. 1541135048Swpaul * This is done in case the transmitter has gone idle. 1542135048Swpaul */ 1543135048Swpaul if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) { 1544135048Swpaul CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1545135048Swpaul } 1546135048Swpaul 1547135048Swpaul return; 1548135048Swpaul} 1549135048Swpaul 1550135048Swpaulstatic void 1551135048Swpaulvge_tick(xsc) 1552135048Swpaul void *xsc; 1553135048Swpaul{ 1554135048Swpaul struct vge_softc *sc; 1555135048Swpaul struct ifnet *ifp; 1556135048Swpaul struct mii_data *mii; 1557135048Swpaul 1558135048Swpaul sc = xsc; 1559147256Sbrooks ifp = sc->vge_ifp; 1560135048Swpaul VGE_LOCK(sc); 1561135048Swpaul mii = device_get_softc(sc->vge_miibus); 1562135048Swpaul 1563135048Swpaul mii_tick(mii); 1564135048Swpaul if (sc->vge_link) { 1565135048Swpaul if (!(mii->mii_media_status & IFM_ACTIVE)) { 1566135048Swpaul sc->vge_link = 0; 1567147256Sbrooks if_link_state_change(sc->vge_ifp, 1568145521Swpaul LINK_STATE_DOWN); 1569135048Swpaul } 1570135048Swpaul } else { 1571135048Swpaul if (mii->mii_media_status & IFM_ACTIVE && 1572135048Swpaul IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1573135048Swpaul sc->vge_link = 1; 1574147256Sbrooks if_link_state_change(sc->vge_ifp, 1575145521Swpaul LINK_STATE_UP); 1576135048Swpaul if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1577135048Swpaul taskqueue_enqueue(taskqueue_swi, 1578135048Swpaul &sc->vge_txtask); 1579135048Swpaul } 1580135048Swpaul } 1581135048Swpaul 1582135048Swpaul VGE_UNLOCK(sc); 1583135048Swpaul 1584135048Swpaul return; 1585135048Swpaul} 1586135048Swpaul 1587135048Swpaul#ifdef DEVICE_POLLING 1588135048Swpaulstatic void 1589135048Swpaulvge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1590135048Swpaul{ 1591135048Swpaul struct vge_softc *sc = ifp->if_softc; 1592135048Swpaul 1593135048Swpaul VGE_LOCK(sc); 1594150789Sglebius if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1595135048Swpaul goto done; 1596135048Swpaul 1597135048Swpaul sc->rxcycles = count; 1598135048Swpaul vge_rxeof(sc); 1599135048Swpaul vge_txeof(sc); 1600135048Swpaul 1601135048Swpaul if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1602135048Swpaul taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1603135048Swpaul 1604135048Swpaul if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1605135048Swpaul u_int32_t status; 1606135048Swpaul status = CSR_READ_4(sc, VGE_ISR); 1607135048Swpaul if (status == 0xFFFFFFFF) 1608135048Swpaul goto done; 1609135048Swpaul if (status) 1610135048Swpaul CSR_WRITE_4(sc, VGE_ISR, status); 1611135048Swpaul 1612135048Swpaul /* 1613135048Swpaul * XXX check behaviour on receiver stalls. 1614135048Swpaul */ 1615135048Swpaul 1616135048Swpaul if (status & VGE_ISR_TXDMA_STALL || 1617135048Swpaul status & VGE_ISR_RXDMA_STALL) 1618135048Swpaul vge_init(sc); 1619135048Swpaul 1620135048Swpaul if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1621135048Swpaul vge_rxeof(sc); 1622135048Swpaul ifp->if_ierrors++; 1623135048Swpaul CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1624135048Swpaul CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1625135048Swpaul } 1626135048Swpaul } 1627135048Swpauldone: 1628135048Swpaul VGE_UNLOCK(sc); 1629135048Swpaul} 1630135048Swpaul#endif /* DEVICE_POLLING */ 1631135048Swpaul 1632135048Swpaulstatic void 1633135048Swpaulvge_intr(arg) 1634135048Swpaul void *arg; 1635135048Swpaul{ 1636135048Swpaul struct vge_softc *sc; 1637135048Swpaul struct ifnet *ifp; 1638135048Swpaul u_int32_t status; 1639135048Swpaul 1640135048Swpaul sc = arg; 1641135048Swpaul 1642135048Swpaul if (sc->suspended) { 1643135048Swpaul return; 1644135048Swpaul } 1645135048Swpaul 1646135048Swpaul VGE_LOCK(sc); 1647147256Sbrooks ifp = sc->vge_ifp; 1648135048Swpaul 1649135048Swpaul if (!(ifp->if_flags & IFF_UP)) { 1650135048Swpaul VGE_UNLOCK(sc); 1651135048Swpaul return; 1652135048Swpaul } 1653135048Swpaul 1654135048Swpaul#ifdef DEVICE_POLLING 1655150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) { 1656150789Sglebius VGE_UNLOCK(sc); 1657150789Sglebius return; 1658150789Sglebius } 1659135048Swpaul#endif 1660135048Swpaul 1661135048Swpaul /* Disable interrupts */ 1662135048Swpaul CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1663135048Swpaul 1664135048Swpaul for (;;) { 1665135048Swpaul 1666135048Swpaul status = CSR_READ_4(sc, VGE_ISR); 1667135048Swpaul /* If the card has gone away the read returns 0xffff. */ 1668135048Swpaul if (status == 0xFFFFFFFF) 1669135048Swpaul break; 1670135048Swpaul 1671135048Swpaul if (status) 1672135048Swpaul CSR_WRITE_4(sc, VGE_ISR, status); 1673135048Swpaul 1674135048Swpaul if ((status & VGE_INTRS) == 0) 1675135048Swpaul break; 1676135048Swpaul 1677135048Swpaul if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1678135048Swpaul vge_rxeof(sc); 1679135048Swpaul 1680135048Swpaul if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1681135048Swpaul vge_rxeof(sc); 1682135048Swpaul CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1683135048Swpaul CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1684135048Swpaul } 1685135048Swpaul 1686135048Swpaul if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1687135048Swpaul vge_txeof(sc); 1688135048Swpaul 1689135048Swpaul if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1690135048Swpaul vge_init(sc); 1691135048Swpaul 1692135048Swpaul if (status & VGE_ISR_LINKSTS) 1693135048Swpaul vge_tick(sc); 1694135048Swpaul } 1695135048Swpaul 1696135048Swpaul /* Re-enable interrupts */ 1697135048Swpaul CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1698135048Swpaul 1699135048Swpaul VGE_UNLOCK(sc); 1700135048Swpaul 1701135048Swpaul if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1702135048Swpaul taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1703135048Swpaul 1704135048Swpaul return; 1705135048Swpaul} 1706135048Swpaul 1707135048Swpaulstatic int 1708135048Swpaulvge_encap(sc, m_head, idx) 1709135048Swpaul struct vge_softc *sc; 1710135048Swpaul struct mbuf *m_head; 1711135048Swpaul int idx; 1712135048Swpaul{ 1713135048Swpaul struct mbuf *m_new = NULL; 1714135048Swpaul struct vge_dmaload_arg arg; 1715135048Swpaul bus_dmamap_t map; 1716135048Swpaul int error; 1717135048Swpaul 1718135048Swpaul if (sc->vge_ldata.vge_tx_free <= 2) 1719135048Swpaul return (EFBIG); 1720135048Swpaul 1721135048Swpaul arg.vge_flags = 0; 1722135048Swpaul 1723135048Swpaul if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1724135048Swpaul arg.vge_flags |= VGE_TDCTL_IPCSUM; 1725135048Swpaul if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1726135048Swpaul arg.vge_flags |= VGE_TDCTL_TCPCSUM; 1727135048Swpaul if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1728135048Swpaul arg.vge_flags |= VGE_TDCTL_UDPCSUM; 1729135048Swpaul 1730135048Swpaul arg.sc = sc; 1731135048Swpaul arg.vge_idx = idx; 1732135048Swpaul arg.vge_m0 = m_head; 1733135048Swpaul arg.vge_maxsegs = VGE_TX_FRAGS; 1734135048Swpaul 1735135048Swpaul map = sc->vge_ldata.vge_tx_dmamap[idx]; 1736135048Swpaul error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1737135048Swpaul m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1738135048Swpaul 1739135048Swpaul if (error && error != EFBIG) { 1740135048Swpaul printf("vge%d: can't map mbuf (error %d)\n", 1741135048Swpaul sc->vge_unit, error); 1742135048Swpaul return (ENOBUFS); 1743135048Swpaul } 1744135048Swpaul 1745135048Swpaul /* Too many segments to map, coalesce into a single mbuf */ 1746135048Swpaul 1747135048Swpaul if (error || arg.vge_maxsegs == 0) { 1748135048Swpaul m_new = m_defrag(m_head, M_DONTWAIT); 1749135048Swpaul if (m_new == NULL) 1750135048Swpaul return (1); 1751135048Swpaul else 1752135048Swpaul m_head = m_new; 1753135048Swpaul 1754135048Swpaul arg.sc = sc; 1755135048Swpaul arg.vge_m0 = m_head; 1756135048Swpaul arg.vge_idx = idx; 1757135048Swpaul arg.vge_maxsegs = 1; 1758135048Swpaul 1759135048Swpaul error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1760135048Swpaul m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1761135048Swpaul if (error) { 1762135048Swpaul printf("vge%d: can't map mbuf (error %d)\n", 1763135048Swpaul sc->vge_unit, error); 1764135048Swpaul return (EFBIG); 1765135048Swpaul } 1766135048Swpaul } 1767135048Swpaul 1768135048Swpaul sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1769135048Swpaul sc->vge_ldata.vge_tx_free--; 1770135048Swpaul 1771135048Swpaul /* 1772135048Swpaul * Set up hardware VLAN tagging. 1773135048Swpaul */ 1774135048Swpaul 1775162375Sandre if (m_head->m_flags & M_VLANTAG) 1776135048Swpaul sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1777164776Sru htole32(m_head->m_pkthdr.ether_vtag | VGE_TDCTL_VTAG); 1778135048Swpaul 1779135048Swpaul sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1780135048Swpaul 1781135048Swpaul return (0); 1782135048Swpaul} 1783135048Swpaul 1784135048Swpaulstatic void 1785135048Swpaulvge_tx_task(arg, npending) 1786135048Swpaul void *arg; 1787135048Swpaul int npending; 1788135048Swpaul{ 1789135048Swpaul struct ifnet *ifp; 1790135048Swpaul 1791135048Swpaul ifp = arg; 1792135048Swpaul vge_start(ifp); 1793135048Swpaul 1794135048Swpaul return; 1795135048Swpaul} 1796135048Swpaul 1797135048Swpaul/* 1798135048Swpaul * Main transmit routine. 1799135048Swpaul */ 1800135048Swpaul 1801135048Swpaulstatic void 1802135048Swpaulvge_start(ifp) 1803135048Swpaul struct ifnet *ifp; 1804135048Swpaul{ 1805135048Swpaul struct vge_softc *sc; 1806135048Swpaul struct mbuf *m_head = NULL; 1807135048Swpaul int idx, pidx = 0; 1808135048Swpaul 1809135048Swpaul sc = ifp->if_softc; 1810135048Swpaul VGE_LOCK(sc); 1811135048Swpaul 1812148887Srwatson if (!sc->vge_link || ifp->if_drv_flags & IFF_DRV_OACTIVE) { 1813135048Swpaul VGE_UNLOCK(sc); 1814135048Swpaul return; 1815135048Swpaul } 1816135048Swpaul 1817135048Swpaul if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 1818135048Swpaul VGE_UNLOCK(sc); 1819135048Swpaul return; 1820135048Swpaul } 1821135048Swpaul 1822135048Swpaul idx = sc->vge_ldata.vge_tx_prodidx; 1823135048Swpaul 1824135048Swpaul pidx = idx - 1; 1825135048Swpaul if (pidx < 0) 1826135048Swpaul pidx = VGE_TX_DESC_CNT - 1; 1827135048Swpaul 1828135048Swpaul 1829135048Swpaul while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1830135048Swpaul IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1831135048Swpaul if (m_head == NULL) 1832135048Swpaul break; 1833135048Swpaul 1834135048Swpaul if (vge_encap(sc, m_head, idx)) { 1835135048Swpaul IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1836148887Srwatson ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1837135048Swpaul break; 1838135048Swpaul } 1839135048Swpaul 1840135048Swpaul sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1841135048Swpaul htole16(VGE_TXDESC_Q); 1842135048Swpaul 1843135048Swpaul pidx = idx; 1844135048Swpaul VGE_TX_DESC_INC(idx); 1845135048Swpaul 1846135048Swpaul /* 1847135048Swpaul * If there's a BPF listener, bounce a copy of this frame 1848135048Swpaul * to him. 1849135048Swpaul */ 1850167190Scsjp ETHER_BPF_MTAP(ifp, m_head); 1851135048Swpaul } 1852135048Swpaul 1853135048Swpaul if (idx == sc->vge_ldata.vge_tx_prodidx) { 1854135048Swpaul VGE_UNLOCK(sc); 1855135048Swpaul return; 1856135048Swpaul } 1857135048Swpaul 1858135048Swpaul /* Flush the TX descriptors */ 1859135048Swpaul 1860135048Swpaul bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1861135048Swpaul sc->vge_ldata.vge_tx_list_map, 1862135048Swpaul BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1863135048Swpaul 1864135048Swpaul /* Issue a transmit command. */ 1865135048Swpaul CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1866135048Swpaul 1867135048Swpaul sc->vge_ldata.vge_tx_prodidx = idx; 1868135048Swpaul 1869135048Swpaul /* 1870135048Swpaul * Use the countdown timer for interrupt moderation. 1871135048Swpaul * 'TX done' interrupts are disabled. Instead, we reset the 1872135048Swpaul * countdown timer, which will begin counting until it hits 1873135048Swpaul * the value in the SSTIMER register, and then trigger an 1874135048Swpaul * interrupt. Each time we set the TIMER0_ENABLE bit, the 1875135048Swpaul * the timer count is reloaded. Only when the transmitter 1876135048Swpaul * is idle will the timer hit 0 and an interrupt fire. 1877135048Swpaul */ 1878135048Swpaul CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1879135048Swpaul 1880135048Swpaul VGE_UNLOCK(sc); 1881135048Swpaul 1882135048Swpaul /* 1883135048Swpaul * Set a timeout in case the chip goes out to lunch. 1884135048Swpaul */ 1885135048Swpaul ifp->if_timer = 5; 1886135048Swpaul 1887135048Swpaul return; 1888135048Swpaul} 1889135048Swpaul 1890135048Swpaulstatic void 1891135048Swpaulvge_init(xsc) 1892135048Swpaul void *xsc; 1893135048Swpaul{ 1894135048Swpaul struct vge_softc *sc = xsc; 1895147256Sbrooks struct ifnet *ifp = sc->vge_ifp; 1896135048Swpaul struct mii_data *mii; 1897135048Swpaul int i; 1898135048Swpaul 1899135048Swpaul VGE_LOCK(sc); 1900135048Swpaul mii = device_get_softc(sc->vge_miibus); 1901135048Swpaul 1902135048Swpaul /* 1903135048Swpaul * Cancel pending I/O and free all RX/TX buffers. 1904135048Swpaul */ 1905135048Swpaul vge_stop(sc); 1906135048Swpaul vge_reset(sc); 1907135048Swpaul 1908135048Swpaul /* 1909135048Swpaul * Initialize the RX and TX descriptors and mbufs. 1910135048Swpaul */ 1911135048Swpaul 1912135048Swpaul vge_rx_list_init(sc); 1913135048Swpaul vge_tx_list_init(sc); 1914135048Swpaul 1915135048Swpaul /* Set our station address */ 1916135048Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 1917152315Sru CSR_WRITE_1(sc, VGE_PAR0 + i, IF_LLADDR(sc->vge_ifp)[i]); 1918135048Swpaul 1919135048Swpaul /* 1920135048Swpaul * Set receive FIFO threshold. Also allow transmission and 1921135048Swpaul * reception of VLAN tagged frames. 1922135048Swpaul */ 1923135048Swpaul CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1924135048Swpaul CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1925135048Swpaul 1926135048Swpaul /* Set DMA burst length */ 1927135048Swpaul CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1928135048Swpaul CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1929135048Swpaul 1930135048Swpaul CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1931135048Swpaul 1932135048Swpaul /* Set collision backoff algorithm */ 1933135048Swpaul CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1934135048Swpaul VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1935135048Swpaul CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1936135048Swpaul 1937135048Swpaul /* Disable LPSEL field in priority resolution */ 1938135048Swpaul CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1939135048Swpaul 1940135048Swpaul /* 1941135048Swpaul * Load the addresses of the DMA queues into the chip. 1942135048Swpaul * Note that we only use one transmit queue. 1943135048Swpaul */ 1944135048Swpaul 1945135048Swpaul CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 1946135048Swpaul VGE_ADDR_LO(sc->vge_ldata.vge_tx_list_addr)); 1947135048Swpaul CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 1948135048Swpaul 1949135048Swpaul CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 1950135048Swpaul VGE_ADDR_LO(sc->vge_ldata.vge_rx_list_addr)); 1951135048Swpaul CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 1952135048Swpaul CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 1953135048Swpaul 1954135048Swpaul /* Enable and wake up the RX descriptor queue */ 1955135048Swpaul CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1956135048Swpaul CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1957135048Swpaul 1958135048Swpaul /* Enable the TX descriptor queue */ 1959135048Swpaul CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1960135048Swpaul 1961135048Swpaul /* Set up the receive filter -- allow large frames for VLANs. */ 1962135048Swpaul CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 1963135048Swpaul 1964135048Swpaul /* If we want promiscuous mode, set the allframes bit. */ 1965135048Swpaul if (ifp->if_flags & IFF_PROMISC) { 1966135048Swpaul CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1967135048Swpaul } 1968135048Swpaul 1969135048Swpaul /* Set capture broadcast bit to capture broadcast frames. */ 1970135048Swpaul if (ifp->if_flags & IFF_BROADCAST) { 1971135048Swpaul CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1972135048Swpaul } 1973135048Swpaul 1974135048Swpaul /* Set multicast bit to capture multicast frames. */ 1975135048Swpaul if (ifp->if_flags & IFF_MULTICAST) { 1976135048Swpaul CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1977135048Swpaul } 1978135048Swpaul 1979135048Swpaul /* Init the cam filter. */ 1980135048Swpaul vge_cam_clear(sc); 1981135048Swpaul 1982135048Swpaul /* Init the multicast filter. */ 1983135048Swpaul vge_setmulti(sc); 1984135048Swpaul 1985135048Swpaul /* Enable flow control */ 1986135048Swpaul 1987135048Swpaul CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1988135048Swpaul 1989135048Swpaul /* Enable jumbo frame reception (if desired) */ 1990135048Swpaul 1991135048Swpaul /* Start the MAC. */ 1992135048Swpaul CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1993135048Swpaul CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1994135048Swpaul CSR_WRITE_1(sc, VGE_CRS0, 1995135048Swpaul VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1996135048Swpaul 1997135048Swpaul /* 1998135048Swpaul * Configure one-shot timer for microsecond 1999135048Swpaul * resulution and load it for 500 usecs. 2000135048Swpaul */ 2001135048Swpaul CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 2002135048Swpaul CSR_WRITE_2(sc, VGE_SSTIMER, 400); 2003135048Swpaul 2004135048Swpaul /* 2005135048Swpaul * Configure interrupt moderation for receive. Enable 2006135048Swpaul * the holdoff counter and load it, and set the RX 2007135048Swpaul * suppression count to the number of descriptors we 2008135048Swpaul * want to allow before triggering an interrupt. 2009135048Swpaul * The holdoff timer is in units of 20 usecs. 2010135048Swpaul */ 2011135048Swpaul 2012135048Swpaul#ifdef notyet 2013135048Swpaul CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 2014135048Swpaul /* Select the interrupt holdoff timer page. */ 2015135048Swpaul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2016135048Swpaul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 2017135048Swpaul CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 2018135048Swpaul 2019135048Swpaul /* Enable use of the holdoff timer. */ 2020135048Swpaul CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 2021135048Swpaul CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 2022135048Swpaul 2023135048Swpaul /* Select the RX suppression threshold page. */ 2024135048Swpaul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2025135048Swpaul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 2026135048Swpaul CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 2027135048Swpaul 2028135048Swpaul /* Restore the page select bits. */ 2029135048Swpaul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2030135048Swpaul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 2031135048Swpaul#endif 2032135048Swpaul 2033135048Swpaul#ifdef DEVICE_POLLING 2034135048Swpaul /* 2035135048Swpaul * Disable interrupts if we are polling. 2036135048Swpaul */ 2037150789Sglebius if (ifp->if_capenable & IFCAP_POLLING) { 2038135048Swpaul CSR_WRITE_4(sc, VGE_IMR, 0); 2039135048Swpaul CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2040135048Swpaul } else /* otherwise ... */ 2041150789Sglebius#endif 2042135048Swpaul { 2043135048Swpaul /* 2044135048Swpaul * Enable interrupts. 2045135048Swpaul */ 2046135048Swpaul CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2047135048Swpaul CSR_WRITE_4(sc, VGE_ISR, 0); 2048135048Swpaul CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2049135048Swpaul } 2050135048Swpaul 2051135048Swpaul mii_mediachg(mii); 2052135048Swpaul 2053148887Srwatson ifp->if_drv_flags |= IFF_DRV_RUNNING; 2054148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2055135048Swpaul 2056135048Swpaul sc->vge_if_flags = 0; 2057135048Swpaul sc->vge_link = 0; 2058135048Swpaul 2059135048Swpaul VGE_UNLOCK(sc); 2060135048Swpaul 2061135048Swpaul return; 2062135048Swpaul} 2063135048Swpaul 2064135048Swpaul/* 2065135048Swpaul * Set media options. 2066135048Swpaul */ 2067135048Swpaulstatic int 2068135048Swpaulvge_ifmedia_upd(ifp) 2069135048Swpaul struct ifnet *ifp; 2070135048Swpaul{ 2071135048Swpaul struct vge_softc *sc; 2072135048Swpaul struct mii_data *mii; 2073135048Swpaul 2074135048Swpaul sc = ifp->if_softc; 2075161995Smr VGE_LOCK(sc); 2076135048Swpaul mii = device_get_softc(sc->vge_miibus); 2077135048Swpaul mii_mediachg(mii); 2078161995Smr VGE_UNLOCK(sc); 2079135048Swpaul 2080135048Swpaul return (0); 2081135048Swpaul} 2082135048Swpaul 2083135048Swpaul/* 2084135048Swpaul * Report current media status. 2085135048Swpaul */ 2086135048Swpaulstatic void 2087135048Swpaulvge_ifmedia_sts(ifp, ifmr) 2088135048Swpaul struct ifnet *ifp; 2089135048Swpaul struct ifmediareq *ifmr; 2090135048Swpaul{ 2091135048Swpaul struct vge_softc *sc; 2092135048Swpaul struct mii_data *mii; 2093135048Swpaul 2094135048Swpaul sc = ifp->if_softc; 2095135048Swpaul mii = device_get_softc(sc->vge_miibus); 2096135048Swpaul 2097135048Swpaul mii_pollstat(mii); 2098135048Swpaul ifmr->ifm_active = mii->mii_media_active; 2099135048Swpaul ifmr->ifm_status = mii->mii_media_status; 2100135048Swpaul 2101135048Swpaul return; 2102135048Swpaul} 2103135048Swpaul 2104135048Swpaulstatic void 2105135048Swpaulvge_miibus_statchg(dev) 2106135048Swpaul device_t dev; 2107135048Swpaul{ 2108135048Swpaul struct vge_softc *sc; 2109135048Swpaul struct mii_data *mii; 2110135048Swpaul struct ifmedia_entry *ife; 2111135048Swpaul 2112135048Swpaul sc = device_get_softc(dev); 2113135048Swpaul mii = device_get_softc(sc->vge_miibus); 2114135048Swpaul ife = mii->mii_media.ifm_cur; 2115135048Swpaul 2116135048Swpaul /* 2117135048Swpaul * If the user manually selects a media mode, we need to turn 2118135048Swpaul * on the forced MAC mode bit in the DIAGCTL register. If the 2119135048Swpaul * user happens to choose a full duplex mode, we also need to 2120135048Swpaul * set the 'force full duplex' bit. This applies only to 2121135048Swpaul * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2122135048Swpaul * mode is disabled, and in 1000baseT mode, full duplex is 2123135048Swpaul * always implied, so we turn on the forced mode bit but leave 2124135048Swpaul * the FDX bit cleared. 2125135048Swpaul */ 2126135048Swpaul 2127135048Swpaul switch (IFM_SUBTYPE(ife->ifm_media)) { 2128135048Swpaul case IFM_AUTO: 2129135048Swpaul CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2130135048Swpaul CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2131135048Swpaul break; 2132135048Swpaul case IFM_1000_T: 2133135048Swpaul CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2134135048Swpaul CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2135135048Swpaul break; 2136135048Swpaul case IFM_100_TX: 2137135048Swpaul case IFM_10_T: 2138135048Swpaul CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2139135048Swpaul if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2140135048Swpaul CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2141135048Swpaul } else { 2142135048Swpaul CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2143135048Swpaul } 2144135048Swpaul break; 2145135048Swpaul default: 2146135048Swpaul device_printf(dev, "unknown media type: %x\n", 2147135048Swpaul IFM_SUBTYPE(ife->ifm_media)); 2148135048Swpaul break; 2149135048Swpaul } 2150135048Swpaul 2151135048Swpaul return; 2152135048Swpaul} 2153135048Swpaul 2154135048Swpaulstatic int 2155135048Swpaulvge_ioctl(ifp, command, data) 2156135048Swpaul struct ifnet *ifp; 2157135048Swpaul u_long command; 2158135048Swpaul caddr_t data; 2159135048Swpaul{ 2160135048Swpaul struct vge_softc *sc = ifp->if_softc; 2161135048Swpaul struct ifreq *ifr = (struct ifreq *) data; 2162135048Swpaul struct mii_data *mii; 2163135048Swpaul int error = 0; 2164135048Swpaul 2165135048Swpaul switch (command) { 2166135048Swpaul case SIOCSIFMTU: 2167135048Swpaul if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2168135048Swpaul error = EINVAL; 2169135048Swpaul ifp->if_mtu = ifr->ifr_mtu; 2170135048Swpaul break; 2171135048Swpaul case SIOCSIFFLAGS: 2172135048Swpaul if (ifp->if_flags & IFF_UP) { 2173148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2174135048Swpaul ifp->if_flags & IFF_PROMISC && 2175135048Swpaul !(sc->vge_if_flags & IFF_PROMISC)) { 2176135048Swpaul CSR_SETBIT_1(sc, VGE_RXCTL, 2177135048Swpaul VGE_RXCTL_RX_PROMISC); 2178135048Swpaul vge_setmulti(sc); 2179148887Srwatson } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2180135048Swpaul !(ifp->if_flags & IFF_PROMISC) && 2181135048Swpaul sc->vge_if_flags & IFF_PROMISC) { 2182135048Swpaul CSR_CLRBIT_1(sc, VGE_RXCTL, 2183135048Swpaul VGE_RXCTL_RX_PROMISC); 2184135048Swpaul vge_setmulti(sc); 2185135048Swpaul } else 2186135048Swpaul vge_init(sc); 2187135048Swpaul } else { 2188148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2189135048Swpaul vge_stop(sc); 2190135048Swpaul } 2191135048Swpaul sc->vge_if_flags = ifp->if_flags; 2192135048Swpaul break; 2193135048Swpaul case SIOCADDMULTI: 2194135048Swpaul case SIOCDELMULTI: 2195135048Swpaul vge_setmulti(sc); 2196135048Swpaul break; 2197135048Swpaul case SIOCGIFMEDIA: 2198135048Swpaul case SIOCSIFMEDIA: 2199135048Swpaul mii = device_get_softc(sc->vge_miibus); 2200135048Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2201135048Swpaul break; 2202135048Swpaul case SIOCSIFCAP: 2203150789Sglebius { 2204150789Sglebius int mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2205150789Sglebius#ifdef DEVICE_POLLING 2206150789Sglebius if (mask & IFCAP_POLLING) { 2207150789Sglebius if (ifr->ifr_reqcap & IFCAP_POLLING) { 2208150789Sglebius error = ether_poll_register(vge_poll, ifp); 2209150789Sglebius if (error) 2210150789Sglebius return(error); 2211150789Sglebius VGE_LOCK(sc); 2212150789Sglebius /* Disable interrupts */ 2213150789Sglebius CSR_WRITE_4(sc, VGE_IMR, 0); 2214150789Sglebius CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2215150789Sglebius ifp->if_capenable |= IFCAP_POLLING; 2216150789Sglebius VGE_UNLOCK(sc); 2217150789Sglebius } else { 2218150789Sglebius error = ether_poll_deregister(ifp); 2219150789Sglebius /* Enable interrupts. */ 2220150789Sglebius VGE_LOCK(sc); 2221150789Sglebius CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2222150789Sglebius CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2223150789Sglebius CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2224150789Sglebius ifp->if_capenable &= ~IFCAP_POLLING; 2225150789Sglebius VGE_UNLOCK(sc); 2226150789Sglebius } 2227150789Sglebius } 2228150789Sglebius#endif /* DEVICE_POLLING */ 2229184908Syongari if ((mask & IFCAP_TXCSUM) != 0 && 2230184908Syongari (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2231184908Syongari ifp->if_capenable ^= IFCAP_TXCSUM; 2232184908Syongari if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2233184908Syongari ifp->if_hwassist |= VGE_CSUM_FEATURES; 2234150789Sglebius else 2235184908Syongari ifp->if_hwassist &= ~VGE_CSUM_FEATURES; 2236150789Sglebius } 2237184908Syongari if ((mask & IFCAP_RXCSUM) != 0 && 2238184908Syongari (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 2239184908Syongari ifp->if_capenable ^= IFCAP_RXCSUM; 2240150789Sglebius } 2241135048Swpaul break; 2242135048Swpaul default: 2243135048Swpaul error = ether_ioctl(ifp, command, data); 2244135048Swpaul break; 2245135048Swpaul } 2246135048Swpaul 2247135048Swpaul return (error); 2248135048Swpaul} 2249135048Swpaul 2250135048Swpaulstatic void 2251135048Swpaulvge_watchdog(ifp) 2252135048Swpaul struct ifnet *ifp; 2253135048Swpaul{ 2254135048Swpaul struct vge_softc *sc; 2255135048Swpaul 2256135048Swpaul sc = ifp->if_softc; 2257135048Swpaul VGE_LOCK(sc); 2258135048Swpaul printf("vge%d: watchdog timeout\n", sc->vge_unit); 2259135048Swpaul ifp->if_oerrors++; 2260135048Swpaul 2261135048Swpaul vge_txeof(sc); 2262135048Swpaul vge_rxeof(sc); 2263135048Swpaul 2264135048Swpaul vge_init(sc); 2265135048Swpaul 2266135048Swpaul VGE_UNLOCK(sc); 2267135048Swpaul 2268135048Swpaul return; 2269135048Swpaul} 2270135048Swpaul 2271135048Swpaul/* 2272135048Swpaul * Stop the adapter and free any mbufs allocated to the 2273135048Swpaul * RX and TX lists. 2274135048Swpaul */ 2275135048Swpaulstatic void 2276135048Swpaulvge_stop(sc) 2277135048Swpaul struct vge_softc *sc; 2278135048Swpaul{ 2279135048Swpaul register int i; 2280135048Swpaul struct ifnet *ifp; 2281135048Swpaul 2282135048Swpaul VGE_LOCK(sc); 2283147256Sbrooks ifp = sc->vge_ifp; 2284135048Swpaul ifp->if_timer = 0; 2285135048Swpaul 2286148887Srwatson ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2287135048Swpaul 2288135048Swpaul CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2289135048Swpaul CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2290135048Swpaul CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2291135048Swpaul CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2292135048Swpaul CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2293135048Swpaul CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2294135048Swpaul 2295135048Swpaul if (sc->vge_head != NULL) { 2296135048Swpaul m_freem(sc->vge_head); 2297135048Swpaul sc->vge_head = sc->vge_tail = NULL; 2298135048Swpaul } 2299135048Swpaul 2300135048Swpaul /* Free the TX list buffers. */ 2301135048Swpaul 2302135048Swpaul for (i = 0; i < VGE_TX_DESC_CNT; i++) { 2303135048Swpaul if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 2304135048Swpaul bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2305135048Swpaul sc->vge_ldata.vge_tx_dmamap[i]); 2306135048Swpaul m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 2307135048Swpaul sc->vge_ldata.vge_tx_mbuf[i] = NULL; 2308135048Swpaul } 2309135048Swpaul } 2310135048Swpaul 2311135048Swpaul /* Free the RX list buffers. */ 2312135048Swpaul 2313135048Swpaul for (i = 0; i < VGE_RX_DESC_CNT; i++) { 2314135048Swpaul if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 2315135048Swpaul bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2316135048Swpaul sc->vge_ldata.vge_rx_dmamap[i]); 2317135048Swpaul m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 2318135048Swpaul sc->vge_ldata.vge_rx_mbuf[i] = NULL; 2319135048Swpaul } 2320135048Swpaul } 2321135048Swpaul 2322135048Swpaul VGE_UNLOCK(sc); 2323135048Swpaul 2324135048Swpaul return; 2325135048Swpaul} 2326135048Swpaul 2327135048Swpaul/* 2328135048Swpaul * Device suspend routine. Stop the interface and save some PCI 2329135048Swpaul * settings in case the BIOS doesn't restore them properly on 2330135048Swpaul * resume. 2331135048Swpaul */ 2332135048Swpaulstatic int 2333135048Swpaulvge_suspend(dev) 2334135048Swpaul device_t dev; 2335135048Swpaul{ 2336135048Swpaul struct vge_softc *sc; 2337135048Swpaul 2338135048Swpaul sc = device_get_softc(dev); 2339135048Swpaul 2340135048Swpaul vge_stop(sc); 2341135048Swpaul 2342135048Swpaul sc->suspended = 1; 2343135048Swpaul 2344135048Swpaul return (0); 2345135048Swpaul} 2346135048Swpaul 2347135048Swpaul/* 2348135048Swpaul * Device resume routine. Restore some PCI settings in case the BIOS 2349135048Swpaul * doesn't, re-enable busmastering, and restart the interface if 2350135048Swpaul * appropriate. 2351135048Swpaul */ 2352135048Swpaulstatic int 2353135048Swpaulvge_resume(dev) 2354135048Swpaul device_t dev; 2355135048Swpaul{ 2356135048Swpaul struct vge_softc *sc; 2357135048Swpaul struct ifnet *ifp; 2358135048Swpaul 2359135048Swpaul sc = device_get_softc(dev); 2360147256Sbrooks ifp = sc->vge_ifp; 2361135048Swpaul 2362135048Swpaul /* reenable busmastering */ 2363135048Swpaul pci_enable_busmaster(dev); 2364135048Swpaul pci_enable_io(dev, SYS_RES_MEMORY); 2365135048Swpaul 2366135048Swpaul /* reinitialize interface if necessary */ 2367135048Swpaul if (ifp->if_flags & IFF_UP) 2368135048Swpaul vge_init(sc); 2369135048Swpaul 2370135048Swpaul sc->suspended = 0; 2371135048Swpaul 2372135048Swpaul return (0); 2373135048Swpaul} 2374135048Swpaul 2375135048Swpaul/* 2376135048Swpaul * Stop all chip I/O so that the kernel's probe routines don't 2377135048Swpaul * get confused by errant DMAs when rebooting. 2378135048Swpaul */ 2379173839Syongaristatic int 2380135048Swpaulvge_shutdown(dev) 2381135048Swpaul device_t dev; 2382135048Swpaul{ 2383135048Swpaul struct vge_softc *sc; 2384135048Swpaul 2385135048Swpaul sc = device_get_softc(dev); 2386135048Swpaul 2387135048Swpaul vge_stop(sc); 2388173839Syongari 2389173839Syongari return (0); 2390135048Swpaul} 2391