if_vge.c revision 148654
1139749Simp/*- 2135048Swpaul * Copyright (c) 2004 3135048Swpaul * Bill Paul <wpaul@windriver.com>. All rights reserved. 4135048Swpaul * 5135048Swpaul * Redistribution and use in source and binary forms, with or without 6135048Swpaul * modification, are permitted provided that the following conditions 7135048Swpaul * are met: 8135048Swpaul * 1. Redistributions of source code must retain the above copyright 9135048Swpaul * notice, this list of conditions and the following disclaimer. 10135048Swpaul * 2. Redistributions in binary form must reproduce the above copyright 11135048Swpaul * notice, this list of conditions and the following disclaimer in the 12135048Swpaul * documentation and/or other materials provided with the distribution. 13135048Swpaul * 3. All advertising materials mentioning features or use of this software 14135048Swpaul * must display the following acknowledgement: 15135048Swpaul * This product includes software developed by Bill Paul. 16135048Swpaul * 4. Neither the name of the author nor the names of any co-contributors 17135048Swpaul * may be used to endorse or promote products derived from this software 18135048Swpaul * without specific prior written permission. 19135048Swpaul * 20135048Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21135048Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22135048Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23135048Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24135048Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25135048Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26135048Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27135048Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28135048Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29135048Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30135048Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 31135048Swpaul */ 32135048Swpaul 33135048Swpaul#include <sys/cdefs.h> 34135048Swpaul__FBSDID("$FreeBSD: head/sys/dev/vge/if_vge.c 148654 2005-08-03 00:18:35Z rwatson $"); 35135048Swpaul 36135048Swpaul/* 37135048Swpaul * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 38135048Swpaul * 39135048Swpaul * Written by Bill Paul <wpaul@windriver.com> 40135048Swpaul * Senior Networking Software Engineer 41135048Swpaul * Wind River Systems 42135048Swpaul */ 43135048Swpaul 44135048Swpaul/* 45135048Swpaul * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 46135048Swpaul * combines a tri-speed ethernet MAC and PHY, with the following 47135048Swpaul * features: 48135048Swpaul * 49135048Swpaul * o Jumbo frame support up to 16K 50135048Swpaul * o Transmit and receive flow control 51135048Swpaul * o IPv4 checksum offload 52135048Swpaul * o VLAN tag insertion and stripping 53135048Swpaul * o TCP large send 54135048Swpaul * o 64-bit multicast hash table filter 55135048Swpaul * o 64 entry CAM filter 56135048Swpaul * o 16K RX FIFO and 48K TX FIFO memory 57135048Swpaul * o Interrupt moderation 58135048Swpaul * 59135048Swpaul * The VT6122 supports up to four transmit DMA queues. The descriptors 60135048Swpaul * in the transmit ring can address up to 7 data fragments; frames which 61135048Swpaul * span more than 7 data buffers must be coalesced, but in general the 62135048Swpaul * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 63135048Swpaul * long. The receive descriptors address only a single buffer. 64135048Swpaul * 65135048Swpaul * There are two peculiar design issues with the VT6122. One is that 66135048Swpaul * receive data buffers must be aligned on a 32-bit boundary. This is 67135048Swpaul * not a problem where the VT6122 is used as a LOM device in x86-based 68135048Swpaul * systems, but on architectures that generate unaligned access traps, we 69135048Swpaul * have to do some copying. 70135048Swpaul * 71135048Swpaul * The other issue has to do with the way 64-bit addresses are handled. 72135048Swpaul * The DMA descriptors only allow you to specify 48 bits of addressing 73135048Swpaul * information. The remaining 16 bits are specified using one of the 74135048Swpaul * I/O registers. If you only have a 32-bit system, then this isn't 75135048Swpaul * an issue, but if you have a 64-bit system and more than 4GB of 76135048Swpaul * memory, you must have to make sure your network data buffers reside 77135048Swpaul * in the same 48-bit 'segment.' 78135048Swpaul * 79135048Swpaul * Special thanks to Ryan Fu at VIA Networking for providing documentation 80135048Swpaul * and sample NICs for testing. 81135048Swpaul */ 82135048Swpaul 83135048Swpaul#include <sys/param.h> 84135048Swpaul#include <sys/endian.h> 85135048Swpaul#include <sys/systm.h> 86135048Swpaul#include <sys/sockio.h> 87135048Swpaul#include <sys/mbuf.h> 88135048Swpaul#include <sys/malloc.h> 89135048Swpaul#include <sys/module.h> 90135048Swpaul#include <sys/kernel.h> 91135048Swpaul#include <sys/socket.h> 92135048Swpaul#include <sys/taskqueue.h> 93135048Swpaul 94135048Swpaul#include <net/if.h> 95135048Swpaul#include <net/if_arp.h> 96135048Swpaul#include <net/ethernet.h> 97135048Swpaul#include <net/if_dl.h> 98135048Swpaul#include <net/if_media.h> 99147256Sbrooks#include <net/if_types.h> 100135048Swpaul#include <net/if_vlan_var.h> 101135048Swpaul 102135048Swpaul#include <net/bpf.h> 103135048Swpaul 104135048Swpaul#include <machine/bus.h> 105135048Swpaul#include <machine/resource.h> 106135048Swpaul#include <sys/bus.h> 107135048Swpaul#include <sys/rman.h> 108135048Swpaul 109135048Swpaul#include <dev/mii/mii.h> 110135048Swpaul#include <dev/mii/miivar.h> 111135048Swpaul 112135048Swpaul#include <dev/pci/pcireg.h> 113135048Swpaul#include <dev/pci/pcivar.h> 114135048Swpaul 115135048SwpaulMODULE_DEPEND(vge, pci, 1, 1, 1); 116135048SwpaulMODULE_DEPEND(vge, ether, 1, 1, 1); 117135048SwpaulMODULE_DEPEND(vge, miibus, 1, 1, 1); 118135048Swpaul 119135048Swpaul/* "controller miibus0" required. See GENERIC if you get errors here. */ 120135048Swpaul#include "miibus_if.h" 121135048Swpaul 122135048Swpaul#include <dev/vge/if_vgereg.h> 123135048Swpaul#include <dev/vge/if_vgevar.h> 124135048Swpaul 125135048Swpaul#define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 126135048Swpaul 127135048Swpaul/* 128135048Swpaul * Various supported device vendors/types and their names. 129135048Swpaul */ 130135048Swpaulstatic struct vge_type vge_devs[] = { 131135048Swpaul { VIA_VENDORID, VIA_DEVICEID_61XX, 132135048Swpaul "VIA Networking Gigabit Ethernet" }, 133135048Swpaul { 0, 0, NULL } 134135048Swpaul}; 135135048Swpaul 136135048Swpaulstatic int vge_probe (device_t); 137135048Swpaulstatic int vge_attach (device_t); 138135048Swpaulstatic int vge_detach (device_t); 139135048Swpaul 140135048Swpaulstatic int vge_encap (struct vge_softc *, struct mbuf *, int); 141135048Swpaul 142135048Swpaulstatic void vge_dma_map_addr (void *, bus_dma_segment_t *, int, int); 143135048Swpaulstatic void vge_dma_map_rx_desc (void *, bus_dma_segment_t *, int, 144135048Swpaul bus_size_t, int); 145135048Swpaulstatic void vge_dma_map_tx_desc (void *, bus_dma_segment_t *, int, 146135048Swpaul bus_size_t, int); 147135048Swpaulstatic int vge_allocmem (device_t, struct vge_softc *); 148135048Swpaulstatic int vge_newbuf (struct vge_softc *, int, struct mbuf *); 149135048Swpaulstatic int vge_rx_list_init (struct vge_softc *); 150135048Swpaulstatic int vge_tx_list_init (struct vge_softc *); 151135048Swpaul#ifdef VGE_FIXUP_RX 152135048Swpaulstatic __inline void vge_fixup_rx 153135048Swpaul (struct mbuf *); 154135048Swpaul#endif 155135048Swpaulstatic void vge_rxeof (struct vge_softc *); 156135048Swpaulstatic void vge_txeof (struct vge_softc *); 157135048Swpaulstatic void vge_intr (void *); 158135048Swpaulstatic void vge_tick (void *); 159135048Swpaulstatic void vge_tx_task (void *, int); 160135048Swpaulstatic void vge_start (struct ifnet *); 161135048Swpaulstatic int vge_ioctl (struct ifnet *, u_long, caddr_t); 162135048Swpaulstatic void vge_init (void *); 163135048Swpaulstatic void vge_stop (struct vge_softc *); 164135048Swpaulstatic void vge_watchdog (struct ifnet *); 165135048Swpaulstatic int vge_suspend (device_t); 166135048Swpaulstatic int vge_resume (device_t); 167135048Swpaulstatic void vge_shutdown (device_t); 168135048Swpaulstatic int vge_ifmedia_upd (struct ifnet *); 169135048Swpaulstatic void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 170135048Swpaul 171145520Swpaul#ifdef VGE_EEPROM 172135048Swpaulstatic void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 173145520Swpaul#endif 174135048Swpaulstatic void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 175135048Swpaul 176135048Swpaulstatic void vge_miipoll_start (struct vge_softc *); 177135048Swpaulstatic void vge_miipoll_stop (struct vge_softc *); 178135048Swpaulstatic int vge_miibus_readreg (device_t, int, int); 179135048Swpaulstatic int vge_miibus_writereg (device_t, int, int, int); 180135048Swpaulstatic void vge_miibus_statchg (device_t); 181135048Swpaul 182135048Swpaulstatic void vge_cam_clear (struct vge_softc *); 183135048Swpaulstatic int vge_cam_set (struct vge_softc *, uint8_t *); 184135048Swpaul#if __FreeBSD_version < 502113 185135048Swpaulstatic uint32_t vge_mchash (uint8_t *); 186135048Swpaul#endif 187135048Swpaulstatic void vge_setmulti (struct vge_softc *); 188135048Swpaulstatic void vge_reset (struct vge_softc *); 189135048Swpaul 190135048Swpaul#define VGE_PCI_LOIO 0x10 191135048Swpaul#define VGE_PCI_LOMEM 0x14 192135048Swpaul 193135048Swpaulstatic device_method_t vge_methods[] = { 194135048Swpaul /* Device interface */ 195135048Swpaul DEVMETHOD(device_probe, vge_probe), 196135048Swpaul DEVMETHOD(device_attach, vge_attach), 197135048Swpaul DEVMETHOD(device_detach, vge_detach), 198135048Swpaul DEVMETHOD(device_suspend, vge_suspend), 199135048Swpaul DEVMETHOD(device_resume, vge_resume), 200135048Swpaul DEVMETHOD(device_shutdown, vge_shutdown), 201135048Swpaul 202135048Swpaul /* bus interface */ 203135048Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 204135048Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 205135048Swpaul 206135048Swpaul /* MII interface */ 207135048Swpaul DEVMETHOD(miibus_readreg, vge_miibus_readreg), 208135048Swpaul DEVMETHOD(miibus_writereg, vge_miibus_writereg), 209135048Swpaul DEVMETHOD(miibus_statchg, vge_miibus_statchg), 210135048Swpaul 211135048Swpaul { 0, 0 } 212135048Swpaul}; 213135048Swpaul 214135048Swpaulstatic driver_t vge_driver = { 215135048Swpaul "vge", 216135048Swpaul vge_methods, 217135048Swpaul sizeof(struct vge_softc) 218135048Swpaul}; 219135048Swpaul 220135048Swpaulstatic devclass_t vge_devclass; 221135048Swpaul 222135048SwpaulDRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0); 223135048SwpaulDRIVER_MODULE(vge, cardbus, vge_driver, vge_devclass, 0, 0); 224135048SwpaulDRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0); 225135048Swpaul 226145520Swpaul#ifdef VGE_EEPROM 227135048Swpaul/* 228135048Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 229135048Swpaul */ 230135048Swpaulstatic void 231135048Swpaulvge_eeprom_getword(sc, addr, dest) 232135048Swpaul struct vge_softc *sc; 233135048Swpaul int addr; 234135048Swpaul u_int16_t *dest; 235135048Swpaul{ 236135048Swpaul register int i; 237135048Swpaul u_int16_t word = 0; 238135048Swpaul 239135048Swpaul /* 240135048Swpaul * Enter EEPROM embedded programming mode. In order to 241135048Swpaul * access the EEPROM at all, we first have to set the 242135048Swpaul * EELOAD bit in the CHIPCFG2 register. 243135048Swpaul */ 244135048Swpaul CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 245135048Swpaul CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 246135048Swpaul 247135048Swpaul /* Select the address of the word we want to read */ 248135048Swpaul CSR_WRITE_1(sc, VGE_EEADDR, addr); 249135048Swpaul 250135048Swpaul /* Issue read command */ 251135048Swpaul CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 252135048Swpaul 253135048Swpaul /* Wait for the done bit to be set. */ 254135048Swpaul for (i = 0; i < VGE_TIMEOUT; i++) { 255135048Swpaul if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 256135048Swpaul break; 257135048Swpaul } 258135048Swpaul 259135048Swpaul if (i == VGE_TIMEOUT) { 260135048Swpaul device_printf(sc->vge_dev, "EEPROM read timed out\n"); 261135048Swpaul *dest = 0; 262135048Swpaul return; 263135048Swpaul } 264135048Swpaul 265135048Swpaul /* Read the result */ 266135048Swpaul word = CSR_READ_2(sc, VGE_EERDDAT); 267135048Swpaul 268135048Swpaul /* Turn off EEPROM access mode. */ 269135048Swpaul CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 270135048Swpaul CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 271135048Swpaul 272135048Swpaul *dest = word; 273135048Swpaul 274135048Swpaul return; 275135048Swpaul} 276145520Swpaul#endif 277135048Swpaul 278135048Swpaul/* 279135048Swpaul * Read a sequence of words from the EEPROM. 280135048Swpaul */ 281135048Swpaulstatic void 282135048Swpaulvge_read_eeprom(sc, dest, off, cnt, swap) 283135048Swpaul struct vge_softc *sc; 284135048Swpaul caddr_t dest; 285135048Swpaul int off; 286135048Swpaul int cnt; 287135048Swpaul int swap; 288135048Swpaul{ 289135048Swpaul int i; 290145520Swpaul#ifdef VGE_EEPROM 291135048Swpaul u_int16_t word = 0, *ptr; 292135048Swpaul 293135048Swpaul for (i = 0; i < cnt; i++) { 294135048Swpaul vge_eeprom_getword(sc, off + i, &word); 295135048Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 296135048Swpaul if (swap) 297135048Swpaul *ptr = ntohs(word); 298135048Swpaul else 299135048Swpaul *ptr = word; 300135048Swpaul } 301145520Swpaul#else 302145520Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 303145520Swpaul dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 304145520Swpaul#endif 305135048Swpaul} 306135048Swpaul 307135048Swpaulstatic void 308135048Swpaulvge_miipoll_stop(sc) 309135048Swpaul struct vge_softc *sc; 310135048Swpaul{ 311135048Swpaul int i; 312135048Swpaul 313135048Swpaul CSR_WRITE_1(sc, VGE_MIICMD, 0); 314135048Swpaul 315135048Swpaul for (i = 0; i < VGE_TIMEOUT; i++) { 316135048Swpaul DELAY(1); 317135048Swpaul if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 318135048Swpaul break; 319135048Swpaul } 320135048Swpaul 321135048Swpaul if (i == VGE_TIMEOUT) 322135048Swpaul device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 323135048Swpaul 324135048Swpaul return; 325135048Swpaul} 326135048Swpaul 327135048Swpaulstatic void 328135048Swpaulvge_miipoll_start(sc) 329135048Swpaul struct vge_softc *sc; 330135048Swpaul{ 331135048Swpaul int i; 332135048Swpaul 333135048Swpaul /* First, make sure we're idle. */ 334135048Swpaul 335135048Swpaul CSR_WRITE_1(sc, VGE_MIICMD, 0); 336135048Swpaul CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 337135048Swpaul 338135048Swpaul for (i = 0; i < VGE_TIMEOUT; i++) { 339135048Swpaul DELAY(1); 340135048Swpaul if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 341135048Swpaul break; 342135048Swpaul } 343135048Swpaul 344135048Swpaul if (i == VGE_TIMEOUT) { 345135048Swpaul device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 346135048Swpaul return; 347135048Swpaul } 348135048Swpaul 349135048Swpaul /* Now enable auto poll mode. */ 350135048Swpaul 351135048Swpaul CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 352135048Swpaul 353135048Swpaul /* And make sure it started. */ 354135048Swpaul 355135048Swpaul for (i = 0; i < VGE_TIMEOUT; i++) { 356135048Swpaul DELAY(1); 357135048Swpaul if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 358135048Swpaul break; 359135048Swpaul } 360135048Swpaul 361135048Swpaul if (i == VGE_TIMEOUT) 362135048Swpaul device_printf(sc->vge_dev, "failed to start MII autopoll\n"); 363135048Swpaul 364135048Swpaul return; 365135048Swpaul} 366135048Swpaul 367135048Swpaulstatic int 368135048Swpaulvge_miibus_readreg(dev, phy, reg) 369135048Swpaul device_t dev; 370135048Swpaul int phy, reg; 371135048Swpaul{ 372135048Swpaul struct vge_softc *sc; 373135048Swpaul int i; 374135048Swpaul u_int16_t rval = 0; 375135048Swpaul 376135048Swpaul sc = device_get_softc(dev); 377135048Swpaul 378135048Swpaul if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 379135048Swpaul return(0); 380135048Swpaul 381135048Swpaul VGE_LOCK(sc); 382135048Swpaul vge_miipoll_stop(sc); 383135048Swpaul 384135048Swpaul /* Specify the register we want to read. */ 385135048Swpaul CSR_WRITE_1(sc, VGE_MIIADDR, reg); 386135048Swpaul 387135048Swpaul /* Issue read command. */ 388135048Swpaul CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 389135048Swpaul 390135048Swpaul /* Wait for the read command bit to self-clear. */ 391135048Swpaul for (i = 0; i < VGE_TIMEOUT; i++) { 392135048Swpaul DELAY(1); 393135048Swpaul if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 394135048Swpaul break; 395135048Swpaul } 396135048Swpaul 397135048Swpaul if (i == VGE_TIMEOUT) 398135048Swpaul device_printf(sc->vge_dev, "MII read timed out\n"); 399135048Swpaul else 400135048Swpaul rval = CSR_READ_2(sc, VGE_MIIDATA); 401135048Swpaul 402135048Swpaul vge_miipoll_start(sc); 403135048Swpaul VGE_UNLOCK(sc); 404135048Swpaul 405135048Swpaul return (rval); 406135048Swpaul} 407135048Swpaul 408135048Swpaulstatic int 409135048Swpaulvge_miibus_writereg(dev, phy, reg, data) 410135048Swpaul device_t dev; 411135048Swpaul int phy, reg, data; 412135048Swpaul{ 413135048Swpaul struct vge_softc *sc; 414135048Swpaul int i, rval = 0; 415135048Swpaul 416135048Swpaul sc = device_get_softc(dev); 417135048Swpaul 418135048Swpaul if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 419135048Swpaul return(0); 420135048Swpaul 421135048Swpaul VGE_LOCK(sc); 422135048Swpaul vge_miipoll_stop(sc); 423135048Swpaul 424135048Swpaul /* Specify the register we want to write. */ 425135048Swpaul CSR_WRITE_1(sc, VGE_MIIADDR, reg); 426135048Swpaul 427135048Swpaul /* Specify the data we want to write. */ 428135048Swpaul CSR_WRITE_2(sc, VGE_MIIDATA, data); 429135048Swpaul 430135048Swpaul /* Issue write command. */ 431135048Swpaul CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 432135048Swpaul 433135048Swpaul /* Wait for the write command bit to self-clear. */ 434135048Swpaul for (i = 0; i < VGE_TIMEOUT; i++) { 435135048Swpaul DELAY(1); 436135048Swpaul if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 437135048Swpaul break; 438135048Swpaul } 439135048Swpaul 440135048Swpaul if (i == VGE_TIMEOUT) { 441135048Swpaul device_printf(sc->vge_dev, "MII write timed out\n"); 442135048Swpaul rval = EIO; 443135048Swpaul } 444135048Swpaul 445135048Swpaul vge_miipoll_start(sc); 446135048Swpaul VGE_UNLOCK(sc); 447135048Swpaul 448135048Swpaul return (rval); 449135048Swpaul} 450135048Swpaul 451135048Swpaulstatic void 452135048Swpaulvge_cam_clear(sc) 453135048Swpaul struct vge_softc *sc; 454135048Swpaul{ 455135048Swpaul int i; 456135048Swpaul 457135048Swpaul /* 458135048Swpaul * Turn off all the mask bits. This tells the chip 459135048Swpaul * that none of the entries in the CAM filter are valid. 460135048Swpaul * desired entries will be enabled as we fill the filter in. 461135048Swpaul */ 462135048Swpaul 463135048Swpaul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 464135048Swpaul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 465135048Swpaul CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 466135048Swpaul for (i = 0; i < 8; i++) 467135048Swpaul CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 468135048Swpaul 469135048Swpaul /* Clear the VLAN filter too. */ 470135048Swpaul 471135048Swpaul CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 472135048Swpaul for (i = 0; i < 8; i++) 473135048Swpaul CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 474135048Swpaul 475135048Swpaul CSR_WRITE_1(sc, VGE_CAMADDR, 0); 476135048Swpaul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 477135048Swpaul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 478135048Swpaul 479135048Swpaul sc->vge_camidx = 0; 480135048Swpaul 481135048Swpaul return; 482135048Swpaul} 483135048Swpaul 484135048Swpaulstatic int 485135048Swpaulvge_cam_set(sc, addr) 486135048Swpaul struct vge_softc *sc; 487135048Swpaul uint8_t *addr; 488135048Swpaul{ 489135048Swpaul int i, error = 0; 490135048Swpaul 491135048Swpaul if (sc->vge_camidx == VGE_CAM_MAXADDRS) 492135048Swpaul return(ENOSPC); 493135048Swpaul 494135048Swpaul /* Select the CAM data page. */ 495135048Swpaul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 496135048Swpaul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 497135048Swpaul 498135048Swpaul /* Set the filter entry we want to update and enable writing. */ 499135048Swpaul CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 500135048Swpaul 501135048Swpaul /* Write the address to the CAM registers */ 502135048Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 503135048Swpaul CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 504135048Swpaul 505135048Swpaul /* Issue a write command. */ 506135048Swpaul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 507135048Swpaul 508135048Swpaul /* Wake for it to clear. */ 509135048Swpaul for (i = 0; i < VGE_TIMEOUT; i++) { 510135048Swpaul DELAY(1); 511135048Swpaul if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 512135048Swpaul break; 513135048Swpaul } 514135048Swpaul 515135048Swpaul if (i == VGE_TIMEOUT) { 516135048Swpaul device_printf(sc->vge_dev, "setting CAM filter failed\n"); 517135048Swpaul error = EIO; 518135048Swpaul goto fail; 519135048Swpaul } 520135048Swpaul 521135048Swpaul /* Select the CAM mask page. */ 522135048Swpaul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 523135048Swpaul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 524135048Swpaul 525135048Swpaul /* Set the mask bit that enables this filter. */ 526135048Swpaul CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 527135048Swpaul 1<<(sc->vge_camidx & 7)); 528135048Swpaul 529135048Swpaul sc->vge_camidx++; 530135048Swpaul 531135048Swpaulfail: 532135048Swpaul /* Turn off access to CAM. */ 533135048Swpaul CSR_WRITE_1(sc, VGE_CAMADDR, 0); 534135048Swpaul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 535135048Swpaul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 536135048Swpaul 537135048Swpaul return (error); 538135048Swpaul} 539135048Swpaul 540135048Swpaul#if __FreeBSD_version < 502113 541135048Swpaulstatic uint32_t 542135048Swpaulvge_mchash(addr) 543135048Swpaul uint8_t *addr; 544135048Swpaul{ 545135048Swpaul uint32_t crc, carry; 546135048Swpaul int idx, bit; 547135048Swpaul uint8_t data; 548135048Swpaul 549135048Swpaul /* Compute CRC for the address value. */ 550135048Swpaul crc = 0xFFFFFFFF; /* initial value */ 551135048Swpaul 552135048Swpaul for (idx = 0; idx < 6; idx++) { 553135048Swpaul for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 554135048Swpaul carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 555135048Swpaul crc <<= 1; 556135048Swpaul if (carry) 557135048Swpaul crc = (crc ^ 0x04c11db6) | carry; 558135048Swpaul } 559135048Swpaul } 560135048Swpaul 561135048Swpaul return(crc); 562135048Swpaul} 563135048Swpaul#endif 564135048Swpaul 565135048Swpaul/* 566135048Swpaul * Program the multicast filter. We use the 64-entry CAM filter 567135048Swpaul * for perfect filtering. If there's more than 64 multicast addresses, 568135048Swpaul * we use the hash filter insted. 569135048Swpaul */ 570135048Swpaulstatic void 571135048Swpaulvge_setmulti(sc) 572135048Swpaul struct vge_softc *sc; 573135048Swpaul{ 574135048Swpaul struct ifnet *ifp; 575135048Swpaul int error = 0/*, h = 0*/; 576135048Swpaul struct ifmultiaddr *ifma; 577135048Swpaul u_int32_t h, hashes[2] = { 0, 0 }; 578135048Swpaul 579147256Sbrooks ifp = sc->vge_ifp; 580135048Swpaul 581135048Swpaul /* First, zot all the multicast entries. */ 582135048Swpaul vge_cam_clear(sc); 583135048Swpaul CSR_WRITE_4(sc, VGE_MAR0, 0); 584135048Swpaul CSR_WRITE_4(sc, VGE_MAR1, 0); 585135048Swpaul 586135048Swpaul /* 587135048Swpaul * If the user wants allmulti or promisc mode, enable reception 588135048Swpaul * of all multicast frames. 589135048Swpaul */ 590135048Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 591135048Swpaul CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 592135048Swpaul CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 593135048Swpaul return; 594135048Swpaul } 595135048Swpaul 596135048Swpaul /* Now program new ones */ 597148654Srwatson IF_ADDR_LOCK(ifp); 598135048Swpaul TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 599135048Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 600135048Swpaul continue; 601135048Swpaul error = vge_cam_set(sc, 602135048Swpaul LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 603135048Swpaul if (error) 604135048Swpaul break; 605135048Swpaul } 606135048Swpaul 607135048Swpaul /* If there were too many addresses, use the hash filter. */ 608135048Swpaul if (error) { 609135048Swpaul vge_cam_clear(sc); 610135048Swpaul 611135048Swpaul TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 612135048Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 613135048Swpaul continue; 614135048Swpaul#if __FreeBSD_version < 502113 615135048Swpaul h = vge_mchash(LLADDR((struct sockaddr_dl *) 616135048Swpaul ifma->ifma_addr)) >> 26; 617135048Swpaul#else 618135048Swpaul h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 619135048Swpaul ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 620135048Swpaul#endif 621135048Swpaul if (h < 32) 622135048Swpaul hashes[0] |= (1 << h); 623135048Swpaul else 624135048Swpaul hashes[1] |= (1 << (h - 32)); 625135048Swpaul } 626135048Swpaul 627135048Swpaul CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 628135048Swpaul CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 629135048Swpaul } 630148654Srwatson IF_ADDR_UNLOCK(ifp); 631135048Swpaul 632135048Swpaul return; 633135048Swpaul} 634135048Swpaul 635135048Swpaulstatic void 636135048Swpaulvge_reset(sc) 637135048Swpaul struct vge_softc *sc; 638135048Swpaul{ 639135048Swpaul register int i; 640135048Swpaul 641135048Swpaul CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 642135048Swpaul 643135048Swpaul for (i = 0; i < VGE_TIMEOUT; i++) { 644135048Swpaul DELAY(5); 645135048Swpaul if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 646135048Swpaul break; 647135048Swpaul } 648135048Swpaul 649135048Swpaul if (i == VGE_TIMEOUT) { 650135048Swpaul device_printf(sc->vge_dev, "soft reset timed out"); 651135048Swpaul CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 652135048Swpaul DELAY(2000); 653135048Swpaul } 654135048Swpaul 655135048Swpaul DELAY(5000); 656135048Swpaul 657135048Swpaul CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 658135048Swpaul 659135048Swpaul for (i = 0; i < VGE_TIMEOUT; i++) { 660135048Swpaul DELAY(5); 661135048Swpaul if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 662135048Swpaul break; 663135048Swpaul } 664135048Swpaul 665135048Swpaul if (i == VGE_TIMEOUT) { 666135048Swpaul device_printf(sc->vge_dev, "EEPROM reload timed out\n"); 667135048Swpaul return; 668135048Swpaul } 669135048Swpaul 670135048Swpaul CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 671135048Swpaul 672135048Swpaul return; 673135048Swpaul} 674135048Swpaul 675135048Swpaul/* 676135048Swpaul * Probe for a VIA gigabit chip. Check the PCI vendor and device 677135048Swpaul * IDs against our list and return a device name if we find a match. 678135048Swpaul */ 679135048Swpaulstatic int 680135048Swpaulvge_probe(dev) 681135048Swpaul device_t dev; 682135048Swpaul{ 683135048Swpaul struct vge_type *t; 684135048Swpaul struct vge_softc *sc; 685135048Swpaul 686135048Swpaul t = vge_devs; 687135048Swpaul sc = device_get_softc(dev); 688135048Swpaul 689135048Swpaul while (t->vge_name != NULL) { 690135048Swpaul if ((pci_get_vendor(dev) == t->vge_vid) && 691135048Swpaul (pci_get_device(dev) == t->vge_did)) { 692135048Swpaul device_set_desc(dev, t->vge_name); 693142880Simp return (BUS_PROBE_DEFAULT); 694135048Swpaul } 695135048Swpaul t++; 696135048Swpaul } 697135048Swpaul 698135048Swpaul return (ENXIO); 699135048Swpaul} 700135048Swpaul 701135048Swpaulstatic void 702135048Swpaulvge_dma_map_rx_desc(arg, segs, nseg, mapsize, error) 703135048Swpaul void *arg; 704135048Swpaul bus_dma_segment_t *segs; 705135048Swpaul int nseg; 706135048Swpaul bus_size_t mapsize; 707135048Swpaul int error; 708135048Swpaul{ 709135048Swpaul 710135048Swpaul struct vge_dmaload_arg *ctx; 711135048Swpaul struct vge_rx_desc *d = NULL; 712135048Swpaul 713135048Swpaul if (error) 714135048Swpaul return; 715135048Swpaul 716135048Swpaul ctx = arg; 717135048Swpaul 718135048Swpaul /* Signal error to caller if there's too many segments */ 719135048Swpaul if (nseg > ctx->vge_maxsegs) { 720135048Swpaul ctx->vge_maxsegs = 0; 721135048Swpaul return; 722135048Swpaul } 723135048Swpaul 724135048Swpaul /* 725135048Swpaul * Map the segment array into descriptors. 726135048Swpaul */ 727135048Swpaul 728135048Swpaul d = &ctx->sc->vge_ldata.vge_rx_list[ctx->vge_idx]; 729135048Swpaul 730135048Swpaul /* If this descriptor is still owned by the chip, bail. */ 731135048Swpaul 732135048Swpaul if (le32toh(d->vge_sts) & VGE_RDSTS_OWN) { 733135048Swpaul device_printf(ctx->sc->vge_dev, 734135048Swpaul "tried to map busy descriptor\n"); 735135048Swpaul ctx->vge_maxsegs = 0; 736135048Swpaul return; 737135048Swpaul } 738135048Swpaul 739135048Swpaul d->vge_buflen = htole16(VGE_BUFLEN(segs[0].ds_len) | VGE_RXDESC_I); 740135048Swpaul d->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 741135048Swpaul d->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 742135048Swpaul d->vge_sts = 0; 743135048Swpaul d->vge_ctl = 0; 744135048Swpaul 745135048Swpaul ctx->vge_maxsegs = 1; 746135048Swpaul 747135048Swpaul return; 748135048Swpaul} 749135048Swpaul 750135048Swpaulstatic void 751135048Swpaulvge_dma_map_tx_desc(arg, segs, nseg, mapsize, error) 752135048Swpaul void *arg; 753135048Swpaul bus_dma_segment_t *segs; 754135048Swpaul int nseg; 755135048Swpaul bus_size_t mapsize; 756135048Swpaul int error; 757135048Swpaul{ 758135048Swpaul struct vge_dmaload_arg *ctx; 759135048Swpaul struct vge_tx_desc *d = NULL; 760135048Swpaul struct vge_tx_frag *f; 761135048Swpaul int i = 0; 762135048Swpaul 763135048Swpaul if (error) 764135048Swpaul return; 765135048Swpaul 766135048Swpaul ctx = arg; 767135048Swpaul 768135048Swpaul /* Signal error to caller if there's too many segments */ 769135048Swpaul if (nseg > ctx->vge_maxsegs) { 770135048Swpaul ctx->vge_maxsegs = 0; 771135048Swpaul return; 772135048Swpaul } 773135048Swpaul 774135048Swpaul /* Map the segment array into descriptors. */ 775135048Swpaul 776135048Swpaul d = &ctx->sc->vge_ldata.vge_tx_list[ctx->vge_idx]; 777135048Swpaul 778135048Swpaul /* If this descriptor is still owned by the chip, bail. */ 779135048Swpaul 780135048Swpaul if (le32toh(d->vge_sts) & VGE_TDSTS_OWN) { 781135048Swpaul ctx->vge_maxsegs = 0; 782135048Swpaul return; 783135048Swpaul } 784135048Swpaul 785135048Swpaul for (i = 0; i < nseg; i++) { 786135048Swpaul f = &d->vge_frag[i]; 787135048Swpaul f->vge_buflen = htole16(VGE_BUFLEN(segs[i].ds_len)); 788135048Swpaul f->vge_addrlo = htole32(VGE_ADDR_LO(segs[i].ds_addr)); 789135048Swpaul f->vge_addrhi = htole16(VGE_ADDR_HI(segs[i].ds_addr) & 0xFFFF); 790135048Swpaul } 791135048Swpaul 792135048Swpaul /* Argh. This chip does not autopad short frames */ 793135048Swpaul 794135048Swpaul if (ctx->vge_m0->m_pkthdr.len < VGE_MIN_FRAMELEN) { 795135048Swpaul f = &d->vge_frag[i]; 796135048Swpaul f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 797135048Swpaul ctx->vge_m0->m_pkthdr.len)); 798135048Swpaul f->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 799135048Swpaul f->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 800135048Swpaul ctx->vge_m0->m_pkthdr.len = VGE_MIN_FRAMELEN; 801135048Swpaul i++; 802135048Swpaul } 803135048Swpaul 804135048Swpaul /* 805135048Swpaul * When telling the chip how many segments there are, we 806135048Swpaul * must use nsegs + 1 instead of just nsegs. Darned if I 807135048Swpaul * know why. 808135048Swpaul */ 809135048Swpaul i++; 810135048Swpaul 811135048Swpaul d->vge_sts = ctx->vge_m0->m_pkthdr.len << 16; 812135048Swpaul d->vge_ctl = ctx->vge_flags|(i << 28)|VGE_TD_LS_NORM; 813135048Swpaul 814135048Swpaul if (ctx->vge_m0->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 815135048Swpaul d->vge_ctl |= VGE_TDCTL_JUMBO; 816135048Swpaul 817135048Swpaul ctx->vge_maxsegs = nseg; 818135048Swpaul 819135048Swpaul return; 820135048Swpaul} 821135048Swpaul 822135048Swpaul/* 823135048Swpaul * Map a single buffer address. 824135048Swpaul */ 825135048Swpaul 826135048Swpaulstatic void 827135048Swpaulvge_dma_map_addr(arg, segs, nseg, error) 828135048Swpaul void *arg; 829135048Swpaul bus_dma_segment_t *segs; 830135048Swpaul int nseg; 831135048Swpaul int error; 832135048Swpaul{ 833135048Swpaul bus_addr_t *addr; 834135048Swpaul 835135048Swpaul if (error) 836135048Swpaul return; 837135048Swpaul 838135048Swpaul KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 839135048Swpaul addr = arg; 840135048Swpaul *addr = segs->ds_addr; 841135048Swpaul 842135048Swpaul return; 843135048Swpaul} 844135048Swpaul 845135048Swpaulstatic int 846135048Swpaulvge_allocmem(dev, sc) 847135048Swpaul device_t dev; 848135048Swpaul struct vge_softc *sc; 849135048Swpaul{ 850135048Swpaul int error; 851135048Swpaul int nseg; 852135048Swpaul int i; 853135048Swpaul 854135048Swpaul /* 855135048Swpaul * Allocate map for RX mbufs. 856135048Swpaul */ 857135048Swpaul nseg = 32; 858135048Swpaul error = bus_dma_tag_create(sc->vge_parent_tag, ETHER_ALIGN, 0, 859135048Swpaul BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 860135048Swpaul NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 861135048Swpaul NULL, NULL, &sc->vge_ldata.vge_mtag); 862135048Swpaul if (error) { 863135048Swpaul device_printf(dev, "could not allocate dma tag\n"); 864135048Swpaul return (ENOMEM); 865135048Swpaul } 866135048Swpaul 867135048Swpaul /* 868135048Swpaul * Allocate map for TX descriptor list. 869135048Swpaul */ 870135048Swpaul error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 871135048Swpaul 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 872135048Swpaul NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 873135048Swpaul NULL, NULL, &sc->vge_ldata.vge_tx_list_tag); 874135048Swpaul if (error) { 875135048Swpaul device_printf(dev, "could not allocate dma tag\n"); 876135048Swpaul return (ENOMEM); 877135048Swpaul } 878135048Swpaul 879135048Swpaul /* Allocate DMA'able memory for the TX ring */ 880135048Swpaul 881135048Swpaul error = bus_dmamem_alloc(sc->vge_ldata.vge_tx_list_tag, 882135048Swpaul (void **)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 883135048Swpaul &sc->vge_ldata.vge_tx_list_map); 884135048Swpaul if (error) 885135048Swpaul return (ENOMEM); 886135048Swpaul 887135048Swpaul /* Load the map for the TX ring. */ 888135048Swpaul 889135048Swpaul error = bus_dmamap_load(sc->vge_ldata.vge_tx_list_tag, 890135048Swpaul sc->vge_ldata.vge_tx_list_map, sc->vge_ldata.vge_tx_list, 891135048Swpaul VGE_TX_LIST_SZ, vge_dma_map_addr, 892135048Swpaul &sc->vge_ldata.vge_tx_list_addr, BUS_DMA_NOWAIT); 893135048Swpaul 894135048Swpaul /* Create DMA maps for TX buffers */ 895135048Swpaul 896135048Swpaul for (i = 0; i < VGE_TX_DESC_CNT; i++) { 897135048Swpaul error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 898135048Swpaul &sc->vge_ldata.vge_tx_dmamap[i]); 899135048Swpaul if (error) { 900135048Swpaul device_printf(dev, "can't create DMA map for TX\n"); 901135048Swpaul return (ENOMEM); 902135048Swpaul } 903135048Swpaul } 904135048Swpaul 905135048Swpaul /* 906135048Swpaul * Allocate map for RX descriptor list. 907135048Swpaul */ 908135048Swpaul error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 909135048Swpaul 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 910135048Swpaul NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 911135048Swpaul NULL, NULL, &sc->vge_ldata.vge_rx_list_tag); 912135048Swpaul if (error) { 913135048Swpaul device_printf(dev, "could not allocate dma tag\n"); 914135048Swpaul return (ENOMEM); 915135048Swpaul } 916135048Swpaul 917135048Swpaul /* Allocate DMA'able memory for the RX ring */ 918135048Swpaul 919135048Swpaul error = bus_dmamem_alloc(sc->vge_ldata.vge_rx_list_tag, 920135048Swpaul (void **)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 921135048Swpaul &sc->vge_ldata.vge_rx_list_map); 922135048Swpaul if (error) 923135048Swpaul return (ENOMEM); 924135048Swpaul 925135048Swpaul /* Load the map for the RX ring. */ 926135048Swpaul 927135048Swpaul error = bus_dmamap_load(sc->vge_ldata.vge_rx_list_tag, 928135048Swpaul sc->vge_ldata.vge_rx_list_map, sc->vge_ldata.vge_rx_list, 929135048Swpaul VGE_TX_LIST_SZ, vge_dma_map_addr, 930135048Swpaul &sc->vge_ldata.vge_rx_list_addr, BUS_DMA_NOWAIT); 931135048Swpaul 932135048Swpaul /* Create DMA maps for RX buffers */ 933135048Swpaul 934135048Swpaul for (i = 0; i < VGE_RX_DESC_CNT; i++) { 935135048Swpaul error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 936135048Swpaul &sc->vge_ldata.vge_rx_dmamap[i]); 937135048Swpaul if (error) { 938135048Swpaul device_printf(dev, "can't create DMA map for RX\n"); 939135048Swpaul return (ENOMEM); 940135048Swpaul } 941135048Swpaul } 942135048Swpaul 943135048Swpaul return (0); 944135048Swpaul} 945135048Swpaul 946135048Swpaul/* 947135048Swpaul * Attach the interface. Allocate softc structures, do ifmedia 948135048Swpaul * setup and ethernet/BPF attach. 949135048Swpaul */ 950135048Swpaulstatic int 951135048Swpaulvge_attach(dev) 952135048Swpaul device_t dev; 953135048Swpaul{ 954135048Swpaul u_char eaddr[ETHER_ADDR_LEN]; 955135048Swpaul struct vge_softc *sc; 956135048Swpaul struct ifnet *ifp; 957135048Swpaul int unit, error = 0, rid; 958135048Swpaul 959135048Swpaul sc = device_get_softc(dev); 960135048Swpaul unit = device_get_unit(dev); 961135048Swpaul sc->vge_dev = dev; 962135048Swpaul 963135048Swpaul mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 964135048Swpaul MTX_DEF | MTX_RECURSE); 965135048Swpaul /* 966135048Swpaul * Map control/status registers. 967135048Swpaul */ 968135048Swpaul pci_enable_busmaster(dev); 969135048Swpaul 970135048Swpaul rid = VGE_PCI_LOMEM; 971135048Swpaul sc->vge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 972135048Swpaul 0, ~0, 1, RF_ACTIVE); 973135048Swpaul 974135048Swpaul if (sc->vge_res == NULL) { 975135048Swpaul printf ("vge%d: couldn't map ports/memory\n", unit); 976135048Swpaul error = ENXIO; 977135048Swpaul goto fail; 978135048Swpaul } 979135048Swpaul 980135048Swpaul sc->vge_btag = rman_get_bustag(sc->vge_res); 981135048Swpaul sc->vge_bhandle = rman_get_bushandle(sc->vge_res); 982135048Swpaul 983135048Swpaul /* Allocate interrupt */ 984135048Swpaul rid = 0; 985135048Swpaul sc->vge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 986135048Swpaul 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE); 987135048Swpaul 988135048Swpaul if (sc->vge_irq == NULL) { 989135048Swpaul printf("vge%d: couldn't map interrupt\n", unit); 990135048Swpaul error = ENXIO; 991135048Swpaul goto fail; 992135048Swpaul } 993135048Swpaul 994135048Swpaul /* Reset the adapter. */ 995135048Swpaul vge_reset(sc); 996135048Swpaul 997135048Swpaul /* 998135048Swpaul * Get station address from the EEPROM. 999135048Swpaul */ 1000135048Swpaul vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 1001135048Swpaul 1002135048Swpaul sc->vge_unit = unit; 1003135048Swpaul 1004135048Swpaul#if __FreeBSD_version < 502113 1005135048Swpaul printf("vge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1006135048Swpaul#endif 1007135048Swpaul 1008135048Swpaul /* 1009135048Swpaul * Allocate the parent bus DMA tag appropriate for PCI. 1010135048Swpaul */ 1011135048Swpaul#define VGE_NSEG_NEW 32 1012135048Swpaul error = bus_dma_tag_create(NULL, /* parent */ 1013135048Swpaul 1, 0, /* alignment, boundary */ 1014135048Swpaul BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1015135048Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 1016135048Swpaul NULL, NULL, /* filter, filterarg */ 1017135048Swpaul MAXBSIZE, VGE_NSEG_NEW, /* maxsize, nsegments */ 1018135048Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1019135048Swpaul BUS_DMA_ALLOCNOW, /* flags */ 1020135048Swpaul NULL, NULL, /* lockfunc, lockarg */ 1021135048Swpaul &sc->vge_parent_tag); 1022135048Swpaul if (error) 1023135048Swpaul goto fail; 1024135048Swpaul 1025135048Swpaul error = vge_allocmem(dev, sc); 1026135048Swpaul 1027135048Swpaul if (error) 1028135048Swpaul goto fail; 1029135048Swpaul 1030147291Sbrooks ifp = sc->vge_ifp = if_alloc(IFT_ETHER); 1031147291Sbrooks if (ifp == NULL) { 1032147291Sbrooks printf("vge%d: can not if_alloc()\n", sc->vge_unit); 1033147291Sbrooks error = ENOSPC; 1034147291Sbrooks goto fail; 1035147291Sbrooks } 1036147291Sbrooks 1037135048Swpaul /* Do MII setup */ 1038135048Swpaul if (mii_phy_probe(dev, &sc->vge_miibus, 1039135048Swpaul vge_ifmedia_upd, vge_ifmedia_sts)) { 1040135048Swpaul printf("vge%d: MII without any phy!\n", sc->vge_unit); 1041135048Swpaul error = ENXIO; 1042135048Swpaul goto fail; 1043135048Swpaul } 1044135048Swpaul 1045135048Swpaul ifp->if_softc = sc; 1046135048Swpaul if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1047135048Swpaul ifp->if_mtu = ETHERMTU; 1048135048Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1049135048Swpaul ifp->if_ioctl = vge_ioctl; 1050135048Swpaul ifp->if_capabilities = IFCAP_VLAN_MTU; 1051135048Swpaul ifp->if_start = vge_start; 1052135048Swpaul ifp->if_hwassist = VGE_CSUM_FEATURES; 1053135048Swpaul ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1054135048Swpaul#ifdef DEVICE_POLLING 1055135048Swpaul#ifdef IFCAP_POLLING 1056135048Swpaul ifp->if_capabilities |= IFCAP_POLLING; 1057135048Swpaul#endif 1058135048Swpaul#endif 1059135048Swpaul ifp->if_watchdog = vge_watchdog; 1060135048Swpaul ifp->if_init = vge_init; 1061135048Swpaul ifp->if_baudrate = 1000000000; 1062135048Swpaul ifp->if_snd.ifq_maxlen = VGE_IFQ_MAXLEN; 1063135048Swpaul ifp->if_capenable = ifp->if_capabilities; 1064135048Swpaul 1065135048Swpaul TASK_INIT(&sc->vge_txtask, 0, vge_tx_task, ifp); 1066135048Swpaul 1067135048Swpaul /* 1068135048Swpaul * Call MI attach routine. 1069135048Swpaul */ 1070135048Swpaul ether_ifattach(ifp, eaddr); 1071135048Swpaul 1072135048Swpaul /* Hook interrupt last to avoid having to lock softc */ 1073135048Swpaul error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE, 1074135048Swpaul vge_intr, sc, &sc->vge_intrhand); 1075135048Swpaul 1076135048Swpaul if (error) { 1077135048Swpaul printf("vge%d: couldn't set up irq\n", unit); 1078135048Swpaul ether_ifdetach(ifp); 1079135048Swpaul goto fail; 1080135048Swpaul } 1081135048Swpaul 1082135048Swpaulfail: 1083135048Swpaul if (error) 1084135048Swpaul vge_detach(dev); 1085135048Swpaul 1086135048Swpaul return (error); 1087135048Swpaul} 1088135048Swpaul 1089135048Swpaul/* 1090135048Swpaul * Shutdown hardware and free up resources. This can be called any 1091135048Swpaul * time after the mutex has been initialized. It is called in both 1092135048Swpaul * the error case in attach and the normal detach case so it needs 1093135048Swpaul * to be careful about only freeing resources that have actually been 1094135048Swpaul * allocated. 1095135048Swpaul */ 1096135048Swpaulstatic int 1097135048Swpaulvge_detach(dev) 1098135048Swpaul device_t dev; 1099135048Swpaul{ 1100135048Swpaul struct vge_softc *sc; 1101135048Swpaul struct ifnet *ifp; 1102135048Swpaul int i; 1103135048Swpaul 1104135048Swpaul sc = device_get_softc(dev); 1105135048Swpaul KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized")); 1106147256Sbrooks ifp = sc->vge_ifp; 1107135048Swpaul 1108135048Swpaul /* These should only be active if attach succeeded */ 1109135048Swpaul if (device_is_attached(dev)) { 1110135048Swpaul vge_stop(sc); 1111135048Swpaul /* 1112135048Swpaul * Force off the IFF_UP flag here, in case someone 1113135048Swpaul * still had a BPF descriptor attached to this 1114135048Swpaul * interface. If they do, ether_ifattach() will cause 1115135048Swpaul * the BPF code to try and clear the promisc mode 1116135048Swpaul * flag, which will bubble down to vge_ioctl(), 1117135048Swpaul * which will try to call vge_init() again. This will 1118135048Swpaul * turn the NIC back on and restart the MII ticker, 1119135048Swpaul * which will panic the system when the kernel tries 1120135048Swpaul * to invoke the vge_tick() function that isn't there 1121135048Swpaul * anymore. 1122135048Swpaul */ 1123135048Swpaul ifp->if_flags &= ~IFF_UP; 1124135048Swpaul ether_ifdetach(ifp); 1125147256Sbrooks if_free(ifp); 1126135048Swpaul } 1127135048Swpaul if (sc->vge_miibus) 1128135048Swpaul device_delete_child(dev, sc->vge_miibus); 1129135048Swpaul bus_generic_detach(dev); 1130135048Swpaul 1131135048Swpaul if (sc->vge_intrhand) 1132135048Swpaul bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); 1133135048Swpaul if (sc->vge_irq) 1134135048Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vge_irq); 1135135048Swpaul if (sc->vge_res) 1136135048Swpaul bus_release_resource(dev, SYS_RES_MEMORY, 1137135048Swpaul VGE_PCI_LOMEM, sc->vge_res); 1138135048Swpaul 1139135048Swpaul /* Unload and free the RX DMA ring memory and map */ 1140135048Swpaul 1141135048Swpaul if (sc->vge_ldata.vge_rx_list_tag) { 1142135048Swpaul bus_dmamap_unload(sc->vge_ldata.vge_rx_list_tag, 1143135048Swpaul sc->vge_ldata.vge_rx_list_map); 1144135048Swpaul bus_dmamem_free(sc->vge_ldata.vge_rx_list_tag, 1145135048Swpaul sc->vge_ldata.vge_rx_list, 1146135048Swpaul sc->vge_ldata.vge_rx_list_map); 1147135048Swpaul bus_dma_tag_destroy(sc->vge_ldata.vge_rx_list_tag); 1148135048Swpaul } 1149135048Swpaul 1150135048Swpaul /* Unload and free the TX DMA ring memory and map */ 1151135048Swpaul 1152135048Swpaul if (sc->vge_ldata.vge_tx_list_tag) { 1153135048Swpaul bus_dmamap_unload(sc->vge_ldata.vge_tx_list_tag, 1154135048Swpaul sc->vge_ldata.vge_tx_list_map); 1155135048Swpaul bus_dmamem_free(sc->vge_ldata.vge_tx_list_tag, 1156135048Swpaul sc->vge_ldata.vge_tx_list, 1157135048Swpaul sc->vge_ldata.vge_tx_list_map); 1158135048Swpaul bus_dma_tag_destroy(sc->vge_ldata.vge_tx_list_tag); 1159135048Swpaul } 1160135048Swpaul 1161135048Swpaul /* Destroy all the RX and TX buffer maps */ 1162135048Swpaul 1163135048Swpaul if (sc->vge_ldata.vge_mtag) { 1164135048Swpaul for (i = 0; i < VGE_TX_DESC_CNT; i++) 1165135048Swpaul bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1166135048Swpaul sc->vge_ldata.vge_tx_dmamap[i]); 1167135048Swpaul for (i = 0; i < VGE_RX_DESC_CNT; i++) 1168135048Swpaul bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1169135048Swpaul sc->vge_ldata.vge_rx_dmamap[i]); 1170135048Swpaul bus_dma_tag_destroy(sc->vge_ldata.vge_mtag); 1171135048Swpaul } 1172135048Swpaul 1173135048Swpaul if (sc->vge_parent_tag) 1174135048Swpaul bus_dma_tag_destroy(sc->vge_parent_tag); 1175135048Swpaul 1176135048Swpaul mtx_destroy(&sc->vge_mtx); 1177135048Swpaul 1178135048Swpaul return (0); 1179135048Swpaul} 1180135048Swpaul 1181135048Swpaulstatic int 1182135048Swpaulvge_newbuf(sc, idx, m) 1183135048Swpaul struct vge_softc *sc; 1184135048Swpaul int idx; 1185135048Swpaul struct mbuf *m; 1186135048Swpaul{ 1187135048Swpaul struct vge_dmaload_arg arg; 1188135048Swpaul struct mbuf *n = NULL; 1189135048Swpaul int i, error; 1190135048Swpaul 1191135048Swpaul if (m == NULL) { 1192135048Swpaul n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1193135048Swpaul if (n == NULL) 1194135048Swpaul return (ENOBUFS); 1195135048Swpaul m = n; 1196135048Swpaul } else 1197135048Swpaul m->m_data = m->m_ext.ext_buf; 1198135048Swpaul 1199135048Swpaul 1200135048Swpaul#ifdef VGE_FIXUP_RX 1201135048Swpaul /* 1202135048Swpaul * This is part of an evil trick to deal with non-x86 platforms. 1203135048Swpaul * The VIA chip requires RX buffers to be aligned on 32-bit 1204135048Swpaul * boundaries, but that will hose non-x86 machines. To get around 1205135048Swpaul * this, we leave some empty space at the start of each buffer 1206135048Swpaul * and for non-x86 hosts, we copy the buffer back two bytes 1207135048Swpaul * to achieve word alignment. This is slightly more efficient 1208135048Swpaul * than allocating a new buffer, copying the contents, and 1209135048Swpaul * discarding the old buffer. 1210135048Swpaul */ 1211135048Swpaul m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_ETHER_ALIGN; 1212135048Swpaul m_adj(m, VGE_ETHER_ALIGN); 1213135048Swpaul#else 1214135048Swpaul m->m_len = m->m_pkthdr.len = MCLBYTES; 1215135048Swpaul#endif 1216135048Swpaul 1217135048Swpaul arg.sc = sc; 1218135048Swpaul arg.vge_idx = idx; 1219135048Swpaul arg.vge_maxsegs = 1; 1220135048Swpaul arg.vge_flags = 0; 1221135048Swpaul 1222135048Swpaul error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, 1223135048Swpaul sc->vge_ldata.vge_rx_dmamap[idx], m, vge_dma_map_rx_desc, 1224135048Swpaul &arg, BUS_DMA_NOWAIT); 1225135048Swpaul if (error || arg.vge_maxsegs != 1) { 1226135048Swpaul if (n != NULL) 1227135048Swpaul m_freem(n); 1228135048Swpaul return (ENOMEM); 1229135048Swpaul } 1230135048Swpaul 1231135048Swpaul /* 1232135048Swpaul * Note: the manual fails to document the fact that for 1233135048Swpaul * proper opration, the driver needs to replentish the RX 1234135048Swpaul * DMA ring 4 descriptors at a time (rather than one at a 1235135048Swpaul * time, like most chips). We can allocate the new buffers 1236135048Swpaul * but we should not set the OWN bits until we're ready 1237135048Swpaul * to hand back 4 of them in one shot. 1238135048Swpaul */ 1239135048Swpaul 1240135048Swpaul#define VGE_RXCHUNK 4 1241135048Swpaul sc->vge_rx_consumed++; 1242135048Swpaul if (sc->vge_rx_consumed == VGE_RXCHUNK) { 1243135048Swpaul for (i = idx; i != idx - sc->vge_rx_consumed; i--) 1244135048Swpaul sc->vge_ldata.vge_rx_list[i].vge_sts |= 1245135048Swpaul htole32(VGE_RDSTS_OWN); 1246135048Swpaul sc->vge_rx_consumed = 0; 1247135048Swpaul } 1248135048Swpaul 1249135048Swpaul sc->vge_ldata.vge_rx_mbuf[idx] = m; 1250135048Swpaul 1251135048Swpaul bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1252135048Swpaul sc->vge_ldata.vge_rx_dmamap[idx], 1253135048Swpaul BUS_DMASYNC_PREREAD); 1254135048Swpaul 1255135048Swpaul return (0); 1256135048Swpaul} 1257135048Swpaul 1258135048Swpaulstatic int 1259135048Swpaulvge_tx_list_init(sc) 1260135048Swpaul struct vge_softc *sc; 1261135048Swpaul{ 1262135048Swpaul bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 1263135048Swpaul bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 1264135048Swpaul (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 1265135048Swpaul 1266135048Swpaul bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1267135048Swpaul sc->vge_ldata.vge_tx_list_map, BUS_DMASYNC_PREWRITE); 1268135048Swpaul sc->vge_ldata.vge_tx_prodidx = 0; 1269135048Swpaul sc->vge_ldata.vge_tx_considx = 0; 1270135048Swpaul sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 1271135048Swpaul 1272135048Swpaul return (0); 1273135048Swpaul} 1274135048Swpaul 1275135048Swpaulstatic int 1276135048Swpaulvge_rx_list_init(sc) 1277135048Swpaul struct vge_softc *sc; 1278135048Swpaul{ 1279135048Swpaul int i; 1280135048Swpaul 1281135048Swpaul bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 1282135048Swpaul bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 1283135048Swpaul (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 1284135048Swpaul 1285135048Swpaul sc->vge_rx_consumed = 0; 1286135048Swpaul 1287135048Swpaul for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1288135048Swpaul if (vge_newbuf(sc, i, NULL) == ENOBUFS) 1289135048Swpaul return (ENOBUFS); 1290135048Swpaul } 1291135048Swpaul 1292135048Swpaul /* Flush the RX descriptors */ 1293135048Swpaul 1294135048Swpaul bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1295135048Swpaul sc->vge_ldata.vge_rx_list_map, 1296135048Swpaul BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1297135048Swpaul 1298135048Swpaul sc->vge_ldata.vge_rx_prodidx = 0; 1299135048Swpaul sc->vge_rx_consumed = 0; 1300135048Swpaul sc->vge_head = sc->vge_tail = NULL; 1301135048Swpaul 1302135048Swpaul return (0); 1303135048Swpaul} 1304135048Swpaul 1305135048Swpaul#ifdef VGE_FIXUP_RX 1306135048Swpaulstatic __inline void 1307135048Swpaulvge_fixup_rx(m) 1308135048Swpaul struct mbuf *m; 1309135048Swpaul{ 1310135048Swpaul int i; 1311135048Swpaul uint16_t *src, *dst; 1312135048Swpaul 1313135048Swpaul src = mtod(m, uint16_t *); 1314135048Swpaul dst = src - 1; 1315135048Swpaul 1316135048Swpaul for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1317135048Swpaul *dst++ = *src++; 1318135048Swpaul 1319135048Swpaul m->m_data -= ETHER_ALIGN; 1320135048Swpaul 1321135048Swpaul return; 1322135048Swpaul} 1323135048Swpaul#endif 1324135048Swpaul 1325135048Swpaul/* 1326135048Swpaul * RX handler. We support the reception of jumbo frames that have 1327135048Swpaul * been fragmented across multiple 2K mbuf cluster buffers. 1328135048Swpaul */ 1329135048Swpaulstatic void 1330135048Swpaulvge_rxeof(sc) 1331135048Swpaul struct vge_softc *sc; 1332135048Swpaul{ 1333135048Swpaul struct mbuf *m; 1334135048Swpaul struct ifnet *ifp; 1335135048Swpaul int i, total_len; 1336135048Swpaul int lim = 0; 1337135048Swpaul struct vge_rx_desc *cur_rx; 1338135048Swpaul u_int32_t rxstat, rxctl; 1339135048Swpaul 1340135048Swpaul VGE_LOCK_ASSERT(sc); 1341147256Sbrooks ifp = sc->vge_ifp; 1342135048Swpaul i = sc->vge_ldata.vge_rx_prodidx; 1343135048Swpaul 1344135048Swpaul /* Invalidate the descriptor memory */ 1345135048Swpaul 1346135048Swpaul bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1347135048Swpaul sc->vge_ldata.vge_rx_list_map, 1348135048Swpaul BUS_DMASYNC_POSTREAD); 1349135048Swpaul 1350135048Swpaul while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 1351135048Swpaul 1352135048Swpaul#ifdef DEVICE_POLLING 1353135048Swpaul if (ifp->if_flags & IFF_POLLING) { 1354135048Swpaul if (sc->rxcycles <= 0) 1355135048Swpaul break; 1356135048Swpaul sc->rxcycles--; 1357135048Swpaul } 1358135048Swpaul#endif /* DEVICE_POLLING */ 1359135048Swpaul 1360135048Swpaul cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1361135048Swpaul m = sc->vge_ldata.vge_rx_mbuf[i]; 1362135048Swpaul total_len = VGE_RXBYTES(cur_rx); 1363135048Swpaul rxstat = le32toh(cur_rx->vge_sts); 1364135048Swpaul rxctl = le32toh(cur_rx->vge_ctl); 1365135048Swpaul 1366135048Swpaul /* Invalidate the RX mbuf and unload its map */ 1367135048Swpaul 1368135048Swpaul bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1369135048Swpaul sc->vge_ldata.vge_rx_dmamap[i], 1370135048Swpaul BUS_DMASYNC_POSTWRITE); 1371135048Swpaul bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1372135048Swpaul sc->vge_ldata.vge_rx_dmamap[i]); 1373135048Swpaul 1374135048Swpaul /* 1375135048Swpaul * If the 'start of frame' bit is set, this indicates 1376135048Swpaul * either the first fragment in a multi-fragment receive, 1377135048Swpaul * or an intermediate fragment. Either way, we want to 1378135048Swpaul * accumulate the buffers. 1379135048Swpaul */ 1380135048Swpaul if (rxstat & VGE_RXPKT_SOF) { 1381135048Swpaul m->m_len = MCLBYTES - VGE_ETHER_ALIGN; 1382135048Swpaul if (sc->vge_head == NULL) 1383135048Swpaul sc->vge_head = sc->vge_tail = m; 1384135048Swpaul else { 1385135048Swpaul m->m_flags &= ~M_PKTHDR; 1386135048Swpaul sc->vge_tail->m_next = m; 1387135048Swpaul sc->vge_tail = m; 1388135048Swpaul } 1389135048Swpaul vge_newbuf(sc, i, NULL); 1390135048Swpaul VGE_RX_DESC_INC(i); 1391135048Swpaul continue; 1392135048Swpaul } 1393135048Swpaul 1394135048Swpaul /* 1395135048Swpaul * Bad/error frames will have the RXOK bit cleared. 1396135048Swpaul * However, there's one error case we want to allow: 1397135048Swpaul * if a VLAN tagged frame arrives and the chip can't 1398135048Swpaul * match it against the CAM filter, it considers this 1399135048Swpaul * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1400135048Swpaul * We don't want to drop the frame though: our VLAN 1401135048Swpaul * filtering is done in software. 1402135048Swpaul */ 1403135048Swpaul if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1404135048Swpaul && !(rxstat & VGE_RDSTS_CSUMERR)) { 1405135048Swpaul ifp->if_ierrors++; 1406135048Swpaul /* 1407135048Swpaul * If this is part of a multi-fragment packet, 1408135048Swpaul * discard all the pieces. 1409135048Swpaul */ 1410135048Swpaul if (sc->vge_head != NULL) { 1411135048Swpaul m_freem(sc->vge_head); 1412135048Swpaul sc->vge_head = sc->vge_tail = NULL; 1413135048Swpaul } 1414135048Swpaul vge_newbuf(sc, i, m); 1415135048Swpaul VGE_RX_DESC_INC(i); 1416135048Swpaul continue; 1417135048Swpaul } 1418135048Swpaul 1419135048Swpaul /* 1420135048Swpaul * If allocating a replacement mbuf fails, 1421135048Swpaul * reload the current one. 1422135048Swpaul */ 1423135048Swpaul 1424135048Swpaul if (vge_newbuf(sc, i, NULL)) { 1425135048Swpaul ifp->if_ierrors++; 1426135048Swpaul if (sc->vge_head != NULL) { 1427135048Swpaul m_freem(sc->vge_head); 1428135048Swpaul sc->vge_head = sc->vge_tail = NULL; 1429135048Swpaul } 1430135048Swpaul vge_newbuf(sc, i, m); 1431135048Swpaul VGE_RX_DESC_INC(i); 1432135048Swpaul continue; 1433135048Swpaul } 1434135048Swpaul 1435135048Swpaul VGE_RX_DESC_INC(i); 1436135048Swpaul 1437135048Swpaul if (sc->vge_head != NULL) { 1438135048Swpaul m->m_len = total_len % (MCLBYTES - VGE_ETHER_ALIGN); 1439135048Swpaul /* 1440135048Swpaul * Special case: if there's 4 bytes or less 1441135048Swpaul * in this buffer, the mbuf can be discarded: 1442135048Swpaul * the last 4 bytes is the CRC, which we don't 1443135048Swpaul * care about anyway. 1444135048Swpaul */ 1445135048Swpaul if (m->m_len <= ETHER_CRC_LEN) { 1446135048Swpaul sc->vge_tail->m_len -= 1447135048Swpaul (ETHER_CRC_LEN - m->m_len); 1448135048Swpaul m_freem(m); 1449135048Swpaul } else { 1450135048Swpaul m->m_len -= ETHER_CRC_LEN; 1451135048Swpaul m->m_flags &= ~M_PKTHDR; 1452135048Swpaul sc->vge_tail->m_next = m; 1453135048Swpaul } 1454135048Swpaul m = sc->vge_head; 1455135048Swpaul sc->vge_head = sc->vge_tail = NULL; 1456135048Swpaul m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1457135048Swpaul } else 1458135048Swpaul m->m_pkthdr.len = m->m_len = 1459135048Swpaul (total_len - ETHER_CRC_LEN); 1460135048Swpaul 1461135048Swpaul#ifdef VGE_FIXUP_RX 1462135048Swpaul vge_fixup_rx(m); 1463135048Swpaul#endif 1464135048Swpaul ifp->if_ipackets++; 1465135048Swpaul m->m_pkthdr.rcvif = ifp; 1466135048Swpaul 1467135048Swpaul /* Do RX checksumming if enabled */ 1468135048Swpaul if (ifp->if_capenable & IFCAP_RXCSUM) { 1469135048Swpaul 1470135048Swpaul /* Check IP header checksum */ 1471135048Swpaul if (rxctl & VGE_RDCTL_IPPKT) 1472135048Swpaul m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1473135048Swpaul if (rxctl & VGE_RDCTL_IPCSUMOK) 1474135048Swpaul m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1475135048Swpaul 1476135048Swpaul /* Check TCP/UDP checksum */ 1477135048Swpaul if (rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT) && 1478135048Swpaul rxctl & VGE_RDCTL_PROTOCSUMOK) { 1479135048Swpaul m->m_pkthdr.csum_flags |= 1480135048Swpaul CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1481135048Swpaul m->m_pkthdr.csum_data = 0xffff; 1482135048Swpaul } 1483135048Swpaul } 1484135048Swpaul 1485135048Swpaul if (rxstat & VGE_RDSTS_VTAG) 1486135048Swpaul VLAN_INPUT_TAG(ifp, m, 1487135048Swpaul ntohs((rxctl & VGE_RDCTL_VLANID)), continue); 1488135048Swpaul 1489135048Swpaul VGE_UNLOCK(sc); 1490135048Swpaul (*ifp->if_input)(ifp, m); 1491135048Swpaul VGE_LOCK(sc); 1492135048Swpaul 1493135048Swpaul lim++; 1494135048Swpaul if (lim == VGE_RX_DESC_CNT) 1495135048Swpaul break; 1496135048Swpaul 1497135048Swpaul } 1498135048Swpaul 1499135048Swpaul /* Flush the RX DMA ring */ 1500135048Swpaul 1501135048Swpaul bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1502135048Swpaul sc->vge_ldata.vge_rx_list_map, 1503135048Swpaul BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1504135048Swpaul 1505135048Swpaul sc->vge_ldata.vge_rx_prodidx = i; 1506135048Swpaul CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1507135048Swpaul 1508135048Swpaul 1509135048Swpaul return; 1510135048Swpaul} 1511135048Swpaul 1512135048Swpaulstatic void 1513135048Swpaulvge_txeof(sc) 1514135048Swpaul struct vge_softc *sc; 1515135048Swpaul{ 1516135048Swpaul struct ifnet *ifp; 1517135048Swpaul u_int32_t txstat; 1518135048Swpaul int idx; 1519135048Swpaul 1520147256Sbrooks ifp = sc->vge_ifp; 1521135048Swpaul idx = sc->vge_ldata.vge_tx_considx; 1522135048Swpaul 1523135048Swpaul /* Invalidate the TX descriptor list */ 1524135048Swpaul 1525135048Swpaul bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1526135048Swpaul sc->vge_ldata.vge_tx_list_map, 1527135048Swpaul BUS_DMASYNC_POSTREAD); 1528135048Swpaul 1529135048Swpaul while (idx != sc->vge_ldata.vge_tx_prodidx) { 1530135048Swpaul 1531135048Swpaul txstat = le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1532135048Swpaul if (txstat & VGE_TDSTS_OWN) 1533135048Swpaul break; 1534135048Swpaul 1535135048Swpaul m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1536135048Swpaul sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1537135048Swpaul bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1538135048Swpaul sc->vge_ldata.vge_tx_dmamap[idx]); 1539135048Swpaul if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1540135048Swpaul ifp->if_collisions++; 1541135048Swpaul if (txstat & VGE_TDSTS_TXERR) 1542135048Swpaul ifp->if_oerrors++; 1543135048Swpaul else 1544135048Swpaul ifp->if_opackets++; 1545135048Swpaul 1546135048Swpaul sc->vge_ldata.vge_tx_free++; 1547135048Swpaul VGE_TX_DESC_INC(idx); 1548135048Swpaul } 1549135048Swpaul 1550135048Swpaul /* No changes made to the TX ring, so no flush needed */ 1551135048Swpaul 1552135048Swpaul if (idx != sc->vge_ldata.vge_tx_considx) { 1553135048Swpaul sc->vge_ldata.vge_tx_considx = idx; 1554135048Swpaul ifp->if_flags &= ~IFF_OACTIVE; 1555135048Swpaul ifp->if_timer = 0; 1556135048Swpaul } 1557135048Swpaul 1558135048Swpaul /* 1559135048Swpaul * If not all descriptors have been released reaped yet, 1560135048Swpaul * reload the timer so that we will eventually get another 1561135048Swpaul * interrupt that will cause us to re-enter this routine. 1562135048Swpaul * This is done in case the transmitter has gone idle. 1563135048Swpaul */ 1564135048Swpaul if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) { 1565135048Swpaul CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1566135048Swpaul } 1567135048Swpaul 1568135048Swpaul return; 1569135048Swpaul} 1570135048Swpaul 1571135048Swpaulstatic void 1572135048Swpaulvge_tick(xsc) 1573135048Swpaul void *xsc; 1574135048Swpaul{ 1575135048Swpaul struct vge_softc *sc; 1576135048Swpaul struct ifnet *ifp; 1577135048Swpaul struct mii_data *mii; 1578135048Swpaul 1579135048Swpaul sc = xsc; 1580147256Sbrooks ifp = sc->vge_ifp; 1581135048Swpaul VGE_LOCK(sc); 1582135048Swpaul mii = device_get_softc(sc->vge_miibus); 1583135048Swpaul 1584135048Swpaul mii_tick(mii); 1585135048Swpaul if (sc->vge_link) { 1586135048Swpaul if (!(mii->mii_media_status & IFM_ACTIVE)) { 1587135048Swpaul sc->vge_link = 0; 1588147256Sbrooks if_link_state_change(sc->vge_ifp, 1589145521Swpaul LINK_STATE_DOWN); 1590135048Swpaul } 1591135048Swpaul } else { 1592135048Swpaul if (mii->mii_media_status & IFM_ACTIVE && 1593135048Swpaul IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1594135048Swpaul sc->vge_link = 1; 1595147256Sbrooks if_link_state_change(sc->vge_ifp, 1596145521Swpaul LINK_STATE_UP); 1597135048Swpaul#if __FreeBSD_version < 502114 1598135048Swpaul if (ifp->if_snd.ifq_head != NULL) 1599135048Swpaul#else 1600135048Swpaul if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1601135048Swpaul#endif 1602135048Swpaul taskqueue_enqueue(taskqueue_swi, 1603135048Swpaul &sc->vge_txtask); 1604135048Swpaul } 1605135048Swpaul } 1606135048Swpaul 1607135048Swpaul VGE_UNLOCK(sc); 1608135048Swpaul 1609135048Swpaul return; 1610135048Swpaul} 1611135048Swpaul 1612135048Swpaul#ifdef DEVICE_POLLING 1613135048Swpaulstatic void 1614135048Swpaulvge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1615135048Swpaul{ 1616135048Swpaul struct vge_softc *sc = ifp->if_softc; 1617135048Swpaul 1618135048Swpaul VGE_LOCK(sc); 1619135048Swpaul#ifdef IFCAP_POLLING 1620135048Swpaul if (!(ifp->if_capenable & IFCAP_POLLING)) { 1621135048Swpaul ether_poll_deregister(ifp); 1622135048Swpaul cmd = POLL_DEREGISTER; 1623135048Swpaul } 1624135048Swpaul#endif 1625135048Swpaul if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1626135048Swpaul CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1627135048Swpaul CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 1628135048Swpaul CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1629135048Swpaul goto done; 1630135048Swpaul } 1631135048Swpaul 1632135048Swpaul sc->rxcycles = count; 1633135048Swpaul vge_rxeof(sc); 1634135048Swpaul vge_txeof(sc); 1635135048Swpaul 1636135048Swpaul#if __FreeBSD_version < 502114 1637135048Swpaul if (ifp->if_snd.ifq_head != NULL) 1638135048Swpaul#else 1639135048Swpaul if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1640135048Swpaul#endif 1641135048Swpaul taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1642135048Swpaul 1643135048Swpaul if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1644135048Swpaul u_int32_t status; 1645135048Swpaul status = CSR_READ_4(sc, VGE_ISR); 1646135048Swpaul if (status == 0xFFFFFFFF) 1647135048Swpaul goto done; 1648135048Swpaul if (status) 1649135048Swpaul CSR_WRITE_4(sc, VGE_ISR, status); 1650135048Swpaul 1651135048Swpaul /* 1652135048Swpaul * XXX check behaviour on receiver stalls. 1653135048Swpaul */ 1654135048Swpaul 1655135048Swpaul if (status & VGE_ISR_TXDMA_STALL || 1656135048Swpaul status & VGE_ISR_RXDMA_STALL) 1657135048Swpaul vge_init(sc); 1658135048Swpaul 1659135048Swpaul if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1660135048Swpaul vge_rxeof(sc); 1661135048Swpaul ifp->if_ierrors++; 1662135048Swpaul CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1663135048Swpaul CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1664135048Swpaul } 1665135048Swpaul } 1666135048Swpauldone: 1667135048Swpaul VGE_UNLOCK(sc); 1668135048Swpaul} 1669135048Swpaul#endif /* DEVICE_POLLING */ 1670135048Swpaul 1671135048Swpaulstatic void 1672135048Swpaulvge_intr(arg) 1673135048Swpaul void *arg; 1674135048Swpaul{ 1675135048Swpaul struct vge_softc *sc; 1676135048Swpaul struct ifnet *ifp; 1677135048Swpaul u_int32_t status; 1678135048Swpaul 1679135048Swpaul sc = arg; 1680135048Swpaul 1681135048Swpaul if (sc->suspended) { 1682135048Swpaul return; 1683135048Swpaul } 1684135048Swpaul 1685135048Swpaul VGE_LOCK(sc); 1686147256Sbrooks ifp = sc->vge_ifp; 1687135048Swpaul 1688135048Swpaul if (!(ifp->if_flags & IFF_UP)) { 1689135048Swpaul VGE_UNLOCK(sc); 1690135048Swpaul return; 1691135048Swpaul } 1692135048Swpaul 1693135048Swpaul#ifdef DEVICE_POLLING 1694135048Swpaul if (ifp->if_flags & IFF_POLLING) 1695135048Swpaul goto done; 1696135048Swpaul if ( 1697135048Swpaul#ifdef IFCAP_POLLING 1698135048Swpaul (ifp->if_capenable & IFCAP_POLLING) && 1699135048Swpaul#endif 1700135048Swpaul ether_poll_register(vge_poll, ifp)) { /* ok, disable interrupts */ 1701135048Swpaul CSR_WRITE_4(sc, VGE_IMR, 0); 1702135048Swpaul CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1703135048Swpaul vge_poll(ifp, 0, 1); 1704135048Swpaul goto done; 1705135048Swpaul } 1706135048Swpaul 1707135048Swpaul#endif /* DEVICE_POLLING */ 1708135048Swpaul 1709135048Swpaul /* Disable interrupts */ 1710135048Swpaul CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1711135048Swpaul 1712135048Swpaul for (;;) { 1713135048Swpaul 1714135048Swpaul status = CSR_READ_4(sc, VGE_ISR); 1715135048Swpaul /* If the card has gone away the read returns 0xffff. */ 1716135048Swpaul if (status == 0xFFFFFFFF) 1717135048Swpaul break; 1718135048Swpaul 1719135048Swpaul if (status) 1720135048Swpaul CSR_WRITE_4(sc, VGE_ISR, status); 1721135048Swpaul 1722135048Swpaul if ((status & VGE_INTRS) == 0) 1723135048Swpaul break; 1724135048Swpaul 1725135048Swpaul if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1726135048Swpaul vge_rxeof(sc); 1727135048Swpaul 1728135048Swpaul if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1729135048Swpaul vge_rxeof(sc); 1730135048Swpaul CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1731135048Swpaul CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1732135048Swpaul } 1733135048Swpaul 1734135048Swpaul if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1735135048Swpaul vge_txeof(sc); 1736135048Swpaul 1737135048Swpaul if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1738135048Swpaul vge_init(sc); 1739135048Swpaul 1740135048Swpaul if (status & VGE_ISR_LINKSTS) 1741135048Swpaul vge_tick(sc); 1742135048Swpaul } 1743135048Swpaul 1744135048Swpaul /* Re-enable interrupts */ 1745135048Swpaul CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1746135048Swpaul 1747135048Swpaul#ifdef DEVICE_POLLING 1748135048Swpauldone: 1749135048Swpaul#endif 1750135048Swpaul VGE_UNLOCK(sc); 1751135048Swpaul 1752135048Swpaul#if __FreeBSD_version < 502114 1753135048Swpaul if (ifp->if_snd.ifq_head != NULL) 1754135048Swpaul#else 1755135048Swpaul if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1756135048Swpaul#endif 1757135048Swpaul taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1758135048Swpaul 1759135048Swpaul return; 1760135048Swpaul} 1761135048Swpaul 1762135048Swpaulstatic int 1763135048Swpaulvge_encap(sc, m_head, idx) 1764135048Swpaul struct vge_softc *sc; 1765135048Swpaul struct mbuf *m_head; 1766135048Swpaul int idx; 1767135048Swpaul{ 1768135048Swpaul struct mbuf *m_new = NULL; 1769135048Swpaul struct vge_dmaload_arg arg; 1770135048Swpaul bus_dmamap_t map; 1771135048Swpaul int error; 1772135048Swpaul struct m_tag *mtag; 1773135048Swpaul 1774135048Swpaul if (sc->vge_ldata.vge_tx_free <= 2) 1775135048Swpaul return (EFBIG); 1776135048Swpaul 1777135048Swpaul arg.vge_flags = 0; 1778135048Swpaul 1779135048Swpaul if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1780135048Swpaul arg.vge_flags |= VGE_TDCTL_IPCSUM; 1781135048Swpaul if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1782135048Swpaul arg.vge_flags |= VGE_TDCTL_TCPCSUM; 1783135048Swpaul if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1784135048Swpaul arg.vge_flags |= VGE_TDCTL_UDPCSUM; 1785135048Swpaul 1786135048Swpaul arg.sc = sc; 1787135048Swpaul arg.vge_idx = idx; 1788135048Swpaul arg.vge_m0 = m_head; 1789135048Swpaul arg.vge_maxsegs = VGE_TX_FRAGS; 1790135048Swpaul 1791135048Swpaul map = sc->vge_ldata.vge_tx_dmamap[idx]; 1792135048Swpaul error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1793135048Swpaul m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1794135048Swpaul 1795135048Swpaul if (error && error != EFBIG) { 1796135048Swpaul printf("vge%d: can't map mbuf (error %d)\n", 1797135048Swpaul sc->vge_unit, error); 1798135048Swpaul return (ENOBUFS); 1799135048Swpaul } 1800135048Swpaul 1801135048Swpaul /* Too many segments to map, coalesce into a single mbuf */ 1802135048Swpaul 1803135048Swpaul if (error || arg.vge_maxsegs == 0) { 1804135048Swpaul m_new = m_defrag(m_head, M_DONTWAIT); 1805135048Swpaul if (m_new == NULL) 1806135048Swpaul return (1); 1807135048Swpaul else 1808135048Swpaul m_head = m_new; 1809135048Swpaul 1810135048Swpaul arg.sc = sc; 1811135048Swpaul arg.vge_m0 = m_head; 1812135048Swpaul arg.vge_idx = idx; 1813135048Swpaul arg.vge_maxsegs = 1; 1814135048Swpaul 1815135048Swpaul error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1816135048Swpaul m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1817135048Swpaul if (error) { 1818135048Swpaul printf("vge%d: can't map mbuf (error %d)\n", 1819135048Swpaul sc->vge_unit, error); 1820135048Swpaul return (EFBIG); 1821135048Swpaul } 1822135048Swpaul } 1823135048Swpaul 1824135048Swpaul sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1825135048Swpaul sc->vge_ldata.vge_tx_free--; 1826135048Swpaul 1827135048Swpaul /* 1828135048Swpaul * Set up hardware VLAN tagging. 1829135048Swpaul */ 1830135048Swpaul 1831147256Sbrooks mtag = VLAN_OUTPUT_TAG(sc->vge_ifp, m_head); 1832135048Swpaul if (mtag != NULL) 1833135048Swpaul sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1834135048Swpaul htole32(htons(VLAN_TAG_VALUE(mtag)) | VGE_TDCTL_VTAG); 1835135048Swpaul 1836135048Swpaul sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1837135048Swpaul 1838135048Swpaul return (0); 1839135048Swpaul} 1840135048Swpaul 1841135048Swpaulstatic void 1842135048Swpaulvge_tx_task(arg, npending) 1843135048Swpaul void *arg; 1844135048Swpaul int npending; 1845135048Swpaul{ 1846135048Swpaul struct ifnet *ifp; 1847135048Swpaul 1848135048Swpaul ifp = arg; 1849135048Swpaul vge_start(ifp); 1850135048Swpaul 1851135048Swpaul return; 1852135048Swpaul} 1853135048Swpaul 1854135048Swpaul/* 1855135048Swpaul * Main transmit routine. 1856135048Swpaul */ 1857135048Swpaul 1858135048Swpaulstatic void 1859135048Swpaulvge_start(ifp) 1860135048Swpaul struct ifnet *ifp; 1861135048Swpaul{ 1862135048Swpaul struct vge_softc *sc; 1863135048Swpaul struct mbuf *m_head = NULL; 1864135048Swpaul int idx, pidx = 0; 1865135048Swpaul 1866135048Swpaul sc = ifp->if_softc; 1867135048Swpaul VGE_LOCK(sc); 1868135048Swpaul 1869135048Swpaul if (!sc->vge_link || ifp->if_flags & IFF_OACTIVE) { 1870135048Swpaul VGE_UNLOCK(sc); 1871135048Swpaul return; 1872135048Swpaul } 1873135048Swpaul 1874135048Swpaul#if __FreeBSD_version < 502114 1875135048Swpaul if (ifp->if_snd.ifq_head == NULL) { 1876135048Swpaul#else 1877135048Swpaul if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 1878135048Swpaul#endif 1879135048Swpaul VGE_UNLOCK(sc); 1880135048Swpaul return; 1881135048Swpaul } 1882135048Swpaul 1883135048Swpaul idx = sc->vge_ldata.vge_tx_prodidx; 1884135048Swpaul 1885135048Swpaul pidx = idx - 1; 1886135048Swpaul if (pidx < 0) 1887135048Swpaul pidx = VGE_TX_DESC_CNT - 1; 1888135048Swpaul 1889135048Swpaul 1890135048Swpaul while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1891135048Swpaul#if __FreeBSD_version < 502114 1892135048Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 1893135048Swpaul#else 1894135048Swpaul IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1895135048Swpaul#endif 1896135048Swpaul if (m_head == NULL) 1897135048Swpaul break; 1898135048Swpaul 1899135048Swpaul if (vge_encap(sc, m_head, idx)) { 1900135048Swpaul#if __FreeBSD_version >= 502114 1901135048Swpaul IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1902135048Swpaul#else 1903135048Swpaul IF_PREPEND(&ifp->if_snd, m_head); 1904135048Swpaul#endif 1905135048Swpaul ifp->if_flags |= IFF_OACTIVE; 1906135048Swpaul break; 1907135048Swpaul } 1908135048Swpaul 1909135048Swpaul sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1910135048Swpaul htole16(VGE_TXDESC_Q); 1911135048Swpaul 1912135048Swpaul pidx = idx; 1913135048Swpaul VGE_TX_DESC_INC(idx); 1914135048Swpaul 1915135048Swpaul /* 1916135048Swpaul * If there's a BPF listener, bounce a copy of this frame 1917135048Swpaul * to him. 1918135048Swpaul */ 1919135048Swpaul BPF_MTAP(ifp, m_head); 1920135048Swpaul } 1921135048Swpaul 1922135048Swpaul if (idx == sc->vge_ldata.vge_tx_prodidx) { 1923135048Swpaul VGE_UNLOCK(sc); 1924135048Swpaul return; 1925135048Swpaul } 1926135048Swpaul 1927135048Swpaul /* Flush the TX descriptors */ 1928135048Swpaul 1929135048Swpaul bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1930135048Swpaul sc->vge_ldata.vge_tx_list_map, 1931135048Swpaul BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1932135048Swpaul 1933135048Swpaul /* Issue a transmit command. */ 1934135048Swpaul CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1935135048Swpaul 1936135048Swpaul sc->vge_ldata.vge_tx_prodidx = idx; 1937135048Swpaul 1938135048Swpaul /* 1939135048Swpaul * Use the countdown timer for interrupt moderation. 1940135048Swpaul * 'TX done' interrupts are disabled. Instead, we reset the 1941135048Swpaul * countdown timer, which will begin counting until it hits 1942135048Swpaul * the value in the SSTIMER register, and then trigger an 1943135048Swpaul * interrupt. Each time we set the TIMER0_ENABLE bit, the 1944135048Swpaul * the timer count is reloaded. Only when the transmitter 1945135048Swpaul * is idle will the timer hit 0 and an interrupt fire. 1946135048Swpaul */ 1947135048Swpaul CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1948135048Swpaul 1949135048Swpaul VGE_UNLOCK(sc); 1950135048Swpaul 1951135048Swpaul /* 1952135048Swpaul * Set a timeout in case the chip goes out to lunch. 1953135048Swpaul */ 1954135048Swpaul ifp->if_timer = 5; 1955135048Swpaul 1956135048Swpaul return; 1957135048Swpaul} 1958135048Swpaul 1959135048Swpaulstatic void 1960135048Swpaulvge_init(xsc) 1961135048Swpaul void *xsc; 1962135048Swpaul{ 1963135048Swpaul struct vge_softc *sc = xsc; 1964147256Sbrooks struct ifnet *ifp = sc->vge_ifp; 1965135048Swpaul struct mii_data *mii; 1966135048Swpaul int i; 1967135048Swpaul 1968135048Swpaul VGE_LOCK(sc); 1969135048Swpaul mii = device_get_softc(sc->vge_miibus); 1970135048Swpaul 1971135048Swpaul /* 1972135048Swpaul * Cancel pending I/O and free all RX/TX buffers. 1973135048Swpaul */ 1974135048Swpaul vge_stop(sc); 1975135048Swpaul vge_reset(sc); 1976135048Swpaul 1977135048Swpaul /* 1978135048Swpaul * Initialize the RX and TX descriptors and mbufs. 1979135048Swpaul */ 1980135048Swpaul 1981135048Swpaul vge_rx_list_init(sc); 1982135048Swpaul vge_tx_list_init(sc); 1983135048Swpaul 1984135048Swpaul /* Set our station address */ 1985135048Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 1986147256Sbrooks CSR_WRITE_1(sc, VGE_PAR0 + i, IFP2ENADDR(sc->vge_ifp)[i]); 1987135048Swpaul 1988135048Swpaul /* 1989135048Swpaul * Set receive FIFO threshold. Also allow transmission and 1990135048Swpaul * reception of VLAN tagged frames. 1991135048Swpaul */ 1992135048Swpaul CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1993135048Swpaul CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1994135048Swpaul 1995135048Swpaul /* Set DMA burst length */ 1996135048Swpaul CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1997135048Swpaul CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1998135048Swpaul 1999135048Swpaul CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 2000135048Swpaul 2001135048Swpaul /* Set collision backoff algorithm */ 2002135048Swpaul CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 2003135048Swpaul VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 2004135048Swpaul CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 2005135048Swpaul 2006135048Swpaul /* Disable LPSEL field in priority resolution */ 2007135048Swpaul CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 2008135048Swpaul 2009135048Swpaul /* 2010135048Swpaul * Load the addresses of the DMA queues into the chip. 2011135048Swpaul * Note that we only use one transmit queue. 2012135048Swpaul */ 2013135048Swpaul 2014135048Swpaul CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 2015135048Swpaul VGE_ADDR_LO(sc->vge_ldata.vge_tx_list_addr)); 2016135048Swpaul CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 2017135048Swpaul 2018135048Swpaul CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 2019135048Swpaul VGE_ADDR_LO(sc->vge_ldata.vge_rx_list_addr)); 2020135048Swpaul CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 2021135048Swpaul CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 2022135048Swpaul 2023135048Swpaul /* Enable and wake up the RX descriptor queue */ 2024135048Swpaul CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 2025135048Swpaul CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 2026135048Swpaul 2027135048Swpaul /* Enable the TX descriptor queue */ 2028135048Swpaul CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 2029135048Swpaul 2030135048Swpaul /* Set up the receive filter -- allow large frames for VLANs. */ 2031135048Swpaul CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 2032135048Swpaul 2033135048Swpaul /* If we want promiscuous mode, set the allframes bit. */ 2034135048Swpaul if (ifp->if_flags & IFF_PROMISC) { 2035135048Swpaul CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 2036135048Swpaul } 2037135048Swpaul 2038135048Swpaul /* Set capture broadcast bit to capture broadcast frames. */ 2039135048Swpaul if (ifp->if_flags & IFF_BROADCAST) { 2040135048Swpaul CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 2041135048Swpaul } 2042135048Swpaul 2043135048Swpaul /* Set multicast bit to capture multicast frames. */ 2044135048Swpaul if (ifp->if_flags & IFF_MULTICAST) { 2045135048Swpaul CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 2046135048Swpaul } 2047135048Swpaul 2048135048Swpaul /* Init the cam filter. */ 2049135048Swpaul vge_cam_clear(sc); 2050135048Swpaul 2051135048Swpaul /* Init the multicast filter. */ 2052135048Swpaul vge_setmulti(sc); 2053135048Swpaul 2054135048Swpaul /* Enable flow control */ 2055135048Swpaul 2056135048Swpaul CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 2057135048Swpaul 2058135048Swpaul /* Enable jumbo frame reception (if desired) */ 2059135048Swpaul 2060135048Swpaul /* Start the MAC. */ 2061135048Swpaul CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 2062135048Swpaul CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 2063135048Swpaul CSR_WRITE_1(sc, VGE_CRS0, 2064135048Swpaul VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 2065135048Swpaul 2066135048Swpaul /* 2067135048Swpaul * Configure one-shot timer for microsecond 2068135048Swpaul * resulution and load it for 500 usecs. 2069135048Swpaul */ 2070135048Swpaul CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 2071135048Swpaul CSR_WRITE_2(sc, VGE_SSTIMER, 400); 2072135048Swpaul 2073135048Swpaul /* 2074135048Swpaul * Configure interrupt moderation for receive. Enable 2075135048Swpaul * the holdoff counter and load it, and set the RX 2076135048Swpaul * suppression count to the number of descriptors we 2077135048Swpaul * want to allow before triggering an interrupt. 2078135048Swpaul * The holdoff timer is in units of 20 usecs. 2079135048Swpaul */ 2080135048Swpaul 2081135048Swpaul#ifdef notyet 2082135048Swpaul CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 2083135048Swpaul /* Select the interrupt holdoff timer page. */ 2084135048Swpaul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2085135048Swpaul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 2086135048Swpaul CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 2087135048Swpaul 2088135048Swpaul /* Enable use of the holdoff timer. */ 2089135048Swpaul CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 2090135048Swpaul CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 2091135048Swpaul 2092135048Swpaul /* Select the RX suppression threshold page. */ 2093135048Swpaul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2094135048Swpaul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 2095135048Swpaul CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 2096135048Swpaul 2097135048Swpaul /* Restore the page select bits. */ 2098135048Swpaul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2099135048Swpaul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 2100135048Swpaul#endif 2101135048Swpaul 2102135048Swpaul#ifdef DEVICE_POLLING 2103135048Swpaul /* 2104135048Swpaul * Disable interrupts if we are polling. 2105135048Swpaul */ 2106135048Swpaul if (ifp->if_flags & IFF_POLLING) { 2107135048Swpaul CSR_WRITE_4(sc, VGE_IMR, 0); 2108135048Swpaul CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2109135048Swpaul } else /* otherwise ... */ 2110135048Swpaul#endif /* DEVICE_POLLING */ 2111135048Swpaul { 2112135048Swpaul /* 2113135048Swpaul * Enable interrupts. 2114135048Swpaul */ 2115135048Swpaul CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2116135048Swpaul CSR_WRITE_4(sc, VGE_ISR, 0); 2117135048Swpaul CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2118135048Swpaul } 2119135048Swpaul 2120135048Swpaul mii_mediachg(mii); 2121135048Swpaul 2122135048Swpaul ifp->if_flags |= IFF_RUNNING; 2123135048Swpaul ifp->if_flags &= ~IFF_OACTIVE; 2124135048Swpaul 2125135048Swpaul sc->vge_if_flags = 0; 2126135048Swpaul sc->vge_link = 0; 2127135048Swpaul 2128135048Swpaul VGE_UNLOCK(sc); 2129135048Swpaul 2130135048Swpaul return; 2131135048Swpaul} 2132135048Swpaul 2133135048Swpaul/* 2134135048Swpaul * Set media options. 2135135048Swpaul */ 2136135048Swpaulstatic int 2137135048Swpaulvge_ifmedia_upd(ifp) 2138135048Swpaul struct ifnet *ifp; 2139135048Swpaul{ 2140135048Swpaul struct vge_softc *sc; 2141135048Swpaul struct mii_data *mii; 2142135048Swpaul 2143135048Swpaul sc = ifp->if_softc; 2144135048Swpaul mii = device_get_softc(sc->vge_miibus); 2145135048Swpaul mii_mediachg(mii); 2146135048Swpaul 2147135048Swpaul return (0); 2148135048Swpaul} 2149135048Swpaul 2150135048Swpaul/* 2151135048Swpaul * Report current media status. 2152135048Swpaul */ 2153135048Swpaulstatic void 2154135048Swpaulvge_ifmedia_sts(ifp, ifmr) 2155135048Swpaul struct ifnet *ifp; 2156135048Swpaul struct ifmediareq *ifmr; 2157135048Swpaul{ 2158135048Swpaul struct vge_softc *sc; 2159135048Swpaul struct mii_data *mii; 2160135048Swpaul 2161135048Swpaul sc = ifp->if_softc; 2162135048Swpaul mii = device_get_softc(sc->vge_miibus); 2163135048Swpaul 2164135048Swpaul mii_pollstat(mii); 2165135048Swpaul ifmr->ifm_active = mii->mii_media_active; 2166135048Swpaul ifmr->ifm_status = mii->mii_media_status; 2167135048Swpaul 2168135048Swpaul return; 2169135048Swpaul} 2170135048Swpaul 2171135048Swpaulstatic void 2172135048Swpaulvge_miibus_statchg(dev) 2173135048Swpaul device_t dev; 2174135048Swpaul{ 2175135048Swpaul struct vge_softc *sc; 2176135048Swpaul struct mii_data *mii; 2177135048Swpaul struct ifmedia_entry *ife; 2178135048Swpaul 2179135048Swpaul sc = device_get_softc(dev); 2180135048Swpaul mii = device_get_softc(sc->vge_miibus); 2181135048Swpaul ife = mii->mii_media.ifm_cur; 2182135048Swpaul 2183135048Swpaul /* 2184135048Swpaul * If the user manually selects a media mode, we need to turn 2185135048Swpaul * on the forced MAC mode bit in the DIAGCTL register. If the 2186135048Swpaul * user happens to choose a full duplex mode, we also need to 2187135048Swpaul * set the 'force full duplex' bit. This applies only to 2188135048Swpaul * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2189135048Swpaul * mode is disabled, and in 1000baseT mode, full duplex is 2190135048Swpaul * always implied, so we turn on the forced mode bit but leave 2191135048Swpaul * the FDX bit cleared. 2192135048Swpaul */ 2193135048Swpaul 2194135048Swpaul switch (IFM_SUBTYPE(ife->ifm_media)) { 2195135048Swpaul case IFM_AUTO: 2196135048Swpaul CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2197135048Swpaul CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2198135048Swpaul break; 2199135048Swpaul case IFM_1000_T: 2200135048Swpaul CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2201135048Swpaul CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2202135048Swpaul break; 2203135048Swpaul case IFM_100_TX: 2204135048Swpaul case IFM_10_T: 2205135048Swpaul CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2206135048Swpaul if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2207135048Swpaul CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2208135048Swpaul } else { 2209135048Swpaul CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2210135048Swpaul } 2211135048Swpaul break; 2212135048Swpaul default: 2213135048Swpaul device_printf(dev, "unknown media type: %x\n", 2214135048Swpaul IFM_SUBTYPE(ife->ifm_media)); 2215135048Swpaul break; 2216135048Swpaul } 2217135048Swpaul 2218135048Swpaul return; 2219135048Swpaul} 2220135048Swpaul 2221135048Swpaulstatic int 2222135048Swpaulvge_ioctl(ifp, command, data) 2223135048Swpaul struct ifnet *ifp; 2224135048Swpaul u_long command; 2225135048Swpaul caddr_t data; 2226135048Swpaul{ 2227135048Swpaul struct vge_softc *sc = ifp->if_softc; 2228135048Swpaul struct ifreq *ifr = (struct ifreq *) data; 2229135048Swpaul struct mii_data *mii; 2230135048Swpaul int error = 0; 2231135048Swpaul 2232135048Swpaul switch (command) { 2233135048Swpaul case SIOCSIFMTU: 2234135048Swpaul if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2235135048Swpaul error = EINVAL; 2236135048Swpaul ifp->if_mtu = ifr->ifr_mtu; 2237135048Swpaul break; 2238135048Swpaul case SIOCSIFFLAGS: 2239135048Swpaul if (ifp->if_flags & IFF_UP) { 2240135048Swpaul if (ifp->if_flags & IFF_RUNNING && 2241135048Swpaul ifp->if_flags & IFF_PROMISC && 2242135048Swpaul !(sc->vge_if_flags & IFF_PROMISC)) { 2243135048Swpaul CSR_SETBIT_1(sc, VGE_RXCTL, 2244135048Swpaul VGE_RXCTL_RX_PROMISC); 2245135048Swpaul vge_setmulti(sc); 2246135048Swpaul } else if (ifp->if_flags & IFF_RUNNING && 2247135048Swpaul !(ifp->if_flags & IFF_PROMISC) && 2248135048Swpaul sc->vge_if_flags & IFF_PROMISC) { 2249135048Swpaul CSR_CLRBIT_1(sc, VGE_RXCTL, 2250135048Swpaul VGE_RXCTL_RX_PROMISC); 2251135048Swpaul vge_setmulti(sc); 2252135048Swpaul } else 2253135048Swpaul vge_init(sc); 2254135048Swpaul } else { 2255135048Swpaul if (ifp->if_flags & IFF_RUNNING) 2256135048Swpaul vge_stop(sc); 2257135048Swpaul } 2258135048Swpaul sc->vge_if_flags = ifp->if_flags; 2259135048Swpaul break; 2260135048Swpaul case SIOCADDMULTI: 2261135048Swpaul case SIOCDELMULTI: 2262135048Swpaul vge_setmulti(sc); 2263135048Swpaul break; 2264135048Swpaul case SIOCGIFMEDIA: 2265135048Swpaul case SIOCSIFMEDIA: 2266135048Swpaul mii = device_get_softc(sc->vge_miibus); 2267135048Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2268135048Swpaul break; 2269135048Swpaul case SIOCSIFCAP: 2270135048Swpaul#ifdef IFCAP_POLLING 2271135048Swpaul ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_POLLING); 2272135048Swpaul#else 2273135048Swpaul ifp->if_capenable &= ~(IFCAP_HWCSUM); 2274135048Swpaul#endif 2275135048Swpaul ifp->if_capenable |= 2276135048Swpaul#ifdef IFCAP_POLLING 2277135048Swpaul ifr->ifr_reqcap & (IFCAP_HWCSUM | IFCAP_POLLING); 2278135048Swpaul#else 2279135048Swpaul ifr->ifr_reqcap & (IFCAP_HWCSUM); 2280135048Swpaul#endif 2281135048Swpaul if (ifp->if_capenable & IFCAP_TXCSUM) 2282135048Swpaul ifp->if_hwassist = VGE_CSUM_FEATURES; 2283135048Swpaul else 2284135048Swpaul ifp->if_hwassist = 0; 2285135048Swpaul if (ifp->if_flags & IFF_RUNNING) 2286135048Swpaul vge_init(sc); 2287135048Swpaul break; 2288135048Swpaul default: 2289135048Swpaul error = ether_ioctl(ifp, command, data); 2290135048Swpaul break; 2291135048Swpaul } 2292135048Swpaul 2293135048Swpaul return (error); 2294135048Swpaul} 2295135048Swpaul 2296135048Swpaulstatic void 2297135048Swpaulvge_watchdog(ifp) 2298135048Swpaul struct ifnet *ifp; 2299135048Swpaul{ 2300135048Swpaul struct vge_softc *sc; 2301135048Swpaul 2302135048Swpaul sc = ifp->if_softc; 2303135048Swpaul VGE_LOCK(sc); 2304135048Swpaul printf("vge%d: watchdog timeout\n", sc->vge_unit); 2305135048Swpaul ifp->if_oerrors++; 2306135048Swpaul 2307135048Swpaul vge_txeof(sc); 2308135048Swpaul vge_rxeof(sc); 2309135048Swpaul 2310135048Swpaul vge_init(sc); 2311135048Swpaul 2312135048Swpaul VGE_UNLOCK(sc); 2313135048Swpaul 2314135048Swpaul return; 2315135048Swpaul} 2316135048Swpaul 2317135048Swpaul/* 2318135048Swpaul * Stop the adapter and free any mbufs allocated to the 2319135048Swpaul * RX and TX lists. 2320135048Swpaul */ 2321135048Swpaulstatic void 2322135048Swpaulvge_stop(sc) 2323135048Swpaul struct vge_softc *sc; 2324135048Swpaul{ 2325135048Swpaul register int i; 2326135048Swpaul struct ifnet *ifp; 2327135048Swpaul 2328135048Swpaul VGE_LOCK(sc); 2329147256Sbrooks ifp = sc->vge_ifp; 2330135048Swpaul ifp->if_timer = 0; 2331135048Swpaul 2332135048Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2333135048Swpaul#ifdef DEVICE_POLLING 2334135048Swpaul ether_poll_deregister(ifp); 2335135048Swpaul#endif /* DEVICE_POLLING */ 2336135048Swpaul 2337135048Swpaul CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2338135048Swpaul CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2339135048Swpaul CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2340135048Swpaul CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2341135048Swpaul CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2342135048Swpaul CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2343135048Swpaul 2344135048Swpaul if (sc->vge_head != NULL) { 2345135048Swpaul m_freem(sc->vge_head); 2346135048Swpaul sc->vge_head = sc->vge_tail = NULL; 2347135048Swpaul } 2348135048Swpaul 2349135048Swpaul /* Free the TX list buffers. */ 2350135048Swpaul 2351135048Swpaul for (i = 0; i < VGE_TX_DESC_CNT; i++) { 2352135048Swpaul if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 2353135048Swpaul bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2354135048Swpaul sc->vge_ldata.vge_tx_dmamap[i]); 2355135048Swpaul m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 2356135048Swpaul sc->vge_ldata.vge_tx_mbuf[i] = NULL; 2357135048Swpaul } 2358135048Swpaul } 2359135048Swpaul 2360135048Swpaul /* Free the RX list buffers. */ 2361135048Swpaul 2362135048Swpaul for (i = 0; i < VGE_RX_DESC_CNT; i++) { 2363135048Swpaul if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 2364135048Swpaul bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2365135048Swpaul sc->vge_ldata.vge_rx_dmamap[i]); 2366135048Swpaul m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 2367135048Swpaul sc->vge_ldata.vge_rx_mbuf[i] = NULL; 2368135048Swpaul } 2369135048Swpaul } 2370135048Swpaul 2371135048Swpaul VGE_UNLOCK(sc); 2372135048Swpaul 2373135048Swpaul return; 2374135048Swpaul} 2375135048Swpaul 2376135048Swpaul/* 2377135048Swpaul * Device suspend routine. Stop the interface and save some PCI 2378135048Swpaul * settings in case the BIOS doesn't restore them properly on 2379135048Swpaul * resume. 2380135048Swpaul */ 2381135048Swpaulstatic int 2382135048Swpaulvge_suspend(dev) 2383135048Swpaul device_t dev; 2384135048Swpaul{ 2385135048Swpaul struct vge_softc *sc; 2386135048Swpaul 2387135048Swpaul sc = device_get_softc(dev); 2388135048Swpaul 2389135048Swpaul vge_stop(sc); 2390135048Swpaul 2391135048Swpaul sc->suspended = 1; 2392135048Swpaul 2393135048Swpaul return (0); 2394135048Swpaul} 2395135048Swpaul 2396135048Swpaul/* 2397135048Swpaul * Device resume routine. Restore some PCI settings in case the BIOS 2398135048Swpaul * doesn't, re-enable busmastering, and restart the interface if 2399135048Swpaul * appropriate. 2400135048Swpaul */ 2401135048Swpaulstatic int 2402135048Swpaulvge_resume(dev) 2403135048Swpaul device_t dev; 2404135048Swpaul{ 2405135048Swpaul struct vge_softc *sc; 2406135048Swpaul struct ifnet *ifp; 2407135048Swpaul 2408135048Swpaul sc = device_get_softc(dev); 2409147256Sbrooks ifp = sc->vge_ifp; 2410135048Swpaul 2411135048Swpaul /* reenable busmastering */ 2412135048Swpaul pci_enable_busmaster(dev); 2413135048Swpaul pci_enable_io(dev, SYS_RES_MEMORY); 2414135048Swpaul 2415135048Swpaul /* reinitialize interface if necessary */ 2416135048Swpaul if (ifp->if_flags & IFF_UP) 2417135048Swpaul vge_init(sc); 2418135048Swpaul 2419135048Swpaul sc->suspended = 0; 2420135048Swpaul 2421135048Swpaul return (0); 2422135048Swpaul} 2423135048Swpaul 2424135048Swpaul/* 2425135048Swpaul * Stop all chip I/O so that the kernel's probe routines don't 2426135048Swpaul * get confused by errant DMAs when rebooting. 2427135048Swpaul */ 2428135048Swpaulstatic void 2429135048Swpaulvge_shutdown(dev) 2430135048Swpaul device_t dev; 2431135048Swpaul{ 2432135048Swpaul struct vge_softc *sc; 2433135048Swpaul 2434135048Swpaul sc = device_get_softc(dev); 2435135048Swpaul 2436135048Swpaul vge_stop(sc); 2437135048Swpaul} 2438