if_ural.c revision 192502
1/* $FreeBSD: head/sys/dev/usb/wlan/if_ural.c 192502 2009-05-21 01:48:42Z thompsa $ */ 2 3/*- 4 * Copyright (c) 2005, 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Copyright (c) 2006, 2008 8 * Hans Petter Selasky <hselasky@FreeBSD.org> 9 * 10 * Permission to use, copy, modify, and distribute this software for any 11 * purpose with or without fee is hereby granted, provided that the above 12 * copyright notice and this permission notice appear in all copies. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 18 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 19 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 20 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 21 */ 22 23#include <sys/cdefs.h> 24__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_ural.c 192502 2009-05-21 01:48:42Z thompsa $"); 25 26/*- 27 * Ralink Technology RT2500USB chipset driver 28 * http://www.ralinktech.com/ 29 */ 30 31#include <sys/param.h> 32#include <sys/sockio.h> 33#include <sys/sysctl.h> 34#include <sys/lock.h> 35#include <sys/mutex.h> 36#include <sys/mbuf.h> 37#include <sys/kernel.h> 38#include <sys/socket.h> 39#include <sys/systm.h> 40#include <sys/malloc.h> 41#include <sys/module.h> 42#include <sys/bus.h> 43#include <sys/endian.h> 44#include <sys/kdb.h> 45 46#include <machine/bus.h> 47#include <machine/resource.h> 48#include <sys/rman.h> 49 50#include <net/bpf.h> 51#include <net/if.h> 52#include <net/if_arp.h> 53#include <net/ethernet.h> 54#include <net/if_dl.h> 55#include <net/if_media.h> 56#include <net/if_types.h> 57 58#ifdef INET 59#include <netinet/in.h> 60#include <netinet/in_systm.h> 61#include <netinet/in_var.h> 62#include <netinet/if_ether.h> 63#include <netinet/ip.h> 64#endif 65 66#include <net80211/ieee80211_var.h> 67#include <net80211/ieee80211_regdomain.h> 68#include <net80211/ieee80211_radiotap.h> 69#include <net80211/ieee80211_amrr.h> 70 71#define USB_DEBUG_VAR ural_debug 72 73#include <dev/usb/usb.h> 74#include <dev/usb/usb_error.h> 75#include <dev/usb/usb_core.h> 76#include <dev/usb/usb_lookup.h> 77#include <dev/usb/usb_debug.h> 78#include <dev/usb/usb_request.h> 79#include <dev/usb/usb_busdma.h> 80#include <dev/usb/usb_util.h> 81#include "usbdevs.h" 82 83 84#include <dev/usb/wlan/if_uralreg.h> 85#include <dev/usb/wlan/if_uralvar.h> 86 87#if USB_DEBUG 88static int ural_debug = 0; 89 90SYSCTL_NODE(_hw_usb, OID_AUTO, ural, CTLFLAG_RW, 0, "USB ural"); 91SYSCTL_INT(_hw_usb_ural, OID_AUTO, debug, CTLFLAG_RW, &ural_debug, 0, 92 "Debug level"); 93#endif 94 95#define URAL_RSSI(rssi) \ 96 ((rssi) > (RAL_NOISE_FLOOR + RAL_RSSI_CORR) ? \ 97 ((rssi) - (RAL_NOISE_FLOOR + RAL_RSSI_CORR)) : 0) 98 99/* various supported device vendors/products */ 100static const struct usb2_device_id ural_devs[] = { 101 { USB_VP(USB_VENDOR_ASUS, USB_PRODUCT_ASUS_WL167G) }, 102 { USB_VP(USB_VENDOR_ASUS, USB_PRODUCT_RALINK_RT2570) }, 103 { USB_VP(USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D7050) }, 104 { USB_VP(USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F5D7051) }, 105 { USB_VP(USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_HU200TS) }, 106 { USB_VP(USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_WUSB54G) }, 107 { USB_VP(USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_WUSB54GP) }, 108 { USB_VP(USB_VENDOR_CONCEPTRONIC2, USB_PRODUCT_CONCEPTRONIC2_C54RU) }, 109 { USB_VP(USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DWLG122) }, 110 { USB_VP(USB_VENDOR_GIGABYTE, USB_PRODUCT_GIGABYTE_GN54G) }, 111 { USB_VP(USB_VENDOR_GIGABYTE, USB_PRODUCT_GIGABYTE_GNWBKG) }, 112 { USB_VP(USB_VENDOR_GUILLEMOT, USB_PRODUCT_GUILLEMOT_HWGUSB254) }, 113 { USB_VP(USB_VENDOR_MELCO, USB_PRODUCT_MELCO_KG54) }, 114 { USB_VP(USB_VENDOR_MELCO, USB_PRODUCT_MELCO_KG54AI) }, 115 { USB_VP(USB_VENDOR_MELCO, USB_PRODUCT_MELCO_KG54YB) }, 116 { USB_VP(USB_VENDOR_MELCO, USB_PRODUCT_MELCO_NINWIFI) }, 117 { USB_VP(USB_VENDOR_MSI, USB_PRODUCT_MSI_RT2570) }, 118 { USB_VP(USB_VENDOR_MSI, USB_PRODUCT_MSI_RT2570_2) }, 119 { USB_VP(USB_VENDOR_MSI, USB_PRODUCT_MSI_RT2570_3) }, 120 { USB_VP(USB_VENDOR_NOVATECH, USB_PRODUCT_NOVATECH_NV902) }, 121 { USB_VP(USB_VENDOR_RALINK, USB_PRODUCT_RALINK_RT2570) }, 122 { USB_VP(USB_VENDOR_RALINK, USB_PRODUCT_RALINK_RT2570_2) }, 123 { USB_VP(USB_VENDOR_RALINK, USB_PRODUCT_RALINK_RT2570_3) }, 124 { USB_VP(USB_VENDOR_SIEMENS2, USB_PRODUCT_SIEMENS2_WL54G) }, 125 { USB_VP(USB_VENDOR_SMC, USB_PRODUCT_SMC_2862WG) }, 126 { USB_VP(USB_VENDOR_SPHAIRON, USB_PRODUCT_SPHAIRON_UB801R) }, 127 { USB_VP(USB_VENDOR_SURECOM, USB_PRODUCT_SURECOM_RT2570) }, 128 { USB_VP(USB_VENDOR_VTECH, USB_PRODUCT_VTECH_RT2570) }, 129 { USB_VP(USB_VENDOR_ZINWELL, USB_PRODUCT_ZINWELL_RT2570) }, 130}; 131 132static usb2_callback_t ural_bulk_read_callback; 133static usb2_callback_t ural_bulk_write_callback; 134 135static usb2_error_t ural_do_request(struct ural_softc *sc, 136 struct usb2_device_request *req, void *data); 137static struct ieee80211vap *ural_vap_create(struct ieee80211com *, 138 const char name[IFNAMSIZ], int unit, int opmode, 139 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 140 const uint8_t mac[IEEE80211_ADDR_LEN]); 141static void ural_vap_delete(struct ieee80211vap *); 142static void ural_tx_free(struct ural_tx_data *, int); 143static void ural_setup_tx_list(struct ural_softc *); 144static void ural_unsetup_tx_list(struct ural_softc *); 145static int ural_newstate(struct ieee80211vap *, 146 enum ieee80211_state, int); 147static void ural_setup_tx_desc(struct ural_softc *, 148 struct ural_tx_desc *, uint32_t, int, int); 149static int ural_tx_bcn(struct ural_softc *, struct mbuf *, 150 struct ieee80211_node *); 151static int ural_tx_mgt(struct ural_softc *, struct mbuf *, 152 struct ieee80211_node *); 153static int ural_tx_data(struct ural_softc *, struct mbuf *, 154 struct ieee80211_node *); 155static void ural_start(struct ifnet *); 156static int ural_ioctl(struct ifnet *, u_long, caddr_t); 157static void ural_set_testmode(struct ural_softc *); 158static void ural_eeprom_read(struct ural_softc *, uint16_t, void *, 159 int); 160static uint16_t ural_read(struct ural_softc *, uint16_t); 161static void ural_read_multi(struct ural_softc *, uint16_t, void *, 162 int); 163static void ural_write(struct ural_softc *, uint16_t, uint16_t); 164static void ural_write_multi(struct ural_softc *, uint16_t, void *, 165 int) __unused; 166static void ural_bbp_write(struct ural_softc *, uint8_t, uint8_t); 167static uint8_t ural_bbp_read(struct ural_softc *, uint8_t); 168static void ural_rf_write(struct ural_softc *, uint8_t, uint32_t); 169static struct ieee80211_node *ural_node_alloc(struct ieee80211vap *, 170 const uint8_t mac[IEEE80211_ADDR_LEN]); 171static void ural_newassoc(struct ieee80211_node *, int); 172static void ural_scan_start(struct ieee80211com *); 173static void ural_scan_end(struct ieee80211com *); 174static void ural_set_channel(struct ieee80211com *); 175static void ural_set_chan(struct ural_softc *, 176 struct ieee80211_channel *); 177static void ural_disable_rf_tune(struct ural_softc *); 178static void ural_enable_tsf_sync(struct ural_softc *); 179static void ural_enable_tsf(struct ural_softc *); 180static void ural_update_slot(struct ifnet *); 181static void ural_set_txpreamble(struct ural_softc *); 182static void ural_set_basicrates(struct ural_softc *, 183 const struct ieee80211_channel *); 184static void ural_set_bssid(struct ural_softc *, const uint8_t *); 185static void ural_set_macaddr(struct ural_softc *, uint8_t *); 186static void ural_update_promisc(struct ifnet *); 187static void ural_setpromisc(struct ural_softc *); 188static const char *ural_get_rf(int); 189static void ural_read_eeprom(struct ural_softc *); 190static int ural_bbp_init(struct ural_softc *); 191static void ural_set_txantenna(struct ural_softc *, int); 192static void ural_set_rxantenna(struct ural_softc *, int); 193static void ural_init_locked(struct ural_softc *); 194static void ural_init(void *); 195static void ural_stop(struct ural_softc *); 196static int ural_raw_xmit(struct ieee80211_node *, struct mbuf *, 197 const struct ieee80211_bpf_params *); 198static void ural_amrr_start(struct ural_softc *, 199 struct ieee80211_node *); 200static void ural_amrr_timeout(void *); 201static void ural_amrr_task(void *, int); 202static int ural_pause(struct ural_softc *sc, int timeout); 203 204/* 205 * Default values for MAC registers; values taken from the reference driver. 206 */ 207static const struct { 208 uint16_t reg; 209 uint16_t val; 210} ural_def_mac[] = { 211 { RAL_TXRX_CSR5, 0x8c8d }, 212 { RAL_TXRX_CSR6, 0x8b8a }, 213 { RAL_TXRX_CSR7, 0x8687 }, 214 { RAL_TXRX_CSR8, 0x0085 }, 215 { RAL_MAC_CSR13, 0x1111 }, 216 { RAL_MAC_CSR14, 0x1e11 }, 217 { RAL_TXRX_CSR21, 0xe78f }, 218 { RAL_MAC_CSR9, 0xff1d }, 219 { RAL_MAC_CSR11, 0x0002 }, 220 { RAL_MAC_CSR22, 0x0053 }, 221 { RAL_MAC_CSR15, 0x0000 }, 222 { RAL_MAC_CSR8, RAL_FRAME_SIZE }, 223 { RAL_TXRX_CSR19, 0x0000 }, 224 { RAL_TXRX_CSR18, 0x005a }, 225 { RAL_PHY_CSR2, 0x0000 }, 226 { RAL_TXRX_CSR0, 0x1ec0 }, 227 { RAL_PHY_CSR4, 0x000f } 228}; 229 230/* 231 * Default values for BBP registers; values taken from the reference driver. 232 */ 233static const struct { 234 uint8_t reg; 235 uint8_t val; 236} ural_def_bbp[] = { 237 { 3, 0x02 }, 238 { 4, 0x19 }, 239 { 14, 0x1c }, 240 { 15, 0x30 }, 241 { 16, 0xac }, 242 { 17, 0x48 }, 243 { 18, 0x18 }, 244 { 19, 0xff }, 245 { 20, 0x1e }, 246 { 21, 0x08 }, 247 { 22, 0x08 }, 248 { 23, 0x08 }, 249 { 24, 0x80 }, 250 { 25, 0x50 }, 251 { 26, 0x08 }, 252 { 27, 0x23 }, 253 { 30, 0x10 }, 254 { 31, 0x2b }, 255 { 32, 0xb9 }, 256 { 34, 0x12 }, 257 { 35, 0x50 }, 258 { 39, 0xc4 }, 259 { 40, 0x02 }, 260 { 41, 0x60 }, 261 { 53, 0x10 }, 262 { 54, 0x18 }, 263 { 56, 0x08 }, 264 { 57, 0x10 }, 265 { 58, 0x08 }, 266 { 61, 0x60 }, 267 { 62, 0x10 }, 268 { 75, 0xff } 269}; 270 271/* 272 * Default values for RF register R2 indexed by channel numbers. 273 */ 274static const uint32_t ural_rf2522_r2[] = { 275 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, 276 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e 277}; 278 279static const uint32_t ural_rf2523_r2[] = { 280 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 281 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 282}; 283 284static const uint32_t ural_rf2524_r2[] = { 285 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 286 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 287}; 288 289static const uint32_t ural_rf2525_r2[] = { 290 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, 291 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 292}; 293 294static const uint32_t ural_rf2525_hi_r2[] = { 295 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, 296 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e 297}; 298 299static const uint32_t ural_rf2525e_r2[] = { 300 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, 301 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b 302}; 303 304static const uint32_t ural_rf2526_hi_r2[] = { 305 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, 306 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 307}; 308 309static const uint32_t ural_rf2526_r2[] = { 310 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, 311 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d 312}; 313 314/* 315 * For dual-band RF, RF registers R1 and R4 also depend on channel number; 316 * values taken from the reference driver. 317 */ 318static const struct { 319 uint8_t chan; 320 uint32_t r1; 321 uint32_t r2; 322 uint32_t r4; 323} ural_rf5222[] = { 324 { 1, 0x08808, 0x0044d, 0x00282 }, 325 { 2, 0x08808, 0x0044e, 0x00282 }, 326 { 3, 0x08808, 0x0044f, 0x00282 }, 327 { 4, 0x08808, 0x00460, 0x00282 }, 328 { 5, 0x08808, 0x00461, 0x00282 }, 329 { 6, 0x08808, 0x00462, 0x00282 }, 330 { 7, 0x08808, 0x00463, 0x00282 }, 331 { 8, 0x08808, 0x00464, 0x00282 }, 332 { 9, 0x08808, 0x00465, 0x00282 }, 333 { 10, 0x08808, 0x00466, 0x00282 }, 334 { 11, 0x08808, 0x00467, 0x00282 }, 335 { 12, 0x08808, 0x00468, 0x00282 }, 336 { 13, 0x08808, 0x00469, 0x00282 }, 337 { 14, 0x08808, 0x0046b, 0x00286 }, 338 339 { 36, 0x08804, 0x06225, 0x00287 }, 340 { 40, 0x08804, 0x06226, 0x00287 }, 341 { 44, 0x08804, 0x06227, 0x00287 }, 342 { 48, 0x08804, 0x06228, 0x00287 }, 343 { 52, 0x08804, 0x06229, 0x00287 }, 344 { 56, 0x08804, 0x0622a, 0x00287 }, 345 { 60, 0x08804, 0x0622b, 0x00287 }, 346 { 64, 0x08804, 0x0622c, 0x00287 }, 347 348 { 100, 0x08804, 0x02200, 0x00283 }, 349 { 104, 0x08804, 0x02201, 0x00283 }, 350 { 108, 0x08804, 0x02202, 0x00283 }, 351 { 112, 0x08804, 0x02203, 0x00283 }, 352 { 116, 0x08804, 0x02204, 0x00283 }, 353 { 120, 0x08804, 0x02205, 0x00283 }, 354 { 124, 0x08804, 0x02206, 0x00283 }, 355 { 128, 0x08804, 0x02207, 0x00283 }, 356 { 132, 0x08804, 0x02208, 0x00283 }, 357 { 136, 0x08804, 0x02209, 0x00283 }, 358 { 140, 0x08804, 0x0220a, 0x00283 }, 359 360 { 149, 0x08808, 0x02429, 0x00281 }, 361 { 153, 0x08808, 0x0242b, 0x00281 }, 362 { 157, 0x08808, 0x0242d, 0x00281 }, 363 { 161, 0x08808, 0x0242f, 0x00281 } 364}; 365 366static const struct usb2_config ural_config[URAL_N_TRANSFER] = { 367 [URAL_BULK_WR] = { 368 .type = UE_BULK, 369 .endpoint = UE_ADDR_ANY, 370 .direction = UE_DIR_OUT, 371 .bufsize = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE + 4), 372 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 373 .callback = ural_bulk_write_callback, 374 .timeout = 5000, /* ms */ 375 }, 376 [URAL_BULK_RD] = { 377 .type = UE_BULK, 378 .endpoint = UE_ADDR_ANY, 379 .direction = UE_DIR_IN, 380 .bufsize = (RAL_FRAME_SIZE + RAL_RX_DESC_SIZE), 381 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 382 .callback = ural_bulk_read_callback, 383 }, 384}; 385 386static device_probe_t ural_match; 387static device_attach_t ural_attach; 388static device_detach_t ural_detach; 389 390static device_method_t ural_methods[] = { 391 /* Device interface */ 392 DEVMETHOD(device_probe, ural_match), 393 DEVMETHOD(device_attach, ural_attach), 394 DEVMETHOD(device_detach, ural_detach), 395 396 { 0, 0 } 397}; 398 399static driver_t ural_driver = { 400 .name = "ural", 401 .methods = ural_methods, 402 .size = sizeof(struct ural_softc), 403}; 404 405static devclass_t ural_devclass; 406 407DRIVER_MODULE(ural, uhub, ural_driver, ural_devclass, NULL, 0); 408MODULE_DEPEND(ural, usb, 1, 1, 1); 409MODULE_DEPEND(ural, wlan, 1, 1, 1); 410MODULE_DEPEND(ural, wlan_amrr, 1, 1, 1); 411 412static int 413ural_match(device_t self) 414{ 415 struct usb2_attach_arg *uaa = device_get_ivars(self); 416 417 if (uaa->usb_mode != USB_MODE_HOST) 418 return (ENXIO); 419 if (uaa->info.bConfigIndex != 0) 420 return (ENXIO); 421 if (uaa->info.bIfaceIndex != RAL_IFACE_INDEX) 422 return (ENXIO); 423 424 return (usb2_lookup_id_by_uaa(ural_devs, sizeof(ural_devs), uaa)); 425} 426 427static int 428ural_attach(device_t self) 429{ 430 struct usb2_attach_arg *uaa = device_get_ivars(self); 431 struct ural_softc *sc = device_get_softc(self); 432 struct ifnet *ifp; 433 struct ieee80211com *ic; 434 uint8_t iface_index, bands; 435 int error; 436 437 device_set_usb2_desc(self); 438 sc->sc_udev = uaa->device; 439 sc->sc_dev = self; 440 441 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 442 MTX_NETWORK_LOCK, MTX_DEF); 443 444 iface_index = RAL_IFACE_INDEX; 445 error = usb2_transfer_setup(uaa->device, 446 &iface_index, sc->sc_xfer, ural_config, 447 URAL_N_TRANSFER, sc, &sc->sc_mtx); 448 if (error) { 449 device_printf(self, "could not allocate USB transfers, " 450 "err=%s\n", usb2_errstr(error)); 451 goto detach; 452 } 453 454 RAL_LOCK(sc); 455 /* retrieve RT2570 rev. no */ 456 sc->asic_rev = ural_read(sc, RAL_MAC_CSR0); 457 458 /* retrieve MAC address and various other things from EEPROM */ 459 ural_read_eeprom(sc); 460 RAL_UNLOCK(sc); 461 462 device_printf(self, "MAC/BBP RT2570 (rev 0x%02x), RF %s\n", 463 sc->asic_rev, ural_get_rf(sc->rf_rev)); 464 465 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 466 if (ifp == NULL) { 467 device_printf(sc->sc_dev, "can not if_alloc()\n"); 468 goto detach; 469 } 470 ic = ifp->if_l2com; 471 472 ifp->if_softc = sc; 473 if_initname(ifp, "ural", device_get_unit(sc->sc_dev)); 474 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 475 ifp->if_init = ural_init; 476 ifp->if_ioctl = ural_ioctl; 477 ifp->if_start = ural_start; 478 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 479 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 480 IFQ_SET_READY(&ifp->if_snd); 481 482 ic->ic_ifp = ifp; 483 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 484 485 /* set device capabilities */ 486 ic->ic_caps = 487 IEEE80211_C_STA /* station mode supported */ 488 | IEEE80211_C_IBSS /* IBSS mode supported */ 489 | IEEE80211_C_MONITOR /* monitor mode supported */ 490 | IEEE80211_C_HOSTAP /* HostAp mode supported */ 491 | IEEE80211_C_TXPMGT /* tx power management */ 492 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 493 | IEEE80211_C_SHSLOT /* short slot time supported */ 494 | IEEE80211_C_BGSCAN /* bg scanning supported */ 495 | IEEE80211_C_WPA /* 802.11i */ 496 ; 497 498 bands = 0; 499 setbit(&bands, IEEE80211_MODE_11B); 500 setbit(&bands, IEEE80211_MODE_11G); 501 if (sc->rf_rev == RAL_RF_5222) 502 setbit(&bands, IEEE80211_MODE_11A); 503 ieee80211_init_channels(ic, NULL, &bands); 504 505 ieee80211_ifattach(ic, sc->sc_bssid); 506 ic->ic_update_promisc = ural_update_promisc; 507 ic->ic_newassoc = ural_newassoc; 508 ic->ic_raw_xmit = ural_raw_xmit; 509 ic->ic_node_alloc = ural_node_alloc; 510 ic->ic_scan_start = ural_scan_start; 511 ic->ic_scan_end = ural_scan_end; 512 ic->ic_set_channel = ural_set_channel; 513 514 ic->ic_vap_create = ural_vap_create; 515 ic->ic_vap_delete = ural_vap_delete; 516 517 ieee80211_radiotap_attach(ic, 518 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 519 RAL_TX_RADIOTAP_PRESENT, 520 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 521 RAL_RX_RADIOTAP_PRESENT); 522 523 if (bootverbose) 524 ieee80211_announce(ic); 525 526 return (0); 527 528detach: 529 ural_detach(self); 530 return (ENXIO); /* failure */ 531} 532 533static int 534ural_detach(device_t self) 535{ 536 struct ural_softc *sc = device_get_softc(self); 537 struct ifnet *ifp = sc->sc_ifp; 538 struct ieee80211com *ic; 539 540 /* stop all USB transfers */ 541 usb2_transfer_unsetup(sc->sc_xfer, URAL_N_TRANSFER); 542 543 /* free TX list, if any */ 544 RAL_LOCK(sc); 545 ural_unsetup_tx_list(sc); 546 RAL_UNLOCK(sc); 547 548 if (ifp) { 549 ic = ifp->if_l2com; 550 ieee80211_ifdetach(ic); 551 if_free(ifp); 552 } 553 mtx_destroy(&sc->sc_mtx); 554 555 return (0); 556} 557 558static usb2_error_t 559ural_do_request(struct ural_softc *sc, 560 struct usb2_device_request *req, void *data) 561{ 562 usb2_error_t err; 563 int ntries = 10; 564 565 while (ntries--) { 566 err = usb2_do_request_flags(sc->sc_udev, &sc->sc_mtx, 567 req, data, 0, NULL, 250 /* ms */); 568 if (err == 0) 569 break; 570 571 DPRINTFN(1, "Control request failed, %s (retrying)\n", 572 usb2_errstr(err)); 573 if (ural_pause(sc, hz / 100)) 574 break; 575 } 576 return (err); 577} 578 579static struct ieee80211vap * 580ural_vap_create(struct ieee80211com *ic, 581 const char name[IFNAMSIZ], int unit, int opmode, int flags, 582 const uint8_t bssid[IEEE80211_ADDR_LEN], 583 const uint8_t mac[IEEE80211_ADDR_LEN]) 584{ 585 struct ural_softc *sc = ic->ic_ifp->if_softc; 586 struct ural_vap *uvp; 587 struct ieee80211vap *vap; 588 589 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 590 return NULL; 591 uvp = (struct ural_vap *) malloc(sizeof(struct ural_vap), 592 M_80211_VAP, M_NOWAIT | M_ZERO); 593 if (uvp == NULL) 594 return NULL; 595 vap = &uvp->vap; 596 /* enable s/w bmiss handling for sta mode */ 597 ieee80211_vap_setup(ic, vap, name, unit, opmode, 598 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac); 599 600 /* override state transition machine */ 601 uvp->newstate = vap->iv_newstate; 602 vap->iv_newstate = ural_newstate; 603 604 usb2_callout_init_mtx(&uvp->amrr_ch, &sc->sc_mtx, 0); 605 TASK_INIT(&uvp->amrr_task, 0, ural_amrr_task, uvp); 606 ieee80211_amrr_init(&uvp->amrr, vap, 607 IEEE80211_AMRR_MIN_SUCCESS_THRESHOLD, 608 IEEE80211_AMRR_MAX_SUCCESS_THRESHOLD, 609 1000 /* 1 sec */); 610 611 /* complete setup */ 612 ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status); 613 ic->ic_opmode = opmode; 614 return vap; 615} 616 617static void 618ural_vap_delete(struct ieee80211vap *vap) 619{ 620 struct ural_vap *uvp = URAL_VAP(vap); 621 struct ieee80211com *ic = vap->iv_ic; 622 623 usb2_callout_drain(&uvp->amrr_ch); 624 ieee80211_draintask(ic, &uvp->amrr_task); 625 ieee80211_amrr_cleanup(&uvp->amrr); 626 ieee80211_vap_detach(vap); 627 free(uvp, M_80211_VAP); 628} 629 630static void 631ural_tx_free(struct ural_tx_data *data, int txerr) 632{ 633 struct ural_softc *sc = data->sc; 634 635 if (data->m != NULL) { 636 if (data->m->m_flags & M_TXCB) 637 ieee80211_process_callback(data->ni, data->m, 638 txerr ? ETIMEDOUT : 0); 639 m_freem(data->m); 640 data->m = NULL; 641 642 ieee80211_free_node(data->ni); 643 data->ni = NULL; 644 } 645 STAILQ_INSERT_TAIL(&sc->tx_free, data, next); 646 sc->tx_nfree++; 647} 648 649static void 650ural_setup_tx_list(struct ural_softc *sc) 651{ 652 struct ural_tx_data *data; 653 int i; 654 655 sc->tx_nfree = 0; 656 STAILQ_INIT(&sc->tx_q); 657 STAILQ_INIT(&sc->tx_free); 658 659 for (i = 0; i < RAL_TX_LIST_COUNT; i++) { 660 data = &sc->tx_data[i]; 661 662 data->sc = sc; 663 STAILQ_INSERT_TAIL(&sc->tx_free, data, next); 664 sc->tx_nfree++; 665 } 666} 667 668static void 669ural_unsetup_tx_list(struct ural_softc *sc) 670{ 671 struct ural_tx_data *data; 672 int i; 673 674 /* make sure any subsequent use of the queues will fail */ 675 sc->tx_nfree = 0; 676 STAILQ_INIT(&sc->tx_q); 677 STAILQ_INIT(&sc->tx_free); 678 679 /* free up all node references and mbufs */ 680 for (i = 0; i < RAL_TX_LIST_COUNT; i++) { 681 data = &sc->tx_data[i]; 682 683 if (data->m != NULL) { 684 m_freem(data->m); 685 data->m = NULL; 686 } 687 if (data->ni != NULL) { 688 ieee80211_free_node(data->ni); 689 data->ni = NULL; 690 } 691 } 692} 693 694static int 695ural_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 696{ 697 struct ural_vap *uvp = URAL_VAP(vap); 698 struct ieee80211com *ic = vap->iv_ic; 699 struct ural_softc *sc = ic->ic_ifp->if_softc; 700 const struct ieee80211_txparam *tp; 701 struct ieee80211_node *ni; 702 struct mbuf *m; 703 704 DPRINTF("%s -> %s\n", 705 ieee80211_state_name[vap->iv_state], 706 ieee80211_state_name[nstate]); 707 708 IEEE80211_UNLOCK(ic); 709 RAL_LOCK(sc); 710 usb2_callout_stop(&uvp->amrr_ch); 711 712 switch (nstate) { 713 case IEEE80211_S_INIT: 714 if (vap->iv_state == IEEE80211_S_RUN) { 715 /* abort TSF synchronization */ 716 ural_write(sc, RAL_TXRX_CSR19, 0); 717 718 /* force tx led to stop blinking */ 719 ural_write(sc, RAL_MAC_CSR20, 0); 720 } 721 break; 722 723 case IEEE80211_S_RUN: 724 ni = vap->iv_bss; 725 726 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 727 ural_update_slot(ic->ic_ifp); 728 ural_set_txpreamble(sc); 729 ural_set_basicrates(sc, ic->ic_bsschan); 730 IEEE80211_ADDR_COPY(sc->sc_bssid, ni->ni_bssid); 731 ural_set_bssid(sc, sc->sc_bssid); 732 } 733 734 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 735 vap->iv_opmode == IEEE80211_M_IBSS) { 736 m = ieee80211_beacon_alloc(ni, &uvp->bo); 737 if (m == NULL) { 738 device_printf(sc->sc_dev, 739 "could not allocate beacon\n"); 740 RAL_UNLOCK(sc); 741 IEEE80211_LOCK(ic); 742 return (-1); 743 } 744 ieee80211_ref_node(ni); 745 if (ural_tx_bcn(sc, m, ni) != 0) { 746 device_printf(sc->sc_dev, 747 "could not send beacon\n"); 748 RAL_UNLOCK(sc); 749 IEEE80211_LOCK(ic); 750 return (-1); 751 } 752 } 753 754 /* make tx led blink on tx (controlled by ASIC) */ 755 ural_write(sc, RAL_MAC_CSR20, 1); 756 757 if (vap->iv_opmode != IEEE80211_M_MONITOR) 758 ural_enable_tsf_sync(sc); 759 else 760 ural_enable_tsf(sc); 761 762 /* enable automatic rate adaptation */ 763 /* XXX should use ic_bsschan but not valid until after newstate call below */ 764 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 765 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) 766 ural_amrr_start(sc, ni); 767 768 break; 769 770 default: 771 break; 772 } 773 RAL_UNLOCK(sc); 774 IEEE80211_LOCK(ic); 775 return (uvp->newstate(vap, nstate, arg)); 776} 777 778 779static void 780ural_bulk_write_callback(struct usb2_xfer *xfer) 781{ 782 struct ural_softc *sc = xfer->priv_sc; 783 struct ifnet *ifp = sc->sc_ifp; 784 struct ieee80211vap *vap; 785 struct ural_tx_data *data; 786 struct mbuf *m; 787 unsigned int len; 788 789 switch (USB_GET_STATE(xfer)) { 790 case USB_ST_TRANSFERRED: 791 DPRINTFN(11, "transfer complete, %d bytes\n", xfer->actlen); 792 793 /* free resources */ 794 data = xfer->priv_fifo; 795 ural_tx_free(data, 0); 796 xfer->priv_fifo = NULL; 797 798 ifp->if_opackets++; 799 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 800 801 /* FALLTHROUGH */ 802 case USB_ST_SETUP: 803tr_setup: 804 data = STAILQ_FIRST(&sc->tx_q); 805 if (data) { 806 STAILQ_REMOVE_HEAD(&sc->tx_q, next); 807 m = data->m; 808 809 if (m->m_pkthdr.len > (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE)) { 810 DPRINTFN(0, "data overflow, %u bytes\n", 811 m->m_pkthdr.len); 812 m->m_pkthdr.len = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE); 813 } 814 usb2_copy_in(xfer->frbuffers, 0, &data->desc, 815 RAL_TX_DESC_SIZE); 816 usb2_m_copy_in(xfer->frbuffers, RAL_TX_DESC_SIZE, m, 0, 817 m->m_pkthdr.len); 818 819 vap = data->ni->ni_vap; 820 if (ieee80211_radiotap_active_vap(vap)) { 821 struct ural_tx_radiotap_header *tap = &sc->sc_txtap; 822 823 tap->wt_flags = 0; 824 tap->wt_rate = data->rate; 825 tap->wt_antenna = sc->tx_ant; 826 827 ieee80211_radiotap_tx(vap, m); 828 } 829 830 /* xfer length needs to be a multiple of two! */ 831 len = (RAL_TX_DESC_SIZE + m->m_pkthdr.len + 1) & ~1; 832 if ((len % 64) == 0) 833 len += 2; 834 835 DPRINTFN(11, "sending frame len=%u xferlen=%u\n", 836 m->m_pkthdr.len, len); 837 838 xfer->frlengths[0] = len; 839 xfer->priv_fifo = data; 840 841 usb2_start_hardware(xfer); 842 } 843 break; 844 845 default: /* Error */ 846 DPRINTFN(11, "transfer error, %s\n", 847 usb2_errstr(xfer->error)); 848 849 ifp->if_oerrors++; 850 data = xfer->priv_fifo; 851 if (data != NULL) { 852 ural_tx_free(data, xfer->error); 853 xfer->priv_fifo = NULL; 854 } 855 856 if (xfer->error == USB_ERR_STALLED) { 857 /* try to clear stall first */ 858 xfer->flags.stall_pipe = 1; 859 goto tr_setup; 860 } 861 if (xfer->error == USB_ERR_TIMEOUT) 862 device_printf(sc->sc_dev, "device timeout\n"); 863 break; 864 } 865} 866 867static void 868ural_bulk_read_callback(struct usb2_xfer *xfer) 869{ 870 struct ural_softc *sc = xfer->priv_sc; 871 struct ifnet *ifp = sc->sc_ifp; 872 struct ieee80211com *ic = ifp->if_l2com; 873 struct ieee80211_node *ni; 874 struct mbuf *m = NULL; 875 uint32_t flags; 876 int8_t rssi = 0, nf = 0; 877 unsigned int len; 878 879 switch (USB_GET_STATE(xfer)) { 880 case USB_ST_TRANSFERRED: 881 882 DPRINTFN(15, "rx done, actlen=%d\n", xfer->actlen); 883 884 len = xfer->actlen; 885 if (len < RAL_RX_DESC_SIZE + IEEE80211_MIN_LEN) { 886 DPRINTF("%s: xfer too short %d\n", 887 device_get_nameunit(sc->sc_dev), len); 888 ifp->if_ierrors++; 889 goto tr_setup; 890 } 891 892 len -= RAL_RX_DESC_SIZE; 893 /* rx descriptor is located at the end */ 894 usb2_copy_out(xfer->frbuffers, len, &sc->sc_rx_desc, 895 RAL_RX_DESC_SIZE); 896 897 rssi = URAL_RSSI(sc->sc_rx_desc.rssi); 898 nf = RAL_NOISE_FLOOR; 899 flags = le32toh(sc->sc_rx_desc.flags); 900 if (flags & (RAL_RX_PHY_ERROR | RAL_RX_CRC_ERROR)) { 901 /* 902 * This should not happen since we did not 903 * request to receive those frames when we 904 * filled RAL_TXRX_CSR2: 905 */ 906 DPRINTFN(5, "PHY or CRC error\n"); 907 ifp->if_ierrors++; 908 goto tr_setup; 909 } 910 911 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 912 if (m == NULL) { 913 DPRINTF("could not allocate mbuf\n"); 914 ifp->if_ierrors++; 915 goto tr_setup; 916 } 917 usb2_copy_out(xfer->frbuffers, 0, mtod(m, uint8_t *), len); 918 919 /* finalize mbuf */ 920 m->m_pkthdr.rcvif = ifp; 921 m->m_pkthdr.len = m->m_len = (flags >> 16) & 0xfff; 922 923 if (ieee80211_radiotap_active(ic)) { 924 struct ural_rx_radiotap_header *tap = &sc->sc_rxtap; 925 926 /* XXX set once */ 927 tap->wr_flags = 0; 928 tap->wr_rate = ieee80211_plcp2rate(sc->sc_rx_desc.rate, 929 (flags & RAL_RX_OFDM) ? 930 IEEE80211_T_OFDM : IEEE80211_T_CCK); 931 tap->wr_antenna = sc->rx_ant; 932 tap->wr_antsignal = nf + rssi; 933 tap->wr_antnoise = nf; 934 } 935 /* Strip trailing 802.11 MAC FCS. */ 936 m_adj(m, -IEEE80211_CRC_LEN); 937 938 /* FALLTHROUGH */ 939 case USB_ST_SETUP: 940tr_setup: 941 xfer->frlengths[0] = xfer->max_data_length; 942 usb2_start_hardware(xfer); 943 944 /* 945 * At the end of a USB callback it is always safe to unlock 946 * the private mutex of a device! That is why we do the 947 * "ieee80211_input" here, and not some lines up! 948 */ 949 if (m) { 950 RAL_UNLOCK(sc); 951 ni = ieee80211_find_rxnode(ic, 952 mtod(m, struct ieee80211_frame_min *)); 953 if (ni != NULL) { 954 (void) ieee80211_input(ni, m, rssi, nf); 955 ieee80211_free_node(ni); 956 } else 957 (void) ieee80211_input_all(ic, m, rssi, nf); 958 RAL_LOCK(sc); 959 } 960 return; 961 962 default: /* Error */ 963 if (xfer->error != USB_ERR_CANCELLED) { 964 /* try to clear stall first */ 965 xfer->flags.stall_pipe = 1; 966 goto tr_setup; 967 } 968 return; 969 } 970} 971 972static uint8_t 973ural_plcp_signal(int rate) 974{ 975 switch (rate) { 976 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 977 case 12: return 0xb; 978 case 18: return 0xf; 979 case 24: return 0xa; 980 case 36: return 0xe; 981 case 48: return 0x9; 982 case 72: return 0xd; 983 case 96: return 0x8; 984 case 108: return 0xc; 985 986 /* CCK rates (NB: not IEEE std, device-specific) */ 987 case 2: return 0x0; 988 case 4: return 0x1; 989 case 11: return 0x2; 990 case 22: return 0x3; 991 } 992 return 0xff; /* XXX unsupported/unknown rate */ 993} 994 995static void 996ural_setup_tx_desc(struct ural_softc *sc, struct ural_tx_desc *desc, 997 uint32_t flags, int len, int rate) 998{ 999 struct ifnet *ifp = sc->sc_ifp; 1000 struct ieee80211com *ic = ifp->if_l2com; 1001 uint16_t plcp_length; 1002 int remainder; 1003 1004 desc->flags = htole32(flags); 1005 desc->flags |= htole32(RAL_TX_NEWSEQ); 1006 desc->flags |= htole32(len << 16); 1007 1008 desc->wme = htole16(RAL_AIFSN(2) | RAL_LOGCWMIN(3) | RAL_LOGCWMAX(5)); 1009 desc->wme |= htole16(RAL_IVOFFSET(sizeof (struct ieee80211_frame))); 1010 1011 /* setup PLCP fields */ 1012 desc->plcp_signal = ural_plcp_signal(rate); 1013 desc->plcp_service = 4; 1014 1015 len += IEEE80211_CRC_LEN; 1016 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) { 1017 desc->flags |= htole32(RAL_TX_OFDM); 1018 1019 plcp_length = len & 0xfff; 1020 desc->plcp_length_hi = plcp_length >> 6; 1021 desc->plcp_length_lo = plcp_length & 0x3f; 1022 } else { 1023 plcp_length = (16 * len + rate - 1) / rate; 1024 if (rate == 22) { 1025 remainder = (16 * len) % 22; 1026 if (remainder != 0 && remainder < 7) 1027 desc->plcp_service |= RAL_PLCP_LENGEXT; 1028 } 1029 desc->plcp_length_hi = plcp_length >> 8; 1030 desc->plcp_length_lo = plcp_length & 0xff; 1031 1032 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1033 desc->plcp_signal |= 0x08; 1034 } 1035 1036 desc->iv = 0; 1037 desc->eiv = 0; 1038} 1039 1040#define RAL_TX_TIMEOUT 5000 1041 1042static int 1043ural_tx_bcn(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1044{ 1045 struct ieee80211vap *vap = ni->ni_vap; 1046 struct ieee80211com *ic = ni->ni_ic; 1047 struct ifnet *ifp = sc->sc_ifp; 1048 const struct ieee80211_txparam *tp; 1049 struct ural_tx_data *data; 1050 1051 if (sc->tx_nfree == 0) { 1052 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1053 m_freem(m0); 1054 ieee80211_free_node(ni); 1055 return EIO; 1056 } 1057 data = STAILQ_FIRST(&sc->tx_free); 1058 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1059 sc->tx_nfree--; 1060 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_bsschan)]; 1061 1062 data->m = m0; 1063 data->ni = ni; 1064 data->rate = tp->mgmtrate; 1065 1066 ural_setup_tx_desc(sc, &data->desc, 1067 RAL_TX_IFS_NEWBACKOFF | RAL_TX_TIMESTAMP, m0->m_pkthdr.len, 1068 tp->mgmtrate); 1069 1070 DPRINTFN(10, "sending beacon frame len=%u rate=%u\n", 1071 m0->m_pkthdr.len, tp->mgmtrate); 1072 1073 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1074 usb2_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1075 1076 return (0); 1077} 1078 1079static int 1080ural_tx_mgt(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1081{ 1082 struct ieee80211vap *vap = ni->ni_vap; 1083 struct ieee80211com *ic = ni->ni_ic; 1084 const struct ieee80211_txparam *tp; 1085 struct ural_tx_data *data; 1086 struct ieee80211_frame *wh; 1087 struct ieee80211_key *k; 1088 uint32_t flags; 1089 uint16_t dur; 1090 1091 RAL_LOCK_ASSERT(sc, MA_OWNED); 1092 1093 data = STAILQ_FIRST(&sc->tx_free); 1094 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1095 sc->tx_nfree--; 1096 1097 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 1098 1099 wh = mtod(m0, struct ieee80211_frame *); 1100 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1101 k = ieee80211_crypto_encap(ni, m0); 1102 if (k == NULL) { 1103 m_freem(m0); 1104 return ENOBUFS; 1105 } 1106 wh = mtod(m0, struct ieee80211_frame *); 1107 } 1108 1109 data->m = m0; 1110 data->ni = ni; 1111 data->rate = tp->mgmtrate; 1112 1113 flags = 0; 1114 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1115 flags |= RAL_TX_ACK; 1116 1117 dur = ieee80211_ack_duration(ic->ic_rt, tp->mgmtrate, 1118 ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1119 *(uint16_t *)wh->i_dur = htole16(dur); 1120 1121 /* tell hardware to add timestamp for probe responses */ 1122 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 1123 IEEE80211_FC0_TYPE_MGT && 1124 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1125 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1126 flags |= RAL_TX_TIMESTAMP; 1127 } 1128 1129 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, tp->mgmtrate); 1130 1131 DPRINTFN(10, "sending mgt frame len=%u rate=%u\n", 1132 m0->m_pkthdr.len, tp->mgmtrate); 1133 1134 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1135 usb2_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1136 1137 return 0; 1138} 1139 1140static int 1141ural_sendprot(struct ural_softc *sc, 1142 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) 1143{ 1144 struct ieee80211com *ic = ni->ni_ic; 1145 const struct ieee80211_frame *wh; 1146 struct ural_tx_data *data; 1147 struct mbuf *mprot; 1148 int protrate, ackrate, pktlen, flags, isshort; 1149 uint16_t dur; 1150 1151 KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY, 1152 ("protection %d", prot)); 1153 1154 wh = mtod(m, const struct ieee80211_frame *); 1155 pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1156 1157 protrate = ieee80211_ctl_rate(ic->ic_rt, rate); 1158 ackrate = ieee80211_ack_rate(ic->ic_rt, rate); 1159 1160 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; 1161 dur = ieee80211_compute_duration(ic->ic_rt, pktlen, rate, isshort); 1162 + ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1163 flags = RAL_TX_RETRY(7); 1164 if (prot == IEEE80211_PROT_RTSCTS) { 1165 /* NB: CTS is the same size as an ACK */ 1166 dur += ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1167 flags |= RAL_TX_ACK; 1168 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur); 1169 } else { 1170 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur); 1171 } 1172 if (mprot == NULL) { 1173 /* XXX stat + msg */ 1174 return ENOBUFS; 1175 } 1176 data = STAILQ_FIRST(&sc->tx_free); 1177 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1178 sc->tx_nfree--; 1179 1180 data->m = mprot; 1181 data->ni = ieee80211_ref_node(ni); 1182 data->rate = protrate; 1183 ural_setup_tx_desc(sc, &data->desc, flags, mprot->m_pkthdr.len, protrate); 1184 1185 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1186 usb2_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1187 1188 return 0; 1189} 1190 1191static int 1192ural_tx_raw(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni, 1193 const struct ieee80211_bpf_params *params) 1194{ 1195 struct ural_tx_data *data; 1196 uint32_t flags; 1197 int error; 1198 int rate; 1199 1200 RAL_LOCK_ASSERT(sc, MA_OWNED); 1201 KASSERT(params != NULL, ("no raw xmit params")); 1202 1203 rate = params->ibp_rate0 & IEEE80211_RATE_VAL; 1204 /* XXX validate */ 1205 if (rate == 0) { 1206 m_freem(m0); 1207 return EINVAL; 1208 } 1209 flags = 0; 1210 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 1211 flags |= RAL_TX_ACK; 1212 if (params->ibp_flags & (IEEE80211_BPF_RTS|IEEE80211_BPF_CTS)) { 1213 error = ural_sendprot(sc, m0, ni, 1214 params->ibp_flags & IEEE80211_BPF_RTS ? 1215 IEEE80211_PROT_RTSCTS : IEEE80211_PROT_CTSONLY, 1216 rate); 1217 if (error || sc->tx_nfree == 0) { 1218 m_freem(m0); 1219 return ENOBUFS; 1220 } 1221 flags |= RAL_TX_IFS_SIFS; 1222 } 1223 1224 data = STAILQ_FIRST(&sc->tx_free); 1225 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1226 sc->tx_nfree--; 1227 1228 data->m = m0; 1229 data->ni = ni; 1230 data->rate = rate; 1231 1232 /* XXX need to setup descriptor ourself */ 1233 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate); 1234 1235 DPRINTFN(10, "sending raw frame len=%u rate=%u\n", 1236 m0->m_pkthdr.len, rate); 1237 1238 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1239 usb2_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1240 1241 return 0; 1242} 1243 1244static int 1245ural_tx_data(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1246{ 1247 struct ieee80211vap *vap = ni->ni_vap; 1248 struct ieee80211com *ic = ni->ni_ic; 1249 struct ural_tx_data *data; 1250 struct ieee80211_frame *wh; 1251 const struct ieee80211_txparam *tp; 1252 struct ieee80211_key *k; 1253 uint32_t flags = 0; 1254 uint16_t dur; 1255 int error, rate; 1256 1257 RAL_LOCK_ASSERT(sc, MA_OWNED); 1258 1259 wh = mtod(m0, struct ieee80211_frame *); 1260 1261 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1262 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1263 rate = tp->mcastrate; 1264 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 1265 rate = tp->ucastrate; 1266 else 1267 rate = ni->ni_txrate; 1268 1269 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1270 k = ieee80211_crypto_encap(ni, m0); 1271 if (k == NULL) { 1272 m_freem(m0); 1273 return ENOBUFS; 1274 } 1275 /* packet header may have moved, reset our local pointer */ 1276 wh = mtod(m0, struct ieee80211_frame *); 1277 } 1278 1279 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1280 int prot = IEEE80211_PROT_NONE; 1281 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 1282 prot = IEEE80211_PROT_RTSCTS; 1283 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1284 ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) 1285 prot = ic->ic_protmode; 1286 if (prot != IEEE80211_PROT_NONE) { 1287 error = ural_sendprot(sc, m0, ni, prot, rate); 1288 if (error || sc->tx_nfree == 0) { 1289 m_freem(m0); 1290 return ENOBUFS; 1291 } 1292 flags |= RAL_TX_IFS_SIFS; 1293 } 1294 } 1295 1296 data = STAILQ_FIRST(&sc->tx_free); 1297 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1298 sc->tx_nfree--; 1299 1300 data->m = m0; 1301 data->ni = ni; 1302 data->rate = rate; 1303 1304 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1305 flags |= RAL_TX_ACK; 1306 flags |= RAL_TX_RETRY(7); 1307 1308 dur = ieee80211_ack_duration(ic->ic_rt, rate, 1309 ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1310 *(uint16_t *)wh->i_dur = htole16(dur); 1311 } 1312 1313 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate); 1314 1315 DPRINTFN(10, "sending data frame len=%u rate=%u\n", 1316 m0->m_pkthdr.len, rate); 1317 1318 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1319 usb2_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1320 1321 return 0; 1322} 1323 1324static void 1325ural_start(struct ifnet *ifp) 1326{ 1327 struct ural_softc *sc = ifp->if_softc; 1328 struct ieee80211_node *ni; 1329 struct mbuf *m; 1330 1331 RAL_LOCK(sc); 1332 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1333 RAL_UNLOCK(sc); 1334 return; 1335 } 1336 for (;;) { 1337 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1338 if (m == NULL) 1339 break; 1340 if (sc->tx_nfree < RAL_TX_MINFREE) { 1341 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1342 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1343 break; 1344 } 1345 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1346 if (ural_tx_data(sc, m, ni) != 0) { 1347 ieee80211_free_node(ni); 1348 ifp->if_oerrors++; 1349 break; 1350 } 1351 } 1352 RAL_UNLOCK(sc); 1353} 1354 1355static int 1356ural_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1357{ 1358 struct ural_softc *sc = ifp->if_softc; 1359 struct ieee80211com *ic = ifp->if_l2com; 1360 struct ifreq *ifr = (struct ifreq *) data; 1361 int error = 0, startall = 0; 1362 1363 switch (cmd) { 1364 case SIOCSIFFLAGS: 1365 RAL_LOCK(sc); 1366 if (ifp->if_flags & IFF_UP) { 1367 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1368 ural_init_locked(sc); 1369 startall = 1; 1370 } else 1371 ural_setpromisc(sc); 1372 } else { 1373 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1374 ural_stop(sc); 1375 } 1376 RAL_UNLOCK(sc); 1377 if (startall) 1378 ieee80211_start_all(ic); 1379 break; 1380 case SIOCGIFMEDIA: 1381 case SIOCSIFMEDIA: 1382 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1383 break; 1384 default: 1385 error = ether_ioctl(ifp, cmd, data); 1386 break; 1387 } 1388 return error; 1389} 1390 1391static void 1392ural_set_testmode(struct ural_softc *sc) 1393{ 1394 struct usb2_device_request req; 1395 usb2_error_t error; 1396 1397 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1398 req.bRequest = RAL_VENDOR_REQUEST; 1399 USETW(req.wValue, 4); 1400 USETW(req.wIndex, 1); 1401 USETW(req.wLength, 0); 1402 1403 error = ural_do_request(sc, &req, NULL); 1404 if (error != 0) { 1405 device_printf(sc->sc_dev, "could not set test mode: %s\n", 1406 usb2_errstr(error)); 1407 } 1408} 1409 1410static void 1411ural_eeprom_read(struct ural_softc *sc, uint16_t addr, void *buf, int len) 1412{ 1413 struct usb2_device_request req; 1414 usb2_error_t error; 1415 1416 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1417 req.bRequest = RAL_READ_EEPROM; 1418 USETW(req.wValue, 0); 1419 USETW(req.wIndex, addr); 1420 USETW(req.wLength, len); 1421 1422 error = ural_do_request(sc, &req, buf); 1423 if (error != 0) { 1424 device_printf(sc->sc_dev, "could not read EEPROM: %s\n", 1425 usb2_errstr(error)); 1426 } 1427} 1428 1429static uint16_t 1430ural_read(struct ural_softc *sc, uint16_t reg) 1431{ 1432 struct usb2_device_request req; 1433 usb2_error_t error; 1434 uint16_t val; 1435 1436 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1437 req.bRequest = RAL_READ_MAC; 1438 USETW(req.wValue, 0); 1439 USETW(req.wIndex, reg); 1440 USETW(req.wLength, sizeof (uint16_t)); 1441 1442 error = ural_do_request(sc, &req, &val); 1443 if (error != 0) { 1444 device_printf(sc->sc_dev, "could not read MAC register: %s\n", 1445 usb2_errstr(error)); 1446 return 0; 1447 } 1448 1449 return le16toh(val); 1450} 1451 1452static void 1453ural_read_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 1454{ 1455 struct usb2_device_request req; 1456 usb2_error_t error; 1457 1458 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1459 req.bRequest = RAL_READ_MULTI_MAC; 1460 USETW(req.wValue, 0); 1461 USETW(req.wIndex, reg); 1462 USETW(req.wLength, len); 1463 1464 error = ural_do_request(sc, &req, buf); 1465 if (error != 0) { 1466 device_printf(sc->sc_dev, "could not read MAC register: %s\n", 1467 usb2_errstr(error)); 1468 } 1469} 1470 1471static void 1472ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val) 1473{ 1474 struct usb2_device_request req; 1475 usb2_error_t error; 1476 1477 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1478 req.bRequest = RAL_WRITE_MAC; 1479 USETW(req.wValue, val); 1480 USETW(req.wIndex, reg); 1481 USETW(req.wLength, 0); 1482 1483 error = ural_do_request(sc, &req, NULL); 1484 if (error != 0) { 1485 device_printf(sc->sc_dev, "could not write MAC register: %s\n", 1486 usb2_errstr(error)); 1487 } 1488} 1489 1490static void 1491ural_write_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 1492{ 1493 struct usb2_device_request req; 1494 usb2_error_t error; 1495 1496 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1497 req.bRequest = RAL_WRITE_MULTI_MAC; 1498 USETW(req.wValue, 0); 1499 USETW(req.wIndex, reg); 1500 USETW(req.wLength, len); 1501 1502 error = ural_do_request(sc, &req, buf); 1503 if (error != 0) { 1504 device_printf(sc->sc_dev, "could not write MAC register: %s\n", 1505 usb2_errstr(error)); 1506 } 1507} 1508 1509static void 1510ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val) 1511{ 1512 uint16_t tmp; 1513 int ntries; 1514 1515 for (ntries = 0; ntries < 100; ntries++) { 1516 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 1517 break; 1518 if (ural_pause(sc, hz / 100)) 1519 break; 1520 } 1521 if (ntries == 100) { 1522 device_printf(sc->sc_dev, "could not write to BBP\n"); 1523 return; 1524 } 1525 1526 tmp = reg << 8 | val; 1527 ural_write(sc, RAL_PHY_CSR7, tmp); 1528} 1529 1530static uint8_t 1531ural_bbp_read(struct ural_softc *sc, uint8_t reg) 1532{ 1533 uint16_t val; 1534 int ntries; 1535 1536 val = RAL_BBP_WRITE | reg << 8; 1537 ural_write(sc, RAL_PHY_CSR7, val); 1538 1539 for (ntries = 0; ntries < 100; ntries++) { 1540 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 1541 break; 1542 if (ural_pause(sc, hz / 100)) 1543 break; 1544 } 1545 if (ntries == 100) { 1546 device_printf(sc->sc_dev, "could not read BBP\n"); 1547 return 0; 1548 } 1549 1550 return ural_read(sc, RAL_PHY_CSR7) & 0xff; 1551} 1552 1553static void 1554ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val) 1555{ 1556 uint32_t tmp; 1557 int ntries; 1558 1559 for (ntries = 0; ntries < 100; ntries++) { 1560 if (!(ural_read(sc, RAL_PHY_CSR10) & RAL_RF_LOBUSY)) 1561 break; 1562 if (ural_pause(sc, hz / 100)) 1563 break; 1564 } 1565 if (ntries == 100) { 1566 device_printf(sc->sc_dev, "could not write to RF\n"); 1567 return; 1568 } 1569 1570 tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xfffff) << 2 | (reg & 0x3); 1571 ural_write(sc, RAL_PHY_CSR9, tmp & 0xffff); 1572 ural_write(sc, RAL_PHY_CSR10, tmp >> 16); 1573 1574 /* remember last written value in sc */ 1575 sc->rf_regs[reg] = val; 1576 1577 DPRINTFN(15, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff); 1578} 1579 1580/* ARGUSED */ 1581static struct ieee80211_node * 1582ural_node_alloc(struct ieee80211vap *vap __unused, 1583 const uint8_t mac[IEEE80211_ADDR_LEN] __unused) 1584{ 1585 struct ural_node *un; 1586 1587 un = malloc(sizeof(struct ural_node), M_80211_NODE, M_NOWAIT | M_ZERO); 1588 return un != NULL ? &un->ni : NULL; 1589} 1590 1591static void 1592ural_newassoc(struct ieee80211_node *ni, int isnew) 1593{ 1594 struct ieee80211vap *vap = ni->ni_vap; 1595 1596 ieee80211_amrr_node_init(&URAL_VAP(vap)->amrr, &URAL_NODE(ni)->amn, ni); 1597} 1598 1599static void 1600ural_scan_start(struct ieee80211com *ic) 1601{ 1602 struct ifnet *ifp = ic->ic_ifp; 1603 struct ural_softc *sc = ifp->if_softc; 1604 1605 RAL_LOCK(sc); 1606 ural_write(sc, RAL_TXRX_CSR19, 0); 1607 ural_set_bssid(sc, ifp->if_broadcastaddr); 1608 RAL_UNLOCK(sc); 1609} 1610 1611static void 1612ural_scan_end(struct ieee80211com *ic) 1613{ 1614 struct ural_softc *sc = ic->ic_ifp->if_softc; 1615 1616 RAL_LOCK(sc); 1617 ural_enable_tsf_sync(sc); 1618 ural_set_bssid(sc, sc->sc_bssid); 1619 RAL_UNLOCK(sc); 1620 1621} 1622 1623static void 1624ural_set_channel(struct ieee80211com *ic) 1625{ 1626 struct ural_softc *sc = ic->ic_ifp->if_softc; 1627 1628 RAL_LOCK(sc); 1629 ural_set_chan(sc, ic->ic_curchan); 1630 RAL_UNLOCK(sc); 1631} 1632 1633static void 1634ural_set_chan(struct ural_softc *sc, struct ieee80211_channel *c) 1635{ 1636 struct ifnet *ifp = sc->sc_ifp; 1637 struct ieee80211com *ic = ifp->if_l2com; 1638 uint8_t power, tmp; 1639 int i, chan; 1640 1641 chan = ieee80211_chan2ieee(ic, c); 1642 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 1643 return; 1644 1645 if (IEEE80211_IS_CHAN_2GHZ(c)) 1646 power = min(sc->txpow[chan - 1], 31); 1647 else 1648 power = 31; 1649 1650 /* adjust txpower using ifconfig settings */ 1651 power -= (100 - ic->ic_txpowlimit) / 8; 1652 1653 DPRINTFN(2, "setting channel to %u, txpower to %u\n", chan, power); 1654 1655 switch (sc->rf_rev) { 1656 case RAL_RF_2522: 1657 ural_rf_write(sc, RAL_RF1, 0x00814); 1658 ural_rf_write(sc, RAL_RF2, ural_rf2522_r2[chan - 1]); 1659 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1660 break; 1661 1662 case RAL_RF_2523: 1663 ural_rf_write(sc, RAL_RF1, 0x08804); 1664 ural_rf_write(sc, RAL_RF2, ural_rf2523_r2[chan - 1]); 1665 ural_rf_write(sc, RAL_RF3, power << 7 | 0x38044); 1666 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1667 break; 1668 1669 case RAL_RF_2524: 1670 ural_rf_write(sc, RAL_RF1, 0x0c808); 1671 ural_rf_write(sc, RAL_RF2, ural_rf2524_r2[chan - 1]); 1672 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1673 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1674 break; 1675 1676 case RAL_RF_2525: 1677 ural_rf_write(sc, RAL_RF1, 0x08808); 1678 ural_rf_write(sc, RAL_RF2, ural_rf2525_hi_r2[chan - 1]); 1679 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1680 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1681 1682 ural_rf_write(sc, RAL_RF1, 0x08808); 1683 ural_rf_write(sc, RAL_RF2, ural_rf2525_r2[chan - 1]); 1684 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1685 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1686 break; 1687 1688 case RAL_RF_2525E: 1689 ural_rf_write(sc, RAL_RF1, 0x08808); 1690 ural_rf_write(sc, RAL_RF2, ural_rf2525e_r2[chan - 1]); 1691 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1692 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282); 1693 break; 1694 1695 case RAL_RF_2526: 1696 ural_rf_write(sc, RAL_RF2, ural_rf2526_hi_r2[chan - 1]); 1697 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1698 ural_rf_write(sc, RAL_RF1, 0x08804); 1699 1700 ural_rf_write(sc, RAL_RF2, ural_rf2526_r2[chan - 1]); 1701 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1702 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1703 break; 1704 1705 /* dual-band RF */ 1706 case RAL_RF_5222: 1707 for (i = 0; ural_rf5222[i].chan != chan; i++); 1708 1709 ural_rf_write(sc, RAL_RF1, ural_rf5222[i].r1); 1710 ural_rf_write(sc, RAL_RF2, ural_rf5222[i].r2); 1711 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1712 ural_rf_write(sc, RAL_RF4, ural_rf5222[i].r4); 1713 break; 1714 } 1715 1716 if (ic->ic_opmode != IEEE80211_M_MONITOR && 1717 (ic->ic_flags & IEEE80211_F_SCAN) == 0) { 1718 /* set Japan filter bit for channel 14 */ 1719 tmp = ural_bbp_read(sc, 70); 1720 1721 tmp &= ~RAL_JAPAN_FILTER; 1722 if (chan == 14) 1723 tmp |= RAL_JAPAN_FILTER; 1724 1725 ural_bbp_write(sc, 70, tmp); 1726 1727 /* clear CRC errors */ 1728 ural_read(sc, RAL_STA_CSR0); 1729 1730 ural_pause(sc, hz / 100); 1731 ural_disable_rf_tune(sc); 1732 } 1733 1734 /* XXX doesn't belong here */ 1735 /* update basic rate set */ 1736 ural_set_basicrates(sc, c); 1737 1738 /* give the hardware some time to do the switchover */ 1739 ural_pause(sc, hz / 100); 1740} 1741 1742/* 1743 * Disable RF auto-tuning. 1744 */ 1745static void 1746ural_disable_rf_tune(struct ural_softc *sc) 1747{ 1748 uint32_t tmp; 1749 1750 if (sc->rf_rev != RAL_RF_2523) { 1751 tmp = sc->rf_regs[RAL_RF1] & ~RAL_RF1_AUTOTUNE; 1752 ural_rf_write(sc, RAL_RF1, tmp); 1753 } 1754 1755 tmp = sc->rf_regs[RAL_RF3] & ~RAL_RF3_AUTOTUNE; 1756 ural_rf_write(sc, RAL_RF3, tmp); 1757 1758 DPRINTFN(2, "disabling RF autotune\n"); 1759} 1760 1761/* 1762 * Refer to IEEE Std 802.11-1999 pp. 123 for more information on TSF 1763 * synchronization. 1764 */ 1765static void 1766ural_enable_tsf_sync(struct ural_softc *sc) 1767{ 1768 struct ifnet *ifp = sc->sc_ifp; 1769 struct ieee80211com *ic = ifp->if_l2com; 1770 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1771 uint16_t logcwmin, preload, tmp; 1772 1773 /* first, disable TSF synchronization */ 1774 ural_write(sc, RAL_TXRX_CSR19, 0); 1775 1776 tmp = (16 * vap->iv_bss->ni_intval) << 4; 1777 ural_write(sc, RAL_TXRX_CSR18, tmp); 1778 1779 logcwmin = (ic->ic_opmode == IEEE80211_M_IBSS) ? 2 : 0; 1780 preload = (ic->ic_opmode == IEEE80211_M_IBSS) ? 320 : 6; 1781 tmp = logcwmin << 12 | preload; 1782 ural_write(sc, RAL_TXRX_CSR20, tmp); 1783 1784 /* finally, enable TSF synchronization */ 1785 tmp = RAL_ENABLE_TSF | RAL_ENABLE_TBCN; 1786 if (ic->ic_opmode == IEEE80211_M_STA) 1787 tmp |= RAL_ENABLE_TSF_SYNC(1); 1788 else 1789 tmp |= RAL_ENABLE_TSF_SYNC(2) | RAL_ENABLE_BEACON_GENERATOR; 1790 ural_write(sc, RAL_TXRX_CSR19, tmp); 1791 1792 DPRINTF("enabling TSF synchronization\n"); 1793} 1794 1795static void 1796ural_enable_tsf(struct ural_softc *sc) 1797{ 1798 /* first, disable TSF synchronization */ 1799 ural_write(sc, RAL_TXRX_CSR19, 0); 1800 ural_write(sc, RAL_TXRX_CSR19, RAL_ENABLE_TSF | RAL_ENABLE_TSF_SYNC(2)); 1801} 1802 1803#define RAL_RXTX_TURNAROUND 5 /* us */ 1804static void 1805ural_update_slot(struct ifnet *ifp) 1806{ 1807 struct ural_softc *sc = ifp->if_softc; 1808 struct ieee80211com *ic = ifp->if_l2com; 1809 uint16_t slottime, sifs, eifs; 1810 1811 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1812 1813 /* 1814 * These settings may sound a bit inconsistent but this is what the 1815 * reference driver does. 1816 */ 1817 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1818 sifs = 16 - RAL_RXTX_TURNAROUND; 1819 eifs = 364; 1820 } else { 1821 sifs = 10 - RAL_RXTX_TURNAROUND; 1822 eifs = 64; 1823 } 1824 1825 ural_write(sc, RAL_MAC_CSR10, slottime); 1826 ural_write(sc, RAL_MAC_CSR11, sifs); 1827 ural_write(sc, RAL_MAC_CSR12, eifs); 1828} 1829 1830static void 1831ural_set_txpreamble(struct ural_softc *sc) 1832{ 1833 struct ifnet *ifp = sc->sc_ifp; 1834 struct ieee80211com *ic = ifp->if_l2com; 1835 uint16_t tmp; 1836 1837 tmp = ural_read(sc, RAL_TXRX_CSR10); 1838 1839 tmp &= ~RAL_SHORT_PREAMBLE; 1840 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1841 tmp |= RAL_SHORT_PREAMBLE; 1842 1843 ural_write(sc, RAL_TXRX_CSR10, tmp); 1844} 1845 1846static void 1847ural_set_basicrates(struct ural_softc *sc, const struct ieee80211_channel *c) 1848{ 1849 /* XXX wrong, take from rate set */ 1850 /* update basic rate set */ 1851 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1852 /* 11a basic rates: 6, 12, 24Mbps */ 1853 ural_write(sc, RAL_TXRX_CSR11, 0x150); 1854 } else if (IEEE80211_IS_CHAN_ANYG(c)) { 1855 /* 11g basic rates: 1, 2, 5.5, 11, 6, 12, 24Mbps */ 1856 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 1857 } else { 1858 /* 11b basic rates: 1, 2Mbps */ 1859 ural_write(sc, RAL_TXRX_CSR11, 0x3); 1860 } 1861} 1862 1863static void 1864ural_set_bssid(struct ural_softc *sc, const uint8_t *bssid) 1865{ 1866 uint16_t tmp; 1867 1868 tmp = bssid[0] | bssid[1] << 8; 1869 ural_write(sc, RAL_MAC_CSR5, tmp); 1870 1871 tmp = bssid[2] | bssid[3] << 8; 1872 ural_write(sc, RAL_MAC_CSR6, tmp); 1873 1874 tmp = bssid[4] | bssid[5] << 8; 1875 ural_write(sc, RAL_MAC_CSR7, tmp); 1876 1877 DPRINTF("setting BSSID to %6D\n", bssid, ":"); 1878} 1879 1880static void 1881ural_set_macaddr(struct ural_softc *sc, uint8_t *addr) 1882{ 1883 uint16_t tmp; 1884 1885 tmp = addr[0] | addr[1] << 8; 1886 ural_write(sc, RAL_MAC_CSR2, tmp); 1887 1888 tmp = addr[2] | addr[3] << 8; 1889 ural_write(sc, RAL_MAC_CSR3, tmp); 1890 1891 tmp = addr[4] | addr[5] << 8; 1892 ural_write(sc, RAL_MAC_CSR4, tmp); 1893 1894 DPRINTF("setting MAC address to %6D\n", addr, ":"); 1895} 1896 1897static void 1898ural_setpromisc(struct ural_softc *sc) 1899{ 1900 struct ifnet *ifp = sc->sc_ifp; 1901 uint32_t tmp; 1902 1903 tmp = ural_read(sc, RAL_TXRX_CSR2); 1904 1905 tmp &= ~RAL_DROP_NOT_TO_ME; 1906 if (!(ifp->if_flags & IFF_PROMISC)) 1907 tmp |= RAL_DROP_NOT_TO_ME; 1908 1909 ural_write(sc, RAL_TXRX_CSR2, tmp); 1910 1911 DPRINTF("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 1912 "entering" : "leaving"); 1913} 1914 1915static void 1916ural_update_promisc(struct ifnet *ifp) 1917{ 1918 struct ural_softc *sc = ifp->if_softc; 1919 1920 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1921 return; 1922 1923 RAL_LOCK(sc); 1924 ural_setpromisc(sc); 1925 RAL_UNLOCK(sc); 1926} 1927 1928static const char * 1929ural_get_rf(int rev) 1930{ 1931 switch (rev) { 1932 case RAL_RF_2522: return "RT2522"; 1933 case RAL_RF_2523: return "RT2523"; 1934 case RAL_RF_2524: return "RT2524"; 1935 case RAL_RF_2525: return "RT2525"; 1936 case RAL_RF_2525E: return "RT2525e"; 1937 case RAL_RF_2526: return "RT2526"; 1938 case RAL_RF_5222: return "RT5222"; 1939 default: return "unknown"; 1940 } 1941} 1942 1943static void 1944ural_read_eeprom(struct ural_softc *sc) 1945{ 1946 uint16_t val; 1947 1948 ural_eeprom_read(sc, RAL_EEPROM_CONFIG0, &val, 2); 1949 val = le16toh(val); 1950 sc->rf_rev = (val >> 11) & 0x7; 1951 sc->hw_radio = (val >> 10) & 0x1; 1952 sc->led_mode = (val >> 6) & 0x7; 1953 sc->rx_ant = (val >> 4) & 0x3; 1954 sc->tx_ant = (val >> 2) & 0x3; 1955 sc->nb_ant = val & 0x3; 1956 1957 /* read MAC address */ 1958 ural_eeprom_read(sc, RAL_EEPROM_ADDRESS, sc->sc_bssid, 6); 1959 1960 /* read default values for BBP registers */ 1961 ural_eeprom_read(sc, RAL_EEPROM_BBP_BASE, sc->bbp_prom, 2 * 16); 1962 1963 /* read Tx power for all b/g channels */ 1964 ural_eeprom_read(sc, RAL_EEPROM_TXPOWER, sc->txpow, 14); 1965} 1966 1967static int 1968ural_bbp_init(struct ural_softc *sc) 1969{ 1970#define N(a) (sizeof (a) / sizeof ((a)[0])) 1971 int i, ntries; 1972 1973 /* wait for BBP to be ready */ 1974 for (ntries = 0; ntries < 100; ntries++) { 1975 if (ural_bbp_read(sc, RAL_BBP_VERSION) != 0) 1976 break; 1977 if (ural_pause(sc, hz / 100)) 1978 break; 1979 } 1980 if (ntries == 100) { 1981 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 1982 return EIO; 1983 } 1984 1985 /* initialize BBP registers to default values */ 1986 for (i = 0; i < N(ural_def_bbp); i++) 1987 ural_bbp_write(sc, ural_def_bbp[i].reg, ural_def_bbp[i].val); 1988 1989#if 0 1990 /* initialize BBP registers to values stored in EEPROM */ 1991 for (i = 0; i < 16; i++) { 1992 if (sc->bbp_prom[i].reg == 0xff) 1993 continue; 1994 ural_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 1995 } 1996#endif 1997 1998 return 0; 1999#undef N 2000} 2001 2002static void 2003ural_set_txantenna(struct ural_softc *sc, int antenna) 2004{ 2005 uint16_t tmp; 2006 uint8_t tx; 2007 2008 tx = ural_bbp_read(sc, RAL_BBP_TX) & ~RAL_BBP_ANTMASK; 2009 if (antenna == 1) 2010 tx |= RAL_BBP_ANTA; 2011 else if (antenna == 2) 2012 tx |= RAL_BBP_ANTB; 2013 else 2014 tx |= RAL_BBP_DIVERSITY; 2015 2016 /* need to force I/Q flip for RF 2525e, 2526 and 5222 */ 2017 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526 || 2018 sc->rf_rev == RAL_RF_5222) 2019 tx |= RAL_BBP_FLIPIQ; 2020 2021 ural_bbp_write(sc, RAL_BBP_TX, tx); 2022 2023 /* update values in PHY_CSR5 and PHY_CSR6 */ 2024 tmp = ural_read(sc, RAL_PHY_CSR5) & ~0x7; 2025 ural_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7)); 2026 2027 tmp = ural_read(sc, RAL_PHY_CSR6) & ~0x7; 2028 ural_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7)); 2029} 2030 2031static void 2032ural_set_rxantenna(struct ural_softc *sc, int antenna) 2033{ 2034 uint8_t rx; 2035 2036 rx = ural_bbp_read(sc, RAL_BBP_RX) & ~RAL_BBP_ANTMASK; 2037 if (antenna == 1) 2038 rx |= RAL_BBP_ANTA; 2039 else if (antenna == 2) 2040 rx |= RAL_BBP_ANTB; 2041 else 2042 rx |= RAL_BBP_DIVERSITY; 2043 2044 /* need to force no I/Q flip for RF 2525e and 2526 */ 2045 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526) 2046 rx &= ~RAL_BBP_FLIPIQ; 2047 2048 ural_bbp_write(sc, RAL_BBP_RX, rx); 2049} 2050 2051static void 2052ural_init_locked(struct ural_softc *sc) 2053{ 2054#define N(a) (sizeof (a) / sizeof ((a)[0])) 2055 struct ifnet *ifp = sc->sc_ifp; 2056 struct ieee80211com *ic = ifp->if_l2com; 2057 uint16_t tmp; 2058 int i, ntries; 2059 2060 RAL_LOCK_ASSERT(sc, MA_OWNED); 2061 2062 ural_set_testmode(sc); 2063 ural_write(sc, 0x308, 0x00f0); /* XXX magic */ 2064 2065 ural_stop(sc); 2066 2067 /* initialize MAC registers to default values */ 2068 for (i = 0; i < N(ural_def_mac); i++) 2069 ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val); 2070 2071 /* wait for BBP and RF to wake up (this can take a long time!) */ 2072 for (ntries = 0; ntries < 100; ntries++) { 2073 tmp = ural_read(sc, RAL_MAC_CSR17); 2074 if ((tmp & (RAL_BBP_AWAKE | RAL_RF_AWAKE)) == 2075 (RAL_BBP_AWAKE | RAL_RF_AWAKE)) 2076 break; 2077 if (ural_pause(sc, hz / 100)) 2078 break; 2079 } 2080 if (ntries == 100) { 2081 device_printf(sc->sc_dev, 2082 "timeout waiting for BBP/RF to wakeup\n"); 2083 goto fail; 2084 } 2085 2086 /* we're ready! */ 2087 ural_write(sc, RAL_MAC_CSR1, RAL_HOST_READY); 2088 2089 /* set basic rate set (will be updated later) */ 2090 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 2091 2092 if (ural_bbp_init(sc) != 0) 2093 goto fail; 2094 2095 ural_set_chan(sc, ic->ic_curchan); 2096 2097 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 2098 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta); 2099 2100 ural_set_txantenna(sc, sc->tx_ant); 2101 ural_set_rxantenna(sc, sc->rx_ant); 2102 2103 ural_set_macaddr(sc, IF_LLADDR(ifp)); 2104 2105 /* 2106 * Allocate Tx and Rx xfer queues. 2107 */ 2108 ural_setup_tx_list(sc); 2109 2110 /* kick Rx */ 2111 tmp = RAL_DROP_PHY | RAL_DROP_CRC; 2112 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2113 tmp |= RAL_DROP_CTL | RAL_DROP_BAD_VERSION; 2114 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2115 tmp |= RAL_DROP_TODS; 2116 if (!(ifp->if_flags & IFF_PROMISC)) 2117 tmp |= RAL_DROP_NOT_TO_ME; 2118 } 2119 ural_write(sc, RAL_TXRX_CSR2, tmp); 2120 2121 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2122 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2123 usb2_transfer_set_stall(sc->sc_xfer[URAL_BULK_WR]); 2124 usb2_transfer_start(sc->sc_xfer[URAL_BULK_RD]); 2125 return; 2126 2127fail: ural_stop(sc); 2128#undef N 2129} 2130 2131static void 2132ural_init(void *priv) 2133{ 2134 struct ural_softc *sc = priv; 2135 struct ifnet *ifp = sc->sc_ifp; 2136 struct ieee80211com *ic = ifp->if_l2com; 2137 2138 RAL_LOCK(sc); 2139 ural_init_locked(sc); 2140 RAL_UNLOCK(sc); 2141 2142 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2143 ieee80211_start_all(ic); /* start all vap's */ 2144} 2145 2146static void 2147ural_stop(struct ural_softc *sc) 2148{ 2149 struct ifnet *ifp = sc->sc_ifp; 2150 2151 RAL_LOCK_ASSERT(sc, MA_OWNED); 2152 2153 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2154 2155 /* 2156 * Drain all the transfers, if not already drained: 2157 */ 2158 RAL_UNLOCK(sc); 2159 usb2_transfer_drain(sc->sc_xfer[URAL_BULK_WR]); 2160 usb2_transfer_drain(sc->sc_xfer[URAL_BULK_RD]); 2161 RAL_LOCK(sc); 2162 2163 ural_unsetup_tx_list(sc); 2164 2165 /* disable Rx */ 2166 ural_write(sc, RAL_TXRX_CSR2, RAL_DISABLE_RX); 2167 /* reset ASIC and BBP (but won't reset MAC registers!) */ 2168 ural_write(sc, RAL_MAC_CSR1, RAL_RESET_ASIC | RAL_RESET_BBP); 2169 /* wait a little */ 2170 ural_pause(sc, hz / 10); 2171 ural_write(sc, RAL_MAC_CSR1, 0); 2172 /* wait a little */ 2173 ural_pause(sc, hz / 10); 2174} 2175 2176static int 2177ural_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 2178 const struct ieee80211_bpf_params *params) 2179{ 2180 struct ieee80211com *ic = ni->ni_ic; 2181 struct ifnet *ifp = ic->ic_ifp; 2182 struct ural_softc *sc = ifp->if_softc; 2183 2184 RAL_LOCK(sc); 2185 /* prevent management frames from being sent if we're not ready */ 2186 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 2187 RAL_UNLOCK(sc); 2188 m_freem(m); 2189 ieee80211_free_node(ni); 2190 return ENETDOWN; 2191 } 2192 if (sc->tx_nfree < RAL_TX_MINFREE) { 2193 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2194 RAL_UNLOCK(sc); 2195 m_freem(m); 2196 ieee80211_free_node(ni); 2197 return EIO; 2198 } 2199 2200 ifp->if_opackets++; 2201 2202 if (params == NULL) { 2203 /* 2204 * Legacy path; interpret frame contents to decide 2205 * precisely how to send the frame. 2206 */ 2207 if (ural_tx_mgt(sc, m, ni) != 0) 2208 goto bad; 2209 } else { 2210 /* 2211 * Caller supplied explicit parameters to use in 2212 * sending the frame. 2213 */ 2214 if (ural_tx_raw(sc, m, ni, params) != 0) 2215 goto bad; 2216 } 2217 RAL_UNLOCK(sc); 2218 return 0; 2219bad: 2220 ifp->if_oerrors++; 2221 RAL_UNLOCK(sc); 2222 ieee80211_free_node(ni); 2223 return EIO; /* XXX */ 2224} 2225 2226static void 2227ural_amrr_start(struct ural_softc *sc, struct ieee80211_node *ni) 2228{ 2229 struct ieee80211vap *vap = ni->ni_vap; 2230 struct ural_vap *uvp = URAL_VAP(vap); 2231 2232 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 2233 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta); 2234 2235 ieee80211_amrr_node_init(&uvp->amrr, &URAL_NODE(ni)->amn, ni); 2236 2237 usb2_callout_reset(&uvp->amrr_ch, hz, ural_amrr_timeout, uvp); 2238} 2239 2240static void 2241ural_amrr_timeout(void *arg) 2242{ 2243 struct ural_vap *uvp = arg; 2244 struct ieee80211vap *vap = &uvp->vap; 2245 struct ieee80211com *ic = vap->iv_ic; 2246 2247 ieee80211_runtask(ic, &uvp->amrr_task); 2248} 2249 2250static void 2251ural_amrr_task(void *arg, int pending) 2252{ 2253 struct ural_vap *uvp = arg; 2254 struct ieee80211vap *vap = &uvp->vap; 2255 struct ieee80211com *ic = vap->iv_ic; 2256 struct ifnet *ifp = ic->ic_ifp; 2257 struct ural_softc *sc = ifp->if_softc; 2258 struct ieee80211_node *ni = vap->iv_bss; 2259 int ok, fail; 2260 2261 RAL_LOCK(sc); 2262 /* read and clear statistic registers (STA_CSR0 to STA_CSR10) */ 2263 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof(sc->sta)); 2264 2265 ok = sc->sta[7] + /* TX ok w/o retry */ 2266 sc->sta[8]; /* TX ok w/ retry */ 2267 fail = sc->sta[9]; /* TX retry-fail count */ 2268 2269 ieee80211_amrr_tx_update(&URAL_NODE(ni)->amn, 2270 ok+fail, ok, sc->sta[8] + fail); 2271 (void) ieee80211_amrr_choose(ni, &URAL_NODE(ni)->amn); 2272 2273 ifp->if_oerrors += fail; /* count TX retry-fail as Tx errors */ 2274 2275 usb2_callout_reset(&uvp->amrr_ch, hz, ural_amrr_timeout, uvp); 2276 RAL_UNLOCK(sc); 2277} 2278 2279static int 2280ural_pause(struct ural_softc *sc, int timeout) 2281{ 2282 2283 usb2_pause_mtx(&sc->sc_mtx, timeout); 2284 return (0); 2285} 2286