1/* $FreeBSD: stable/11/sys/dev/usb/wlan/if_ural.c 343976 2019-02-10 21:00:02Z avos $ */ 2 3/*- 4 * Copyright (c) 2005, 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Copyright (c) 2006, 2008 8 * Hans Petter Selasky <hselasky@FreeBSD.org> 9 * 10 * Permission to use, copy, modify, and distribute this software for any 11 * purpose with or without fee is hereby granted, provided that the above 12 * copyright notice and this permission notice appear in all copies. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 18 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 19 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 20 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 21 */ 22 23#include <sys/cdefs.h> 24__FBSDID("$FreeBSD: stable/11/sys/dev/usb/wlan/if_ural.c 343976 2019-02-10 21:00:02Z avos $"); 25 26/*- 27 * Ralink Technology RT2500USB chipset driver 28 * http://www.ralinktech.com/ 29 */ 30 31#include <sys/param.h> 32#include <sys/sockio.h> 33#include <sys/sysctl.h> 34#include <sys/lock.h> 35#include <sys/mutex.h> 36#include <sys/mbuf.h> 37#include <sys/kernel.h> 38#include <sys/socket.h> 39#include <sys/systm.h> 40#include <sys/malloc.h> 41#include <sys/module.h> 42#include <sys/bus.h> 43#include <sys/endian.h> 44#include <sys/kdb.h> 45 46#include <net/bpf.h> 47#include <net/if.h> 48#include <net/if_var.h> 49#include <net/if_arp.h> 50#include <net/ethernet.h> 51#include <net/if_dl.h> 52#include <net/if_media.h> 53#include <net/if_types.h> 54 55#ifdef INET 56#include <netinet/in.h> 57#include <netinet/in_systm.h> 58#include <netinet/in_var.h> 59#include <netinet/if_ether.h> 60#include <netinet/ip.h> 61#endif 62 63#include <net80211/ieee80211_var.h> 64#include <net80211/ieee80211_regdomain.h> 65#include <net80211/ieee80211_radiotap.h> 66#include <net80211/ieee80211_ratectl.h> 67 68#include <dev/usb/usb.h> 69#include <dev/usb/usbdi.h> 70#include "usbdevs.h" 71 72#define USB_DEBUG_VAR ural_debug 73#include <dev/usb/usb_debug.h> 74 75#include <dev/usb/wlan/if_uralreg.h> 76#include <dev/usb/wlan/if_uralvar.h> 77 78#ifdef USB_DEBUG 79static int ural_debug = 0; 80 81static SYSCTL_NODE(_hw_usb, OID_AUTO, ural, CTLFLAG_RW, 0, "USB ural"); 82SYSCTL_INT(_hw_usb_ural, OID_AUTO, debug, CTLFLAG_RWTUN, &ural_debug, 0, 83 "Debug level"); 84#endif 85 86#define URAL_RSSI(rssi) \ 87 ((rssi) > (RAL_NOISE_FLOOR + RAL_RSSI_CORR) ? \ 88 ((rssi) - (RAL_NOISE_FLOOR + RAL_RSSI_CORR)) : 0) 89 90/* various supported device vendors/products */ 91static const STRUCT_USB_HOST_ID ural_devs[] = { 92#define URAL_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 93 URAL_DEV(ASUS, WL167G), 94 URAL_DEV(ASUS, RT2570), 95 URAL_DEV(BELKIN, F5D7050), 96 URAL_DEV(BELKIN, F5D7051), 97 URAL_DEV(CISCOLINKSYS, HU200TS), 98 URAL_DEV(CISCOLINKSYS, WUSB54G), 99 URAL_DEV(CISCOLINKSYS, WUSB54GP), 100 URAL_DEV(CONCEPTRONIC2, C54RU), 101 URAL_DEV(DLINK, DWLG122), 102 URAL_DEV(GIGABYTE, GN54G), 103 URAL_DEV(GIGABYTE, GNWBKG), 104 URAL_DEV(GUILLEMOT, HWGUSB254), 105 URAL_DEV(MELCO, KG54), 106 URAL_DEV(MELCO, KG54AI), 107 URAL_DEV(MELCO, KG54YB), 108 URAL_DEV(MELCO, NINWIFI), 109 URAL_DEV(MSI, RT2570), 110 URAL_DEV(MSI, RT2570_2), 111 URAL_DEV(MSI, RT2570_3), 112 URAL_DEV(NOVATECH, NV902), 113 URAL_DEV(RALINK, RT2570), 114 URAL_DEV(RALINK, RT2570_2), 115 URAL_DEV(RALINK, RT2570_3), 116 URAL_DEV(SIEMENS2, WL54G), 117 URAL_DEV(SMC, 2862WG), 118 URAL_DEV(SPHAIRON, UB801R), 119 URAL_DEV(SURECOM, RT2570), 120 URAL_DEV(VTECH, RT2570), 121 URAL_DEV(ZINWELL, RT2570), 122#undef URAL_DEV 123}; 124 125static usb_callback_t ural_bulk_read_callback; 126static usb_callback_t ural_bulk_write_callback; 127 128static usb_error_t ural_do_request(struct ural_softc *sc, 129 struct usb_device_request *req, void *data); 130static struct ieee80211vap *ural_vap_create(struct ieee80211com *, 131 const char [IFNAMSIZ], int, enum ieee80211_opmode, 132 int, const uint8_t [IEEE80211_ADDR_LEN], 133 const uint8_t [IEEE80211_ADDR_LEN]); 134static void ural_vap_delete(struct ieee80211vap *); 135static void ural_tx_free(struct ural_tx_data *, int); 136static void ural_setup_tx_list(struct ural_softc *); 137static void ural_unsetup_tx_list(struct ural_softc *); 138static int ural_newstate(struct ieee80211vap *, 139 enum ieee80211_state, int); 140static void ural_setup_tx_desc(struct ural_softc *, 141 struct ural_tx_desc *, uint32_t, int, int); 142static int ural_tx_bcn(struct ural_softc *, struct mbuf *, 143 struct ieee80211_node *); 144static int ural_tx_mgt(struct ural_softc *, struct mbuf *, 145 struct ieee80211_node *); 146static int ural_tx_data(struct ural_softc *, struct mbuf *, 147 struct ieee80211_node *); 148static int ural_transmit(struct ieee80211com *, struct mbuf *); 149static void ural_start(struct ural_softc *); 150static void ural_parent(struct ieee80211com *); 151static void ural_set_testmode(struct ural_softc *); 152static void ural_eeprom_read(struct ural_softc *, uint16_t, void *, 153 int); 154static uint16_t ural_read(struct ural_softc *, uint16_t); 155static void ural_read_multi(struct ural_softc *, uint16_t, void *, 156 int); 157static void ural_write(struct ural_softc *, uint16_t, uint16_t); 158static void ural_write_multi(struct ural_softc *, uint16_t, void *, 159 int) __unused; 160static void ural_bbp_write(struct ural_softc *, uint8_t, uint8_t); 161static uint8_t ural_bbp_read(struct ural_softc *, uint8_t); 162static void ural_rf_write(struct ural_softc *, uint8_t, uint32_t); 163static void ural_scan_start(struct ieee80211com *); 164static void ural_scan_end(struct ieee80211com *); 165static void ural_getradiocaps(struct ieee80211com *, int, int *, 166 struct ieee80211_channel[]); 167static void ural_set_channel(struct ieee80211com *); 168static void ural_set_chan(struct ural_softc *, 169 struct ieee80211_channel *); 170static void ural_disable_rf_tune(struct ural_softc *); 171static void ural_enable_tsf_sync(struct ural_softc *); 172static void ural_enable_tsf(struct ural_softc *); 173static void ural_update_slot(struct ural_softc *); 174static void ural_set_txpreamble(struct ural_softc *); 175static void ural_set_basicrates(struct ural_softc *, 176 const struct ieee80211_channel *); 177static void ural_set_bssid(struct ural_softc *, const uint8_t *); 178static void ural_set_macaddr(struct ural_softc *, const uint8_t *); 179static void ural_update_promisc(struct ieee80211com *); 180static void ural_setpromisc(struct ural_softc *); 181static const char *ural_get_rf(int); 182static void ural_read_eeprom(struct ural_softc *); 183static int ural_bbp_init(struct ural_softc *); 184static void ural_set_txantenna(struct ural_softc *, int); 185static void ural_set_rxantenna(struct ural_softc *, int); 186static void ural_init(struct ural_softc *); 187static void ural_stop(struct ural_softc *); 188static int ural_raw_xmit(struct ieee80211_node *, struct mbuf *, 189 const struct ieee80211_bpf_params *); 190static void ural_ratectl_start(struct ural_softc *, 191 struct ieee80211_node *); 192static void ural_ratectl_timeout(void *); 193static void ural_ratectl_task(void *, int); 194static int ural_pause(struct ural_softc *sc, int timeout); 195 196/* 197 * Default values for MAC registers; values taken from the reference driver. 198 */ 199static const struct { 200 uint16_t reg; 201 uint16_t val; 202} ural_def_mac[] = { 203 { RAL_TXRX_CSR5, 0x8c8d }, 204 { RAL_TXRX_CSR6, 0x8b8a }, 205 { RAL_TXRX_CSR7, 0x8687 }, 206 { RAL_TXRX_CSR8, 0x0085 }, 207 { RAL_MAC_CSR13, 0x1111 }, 208 { RAL_MAC_CSR14, 0x1e11 }, 209 { RAL_TXRX_CSR21, 0xe78f }, 210 { RAL_MAC_CSR9, 0xff1d }, 211 { RAL_MAC_CSR11, 0x0002 }, 212 { RAL_MAC_CSR22, 0x0053 }, 213 { RAL_MAC_CSR15, 0x0000 }, 214 { RAL_MAC_CSR8, RAL_FRAME_SIZE }, 215 { RAL_TXRX_CSR19, 0x0000 }, 216 { RAL_TXRX_CSR18, 0x005a }, 217 { RAL_PHY_CSR2, 0x0000 }, 218 { RAL_TXRX_CSR0, 0x1ec0 }, 219 { RAL_PHY_CSR4, 0x000f } 220}; 221 222/* 223 * Default values for BBP registers; values taken from the reference driver. 224 */ 225static const struct { 226 uint8_t reg; 227 uint8_t val; 228} ural_def_bbp[] = { 229 { 3, 0x02 }, 230 { 4, 0x19 }, 231 { 14, 0x1c }, 232 { 15, 0x30 }, 233 { 16, 0xac }, 234 { 17, 0x48 }, 235 { 18, 0x18 }, 236 { 19, 0xff }, 237 { 20, 0x1e }, 238 { 21, 0x08 }, 239 { 22, 0x08 }, 240 { 23, 0x08 }, 241 { 24, 0x80 }, 242 { 25, 0x50 }, 243 { 26, 0x08 }, 244 { 27, 0x23 }, 245 { 30, 0x10 }, 246 { 31, 0x2b }, 247 { 32, 0xb9 }, 248 { 34, 0x12 }, 249 { 35, 0x50 }, 250 { 39, 0xc4 }, 251 { 40, 0x02 }, 252 { 41, 0x60 }, 253 { 53, 0x10 }, 254 { 54, 0x18 }, 255 { 56, 0x08 }, 256 { 57, 0x10 }, 257 { 58, 0x08 }, 258 { 61, 0x60 }, 259 { 62, 0x10 }, 260 { 75, 0xff } 261}; 262 263/* 264 * Default values for RF register R2 indexed by channel numbers. 265 */ 266static const uint32_t ural_rf2522_r2[] = { 267 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, 268 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e 269}; 270 271static const uint32_t ural_rf2523_r2[] = { 272 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 273 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 274}; 275 276static const uint32_t ural_rf2524_r2[] = { 277 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 278 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 279}; 280 281static const uint32_t ural_rf2525_r2[] = { 282 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, 283 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 284}; 285 286static const uint32_t ural_rf2525_hi_r2[] = { 287 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, 288 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e 289}; 290 291static const uint32_t ural_rf2525e_r2[] = { 292 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, 293 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b 294}; 295 296static const uint32_t ural_rf2526_hi_r2[] = { 297 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, 298 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 299}; 300 301static const uint32_t ural_rf2526_r2[] = { 302 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, 303 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d 304}; 305 306/* 307 * For dual-band RF, RF registers R1 and R4 also depend on channel number; 308 * values taken from the reference driver. 309 */ 310static const struct { 311 uint8_t chan; 312 uint32_t r1; 313 uint32_t r2; 314 uint32_t r4; 315} ural_rf5222[] = { 316 { 1, 0x08808, 0x0044d, 0x00282 }, 317 { 2, 0x08808, 0x0044e, 0x00282 }, 318 { 3, 0x08808, 0x0044f, 0x00282 }, 319 { 4, 0x08808, 0x00460, 0x00282 }, 320 { 5, 0x08808, 0x00461, 0x00282 }, 321 { 6, 0x08808, 0x00462, 0x00282 }, 322 { 7, 0x08808, 0x00463, 0x00282 }, 323 { 8, 0x08808, 0x00464, 0x00282 }, 324 { 9, 0x08808, 0x00465, 0x00282 }, 325 { 10, 0x08808, 0x00466, 0x00282 }, 326 { 11, 0x08808, 0x00467, 0x00282 }, 327 { 12, 0x08808, 0x00468, 0x00282 }, 328 { 13, 0x08808, 0x00469, 0x00282 }, 329 { 14, 0x08808, 0x0046b, 0x00286 }, 330 331 { 36, 0x08804, 0x06225, 0x00287 }, 332 { 40, 0x08804, 0x06226, 0x00287 }, 333 { 44, 0x08804, 0x06227, 0x00287 }, 334 { 48, 0x08804, 0x06228, 0x00287 }, 335 { 52, 0x08804, 0x06229, 0x00287 }, 336 { 56, 0x08804, 0x0622a, 0x00287 }, 337 { 60, 0x08804, 0x0622b, 0x00287 }, 338 { 64, 0x08804, 0x0622c, 0x00287 }, 339 340 { 100, 0x08804, 0x02200, 0x00283 }, 341 { 104, 0x08804, 0x02201, 0x00283 }, 342 { 108, 0x08804, 0x02202, 0x00283 }, 343 { 112, 0x08804, 0x02203, 0x00283 }, 344 { 116, 0x08804, 0x02204, 0x00283 }, 345 { 120, 0x08804, 0x02205, 0x00283 }, 346 { 124, 0x08804, 0x02206, 0x00283 }, 347 { 128, 0x08804, 0x02207, 0x00283 }, 348 { 132, 0x08804, 0x02208, 0x00283 }, 349 { 136, 0x08804, 0x02209, 0x00283 }, 350 { 140, 0x08804, 0x0220a, 0x00283 }, 351 352 { 149, 0x08808, 0x02429, 0x00281 }, 353 { 153, 0x08808, 0x0242b, 0x00281 }, 354 { 157, 0x08808, 0x0242d, 0x00281 }, 355 { 161, 0x08808, 0x0242f, 0x00281 } 356}; 357 358static const uint8_t ural_chan_5ghz[] = 359 { 36, 40, 44, 48, 52, 56, 60, 64, 360 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 361 149, 153, 157, 161 }; 362 363static const struct usb_config ural_config[URAL_N_TRANSFER] = { 364 [URAL_BULK_WR] = { 365 .type = UE_BULK, 366 .endpoint = UE_ADDR_ANY, 367 .direction = UE_DIR_OUT, 368 .bufsize = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE + 4), 369 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 370 .callback = ural_bulk_write_callback, 371 .timeout = 5000, /* ms */ 372 }, 373 [URAL_BULK_RD] = { 374 .type = UE_BULK, 375 .endpoint = UE_ADDR_ANY, 376 .direction = UE_DIR_IN, 377 .bufsize = (RAL_FRAME_SIZE + RAL_RX_DESC_SIZE), 378 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 379 .callback = ural_bulk_read_callback, 380 }, 381}; 382 383static device_probe_t ural_match; 384static device_attach_t ural_attach; 385static device_detach_t ural_detach; 386 387static device_method_t ural_methods[] = { 388 /* Device interface */ 389 DEVMETHOD(device_probe, ural_match), 390 DEVMETHOD(device_attach, ural_attach), 391 DEVMETHOD(device_detach, ural_detach), 392 DEVMETHOD_END 393}; 394 395static driver_t ural_driver = { 396 .name = "ural", 397 .methods = ural_methods, 398 .size = sizeof(struct ural_softc), 399}; 400 401static devclass_t ural_devclass; 402 403DRIVER_MODULE(ural, uhub, ural_driver, ural_devclass, NULL, 0); 404MODULE_DEPEND(ural, usb, 1, 1, 1); 405MODULE_DEPEND(ural, wlan, 1, 1, 1); 406MODULE_VERSION(ural, 1); 407USB_PNP_HOST_INFO(ural_devs); 408 409static int 410ural_match(device_t self) 411{ 412 struct usb_attach_arg *uaa = device_get_ivars(self); 413 414 if (uaa->usb_mode != USB_MODE_HOST) 415 return (ENXIO); 416 if (uaa->info.bConfigIndex != 0) 417 return (ENXIO); 418 if (uaa->info.bIfaceIndex != RAL_IFACE_INDEX) 419 return (ENXIO); 420 421 return (usbd_lookup_id_by_uaa(ural_devs, sizeof(ural_devs), uaa)); 422} 423 424static int 425ural_attach(device_t self) 426{ 427 struct usb_attach_arg *uaa = device_get_ivars(self); 428 struct ural_softc *sc = device_get_softc(self); 429 struct ieee80211com *ic = &sc->sc_ic; 430 uint8_t iface_index; 431 int error; 432 433 device_set_usb_desc(self); 434 sc->sc_udev = uaa->device; 435 sc->sc_dev = self; 436 437 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 438 MTX_NETWORK_LOCK, MTX_DEF); 439 mbufq_init(&sc->sc_snd, ifqmaxlen); 440 441 iface_index = RAL_IFACE_INDEX; 442 error = usbd_transfer_setup(uaa->device, 443 &iface_index, sc->sc_xfer, ural_config, 444 URAL_N_TRANSFER, sc, &sc->sc_mtx); 445 if (error) { 446 device_printf(self, "could not allocate USB transfers, " 447 "err=%s\n", usbd_errstr(error)); 448 goto detach; 449 } 450 451 RAL_LOCK(sc); 452 /* retrieve RT2570 rev. no */ 453 sc->asic_rev = ural_read(sc, RAL_MAC_CSR0); 454 455 /* retrieve MAC address and various other things from EEPROM */ 456 ural_read_eeprom(sc); 457 RAL_UNLOCK(sc); 458 459 device_printf(self, "MAC/BBP RT2570 (rev 0x%02x), RF %s\n", 460 sc->asic_rev, ural_get_rf(sc->rf_rev)); 461 462 ic->ic_softc = sc; 463 ic->ic_name = device_get_nameunit(self); 464 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 465 466 /* set device capabilities */ 467 ic->ic_caps = 468 IEEE80211_C_STA /* station mode supported */ 469 | IEEE80211_C_IBSS /* IBSS mode supported */ 470 | IEEE80211_C_MONITOR /* monitor mode supported */ 471 | IEEE80211_C_HOSTAP /* HostAp mode supported */ 472 | IEEE80211_C_TXPMGT /* tx power management */ 473 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 474 | IEEE80211_C_SHSLOT /* short slot time supported */ 475 | IEEE80211_C_BGSCAN /* bg scanning supported */ 476 | IEEE80211_C_WPA /* 802.11i */ 477 ; 478 479 ural_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 480 ic->ic_channels); 481 482 ieee80211_ifattach(ic); 483 ic->ic_update_promisc = ural_update_promisc; 484 ic->ic_raw_xmit = ural_raw_xmit; 485 ic->ic_scan_start = ural_scan_start; 486 ic->ic_scan_end = ural_scan_end; 487 ic->ic_getradiocaps = ural_getradiocaps; 488 ic->ic_set_channel = ural_set_channel; 489 ic->ic_parent = ural_parent; 490 ic->ic_transmit = ural_transmit; 491 ic->ic_vap_create = ural_vap_create; 492 ic->ic_vap_delete = ural_vap_delete; 493 494 ieee80211_radiotap_attach(ic, 495 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 496 RAL_TX_RADIOTAP_PRESENT, 497 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 498 RAL_RX_RADIOTAP_PRESENT); 499 500 if (bootverbose) 501 ieee80211_announce(ic); 502 503 return (0); 504 505detach: 506 ural_detach(self); 507 return (ENXIO); /* failure */ 508} 509 510static int 511ural_detach(device_t self) 512{ 513 struct ural_softc *sc = device_get_softc(self); 514 struct ieee80211com *ic = &sc->sc_ic; 515 516 /* prevent further ioctls */ 517 RAL_LOCK(sc); 518 sc->sc_detached = 1; 519 RAL_UNLOCK(sc); 520 521 /* stop all USB transfers */ 522 usbd_transfer_unsetup(sc->sc_xfer, URAL_N_TRANSFER); 523 524 /* free TX list, if any */ 525 RAL_LOCK(sc); 526 ural_unsetup_tx_list(sc); 527 RAL_UNLOCK(sc); 528 529 if (ic->ic_softc == sc) 530 ieee80211_ifdetach(ic); 531 mbufq_drain(&sc->sc_snd); 532 mtx_destroy(&sc->sc_mtx); 533 534 return (0); 535} 536 537static usb_error_t 538ural_do_request(struct ural_softc *sc, 539 struct usb_device_request *req, void *data) 540{ 541 usb_error_t err; 542 int ntries = 10; 543 544 while (ntries--) { 545 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 546 req, data, 0, NULL, 250 /* ms */); 547 if (err == 0) 548 break; 549 550 DPRINTFN(1, "Control request failed, %s (retrying)\n", 551 usbd_errstr(err)); 552 if (ural_pause(sc, hz / 100)) 553 break; 554 } 555 return (err); 556} 557 558static struct ieee80211vap * 559ural_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 560 enum ieee80211_opmode opmode, int flags, 561 const uint8_t bssid[IEEE80211_ADDR_LEN], 562 const uint8_t mac[IEEE80211_ADDR_LEN]) 563{ 564 struct ural_softc *sc = ic->ic_softc; 565 struct ural_vap *uvp; 566 struct ieee80211vap *vap; 567 568 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 569 return NULL; 570 uvp = malloc(sizeof(struct ural_vap), M_80211_VAP, M_WAITOK | M_ZERO); 571 vap = &uvp->vap; 572 /* enable s/w bmiss handling for sta mode */ 573 574 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 575 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 576 /* out of memory */ 577 free(uvp, M_80211_VAP); 578 return (NULL); 579 } 580 581 /* override state transition machine */ 582 uvp->newstate = vap->iv_newstate; 583 vap->iv_newstate = ural_newstate; 584 585 usb_callout_init_mtx(&uvp->ratectl_ch, &sc->sc_mtx, 0); 586 TASK_INIT(&uvp->ratectl_task, 0, ural_ratectl_task, uvp); 587 ieee80211_ratectl_init(vap); 588 ieee80211_ratectl_setinterval(vap, 1000 /* 1 sec */); 589 590 /* complete setup */ 591 ieee80211_vap_attach(vap, ieee80211_media_change, 592 ieee80211_media_status, mac); 593 ic->ic_opmode = opmode; 594 return vap; 595} 596 597static void 598ural_vap_delete(struct ieee80211vap *vap) 599{ 600 struct ural_vap *uvp = URAL_VAP(vap); 601 struct ieee80211com *ic = vap->iv_ic; 602 603 usb_callout_drain(&uvp->ratectl_ch); 604 ieee80211_draintask(ic, &uvp->ratectl_task); 605 ieee80211_ratectl_deinit(vap); 606 ieee80211_vap_detach(vap); 607 free(uvp, M_80211_VAP); 608} 609 610static void 611ural_tx_free(struct ural_tx_data *data, int txerr) 612{ 613 struct ural_softc *sc = data->sc; 614 615 if (data->m != NULL) { 616 ieee80211_tx_complete(data->ni, data->m, txerr); 617 data->m = NULL; 618 data->ni = NULL; 619 } 620 STAILQ_INSERT_TAIL(&sc->tx_free, data, next); 621 sc->tx_nfree++; 622} 623 624static void 625ural_setup_tx_list(struct ural_softc *sc) 626{ 627 struct ural_tx_data *data; 628 int i; 629 630 sc->tx_nfree = 0; 631 STAILQ_INIT(&sc->tx_q); 632 STAILQ_INIT(&sc->tx_free); 633 634 for (i = 0; i < RAL_TX_LIST_COUNT; i++) { 635 data = &sc->tx_data[i]; 636 637 data->sc = sc; 638 STAILQ_INSERT_TAIL(&sc->tx_free, data, next); 639 sc->tx_nfree++; 640 } 641} 642 643static void 644ural_unsetup_tx_list(struct ural_softc *sc) 645{ 646 struct ural_tx_data *data; 647 int i; 648 649 /* make sure any subsequent use of the queues will fail */ 650 sc->tx_nfree = 0; 651 STAILQ_INIT(&sc->tx_q); 652 STAILQ_INIT(&sc->tx_free); 653 654 /* free up all node references and mbufs */ 655 for (i = 0; i < RAL_TX_LIST_COUNT; i++) { 656 data = &sc->tx_data[i]; 657 658 if (data->m != NULL) { 659 m_freem(data->m); 660 data->m = NULL; 661 } 662 if (data->ni != NULL) { 663 ieee80211_free_node(data->ni); 664 data->ni = NULL; 665 } 666 } 667} 668 669static int 670ural_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 671{ 672 struct ural_vap *uvp = URAL_VAP(vap); 673 struct ieee80211com *ic = vap->iv_ic; 674 struct ural_softc *sc = ic->ic_softc; 675 const struct ieee80211_txparam *tp; 676 struct ieee80211_node *ni; 677 struct mbuf *m; 678 679 DPRINTF("%s -> %s\n", 680 ieee80211_state_name[vap->iv_state], 681 ieee80211_state_name[nstate]); 682 683 IEEE80211_UNLOCK(ic); 684 RAL_LOCK(sc); 685 usb_callout_stop(&uvp->ratectl_ch); 686 687 switch (nstate) { 688 case IEEE80211_S_INIT: 689 if (vap->iv_state == IEEE80211_S_RUN) { 690 /* abort TSF synchronization */ 691 ural_write(sc, RAL_TXRX_CSR19, 0); 692 693 /* force tx led to stop blinking */ 694 ural_write(sc, RAL_MAC_CSR20, 0); 695 } 696 break; 697 698 case IEEE80211_S_RUN: 699 ni = ieee80211_ref_node(vap->iv_bss); 700 701 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 702 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC) 703 goto fail; 704 705 ural_update_slot(sc); 706 ural_set_txpreamble(sc); 707 ural_set_basicrates(sc, ic->ic_bsschan); 708 IEEE80211_ADDR_COPY(sc->sc_bssid, ni->ni_bssid); 709 ural_set_bssid(sc, sc->sc_bssid); 710 } 711 712 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 713 vap->iv_opmode == IEEE80211_M_IBSS) { 714 m = ieee80211_beacon_alloc(ni); 715 if (m == NULL) { 716 device_printf(sc->sc_dev, 717 "could not allocate beacon\n"); 718 goto fail; 719 } 720 ieee80211_ref_node(ni); 721 if (ural_tx_bcn(sc, m, ni) != 0) { 722 device_printf(sc->sc_dev, 723 "could not send beacon\n"); 724 goto fail; 725 } 726 } 727 728 /* make tx led blink on tx (controlled by ASIC) */ 729 ural_write(sc, RAL_MAC_CSR20, 1); 730 731 if (vap->iv_opmode != IEEE80211_M_MONITOR) 732 ural_enable_tsf_sync(sc); 733 else 734 ural_enable_tsf(sc); 735 736 /* enable automatic rate adaptation */ 737 /* XXX should use ic_bsschan but not valid until after newstate call below */ 738 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 739 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) 740 ural_ratectl_start(sc, ni); 741 ieee80211_free_node(ni); 742 break; 743 744 default: 745 break; 746 } 747 RAL_UNLOCK(sc); 748 IEEE80211_LOCK(ic); 749 return (uvp->newstate(vap, nstate, arg)); 750 751fail: 752 RAL_UNLOCK(sc); 753 IEEE80211_LOCK(ic); 754 ieee80211_free_node(ni); 755 return (-1); 756} 757 758 759static void 760ural_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 761{ 762 struct ural_softc *sc = usbd_xfer_softc(xfer); 763 struct ieee80211vap *vap; 764 struct ural_tx_data *data; 765 struct mbuf *m; 766 struct usb_page_cache *pc; 767 int len; 768 769 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 770 771 switch (USB_GET_STATE(xfer)) { 772 case USB_ST_TRANSFERRED: 773 DPRINTFN(11, "transfer complete, %d bytes\n", len); 774 775 /* free resources */ 776 data = usbd_xfer_get_priv(xfer); 777 ural_tx_free(data, 0); 778 usbd_xfer_set_priv(xfer, NULL); 779 780 /* FALLTHROUGH */ 781 case USB_ST_SETUP: 782tr_setup: 783 data = STAILQ_FIRST(&sc->tx_q); 784 if (data) { 785 STAILQ_REMOVE_HEAD(&sc->tx_q, next); 786 m = data->m; 787 788 if (m->m_pkthdr.len > (int)(RAL_FRAME_SIZE + RAL_TX_DESC_SIZE)) { 789 DPRINTFN(0, "data overflow, %u bytes\n", 790 m->m_pkthdr.len); 791 m->m_pkthdr.len = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE); 792 } 793 pc = usbd_xfer_get_frame(xfer, 0); 794 usbd_copy_in(pc, 0, &data->desc, RAL_TX_DESC_SIZE); 795 usbd_m_copy_in(pc, RAL_TX_DESC_SIZE, m, 0, 796 m->m_pkthdr.len); 797 798 vap = data->ni->ni_vap; 799 if (ieee80211_radiotap_active_vap(vap)) { 800 struct ural_tx_radiotap_header *tap = &sc->sc_txtap; 801 802 tap->wt_flags = 0; 803 tap->wt_rate = data->rate; 804 tap->wt_antenna = sc->tx_ant; 805 806 ieee80211_radiotap_tx(vap, m); 807 } 808 809 /* xfer length needs to be a multiple of two! */ 810 len = (RAL_TX_DESC_SIZE + m->m_pkthdr.len + 1) & ~1; 811 if ((len % 64) == 0) 812 len += 2; 813 814 DPRINTFN(11, "sending frame len=%u xferlen=%u\n", 815 m->m_pkthdr.len, len); 816 817 usbd_xfer_set_frame_len(xfer, 0, len); 818 usbd_xfer_set_priv(xfer, data); 819 820 usbd_transfer_submit(xfer); 821 } 822 ural_start(sc); 823 break; 824 825 default: /* Error */ 826 DPRINTFN(11, "transfer error, %s\n", 827 usbd_errstr(error)); 828 829 data = usbd_xfer_get_priv(xfer); 830 if (data != NULL) { 831 ural_tx_free(data, error); 832 usbd_xfer_set_priv(xfer, NULL); 833 } 834 835 if (error == USB_ERR_STALLED) { 836 /* try to clear stall first */ 837 usbd_xfer_set_stall(xfer); 838 goto tr_setup; 839 } 840 if (error == USB_ERR_TIMEOUT) 841 device_printf(sc->sc_dev, "device timeout\n"); 842 break; 843 } 844} 845 846static void 847ural_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 848{ 849 struct ural_softc *sc = usbd_xfer_softc(xfer); 850 struct ieee80211com *ic = &sc->sc_ic; 851 struct ieee80211_node *ni; 852 struct mbuf *m = NULL; 853 struct usb_page_cache *pc; 854 uint32_t flags; 855 int8_t rssi = 0, nf = 0; 856 int len; 857 858 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 859 860 switch (USB_GET_STATE(xfer)) { 861 case USB_ST_TRANSFERRED: 862 863 DPRINTFN(15, "rx done, actlen=%d\n", len); 864 865 if (len < (int)(RAL_RX_DESC_SIZE + IEEE80211_MIN_LEN)) { 866 DPRINTF("%s: xfer too short %d\n", 867 device_get_nameunit(sc->sc_dev), len); 868 counter_u64_add(ic->ic_ierrors, 1); 869 goto tr_setup; 870 } 871 872 len -= RAL_RX_DESC_SIZE; 873 /* rx descriptor is located at the end */ 874 pc = usbd_xfer_get_frame(xfer, 0); 875 usbd_copy_out(pc, len, &sc->sc_rx_desc, RAL_RX_DESC_SIZE); 876 877 rssi = URAL_RSSI(sc->sc_rx_desc.rssi); 878 nf = RAL_NOISE_FLOOR; 879 flags = le32toh(sc->sc_rx_desc.flags); 880 if (flags & (RAL_RX_PHY_ERROR | RAL_RX_CRC_ERROR)) { 881 /* 882 * This should not happen since we did not 883 * request to receive those frames when we 884 * filled RAL_TXRX_CSR2: 885 */ 886 DPRINTFN(5, "PHY or CRC error\n"); 887 counter_u64_add(ic->ic_ierrors, 1); 888 goto tr_setup; 889 } 890 891 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 892 if (m == NULL) { 893 DPRINTF("could not allocate mbuf\n"); 894 counter_u64_add(ic->ic_ierrors, 1); 895 goto tr_setup; 896 } 897 usbd_copy_out(pc, 0, mtod(m, uint8_t *), len); 898 899 /* finalize mbuf */ 900 m->m_pkthdr.len = m->m_len = (flags >> 16) & 0xfff; 901 902 if (ieee80211_radiotap_active(ic)) { 903 struct ural_rx_radiotap_header *tap = &sc->sc_rxtap; 904 905 /* XXX set once */ 906 tap->wr_flags = 0; 907 tap->wr_rate = ieee80211_plcp2rate(sc->sc_rx_desc.rate, 908 (flags & RAL_RX_OFDM) ? 909 IEEE80211_T_OFDM : IEEE80211_T_CCK); 910 tap->wr_antenna = sc->rx_ant; 911 tap->wr_antsignal = nf + rssi; 912 tap->wr_antnoise = nf; 913 } 914 /* Strip trailing 802.11 MAC FCS. */ 915 m_adj(m, -IEEE80211_CRC_LEN); 916 917 /* FALLTHROUGH */ 918 case USB_ST_SETUP: 919tr_setup: 920 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 921 usbd_transfer_submit(xfer); 922 923 /* 924 * At the end of a USB callback it is always safe to unlock 925 * the private mutex of a device! That is why we do the 926 * "ieee80211_input" here, and not some lines up! 927 */ 928 RAL_UNLOCK(sc); 929 if (m) { 930 ni = ieee80211_find_rxnode(ic, 931 mtod(m, struct ieee80211_frame_min *)); 932 if (ni != NULL) { 933 (void) ieee80211_input(ni, m, rssi, nf); 934 ieee80211_free_node(ni); 935 } else 936 (void) ieee80211_input_all(ic, m, rssi, nf); 937 } 938 RAL_LOCK(sc); 939 ural_start(sc); 940 return; 941 942 default: /* Error */ 943 if (error != USB_ERR_CANCELLED) { 944 /* try to clear stall first */ 945 usbd_xfer_set_stall(xfer); 946 goto tr_setup; 947 } 948 return; 949 } 950} 951 952static uint8_t 953ural_plcp_signal(int rate) 954{ 955 switch (rate) { 956 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 957 case 12: return 0xb; 958 case 18: return 0xf; 959 case 24: return 0xa; 960 case 36: return 0xe; 961 case 48: return 0x9; 962 case 72: return 0xd; 963 case 96: return 0x8; 964 case 108: return 0xc; 965 966 /* CCK rates (NB: not IEEE std, device-specific) */ 967 case 2: return 0x0; 968 case 4: return 0x1; 969 case 11: return 0x2; 970 case 22: return 0x3; 971 } 972 return 0xff; /* XXX unsupported/unknown rate */ 973} 974 975static void 976ural_setup_tx_desc(struct ural_softc *sc, struct ural_tx_desc *desc, 977 uint32_t flags, int len, int rate) 978{ 979 struct ieee80211com *ic = &sc->sc_ic; 980 uint16_t plcp_length; 981 int remainder; 982 983 desc->flags = htole32(flags); 984 desc->flags |= htole32(RAL_TX_NEWSEQ); 985 desc->flags |= htole32(len << 16); 986 987 desc->wme = htole16(RAL_AIFSN(2) | RAL_LOGCWMIN(3) | RAL_LOGCWMAX(5)); 988 desc->wme |= htole16(RAL_IVOFFSET(sizeof (struct ieee80211_frame))); 989 990 /* setup PLCP fields */ 991 desc->plcp_signal = ural_plcp_signal(rate); 992 desc->plcp_service = 4; 993 994 len += IEEE80211_CRC_LEN; 995 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) { 996 desc->flags |= htole32(RAL_TX_OFDM); 997 998 plcp_length = len & 0xfff; 999 desc->plcp_length_hi = plcp_length >> 6; 1000 desc->plcp_length_lo = plcp_length & 0x3f; 1001 } else { 1002 if (rate == 0) 1003 rate = 2; /* avoid division by zero */ 1004 plcp_length = howmany(16 * len, rate); 1005 if (rate == 22) { 1006 remainder = (16 * len) % 22; 1007 if (remainder != 0 && remainder < 7) 1008 desc->plcp_service |= RAL_PLCP_LENGEXT; 1009 } 1010 desc->plcp_length_hi = plcp_length >> 8; 1011 desc->plcp_length_lo = plcp_length & 0xff; 1012 1013 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1014 desc->plcp_signal |= 0x08; 1015 } 1016 1017 desc->iv = 0; 1018 desc->eiv = 0; 1019} 1020 1021#define RAL_TX_TIMEOUT 5000 1022 1023static int 1024ural_tx_bcn(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1025{ 1026 struct ieee80211vap *vap = ni->ni_vap; 1027 struct ieee80211com *ic = ni->ni_ic; 1028 const struct ieee80211_txparam *tp; 1029 struct ural_tx_data *data; 1030 1031 if (sc->tx_nfree == 0) { 1032 m_freem(m0); 1033 ieee80211_free_node(ni); 1034 return (EIO); 1035 } 1036 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC) { 1037 m_freem(m0); 1038 ieee80211_free_node(ni); 1039 return (ENXIO); 1040 } 1041 data = STAILQ_FIRST(&sc->tx_free); 1042 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1043 sc->tx_nfree--; 1044 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_bsschan)]; 1045 1046 data->m = m0; 1047 data->ni = ni; 1048 data->rate = tp->mgmtrate; 1049 1050 ural_setup_tx_desc(sc, &data->desc, 1051 RAL_TX_IFS_NEWBACKOFF | RAL_TX_TIMESTAMP, m0->m_pkthdr.len, 1052 tp->mgmtrate); 1053 1054 DPRINTFN(10, "sending beacon frame len=%u rate=%u\n", 1055 m0->m_pkthdr.len, tp->mgmtrate); 1056 1057 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1058 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1059 1060 return (0); 1061} 1062 1063static int 1064ural_tx_mgt(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1065{ 1066 struct ieee80211vap *vap = ni->ni_vap; 1067 struct ieee80211com *ic = ni->ni_ic; 1068 const struct ieee80211_txparam *tp; 1069 struct ural_tx_data *data; 1070 struct ieee80211_frame *wh; 1071 struct ieee80211_key *k; 1072 uint32_t flags; 1073 uint16_t dur; 1074 1075 RAL_LOCK_ASSERT(sc, MA_OWNED); 1076 1077 data = STAILQ_FIRST(&sc->tx_free); 1078 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1079 sc->tx_nfree--; 1080 1081 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 1082 1083 wh = mtod(m0, struct ieee80211_frame *); 1084 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1085 k = ieee80211_crypto_encap(ni, m0); 1086 if (k == NULL) { 1087 m_freem(m0); 1088 return ENOBUFS; 1089 } 1090 wh = mtod(m0, struct ieee80211_frame *); 1091 } 1092 1093 data->m = m0; 1094 data->ni = ni; 1095 data->rate = tp->mgmtrate; 1096 1097 flags = 0; 1098 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1099 flags |= RAL_TX_ACK; 1100 1101 dur = ieee80211_ack_duration(ic->ic_rt, tp->mgmtrate, 1102 ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1103 USETW(wh->i_dur, dur); 1104 1105 /* tell hardware to add timestamp for probe responses */ 1106 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 1107 IEEE80211_FC0_TYPE_MGT && 1108 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1109 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1110 flags |= RAL_TX_TIMESTAMP; 1111 } 1112 1113 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, tp->mgmtrate); 1114 1115 DPRINTFN(10, "sending mgt frame len=%u rate=%u\n", 1116 m0->m_pkthdr.len, tp->mgmtrate); 1117 1118 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1119 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1120 1121 return 0; 1122} 1123 1124static int 1125ural_sendprot(struct ural_softc *sc, 1126 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) 1127{ 1128 struct ieee80211com *ic = ni->ni_ic; 1129 const struct ieee80211_frame *wh; 1130 struct ural_tx_data *data; 1131 struct mbuf *mprot; 1132 int protrate, ackrate, pktlen, flags, isshort; 1133 uint16_t dur; 1134 1135 KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY, 1136 ("protection %d", prot)); 1137 1138 wh = mtod(m, const struct ieee80211_frame *); 1139 pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1140 1141 protrate = ieee80211_ctl_rate(ic->ic_rt, rate); 1142 ackrate = ieee80211_ack_rate(ic->ic_rt, rate); 1143 1144 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; 1145 dur = ieee80211_compute_duration(ic->ic_rt, pktlen, rate, isshort) 1146 + ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1147 flags = RAL_TX_RETRY(7); 1148 if (prot == IEEE80211_PROT_RTSCTS) { 1149 /* NB: CTS is the same size as an ACK */ 1150 dur += ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1151 flags |= RAL_TX_ACK; 1152 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur); 1153 } else { 1154 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur); 1155 } 1156 if (mprot == NULL) { 1157 /* XXX stat + msg */ 1158 return ENOBUFS; 1159 } 1160 data = STAILQ_FIRST(&sc->tx_free); 1161 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1162 sc->tx_nfree--; 1163 1164 data->m = mprot; 1165 data->ni = ieee80211_ref_node(ni); 1166 data->rate = protrate; 1167 ural_setup_tx_desc(sc, &data->desc, flags, mprot->m_pkthdr.len, protrate); 1168 1169 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1170 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1171 1172 return 0; 1173} 1174 1175static int 1176ural_tx_raw(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni, 1177 const struct ieee80211_bpf_params *params) 1178{ 1179 struct ieee80211com *ic = ni->ni_ic; 1180 struct ural_tx_data *data; 1181 uint32_t flags; 1182 int error; 1183 int rate; 1184 1185 RAL_LOCK_ASSERT(sc, MA_OWNED); 1186 KASSERT(params != NULL, ("no raw xmit params")); 1187 1188 rate = params->ibp_rate0; 1189 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 1190 m_freem(m0); 1191 return EINVAL; 1192 } 1193 flags = 0; 1194 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 1195 flags |= RAL_TX_ACK; 1196 if (params->ibp_flags & (IEEE80211_BPF_RTS|IEEE80211_BPF_CTS)) { 1197 error = ural_sendprot(sc, m0, ni, 1198 params->ibp_flags & IEEE80211_BPF_RTS ? 1199 IEEE80211_PROT_RTSCTS : IEEE80211_PROT_CTSONLY, 1200 rate); 1201 if (error || sc->tx_nfree == 0) { 1202 m_freem(m0); 1203 return ENOBUFS; 1204 } 1205 flags |= RAL_TX_IFS_SIFS; 1206 } 1207 1208 data = STAILQ_FIRST(&sc->tx_free); 1209 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1210 sc->tx_nfree--; 1211 1212 data->m = m0; 1213 data->ni = ni; 1214 data->rate = rate; 1215 1216 /* XXX need to setup descriptor ourself */ 1217 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate); 1218 1219 DPRINTFN(10, "sending raw frame len=%u rate=%u\n", 1220 m0->m_pkthdr.len, rate); 1221 1222 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1223 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1224 1225 return 0; 1226} 1227 1228static int 1229ural_tx_data(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1230{ 1231 struct ieee80211vap *vap = ni->ni_vap; 1232 struct ieee80211com *ic = ni->ni_ic; 1233 struct ural_tx_data *data; 1234 struct ieee80211_frame *wh; 1235 const struct ieee80211_txparam *tp; 1236 struct ieee80211_key *k; 1237 uint32_t flags = 0; 1238 uint16_t dur; 1239 int error, rate; 1240 1241 RAL_LOCK_ASSERT(sc, MA_OWNED); 1242 1243 wh = mtod(m0, struct ieee80211_frame *); 1244 1245 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1246 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1247 rate = tp->mcastrate; 1248 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 1249 rate = tp->ucastrate; 1250 else 1251 rate = ni->ni_txrate; 1252 1253 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1254 k = ieee80211_crypto_encap(ni, m0); 1255 if (k == NULL) { 1256 m_freem(m0); 1257 return ENOBUFS; 1258 } 1259 /* packet header may have moved, reset our local pointer */ 1260 wh = mtod(m0, struct ieee80211_frame *); 1261 } 1262 1263 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1264 int prot = IEEE80211_PROT_NONE; 1265 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 1266 prot = IEEE80211_PROT_RTSCTS; 1267 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1268 ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) 1269 prot = ic->ic_protmode; 1270 if (prot != IEEE80211_PROT_NONE) { 1271 error = ural_sendprot(sc, m0, ni, prot, rate); 1272 if (error || sc->tx_nfree == 0) { 1273 m_freem(m0); 1274 return ENOBUFS; 1275 } 1276 flags |= RAL_TX_IFS_SIFS; 1277 } 1278 } 1279 1280 data = STAILQ_FIRST(&sc->tx_free); 1281 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1282 sc->tx_nfree--; 1283 1284 data->m = m0; 1285 data->ni = ni; 1286 data->rate = rate; 1287 1288 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1289 flags |= RAL_TX_ACK; 1290 flags |= RAL_TX_RETRY(7); 1291 1292 dur = ieee80211_ack_duration(ic->ic_rt, rate, 1293 ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1294 USETW(wh->i_dur, dur); 1295 } 1296 1297 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate); 1298 1299 DPRINTFN(10, "sending data frame len=%u rate=%u\n", 1300 m0->m_pkthdr.len, rate); 1301 1302 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1303 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1304 1305 return 0; 1306} 1307 1308static int 1309ural_transmit(struct ieee80211com *ic, struct mbuf *m) 1310{ 1311 struct ural_softc *sc = ic->ic_softc; 1312 int error; 1313 1314 RAL_LOCK(sc); 1315 if (!sc->sc_running) { 1316 RAL_UNLOCK(sc); 1317 return (ENXIO); 1318 } 1319 error = mbufq_enqueue(&sc->sc_snd, m); 1320 if (error) { 1321 RAL_UNLOCK(sc); 1322 return (error); 1323 } 1324 ural_start(sc); 1325 RAL_UNLOCK(sc); 1326 1327 return (0); 1328} 1329 1330static void 1331ural_start(struct ural_softc *sc) 1332{ 1333 struct ieee80211_node *ni; 1334 struct mbuf *m; 1335 1336 RAL_LOCK_ASSERT(sc, MA_OWNED); 1337 1338 if (sc->sc_running == 0) 1339 return; 1340 1341 while (sc->tx_nfree >= RAL_TX_MINFREE && 1342 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1343 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1344 if (ural_tx_data(sc, m, ni) != 0) { 1345 if_inc_counter(ni->ni_vap->iv_ifp, 1346 IFCOUNTER_OERRORS, 1); 1347 ieee80211_free_node(ni); 1348 break; 1349 } 1350 } 1351} 1352 1353static void 1354ural_parent(struct ieee80211com *ic) 1355{ 1356 struct ural_softc *sc = ic->ic_softc; 1357 int startall = 0; 1358 1359 RAL_LOCK(sc); 1360 if (sc->sc_detached) { 1361 RAL_UNLOCK(sc); 1362 return; 1363 } 1364 if (ic->ic_nrunning > 0) { 1365 if (sc->sc_running == 0) { 1366 ural_init(sc); 1367 startall = 1; 1368 } else 1369 ural_setpromisc(sc); 1370 } else if (sc->sc_running) 1371 ural_stop(sc); 1372 RAL_UNLOCK(sc); 1373 if (startall) 1374 ieee80211_start_all(ic); 1375} 1376 1377static void 1378ural_set_testmode(struct ural_softc *sc) 1379{ 1380 struct usb_device_request req; 1381 usb_error_t error; 1382 1383 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1384 req.bRequest = RAL_VENDOR_REQUEST; 1385 USETW(req.wValue, 4); 1386 USETW(req.wIndex, 1); 1387 USETW(req.wLength, 0); 1388 1389 error = ural_do_request(sc, &req, NULL); 1390 if (error != 0) { 1391 device_printf(sc->sc_dev, "could not set test mode: %s\n", 1392 usbd_errstr(error)); 1393 } 1394} 1395 1396static void 1397ural_eeprom_read(struct ural_softc *sc, uint16_t addr, void *buf, int len) 1398{ 1399 struct usb_device_request req; 1400 usb_error_t error; 1401 1402 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1403 req.bRequest = RAL_READ_EEPROM; 1404 USETW(req.wValue, 0); 1405 USETW(req.wIndex, addr); 1406 USETW(req.wLength, len); 1407 1408 error = ural_do_request(sc, &req, buf); 1409 if (error != 0) { 1410 device_printf(sc->sc_dev, "could not read EEPROM: %s\n", 1411 usbd_errstr(error)); 1412 } 1413} 1414 1415static uint16_t 1416ural_read(struct ural_softc *sc, uint16_t reg) 1417{ 1418 struct usb_device_request req; 1419 usb_error_t error; 1420 uint16_t val; 1421 1422 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1423 req.bRequest = RAL_READ_MAC; 1424 USETW(req.wValue, 0); 1425 USETW(req.wIndex, reg); 1426 USETW(req.wLength, sizeof (uint16_t)); 1427 1428 error = ural_do_request(sc, &req, &val); 1429 if (error != 0) { 1430 device_printf(sc->sc_dev, "could not read MAC register: %s\n", 1431 usbd_errstr(error)); 1432 return 0; 1433 } 1434 1435 return le16toh(val); 1436} 1437 1438static void 1439ural_read_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 1440{ 1441 struct usb_device_request req; 1442 usb_error_t error; 1443 1444 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1445 req.bRequest = RAL_READ_MULTI_MAC; 1446 USETW(req.wValue, 0); 1447 USETW(req.wIndex, reg); 1448 USETW(req.wLength, len); 1449 1450 error = ural_do_request(sc, &req, buf); 1451 if (error != 0) { 1452 device_printf(sc->sc_dev, "could not read MAC register: %s\n", 1453 usbd_errstr(error)); 1454 } 1455} 1456 1457static void 1458ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val) 1459{ 1460 struct usb_device_request req; 1461 usb_error_t error; 1462 1463 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1464 req.bRequest = RAL_WRITE_MAC; 1465 USETW(req.wValue, val); 1466 USETW(req.wIndex, reg); 1467 USETW(req.wLength, 0); 1468 1469 error = ural_do_request(sc, &req, NULL); 1470 if (error != 0) { 1471 device_printf(sc->sc_dev, "could not write MAC register: %s\n", 1472 usbd_errstr(error)); 1473 } 1474} 1475 1476static void 1477ural_write_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 1478{ 1479 struct usb_device_request req; 1480 usb_error_t error; 1481 1482 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1483 req.bRequest = RAL_WRITE_MULTI_MAC; 1484 USETW(req.wValue, 0); 1485 USETW(req.wIndex, reg); 1486 USETW(req.wLength, len); 1487 1488 error = ural_do_request(sc, &req, buf); 1489 if (error != 0) { 1490 device_printf(sc->sc_dev, "could not write MAC register: %s\n", 1491 usbd_errstr(error)); 1492 } 1493} 1494 1495static void 1496ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val) 1497{ 1498 uint16_t tmp; 1499 int ntries; 1500 1501 for (ntries = 0; ntries < 100; ntries++) { 1502 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 1503 break; 1504 if (ural_pause(sc, hz / 100)) 1505 break; 1506 } 1507 if (ntries == 100) { 1508 device_printf(sc->sc_dev, "could not write to BBP\n"); 1509 return; 1510 } 1511 1512 tmp = reg << 8 | val; 1513 ural_write(sc, RAL_PHY_CSR7, tmp); 1514} 1515 1516static uint8_t 1517ural_bbp_read(struct ural_softc *sc, uint8_t reg) 1518{ 1519 uint16_t val; 1520 int ntries; 1521 1522 val = RAL_BBP_WRITE | reg << 8; 1523 ural_write(sc, RAL_PHY_CSR7, val); 1524 1525 for (ntries = 0; ntries < 100; ntries++) { 1526 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 1527 break; 1528 if (ural_pause(sc, hz / 100)) 1529 break; 1530 } 1531 if (ntries == 100) { 1532 device_printf(sc->sc_dev, "could not read BBP\n"); 1533 return 0; 1534 } 1535 1536 return ural_read(sc, RAL_PHY_CSR7) & 0xff; 1537} 1538 1539static void 1540ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val) 1541{ 1542 uint32_t tmp; 1543 int ntries; 1544 1545 for (ntries = 0; ntries < 100; ntries++) { 1546 if (!(ural_read(sc, RAL_PHY_CSR10) & RAL_RF_LOBUSY)) 1547 break; 1548 if (ural_pause(sc, hz / 100)) 1549 break; 1550 } 1551 if (ntries == 100) { 1552 device_printf(sc->sc_dev, "could not write to RF\n"); 1553 return; 1554 } 1555 1556 tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xfffff) << 2 | (reg & 0x3); 1557 ural_write(sc, RAL_PHY_CSR9, tmp & 0xffff); 1558 ural_write(sc, RAL_PHY_CSR10, tmp >> 16); 1559 1560 /* remember last written value in sc */ 1561 sc->rf_regs[reg] = val; 1562 1563 DPRINTFN(15, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff); 1564} 1565 1566static void 1567ural_scan_start(struct ieee80211com *ic) 1568{ 1569 struct ural_softc *sc = ic->ic_softc; 1570 1571 RAL_LOCK(sc); 1572 ural_write(sc, RAL_TXRX_CSR19, 0); 1573 ural_set_bssid(sc, ieee80211broadcastaddr); 1574 RAL_UNLOCK(sc); 1575} 1576 1577static void 1578ural_scan_end(struct ieee80211com *ic) 1579{ 1580 struct ural_softc *sc = ic->ic_softc; 1581 1582 RAL_LOCK(sc); 1583 ural_enable_tsf_sync(sc); 1584 ural_set_bssid(sc, sc->sc_bssid); 1585 RAL_UNLOCK(sc); 1586 1587} 1588 1589static void 1590ural_getradiocaps(struct ieee80211com *ic, 1591 int maxchans, int *nchans, struct ieee80211_channel chans[]) 1592{ 1593 struct ural_softc *sc = ic->ic_softc; 1594 uint8_t bands[IEEE80211_MODE_BYTES]; 1595 1596 memset(bands, 0, sizeof(bands)); 1597 setbit(bands, IEEE80211_MODE_11B); 1598 setbit(bands, IEEE80211_MODE_11G); 1599 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0); 1600 1601 if (sc->rf_rev == RAL_RF_5222) { 1602 setbit(bands, IEEE80211_MODE_11A); 1603 ieee80211_add_channel_list_5ghz(chans, maxchans, nchans, 1604 ural_chan_5ghz, nitems(ural_chan_5ghz), bands, 0); 1605 } 1606} 1607 1608static void 1609ural_set_channel(struct ieee80211com *ic) 1610{ 1611 struct ural_softc *sc = ic->ic_softc; 1612 1613 RAL_LOCK(sc); 1614 ural_set_chan(sc, ic->ic_curchan); 1615 RAL_UNLOCK(sc); 1616} 1617 1618static void 1619ural_set_chan(struct ural_softc *sc, struct ieee80211_channel *c) 1620{ 1621 struct ieee80211com *ic = &sc->sc_ic; 1622 uint8_t power, tmp; 1623 int i, chan; 1624 1625 chan = ieee80211_chan2ieee(ic, c); 1626 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 1627 return; 1628 1629 if (IEEE80211_IS_CHAN_2GHZ(c)) 1630 power = min(sc->txpow[chan - 1], 31); 1631 else 1632 power = 31; 1633 1634 /* adjust txpower using ifconfig settings */ 1635 power -= (100 - ic->ic_txpowlimit) / 8; 1636 1637 DPRINTFN(2, "setting channel to %u, txpower to %u\n", chan, power); 1638 1639 switch (sc->rf_rev) { 1640 case RAL_RF_2522: 1641 ural_rf_write(sc, RAL_RF1, 0x00814); 1642 ural_rf_write(sc, RAL_RF2, ural_rf2522_r2[chan - 1]); 1643 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1644 break; 1645 1646 case RAL_RF_2523: 1647 ural_rf_write(sc, RAL_RF1, 0x08804); 1648 ural_rf_write(sc, RAL_RF2, ural_rf2523_r2[chan - 1]); 1649 ural_rf_write(sc, RAL_RF3, power << 7 | 0x38044); 1650 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1651 break; 1652 1653 case RAL_RF_2524: 1654 ural_rf_write(sc, RAL_RF1, 0x0c808); 1655 ural_rf_write(sc, RAL_RF2, ural_rf2524_r2[chan - 1]); 1656 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1657 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1658 break; 1659 1660 case RAL_RF_2525: 1661 ural_rf_write(sc, RAL_RF1, 0x08808); 1662 ural_rf_write(sc, RAL_RF2, ural_rf2525_hi_r2[chan - 1]); 1663 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1664 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1665 1666 ural_rf_write(sc, RAL_RF1, 0x08808); 1667 ural_rf_write(sc, RAL_RF2, ural_rf2525_r2[chan - 1]); 1668 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1669 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1670 break; 1671 1672 case RAL_RF_2525E: 1673 ural_rf_write(sc, RAL_RF1, 0x08808); 1674 ural_rf_write(sc, RAL_RF2, ural_rf2525e_r2[chan - 1]); 1675 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1676 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282); 1677 break; 1678 1679 case RAL_RF_2526: 1680 ural_rf_write(sc, RAL_RF2, ural_rf2526_hi_r2[chan - 1]); 1681 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1682 ural_rf_write(sc, RAL_RF1, 0x08804); 1683 1684 ural_rf_write(sc, RAL_RF2, ural_rf2526_r2[chan - 1]); 1685 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1686 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1687 break; 1688 1689 /* dual-band RF */ 1690 case RAL_RF_5222: 1691 for (i = 0; ural_rf5222[i].chan != chan; i++); 1692 1693 ural_rf_write(sc, RAL_RF1, ural_rf5222[i].r1); 1694 ural_rf_write(sc, RAL_RF2, ural_rf5222[i].r2); 1695 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1696 ural_rf_write(sc, RAL_RF4, ural_rf5222[i].r4); 1697 break; 1698 } 1699 1700 if (ic->ic_opmode != IEEE80211_M_MONITOR && 1701 (ic->ic_flags & IEEE80211_F_SCAN) == 0) { 1702 /* set Japan filter bit for channel 14 */ 1703 tmp = ural_bbp_read(sc, 70); 1704 1705 tmp &= ~RAL_JAPAN_FILTER; 1706 if (chan == 14) 1707 tmp |= RAL_JAPAN_FILTER; 1708 1709 ural_bbp_write(sc, 70, tmp); 1710 1711 /* clear CRC errors */ 1712 ural_read(sc, RAL_STA_CSR0); 1713 1714 ural_pause(sc, hz / 100); 1715 ural_disable_rf_tune(sc); 1716 } 1717 1718 /* XXX doesn't belong here */ 1719 /* update basic rate set */ 1720 ural_set_basicrates(sc, c); 1721 1722 /* give the hardware some time to do the switchover */ 1723 ural_pause(sc, hz / 100); 1724} 1725 1726/* 1727 * Disable RF auto-tuning. 1728 */ 1729static void 1730ural_disable_rf_tune(struct ural_softc *sc) 1731{ 1732 uint32_t tmp; 1733 1734 if (sc->rf_rev != RAL_RF_2523) { 1735 tmp = sc->rf_regs[RAL_RF1] & ~RAL_RF1_AUTOTUNE; 1736 ural_rf_write(sc, RAL_RF1, tmp); 1737 } 1738 1739 tmp = sc->rf_regs[RAL_RF3] & ~RAL_RF3_AUTOTUNE; 1740 ural_rf_write(sc, RAL_RF3, tmp); 1741 1742 DPRINTFN(2, "disabling RF autotune\n"); 1743} 1744 1745/* 1746 * Refer to IEEE Std 802.11-1999 pp. 123 for more information on TSF 1747 * synchronization. 1748 */ 1749static void 1750ural_enable_tsf_sync(struct ural_softc *sc) 1751{ 1752 struct ieee80211com *ic = &sc->sc_ic; 1753 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1754 uint16_t logcwmin, preload, tmp; 1755 1756 /* first, disable TSF synchronization */ 1757 ural_write(sc, RAL_TXRX_CSR19, 0); 1758 1759 tmp = (16 * vap->iv_bss->ni_intval) << 4; 1760 ural_write(sc, RAL_TXRX_CSR18, tmp); 1761 1762 logcwmin = (ic->ic_opmode == IEEE80211_M_IBSS) ? 2 : 0; 1763 preload = (ic->ic_opmode == IEEE80211_M_IBSS) ? 320 : 6; 1764 tmp = logcwmin << 12 | preload; 1765 ural_write(sc, RAL_TXRX_CSR20, tmp); 1766 1767 /* finally, enable TSF synchronization */ 1768 tmp = RAL_ENABLE_TSF | RAL_ENABLE_TBCN; 1769 if (ic->ic_opmode == IEEE80211_M_STA) 1770 tmp |= RAL_ENABLE_TSF_SYNC(1); 1771 else 1772 tmp |= RAL_ENABLE_TSF_SYNC(2) | RAL_ENABLE_BEACON_GENERATOR; 1773 ural_write(sc, RAL_TXRX_CSR19, tmp); 1774 1775 DPRINTF("enabling TSF synchronization\n"); 1776} 1777 1778static void 1779ural_enable_tsf(struct ural_softc *sc) 1780{ 1781 /* first, disable TSF synchronization */ 1782 ural_write(sc, RAL_TXRX_CSR19, 0); 1783 ural_write(sc, RAL_TXRX_CSR19, RAL_ENABLE_TSF | RAL_ENABLE_TSF_SYNC(2)); 1784} 1785 1786#define RAL_RXTX_TURNAROUND 5 /* us */ 1787static void 1788ural_update_slot(struct ural_softc *sc) 1789{ 1790 struct ieee80211com *ic = &sc->sc_ic; 1791 uint16_t slottime, sifs, eifs; 1792 1793 slottime = IEEE80211_GET_SLOTTIME(ic); 1794 1795 /* 1796 * These settings may sound a bit inconsistent but this is what the 1797 * reference driver does. 1798 */ 1799 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1800 sifs = 16 - RAL_RXTX_TURNAROUND; 1801 eifs = 364; 1802 } else { 1803 sifs = 10 - RAL_RXTX_TURNAROUND; 1804 eifs = 64; 1805 } 1806 1807 ural_write(sc, RAL_MAC_CSR10, slottime); 1808 ural_write(sc, RAL_MAC_CSR11, sifs); 1809 ural_write(sc, RAL_MAC_CSR12, eifs); 1810} 1811 1812static void 1813ural_set_txpreamble(struct ural_softc *sc) 1814{ 1815 struct ieee80211com *ic = &sc->sc_ic; 1816 uint16_t tmp; 1817 1818 tmp = ural_read(sc, RAL_TXRX_CSR10); 1819 1820 tmp &= ~RAL_SHORT_PREAMBLE; 1821 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1822 tmp |= RAL_SHORT_PREAMBLE; 1823 1824 ural_write(sc, RAL_TXRX_CSR10, tmp); 1825} 1826 1827static void 1828ural_set_basicrates(struct ural_softc *sc, const struct ieee80211_channel *c) 1829{ 1830 /* XXX wrong, take from rate set */ 1831 /* update basic rate set */ 1832 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1833 /* 11a basic rates: 6, 12, 24Mbps */ 1834 ural_write(sc, RAL_TXRX_CSR11, 0x150); 1835 } else if (IEEE80211_IS_CHAN_ANYG(c)) { 1836 /* 11g basic rates: 1, 2, 5.5, 11, 6, 12, 24Mbps */ 1837 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 1838 } else { 1839 /* 11b basic rates: 1, 2Mbps */ 1840 ural_write(sc, RAL_TXRX_CSR11, 0x3); 1841 } 1842} 1843 1844static void 1845ural_set_bssid(struct ural_softc *sc, const uint8_t *bssid) 1846{ 1847 uint16_t tmp; 1848 1849 tmp = bssid[0] | bssid[1] << 8; 1850 ural_write(sc, RAL_MAC_CSR5, tmp); 1851 1852 tmp = bssid[2] | bssid[3] << 8; 1853 ural_write(sc, RAL_MAC_CSR6, tmp); 1854 1855 tmp = bssid[4] | bssid[5] << 8; 1856 ural_write(sc, RAL_MAC_CSR7, tmp); 1857 1858 DPRINTF("setting BSSID to %6D\n", bssid, ":"); 1859} 1860 1861static void 1862ural_set_macaddr(struct ural_softc *sc, const uint8_t *addr) 1863{ 1864 uint16_t tmp; 1865 1866 tmp = addr[0] | addr[1] << 8; 1867 ural_write(sc, RAL_MAC_CSR2, tmp); 1868 1869 tmp = addr[2] | addr[3] << 8; 1870 ural_write(sc, RAL_MAC_CSR3, tmp); 1871 1872 tmp = addr[4] | addr[5] << 8; 1873 ural_write(sc, RAL_MAC_CSR4, tmp); 1874 1875 DPRINTF("setting MAC address to %6D\n", addr, ":"); 1876} 1877 1878static void 1879ural_setpromisc(struct ural_softc *sc) 1880{ 1881 uint32_t tmp; 1882 1883 tmp = ural_read(sc, RAL_TXRX_CSR2); 1884 1885 tmp &= ~RAL_DROP_NOT_TO_ME; 1886 if (sc->sc_ic.ic_promisc == 0) 1887 tmp |= RAL_DROP_NOT_TO_ME; 1888 1889 ural_write(sc, RAL_TXRX_CSR2, tmp); 1890 1891 DPRINTF("%s promiscuous mode\n", sc->sc_ic.ic_promisc ? 1892 "entering" : "leaving"); 1893} 1894 1895static void 1896ural_update_promisc(struct ieee80211com *ic) 1897{ 1898 struct ural_softc *sc = ic->ic_softc; 1899 1900 RAL_LOCK(sc); 1901 if (sc->sc_running) 1902 ural_setpromisc(sc); 1903 RAL_UNLOCK(sc); 1904} 1905 1906static const char * 1907ural_get_rf(int rev) 1908{ 1909 switch (rev) { 1910 case RAL_RF_2522: return "RT2522"; 1911 case RAL_RF_2523: return "RT2523"; 1912 case RAL_RF_2524: return "RT2524"; 1913 case RAL_RF_2525: return "RT2525"; 1914 case RAL_RF_2525E: return "RT2525e"; 1915 case RAL_RF_2526: return "RT2526"; 1916 case RAL_RF_5222: return "RT5222"; 1917 default: return "unknown"; 1918 } 1919} 1920 1921static void 1922ural_read_eeprom(struct ural_softc *sc) 1923{ 1924 struct ieee80211com *ic = &sc->sc_ic; 1925 uint16_t val; 1926 1927 ural_eeprom_read(sc, RAL_EEPROM_CONFIG0, &val, 2); 1928 val = le16toh(val); 1929 sc->rf_rev = (val >> 11) & 0x7; 1930 sc->hw_radio = (val >> 10) & 0x1; 1931 sc->led_mode = (val >> 6) & 0x7; 1932 sc->rx_ant = (val >> 4) & 0x3; 1933 sc->tx_ant = (val >> 2) & 0x3; 1934 sc->nb_ant = val & 0x3; 1935 1936 /* read MAC address */ 1937 ural_eeprom_read(sc, RAL_EEPROM_ADDRESS, ic->ic_macaddr, 6); 1938 1939 /* read default values for BBP registers */ 1940 ural_eeprom_read(sc, RAL_EEPROM_BBP_BASE, sc->bbp_prom, 2 * 16); 1941 1942 /* read Tx power for all b/g channels */ 1943 ural_eeprom_read(sc, RAL_EEPROM_TXPOWER, sc->txpow, 14); 1944} 1945 1946static int 1947ural_bbp_init(struct ural_softc *sc) 1948{ 1949 int i, ntries; 1950 1951 /* wait for BBP to be ready */ 1952 for (ntries = 0; ntries < 100; ntries++) { 1953 if (ural_bbp_read(sc, RAL_BBP_VERSION) != 0) 1954 break; 1955 if (ural_pause(sc, hz / 100)) 1956 break; 1957 } 1958 if (ntries == 100) { 1959 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 1960 return EIO; 1961 } 1962 1963 /* initialize BBP registers to default values */ 1964 for (i = 0; i < nitems(ural_def_bbp); i++) 1965 ural_bbp_write(sc, ural_def_bbp[i].reg, ural_def_bbp[i].val); 1966 1967#if 0 1968 /* initialize BBP registers to values stored in EEPROM */ 1969 for (i = 0; i < 16; i++) { 1970 if (sc->bbp_prom[i].reg == 0xff) 1971 continue; 1972 ural_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 1973 } 1974#endif 1975 1976 return 0; 1977} 1978 1979static void 1980ural_set_txantenna(struct ural_softc *sc, int antenna) 1981{ 1982 uint16_t tmp; 1983 uint8_t tx; 1984 1985 tx = ural_bbp_read(sc, RAL_BBP_TX) & ~RAL_BBP_ANTMASK; 1986 if (antenna == 1) 1987 tx |= RAL_BBP_ANTA; 1988 else if (antenna == 2) 1989 tx |= RAL_BBP_ANTB; 1990 else 1991 tx |= RAL_BBP_DIVERSITY; 1992 1993 /* need to force I/Q flip for RF 2525e, 2526 and 5222 */ 1994 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526 || 1995 sc->rf_rev == RAL_RF_5222) 1996 tx |= RAL_BBP_FLIPIQ; 1997 1998 ural_bbp_write(sc, RAL_BBP_TX, tx); 1999 2000 /* update values in PHY_CSR5 and PHY_CSR6 */ 2001 tmp = ural_read(sc, RAL_PHY_CSR5) & ~0x7; 2002 ural_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7)); 2003 2004 tmp = ural_read(sc, RAL_PHY_CSR6) & ~0x7; 2005 ural_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7)); 2006} 2007 2008static void 2009ural_set_rxantenna(struct ural_softc *sc, int antenna) 2010{ 2011 uint8_t rx; 2012 2013 rx = ural_bbp_read(sc, RAL_BBP_RX) & ~RAL_BBP_ANTMASK; 2014 if (antenna == 1) 2015 rx |= RAL_BBP_ANTA; 2016 else if (antenna == 2) 2017 rx |= RAL_BBP_ANTB; 2018 else 2019 rx |= RAL_BBP_DIVERSITY; 2020 2021 /* need to force no I/Q flip for RF 2525e and 2526 */ 2022 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526) 2023 rx &= ~RAL_BBP_FLIPIQ; 2024 2025 ural_bbp_write(sc, RAL_BBP_RX, rx); 2026} 2027 2028static void 2029ural_init(struct ural_softc *sc) 2030{ 2031 struct ieee80211com *ic = &sc->sc_ic; 2032 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2033 uint16_t tmp; 2034 int i, ntries; 2035 2036 RAL_LOCK_ASSERT(sc, MA_OWNED); 2037 2038 ural_set_testmode(sc); 2039 ural_write(sc, 0x308, 0x00f0); /* XXX magic */ 2040 2041 ural_stop(sc); 2042 2043 /* initialize MAC registers to default values */ 2044 for (i = 0; i < nitems(ural_def_mac); i++) 2045 ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val); 2046 2047 /* wait for BBP and RF to wake up (this can take a long time!) */ 2048 for (ntries = 0; ntries < 100; ntries++) { 2049 tmp = ural_read(sc, RAL_MAC_CSR17); 2050 if ((tmp & (RAL_BBP_AWAKE | RAL_RF_AWAKE)) == 2051 (RAL_BBP_AWAKE | RAL_RF_AWAKE)) 2052 break; 2053 if (ural_pause(sc, hz / 100)) 2054 break; 2055 } 2056 if (ntries == 100) { 2057 device_printf(sc->sc_dev, 2058 "timeout waiting for BBP/RF to wakeup\n"); 2059 goto fail; 2060 } 2061 2062 /* we're ready! */ 2063 ural_write(sc, RAL_MAC_CSR1, RAL_HOST_READY); 2064 2065 /* set basic rate set (will be updated later) */ 2066 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 2067 2068 if (ural_bbp_init(sc) != 0) 2069 goto fail; 2070 2071 ural_set_chan(sc, ic->ic_curchan); 2072 2073 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 2074 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta); 2075 2076 ural_set_txantenna(sc, sc->tx_ant); 2077 ural_set_rxantenna(sc, sc->rx_ant); 2078 2079 ural_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr); 2080 2081 /* 2082 * Allocate Tx and Rx xfer queues. 2083 */ 2084 ural_setup_tx_list(sc); 2085 2086 /* kick Rx */ 2087 tmp = RAL_DROP_PHY | RAL_DROP_CRC; 2088 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2089 tmp |= RAL_DROP_CTL | RAL_DROP_BAD_VERSION; 2090 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2091 tmp |= RAL_DROP_TODS; 2092 if (ic->ic_promisc == 0) 2093 tmp |= RAL_DROP_NOT_TO_ME; 2094 } 2095 ural_write(sc, RAL_TXRX_CSR2, tmp); 2096 2097 sc->sc_running = 1; 2098 usbd_xfer_set_stall(sc->sc_xfer[URAL_BULK_WR]); 2099 usbd_transfer_start(sc->sc_xfer[URAL_BULK_RD]); 2100 return; 2101 2102fail: ural_stop(sc); 2103} 2104 2105static void 2106ural_stop(struct ural_softc *sc) 2107{ 2108 2109 RAL_LOCK_ASSERT(sc, MA_OWNED); 2110 2111 sc->sc_running = 0; 2112 2113 /* 2114 * Drain all the transfers, if not already drained: 2115 */ 2116 RAL_UNLOCK(sc); 2117 usbd_transfer_drain(sc->sc_xfer[URAL_BULK_WR]); 2118 usbd_transfer_drain(sc->sc_xfer[URAL_BULK_RD]); 2119 RAL_LOCK(sc); 2120 2121 ural_unsetup_tx_list(sc); 2122 2123 /* disable Rx */ 2124 ural_write(sc, RAL_TXRX_CSR2, RAL_DISABLE_RX); 2125 /* reset ASIC and BBP (but won't reset MAC registers!) */ 2126 ural_write(sc, RAL_MAC_CSR1, RAL_RESET_ASIC | RAL_RESET_BBP); 2127 /* wait a little */ 2128 ural_pause(sc, hz / 10); 2129 ural_write(sc, RAL_MAC_CSR1, 0); 2130 /* wait a little */ 2131 ural_pause(sc, hz / 10); 2132} 2133 2134static int 2135ural_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 2136 const struct ieee80211_bpf_params *params) 2137{ 2138 struct ieee80211com *ic = ni->ni_ic; 2139 struct ural_softc *sc = ic->ic_softc; 2140 2141 RAL_LOCK(sc); 2142 /* prevent management frames from being sent if we're not ready */ 2143 if (!sc->sc_running) { 2144 RAL_UNLOCK(sc); 2145 m_freem(m); 2146 return ENETDOWN; 2147 } 2148 if (sc->tx_nfree < RAL_TX_MINFREE) { 2149 RAL_UNLOCK(sc); 2150 m_freem(m); 2151 return EIO; 2152 } 2153 2154 if (params == NULL) { 2155 /* 2156 * Legacy path; interpret frame contents to decide 2157 * precisely how to send the frame. 2158 */ 2159 if (ural_tx_mgt(sc, m, ni) != 0) 2160 goto bad; 2161 } else { 2162 /* 2163 * Caller supplied explicit parameters to use in 2164 * sending the frame. 2165 */ 2166 if (ural_tx_raw(sc, m, ni, params) != 0) 2167 goto bad; 2168 } 2169 RAL_UNLOCK(sc); 2170 return 0; 2171bad: 2172 RAL_UNLOCK(sc); 2173 return EIO; /* XXX */ 2174} 2175 2176static void 2177ural_ratectl_start(struct ural_softc *sc, struct ieee80211_node *ni) 2178{ 2179 struct ieee80211vap *vap = ni->ni_vap; 2180 struct ural_vap *uvp = URAL_VAP(vap); 2181 2182 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 2183 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta); 2184 2185 usb_callout_reset(&uvp->ratectl_ch, hz, ural_ratectl_timeout, uvp); 2186} 2187 2188static void 2189ural_ratectl_timeout(void *arg) 2190{ 2191 struct ural_vap *uvp = arg; 2192 struct ieee80211vap *vap = &uvp->vap; 2193 struct ieee80211com *ic = vap->iv_ic; 2194 2195 ieee80211_runtask(ic, &uvp->ratectl_task); 2196} 2197 2198static void 2199ural_ratectl_task(void *arg, int pending) 2200{ 2201 struct ural_vap *uvp = arg; 2202 struct ieee80211vap *vap = &uvp->vap; 2203 struct ieee80211com *ic = vap->iv_ic; 2204 struct ural_softc *sc = ic->ic_softc; 2205 struct ieee80211_node *ni; 2206 int ok, fail; 2207 int sum, retrycnt; 2208 2209 ni = ieee80211_ref_node(vap->iv_bss); 2210 RAL_LOCK(sc); 2211 /* read and clear statistic registers (STA_CSR0 to STA_CSR10) */ 2212 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof(sc->sta)); 2213 2214 ok = sc->sta[7] + /* TX ok w/o retry */ 2215 sc->sta[8]; /* TX ok w/ retry */ 2216 fail = sc->sta[9]; /* TX retry-fail count */ 2217 sum = ok+fail; 2218 retrycnt = sc->sta[8] + fail; 2219 2220 ieee80211_ratectl_tx_update(vap, ni, &sum, &ok, &retrycnt); 2221 (void) ieee80211_ratectl_rate(ni, NULL, 0); 2222 2223 /* count TX retry-fail as Tx errors */ 2224 if_inc_counter(ni->ni_vap->iv_ifp, IFCOUNTER_OERRORS, fail); 2225 2226 usb_callout_reset(&uvp->ratectl_ch, hz, ural_ratectl_timeout, uvp); 2227 RAL_UNLOCK(sc); 2228 ieee80211_free_node(ni); 2229} 2230 2231static int 2232ural_pause(struct ural_softc *sc, int timeout) 2233{ 2234 2235 usb_pause_mtx(&sc->sc_mtx, timeout); 2236 return (0); 2237} 2238