if_rsu.c revision 287953
1/* $OpenBSD: if_rsu.c,v 1.17 2013/04/15 09:23:01 mglocker Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18#include <sys/cdefs.h> 19__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_rsu.c 287953 2015-09-18 07:26:34Z adrian $"); 20 21/* 22 * Driver for Realtek RTL8188SU/RTL8191SU/RTL8192SU. 23 * 24 * TODO: 25 * o 11n support 26 * o h/w crypto 27 * o hostap / ibss / mesh 28 */ 29 30#include <sys/param.h> 31#include <sys/endian.h> 32#include <sys/sockio.h> 33#include <sys/mbuf.h> 34#include <sys/kernel.h> 35#include <sys/socket.h> 36#include <sys/systm.h> 37#include <sys/conf.h> 38#include <sys/bus.h> 39#include <sys/rman.h> 40#include <sys/firmware.h> 41#include <sys/module.h> 42 43#include <machine/bus.h> 44#include <machine/resource.h> 45 46#include <net/bpf.h> 47#include <net/if.h> 48#include <net/if_var.h> 49#include <net/if_arp.h> 50#include <net/if_dl.h> 51#include <net/if_media.h> 52#include <net/if_types.h> 53 54#include <netinet/in.h> 55#include <netinet/in_systm.h> 56#include <netinet/in_var.h> 57#include <netinet/if_ether.h> 58#include <netinet/ip.h> 59 60#include <net80211/ieee80211_var.h> 61#include <net80211/ieee80211_regdomain.h> 62#include <net80211/ieee80211_radiotap.h> 63 64#include <dev/usb/usb.h> 65#include <dev/usb/usbdi.h> 66#include "usbdevs.h" 67 68#define USB_DEBUG_VAR rsu_debug 69#include <dev/usb/usb_debug.h> 70 71#include <dev/usb/wlan/if_rsureg.h> 72 73#ifdef USB_DEBUG 74static int rsu_debug = 0; 75SYSCTL_NODE(_hw_usb, OID_AUTO, rsu, CTLFLAG_RW, 0, "USB rsu"); 76SYSCTL_INT(_hw_usb_rsu, OID_AUTO, debug, CTLFLAG_RWTUN, &rsu_debug, 0, 77 "Debug level"); 78#define RSU_DPRINTF(_sc, _flg, ...) \ 79 do \ 80 if (((_flg) == (RSU_DEBUG_ANY)) || (rsu_debug & (_flg))) \ 81 device_printf((_sc)->sc_dev, __VA_ARGS__); \ 82 while (0) 83#else 84#define RSU_DPRINTF(_sc, _flg, ...) 85#endif 86 87static int rsu_enable_11n = 0; 88TUNABLE_INT("hw.usb.rsu.enable_11n", &rsu_enable_11n); 89 90#define RSU_DEBUG_ANY 0xffffffff 91#define RSU_DEBUG_TX 0x00000001 92#define RSU_DEBUG_RX 0x00000002 93#define RSU_DEBUG_RESET 0x00000004 94#define RSU_DEBUG_CALIB 0x00000008 95#define RSU_DEBUG_STATE 0x00000010 96#define RSU_DEBUG_SCAN 0x00000020 97#define RSU_DEBUG_FWCMD 0x00000040 98#define RSU_DEBUG_TXDONE 0x00000080 99#define RSU_DEBUG_FW 0x00000100 100#define RSU_DEBUG_FWDBG 0x00000200 101 102static const STRUCT_USB_HOST_ID rsu_devs[] = { 103#define RSU_HT_NOT_SUPPORTED 0 104#define RSU_HT_SUPPORTED 1 105#define RSU_DEV_HT(v,p) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, \ 106 RSU_HT_SUPPORTED) } 107#define RSU_DEV(v,p) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, \ 108 RSU_HT_NOT_SUPPORTED) } 109 RSU_DEV(ASUS, RTL8192SU), 110 RSU_DEV(AZUREWAVE, RTL8192SU_4), 111 RSU_DEV_HT(ACCTON, RTL8192SU), 112 RSU_DEV_HT(ASUS, USBN10), 113 RSU_DEV_HT(AZUREWAVE, RTL8192SU_1), 114 RSU_DEV_HT(AZUREWAVE, RTL8192SU_2), 115 RSU_DEV_HT(AZUREWAVE, RTL8192SU_3), 116 RSU_DEV_HT(AZUREWAVE, RTL8192SU_5), 117 RSU_DEV_HT(BELKIN, RTL8192SU_1), 118 RSU_DEV_HT(BELKIN, RTL8192SU_2), 119 RSU_DEV_HT(BELKIN, RTL8192SU_3), 120 RSU_DEV_HT(CONCEPTRONIC2, RTL8192SU_1), 121 RSU_DEV_HT(CONCEPTRONIC2, RTL8192SU_2), 122 RSU_DEV_HT(CONCEPTRONIC2, RTL8192SU_3), 123 RSU_DEV_HT(COREGA, RTL8192SU), 124 RSU_DEV_HT(DLINK2, DWA131A1), 125 RSU_DEV_HT(DLINK2, RTL8192SU_1), 126 RSU_DEV_HT(DLINK2, RTL8192SU_2), 127 RSU_DEV_HT(EDIMAX, RTL8192SU_1), 128 RSU_DEV_HT(EDIMAX, RTL8192SU_2), 129 RSU_DEV_HT(EDIMAX, EW7622UMN), 130 RSU_DEV_HT(GUILLEMOT, HWGUN54), 131 RSU_DEV_HT(GUILLEMOT, HWNUM300), 132 RSU_DEV_HT(HAWKING, RTL8192SU_1), 133 RSU_DEV_HT(HAWKING, RTL8192SU_2), 134 RSU_DEV_HT(PLANEX2, GWUSNANO), 135 RSU_DEV_HT(REALTEK, RTL8171), 136 RSU_DEV_HT(REALTEK, RTL8172), 137 RSU_DEV_HT(REALTEK, RTL8173), 138 RSU_DEV_HT(REALTEK, RTL8174), 139 RSU_DEV_HT(REALTEK, RTL8192SU), 140 RSU_DEV_HT(REALTEK, RTL8712), 141 RSU_DEV_HT(REALTEK, RTL8713), 142 RSU_DEV_HT(SENAO, RTL8192SU_1), 143 RSU_DEV_HT(SENAO, RTL8192SU_2), 144 RSU_DEV_HT(SITECOMEU, WL349V1), 145 RSU_DEV_HT(SITECOMEU, WL353), 146 RSU_DEV_HT(SWEEX2, LW154), 147 RSU_DEV_HT(TRENDNET, TEW646UBH), 148#undef RSU_DEV_HT 149#undef RSU_DEV 150}; 151 152static device_probe_t rsu_match; 153static device_attach_t rsu_attach; 154static device_detach_t rsu_detach; 155static usb_callback_t rsu_bulk_tx_callback_be_bk; 156static usb_callback_t rsu_bulk_tx_callback_vi_vo; 157static usb_callback_t rsu_bulk_tx_callback_h2c; 158static usb_callback_t rsu_bulk_rx_callback; 159static usb_error_t rsu_do_request(struct rsu_softc *, 160 struct usb_device_request *, void *); 161static struct ieee80211vap * 162 rsu_vap_create(struct ieee80211com *, const char name[], 163 int, enum ieee80211_opmode, int, const uint8_t bssid[], 164 const uint8_t mac[]); 165static void rsu_vap_delete(struct ieee80211vap *); 166static void rsu_scan_start(struct ieee80211com *); 167static void rsu_scan_end(struct ieee80211com *); 168static void rsu_set_channel(struct ieee80211com *); 169static void rsu_update_mcast(struct ieee80211com *); 170static int rsu_alloc_rx_list(struct rsu_softc *); 171static void rsu_free_rx_list(struct rsu_softc *); 172static int rsu_alloc_tx_list(struct rsu_softc *); 173static void rsu_free_tx_list(struct rsu_softc *); 174static void rsu_free_list(struct rsu_softc *, struct rsu_data [], int); 175static struct rsu_data *_rsu_getbuf(struct rsu_softc *); 176static struct rsu_data *rsu_getbuf(struct rsu_softc *); 177static void rsu_freebuf(struct rsu_softc *, struct rsu_data *); 178static int rsu_write_region_1(struct rsu_softc *, uint16_t, uint8_t *, 179 int); 180static void rsu_write_1(struct rsu_softc *, uint16_t, uint8_t); 181static void rsu_write_2(struct rsu_softc *, uint16_t, uint16_t); 182static void rsu_write_4(struct rsu_softc *, uint16_t, uint32_t); 183static int rsu_read_region_1(struct rsu_softc *, uint16_t, uint8_t *, 184 int); 185static uint8_t rsu_read_1(struct rsu_softc *, uint16_t); 186static uint16_t rsu_read_2(struct rsu_softc *, uint16_t); 187static uint32_t rsu_read_4(struct rsu_softc *, uint16_t); 188static int rsu_fw_iocmd(struct rsu_softc *, uint32_t); 189static uint8_t rsu_efuse_read_1(struct rsu_softc *, uint16_t); 190static int rsu_read_rom(struct rsu_softc *); 191static int rsu_fw_cmd(struct rsu_softc *, uint8_t, void *, int); 192static void rsu_calib_task(void *, int); 193static int rsu_newstate(struct ieee80211vap *, enum ieee80211_state, int); 194#ifdef notyet 195static void rsu_set_key(struct rsu_softc *, const struct ieee80211_key *); 196static void rsu_delete_key(struct rsu_softc *, const struct ieee80211_key *); 197#endif 198static int rsu_site_survey(struct rsu_softc *, struct ieee80211vap *); 199static int rsu_join_bss(struct rsu_softc *, struct ieee80211_node *); 200static int rsu_disconnect(struct rsu_softc *); 201static void rsu_event_survey(struct rsu_softc *, uint8_t *, int); 202static void rsu_event_join_bss(struct rsu_softc *, uint8_t *, int); 203static void rsu_rx_event(struct rsu_softc *, uint8_t, uint8_t *, int); 204static void rsu_rx_multi_event(struct rsu_softc *, uint8_t *, int); 205static int8_t rsu_get_rssi(struct rsu_softc *, int, void *); 206static struct mbuf * 207 rsu_rx_frame(struct rsu_softc *, uint8_t *, int, int *); 208static struct mbuf * 209 rsu_rx_multi_frame(struct rsu_softc *, uint8_t *, int, int *); 210static struct mbuf * 211 rsu_rxeof(struct usb_xfer *, struct rsu_data *, int *); 212static void rsu_txeof(struct usb_xfer *, struct rsu_data *); 213static int rsu_raw_xmit(struct ieee80211_node *, struct mbuf *, 214 const struct ieee80211_bpf_params *); 215static void rsu_init(struct rsu_softc *); 216static int rsu_tx_start(struct rsu_softc *, struct ieee80211_node *, 217 struct mbuf *, struct rsu_data *); 218static int rsu_transmit(struct ieee80211com *, struct mbuf *); 219static void rsu_start(struct rsu_softc *); 220static void rsu_parent(struct ieee80211com *); 221static void rsu_stop(struct rsu_softc *); 222static void rsu_ms_delay(struct rsu_softc *, int); 223 224static device_method_t rsu_methods[] = { 225 DEVMETHOD(device_probe, rsu_match), 226 DEVMETHOD(device_attach, rsu_attach), 227 DEVMETHOD(device_detach, rsu_detach), 228 229 DEVMETHOD_END 230}; 231 232static driver_t rsu_driver = { 233 .name = "rsu", 234 .methods = rsu_methods, 235 .size = sizeof(struct rsu_softc) 236}; 237 238static devclass_t rsu_devclass; 239 240DRIVER_MODULE(rsu, uhub, rsu_driver, rsu_devclass, NULL, 0); 241MODULE_DEPEND(rsu, wlan, 1, 1, 1); 242MODULE_DEPEND(rsu, usb, 1, 1, 1); 243MODULE_DEPEND(rsu, firmware, 1, 1, 1); 244MODULE_VERSION(rsu, 1); 245 246static uint8_t rsu_wme_ac_xfer_map[4] = { 247 [WME_AC_BE] = RSU_BULK_TX_BE_BK, 248 [WME_AC_BK] = RSU_BULK_TX_BE_BK, 249 [WME_AC_VI] = RSU_BULK_TX_VI_VO, 250 [WME_AC_VO] = RSU_BULK_TX_VI_VO, 251}; 252 253/* XXX hard-coded */ 254#define RSU_H2C_ENDPOINT 3 255 256static const struct usb_config rsu_config[RSU_N_TRANSFER] = { 257 [RSU_BULK_RX] = { 258 .type = UE_BULK, 259 .endpoint = UE_ADDR_ANY, 260 .direction = UE_DIR_IN, 261 .bufsize = RSU_RXBUFSZ, 262 .flags = { 263 .pipe_bof = 1, 264 .short_xfer_ok = 1 265 }, 266 .callback = rsu_bulk_rx_callback 267 }, 268 [RSU_BULK_TX_BE_BK] = { 269 .type = UE_BULK, 270 .endpoint = 0x06, 271 .direction = UE_DIR_OUT, 272 .bufsize = RSU_TXBUFSZ, 273 .flags = { 274 .ext_buffer = 1, 275 .pipe_bof = 1, 276 .force_short_xfer = 1 277 }, 278 .callback = rsu_bulk_tx_callback_be_bk, 279 .timeout = RSU_TX_TIMEOUT 280 }, 281 [RSU_BULK_TX_VI_VO] = { 282 .type = UE_BULK, 283 .endpoint = 0x04, 284 .direction = UE_DIR_OUT, 285 .bufsize = RSU_TXBUFSZ, 286 .flags = { 287 .ext_buffer = 1, 288 .pipe_bof = 1, 289 .force_short_xfer = 1 290 }, 291 .callback = rsu_bulk_tx_callback_vi_vo, 292 .timeout = RSU_TX_TIMEOUT 293 }, 294 [RSU_BULK_TX_H2C] = { 295 .type = UE_BULK, 296 .endpoint = 0x0d, 297 .direction = UE_DIR_OUT, 298 .bufsize = RSU_TXBUFSZ, 299 .flags = { 300 .ext_buffer = 1, 301 .pipe_bof = 1, 302 .short_xfer_ok = 1 303 }, 304 .callback = rsu_bulk_tx_callback_h2c, 305 .timeout = RSU_TX_TIMEOUT 306 }, 307}; 308 309static int 310rsu_match(device_t self) 311{ 312 struct usb_attach_arg *uaa = device_get_ivars(self); 313 314 if (uaa->usb_mode != USB_MODE_HOST || 315 uaa->info.bIfaceIndex != 0 || 316 uaa->info.bConfigIndex != 0) 317 return (ENXIO); 318 319 return (usbd_lookup_id_by_uaa(rsu_devs, sizeof(rsu_devs), uaa)); 320} 321 322static int 323rsu_send_mgmt(struct ieee80211_node *ni, int type, int arg) 324{ 325 326 return (ENOTSUP); 327} 328 329static void 330rsu_update_chw(struct ieee80211com *ic) 331{ 332 333} 334 335static int 336rsu_ampdu_enable(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 337{ 338 339 /* Firmware handles this; not our problem */ 340 return (0); 341} 342 343static int 344rsu_wme_update(struct ieee80211com *ic) 345{ 346 347 /* Firmware handles this; not our problem */ 348 return (0); 349} 350 351static int 352rsu_attach(device_t self) 353{ 354 struct usb_attach_arg *uaa = device_get_ivars(self); 355 struct rsu_softc *sc = device_get_softc(self); 356 struct ieee80211com *ic = &sc->sc_ic; 357 int error; 358 uint8_t iface_index, bands; 359 struct usb_interface *iface; 360 361 device_set_usb_desc(self); 362 sc->sc_udev = uaa->device; 363 sc->sc_dev = self; 364 if (rsu_enable_11n) 365 sc->sc_ht = !! (USB_GET_DRIVER_INFO(uaa) & RSU_HT_SUPPORTED); 366 367 /* Get number of endpoints */ 368 iface = usbd_get_iface(sc->sc_udev, 0); 369 sc->sc_nendpoints = iface->idesc->bNumEndpoints; 370 371 /* Endpoints are hard-coded for now, so enforce 4-endpoint only */ 372 if (sc->sc_nendpoints != 4) { 373 device_printf(sc->sc_dev, 374 "the driver currently only supports 4-endpoint devices\n"); 375 return (ENXIO); 376 } 377 378 mtx_init(&sc->sc_mtx, device_get_nameunit(self), MTX_NETWORK_LOCK, 379 MTX_DEF); 380 TIMEOUT_TASK_INIT(taskqueue_thread, &sc->calib_task, 0, 381 rsu_calib_task, sc); 382 mbufq_init(&sc->sc_snd, ifqmaxlen); 383 384 /* Allocate Tx/Rx buffers. */ 385 error = rsu_alloc_rx_list(sc); 386 if (error != 0) { 387 device_printf(sc->sc_dev, "could not allocate Rx buffers\n"); 388 goto fail_usb; 389 } 390 391 error = rsu_alloc_tx_list(sc); 392 if (error != 0) { 393 device_printf(sc->sc_dev, "could not allocate Tx buffers\n"); 394 rsu_free_rx_list(sc); 395 goto fail_usb; 396 } 397 398 iface_index = 0; 399 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 400 rsu_config, RSU_N_TRANSFER, sc, &sc->sc_mtx); 401 if (error) { 402 device_printf(sc->sc_dev, 403 "could not allocate USB transfers, err=%s\n", 404 usbd_errstr(error)); 405 goto fail_usb; 406 } 407 RSU_LOCK(sc); 408 /* Read chip revision. */ 409 sc->cut = MS(rsu_read_4(sc, R92S_PMC_FSM), R92S_PMC_FSM_CUT); 410 if (sc->cut != 3) 411 sc->cut = (sc->cut >> 1) + 1; 412 error = rsu_read_rom(sc); 413 RSU_UNLOCK(sc); 414 if (error != 0) { 415 device_printf(self, "could not read ROM\n"); 416 goto fail_rom; 417 } 418 IEEE80211_ADDR_COPY(ic->ic_macaddr, &sc->rom[0x12]); 419 device_printf(self, "MAC/BB RTL8712 cut %d\n", sc->cut); 420 421 ic->ic_softc = sc; 422 ic->ic_name = device_get_nameunit(self); 423 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 424 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 425 426 /* Set device capabilities. */ 427 ic->ic_caps = 428 IEEE80211_C_STA | /* station mode */ 429#if 0 430 IEEE80211_C_BGSCAN | /* Background scan. */ 431#endif 432 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 433 IEEE80211_C_WME | /* WME/QoS */ 434 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 435 IEEE80211_C_WPA; /* WPA/RSN. */ 436 437 /* Check if HT support is present. */ 438 if (sc->sc_ht) { 439 device_printf(sc->sc_dev, "%s: enabling 11n\n", __func__); 440 441 /* Enable basic HT */ 442 ic->ic_htcaps = IEEE80211_HTC_HT | 443 IEEE80211_HTC_AMPDU | 444 IEEE80211_HTC_AMSDU | 445 IEEE80211_HTCAP_MAXAMSDU_3839 | 446 IEEE80211_HTCAP_SMPS_OFF; 447 448 ic->ic_htcaps |= IEEE80211_HTCAP_CHWIDTH40; 449 450 /* set number of spatial streams */ 451 ic->ic_txstream = 1; 452 ic->ic_rxstream = 1; 453 } 454 455 /* Set supported .11b and .11g rates. */ 456 bands = 0; 457 setbit(&bands, IEEE80211_MODE_11B); 458 setbit(&bands, IEEE80211_MODE_11G); 459 if (sc->sc_ht) 460 setbit(&bands, IEEE80211_MODE_11NG); 461 ieee80211_init_channels(ic, NULL, &bands); 462 463 ieee80211_ifattach(ic); 464 ic->ic_raw_xmit = rsu_raw_xmit; 465 ic->ic_scan_start = rsu_scan_start; 466 ic->ic_scan_end = rsu_scan_end; 467 ic->ic_set_channel = rsu_set_channel; 468 ic->ic_vap_create = rsu_vap_create; 469 ic->ic_vap_delete = rsu_vap_delete; 470 ic->ic_update_mcast = rsu_update_mcast; 471 ic->ic_parent = rsu_parent; 472 ic->ic_transmit = rsu_transmit; 473 ic->ic_send_mgmt = rsu_send_mgmt; 474 ic->ic_update_chw = rsu_update_chw; 475 ic->ic_ampdu_enable = rsu_ampdu_enable; 476 ic->ic_wme.wme_update = rsu_wme_update; 477 478 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 479 sizeof(sc->sc_txtap), RSU_TX_RADIOTAP_PRESENT, 480 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 481 RSU_RX_RADIOTAP_PRESENT); 482 483 if (bootverbose) 484 ieee80211_announce(ic); 485 486 return (0); 487 488fail_rom: 489 usbd_transfer_unsetup(sc->sc_xfer, RSU_N_TRANSFER); 490fail_usb: 491 mtx_destroy(&sc->sc_mtx); 492 return (ENXIO); 493} 494 495static int 496rsu_detach(device_t self) 497{ 498 struct rsu_softc *sc = device_get_softc(self); 499 struct ieee80211com *ic = &sc->sc_ic; 500 501 RSU_LOCK(sc); 502 rsu_stop(sc); 503 RSU_UNLOCK(sc); 504 usbd_transfer_unsetup(sc->sc_xfer, RSU_N_TRANSFER); 505 ieee80211_ifdetach(ic); 506 507 taskqueue_drain_timeout(taskqueue_thread, &sc->calib_task); 508 509 /* Free Tx/Rx buffers. */ 510 rsu_free_tx_list(sc); 511 rsu_free_rx_list(sc); 512 513 mbufq_drain(&sc->sc_snd); 514 mtx_destroy(&sc->sc_mtx); 515 516 return (0); 517} 518 519static usb_error_t 520rsu_do_request(struct rsu_softc *sc, struct usb_device_request *req, 521 void *data) 522{ 523 usb_error_t err; 524 int ntries = 10; 525 526 RSU_ASSERT_LOCKED(sc); 527 528 while (ntries--) { 529 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 530 req, data, 0, NULL, 250 /* ms */); 531 if (err == 0 || err == USB_ERR_NOT_CONFIGURED) 532 break; 533 DPRINTFN(1, "Control request failed, %s (retrying)\n", 534 usbd_errstr(err)); 535 rsu_ms_delay(sc, 10); 536 } 537 538 return (err); 539} 540 541static struct ieee80211vap * 542rsu_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 543 enum ieee80211_opmode opmode, int flags, 544 const uint8_t bssid[IEEE80211_ADDR_LEN], 545 const uint8_t mac[IEEE80211_ADDR_LEN]) 546{ 547 struct rsu_vap *uvp; 548 struct ieee80211vap *vap; 549 550 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 551 return (NULL); 552 553 uvp = malloc(sizeof(struct rsu_vap), M_80211_VAP, M_WAITOK | M_ZERO); 554 vap = &uvp->vap; 555 556 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 557 flags, bssid) != 0) { 558 /* out of memory */ 559 free(uvp, M_80211_VAP); 560 return (NULL); 561 } 562 563 /* override state transition machine */ 564 uvp->newstate = vap->iv_newstate; 565 vap->iv_newstate = rsu_newstate; 566 567 /* Limits from the r92su driver */ 568 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_16; 569 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_32K; 570 571 /* complete setup */ 572 ieee80211_vap_attach(vap, ieee80211_media_change, 573 ieee80211_media_status, mac); 574 ic->ic_opmode = opmode; 575 576 return (vap); 577} 578 579static void 580rsu_vap_delete(struct ieee80211vap *vap) 581{ 582 struct rsu_vap *uvp = RSU_VAP(vap); 583 584 ieee80211_vap_detach(vap); 585 free(uvp, M_80211_VAP); 586} 587 588static void 589rsu_scan_start(struct ieee80211com *ic) 590{ 591 struct rsu_softc *sc = ic->ic_softc; 592 int error; 593 594 /* Scanning is done by the firmware. */ 595 RSU_LOCK(sc); 596 error = rsu_site_survey(sc, TAILQ_FIRST(&ic->ic_vaps)); 597 RSU_UNLOCK(sc); 598 if (error != 0) 599 device_printf(sc->sc_dev, 600 "could not send site survey command\n"); 601} 602 603static void 604rsu_scan_end(struct ieee80211com *ic) 605{ 606 /* Nothing to do here. */ 607} 608 609static void 610rsu_set_channel(struct ieee80211com *ic __unused) 611{ 612 /* We are unable to switch channels, yet. */ 613} 614 615static void 616rsu_update_mcast(struct ieee80211com *ic) 617{ 618 /* XXX do nothing? */ 619} 620 621static int 622rsu_alloc_list(struct rsu_softc *sc, struct rsu_data data[], 623 int ndata, int maxsz) 624{ 625 int i, error; 626 627 for (i = 0; i < ndata; i++) { 628 struct rsu_data *dp = &data[i]; 629 dp->sc = sc; 630 dp->m = NULL; 631 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 632 if (dp->buf == NULL) { 633 device_printf(sc->sc_dev, 634 "could not allocate buffer\n"); 635 error = ENOMEM; 636 goto fail; 637 } 638 dp->ni = NULL; 639 } 640 641 return (0); 642fail: 643 rsu_free_list(sc, data, ndata); 644 return (error); 645} 646 647static int 648rsu_alloc_rx_list(struct rsu_softc *sc) 649{ 650 int error, i; 651 652 error = rsu_alloc_list(sc, sc->sc_rx, RSU_RX_LIST_COUNT, 653 RSU_RXBUFSZ); 654 if (error != 0) 655 return (error); 656 657 STAILQ_INIT(&sc->sc_rx_active); 658 STAILQ_INIT(&sc->sc_rx_inactive); 659 660 for (i = 0; i < RSU_RX_LIST_COUNT; i++) 661 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 662 663 return (0); 664} 665 666static int 667rsu_alloc_tx_list(struct rsu_softc *sc) 668{ 669 int error, i; 670 671 error = rsu_alloc_list(sc, sc->sc_tx, RSU_TX_LIST_COUNT, 672 RSU_TXBUFSZ); 673 if (error != 0) 674 return (error); 675 676 STAILQ_INIT(&sc->sc_tx_inactive); 677 678 for (i = 0; i != RSU_N_TRANSFER; i++) { 679 STAILQ_INIT(&sc->sc_tx_active[i]); 680 STAILQ_INIT(&sc->sc_tx_pending[i]); 681 } 682 683 for (i = 0; i < RSU_TX_LIST_COUNT; i++) { 684 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 685 } 686 687 return (0); 688} 689 690static void 691rsu_free_tx_list(struct rsu_softc *sc) 692{ 693 int i; 694 695 /* prevent further allocations from TX list(s) */ 696 STAILQ_INIT(&sc->sc_tx_inactive); 697 698 for (i = 0; i != RSU_N_TRANSFER; i++) { 699 STAILQ_INIT(&sc->sc_tx_active[i]); 700 STAILQ_INIT(&sc->sc_tx_pending[i]); 701 } 702 703 rsu_free_list(sc, sc->sc_tx, RSU_TX_LIST_COUNT); 704} 705 706static void 707rsu_free_rx_list(struct rsu_softc *sc) 708{ 709 /* prevent further allocations from RX list(s) */ 710 STAILQ_INIT(&sc->sc_rx_inactive); 711 STAILQ_INIT(&sc->sc_rx_active); 712 713 rsu_free_list(sc, sc->sc_rx, RSU_RX_LIST_COUNT); 714} 715 716static void 717rsu_free_list(struct rsu_softc *sc, struct rsu_data data[], int ndata) 718{ 719 int i; 720 721 for (i = 0; i < ndata; i++) { 722 struct rsu_data *dp = &data[i]; 723 724 if (dp->buf != NULL) { 725 free(dp->buf, M_USBDEV); 726 dp->buf = NULL; 727 } 728 if (dp->ni != NULL) { 729 ieee80211_free_node(dp->ni); 730 dp->ni = NULL; 731 } 732 } 733} 734 735static struct rsu_data * 736_rsu_getbuf(struct rsu_softc *sc) 737{ 738 struct rsu_data *bf; 739 740 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 741 if (bf != NULL) 742 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 743 else 744 bf = NULL; 745 if (bf == NULL) 746 DPRINTF("out of xmit buffers\n"); 747 return (bf); 748} 749 750static struct rsu_data * 751rsu_getbuf(struct rsu_softc *sc) 752{ 753 struct rsu_data *bf; 754 755 RSU_ASSERT_LOCKED(sc); 756 757 bf = _rsu_getbuf(sc); 758 if (bf == NULL) 759 DPRINTF("stop queue\n"); 760 return (bf); 761} 762 763static void 764rsu_freebuf(struct rsu_softc *sc, struct rsu_data *bf) 765{ 766 767 RSU_ASSERT_LOCKED(sc); 768 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, bf, next); 769} 770 771static int 772rsu_write_region_1(struct rsu_softc *sc, uint16_t addr, uint8_t *buf, 773 int len) 774{ 775 usb_device_request_t req; 776 777 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 778 req.bRequest = R92S_REQ_REGS; 779 USETW(req.wValue, addr); 780 USETW(req.wIndex, 0); 781 USETW(req.wLength, len); 782 783 return (rsu_do_request(sc, &req, buf)); 784} 785 786static void 787rsu_write_1(struct rsu_softc *sc, uint16_t addr, uint8_t val) 788{ 789 rsu_write_region_1(sc, addr, &val, 1); 790} 791 792static void 793rsu_write_2(struct rsu_softc *sc, uint16_t addr, uint16_t val) 794{ 795 val = htole16(val); 796 rsu_write_region_1(sc, addr, (uint8_t *)&val, 2); 797} 798 799static void 800rsu_write_4(struct rsu_softc *sc, uint16_t addr, uint32_t val) 801{ 802 val = htole32(val); 803 rsu_write_region_1(sc, addr, (uint8_t *)&val, 4); 804} 805 806static int 807rsu_read_region_1(struct rsu_softc *sc, uint16_t addr, uint8_t *buf, 808 int len) 809{ 810 usb_device_request_t req; 811 812 req.bmRequestType = UT_READ_VENDOR_DEVICE; 813 req.bRequest = R92S_REQ_REGS; 814 USETW(req.wValue, addr); 815 USETW(req.wIndex, 0); 816 USETW(req.wLength, len); 817 818 return (rsu_do_request(sc, &req, buf)); 819} 820 821static uint8_t 822rsu_read_1(struct rsu_softc *sc, uint16_t addr) 823{ 824 uint8_t val; 825 826 if (rsu_read_region_1(sc, addr, &val, 1) != 0) 827 return (0xff); 828 return (val); 829} 830 831static uint16_t 832rsu_read_2(struct rsu_softc *sc, uint16_t addr) 833{ 834 uint16_t val; 835 836 if (rsu_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 837 return (0xffff); 838 return (le16toh(val)); 839} 840 841static uint32_t 842rsu_read_4(struct rsu_softc *sc, uint16_t addr) 843{ 844 uint32_t val; 845 846 if (rsu_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 847 return (0xffffffff); 848 return (le32toh(val)); 849} 850 851static int 852rsu_fw_iocmd(struct rsu_softc *sc, uint32_t iocmd) 853{ 854 int ntries; 855 856 rsu_write_4(sc, R92S_IOCMD_CTRL, iocmd); 857 rsu_ms_delay(sc, 1); 858 for (ntries = 0; ntries < 50; ntries++) { 859 if (rsu_read_4(sc, R92S_IOCMD_CTRL) == 0) 860 return (0); 861 rsu_ms_delay(sc, 1); 862 } 863 return (ETIMEDOUT); 864} 865 866static uint8_t 867rsu_efuse_read_1(struct rsu_softc *sc, uint16_t addr) 868{ 869 uint32_t reg; 870 int ntries; 871 872 reg = rsu_read_4(sc, R92S_EFUSE_CTRL); 873 reg = RW(reg, R92S_EFUSE_CTRL_ADDR, addr); 874 reg &= ~R92S_EFUSE_CTRL_VALID; 875 rsu_write_4(sc, R92S_EFUSE_CTRL, reg); 876 /* Wait for read operation to complete. */ 877 for (ntries = 0; ntries < 100; ntries++) { 878 reg = rsu_read_4(sc, R92S_EFUSE_CTRL); 879 if (reg & R92S_EFUSE_CTRL_VALID) 880 return (MS(reg, R92S_EFUSE_CTRL_DATA)); 881 rsu_ms_delay(sc, 1); 882 } 883 device_printf(sc->sc_dev, 884 "could not read efuse byte at address 0x%x\n", addr); 885 return (0xff); 886} 887 888static int 889rsu_read_rom(struct rsu_softc *sc) 890{ 891 uint8_t *rom = sc->rom; 892 uint16_t addr = 0; 893 uint32_t reg; 894 uint8_t off, msk; 895 int i; 896 897 /* Make sure that ROM type is eFuse and that autoload succeeded. */ 898 reg = rsu_read_1(sc, R92S_EE_9346CR); 899 if ((reg & (R92S_9356SEL | R92S_EEPROM_EN)) != R92S_EEPROM_EN) 900 return (EIO); 901 902 /* Turn on 2.5V to prevent eFuse leakage. */ 903 reg = rsu_read_1(sc, R92S_EFUSE_TEST + 3); 904 rsu_write_1(sc, R92S_EFUSE_TEST + 3, reg | 0x80); 905 rsu_ms_delay(sc, 1); 906 rsu_write_1(sc, R92S_EFUSE_TEST + 3, reg & ~0x80); 907 908 /* Read full ROM image. */ 909 memset(&sc->rom, 0xff, sizeof(sc->rom)); 910 while (addr < 512) { 911 reg = rsu_efuse_read_1(sc, addr); 912 if (reg == 0xff) 913 break; 914 addr++; 915 off = reg >> 4; 916 msk = reg & 0xf; 917 for (i = 0; i < 4; i++) { 918 if (msk & (1 << i)) 919 continue; 920 rom[off * 8 + i * 2 + 0] = 921 rsu_efuse_read_1(sc, addr); 922 addr++; 923 rom[off * 8 + i * 2 + 1] = 924 rsu_efuse_read_1(sc, addr); 925 addr++; 926 } 927 } 928#ifdef USB_DEBUG 929 if (rsu_debug >= 5) { 930 /* Dump ROM content. */ 931 printf("\n"); 932 for (i = 0; i < sizeof(sc->rom); i++) 933 printf("%02x:", rom[i]); 934 printf("\n"); 935 } 936#endif 937 return (0); 938} 939 940static int 941rsu_fw_cmd(struct rsu_softc *sc, uint8_t code, void *buf, int len) 942{ 943 const uint8_t which = RSU_H2C_ENDPOINT; 944 struct rsu_data *data; 945 struct r92s_tx_desc *txd; 946 struct r92s_fw_cmd_hdr *cmd; 947 int cmdsz; 948 int xferlen; 949 950 data = rsu_getbuf(sc); 951 if (data == NULL) 952 return (ENOMEM); 953 954 /* Round-up command length to a multiple of 8 bytes. */ 955 cmdsz = (len + 7) & ~7; 956 957 xferlen = sizeof(*txd) + sizeof(*cmd) + cmdsz; 958 KASSERT(xferlen <= RSU_TXBUFSZ, ("%s: invalid length", __func__)); 959 memset(data->buf, 0, xferlen); 960 961 /* Setup Tx descriptor. */ 962 txd = (struct r92s_tx_desc *)data->buf; 963 txd->txdw0 = htole32( 964 SM(R92S_TXDW0_OFFSET, sizeof(*txd)) | 965 SM(R92S_TXDW0_PKTLEN, sizeof(*cmd) + cmdsz) | 966 R92S_TXDW0_OWN | R92S_TXDW0_FSG | R92S_TXDW0_LSG); 967 txd->txdw1 = htole32(SM(R92S_TXDW1_QSEL, R92S_TXDW1_QSEL_H2C)); 968 969 /* Setup command header. */ 970 cmd = (struct r92s_fw_cmd_hdr *)&txd[1]; 971 cmd->len = htole16(cmdsz); 972 cmd->code = code; 973 cmd->seq = sc->cmd_seq; 974 sc->cmd_seq = (sc->cmd_seq + 1) & 0x7f; 975 976 /* Copy command payload. */ 977 memcpy(&cmd[1], buf, len); 978 979 RSU_DPRINTF(sc, RSU_DEBUG_TX | RSU_DEBUG_FWCMD, 980 "%s: Tx cmd code=0x%x len=0x%x\n", 981 __func__, code, cmdsz); 982 data->buflen = xferlen; 983 STAILQ_INSERT_TAIL(&sc->sc_tx_pending[which], data, next); 984 usbd_transfer_start(sc->sc_xfer[which]); 985 986 return (0); 987} 988 989/* ARGSUSED */ 990static void 991rsu_calib_task(void *arg, int pending __unused) 992{ 993 struct rsu_softc *sc = arg; 994 uint32_t reg; 995 996 RSU_DPRINTF(sc, RSU_DEBUG_CALIB, "%s: running calibration task\n", 997 __func__); 998 999 RSU_LOCK(sc); 1000#ifdef notyet 1001 /* Read WPS PBC status. */ 1002 rsu_write_1(sc, R92S_MAC_PINMUX_CTRL, 1003 R92S_GPIOMUX_EN | SM(R92S_GPIOSEL_GPIO, R92S_GPIOSEL_GPIO_JTAG)); 1004 rsu_write_1(sc, R92S_GPIO_IO_SEL, 1005 rsu_read_1(sc, R92S_GPIO_IO_SEL) & ~R92S_GPIO_WPS); 1006 reg = rsu_read_1(sc, R92S_GPIO_CTRL); 1007 if (reg != 0xff && (reg & R92S_GPIO_WPS)) 1008 DPRINTF(("WPS PBC is pushed\n")); 1009#endif 1010 /* Read current signal level. */ 1011 if (rsu_fw_iocmd(sc, 0xf4000001) == 0) { 1012 reg = rsu_read_4(sc, R92S_IOCMD_DATA); 1013 RSU_DPRINTF(sc, RSU_DEBUG_CALIB, "%s: RSSI=%d%%\n", 1014 __func__, reg >> 4); 1015 } 1016 if (sc->sc_calibrating) 1017 taskqueue_enqueue_timeout(taskqueue_thread, &sc->calib_task, hz); 1018 RSU_UNLOCK(sc); 1019} 1020 1021static int 1022rsu_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1023{ 1024 struct rsu_vap *uvp = RSU_VAP(vap); 1025 struct ieee80211com *ic = vap->iv_ic; 1026 struct rsu_softc *sc = ic->ic_softc; 1027 struct ieee80211_node *ni; 1028 struct ieee80211_rateset *rs; 1029 enum ieee80211_state ostate; 1030 int error, startcal = 0; 1031 1032 ostate = vap->iv_state; 1033 RSU_DPRINTF(sc, RSU_DEBUG_STATE, "%s: %s -> %s\n", 1034 __func__, 1035 ieee80211_state_name[ostate], 1036 ieee80211_state_name[nstate]); 1037 1038 IEEE80211_UNLOCK(ic); 1039 if (ostate == IEEE80211_S_RUN) { 1040 RSU_LOCK(sc); 1041 /* Stop calibration. */ 1042 sc->sc_calibrating = 0; 1043 RSU_UNLOCK(sc); 1044 taskqueue_drain_timeout(taskqueue_thread, &sc->calib_task); 1045 /* Disassociate from our current BSS. */ 1046 RSU_LOCK(sc); 1047 rsu_disconnect(sc); 1048 } else 1049 RSU_LOCK(sc); 1050 switch (nstate) { 1051 case IEEE80211_S_INIT: 1052 break; 1053 case IEEE80211_S_AUTH: 1054 ni = ieee80211_ref_node(vap->iv_bss); 1055 error = rsu_join_bss(sc, ni); 1056 ieee80211_free_node(ni); 1057 if (error != 0) { 1058 device_printf(sc->sc_dev, 1059 "could not send join command\n"); 1060 } 1061 break; 1062 case IEEE80211_S_RUN: 1063 ni = ieee80211_ref_node(vap->iv_bss); 1064 rs = &ni->ni_rates; 1065 /* Indicate highest supported rate. */ 1066 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1067 ieee80211_free_node(ni); 1068 startcal = 1; 1069 break; 1070 default: 1071 break; 1072 } 1073 sc->sc_calibrating = 1; 1074 /* Start periodic calibration. */ 1075 taskqueue_enqueue_timeout(taskqueue_thread, &sc->calib_task, hz); 1076 RSU_UNLOCK(sc); 1077 IEEE80211_LOCK(ic); 1078 return (uvp->newstate(vap, nstate, arg)); 1079} 1080 1081#ifdef notyet 1082static void 1083rsu_set_key(struct rsu_softc *sc, const struct ieee80211_key *k) 1084{ 1085 struct r92s_fw_cmd_set_key key; 1086 1087 memset(&key, 0, sizeof(key)); 1088 /* Map net80211 cipher to HW crypto algorithm. */ 1089 switch (k->wk_cipher->ic_cipher) { 1090 case IEEE80211_CIPHER_WEP: 1091 if (k->wk_keylen < 8) 1092 key.algo = R92S_KEY_ALGO_WEP40; 1093 else 1094 key.algo = R92S_KEY_ALGO_WEP104; 1095 break; 1096 case IEEE80211_CIPHER_TKIP: 1097 key.algo = R92S_KEY_ALGO_TKIP; 1098 break; 1099 case IEEE80211_CIPHER_AES_CCM: 1100 key.algo = R92S_KEY_ALGO_AES; 1101 break; 1102 default: 1103 return; 1104 } 1105 key.id = k->wk_keyix; 1106 key.grpkey = (k->wk_flags & IEEE80211_KEY_GROUP) != 0; 1107 memcpy(key.key, k->wk_key, MIN(k->wk_keylen, sizeof(key.key))); 1108 (void)rsu_fw_cmd(sc, R92S_CMD_SET_KEY, &key, sizeof(key)); 1109} 1110 1111static void 1112rsu_delete_key(struct rsu_softc *sc, const struct ieee80211_key *k) 1113{ 1114 struct r92s_fw_cmd_set_key key; 1115 1116 memset(&key, 0, sizeof(key)); 1117 key.id = k->wk_keyix; 1118 (void)rsu_fw_cmd(sc, R92S_CMD_SET_KEY, &key, sizeof(key)); 1119} 1120#endif 1121 1122static int 1123rsu_site_survey(struct rsu_softc *sc, struct ieee80211vap *vap) 1124{ 1125 struct r92s_fw_cmd_sitesurvey cmd; 1126 struct ieee80211com *ic = &sc->sc_ic; 1127 1128 memset(&cmd, 0, sizeof(cmd)); 1129 if ((ic->ic_flags & IEEE80211_F_ASCAN) || sc->sc_scan_pass == 1) 1130 cmd.active = htole32(1); 1131 cmd.limit = htole32(48); 1132 if (sc->sc_scan_pass == 1 && vap->iv_des_nssid > 0) { 1133 /* Do a directed scan for second pass. */ 1134 cmd.ssidlen = htole32(vap->iv_des_ssid[0].len); 1135 memcpy(cmd.ssid, vap->iv_des_ssid[0].ssid, 1136 vap->iv_des_ssid[0].len); 1137 1138 } 1139 DPRINTF("sending site survey command, pass=%d\n", sc->sc_scan_pass); 1140 return (rsu_fw_cmd(sc, R92S_CMD_SITE_SURVEY, &cmd, sizeof(cmd))); 1141} 1142 1143static int 1144rsu_join_bss(struct rsu_softc *sc, struct ieee80211_node *ni) 1145{ 1146 struct ieee80211com *ic = &sc->sc_ic; 1147 struct ieee80211vap *vap = ni->ni_vap; 1148 struct ndis_wlan_bssid_ex *bss; 1149 struct ndis_802_11_fixed_ies *fixed; 1150 struct r92s_fw_cmd_auth auth; 1151 uint8_t buf[sizeof(*bss) + 128] __aligned(4); 1152 uint8_t *frm; 1153 uint8_t opmode; 1154 int error; 1155 1156 /* Let the FW decide the opmode based on the capinfo field. */ 1157 opmode = NDIS802_11AUTOUNKNOWN; 1158 RSU_DPRINTF(sc, RSU_DEBUG_RESET, 1159 "%s: setting operating mode to %d\n", 1160 __func__, opmode); 1161 error = rsu_fw_cmd(sc, R92S_CMD_SET_OPMODE, &opmode, sizeof(opmode)); 1162 if (error != 0) 1163 return (error); 1164 1165 memset(&auth, 0, sizeof(auth)); 1166 if (vap->iv_flags & IEEE80211_F_WPA) { 1167 auth.mode = R92S_AUTHMODE_WPA; 1168 auth.dot1x = (ni->ni_authmode == IEEE80211_AUTH_8021X); 1169 } else 1170 auth.mode = R92S_AUTHMODE_OPEN; 1171 RSU_DPRINTF(sc, RSU_DEBUG_RESET, 1172 "%s: setting auth mode to %d\n", 1173 __func__, auth.mode); 1174 error = rsu_fw_cmd(sc, R92S_CMD_SET_AUTH, &auth, sizeof(auth)); 1175 if (error != 0) 1176 return (error); 1177 1178 memset(buf, 0, sizeof(buf)); 1179 bss = (struct ndis_wlan_bssid_ex *)buf; 1180 IEEE80211_ADDR_COPY(bss->macaddr, ni->ni_bssid); 1181 bss->ssid.ssidlen = htole32(ni->ni_esslen); 1182 memcpy(bss->ssid.ssid, ni->ni_essid, ni->ni_esslen); 1183 if (vap->iv_flags & (IEEE80211_F_PRIVACY | IEEE80211_F_WPA)) 1184 bss->privacy = htole32(1); 1185 bss->rssi = htole32(ni->ni_avgrssi); 1186 if (ic->ic_curmode == IEEE80211_MODE_11B) 1187 bss->networktype = htole32(NDIS802_11DS); 1188 else 1189 bss->networktype = htole32(NDIS802_11OFDM24); 1190 bss->config.len = htole32(sizeof(bss->config)); 1191 bss->config.bintval = htole32(ni->ni_intval); 1192 bss->config.dsconfig = htole32(ieee80211_chan2ieee(ic, ni->ni_chan)); 1193 bss->inframode = htole32(NDIS802_11INFRASTRUCTURE); 1194 /* XXX verify how this is supposed to look! */ 1195 memcpy(bss->supprates, ni->ni_rates.rs_rates, 1196 ni->ni_rates.rs_nrates); 1197 /* Write the fixed fields of the beacon frame. */ 1198 fixed = (struct ndis_802_11_fixed_ies *)&bss[1]; 1199 memcpy(&fixed->tstamp, ni->ni_tstamp.data, 8); 1200 fixed->bintval = htole16(ni->ni_intval); 1201 fixed->capabilities = htole16(ni->ni_capinfo); 1202 /* Write IEs to be included in the association request. */ 1203 frm = (uint8_t *)&fixed[1]; 1204 frm = ieee80211_add_rsn(frm, vap); 1205 frm = ieee80211_add_wpa(frm, vap); 1206 frm = ieee80211_add_qos(frm, ni); 1207 if ((ic->ic_flags & IEEE80211_F_WME) && 1208 (ni->ni_ies.wme_ie != NULL)) 1209 frm = ieee80211_add_wme_info(frm, &ic->ic_wme); 1210 if (ni->ni_flags & IEEE80211_NODE_HT) 1211 frm = ieee80211_add_htcap(frm, ni); 1212 bss->ieslen = htole32(frm - (uint8_t *)fixed); 1213 bss->len = htole32(((frm - buf) + 3) & ~3); 1214 RSU_DPRINTF(sc, RSU_DEBUG_RESET | RSU_DEBUG_FWCMD, 1215 "%s: sending join bss command to %s chan %d\n", 1216 __func__, 1217 ether_sprintf(bss->macaddr), le32toh(bss->config.dsconfig)); 1218 return (rsu_fw_cmd(sc, R92S_CMD_JOIN_BSS, buf, sizeof(buf))); 1219} 1220 1221static int 1222rsu_disconnect(struct rsu_softc *sc) 1223{ 1224 uint32_t zero = 0; /* :-) */ 1225 1226 /* Disassociate from our current BSS. */ 1227 RSU_DPRINTF(sc, RSU_DEBUG_STATE | RSU_DEBUG_FWCMD, 1228 "%s: sending disconnect command\n", __func__); 1229 return (rsu_fw_cmd(sc, R92S_CMD_DISCONNECT, &zero, sizeof(zero))); 1230} 1231 1232static void 1233rsu_event_survey(struct rsu_softc *sc, uint8_t *buf, int len) 1234{ 1235 struct ieee80211com *ic = &sc->sc_ic; 1236 struct ieee80211_frame *wh; 1237 struct ndis_wlan_bssid_ex *bss; 1238 struct ieee80211_rx_stats rxs; 1239 struct mbuf *m; 1240 int pktlen; 1241 1242 if (__predict_false(len < sizeof(*bss))) 1243 return; 1244 bss = (struct ndis_wlan_bssid_ex *)buf; 1245 if (__predict_false(len < sizeof(*bss) + le32toh(bss->ieslen))) 1246 return; 1247 1248 RSU_DPRINTF(sc, RSU_DEBUG_SCAN, 1249 "%s: found BSS %s: len=%d chan=%d inframode=%d " 1250 "networktype=%d privacy=%d, RSSI=%d\n", 1251 __func__, 1252 ether_sprintf(bss->macaddr), le32toh(bss->len), 1253 le32toh(bss->config.dsconfig), le32toh(bss->inframode), 1254 le32toh(bss->networktype), le32toh(bss->privacy), 1255 le32toh(bss->rssi)); 1256 1257 /* Build a fake beacon frame to let net80211 do all the parsing. */ 1258 /* XXX TODO: just call the new scan API methods! */ 1259 pktlen = sizeof(*wh) + le32toh(bss->ieslen); 1260 if (__predict_false(pktlen > MCLBYTES)) 1261 return; 1262 m = m_get2(pktlen, M_NOWAIT, MT_DATA, M_PKTHDR); 1263 if (__predict_false(m == NULL)) 1264 return; 1265 wh = mtod(m, struct ieee80211_frame *); 1266 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 1267 IEEE80211_FC0_SUBTYPE_BEACON; 1268 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 1269 USETW(wh->i_dur, 0); 1270 IEEE80211_ADDR_COPY(wh->i_addr1, ieee80211broadcastaddr); 1271 IEEE80211_ADDR_COPY(wh->i_addr2, bss->macaddr); 1272 IEEE80211_ADDR_COPY(wh->i_addr3, bss->macaddr); 1273 *(uint16_t *)wh->i_seq = 0; 1274 memcpy(&wh[1], (uint8_t *)&bss[1], le32toh(bss->ieslen)); 1275 1276 /* Finalize mbuf. */ 1277 m->m_pkthdr.len = m->m_len = pktlen; 1278 1279 /* Set channel flags for input path */ 1280 bzero(&rxs, sizeof(rxs)); 1281 rxs.r_flags |= IEEE80211_R_IEEE | IEEE80211_R_FREQ; 1282 rxs.r_flags |= IEEE80211_R_NF | IEEE80211_R_RSSI; 1283 rxs.c_ieee = le32toh(bss->config.dsconfig); 1284 rxs.c_freq = ieee80211_ieee2mhz(rxs.c_ieee, IEEE80211_CHAN_2GHZ); 1285 rxs.rssi = le32toh(bss->rssi); 1286 rxs.nf = 0; /* XXX */ 1287 1288 /* XXX avoid a LOR */ 1289 RSU_UNLOCK(sc); 1290 ieee80211_input_mimo_all(ic, m, &rxs); 1291 RSU_LOCK(sc); 1292} 1293 1294static void 1295rsu_event_join_bss(struct rsu_softc *sc, uint8_t *buf, int len) 1296{ 1297 struct ieee80211com *ic = &sc->sc_ic; 1298 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1299 struct ieee80211_node *ni = vap->iv_bss; 1300 struct r92s_event_join_bss *rsp; 1301 uint32_t tmp; 1302 int res; 1303 1304 if (__predict_false(len < sizeof(*rsp))) 1305 return; 1306 rsp = (struct r92s_event_join_bss *)buf; 1307 res = (int)le32toh(rsp->join_res); 1308 1309 RSU_DPRINTF(sc, RSU_DEBUG_STATE | RSU_DEBUG_FWCMD, 1310 "%s: Rx join BSS event len=%d res=%d\n", 1311 __func__, len, res); 1312 if (res <= 0) { 1313 RSU_UNLOCK(sc); 1314 ieee80211_new_state(vap, IEEE80211_S_SCAN, -1); 1315 RSU_LOCK(sc); 1316 return; 1317 } 1318 tmp = le32toh(rsp->associd); 1319 if (tmp >= vap->iv_max_aid) { 1320 DPRINTF("Assoc ID overflow\n"); 1321 tmp = 1; 1322 } 1323 RSU_DPRINTF(sc, RSU_DEBUG_STATE | RSU_DEBUG_FWCMD, 1324 "%s: associated with %s associd=%d\n", 1325 __func__, ether_sprintf(rsp->bss.macaddr), tmp); 1326 /* XXX is this required? What's the top two bits for again? */ 1327 ni->ni_associd = tmp | 0xc000; 1328 RSU_UNLOCK(sc); 1329 ieee80211_new_state(vap, IEEE80211_S_RUN, 1330 IEEE80211_FC0_SUBTYPE_ASSOC_RESP); 1331 RSU_LOCK(sc); 1332} 1333 1334static void 1335rsu_event_addba_req_report(struct rsu_softc *sc, uint8_t *buf, int len) 1336{ 1337 struct ieee80211com *ic = &sc->sc_ic; 1338 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1339 struct r92s_add_ba_event *ba = (void *) buf; 1340 struct ieee80211_node *ni; 1341 1342 if (len < sizeof(*ba)) { 1343 device_printf(sc->sc_dev, "%s: short read (%d)\n", __func__, len); 1344 return; 1345 } 1346 1347 if (vap == NULL) 1348 return; 1349 1350 device_printf(sc->sc_dev, "%s: mac=%s, tid=%d, ssn=%d\n", 1351 __func__, 1352 ether_sprintf(ba->mac_addr), 1353 (int) ba->tid, 1354 (int) le16toh(ba->ssn)); 1355 1356 /* XXX do node lookup; this is STA specific */ 1357 1358 ni = ieee80211_ref_node(vap->iv_bss); 1359 ieee80211_ampdu_rx_start_ext(ni, ba->tid, le16toh(ba->ssn) >> 4, 32); 1360 ieee80211_free_node(ni); 1361} 1362 1363static void 1364rsu_rx_event(struct rsu_softc *sc, uint8_t code, uint8_t *buf, int len) 1365{ 1366 struct ieee80211com *ic = &sc->sc_ic; 1367 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1368 1369 RSU_DPRINTF(sc, RSU_DEBUG_RX | RSU_DEBUG_FWCMD, 1370 "%s: Rx event code=%d len=%d\n", __func__, code, len); 1371 switch (code) { 1372 case R92S_EVT_SURVEY: 1373 rsu_event_survey(sc, buf, len); 1374 break; 1375 case R92S_EVT_SURVEY_DONE: 1376 RSU_DPRINTF(sc, RSU_DEBUG_SCAN, 1377 "%s: site survey pass %d done, found %d BSS\n", 1378 __func__, sc->sc_scan_pass, le32toh(*(uint32_t *)buf)); 1379 if (vap->iv_state != IEEE80211_S_SCAN) 1380 break; /* Ignore if not scanning. */ 1381 if (sc->sc_scan_pass == 0 && vap->iv_des_nssid != 0) { 1382 /* Schedule a directed scan for hidden APs. */ 1383 /* XXX bad! */ 1384 sc->sc_scan_pass = 1; 1385 RSU_UNLOCK(sc); 1386 ieee80211_new_state(vap, IEEE80211_S_SCAN, -1); 1387 RSU_LOCK(sc); 1388 break; 1389 } 1390 sc->sc_scan_pass = 0; 1391 break; 1392 case R92S_EVT_JOIN_BSS: 1393 if (vap->iv_state == IEEE80211_S_AUTH) 1394 rsu_event_join_bss(sc, buf, len); 1395 break; 1396 case R92S_EVT_DEL_STA: 1397 RSU_DPRINTF(sc, RSU_DEBUG_FWCMD | RSU_DEBUG_STATE, 1398 "%s: disassociated from %s\n", __func__, 1399 ether_sprintf(buf)); 1400 if (vap->iv_state == IEEE80211_S_RUN && 1401 IEEE80211_ADDR_EQ(vap->iv_bss->ni_bssid, buf)) { 1402 RSU_UNLOCK(sc); 1403 ieee80211_new_state(vap, IEEE80211_S_SCAN, -1); 1404 RSU_LOCK(sc); 1405 } 1406 break; 1407 case R92S_EVT_WPS_PBC: 1408 RSU_DPRINTF(sc, RSU_DEBUG_RX | RSU_DEBUG_FWCMD, 1409 "%s: WPS PBC pushed.\n", __func__); 1410 break; 1411 case R92S_EVT_FWDBG: 1412 buf[60] = '\0'; 1413 RSU_DPRINTF(sc, RSU_DEBUG_FWDBG, "FWDBG: %s\n", (char *)buf); 1414 break; 1415 1416 case R92S_EVT_ADDBA_REQ_REPORT: 1417 rsu_event_addba_req_report(sc, buf, len); 1418 break; 1419 default: 1420 RSU_DPRINTF(sc, RSU_DEBUG_ANY, "%s: unhandled code (%d)\n", 1421 __func__, code); 1422 break; 1423 } 1424} 1425 1426static void 1427rsu_rx_multi_event(struct rsu_softc *sc, uint8_t *buf, int len) 1428{ 1429 struct r92s_fw_cmd_hdr *cmd; 1430 int cmdsz; 1431 1432 RSU_DPRINTF(sc, RSU_DEBUG_RX, "%s: Rx events len=%d\n", __func__, len); 1433 1434 /* Skip Rx status. */ 1435 buf += sizeof(struct r92s_rx_stat); 1436 len -= sizeof(struct r92s_rx_stat); 1437 1438 /* Process all events. */ 1439 for (;;) { 1440 /* Check that command header fits. */ 1441 if (__predict_false(len < sizeof(*cmd))) 1442 break; 1443 cmd = (struct r92s_fw_cmd_hdr *)buf; 1444 /* Check that command payload fits. */ 1445 cmdsz = le16toh(cmd->len); 1446 if (__predict_false(len < sizeof(*cmd) + cmdsz)) 1447 break; 1448 1449 /* Process firmware event. */ 1450 rsu_rx_event(sc, cmd->code, (uint8_t *)&cmd[1], cmdsz); 1451 1452 if (!(cmd->seq & R92S_FW_CMD_MORE)) 1453 break; 1454 buf += sizeof(*cmd) + cmdsz; 1455 len -= sizeof(*cmd) + cmdsz; 1456 } 1457} 1458 1459static int8_t 1460rsu_get_rssi(struct rsu_softc *sc, int rate, void *physt) 1461{ 1462 static const int8_t cckoff[] = { 14, -2, -20, -40 }; 1463 struct r92s_rx_phystat *phy; 1464 struct r92s_rx_cck *cck; 1465 uint8_t rpt; 1466 int8_t rssi; 1467 1468 if (rate <= 3) { 1469 cck = (struct r92s_rx_cck *)physt; 1470 rpt = (cck->agc_rpt >> 6) & 0x3; 1471 rssi = cck->agc_rpt & 0x3e; 1472 rssi = cckoff[rpt] - rssi; 1473 } else { /* OFDM/HT. */ 1474 phy = (struct r92s_rx_phystat *)physt; 1475 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 106; 1476 } 1477 return (rssi); 1478} 1479 1480static struct mbuf * 1481rsu_rx_frame(struct rsu_softc *sc, uint8_t *buf, int pktlen, int *rssi) 1482{ 1483 struct ieee80211com *ic = &sc->sc_ic; 1484 struct ieee80211_frame *wh; 1485 struct r92s_rx_stat *stat; 1486 uint32_t rxdw0, rxdw3; 1487 struct mbuf *m; 1488 uint8_t rate; 1489 int infosz; 1490 1491 stat = (struct r92s_rx_stat *)buf; 1492 rxdw0 = le32toh(stat->rxdw0); 1493 rxdw3 = le32toh(stat->rxdw3); 1494 1495 if (__predict_false(rxdw0 & R92S_RXDW0_CRCERR)) { 1496 counter_u64_add(ic->ic_ierrors, 1); 1497 return NULL; 1498 } 1499 if (__predict_false(pktlen < sizeof(*wh) || pktlen > MCLBYTES)) { 1500 counter_u64_add(ic->ic_ierrors, 1); 1501 return NULL; 1502 } 1503 1504 rate = MS(rxdw3, R92S_RXDW3_RATE); 1505 infosz = MS(rxdw0, R92S_RXDW0_INFOSZ) * 8; 1506 1507 /* Get RSSI from PHY status descriptor if present. */ 1508 if (infosz != 0) 1509 *rssi = rsu_get_rssi(sc, rate, &stat[1]); 1510 else 1511 *rssi = 0; 1512 1513 RSU_DPRINTF(sc, RSU_DEBUG_RX, 1514 "%s: Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 1515 __func__, 1516 pktlen, rate, infosz, *rssi); 1517 1518 m = m_get2(pktlen, M_NOWAIT, MT_DATA, M_PKTHDR); 1519 if (__predict_false(m == NULL)) { 1520 counter_u64_add(ic->ic_ierrors, 1); 1521 return NULL; 1522 } 1523 /* Hardware does Rx TCP checksum offload. */ 1524 if (rxdw3 & R92S_RXDW3_TCPCHKVALID) { 1525 if (__predict_true(rxdw3 & R92S_RXDW3_TCPCHKRPT)) 1526 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 1527 } 1528 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 1529 memcpy(mtod(m, uint8_t *), wh, pktlen); 1530 m->m_pkthdr.len = m->m_len = pktlen; 1531 1532 if (ieee80211_radiotap_active(ic)) { 1533 struct rsu_rx_radiotap_header *tap = &sc->sc_rxtap; 1534 1535 /* Map HW rate index to 802.11 rate. */ 1536 tap->wr_flags = 2; 1537 if (!(rxdw3 & R92S_RXDW3_HTC)) { 1538 switch (rate) { 1539 /* CCK. */ 1540 case 0: tap->wr_rate = 2; break; 1541 case 1: tap->wr_rate = 4; break; 1542 case 2: tap->wr_rate = 11; break; 1543 case 3: tap->wr_rate = 22; break; 1544 /* OFDM. */ 1545 case 4: tap->wr_rate = 12; break; 1546 case 5: tap->wr_rate = 18; break; 1547 case 6: tap->wr_rate = 24; break; 1548 case 7: tap->wr_rate = 36; break; 1549 case 8: tap->wr_rate = 48; break; 1550 case 9: tap->wr_rate = 72; break; 1551 case 10: tap->wr_rate = 96; break; 1552 case 11: tap->wr_rate = 108; break; 1553 } 1554 } else if (rate >= 12) { /* MCS0~15. */ 1555 /* Bit 7 set means HT MCS instead of rate. */ 1556 tap->wr_rate = 0x80 | (rate - 12); 1557 } 1558 tap->wr_dbm_antsignal = *rssi; 1559 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1560 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1561 } 1562 1563 return (m); 1564} 1565 1566static struct mbuf * 1567rsu_rx_multi_frame(struct rsu_softc *sc, uint8_t *buf, int len, int *rssi) 1568{ 1569 struct r92s_rx_stat *stat; 1570 uint32_t rxdw0; 1571 int totlen, pktlen, infosz, npkts; 1572 struct mbuf *m, *m0 = NULL, *prevm = NULL; 1573 1574 /* Get the number of encapsulated frames. */ 1575 stat = (struct r92s_rx_stat *)buf; 1576 npkts = MS(le32toh(stat->rxdw2), R92S_RXDW2_PKTCNT); 1577 RSU_DPRINTF(sc, RSU_DEBUG_RX, 1578 "%s: Rx %d frames in one chunk\n", __func__, npkts); 1579 1580 /* Process all of them. */ 1581 while (npkts-- > 0) { 1582 if (__predict_false(len < sizeof(*stat))) 1583 break; 1584 stat = (struct r92s_rx_stat *)buf; 1585 rxdw0 = le32toh(stat->rxdw0); 1586 1587 pktlen = MS(rxdw0, R92S_RXDW0_PKTLEN); 1588 if (__predict_false(pktlen == 0)) 1589 break; 1590 1591 infosz = MS(rxdw0, R92S_RXDW0_INFOSZ) * 8; 1592 1593 /* Make sure everything fits in xfer. */ 1594 totlen = sizeof(*stat) + infosz + pktlen; 1595 if (__predict_false(totlen > len)) 1596 break; 1597 1598 /* Process 802.11 frame. */ 1599 m = rsu_rx_frame(sc, buf, pktlen, rssi); 1600 if (m0 == NULL) 1601 m0 = m; 1602 if (prevm == NULL) 1603 prevm = m; 1604 else { 1605 prevm->m_next = m; 1606 prevm = m; 1607 } 1608 /* Next chunk is 128-byte aligned. */ 1609 totlen = (totlen + 127) & ~127; 1610 buf += totlen; 1611 len -= totlen; 1612 } 1613 1614 return (m0); 1615} 1616 1617static struct mbuf * 1618rsu_rxeof(struct usb_xfer *xfer, struct rsu_data *data, int *rssi) 1619{ 1620 struct rsu_softc *sc = data->sc; 1621 struct ieee80211com *ic = &sc->sc_ic; 1622 struct r92s_rx_stat *stat; 1623 int len; 1624 1625 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 1626 1627 if (__predict_false(len < sizeof(*stat))) { 1628 DPRINTF("xfer too short %d\n", len); 1629 counter_u64_add(ic->ic_ierrors, 1); 1630 return (NULL); 1631 } 1632 /* Determine if it is a firmware C2H event or an 802.11 frame. */ 1633 stat = (struct r92s_rx_stat *)data->buf; 1634 if ((le32toh(stat->rxdw1) & 0x1ff) == 0x1ff) { 1635 rsu_rx_multi_event(sc, data->buf, len); 1636 /* No packets to process. */ 1637 return (NULL); 1638 } else 1639 return (rsu_rx_multi_frame(sc, data->buf, len, rssi)); 1640} 1641 1642static void 1643rsu_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 1644{ 1645 struct rsu_softc *sc = usbd_xfer_softc(xfer); 1646 struct ieee80211com *ic = &sc->sc_ic; 1647 struct ieee80211_frame *wh; 1648 struct ieee80211_node *ni; 1649 struct mbuf *m = NULL, *next; 1650 struct rsu_data *data; 1651 int rssi = 1; 1652 1653 RSU_ASSERT_LOCKED(sc); 1654 1655 switch (USB_GET_STATE(xfer)) { 1656 case USB_ST_TRANSFERRED: 1657 data = STAILQ_FIRST(&sc->sc_rx_active); 1658 if (data == NULL) 1659 goto tr_setup; 1660 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1661 m = rsu_rxeof(xfer, data, &rssi); 1662 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1663 /* FALLTHROUGH */ 1664 case USB_ST_SETUP: 1665tr_setup: 1666 data = STAILQ_FIRST(&sc->sc_rx_inactive); 1667 if (data == NULL) { 1668 KASSERT(m == NULL, ("mbuf isn't NULL")); 1669 return; 1670 } 1671 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 1672 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 1673 usbd_xfer_set_frame_data(xfer, 0, data->buf, 1674 usbd_xfer_max_len(xfer)); 1675 usbd_transfer_submit(xfer); 1676 /* 1677 * To avoid LOR we should unlock our private mutex here to call 1678 * ieee80211_input() because here is at the end of a USB 1679 * callback and safe to unlock. 1680 */ 1681 RSU_UNLOCK(sc); 1682 while (m != NULL) { 1683 next = m->m_next; 1684 m->m_next = NULL; 1685 wh = mtod(m, struct ieee80211_frame *); 1686 ni = ieee80211_find_rxnode(ic, 1687 (struct ieee80211_frame_min *)wh); 1688 if (ni != NULL) { 1689 if (ni->ni_flags & IEEE80211_NODE_HT) 1690 m->m_flags |= M_AMPDU; 1691 (void)ieee80211_input(ni, m, rssi, 0); 1692 ieee80211_free_node(ni); 1693 } else 1694 (void)ieee80211_input_all(ic, m, rssi, 0); 1695 m = next; 1696 } 1697 RSU_LOCK(sc); 1698 break; 1699 default: 1700 /* needs it to the inactive queue due to a error. */ 1701 data = STAILQ_FIRST(&sc->sc_rx_active); 1702 if (data != NULL) { 1703 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 1704 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 1705 } 1706 if (error != USB_ERR_CANCELLED) { 1707 usbd_xfer_set_stall(xfer); 1708 counter_u64_add(ic->ic_ierrors, 1); 1709 goto tr_setup; 1710 } 1711 break; 1712 } 1713 1714} 1715 1716static void 1717rsu_txeof(struct usb_xfer *xfer, struct rsu_data *data) 1718{ 1719#ifdef USB_DEBUG 1720 struct rsu_softc *sc = usbd_xfer_softc(xfer); 1721#endif 1722 1723 RSU_DPRINTF(sc, RSU_DEBUG_TXDONE, "%s: called; data=%p\n", 1724 __func__, 1725 data); 1726 1727 if (data->m) { 1728 /* XXX status? */ 1729 ieee80211_tx_complete(data->ni, data->m, 0); 1730 data->m = NULL; 1731 data->ni = NULL; 1732 } 1733} 1734 1735static void 1736rsu_bulk_tx_callback_sub(struct usb_xfer *xfer, usb_error_t error, 1737 uint8_t which) 1738{ 1739 struct rsu_softc *sc = usbd_xfer_softc(xfer); 1740 struct ieee80211com *ic = &sc->sc_ic; 1741 struct rsu_data *data; 1742 1743 RSU_ASSERT_LOCKED(sc); 1744 1745 switch (USB_GET_STATE(xfer)) { 1746 case USB_ST_TRANSFERRED: 1747 data = STAILQ_FIRST(&sc->sc_tx_active[which]); 1748 if (data == NULL) 1749 goto tr_setup; 1750 RSU_DPRINTF(sc, RSU_DEBUG_TXDONE, "%s: transfer done %p\n", 1751 __func__, data); 1752 STAILQ_REMOVE_HEAD(&sc->sc_tx_active[which], next); 1753 rsu_txeof(xfer, data); 1754 rsu_freebuf(sc, data); 1755 /* FALLTHROUGH */ 1756 case USB_ST_SETUP: 1757tr_setup: 1758 data = STAILQ_FIRST(&sc->sc_tx_pending[which]); 1759 if (data == NULL) { 1760 RSU_DPRINTF(sc, RSU_DEBUG_TXDONE, 1761 "%s: empty pending queue sc %p\n", __func__, sc); 1762 return; 1763 } 1764 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending[which], next); 1765 STAILQ_INSERT_TAIL(&sc->sc_tx_active[which], data, next); 1766 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 1767 RSU_DPRINTF(sc, RSU_DEBUG_TXDONE, 1768 "%s: submitting transfer %p\n", 1769 __func__, 1770 data); 1771 usbd_transfer_submit(xfer); 1772 break; 1773 default: 1774 data = STAILQ_FIRST(&sc->sc_tx_active[which]); 1775 if (data != NULL) { 1776 STAILQ_REMOVE_HEAD(&sc->sc_tx_active[which], next); 1777 rsu_txeof(xfer, data); 1778 rsu_freebuf(sc, data); 1779 } 1780 counter_u64_add(ic->ic_oerrors, 1); 1781 1782 if (error != USB_ERR_CANCELLED) { 1783 usbd_xfer_set_stall(xfer); 1784 goto tr_setup; 1785 } 1786 break; 1787 } 1788} 1789 1790static void 1791rsu_bulk_tx_callback_be_bk(struct usb_xfer *xfer, usb_error_t error) 1792{ 1793 rsu_bulk_tx_callback_sub(xfer, error, RSU_BULK_TX_BE_BK); 1794} 1795 1796static void 1797rsu_bulk_tx_callback_vi_vo(struct usb_xfer *xfer, usb_error_t error) 1798{ 1799 rsu_bulk_tx_callback_sub(xfer, error, RSU_BULK_TX_VI_VO); 1800} 1801 1802static void 1803rsu_bulk_tx_callback_h2c(struct usb_xfer *xfer, usb_error_t error) 1804{ 1805 rsu_bulk_tx_callback_sub(xfer, error, RSU_BULK_TX_H2C); 1806} 1807 1808static int 1809rsu_tx_start(struct rsu_softc *sc, struct ieee80211_node *ni, 1810 struct mbuf *m0, struct rsu_data *data) 1811{ 1812 struct ieee80211com *ic = &sc->sc_ic; 1813 struct ieee80211vap *vap = ni->ni_vap; 1814 struct ieee80211_frame *wh; 1815 struct ieee80211_key *k = NULL; 1816 struct r92s_tx_desc *txd; 1817 uint8_t type; 1818 int prio = 0; 1819 uint8_t which; 1820 int hasqos; 1821 int xferlen; 1822 int qid; 1823 1824 RSU_ASSERT_LOCKED(sc); 1825 1826 wh = mtod(m0, struct ieee80211_frame *); 1827 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1828 1829 RSU_DPRINTF(sc, RSU_DEBUG_TX, "%s: data=%p, m=%p\n", 1830 __func__, data, m0); 1831 1832 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1833 k = ieee80211_crypto_encap(ni, m0); 1834 if (k == NULL) { 1835 device_printf(sc->sc_dev, 1836 "ieee80211_crypto_encap returns NULL.\n"); 1837 /* XXX we don't expect the fragmented frames */ 1838 m_freem(m0); 1839 return (ENOBUFS); 1840 } 1841 wh = mtod(m0, struct ieee80211_frame *); 1842 } 1843 /* If we have QoS then use it */ 1844 /* XXX TODO: mbuf WME/PRI versus TID? */ 1845 if (IEEE80211_QOS_HAS_SEQ(wh)) { 1846 /* Has QoS */ 1847 prio = M_WME_GETAC(m0); 1848 which = rsu_wme_ac_xfer_map[prio]; 1849 hasqos = 1; 1850 } else { 1851 /* Non-QoS TID */ 1852 /* XXX TODO: tid=0 for non-qos TID? */ 1853 which = rsu_wme_ac_xfer_map[WME_AC_BE]; 1854 hasqos = 0; 1855 prio = 0; 1856 } 1857 1858 qid = rsu_ac2qid[prio]; 1859#if 0 1860 switch (type) { 1861 case IEEE80211_FC0_TYPE_CTL: 1862 case IEEE80211_FC0_TYPE_MGT: 1863 which = rsu_wme_ac_xfer_map[WME_AC_VO]; 1864 break; 1865 default: 1866 which = rsu_wme_ac_xfer_map[M_WME_GETAC(m0)]; 1867 break; 1868 } 1869 hasqos = 0; 1870#endif 1871 1872 RSU_DPRINTF(sc, RSU_DEBUG_TX, "%s: pri=%d, which=%d, hasqos=%d\n", 1873 __func__, 1874 prio, 1875 which, 1876 hasqos); 1877 1878 /* Fill Tx descriptor. */ 1879 txd = (struct r92s_tx_desc *)data->buf; 1880 memset(txd, 0, sizeof(*txd)); 1881 1882 txd->txdw0 |= htole32( 1883 SM(R92S_TXDW0_PKTLEN, m0->m_pkthdr.len) | 1884 SM(R92S_TXDW0_OFFSET, sizeof(*txd)) | 1885 R92S_TXDW0_OWN | R92S_TXDW0_FSG | R92S_TXDW0_LSG); 1886 1887 txd->txdw1 |= htole32( 1888 SM(R92S_TXDW1_MACID, R92S_MACID_BSS) | SM(R92S_TXDW1_QSEL, qid)); 1889 if (!hasqos) 1890 txd->txdw1 |= htole32(R92S_TXDW1_NONQOS); 1891#ifdef notyet 1892 if (k != NULL) { 1893 switch (k->wk_cipher->ic_cipher) { 1894 case IEEE80211_CIPHER_WEP: 1895 cipher = R92S_TXDW1_CIPHER_WEP; 1896 break; 1897 case IEEE80211_CIPHER_TKIP: 1898 cipher = R92S_TXDW1_CIPHER_TKIP; 1899 break; 1900 case IEEE80211_CIPHER_AES_CCM: 1901 cipher = R92S_TXDW1_CIPHER_AES; 1902 break; 1903 default: 1904 cipher = R92S_TXDW1_CIPHER_NONE; 1905 } 1906 txd->txdw1 |= htole32( 1907 SM(R92S_TXDW1_CIPHER, cipher) | 1908 SM(R92S_TXDW1_KEYIDX, k->k_id)); 1909 } 1910#endif 1911 /* XXX todo: set AGGEN bit if appropriate? */ 1912 txd->txdw2 |= htole32(R92S_TXDW2_BK); 1913 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1914 txd->txdw2 |= htole32(R92S_TXDW2_BMCAST); 1915 /* 1916 * Firmware will use and increment the sequence number for the 1917 * specified priority. 1918 */ 1919 txd->txdw3 |= htole32(SM(R92S_TXDW3_SEQ, prio)); 1920 1921 if (ieee80211_radiotap_active_vap(vap)) { 1922 struct rsu_tx_radiotap_header *tap = &sc->sc_txtap; 1923 1924 tap->wt_flags = 0; 1925 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1926 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1927 ieee80211_radiotap_tx(vap, m0); 1928 } 1929 1930 xferlen = sizeof(*txd) + m0->m_pkthdr.len; 1931 m_copydata(m0, 0, m0->m_pkthdr.len, (caddr_t)&txd[1]); 1932 1933 data->buflen = xferlen; 1934 data->ni = ni; 1935 data->m = m0; 1936 STAILQ_INSERT_TAIL(&sc->sc_tx_pending[which], data, next); 1937 1938 /* start transfer, if any */ 1939 usbd_transfer_start(sc->sc_xfer[which]); 1940 return (0); 1941} 1942 1943static int 1944rsu_transmit(struct ieee80211com *ic, struct mbuf *m) 1945{ 1946 struct rsu_softc *sc = ic->ic_softc; 1947 int error; 1948 1949 RSU_LOCK(sc); 1950 if (!sc->sc_running) { 1951 RSU_UNLOCK(sc); 1952 return (ENXIO); 1953 } 1954 error = mbufq_enqueue(&sc->sc_snd, m); 1955 if (error) { 1956 RSU_UNLOCK(sc); 1957 return (error); 1958 } 1959 rsu_start(sc); 1960 RSU_UNLOCK(sc); 1961 1962 return (0); 1963} 1964 1965static void 1966rsu_start(struct rsu_softc *sc) 1967{ 1968 struct ieee80211_node *ni; 1969 struct rsu_data *bf; 1970 struct mbuf *m; 1971 1972 RSU_ASSERT_LOCKED(sc); 1973 1974 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1975 bf = rsu_getbuf(sc); 1976 if (bf == NULL) { 1977 mbufq_prepend(&sc->sc_snd, m); 1978 break; 1979 } 1980 1981 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1982 m->m_pkthdr.rcvif = NULL; 1983 1984 if (rsu_tx_start(sc, ni, m, bf) != 0) { 1985 if_inc_counter(ni->ni_vap->iv_ifp, 1986 IFCOUNTER_OERRORS, 1); 1987 rsu_freebuf(sc, bf); 1988 ieee80211_free_node(ni); 1989 break; 1990 } 1991 } 1992} 1993 1994static void 1995rsu_parent(struct ieee80211com *ic) 1996{ 1997 struct rsu_softc *sc = ic->ic_softc; 1998 int startall = 0; 1999 2000 RSU_LOCK(sc); 2001 if (ic->ic_nrunning > 0) { 2002 if (!sc->sc_running) { 2003 rsu_init(sc); 2004 startall = 1; 2005 } 2006 } else if (sc->sc_running) 2007 rsu_stop(sc); 2008 RSU_UNLOCK(sc); 2009 2010 if (startall) 2011 ieee80211_start_all(ic); 2012} 2013 2014/* 2015 * Power on sequence for A-cut adapters. 2016 */ 2017static void 2018rsu_power_on_acut(struct rsu_softc *sc) 2019{ 2020 uint32_t reg; 2021 2022 rsu_write_1(sc, R92S_SPS0_CTRL + 1, 0x53); 2023 rsu_write_1(sc, R92S_SPS0_CTRL + 0, 0x57); 2024 2025 /* Enable AFE macro block's bandgap and Mbias. */ 2026 rsu_write_1(sc, R92S_AFE_MISC, 2027 rsu_read_1(sc, R92S_AFE_MISC) | 2028 R92S_AFE_MISC_BGEN | R92S_AFE_MISC_MBEN); 2029 /* Enable LDOA15 block. */ 2030 rsu_write_1(sc, R92S_LDOA15_CTRL, 2031 rsu_read_1(sc, R92S_LDOA15_CTRL) | R92S_LDA15_EN); 2032 2033 rsu_write_1(sc, R92S_SPS1_CTRL, 2034 rsu_read_1(sc, R92S_SPS1_CTRL) | R92S_SPS1_LDEN); 2035 rsu_ms_delay(sc, 2000); 2036 /* Enable switch regulator block. */ 2037 rsu_write_1(sc, R92S_SPS1_CTRL, 2038 rsu_read_1(sc, R92S_SPS1_CTRL) | R92S_SPS1_SWEN); 2039 2040 rsu_write_4(sc, R92S_SPS1_CTRL, 0x00a7b267); 2041 2042 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 1, 2043 rsu_read_1(sc, R92S_SYS_ISO_CTRL + 1) | 0x08); 2044 2045 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 2046 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x20); 2047 2048 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 1, 2049 rsu_read_1(sc, R92S_SYS_ISO_CTRL + 1) & ~0x90); 2050 2051 /* Enable AFE clock. */ 2052 rsu_write_1(sc, R92S_AFE_XTAL_CTRL + 1, 2053 rsu_read_1(sc, R92S_AFE_XTAL_CTRL + 1) & ~0x04); 2054 /* Enable AFE PLL macro block. */ 2055 rsu_write_1(sc, R92S_AFE_PLL_CTRL, 2056 rsu_read_1(sc, R92S_AFE_PLL_CTRL) | 0x11); 2057 /* Attach AFE PLL to MACTOP/BB. */ 2058 rsu_write_1(sc, R92S_SYS_ISO_CTRL, 2059 rsu_read_1(sc, R92S_SYS_ISO_CTRL) & ~0x11); 2060 2061 /* Switch to 40MHz clock instead of 80MHz. */ 2062 rsu_write_2(sc, R92S_SYS_CLKR, 2063 rsu_read_2(sc, R92S_SYS_CLKR) & ~R92S_SYS_CLKSEL); 2064 2065 /* Enable MAC clock. */ 2066 rsu_write_2(sc, R92S_SYS_CLKR, 2067 rsu_read_2(sc, R92S_SYS_CLKR) | 2068 R92S_MAC_CLK_EN | R92S_SYS_CLK_EN); 2069 2070 rsu_write_1(sc, R92S_PMC_FSM, 0x02); 2071 2072 /* Enable digital core and IOREG R/W. */ 2073 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 2074 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x08); 2075 2076 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 2077 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x80); 2078 2079 /* Switch the control path to firmware. */ 2080 reg = rsu_read_2(sc, R92S_SYS_CLKR); 2081 reg = (reg & ~R92S_SWHW_SEL) | R92S_FWHW_SEL; 2082 rsu_write_2(sc, R92S_SYS_CLKR, reg); 2083 2084 rsu_write_2(sc, R92S_CR, 0x37fc); 2085 2086 /* Fix USB RX FIFO issue. */ 2087 rsu_write_1(sc, 0xfe5c, 2088 rsu_read_1(sc, 0xfe5c) | 0x80); 2089 rsu_write_1(sc, 0x00ab, 2090 rsu_read_1(sc, 0x00ab) | 0xc0); 2091 2092 rsu_write_1(sc, R92S_SYS_CLKR, 2093 rsu_read_1(sc, R92S_SYS_CLKR) & ~R92S_SYS_CPU_CLKSEL); 2094} 2095 2096/* 2097 * Power on sequence for B-cut and C-cut adapters. 2098 */ 2099static void 2100rsu_power_on_bcut(struct rsu_softc *sc) 2101{ 2102 uint32_t reg; 2103 int ntries; 2104 2105 /* Prevent eFuse leakage. */ 2106 rsu_write_1(sc, 0x37, 0xb0); 2107 rsu_ms_delay(sc, 10); 2108 rsu_write_1(sc, 0x37, 0x30); 2109 2110 /* Switch the control path to hardware. */ 2111 reg = rsu_read_2(sc, R92S_SYS_CLKR); 2112 if (reg & R92S_FWHW_SEL) { 2113 rsu_write_2(sc, R92S_SYS_CLKR, 2114 reg & ~(R92S_SWHW_SEL | R92S_FWHW_SEL)); 2115 } 2116 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 2117 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) & ~0x8c); 2118 rsu_ms_delay(sc, 1); 2119 2120 rsu_write_1(sc, R92S_SPS0_CTRL + 1, 0x53); 2121 rsu_write_1(sc, R92S_SPS0_CTRL + 0, 0x57); 2122 2123 reg = rsu_read_1(sc, R92S_AFE_MISC); 2124 rsu_write_1(sc, R92S_AFE_MISC, reg | R92S_AFE_MISC_BGEN); 2125 rsu_write_1(sc, R92S_AFE_MISC, reg | R92S_AFE_MISC_BGEN | 2126 R92S_AFE_MISC_MBEN | R92S_AFE_MISC_I32_EN); 2127 2128 /* Enable PLL. */ 2129 rsu_write_1(sc, R92S_LDOA15_CTRL, 2130 rsu_read_1(sc, R92S_LDOA15_CTRL) | R92S_LDA15_EN); 2131 2132 rsu_write_1(sc, R92S_LDOV12D_CTRL, 2133 rsu_read_1(sc, R92S_LDOV12D_CTRL) | R92S_LDV12_EN); 2134 2135 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 1, 2136 rsu_read_1(sc, R92S_SYS_ISO_CTRL + 1) | 0x08); 2137 2138 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 2139 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x20); 2140 2141 /* Support 64KB IMEM. */ 2142 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 1, 2143 rsu_read_1(sc, R92S_SYS_ISO_CTRL + 1) & ~0x97); 2144 2145 /* Enable AFE clock. */ 2146 rsu_write_1(sc, R92S_AFE_XTAL_CTRL + 1, 2147 rsu_read_1(sc, R92S_AFE_XTAL_CTRL + 1) & ~0x04); 2148 /* Enable AFE PLL macro block. */ 2149 reg = rsu_read_1(sc, R92S_AFE_PLL_CTRL); 2150 rsu_write_1(sc, R92S_AFE_PLL_CTRL, reg | 0x11); 2151 rsu_ms_delay(sc, 1); 2152 rsu_write_1(sc, R92S_AFE_PLL_CTRL, reg | 0x51); 2153 rsu_ms_delay(sc, 1); 2154 rsu_write_1(sc, R92S_AFE_PLL_CTRL, reg | 0x11); 2155 rsu_ms_delay(sc, 1); 2156 2157 /* Attach AFE PLL to MACTOP/BB. */ 2158 rsu_write_1(sc, R92S_SYS_ISO_CTRL, 2159 rsu_read_1(sc, R92S_SYS_ISO_CTRL) & ~0x11); 2160 2161 /* Switch to 40MHz clock. */ 2162 rsu_write_1(sc, R92S_SYS_CLKR, 0x00); 2163 /* Disable CPU clock and 80MHz SSC. */ 2164 rsu_write_1(sc, R92S_SYS_CLKR, 2165 rsu_read_1(sc, R92S_SYS_CLKR) | 0xa0); 2166 /* Enable MAC clock. */ 2167 rsu_write_2(sc, R92S_SYS_CLKR, 2168 rsu_read_2(sc, R92S_SYS_CLKR) | 2169 R92S_MAC_CLK_EN | R92S_SYS_CLK_EN); 2170 2171 rsu_write_1(sc, R92S_PMC_FSM, 0x02); 2172 2173 /* Enable digital core and IOREG R/W. */ 2174 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 2175 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x08); 2176 2177 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 2178 rsu_read_1(sc, R92S_SYS_FUNC_EN + 1) | 0x80); 2179 2180 /* Switch the control path to firmware. */ 2181 reg = rsu_read_2(sc, R92S_SYS_CLKR); 2182 reg = (reg & ~R92S_SWHW_SEL) | R92S_FWHW_SEL; 2183 rsu_write_2(sc, R92S_SYS_CLKR, reg); 2184 2185 rsu_write_2(sc, R92S_CR, 0x37fc); 2186 2187 /* Fix USB RX FIFO issue. */ 2188 rsu_write_1(sc, 0xfe5c, 2189 rsu_read_1(sc, 0xfe5c) | 0x80); 2190 2191 rsu_write_1(sc, R92S_SYS_CLKR, 2192 rsu_read_1(sc, R92S_SYS_CLKR) & ~R92S_SYS_CPU_CLKSEL); 2193 2194 rsu_write_1(sc, 0xfe1c, 0x80); 2195 2196 /* Make sure TxDMA is ready to download firmware. */ 2197 for (ntries = 0; ntries < 20; ntries++) { 2198 reg = rsu_read_1(sc, R92S_TCR); 2199 if ((reg & (R92S_TCR_IMEM_CHK_RPT | R92S_TCR_EMEM_CHK_RPT)) == 2200 (R92S_TCR_IMEM_CHK_RPT | R92S_TCR_EMEM_CHK_RPT)) 2201 break; 2202 rsu_ms_delay(sc, 1); 2203 } 2204 if (ntries == 20) { 2205 RSU_DPRINTF(sc, RSU_DEBUG_RESET | RSU_DEBUG_TX, 2206 "%s: TxDMA is not ready\n", 2207 __func__); 2208 /* Reset TxDMA. */ 2209 reg = rsu_read_1(sc, R92S_CR); 2210 rsu_write_1(sc, R92S_CR, reg & ~R92S_CR_TXDMA_EN); 2211 rsu_ms_delay(sc, 1); 2212 rsu_write_1(sc, R92S_CR, reg | R92S_CR_TXDMA_EN); 2213 } 2214} 2215 2216static void 2217rsu_power_off(struct rsu_softc *sc) 2218{ 2219 /* Turn RF off. */ 2220 rsu_write_1(sc, R92S_RF_CTRL, 0x00); 2221 rsu_ms_delay(sc, 5); 2222 2223 /* Turn MAC off. */ 2224 /* Switch control path. */ 2225 rsu_write_1(sc, R92S_SYS_CLKR + 1, 0x38); 2226 /* Reset MACTOP. */ 2227 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 0x70); 2228 rsu_write_1(sc, R92S_PMC_FSM, 0x06); 2229 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 0, 0xf9); 2230 rsu_write_1(sc, R92S_SYS_ISO_CTRL + 1, 0xe8); 2231 2232 /* Disable AFE PLL. */ 2233 rsu_write_1(sc, R92S_AFE_PLL_CTRL, 0x00); 2234 /* Disable A15V. */ 2235 rsu_write_1(sc, R92S_LDOA15_CTRL, 0x54); 2236 /* Disable eFuse 1.2V. */ 2237 rsu_write_1(sc, R92S_SYS_FUNC_EN + 1, 0x50); 2238 rsu_write_1(sc, R92S_LDOV12D_CTRL, 0x24); 2239 /* Enable AFE macro block's bandgap and Mbias. */ 2240 rsu_write_1(sc, R92S_AFE_MISC, 0x30); 2241 /* Disable 1.6V LDO. */ 2242 rsu_write_1(sc, R92S_SPS0_CTRL + 0, 0x56); 2243 rsu_write_1(sc, R92S_SPS0_CTRL + 1, 0x43); 2244} 2245 2246static int 2247rsu_fw_loadsection(struct rsu_softc *sc, const uint8_t *buf, int len) 2248{ 2249 const uint8_t which = rsu_wme_ac_xfer_map[WME_AC_VO]; 2250 struct rsu_data *data; 2251 struct r92s_tx_desc *txd; 2252 int mlen; 2253 2254 while (len > 0) { 2255 data = rsu_getbuf(sc); 2256 if (data == NULL) 2257 return (ENOMEM); 2258 txd = (struct r92s_tx_desc *)data->buf; 2259 memset(txd, 0, sizeof(*txd)); 2260 if (len <= RSU_TXBUFSZ - sizeof(*txd)) { 2261 /* Last chunk. */ 2262 txd->txdw0 |= htole32(R92S_TXDW0_LINIP); 2263 mlen = len; 2264 } else 2265 mlen = RSU_TXBUFSZ - sizeof(*txd); 2266 txd->txdw0 |= htole32(SM(R92S_TXDW0_PKTLEN, mlen)); 2267 memcpy(&txd[1], buf, mlen); 2268 data->buflen = sizeof(*txd) + mlen; 2269 RSU_DPRINTF(sc, RSU_DEBUG_TX | RSU_DEBUG_FW | RSU_DEBUG_RESET, 2270 "%s: starting transfer %p\n", 2271 __func__, data); 2272 STAILQ_INSERT_TAIL(&sc->sc_tx_pending[which], data, next); 2273 buf += mlen; 2274 len -= mlen; 2275 } 2276 usbd_transfer_start(sc->sc_xfer[which]); 2277 return (0); 2278} 2279 2280static int 2281rsu_load_firmware(struct rsu_softc *sc) 2282{ 2283 const struct r92s_fw_hdr *hdr; 2284 struct r92s_fw_priv *dmem; 2285 struct ieee80211com *ic = &sc->sc_ic; 2286 const uint8_t *imem, *emem; 2287 int imemsz, ememsz; 2288 const struct firmware *fw; 2289 size_t size; 2290 uint32_t reg; 2291 int ntries, error; 2292 2293 if (rsu_read_1(sc, R92S_TCR) & R92S_TCR_FWRDY) { 2294 RSU_DPRINTF(sc, RSU_DEBUG_FW | RSU_DEBUG_RESET, 2295 "%s: Firmware already loaded\n", 2296 __func__); 2297 return (0); 2298 } 2299 2300 RSU_UNLOCK(sc); 2301 /* Read firmware image from the filesystem. */ 2302 if ((fw = firmware_get("rsu-rtl8712fw")) == NULL) { 2303 device_printf(sc->sc_dev, 2304 "%s: failed load firmware of file rsu-rtl8712fw\n", 2305 __func__); 2306 RSU_LOCK(sc); 2307 return (ENXIO); 2308 } 2309 RSU_LOCK(sc); 2310 size = fw->datasize; 2311 if (size < sizeof(*hdr)) { 2312 device_printf(sc->sc_dev, "firmware too short\n"); 2313 error = EINVAL; 2314 goto fail; 2315 } 2316 hdr = (const struct r92s_fw_hdr *)fw->data; 2317 if (hdr->signature != htole16(0x8712) && 2318 hdr->signature != htole16(0x8192)) { 2319 device_printf(sc->sc_dev, 2320 "invalid firmware signature 0x%x\n", 2321 le16toh(hdr->signature)); 2322 error = EINVAL; 2323 goto fail; 2324 } 2325 DPRINTF("FW V%d %02x-%02x %02x:%02x\n", le16toh(hdr->version), 2326 hdr->month, hdr->day, hdr->hour, hdr->minute); 2327 2328 /* Make sure that driver and firmware are in sync. */ 2329 if (hdr->privsz != htole32(sizeof(*dmem))) { 2330 device_printf(sc->sc_dev, "unsupported firmware image\n"); 2331 error = EINVAL; 2332 goto fail; 2333 } 2334 /* Get FW sections sizes. */ 2335 imemsz = le32toh(hdr->imemsz); 2336 ememsz = le32toh(hdr->sramsz); 2337 /* Check that all FW sections fit in image. */ 2338 if (size < sizeof(*hdr) + imemsz + ememsz) { 2339 device_printf(sc->sc_dev, "firmware too short\n"); 2340 error = EINVAL; 2341 goto fail; 2342 } 2343 imem = (const uint8_t *)&hdr[1]; 2344 emem = imem + imemsz; 2345 2346 /* Load IMEM section. */ 2347 error = rsu_fw_loadsection(sc, imem, imemsz); 2348 if (error != 0) { 2349 device_printf(sc->sc_dev, 2350 "could not load firmware section %s\n", "IMEM"); 2351 goto fail; 2352 } 2353 /* Wait for load to complete. */ 2354 for (ntries = 0; ntries != 50; ntries++) { 2355 rsu_ms_delay(sc, 10); 2356 reg = rsu_read_1(sc, R92S_TCR); 2357 if (reg & R92S_TCR_IMEM_CODE_DONE) 2358 break; 2359 } 2360 if (ntries == 50) { 2361 device_printf(sc->sc_dev, "timeout waiting for IMEM transfer\n"); 2362 error = ETIMEDOUT; 2363 goto fail; 2364 } 2365 /* Load EMEM section. */ 2366 error = rsu_fw_loadsection(sc, emem, ememsz); 2367 if (error != 0) { 2368 device_printf(sc->sc_dev, 2369 "could not load firmware section %s\n", "EMEM"); 2370 goto fail; 2371 } 2372 /* Wait for load to complete. */ 2373 for (ntries = 0; ntries != 50; ntries++) { 2374 rsu_ms_delay(sc, 10); 2375 reg = rsu_read_2(sc, R92S_TCR); 2376 if (reg & R92S_TCR_EMEM_CODE_DONE) 2377 break; 2378 } 2379 if (ntries == 50) { 2380 device_printf(sc->sc_dev, "timeout waiting for EMEM transfer\n"); 2381 error = ETIMEDOUT; 2382 goto fail; 2383 } 2384 /* Enable CPU. */ 2385 rsu_write_1(sc, R92S_SYS_CLKR, 2386 rsu_read_1(sc, R92S_SYS_CLKR) | R92S_SYS_CPU_CLKSEL); 2387 if (!(rsu_read_1(sc, R92S_SYS_CLKR) & R92S_SYS_CPU_CLKSEL)) { 2388 device_printf(sc->sc_dev, "could not enable system clock\n"); 2389 error = EIO; 2390 goto fail; 2391 } 2392 rsu_write_2(sc, R92S_SYS_FUNC_EN, 2393 rsu_read_2(sc, R92S_SYS_FUNC_EN) | R92S_FEN_CPUEN); 2394 if (!(rsu_read_2(sc, R92S_SYS_FUNC_EN) & R92S_FEN_CPUEN)) { 2395 device_printf(sc->sc_dev, 2396 "could not enable microcontroller\n"); 2397 error = EIO; 2398 goto fail; 2399 } 2400 /* Wait for CPU to initialize. */ 2401 for (ntries = 0; ntries < 100; ntries++) { 2402 if (rsu_read_1(sc, R92S_TCR) & R92S_TCR_IMEM_RDY) 2403 break; 2404 rsu_ms_delay(sc, 1); 2405 } 2406 if (ntries == 100) { 2407 device_printf(sc->sc_dev, 2408 "timeout waiting for microcontroller\n"); 2409 error = ETIMEDOUT; 2410 goto fail; 2411 } 2412 2413 /* Update DMEM section before loading. */ 2414 dmem = __DECONST(struct r92s_fw_priv *, &hdr->priv); 2415 memset(dmem, 0, sizeof(*dmem)); 2416 dmem->hci_sel = R92S_HCI_SEL_USB | R92S_HCI_SEL_8172; 2417 dmem->nendpoints = sc->sc_nendpoints; 2418 /* XXX TODO: rf_config should come from ROM */ 2419 dmem->rf_config = 0x11; /* 1T1R */ 2420 dmem->vcs_type = R92S_VCS_TYPE_AUTO; 2421 dmem->vcs_mode = R92S_VCS_MODE_RTS_CTS; 2422 dmem->turbo_mode = 0; 2423 dmem->bw40_en = !! (ic->ic_htcaps & IEEE80211_HTCAP_CHWIDTH40); 2424 dmem->amsdu2ampdu_en = !! (sc->sc_ht); 2425 dmem->ampdu_en = !! (sc->sc_ht); 2426 dmem->agg_offload = !! (sc->sc_ht); 2427 dmem->qos_en = 1; 2428 /* Load DMEM section. */ 2429 error = rsu_fw_loadsection(sc, (uint8_t *)dmem, sizeof(*dmem)); 2430 if (error != 0) { 2431 device_printf(sc->sc_dev, 2432 "could not load firmware section %s\n", "DMEM"); 2433 goto fail; 2434 } 2435 /* Wait for load to complete. */ 2436 for (ntries = 0; ntries < 100; ntries++) { 2437 if (rsu_read_1(sc, R92S_TCR) & R92S_TCR_DMEM_CODE_DONE) 2438 break; 2439 rsu_ms_delay(sc, 1); 2440 } 2441 if (ntries == 100) { 2442 device_printf(sc->sc_dev, "timeout waiting for %s transfer\n", 2443 "DMEM"); 2444 error = ETIMEDOUT; 2445 goto fail; 2446 } 2447 /* Wait for firmware readiness. */ 2448 for (ntries = 0; ntries < 60; ntries++) { 2449 if (!(rsu_read_1(sc, R92S_TCR) & R92S_TCR_FWRDY)) 2450 break; 2451 rsu_ms_delay(sc, 1); 2452 } 2453 if (ntries == 60) { 2454 device_printf(sc->sc_dev, 2455 "timeout waiting for firmware readiness\n"); 2456 error = ETIMEDOUT; 2457 goto fail; 2458 } 2459 fail: 2460 firmware_put(fw, FIRMWARE_UNLOAD); 2461 return (error); 2462} 2463 2464 2465static int 2466rsu_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 2467 const struct ieee80211_bpf_params *params) 2468{ 2469 struct ieee80211com *ic = ni->ni_ic; 2470 struct rsu_softc *sc = ic->ic_softc; 2471 struct rsu_data *bf; 2472 2473 /* prevent management frames from being sent if we're not ready */ 2474 if (!sc->sc_running) { 2475 m_freem(m); 2476 ieee80211_free_node(ni); 2477 return (ENETDOWN); 2478 } 2479 RSU_LOCK(sc); 2480 bf = rsu_getbuf(sc); 2481 if (bf == NULL) { 2482 ieee80211_free_node(ni); 2483 m_freem(m); 2484 RSU_UNLOCK(sc); 2485 return (ENOBUFS); 2486 } 2487 if (rsu_tx_start(sc, ni, m, bf) != 0) { 2488 ieee80211_free_node(ni); 2489 rsu_freebuf(sc, bf); 2490 RSU_UNLOCK(sc); 2491 return (EIO); 2492 } 2493 RSU_UNLOCK(sc); 2494 2495 return (0); 2496} 2497 2498static void 2499rsu_init(struct rsu_softc *sc) 2500{ 2501 struct ieee80211com *ic = &sc->sc_ic; 2502 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2503 uint8_t macaddr[IEEE80211_ADDR_LEN]; 2504 struct r92s_set_pwr_mode cmd; 2505 int error; 2506 int i; 2507 2508 RSU_ASSERT_LOCKED(sc); 2509 2510 /* Init host async commands ring. */ 2511 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 2512 2513 /* Power on adapter. */ 2514 if (sc->cut == 1) 2515 rsu_power_on_acut(sc); 2516 else 2517 rsu_power_on_bcut(sc); 2518 2519 /* Load firmware. */ 2520 error = rsu_load_firmware(sc); 2521 if (error != 0) 2522 goto fail; 2523 2524 /* Enable Rx TCP checksum offload. */ 2525 rsu_write_4(sc, R92S_RCR, 2526 rsu_read_4(sc, R92S_RCR) | 0x04000000); 2527 /* Append PHY status. */ 2528 rsu_write_4(sc, R92S_RCR, 2529 rsu_read_4(sc, R92S_RCR) | 0x02000000); 2530 2531 rsu_write_4(sc, R92S_CR, 2532 rsu_read_4(sc, R92S_CR) & ~0xff000000); 2533 2534 /* Use 128 bytes pages. */ 2535 rsu_write_1(sc, 0x00b5, 2536 rsu_read_1(sc, 0x00b5) | 0x01); 2537 /* Enable USB Rx aggregation. */ 2538 rsu_write_1(sc, 0x00bd, 2539 rsu_read_1(sc, 0x00bd) | 0x80); 2540 /* Set USB Rx aggregation threshold. */ 2541 rsu_write_1(sc, 0x00d9, 0x01); 2542 /* Set USB Rx aggregation timeout (1.7ms/4). */ 2543 rsu_write_1(sc, 0xfe5b, 0x04); 2544 /* Fix USB Rx FIFO issue. */ 2545 rsu_write_1(sc, 0xfe5c, 2546 rsu_read_1(sc, 0xfe5c) | 0x80); 2547 2548 /* Set MAC address. */ 2549 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 2550 rsu_write_region_1(sc, R92S_MACID, macaddr, IEEE80211_ADDR_LEN); 2551 2552 /* It really takes 1.5 seconds for the firmware to boot: */ 2553 rsu_ms_delay(sc, 2000); 2554 2555 RSU_DPRINTF(sc, RSU_DEBUG_RESET, "%s: setting MAC address to %s\n", 2556 __func__, 2557 ether_sprintf(macaddr)); 2558 error = rsu_fw_cmd(sc, R92S_CMD_SET_MAC_ADDRESS, macaddr, 2559 IEEE80211_ADDR_LEN); 2560 if (error != 0) { 2561 device_printf(sc->sc_dev, "could not set MAC address\n"); 2562 goto fail; 2563 } 2564 2565 rsu_write_1(sc, R92S_USB_HRPWM, 2566 R92S_USB_HRPWM_PS_ST_ACTIVE | R92S_USB_HRPWM_PS_ALL_ON); 2567 2568 /* Set PS mode fully active */ 2569 memset(&cmd, 0, sizeof(cmd)); 2570 cmd.mode = R92S_PS_MODE_ACTIVE; 2571 RSU_DPRINTF(sc, RSU_DEBUG_RESET, "%s: setting ps mode to %d\n", 2572 __func__, cmd.mode); 2573 error = rsu_fw_cmd(sc, R92S_CMD_SET_PWR_MODE, &cmd, sizeof(cmd)); 2574 if (error != 0) { 2575 device_printf(sc->sc_dev, "could not set PS mode\n"); 2576 goto fail; 2577 } 2578 2579 if (ic->ic_htcaps & IEEE80211_HTCAP_CHWIDTH40) { 2580 /* Enable 40MHz mode. */ 2581 error = rsu_fw_iocmd(sc, 2582 SM(R92S_IOCMD_CLASS, 0xf4) | 2583 SM(R92S_IOCMD_INDEX, 0x00) | 2584 SM(R92S_IOCMD_VALUE, 0x0007)); 2585 if (error != 0) { 2586 device_printf(sc->sc_dev, 2587 "could not enable 40MHz mode\n"); 2588 goto fail; 2589 } 2590 } 2591 2592 sc->sc_scan_pass = 0; 2593 usbd_transfer_start(sc->sc_xfer[RSU_BULK_RX]); 2594 2595 /* We're ready to go. */ 2596 sc->sc_running = 1; 2597 return; 2598fail: 2599 /* Need to stop all failed transfers, if any */ 2600 for (i = 0; i != RSU_N_TRANSFER; i++) 2601 usbd_transfer_stop(sc->sc_xfer[i]); 2602} 2603 2604static void 2605rsu_stop(struct rsu_softc *sc) 2606{ 2607 int i; 2608 2609 sc->sc_running = 0; 2610 sc->sc_calibrating = 0; 2611 taskqueue_cancel_timeout(taskqueue_thread, &sc->calib_task, NULL); 2612 2613 /* Power off adapter. */ 2614 rsu_power_off(sc); 2615 2616 for (i = 0; i < RSU_N_TRANSFER; i++) 2617 usbd_transfer_stop(sc->sc_xfer[i]); 2618} 2619 2620/* 2621 * Note: usb_pause_mtx() actually releases the mutex before calling pause(), 2622 * which breaks any kind of driver serialisation. 2623 */ 2624static void 2625rsu_ms_delay(struct rsu_softc *sc, int ms) 2626{ 2627 2628 //usb_pause_mtx(&sc->sc_mtx, hz / 1000); 2629 DELAY(ms * 1000); 2630} 2631