1/*-
2 * Copyright (c) 2013-2014 Kevin Lo
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 */
28
29#define	AXGE_ACCESS_MAC			0x01
30#define	AXGE_ACCESS_PHY			0x02
31#define	AXGE_ACCESS_WAKEUP		0x03
32#define	AXGE_ACCESS_EEPROM		0x04
33#define	AXGE_ACCESS_EFUSE		0x05
34#define	AXGE_RELOAD_EEPROM_EFUSE	0x06
35#define	AXGE_WRITE_EFUSE_EN		0x09
36#define	AXGE_WRITE_EFUSE_DIS		0x0A
37#define	AXGE_ACCESS_MFAB		0x10
38
39/* Physical link status register */
40#define	AXGE_PLSR			0x02
41#define	PLSR_USB_FS			0x01
42#define	PLSR_USB_HS			0x02
43#define	PLSR_USB_SS			0x04
44
45/* EEPROM address register */
46#define	AXGE_EAR			0x07
47
48/* EEPROM data low register */
49#define	AXGE_EDLR			0x08
50
51/* EEPROM data high register */
52#define	AXGE_EDHR			0x09
53
54/* EEPROM command register */
55#define	AXGE_ECR			0x0a
56
57/* Rx control register */
58#define	AXGE_RCR			0x0b
59#define	RCR_STOP			0x0000
60#define	RCR_PRO				0x0001
61#define	RCR_AMALL			0x0002
62#define	RCR_AB				0x0008
63#define	RCR_AM				0x0010
64#define	RCR_AP				0x0020
65#define	RCR_SO				0x0080
66#define	RCR_DROP_CRCE			0x0100
67#define	RCR_IPE				0x0200
68#define	RCR_TX_CRC_PAD			0x0400
69
70/* Node id register */
71#define	AXGE_NIDR			0x10
72
73/* Multicast filter array */
74#define	AXGE_MFA			0x16
75
76/* Medium status register */
77#define	AXGE_MSR			0x22
78#define	MSR_GM				0x0001
79#define	MSR_FD				0x0002
80#define	MSR_EN_125MHZ			0x0008
81#define	MSR_RFC				0x0010
82#define	MSR_TFC				0x0020
83#define	MSR_RE				0x0100
84#define	MSR_PS				0x0200
85
86/* Monitor mode status register */
87#define	AXGE_MMSR			0x24
88#define	MMSR_RWLC			0x02
89#define	MMSR_RWMP			0x04
90#define	MMSR_RWWF			0x08
91#define	MMSR_RW_FLAG			0x10
92#define	MMSR_PME_POL			0x20
93#define	MMSR_PME_TYPE			0x40
94#define	MMSR_PME_IND			0x80
95
96/* GPIO control/status register */
97#define	AXGE_GPIOCR			0x25
98
99/* Ethernet PHY power & reset control register */
100#define	AXGE_EPPRCR			0x26
101#define	EPPRCR_BZ			0x0010
102#define	EPPRCR_IPRL			0x0020
103#define	EPPRCR_AUTODETACH		0x1000
104
105#define	AXGE_RX_BULKIN_QCTRL		0x2e
106
107#define	AXGE_CLK_SELECT			0x33
108#define	AXGE_CLK_SELECT_BCS		0x01
109#define	AXGE_CLK_SELECT_ACS		0x02
110#define	AXGE_CLK_SELECT_ACSREQ		0x10
111#define	AXGE_CLK_SELECT_ULR		0x08
112
113/* COE Rx control register */
114#define	AXGE_CRCR			0x34
115#define	CRCR_IP				0x01
116#define	CRCR_TCP			0x02
117#define	CRCR_UDP			0x04
118#define	CRCR_ICMP			0x08
119#define	CRCR_IGMP			0x10
120#define	CRCR_TCPV6			0x20
121#define	CRCR_UDPV6			0x40
122#define	CRCR_ICMPV6			0x80
123
124/* COE Tx control register */
125#define	AXGE_CTCR			0x35
126#define	CTCR_IP				0x01
127#define	CTCR_TCP			0x02
128#define	CTCR_UDP			0x04
129#define	CTCR_ICMP			0x08
130#define	CTCR_IGMP			0x10
131#define	CTCR_TCPV6			0x20
132#define	CTCR_UDPV6			0x40
133#define	CTCR_ICMPV6			0x80
134
135/* Pause water level high register */
136#define	AXGE_PWLHR			0x54
137
138/* Pause water level low register */
139#define	AXGE_PWLLR			0x55
140
141#define	AXGE_CONFIG_IDX			0	/* config number 1 */
142#define	AXGE_IFACE_IDX			0
143
144#define	AXGE_RXHDR_L4_TYPE_MASK		0x1c
145#define	AXGE_RXHDR_L4CSUM_ERR		1
146#define	AXGE_RXHDR_L3CSUM_ERR		2
147#define	AXGE_RXHDR_L4_TYPE_UDP		4
148#define	AXGE_RXHDR_L4_TYPE_TCP		16
149#define	AXGE_RXHDR_CRC_ERR		0x20000000
150#define	AXGE_RXHDR_DROP_ERR		0x80000000
151
152#define	GET_MII(sc)		uether_getmii(&(sc)->sc_ue)
153
154/* The interrupt endpoint is currently unused by the ASIX part. */
155enum {
156	AXGE_BULK_DT_WR,
157	AXGE_BULK_DT_RD,
158	AXGE_N_TRANSFER,
159};
160
161struct axge_softc {
162	struct usb_ether	sc_ue;
163	struct mtx		sc_mtx;
164	struct usb_xfer		*sc_xfer[AXGE_N_TRANSFER];
165	int			sc_phyno;
166
167	int			sc_flags;
168#define	AXGE_FLAG_LINK		0x0001	/* got a link */
169};
170
171#define	AXGE_LOCK(_sc)			mtx_lock(&(_sc)->sc_mtx)
172#define	AXGE_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_mtx)
173#define	AXGE_LOCK_ASSERT(_sc, t)	mtx_assert(&(_sc)->sc_mtx, t)
174