1/* $FreeBSD: stable/11/sys/dev/usb/controller/xhci.h 358019 2020-02-17 09:59:28Z hselasky $ */ 2 3/*- 4 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28#ifndef _XHCI_H_ 29#define _XHCI_H_ 30 31#define XHCI_MAX_DEVICES MIN(USB_MAX_DEVICES, 128) 32#define XHCI_MAX_ENDPOINTS 32 /* hardcoded - do not change */ 33#define XHCI_MAX_SCRATCHPADS 256 /* theoretical max is 1023 */ 34#define XHCI_MAX_EVENTS (16 * 13) 35#define XHCI_MAX_COMMANDS (16 * 1) 36#define XHCI_MAX_RSEG 1 37#define XHCI_MAX_TRANSFERS 4 38#if USB_MAX_EP_STREAMS == 8 39#define XHCI_MAX_STREAMS 8 40#define XHCI_MAX_STREAMS_LOG 3 41#elif USB_MAX_EP_STREAMS == 1 42#define XHCI_MAX_STREAMS 1 43#define XHCI_MAX_STREAMS_LOG 0 44#else 45#error "The USB_MAX_EP_STREAMS value is not supported." 46#endif 47#define XHCI_DEV_CTX_ADDR_ALIGN 64 /* bytes */ 48#define XHCI_DEV_CTX_ALIGN 64 /* bytes */ 49#define XHCI_INPUT_CTX_ALIGN 64 /* bytes */ 50#define XHCI_SLOT_CTX_ALIGN 32 /* bytes */ 51#define XHCI_ENDP_CTX_ALIGN 32 /* bytes */ 52#define XHCI_STREAM_CTX_ALIGN 16 /* bytes */ 53#define XHCI_TRANS_RING_SEG_ALIGN 16 /* bytes */ 54#define XHCI_CMD_RING_SEG_ALIGN 64 /* bytes */ 55#define XHCI_EVENT_RING_SEG_ALIGN 64 /* bytes */ 56#define XHCI_SCRATCH_BUF_ARRAY_ALIGN 64 /* bytes */ 57#define XHCI_SCRATCH_BUFFER_ALIGN USB_PAGE_SIZE 58#define XHCI_TRB_ALIGN 16 /* bytes */ 59#define XHCI_TD_ALIGN 64 /* bytes */ 60#define XHCI_PAGE_SIZE 4096 /* bytes */ 61 62struct xhci_dev_ctx_addr { 63 volatile uint64_t qwBaaDevCtxAddr[USB_MAX_DEVICES + 1]; 64 struct { 65 volatile uint64_t dummy; 66 } __aligned(64) padding; 67 volatile uint64_t qwSpBufPtr[XHCI_MAX_SCRATCHPADS]; 68}; 69 70#define XHCI_EPNO2EPID(x) \ 71 ((((x) & UE_DIR_IN) ? 1 : 0) | (2 * ((x) & UE_ADDR))) 72 73struct xhci_slot_ctx { 74 volatile uint32_t dwSctx0; 75#define XHCI_SCTX_0_ROUTE_SET(x) ((x) & 0xFFFFF) 76#define XHCI_SCTX_0_ROUTE_GET(x) ((x) & 0xFFFFF) 77#define XHCI_SCTX_0_SPEED_SET(x) (((x) & 0xF) << 20) 78#define XHCI_SCTX_0_SPEED_GET(x) (((x) >> 20) & 0xF) 79#define XHCI_SCTX_0_MTT_SET(x) (((x) & 0x1) << 25) 80#define XHCI_SCTX_0_MTT_GET(x) (((x) >> 25) & 0x1) 81#define XHCI_SCTX_0_HUB_SET(x) (((x) & 0x1) << 26) 82#define XHCI_SCTX_0_HUB_GET(x) (((x) >> 26) & 0x1) 83#define XHCI_SCTX_0_CTX_NUM_SET(x) (((x) & 0x1F) << 27) 84#define XHCI_SCTX_0_CTX_NUM_GET(x) (((x) >> 27) & 0x1F) 85 volatile uint32_t dwSctx1; 86#define XHCI_SCTX_1_MAX_EL_SET(x) ((x) & 0xFFFF) 87#define XHCI_SCTX_1_MAX_EL_GET(x) ((x) & 0xFFFF) 88#define XHCI_SCTX_1_RH_PORT_SET(x) (((x) & 0xFF) << 16) 89#define XHCI_SCTX_1_RH_PORT_GET(x) (((x) >> 16) & 0xFF) 90#define XHCI_SCTX_1_NUM_PORTS_SET(x) (((x) & 0xFF) << 24) 91#define XHCI_SCTX_1_NUM_PORTS_GET(x) (((x) >> 24) & 0xFF) 92 volatile uint32_t dwSctx2; 93#define XHCI_SCTX_2_TT_HUB_SID_SET(x) ((x) & 0xFF) 94#define XHCI_SCTX_2_TT_HUB_SID_GET(x) ((x) & 0xFF) 95#define XHCI_SCTX_2_TT_PORT_NUM_SET(x) (((x) & 0xFF) << 8) 96#define XHCI_SCTX_2_TT_PORT_NUM_GET(x) (((x) >> 8) & 0xFF) 97#define XHCI_SCTX_2_TT_THINK_TIME_SET(x) (((x) & 0x3) << 16) 98#define XHCI_SCTX_2_TT_THINK_TIME_GET(x) (((x) >> 16) & 0x3) 99#define XHCI_SCTX_2_IRQ_TARGET_SET(x) (((x) & 0x3FF) << 22) 100#define XHCI_SCTX_2_IRQ_TARGET_GET(x) (((x) >> 22) & 0x3FF) 101 volatile uint32_t dwSctx3; 102#define XHCI_SCTX_3_DEV_ADDR_SET(x) ((x) & 0xFF) 103#define XHCI_SCTX_3_DEV_ADDR_GET(x) ((x) & 0xFF) 104#define XHCI_SCTX_3_SLOT_STATE_SET(x) (((x) & 0x1F) << 27) 105#define XHCI_SCTX_3_SLOT_STATE_GET(x) (((x) >> 27) & 0x1F) 106 volatile uint32_t dwSctx4; 107 volatile uint32_t dwSctx5; 108 volatile uint32_t dwSctx6; 109 volatile uint32_t dwSctx7; 110}; 111 112struct xhci_endp_ctx { 113 volatile uint32_t dwEpCtx0; 114#define XHCI_EPCTX_0_EPSTATE_SET(x) ((x) & 0x7) 115#define XHCI_EPCTX_0_EPSTATE_GET(x) ((x) & 0x7) 116#define XHCI_EPCTX_0_EPSTATE_DISABLED 0 117#define XHCI_EPCTX_0_EPSTATE_RUNNING 1 118#define XHCI_EPCTX_0_EPSTATE_HALTED 2 119#define XHCI_EPCTX_0_EPSTATE_STOPPED 3 120#define XHCI_EPCTX_0_EPSTATE_ERROR 4 121#define XHCI_EPCTX_0_EPSTATE_RESERVED_5 5 122#define XHCI_EPCTX_0_EPSTATE_RESERVED_6 6 123#define XHCI_EPCTX_0_EPSTATE_RESERVED_7 7 124#define XHCI_EPCTX_0_MULT_SET(x) (((x) & 0x3) << 8) 125#define XHCI_EPCTX_0_MULT_GET(x) (((x) >> 8) & 0x3) 126#define XHCI_EPCTX_0_MAXP_STREAMS_SET(x) (((x) & 0x1F) << 10) 127#define XHCI_EPCTX_0_MAXP_STREAMS_GET(x) (((x) >> 10) & 0x1F) 128#define XHCI_EPCTX_0_LSA_SET(x) (((x) & 0x1) << 15) 129#define XHCI_EPCTX_0_LSA_GET(x) (((x) >> 15) & 0x1) 130#define XHCI_EPCTX_0_IVAL_SET(x) (((x) & 0xFF) << 16) 131#define XHCI_EPCTX_0_IVAL_GET(x) (((x) >> 16) & 0xFF) 132 volatile uint32_t dwEpCtx1; 133#define XHCI_EPCTX_1_CERR_SET(x) (((x) & 0x3) << 1) 134#define XHCI_EPCTX_1_CERR_GET(x) (((x) >> 1) & 0x3) 135#define XHCI_EPCTX_1_EPTYPE_SET(x) (((x) & 0x7) << 3) 136#define XHCI_EPCTX_1_EPTYPE_GET(x) (((x) >> 3) & 0x7) 137#define XHCI_EPCTX_1_HID_SET(x) (((x) & 0x1) << 7) 138#define XHCI_EPCTX_1_HID_GET(x) (((x) >> 7) & 0x1) 139#define XHCI_EPCTX_1_MAXB_SET(x) (((x) & 0xFF) << 8) 140#define XHCI_EPCTX_1_MAXB_GET(x) (((x) >> 8) & 0xFF) 141#define XHCI_EPCTX_1_MAXP_SIZE_SET(x) (((x) & 0xFFFF) << 16) 142#define XHCI_EPCTX_1_MAXP_SIZE_GET(x) (((x) >> 16) & 0xFFFF) 143 volatile uint64_t qwEpCtx2; 144#define XHCI_EPCTX_2_DCS_SET(x) ((x) & 0x1) 145#define XHCI_EPCTX_2_DCS_GET(x) ((x) & 0x1) 146#define XHCI_EPCTX_2_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U 147 volatile uint32_t dwEpCtx4; 148#define XHCI_EPCTX_4_AVG_TRB_LEN_SET(x) ((x) & 0xFFFF) 149#define XHCI_EPCTX_4_AVG_TRB_LEN_GET(x) ((x) & 0xFFFF) 150#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x) (((x) & 0xFFFF) << 16) 151#define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET(x) (((x) >> 16) & 0xFFFF) 152 volatile uint32_t dwEpCtx5; 153 volatile uint32_t dwEpCtx6; 154 volatile uint32_t dwEpCtx7; 155}; 156 157struct xhci_input_ctx { 158#define XHCI_INCTX_NON_CTRL_MASK 0xFFFFFFFCU 159 volatile uint32_t dwInCtx0; 160#define XHCI_INCTX_0_DROP_MASK(n) (1U << (n)) 161 volatile uint32_t dwInCtx1; 162#define XHCI_INCTX_1_ADD_MASK(n) (1U << (n)) 163 volatile uint32_t dwInCtx2; 164 volatile uint32_t dwInCtx3; 165 volatile uint32_t dwInCtx4; 166 volatile uint32_t dwInCtx5; 167 volatile uint32_t dwInCtx6; 168 volatile uint32_t dwInCtx7; 169}; 170 171struct xhci_input_dev_ctx { 172 struct xhci_input_ctx ctx_input; 173 struct xhci_slot_ctx ctx_slot; 174 struct xhci_endp_ctx ctx_ep[XHCI_MAX_ENDPOINTS - 1]; 175}; 176 177struct xhci_dev_ctx { 178 struct xhci_slot_ctx ctx_slot; 179 struct xhci_endp_ctx ctx_ep[XHCI_MAX_ENDPOINTS - 1]; 180} __aligned(XHCI_DEV_CTX_ALIGN); 181 182struct xhci_stream_ctx { 183 volatile uint64_t qwSctx0; 184#define XHCI_SCTX_0_DCS_GET(x) ((x) & 0x1) 185#define XHCI_SCTX_0_DCS_SET(x) ((x) & 0x1) 186#define XHCI_SCTX_0_SCT_SET(x) (((x) & 0x7) << 1) 187#define XHCI_SCTX_0_SCT_GET(x) (((x) >> 1) & 0x7) 188#define XHCI_SCTX_0_SCT_SEC_TR_RING 0x0 189#define XHCI_SCTX_0_SCT_PRIM_TR_RING 0x1 190#define XHCI_SCTX_0_SCT_PRIM_SSA_8 0x2 191#define XHCI_SCTX_0_SCT_PRIM_SSA_16 0x3 192#define XHCI_SCTX_0_SCT_PRIM_SSA_32 0x4 193#define XHCI_SCTX_0_SCT_PRIM_SSA_64 0x5 194#define XHCI_SCTX_0_SCT_PRIM_SSA_128 0x6 195#define XHCI_SCTX_0_SCT_PRIM_SSA_256 0x7 196#define XHCI_SCTX_0_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U 197 volatile uint32_t dwSctx2; 198 volatile uint32_t dwSctx3; 199}; 200 201struct xhci_trb { 202 volatile uint64_t qwTrb0; 203#define XHCI_TRB_0_DIR_IN_MASK (0x80ULL << 0) 204#define XHCI_TRB_0_WLENGTH_MASK (0xFFFFULL << 48) 205 volatile uint32_t dwTrb2; 206#define XHCI_TRB_2_ERROR_GET(x) (((x) >> 24) & 0xFF) 207#define XHCI_TRB_2_ERROR_SET(x) (((x) & 0xFF) << 24) 208#define XHCI_TRB_2_TDSZ_GET(x) (((x) >> 17) & 0x1F) 209#define XHCI_TRB_2_TDSZ_SET(x) (((x) & 0x1F) << 17) 210#define XHCI_TRB_2_REM_GET(x) ((x) & 0xFFFFFF) 211#define XHCI_TRB_2_REM_SET(x) ((x) & 0xFFFFFF) 212#define XHCI_TRB_2_BYTES_GET(x) ((x) & 0x1FFFF) 213#define XHCI_TRB_2_BYTES_SET(x) ((x) & 0x1FFFF) 214#define XHCI_TRB_2_IRQ_GET(x) (((x) >> 22) & 0x3FF) 215#define XHCI_TRB_2_IRQ_SET(x) (((x) & 0x3FF) << 22) 216#define XHCI_TRB_2_STREAM_GET(x) (((x) >> 16) & 0xFFFF) 217#define XHCI_TRB_2_STREAM_SET(x) (((x) & 0xFFFF) << 16) 218 219 volatile uint32_t dwTrb3; 220#define XHCI_TRB_3_TYPE_GET(x) (((x) >> 10) & 0x3F) 221#define XHCI_TRB_3_TYPE_SET(x) (((x) & 0x3F) << 10) 222#define XHCI_TRB_3_CYCLE_BIT (1U << 0) 223#define XHCI_TRB_3_TC_BIT (1U << 1) /* command ring only */ 224#define XHCI_TRB_3_ENT_BIT (1U << 1) /* transfer ring only */ 225#define XHCI_TRB_3_ISP_BIT (1U << 2) 226#define XHCI_TRB_3_NSNOOP_BIT (1U << 3) 227#define XHCI_TRB_3_CHAIN_BIT (1U << 4) 228#define XHCI_TRB_3_IOC_BIT (1U << 5) 229#define XHCI_TRB_3_IDT_BIT (1U << 6) 230#define XHCI_TRB_3_TBC_GET(x) (((x) >> 7) & 3) 231#define XHCI_TRB_3_TBC_SET(x) (((x) & 3) << 7) 232#define XHCI_TRB_3_BEI_BIT (1U << 9) 233#define XHCI_TRB_3_DCEP_BIT (1U << 9) 234#define XHCI_TRB_3_PRSV_BIT (1U << 9) 235#define XHCI_TRB_3_BSR_BIT (1U << 9) 236#define XHCI_TRB_3_TRT_MASK (3U << 16) 237#define XHCI_TRB_3_TRT_NONE (0U << 16) 238#define XHCI_TRB_3_TRT_OUT (2U << 16) 239#define XHCI_TRB_3_TRT_IN (3U << 16) 240#define XHCI_TRB_3_DIR_IN (1U << 16) 241#define XHCI_TRB_3_TLBPC_GET(x) (((x) >> 16) & 0xF) 242#define XHCI_TRB_3_TLBPC_SET(x) (((x) & 0xF) << 16) 243#define XHCI_TRB_3_EP_GET(x) (((x) >> 16) & 0x1F) 244#define XHCI_TRB_3_EP_SET(x) (((x) & 0x1F) << 16) 245#define XHCI_TRB_3_FRID_GET(x) (((x) >> 20) & 0x7FF) 246#define XHCI_TRB_3_FRID_SET(x) (((x) & 0x7FF) << 20) 247#define XHCI_TRB_3_ISO_SIA_BIT (1U << 31) 248#define XHCI_TRB_3_SUSP_EP_BIT (1U << 23) 249#define XHCI_TRB_3_SLOT_GET(x) (((x) >> 24) & 0xFF) 250#define XHCI_TRB_3_SLOT_SET(x) (((x) & 0xFF) << 24) 251 252/* Commands */ 253#define XHCI_TRB_TYPE_RESERVED 0x00 254#define XHCI_TRB_TYPE_NORMAL 0x01 255#define XHCI_TRB_TYPE_SETUP_STAGE 0x02 256#define XHCI_TRB_TYPE_DATA_STAGE 0x03 257#define XHCI_TRB_TYPE_STATUS_STAGE 0x04 258#define XHCI_TRB_TYPE_ISOCH 0x05 259#define XHCI_TRB_TYPE_LINK 0x06 260#define XHCI_TRB_TYPE_EVENT_DATA 0x07 261#define XHCI_TRB_TYPE_NOOP 0x08 262#define XHCI_TRB_TYPE_ENABLE_SLOT 0x09 263#define XHCI_TRB_TYPE_DISABLE_SLOT 0x0A 264#define XHCI_TRB_TYPE_ADDRESS_DEVICE 0x0B 265#define XHCI_TRB_TYPE_CONFIGURE_EP 0x0C 266#define XHCI_TRB_TYPE_EVALUATE_CTX 0x0D 267#define XHCI_TRB_TYPE_RESET_EP 0x0E 268#define XHCI_TRB_TYPE_STOP_EP 0x0F 269#define XHCI_TRB_TYPE_SET_TR_DEQUEUE 0x10 270#define XHCI_TRB_TYPE_RESET_DEVICE 0x11 271#define XHCI_TRB_TYPE_FORCE_EVENT 0x12 272#define XHCI_TRB_TYPE_NEGOTIATE_BW 0x13 273#define XHCI_TRB_TYPE_SET_LATENCY_TOL 0x14 274#define XHCI_TRB_TYPE_GET_PORT_BW 0x15 275#define XHCI_TRB_TYPE_FORCE_HEADER 0x16 276#define XHCI_TRB_TYPE_NOOP_CMD 0x17 277 278/* Events */ 279#define XHCI_TRB_EVENT_TRANSFER 0x20 280#define XHCI_TRB_EVENT_CMD_COMPLETE 0x21 281#define XHCI_TRB_EVENT_PORT_STS_CHANGE 0x22 282#define XHCI_TRB_EVENT_BW_REQUEST 0x23 283#define XHCI_TRB_EVENT_DOORBELL 0x24 284#define XHCI_TRB_EVENT_HOST_CTRL 0x25 285#define XHCI_TRB_EVENT_DEVICE_NOTIFY 0x26 286#define XHCI_TRB_EVENT_MFINDEX_WRAP 0x27 287 288/* Error codes */ 289#define XHCI_TRB_ERROR_INVALID 0x00 290#define XHCI_TRB_ERROR_SUCCESS 0x01 291#define XHCI_TRB_ERROR_DATA_BUF 0x02 292#define XHCI_TRB_ERROR_BABBLE 0x03 293#define XHCI_TRB_ERROR_XACT 0x04 294#define XHCI_TRB_ERROR_TRB 0x05 295#define XHCI_TRB_ERROR_STALL 0x06 296#define XHCI_TRB_ERROR_RESOURCE 0x07 297#define XHCI_TRB_ERROR_BANDWIDTH 0x08 298#define XHCI_TRB_ERROR_NO_SLOTS 0x09 299#define XHCI_TRB_ERROR_STREAM_TYPE 0x0A 300#define XHCI_TRB_ERROR_SLOT_NOT_ON 0x0B 301#define XHCI_TRB_ERROR_ENDP_NOT_ON 0x0C 302#define XHCI_TRB_ERROR_SHORT_PKT 0x0D 303#define XHCI_TRB_ERROR_RING_UNDERRUN 0x0E 304#define XHCI_TRB_ERROR_RING_OVERRUN 0x0F 305#define XHCI_TRB_ERROR_VF_RING_FULL 0x10 306#define XHCI_TRB_ERROR_PARAMETER 0x11 307#define XHCI_TRB_ERROR_BW_OVERRUN 0x12 308#define XHCI_TRB_ERROR_CONTEXT_STATE 0x13 309#define XHCI_TRB_ERROR_NO_PING_RESP 0x14 310#define XHCI_TRB_ERROR_EV_RING_FULL 0x15 311#define XHCI_TRB_ERROR_INCOMPAT_DEV 0x16 312#define XHCI_TRB_ERROR_MISSED_SERVICE 0x17 313#define XHCI_TRB_ERROR_CMD_RING_STOP 0x18 314#define XHCI_TRB_ERROR_CMD_ABORTED 0x19 315#define XHCI_TRB_ERROR_STOPPED 0x1A 316#define XHCI_TRB_ERROR_LENGTH 0x1B 317#define XHCI_TRB_ERROR_BAD_MELAT 0x1D 318#define XHCI_TRB_ERROR_ISOC_OVERRUN 0x1F 319#define XHCI_TRB_ERROR_EVENT_LOST 0x20 320#define XHCI_TRB_ERROR_UNDEFINED 0x21 321#define XHCI_TRB_ERROR_INVALID_SID 0x22 322#define XHCI_TRB_ERROR_SEC_BW 0x23 323#define XHCI_TRB_ERROR_SPLIT_XACT 0x24 324} __aligned(4); 325 326struct xhci_dev_endpoint_trbs { 327 struct xhci_trb trb[(XHCI_MAX_STREAMS * 328 XHCI_MAX_TRANSFERS) + XHCI_MAX_STREAMS]; 329}; 330 331#if (USB_PAGE_SIZE < 4096) 332#error "The XHCI driver needs a pagesize above or equal to 4K" 333#endif 334 335/* Define the maximum payload which we will handle in a single TRB */ 336#define XHCI_TD_PAYLOAD_MAX 65536 /* bytes */ 337 338/* Define the maximum payload of a single scatter-gather list element */ 339#define XHCI_TD_PAGE_SIZE \ 340 ((USB_PAGE_SIZE < XHCI_TD_PAYLOAD_MAX) ? USB_PAGE_SIZE : XHCI_TD_PAYLOAD_MAX) 341 342/* Define the maximum length of the scatter-gather list */ 343#define XHCI_TD_PAGE_NBUF \ 344 (((XHCI_TD_PAYLOAD_MAX + XHCI_TD_PAGE_SIZE - 1) / XHCI_TD_PAGE_SIZE) + 1) 345 346struct xhci_td { 347 /* one LINK TRB has been added to the TRB array */ 348 struct xhci_trb td_trb[XHCI_TD_PAGE_NBUF + 1]; 349 350/* 351 * Extra information needed: 352 */ 353 uint64_t td_self; 354 struct xhci_td *next; 355 struct xhci_td *alt_next; 356 struct xhci_td *obj_next; 357 struct usb_page_cache *page_cache; 358 uint32_t len; 359 uint32_t remainder; 360 uint8_t ntrb; 361 uint8_t status; 362} __aligned(XHCI_TRB_ALIGN); 363 364struct xhci_command { 365 struct xhci_trb trb; 366 TAILQ_ENTRY(xhci_command) entry; 367}; 368 369struct xhci_event_ring_seg { 370 volatile uint64_t qwEvrsTablePtr; 371 volatile uint32_t dwEvrsTableSize; 372 volatile uint32_t dwEvrsReserved; 373}; 374 375struct xhci_hw_root { 376 struct xhci_event_ring_seg hwr_ring_seg[XHCI_MAX_RSEG]; 377 struct { 378 volatile uint64_t dummy; 379 } __aligned(64) padding; 380 struct xhci_trb hwr_events[XHCI_MAX_EVENTS]; 381 struct xhci_trb hwr_commands[XHCI_MAX_COMMANDS]; 382}; 383 384struct xhci_endpoint_ext { 385 struct xhci_trb *trb; 386 struct usb_xfer *xfer[XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS]; 387 struct usb_page_cache *page_cache; 388 uint64_t physaddr; 389 uint8_t trb_used[XHCI_MAX_STREAMS]; 390 uint8_t trb_index[XHCI_MAX_STREAMS]; 391 uint8_t trb_halted; 392 uint8_t trb_running; 393 uint8_t trb_ep_mode; 394 uint8_t trb_ep_maxp; 395}; 396 397enum { 398 XHCI_ST_DISABLED, 399 XHCI_ST_ENABLED, 400 XHCI_ST_DEFAULT, 401 XHCI_ST_ADDRESSED, 402 XHCI_ST_CONFIGURED, 403 XHCI_ST_MAX 404}; 405 406struct xhci_hw_dev { 407 struct usb_page_cache device_pc; 408 struct usb_page_cache input_pc; 409 struct usb_page_cache endpoint_pc[XHCI_MAX_ENDPOINTS]; 410 411 struct usb_page device_pg; 412 struct usb_page input_pg; 413 struct usb_page endpoint_pg[XHCI_MAX_ENDPOINTS]; 414 415 struct xhci_endpoint_ext endp[XHCI_MAX_ENDPOINTS]; 416 417 uint32_t ep_configured; 418 419 uint8_t state; 420 uint8_t nports; 421 uint8_t tt; 422 uint8_t context_num; 423}; 424 425struct xhci_hw_softc { 426 struct usb_page_cache root_pc; 427 struct usb_page_cache ctx_pc; 428 struct usb_page_cache scratch_pc[XHCI_MAX_SCRATCHPADS]; 429 430 struct usb_page root_pg; 431 struct usb_page ctx_pg; 432 struct usb_page scratch_pg[XHCI_MAX_SCRATCHPADS]; 433 434 struct xhci_hw_dev devs[XHCI_MAX_DEVICES + 1]; 435}; 436 437struct xhci_config_desc { 438 struct usb_config_descriptor confd; 439 struct usb_interface_descriptor ifcd; 440 struct usb_endpoint_descriptor endpd; 441 struct usb_endpoint_ss_comp_descriptor endpcd; 442} __packed; 443 444struct xhci_bos_desc { 445 struct usb_bos_descriptor bosd; 446 struct usb_devcap_usb2ext_descriptor usb2extd; 447 struct usb_devcap_ss_descriptor usbdcd; 448 struct usb_devcap_container_id_descriptor cidd; 449} __packed; 450 451union xhci_hub_desc { 452 struct usb_status stat; 453 struct usb_port_status ps; 454 struct usb_hub_ss_descriptor hubd; 455 uint8_t temp[128]; 456}; 457 458typedef int (xhci_port_route_t)(device_t, uint32_t, uint32_t); 459 460struct xhci_softc { 461 struct xhci_hw_softc sc_hw; 462 /* base device */ 463 struct usb_bus sc_bus; 464 /* configure message */ 465 struct usb_bus_msg sc_config_msg[2]; 466 467 struct usb_callout sc_callout; 468 469 xhci_port_route_t *sc_port_route; 470 471 union xhci_hub_desc sc_hub_desc; 472 473 struct cv sc_cmd_cv; 474 struct sx sc_cmd_sx; 475 476 struct usb_device *sc_devices[XHCI_MAX_DEVICES]; 477 struct resource *sc_io_res; 478 struct resource *sc_irq_res; 479 struct resource *sc_msix_res; 480 481 void *sc_intr_hdl; 482 bus_size_t sc_io_size; 483 bus_space_tag_t sc_io_tag; 484 bus_space_handle_t sc_io_hdl; 485 /* last pending command address */ 486 uint64_t sc_cmd_addr; 487 /* result of command */ 488 uint32_t sc_cmd_result[2]; 489 /* copy of cmd register */ 490 uint32_t sc_cmd; 491 /* worst case exit latency */ 492 uint32_t sc_exit_lat_max; 493 494 /* offset to operational registers */ 495 uint32_t sc_oper_off; 496 /* offset to capability registers */ 497 uint32_t sc_capa_off; 498 /* offset to runtime registers */ 499 uint32_t sc_runt_off; 500 /* offset to doorbell registers */ 501 uint32_t sc_door_off; 502 503 /* chip specific */ 504 uint16_t sc_erst_max; 505 uint16_t sc_event_idx; 506 uint16_t sc_command_idx; 507 uint16_t sc_imod_default; 508 509 /* number of scratch pages */ 510 uint16_t sc_noscratch; 511 512 uint8_t sc_event_ccs; 513 uint8_t sc_command_ccs; 514 /* number of XHCI device slots */ 515 uint8_t sc_noslot; 516 /* number of ports on root HUB */ 517 uint8_t sc_noport; 518 /* root HUB device configuration */ 519 uint8_t sc_conf; 520 /* step status stage of all control transfers */ 521 uint8_t sc_ctlstep; 522 /* root HUB port event bitmap, max 256 ports */ 523 uint8_t sc_hub_idata[32]; 524 525 /* size of context */ 526 uint8_t sc_ctx_is_64_byte; 527 528 /* vendor string for root HUB */ 529 char sc_vendor[16]; 530}; 531 532#define XHCI_CMD_LOCK(sc) sx_xlock(&(sc)->sc_cmd_sx) 533#define XHCI_CMD_UNLOCK(sc) sx_xunlock(&(sc)->sc_cmd_sx) 534#define XHCI_CMD_ASSERT_LOCKED(sc) sx_assert(&(sc)->sc_cmd_sx, SA_LOCKED) 535 536/* prototypes */ 537 538uint8_t xhci_use_polling(void); 539usb_error_t xhci_halt_controller(struct xhci_softc *); 540usb_error_t xhci_reset_controller(struct xhci_softc *); 541usb_error_t xhci_init(struct xhci_softc *, device_t, uint8_t); 542usb_error_t xhci_start_controller(struct xhci_softc *); 543void xhci_interrupt(struct xhci_softc *); 544void xhci_uninit(struct xhci_softc *); 545 546#endif /* _XHCI_H_ */ 547