1/* $FreeBSD$ */ 2/*- 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Lennart Augustsson (lennart@augustsson.net) at 8 * Carlstedt Research & Technology. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#ifndef _UHCIREG_H_ 33#define _UHCIREG_H_ 34 35#define PCI_UHCI_BASE_REG 0x20 36 37/* PCI config registers */ 38#define PCI_USBREV 0x60 /* USB protocol revision */ 39#define PCI_USB_REV_MASK 0xff 40#define PCI_USB_REV_PRE_1_0 0x00 41#define PCI_USB_REV_1_0 0x10 42#define PCI_USB_REV_1_1 0x11 43#define PCI_LEGSUP 0xc0 /* Legacy Support register */ 44#define PCI_LEGSUP_USBPIRQDEN 0x2000 /* USB PIRQ D Enable */ 45#define PCI_CBIO 0x20 /* configuration base IO */ 46#define PCI_INTERFACE_UHCI 0x00 47 48/* UHCI registers */ 49#define UHCI_CMD 0x00 50#define UHCI_CMD_RS 0x0001 51#define UHCI_CMD_HCRESET 0x0002 52#define UHCI_CMD_GRESET 0x0004 53#define UHCI_CMD_EGSM 0x0008 54#define UHCI_CMD_FGR 0x0010 55#define UHCI_CMD_SWDBG 0x0020 56#define UHCI_CMD_CF 0x0040 57#define UHCI_CMD_MAXP 0x0080 58#define UHCI_STS 0x02 59#define UHCI_STS_USBINT 0x0001 60#define UHCI_STS_USBEI 0x0002 61#define UHCI_STS_RD 0x0004 62#define UHCI_STS_HSE 0x0008 63#define UHCI_STS_HCPE 0x0010 64#define UHCI_STS_HCH 0x0020 65#define UHCI_STS_ALLINTRS 0x003f 66#define UHCI_INTR 0x04 67#define UHCI_INTR_TOCRCIE 0x0001 68#define UHCI_INTR_RIE 0x0002 69#define UHCI_INTR_IOCE 0x0004 70#define UHCI_INTR_SPIE 0x0008 71#define UHCI_FRNUM 0x06 72#define UHCI_FRNUM_MASK 0x03ff 73#define UHCI_FLBASEADDR 0x08 74#define UHCI_SOF 0x0c 75#define UHCI_SOF_MASK 0x7f 76#define UHCI_PORTSC1 0x010 77#define UHCI_PORTSC2 0x012 78#define UHCI_PORTSC_CCS 0x0001 79#define UHCI_PORTSC_CSC 0x0002 80#define UHCI_PORTSC_PE 0x0004 81#define UHCI_PORTSC_POEDC 0x0008 82#define UHCI_PORTSC_LS 0x0030 83#define UHCI_PORTSC_LS_SHIFT 4 84#define UHCI_PORTSC_RD 0x0040 85#define UHCI_PORTSC_LSDA 0x0100 86#define UHCI_PORTSC_PR 0x0200 87#define UHCI_PORTSC_OCI 0x0400 88#define UHCI_PORTSC_OCIC 0x0800 89#define UHCI_PORTSC_SUSP 0x1000 90 91#define URWMASK(x) ((x) & (UHCI_PORTSC_SUSP | \ 92 UHCI_PORTSC_PR | UHCI_PORTSC_RD | \ 93 UHCI_PORTSC_PE)) 94 95#endif /* _UHCIREG_H_ */ 96