ehci.c revision 221073
1/*-
2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
3 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved.
4 * Copyright (c) 2004 Lennart Augustsson. All rights reserved.
5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29/*
30 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
31 *
32 * The EHCI 0.96 spec can be found at
33 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf
34 * The EHCI 1.0 spec can be found at
35 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf
36 * and the USB 2.0 spec at
37 * http://www.usb.org/developers/docs/usb_20.zip
38 *
39 */
40
41/*
42 * TODO:
43 * 1) command failures are not recovered correctly
44 */
45
46#include <sys/cdefs.h>
47__FBSDID("$FreeBSD: head/sys/dev/usb/controller/ehci.c 221073 2011-04-26 18:50:35Z hselasky $");
48
49#include <sys/stdint.h>
50#include <sys/stddef.h>
51#include <sys/param.h>
52#include <sys/queue.h>
53#include <sys/types.h>
54#include <sys/systm.h>
55#include <sys/kernel.h>
56#include <sys/bus.h>
57#include <sys/module.h>
58#include <sys/lock.h>
59#include <sys/mutex.h>
60#include <sys/condvar.h>
61#include <sys/sysctl.h>
62#include <sys/sx.h>
63#include <sys/unistd.h>
64#include <sys/callout.h>
65#include <sys/malloc.h>
66#include <sys/priv.h>
67
68#include <dev/usb/usb.h>
69#include <dev/usb/usbdi.h>
70
71#define	USB_DEBUG_VAR ehcidebug
72
73#include <dev/usb/usb_core.h>
74#include <dev/usb/usb_debug.h>
75#include <dev/usb/usb_busdma.h>
76#include <dev/usb/usb_process.h>
77#include <dev/usb/usb_transfer.h>
78#include <dev/usb/usb_device.h>
79#include <dev/usb/usb_hub.h>
80#include <dev/usb/usb_util.h>
81
82#include <dev/usb/usb_controller.h>
83#include <dev/usb/usb_bus.h>
84#include <dev/usb/controller/ehci.h>
85#include <dev/usb/controller/ehcireg.h>
86
87#define	EHCI_BUS2SC(bus) \
88   ((ehci_softc_t *)(((uint8_t *)(bus)) - \
89    ((uint8_t *)&(((ehci_softc_t *)0)->sc_bus))))
90
91#ifdef USB_DEBUG
92static int ehcidebug = 0;
93static int ehcinohighspeed = 0;
94static int ehciiaadbug = 0;
95static int ehcilostintrbug = 0;
96
97SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci");
98SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RW,
99    &ehcidebug, 0, "Debug level");
100SYSCTL_INT(_hw_usb_ehci, OID_AUTO, no_hs, CTLFLAG_RW,
101    &ehcinohighspeed, 0, "Disable High Speed USB");
102SYSCTL_INT(_hw_usb_ehci, OID_AUTO, iaadbug, CTLFLAG_RW,
103    &ehciiaadbug, 0, "Enable doorbell bug workaround");
104SYSCTL_INT(_hw_usb_ehci, OID_AUTO, lostintrbug, CTLFLAG_RW,
105    &ehcilostintrbug, 0, "Enable lost interrupt bug workaround");
106
107TUNABLE_INT("hw.usb.ehci.debug", &ehcidebug);
108TUNABLE_INT("hw.usb.ehci.no_hs", &ehcinohighspeed);
109TUNABLE_INT("hw.usb.ehci.iaadbug", &ehciiaadbug);
110TUNABLE_INT("hw.usb.ehci.lostintrbug", &ehcilostintrbug);
111
112static void ehci_dump_regs(ehci_softc_t *sc);
113static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh);
114
115#endif
116
117#define	EHCI_INTR_ENDPT 1
118
119extern struct usb_bus_methods ehci_bus_methods;
120extern struct usb_pipe_methods ehci_device_bulk_methods;
121extern struct usb_pipe_methods ehci_device_ctrl_methods;
122extern struct usb_pipe_methods ehci_device_intr_methods;
123extern struct usb_pipe_methods ehci_device_isoc_fs_methods;
124extern struct usb_pipe_methods ehci_device_isoc_hs_methods;
125
126static void ehci_do_poll(struct usb_bus *);
127static void ehci_device_done(struct usb_xfer *, usb_error_t);
128static uint8_t ehci_check_transfer(struct usb_xfer *);
129static void ehci_timeout(void *);
130static void ehci_poll_timeout(void *);
131
132static void ehci_root_intr(ehci_softc_t *sc);
133
134struct ehci_std_temp {
135	ehci_softc_t *sc;
136	struct usb_page_cache *pc;
137	ehci_qtd_t *td;
138	ehci_qtd_t *td_next;
139	uint32_t average;
140	uint32_t qtd_status;
141	uint32_t len;
142	uint16_t max_frame_size;
143	uint8_t	shortpkt;
144	uint8_t	auto_data_toggle;
145	uint8_t	setup_alt_next;
146	uint8_t	last_frame;
147};
148
149void
150ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
151{
152	ehci_softc_t *sc = EHCI_BUS2SC(bus);
153	uint32_t i;
154
155	cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg,
156	    sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN);
157
158	cb(bus, &sc->sc_hw.terminate_pc, &sc->sc_hw.terminate_pg,
159	    sizeof(struct ehci_qh_sub), EHCI_QH_ALIGN);
160
161	cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg,
162	    sizeof(ehci_qh_t), EHCI_QH_ALIGN);
163
164	for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
165		cb(bus, sc->sc_hw.intr_start_pc + i,
166		    sc->sc_hw.intr_start_pg + i,
167		    sizeof(ehci_qh_t), EHCI_QH_ALIGN);
168	}
169
170	for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
171		cb(bus, sc->sc_hw.isoc_hs_start_pc + i,
172		    sc->sc_hw.isoc_hs_start_pg + i,
173		    sizeof(ehci_itd_t), EHCI_ITD_ALIGN);
174	}
175
176	for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
177		cb(bus, sc->sc_hw.isoc_fs_start_pc + i,
178		    sc->sc_hw.isoc_fs_start_pg + i,
179		    sizeof(ehci_sitd_t), EHCI_SITD_ALIGN);
180	}
181}
182
183usb_error_t
184ehci_reset(ehci_softc_t *sc)
185{
186	uint32_t hcr;
187	int i;
188
189	EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
190	for (i = 0; i < 100; i++) {
191		usb_pause_mtx(NULL, hz / 1000);
192		hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
193		if (!hcr) {
194			if (sc->sc_flags & (EHCI_SCFLG_SETMODE | EHCI_SCFLG_BIGEMMIO)) {
195				/*
196				 * Force USBMODE as requested.  Controllers
197				 * may have multiple operating modes.
198				 */
199				uint32_t usbmode = EOREAD4(sc, EHCI_USBMODE);
200				if (sc->sc_flags & EHCI_SCFLG_SETMODE) {
201					usbmode = (usbmode &~ EHCI_UM_CM) | EHCI_UM_CM_HOST;
202					device_printf(sc->sc_bus.bdev,
203					    "set host controller mode\n");
204				}
205				if (sc->sc_flags & EHCI_SCFLG_BIGEMMIO) {
206					usbmode = (usbmode &~ EHCI_UM_ES) | EHCI_UM_ES_BE;
207					device_printf(sc->sc_bus.bdev,
208					    "set big-endian mode\n");
209				}
210				EOWRITE4(sc,  EHCI_USBMODE, usbmode);
211			}
212			return (0);
213		}
214	}
215	device_printf(sc->sc_bus.bdev, "reset timeout\n");
216	return (USB_ERR_IOERROR);
217}
218
219static usb_error_t
220ehci_hcreset(ehci_softc_t *sc)
221{
222	uint32_t hcr;
223	int i;
224
225	EOWRITE4(sc, EHCI_USBCMD, 0);	/* Halt controller */
226	for (i = 0; i < 100; i++) {
227		usb_pause_mtx(NULL, hz / 1000);
228		hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
229		if (hcr)
230			break;
231	}
232	if (!hcr)
233		/*
234                 * Fall through and try reset anyway even though
235                 * Table 2-9 in the EHCI spec says this will result
236                 * in undefined behavior.
237                 */
238		device_printf(sc->sc_bus.bdev, "stop timeout\n");
239
240	return ehci_reset(sc);
241}
242
243usb_error_t
244ehci_init(ehci_softc_t *sc)
245{
246	struct usb_page_search buf_res;
247	uint32_t version;
248	uint32_t sparams;
249	uint32_t cparams;
250	uint32_t hcr;
251	uint16_t i;
252	uint16_t x;
253	uint16_t y;
254	uint16_t bit;
255	usb_error_t err = 0;
256
257	DPRINTF("start\n");
258
259	usb_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0);
260	usb_callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_mtx, 0);
261
262	sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
263
264#ifdef USB_DEBUG
265	if (ehciiaadbug)
266		sc->sc_flags |= EHCI_SCFLG_IAADBUG;
267	if (ehcilostintrbug)
268		sc->sc_flags |= EHCI_SCFLG_LOSTINTRBUG;
269	if (ehcidebug > 2) {
270		ehci_dump_regs(sc);
271	}
272#endif
273
274	version = EHCI_HCIVERSION(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
275	device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n",
276	    version >> 8, version & 0xff);
277
278	sparams = EREAD4(sc, EHCI_HCSPARAMS);
279	DPRINTF("sparams=0x%x\n", sparams);
280
281	sc->sc_noport = EHCI_HCS_N_PORTS(sparams);
282	cparams = EREAD4(sc, EHCI_HCCPARAMS);
283	DPRINTF("cparams=0x%x\n", cparams);
284
285	if (EHCI_HCC_64BIT(cparams)) {
286		DPRINTF("HCC uses 64-bit structures\n");
287
288		/* MUST clear segment register if 64 bit capable */
289		EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
290	}
291	sc->sc_bus.usbrev = USB_REV_2_0;
292
293	/* Reset the controller */
294	DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev));
295
296	err = ehci_hcreset(sc);
297	if (err) {
298		device_printf(sc->sc_bus.bdev, "reset timeout\n");
299		return (err);
300	}
301	/*
302	 * use current frame-list-size selection 0: 1024*4 bytes 1:  512*4
303	 * bytes 2:  256*4 bytes 3:      unknown
304	 */
305	if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) {
306		device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n");
307		return (USB_ERR_IOERROR);
308	}
309	/* set up the bus struct */
310	sc->sc_bus.methods = &ehci_bus_methods;
311
312	sc->sc_eintrs = EHCI_NORMAL_INTRS;
313
314	if (1) {
315		struct ehci_qh_sub *qh;
316
317		usbd_get_page(&sc->sc_hw.terminate_pc, 0, &buf_res);
318
319		qh = buf_res.buffer;
320
321		sc->sc_terminate_self = htohc32(sc, buf_res.physaddr);
322
323		/* init terminate TD */
324		qh->qtd_next =
325		    htohc32(sc, EHCI_LINK_TERMINATE);
326		qh->qtd_altnext =
327		    htohc32(sc, EHCI_LINK_TERMINATE);
328		qh->qtd_status =
329		    htohc32(sc, EHCI_QTD_HALTED);
330	}
331
332	for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
333		ehci_qh_t *qh;
334
335		usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res);
336
337		qh = buf_res.buffer;
338
339		/* initialize page cache pointer */
340
341		qh->page_cache = sc->sc_hw.intr_start_pc + i;
342
343		/* store a pointer to queue head */
344
345		sc->sc_intr_p_last[i] = qh;
346
347		qh->qh_self =
348		    htohc32(sc, buf_res.physaddr) |
349		    htohc32(sc, EHCI_LINK_QH);
350
351		qh->qh_endp =
352		    htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH));
353		qh->qh_endphub =
354		    htohc32(sc, EHCI_QH_SET_MULT(1));
355		qh->qh_curqtd = 0;
356
357		qh->qh_qtd.qtd_next =
358		    htohc32(sc, EHCI_LINK_TERMINATE);
359		qh->qh_qtd.qtd_altnext =
360		    htohc32(sc, EHCI_LINK_TERMINATE);
361		qh->qh_qtd.qtd_status =
362		    htohc32(sc, EHCI_QTD_HALTED);
363	}
364
365	/*
366	 * the QHs are arranged to give poll intervals that are
367	 * powers of 2 times 1ms
368	 */
369	bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
370	while (bit) {
371		x = bit;
372		while (x & bit) {
373			ehci_qh_t *qh_x;
374			ehci_qh_t *qh_y;
375
376			y = (x ^ bit) | (bit / 2);
377
378			qh_x = sc->sc_intr_p_last[x];
379			qh_y = sc->sc_intr_p_last[y];
380
381			/*
382			 * the next QH has half the poll interval
383			 */
384			qh_x->qh_link = qh_y->qh_self;
385
386			x++;
387		}
388		bit >>= 1;
389	}
390
391	if (1) {
392		ehci_qh_t *qh;
393
394		qh = sc->sc_intr_p_last[0];
395
396		/* the last (1ms) QH terminates */
397		qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE);
398	}
399	for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
400		ehci_sitd_t *sitd;
401		ehci_itd_t *itd;
402
403		usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res);
404
405		sitd = buf_res.buffer;
406
407		/* initialize page cache pointer */
408
409		sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i;
410
411		/* store a pointer to the transfer descriptor */
412
413		sc->sc_isoc_fs_p_last[i] = sitd;
414
415		/* initialize full speed isochronous */
416
417		sitd->sitd_self =
418		    htohc32(sc, buf_res.physaddr) |
419		    htohc32(sc, EHCI_LINK_SITD);
420
421		sitd->sitd_back =
422		    htohc32(sc, EHCI_LINK_TERMINATE);
423
424		sitd->sitd_next =
425		    sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self;
426
427
428		usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res);
429
430		itd = buf_res.buffer;
431
432		/* initialize page cache pointer */
433
434		itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i;
435
436		/* store a pointer to the transfer descriptor */
437
438		sc->sc_isoc_hs_p_last[i] = itd;
439
440		/* initialize high speed isochronous */
441
442		itd->itd_self =
443		    htohc32(sc, buf_res.physaddr) |
444		    htohc32(sc, EHCI_LINK_ITD);
445
446		itd->itd_next =
447		    sitd->sitd_self;
448	}
449
450	usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
451
452	if (1) {
453		uint32_t *pframes;
454
455		pframes = buf_res.buffer;
456
457		/*
458		 * execution order:
459		 * pframes -> high speed isochronous ->
460		 *    full speed isochronous -> interrupt QH's
461		 */
462		for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) {
463			pframes[i] = sc->sc_isoc_hs_p_last
464			    [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self;
465		}
466	}
467	/* setup sync list pointer */
468	EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr);
469
470	usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
471
472	if (1) {
473
474		ehci_qh_t *qh;
475
476		qh = buf_res.buffer;
477
478		/* initialize page cache pointer */
479
480		qh->page_cache = &sc->sc_hw.async_start_pc;
481
482		/* store a pointer to the queue head */
483
484		sc->sc_async_p_last = qh;
485
486		/* init dummy QH that starts the async list */
487
488		qh->qh_self =
489		    htohc32(sc, buf_res.physaddr) |
490		    htohc32(sc, EHCI_LINK_QH);
491
492		/* fill the QH */
493		qh->qh_endp =
494		    htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL);
495		qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1));
496		qh->qh_link = qh->qh_self;
497		qh->qh_curqtd = 0;
498
499		/* fill the overlay qTD */
500		qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE);
501		qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE);
502		qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED);
503	}
504	/* flush all cache into memory */
505
506	usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc);
507
508#ifdef USB_DEBUG
509	if (ehcidebug) {
510		ehci_dump_sqh(sc, sc->sc_async_p_last);
511	}
512#endif
513
514	/* setup async list pointer */
515	EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH);
516
517
518	/* enable interrupts */
519	EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
520
521	/* turn on controller */
522	EOWRITE4(sc, EHCI_USBCMD,
523	    EHCI_CMD_ITC_1 |		/* 1 microframes interrupt delay */
524	    (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
525	    EHCI_CMD_ASE |
526	    EHCI_CMD_PSE |
527	    EHCI_CMD_RS);
528
529	/* Take over port ownership */
530	EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
531
532	for (i = 0; i < 100; i++) {
533		usb_pause_mtx(NULL, hz / 1000);
534		hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
535		if (!hcr) {
536			break;
537		}
538	}
539	if (hcr) {
540		device_printf(sc->sc_bus.bdev, "run timeout\n");
541		return (USB_ERR_IOERROR);
542	}
543
544	if (!err) {
545		/* catch any lost interrupts */
546		ehci_do_poll(&sc->sc_bus);
547	}
548	return (err);
549}
550
551/*
552 * shut down the controller when the system is going down
553 */
554void
555ehci_detach(ehci_softc_t *sc)
556{
557	USB_BUS_LOCK(&sc->sc_bus);
558
559	usb_callout_stop(&sc->sc_tmo_pcd);
560	usb_callout_stop(&sc->sc_tmo_poll);
561
562	EOWRITE4(sc, EHCI_USBINTR, 0);
563	USB_BUS_UNLOCK(&sc->sc_bus);
564
565	if (ehci_hcreset(sc)) {
566		DPRINTF("reset failed!\n");
567	}
568
569	/* XXX let stray task complete */
570	usb_pause_mtx(NULL, hz / 20);
571
572	usb_callout_drain(&sc->sc_tmo_pcd);
573	usb_callout_drain(&sc->sc_tmo_poll);
574}
575
576void
577ehci_suspend(ehci_softc_t *sc)
578{
579	uint32_t cmd;
580	uint32_t hcr;
581	uint8_t i;
582
583	USB_BUS_LOCK(&sc->sc_bus);
584
585	for (i = 1; i <= sc->sc_noport; i++) {
586		cmd = EOREAD4(sc, EHCI_PORTSC(i));
587		if (((cmd & EHCI_PS_PO) == 0) &&
588		    ((cmd & EHCI_PS_PE) == EHCI_PS_PE)) {
589			EOWRITE4(sc, EHCI_PORTSC(i),
590			    cmd | EHCI_PS_SUSP);
591		}
592	}
593
594	sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD);
595
596	cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
597	EOWRITE4(sc, EHCI_USBCMD, cmd);
598
599	for (i = 0; i < 100; i++) {
600		hcr = EOREAD4(sc, EHCI_USBSTS) &
601		    (EHCI_STS_ASS | EHCI_STS_PSS);
602
603		if (hcr == 0) {
604			break;
605		}
606		usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
607	}
608
609	if (hcr != 0) {
610		device_printf(sc->sc_bus.bdev, "reset timeout\n");
611	}
612	cmd &= ~EHCI_CMD_RS;
613	EOWRITE4(sc, EHCI_USBCMD, cmd);
614
615	for (i = 0; i < 100; i++) {
616		hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
617		if (hcr == EHCI_STS_HCH) {
618			break;
619		}
620		usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
621	}
622
623	if (hcr != EHCI_STS_HCH) {
624		device_printf(sc->sc_bus.bdev,
625		    "config timeout\n");
626	}
627	USB_BUS_UNLOCK(&sc->sc_bus);
628}
629
630void
631ehci_resume(ehci_softc_t *sc)
632{
633	struct usb_page_search buf_res;
634	uint32_t cmd;
635	uint32_t hcr;
636	uint8_t i;
637
638	USB_BUS_LOCK(&sc->sc_bus);
639
640	/* restore things in case the bios doesn't */
641	EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
642
643	usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
644	EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr);
645
646	usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
647	EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH);
648
649	EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
650
651	hcr = 0;
652	for (i = 1; i <= sc->sc_noport; i++) {
653		cmd = EOREAD4(sc, EHCI_PORTSC(i));
654		if (((cmd & EHCI_PS_PO) == 0) &&
655		    ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) {
656			EOWRITE4(sc, EHCI_PORTSC(i),
657			    cmd | EHCI_PS_FPR);
658			hcr = 1;
659		}
660	}
661
662	if (hcr) {
663		usb_pause_mtx(&sc->sc_bus.bus_mtx,
664		    USB_MS_TO_TICKS(USB_RESUME_WAIT));
665
666		for (i = 1; i <= sc->sc_noport; i++) {
667			cmd = EOREAD4(sc, EHCI_PORTSC(i));
668			if (((cmd & EHCI_PS_PO) == 0) &&
669			    ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) {
670				EOWRITE4(sc, EHCI_PORTSC(i),
671				    cmd & ~EHCI_PS_FPR);
672			}
673		}
674	}
675	EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd);
676
677	for (i = 0; i < 100; i++) {
678		hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
679		if (hcr != EHCI_STS_HCH) {
680			break;
681		}
682		usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
683	}
684	if (hcr == EHCI_STS_HCH) {
685		device_printf(sc->sc_bus.bdev, "config timeout\n");
686	}
687
688	USB_BUS_UNLOCK(&sc->sc_bus);
689
690	usb_pause_mtx(NULL,
691	    USB_MS_TO_TICKS(USB_RESUME_WAIT));
692
693	/* catch any lost interrupts */
694	ehci_do_poll(&sc->sc_bus);
695}
696
697void
698ehci_shutdown(ehci_softc_t *sc)
699{
700	DPRINTF("stopping the HC\n");
701
702	if (ehci_hcreset(sc)) {
703		DPRINTF("reset failed!\n");
704	}
705}
706
707#ifdef USB_DEBUG
708static void
709ehci_dump_regs(ehci_softc_t *sc)
710{
711	uint32_t i;
712
713	i = EOREAD4(sc, EHCI_USBCMD);
714	printf("cmd=0x%08x\n", i);
715
716	if (i & EHCI_CMD_ITC_1)
717		printf(" EHCI_CMD_ITC_1\n");
718	if (i & EHCI_CMD_ITC_2)
719		printf(" EHCI_CMD_ITC_2\n");
720	if (i & EHCI_CMD_ITC_4)
721		printf(" EHCI_CMD_ITC_4\n");
722	if (i & EHCI_CMD_ITC_8)
723		printf(" EHCI_CMD_ITC_8\n");
724	if (i & EHCI_CMD_ITC_16)
725		printf(" EHCI_CMD_ITC_16\n");
726	if (i & EHCI_CMD_ITC_32)
727		printf(" EHCI_CMD_ITC_32\n");
728	if (i & EHCI_CMD_ITC_64)
729		printf(" EHCI_CMD_ITC_64\n");
730	if (i & EHCI_CMD_ASPME)
731		printf(" EHCI_CMD_ASPME\n");
732	if (i & EHCI_CMD_ASPMC)
733		printf(" EHCI_CMD_ASPMC\n");
734	if (i & EHCI_CMD_LHCR)
735		printf(" EHCI_CMD_LHCR\n");
736	if (i & EHCI_CMD_IAAD)
737		printf(" EHCI_CMD_IAAD\n");
738	if (i & EHCI_CMD_ASE)
739		printf(" EHCI_CMD_ASE\n");
740	if (i & EHCI_CMD_PSE)
741		printf(" EHCI_CMD_PSE\n");
742	if (i & EHCI_CMD_FLS_M)
743		printf(" EHCI_CMD_FLS_M\n");
744	if (i & EHCI_CMD_HCRESET)
745		printf(" EHCI_CMD_HCRESET\n");
746	if (i & EHCI_CMD_RS)
747		printf(" EHCI_CMD_RS\n");
748
749	i = EOREAD4(sc, EHCI_USBSTS);
750
751	printf("sts=0x%08x\n", i);
752
753	if (i & EHCI_STS_ASS)
754		printf(" EHCI_STS_ASS\n");
755	if (i & EHCI_STS_PSS)
756		printf(" EHCI_STS_PSS\n");
757	if (i & EHCI_STS_REC)
758		printf(" EHCI_STS_REC\n");
759	if (i & EHCI_STS_HCH)
760		printf(" EHCI_STS_HCH\n");
761	if (i & EHCI_STS_IAA)
762		printf(" EHCI_STS_IAA\n");
763	if (i & EHCI_STS_HSE)
764		printf(" EHCI_STS_HSE\n");
765	if (i & EHCI_STS_FLR)
766		printf(" EHCI_STS_FLR\n");
767	if (i & EHCI_STS_PCD)
768		printf(" EHCI_STS_PCD\n");
769	if (i & EHCI_STS_ERRINT)
770		printf(" EHCI_STS_ERRINT\n");
771	if (i & EHCI_STS_INT)
772		printf(" EHCI_STS_INT\n");
773
774	printf("ien=0x%08x\n",
775	    EOREAD4(sc, EHCI_USBINTR));
776	printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n",
777	    EOREAD4(sc, EHCI_FRINDEX),
778	    EOREAD4(sc, EHCI_CTRLDSSEGMENT),
779	    EOREAD4(sc, EHCI_PERIODICLISTBASE),
780	    EOREAD4(sc, EHCI_ASYNCLISTADDR));
781	for (i = 1; i <= sc->sc_noport; i++) {
782		printf("port %d status=0x%08x\n", i,
783		    EOREAD4(sc, EHCI_PORTSC(i)));
784	}
785}
786
787static void
788ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type)
789{
790	link = hc32toh(sc, link);
791	printf("0x%08x", link);
792	if (link & EHCI_LINK_TERMINATE)
793		printf("<T>");
794	else {
795		printf("<");
796		if (type) {
797			switch (EHCI_LINK_TYPE(link)) {
798			case EHCI_LINK_ITD:
799				printf("ITD");
800				break;
801			case EHCI_LINK_QH:
802				printf("QH");
803				break;
804			case EHCI_LINK_SITD:
805				printf("SITD");
806				break;
807			case EHCI_LINK_FSTN:
808				printf("FSTN");
809				break;
810			}
811		}
812		printf(">");
813	}
814}
815
816static void
817ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd)
818{
819	uint32_t s;
820
821	printf("  next=");
822	ehci_dump_link(sc, qtd->qtd_next, 0);
823	printf(" altnext=");
824	ehci_dump_link(sc, qtd->qtd_altnext, 0);
825	printf("\n");
826	s = hc32toh(sc, qtd->qtd_status);
827	printf("  status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n",
828	    s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s),
829	    EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s));
830	printf("    cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n",
831	    EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s),
832	    (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE",
833	    (s & EHCI_QTD_HALTED) ? "-HALTED" : "",
834	    (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "",
835	    (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "",
836	    (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "",
837	    (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "",
838	    (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "",
839	    (s & EHCI_QTD_PINGSTATE) ? "-PING" : "");
840
841	for (s = 0; s < 5; s++) {
842		printf("  buffer[%d]=0x%08x\n", s,
843		    hc32toh(sc, qtd->qtd_buffer[s]));
844	}
845	for (s = 0; s < 5; s++) {
846		printf("  buffer_hi[%d]=0x%08x\n", s,
847		    hc32toh(sc, qtd->qtd_buffer_hi[s]));
848	}
849}
850
851static uint8_t
852ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd)
853{
854	uint8_t temp;
855
856	usb_pc_cpu_invalidate(sqtd->page_cache);
857	printf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self));
858	ehci_dump_qtd(sc, sqtd);
859	temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0;
860	return (temp);
861}
862
863static void
864ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd)
865{
866	uint16_t i;
867	uint8_t stop;
868
869	stop = 0;
870	for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) {
871		stop = ehci_dump_sqtd(sc, sqtd);
872	}
873	if (sqtd) {
874		printf("dump aborted, too many TDs\n");
875	}
876}
877
878static void
879ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh)
880{
881	uint32_t endp;
882	uint32_t endphub;
883
884	usb_pc_cpu_invalidate(qh->page_cache);
885	printf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F);
886	printf("  link=");
887	ehci_dump_link(sc, qh->qh_link, 1);
888	printf("\n");
889	endp = hc32toh(sc, qh->qh_endp);
890	printf("  endp=0x%08x\n", endp);
891	printf("    addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n",
892	    EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp),
893	    EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp),
894	    EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp));
895	printf("    mpl=0x%x ctl=%d nrl=%d\n",
896	    EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp),
897	    EHCI_QH_GET_NRL(endp));
898	endphub = hc32toh(sc, qh->qh_endphub);
899	printf("  endphub=0x%08x\n", endphub);
900	printf("    smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n",
901	    EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub),
902	    EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub),
903	    EHCI_QH_GET_MULT(endphub));
904	printf("  curqtd=");
905	ehci_dump_link(sc, qh->qh_curqtd, 0);
906	printf("\n");
907	printf("Overlay qTD:\n");
908	ehci_dump_qtd(sc, (void *)&qh->qh_qtd);
909}
910
911static void
912ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd)
913{
914	usb_pc_cpu_invalidate(sitd->page_cache);
915	printf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F);
916	printf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next));
917	printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n",
918	    hc32toh(sc, sitd->sitd_portaddr),
919	    (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN))
920	    ? "in" : "out",
921	    EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)),
922	    EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)),
923	    EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)),
924	    EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr)));
925	printf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask));
926	printf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status),
927	    (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "",
928	    EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status)));
929	printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n",
930	    hc32toh(sc, sitd->sitd_back),
931	    hc32toh(sc, sitd->sitd_bp[0]),
932	    hc32toh(sc, sitd->sitd_bp[1]),
933	    hc32toh(sc, sitd->sitd_bp_hi[0]),
934	    hc32toh(sc, sitd->sitd_bp_hi[1]));
935}
936
937static void
938ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd)
939{
940	usb_pc_cpu_invalidate(itd->page_cache);
941	printf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F);
942	printf(" next=0x%08x\n", hc32toh(sc, itd->itd_next));
943	printf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]),
944	    (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
945	printf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]),
946	    (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
947	printf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]),
948	    (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
949	printf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]),
950	    (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
951	printf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]),
952	    (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
953	printf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]),
954	    (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
955	printf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]),
956	    (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
957	printf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]),
958	    (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
959	printf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0]));
960	printf("  addr=0x%02x; endpt=0x%01x\n",
961	    EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])),
962	    EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0])));
963	printf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1]));
964	printf(" dir=%s; mpl=0x%02x\n",
965	    (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out",
966	    EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1])));
967	printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n",
968	    hc32toh(sc, itd->itd_bp[2]),
969	    hc32toh(sc, itd->itd_bp[3]),
970	    hc32toh(sc, itd->itd_bp[4]),
971	    hc32toh(sc, itd->itd_bp[5]),
972	    hc32toh(sc, itd->itd_bp[6]));
973	printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n"
974	    "       0x%08x,0x%08x,0x%08x\n",
975	    hc32toh(sc, itd->itd_bp_hi[0]),
976	    hc32toh(sc, itd->itd_bp_hi[1]),
977	    hc32toh(sc, itd->itd_bp_hi[2]),
978	    hc32toh(sc, itd->itd_bp_hi[3]),
979	    hc32toh(sc, itd->itd_bp_hi[4]),
980	    hc32toh(sc, itd->itd_bp_hi[5]),
981	    hc32toh(sc, itd->itd_bp_hi[6]));
982}
983
984static void
985ehci_dump_isoc(ehci_softc_t *sc)
986{
987	ehci_itd_t *itd;
988	ehci_sitd_t *sitd;
989	uint16_t max = 1000;
990	uint16_t pos;
991
992	pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) &
993	    (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
994
995	printf("%s: isochronous dump from frame 0x%03x:\n",
996	    __FUNCTION__, pos);
997
998	itd = sc->sc_isoc_hs_p_last[pos];
999	sitd = sc->sc_isoc_fs_p_last[pos];
1000
1001	while (itd && max && max--) {
1002		ehci_dump_itd(sc, itd);
1003		itd = itd->prev;
1004	}
1005
1006	while (sitd && max && max--) {
1007		ehci_dump_sitd(sc, sitd);
1008		sitd = sitd->prev;
1009	}
1010}
1011
1012#endif
1013
1014static void
1015ehci_transfer_intr_enqueue(struct usb_xfer *xfer)
1016{
1017	/* check for early completion */
1018	if (ehci_check_transfer(xfer)) {
1019		return;
1020	}
1021	/* put transfer on interrupt queue */
1022	usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
1023
1024	/* start timeout, if any */
1025	if (xfer->timeout != 0) {
1026		usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout);
1027	}
1028}
1029
1030#define	EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last)
1031static ehci_sitd_t *
1032_ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last)
1033{
1034	DPRINTFN(11, "%p to %p\n", std, last);
1035
1036	/* (sc->sc_bus.mtx) must be locked */
1037
1038	std->next = last->next;
1039	std->sitd_next = last->sitd_next;
1040
1041	std->prev = last;
1042
1043	usb_pc_cpu_flush(std->page_cache);
1044
1045	/*
1046	 * the last->next->prev is never followed: std->next->prev = std;
1047	 */
1048	last->next = std;
1049	last->sitd_next = std->sitd_self;
1050
1051	usb_pc_cpu_flush(last->page_cache);
1052
1053	return (std);
1054}
1055
1056#define	EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last)
1057static ehci_itd_t *
1058_ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last)
1059{
1060	DPRINTFN(11, "%p to %p\n", std, last);
1061
1062	/* (sc->sc_bus.mtx) must be locked */
1063
1064	std->next = last->next;
1065	std->itd_next = last->itd_next;
1066
1067	std->prev = last;
1068
1069	usb_pc_cpu_flush(std->page_cache);
1070
1071	/*
1072	 * the last->next->prev is never followed: std->next->prev = std;
1073	 */
1074	last->next = std;
1075	last->itd_next = std->itd_self;
1076
1077	usb_pc_cpu_flush(last->page_cache);
1078
1079	return (std);
1080}
1081
1082#define	EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last)
1083static ehci_qh_t *
1084_ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last)
1085{
1086	DPRINTFN(11, "%p to %p\n", sqh, last);
1087
1088	if (sqh->prev != NULL) {
1089		/* should not happen */
1090		DPRINTFN(0, "QH already linked!\n");
1091		return (last);
1092	}
1093	/* (sc->sc_bus.mtx) must be locked */
1094
1095	sqh->next = last->next;
1096	sqh->qh_link = last->qh_link;
1097
1098	sqh->prev = last;
1099
1100	usb_pc_cpu_flush(sqh->page_cache);
1101
1102	/*
1103	 * the last->next->prev is never followed: sqh->next->prev = sqh;
1104	 */
1105
1106	last->next = sqh;
1107	last->qh_link = sqh->qh_self;
1108
1109	usb_pc_cpu_flush(last->page_cache);
1110
1111	return (sqh);
1112}
1113
1114#define	EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last)
1115static ehci_sitd_t *
1116_ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last)
1117{
1118	DPRINTFN(11, "%p from %p\n", std, last);
1119
1120	/* (sc->sc_bus.mtx) must be locked */
1121
1122	std->prev->next = std->next;
1123	std->prev->sitd_next = std->sitd_next;
1124
1125	usb_pc_cpu_flush(std->prev->page_cache);
1126
1127	if (std->next) {
1128		std->next->prev = std->prev;
1129		usb_pc_cpu_flush(std->next->page_cache);
1130	}
1131	return ((last == std) ? std->prev : last);
1132}
1133
1134#define	EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last)
1135static ehci_itd_t *
1136_ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last)
1137{
1138	DPRINTFN(11, "%p from %p\n", std, last);
1139
1140	/* (sc->sc_bus.mtx) must be locked */
1141
1142	std->prev->next = std->next;
1143	std->prev->itd_next = std->itd_next;
1144
1145	usb_pc_cpu_flush(std->prev->page_cache);
1146
1147	if (std->next) {
1148		std->next->prev = std->prev;
1149		usb_pc_cpu_flush(std->next->page_cache);
1150	}
1151	return ((last == std) ? std->prev : last);
1152}
1153
1154#define	EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last)
1155static ehci_qh_t *
1156_ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last)
1157{
1158	DPRINTFN(11, "%p from %p\n", sqh, last);
1159
1160	/* (sc->sc_bus.mtx) must be locked */
1161
1162	/* only remove if not removed from a queue */
1163	if (sqh->prev) {
1164
1165		sqh->prev->next = sqh->next;
1166		sqh->prev->qh_link = sqh->qh_link;
1167
1168		usb_pc_cpu_flush(sqh->prev->page_cache);
1169
1170		if (sqh->next) {
1171			sqh->next->prev = sqh->prev;
1172			usb_pc_cpu_flush(sqh->next->page_cache);
1173		}
1174		last = ((last == sqh) ? sqh->prev : last);
1175
1176		sqh->prev = 0;
1177
1178		usb_pc_cpu_flush(sqh->page_cache);
1179	}
1180	return (last);
1181}
1182
1183static void
1184ehci_data_toggle_update(struct usb_xfer *xfer, uint16_t actlen, uint16_t xlen)
1185{
1186	uint16_t rem;
1187	uint8_t dt;
1188
1189	/* count number of full packets */
1190	dt = (actlen / xfer->max_packet_size) & 1;
1191
1192	/* compute remainder */
1193	rem = actlen % xfer->max_packet_size;
1194
1195	if (rem > 0)
1196		dt ^= 1;	/* short packet at the end */
1197	else if (actlen != xlen)
1198		dt ^= 1;	/* zero length packet at the end */
1199	else if (xlen == 0)
1200		dt ^= 1;	/* zero length transfer */
1201
1202	xfer->endpoint->toggle_next ^= dt;
1203}
1204
1205static usb_error_t
1206ehci_non_isoc_done_sub(struct usb_xfer *xfer)
1207{
1208	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1209	ehci_qtd_t *td;
1210	ehci_qtd_t *td_alt_next;
1211	uint32_t status;
1212	uint16_t len;
1213
1214	td = xfer->td_transfer_cache;
1215	td_alt_next = td->alt_next;
1216
1217	if (xfer->aframes != xfer->nframes) {
1218		usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
1219	}
1220	while (1) {
1221
1222		usb_pc_cpu_invalidate(td->page_cache);
1223		status = hc32toh(sc, td->qtd_status);
1224
1225		len = EHCI_QTD_GET_BYTES(status);
1226
1227		/*
1228	         * Verify the status length and
1229		 * add the length to "frlengths[]":
1230	         */
1231		if (len > td->len) {
1232			/* should not happen */
1233			DPRINTF("Invalid status length, "
1234			    "0x%04x/0x%04x bytes\n", len, td->len);
1235			status |= EHCI_QTD_HALTED;
1236		} else if (xfer->aframes != xfer->nframes) {
1237			xfer->frlengths[xfer->aframes] += td->len - len;
1238			/* manually update data toggle */
1239			ehci_data_toggle_update(xfer, td->len - len, td->len);
1240		}
1241
1242		/* Check for last transfer */
1243		if (((void *)td) == xfer->td_transfer_last) {
1244			td = NULL;
1245			break;
1246		}
1247		/* Check for transfer error */
1248		if (status & EHCI_QTD_HALTED) {
1249			/* the transfer is finished */
1250			td = NULL;
1251			break;
1252		}
1253		/* Check for short transfer */
1254		if (len > 0) {
1255			if (xfer->flags_int.short_frames_ok) {
1256				/* follow alt next */
1257				td = td->alt_next;
1258			} else {
1259				/* the transfer is finished */
1260				td = NULL;
1261			}
1262			break;
1263		}
1264		td = td->obj_next;
1265
1266		if (td->alt_next != td_alt_next) {
1267			/* this USB frame is complete */
1268			break;
1269		}
1270	}
1271
1272	/* update transfer cache */
1273
1274	xfer->td_transfer_cache = td;
1275
1276#ifdef USB_DEBUG
1277	if (status & EHCI_QTD_STATERRS) {
1278		DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x"
1279		    "status=%s%s%s%s%s%s%s%s\n",
1280		    xfer->address, xfer->endpointno, xfer->aframes,
1281		    (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]",
1282		    (status & EHCI_QTD_HALTED) ? "[HALTED]" : "",
1283		    (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "",
1284		    (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "",
1285		    (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "",
1286		    (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "",
1287		    (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "",
1288		    (status & EHCI_QTD_PINGSTATE) ? "[PING]" : "");
1289	}
1290#endif
1291
1292	return ((status & EHCI_QTD_HALTED) ?
1293	    USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1294}
1295
1296static void
1297ehci_non_isoc_done(struct usb_xfer *xfer)
1298{
1299	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1300	ehci_qh_t *qh;
1301	uint32_t status;
1302	usb_error_t err = 0;
1303
1304	DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1305	    xfer, xfer->endpoint);
1306
1307#ifdef USB_DEBUG
1308	if (ehcidebug > 10) {
1309		ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1310
1311		ehci_dump_sqtds(sc, xfer->td_transfer_first);
1312	}
1313#endif
1314
1315	/* extract data toggle directly from the QH's overlay area */
1316
1317	qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1318
1319	usb_pc_cpu_invalidate(qh->page_cache);
1320
1321	status = hc32toh(sc, qh->qh_qtd.qtd_status);
1322
1323	/* reset scanner */
1324
1325	xfer->td_transfer_cache = xfer->td_transfer_first;
1326
1327	if (xfer->flags_int.control_xfr) {
1328
1329		if (xfer->flags_int.control_hdr) {
1330
1331			err = ehci_non_isoc_done_sub(xfer);
1332		}
1333		xfer->aframes = 1;
1334
1335		if (xfer->td_transfer_cache == NULL) {
1336			goto done;
1337		}
1338	}
1339	while (xfer->aframes != xfer->nframes) {
1340
1341		err = ehci_non_isoc_done_sub(xfer);
1342		xfer->aframes++;
1343
1344		if (xfer->td_transfer_cache == NULL) {
1345			goto done;
1346		}
1347	}
1348
1349	if (xfer->flags_int.control_xfr &&
1350	    !xfer->flags_int.control_act) {
1351
1352		err = ehci_non_isoc_done_sub(xfer);
1353	}
1354done:
1355	ehci_device_done(xfer, err);
1356}
1357
1358/*------------------------------------------------------------------------*
1359 *	ehci_check_transfer
1360 *
1361 * Return values:
1362 *    0: USB transfer is not finished
1363 * Else: USB transfer is finished
1364 *------------------------------------------------------------------------*/
1365static uint8_t
1366ehci_check_transfer(struct usb_xfer *xfer)
1367{
1368	struct usb_pipe_methods *methods = xfer->endpoint->methods;
1369	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1370
1371	uint32_t status;
1372
1373	DPRINTFN(13, "xfer=%p checking transfer\n", xfer);
1374
1375	if (methods == &ehci_device_isoc_fs_methods) {
1376		ehci_sitd_t *td;
1377
1378		/* isochronous full speed transfer */
1379
1380		td = xfer->td_transfer_last;
1381		usb_pc_cpu_invalidate(td->page_cache);
1382		status = hc32toh(sc, td->sitd_status);
1383
1384		/* also check if first is complete */
1385
1386		td = xfer->td_transfer_first;
1387		usb_pc_cpu_invalidate(td->page_cache);
1388		status |= hc32toh(sc, td->sitd_status);
1389
1390		if (!(status & EHCI_SITD_ACTIVE)) {
1391			ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1392			goto transferred;
1393		}
1394	} else if (methods == &ehci_device_isoc_hs_methods) {
1395		ehci_itd_t *td;
1396
1397		/* isochronous high speed transfer */
1398
1399		/* check last transfer */
1400		td = xfer->td_transfer_last;
1401		usb_pc_cpu_invalidate(td->page_cache);
1402		status = td->itd_status[0];
1403		status |= td->itd_status[1];
1404		status |= td->itd_status[2];
1405		status |= td->itd_status[3];
1406		status |= td->itd_status[4];
1407		status |= td->itd_status[5];
1408		status |= td->itd_status[6];
1409		status |= td->itd_status[7];
1410
1411		/* also check first transfer */
1412		td = xfer->td_transfer_first;
1413		usb_pc_cpu_invalidate(td->page_cache);
1414		status |= td->itd_status[0];
1415		status |= td->itd_status[1];
1416		status |= td->itd_status[2];
1417		status |= td->itd_status[3];
1418		status |= td->itd_status[4];
1419		status |= td->itd_status[5];
1420		status |= td->itd_status[6];
1421		status |= td->itd_status[7];
1422
1423		/* if no transactions are active we continue */
1424		if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) {
1425			ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1426			goto transferred;
1427		}
1428	} else {
1429		ehci_qtd_t *td;
1430		ehci_qh_t *qh;
1431
1432		/* non-isochronous transfer */
1433
1434		/*
1435		 * check whether there is an error somewhere in the middle,
1436		 * or whether there was a short packet (SPD and not ACTIVE)
1437		 */
1438		td = xfer->td_transfer_cache;
1439
1440		qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1441
1442		usb_pc_cpu_invalidate(qh->page_cache);
1443
1444		status = hc32toh(sc, qh->qh_qtd.qtd_status);
1445		if (status & EHCI_QTD_ACTIVE) {
1446			/* transfer is pending */
1447			goto done;
1448		}
1449
1450		while (1) {
1451			usb_pc_cpu_invalidate(td->page_cache);
1452			status = hc32toh(sc, td->qtd_status);
1453
1454			/*
1455			 * Check if there is an active TD which
1456			 * indicates that the transfer isn't done.
1457			 */
1458			if (status & EHCI_QTD_ACTIVE) {
1459				/* update cache */
1460				xfer->td_transfer_cache = td;
1461				goto done;
1462			}
1463			/*
1464			 * last transfer descriptor makes the transfer done
1465			 */
1466			if (((void *)td) == xfer->td_transfer_last) {
1467				break;
1468			}
1469			/*
1470			 * any kind of error makes the transfer done
1471			 */
1472			if (status & EHCI_QTD_HALTED) {
1473				break;
1474			}
1475			/*
1476			 * if there is no alternate next transfer, a short
1477			 * packet also makes the transfer done
1478			 */
1479			if (EHCI_QTD_GET_BYTES(status)) {
1480				if (xfer->flags_int.short_frames_ok) {
1481					/* follow alt next */
1482					if (td->alt_next) {
1483						td = td->alt_next;
1484						continue;
1485					}
1486				}
1487				/* transfer is done */
1488				break;
1489			}
1490			td = td->obj_next;
1491		}
1492		ehci_non_isoc_done(xfer);
1493		goto transferred;
1494	}
1495
1496done:
1497	DPRINTFN(13, "xfer=%p is still active\n", xfer);
1498	return (0);
1499
1500transferred:
1501	return (1);
1502}
1503
1504static void
1505ehci_pcd_enable(ehci_softc_t *sc)
1506{
1507	USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1508
1509	sc->sc_eintrs |= EHCI_STS_PCD;
1510	EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1511
1512	/* acknowledge any PCD interrupt */
1513	EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD);
1514
1515	ehci_root_intr(sc);
1516}
1517
1518static void
1519ehci_interrupt_poll(ehci_softc_t *sc)
1520{
1521	struct usb_xfer *xfer;
1522
1523repeat:
1524	TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
1525		/*
1526		 * check if transfer is transferred
1527		 */
1528		if (ehci_check_transfer(xfer)) {
1529			/* queue has been modified */
1530			goto repeat;
1531		}
1532	}
1533}
1534
1535/*
1536 * Some EHCI chips from VIA / ATI seem to trigger interrupts before
1537 * writing back the qTD status, or miss signalling occasionally under
1538 * heavy load.  If the host machine is too fast, we can miss
1539 * transaction completion - when we scan the active list the
1540 * transaction still seems to be active. This generally exhibits
1541 * itself as a umass stall that never recovers.
1542 *
1543 * We work around this behaviour by setting up this callback after any
1544 * softintr that completes with transactions still pending, giving us
1545 * another chance to check for completion after the writeback has
1546 * taken place.
1547 */
1548static void
1549ehci_poll_timeout(void *arg)
1550{
1551	ehci_softc_t *sc = arg;
1552
1553	DPRINTFN(3, "\n");
1554	ehci_interrupt_poll(sc);
1555}
1556
1557/*------------------------------------------------------------------------*
1558 *	ehci_interrupt - EHCI interrupt handler
1559 *
1560 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler,
1561 * hence the interrupt handler will be setup before "sc->sc_bus.bdev"
1562 * is present !
1563 *------------------------------------------------------------------------*/
1564void
1565ehci_interrupt(ehci_softc_t *sc)
1566{
1567	uint32_t status;
1568
1569	USB_BUS_LOCK(&sc->sc_bus);
1570
1571	DPRINTFN(16, "real interrupt\n");
1572
1573#ifdef USB_DEBUG
1574	if (ehcidebug > 15) {
1575		ehci_dump_regs(sc);
1576	}
1577#endif
1578
1579	status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
1580	if (status == 0) {
1581		/* the interrupt was not for us */
1582		goto done;
1583	}
1584	if (!(status & sc->sc_eintrs)) {
1585		goto done;
1586	}
1587	EOWRITE4(sc, EHCI_USBSTS, status);	/* acknowledge */
1588
1589	status &= sc->sc_eintrs;
1590
1591	if (status & EHCI_STS_HSE) {
1592		printf("%s: unrecoverable error, "
1593		    "controller halted\n", __FUNCTION__);
1594#ifdef USB_DEBUG
1595		ehci_dump_regs(sc);
1596		ehci_dump_isoc(sc);
1597#endif
1598	}
1599	if (status & EHCI_STS_PCD) {
1600		/*
1601		 * Disable PCD interrupt for now, because it will be
1602		 * on until the port has been reset.
1603		 */
1604		sc->sc_eintrs &= ~EHCI_STS_PCD;
1605		EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1606
1607		ehci_root_intr(sc);
1608
1609		/* do not allow RHSC interrupts > 1 per second */
1610		usb_callout_reset(&sc->sc_tmo_pcd, hz,
1611		    (void *)&ehci_pcd_enable, sc);
1612	}
1613	status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA);
1614
1615	if (status != 0) {
1616		/* block unprocessed interrupts */
1617		sc->sc_eintrs &= ~status;
1618		EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1619		printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status);
1620	}
1621	/* poll all the USB transfers */
1622	ehci_interrupt_poll(sc);
1623
1624	if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) {
1625		usb_callout_reset(&sc->sc_tmo_poll, hz / 128,
1626		    (void *)&ehci_poll_timeout, sc);
1627	}
1628
1629done:
1630	USB_BUS_UNLOCK(&sc->sc_bus);
1631}
1632
1633/*
1634 * called when a request does not complete
1635 */
1636static void
1637ehci_timeout(void *arg)
1638{
1639	struct usb_xfer *xfer = arg;
1640
1641	DPRINTF("xfer=%p\n", xfer);
1642
1643	USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1644
1645	/* transfer is transferred */
1646	ehci_device_done(xfer, USB_ERR_TIMEOUT);
1647}
1648
1649static void
1650ehci_do_poll(struct usb_bus *bus)
1651{
1652	ehci_softc_t *sc = EHCI_BUS2SC(bus);
1653
1654	USB_BUS_LOCK(&sc->sc_bus);
1655	ehci_interrupt_poll(sc);
1656	USB_BUS_UNLOCK(&sc->sc_bus);
1657}
1658
1659static void
1660ehci_setup_standard_chain_sub(struct ehci_std_temp *temp)
1661{
1662	struct usb_page_search buf_res;
1663	ehci_qtd_t *td;
1664	ehci_qtd_t *td_next;
1665	ehci_qtd_t *td_alt_next;
1666	uint32_t buf_offset;
1667	uint32_t average;
1668	uint32_t len_old;
1669	uint32_t terminate;
1670	uint32_t qtd_altnext;
1671	uint8_t shortpkt_old;
1672	uint8_t precompute;
1673
1674	terminate = temp->sc->sc_terminate_self;
1675	qtd_altnext = temp->sc->sc_terminate_self;
1676	td_alt_next = NULL;
1677	buf_offset = 0;
1678	shortpkt_old = temp->shortpkt;
1679	len_old = temp->len;
1680	precompute = 1;
1681
1682restart:
1683
1684	td = temp->td;
1685	td_next = temp->td_next;
1686
1687	while (1) {
1688
1689		if (temp->len == 0) {
1690
1691			if (temp->shortpkt) {
1692				break;
1693			}
1694			/* send a Zero Length Packet, ZLP, last */
1695
1696			temp->shortpkt = 1;
1697			average = 0;
1698
1699		} else {
1700
1701			average = temp->average;
1702
1703			if (temp->len < average) {
1704				if (temp->len % temp->max_frame_size) {
1705					temp->shortpkt = 1;
1706				}
1707				average = temp->len;
1708			}
1709		}
1710
1711		if (td_next == NULL) {
1712			panic("%s: out of EHCI transfer descriptors!", __FUNCTION__);
1713		}
1714		/* get next TD */
1715
1716		td = td_next;
1717		td_next = td->obj_next;
1718
1719		/* check if we are pre-computing */
1720
1721		if (precompute) {
1722
1723			/* update remaining length */
1724
1725			temp->len -= average;
1726
1727			continue;
1728		}
1729		/* fill out current TD */
1730
1731		td->qtd_status =
1732		    temp->qtd_status |
1733		    htohc32(temp->sc, EHCI_QTD_IOC |
1734			EHCI_QTD_SET_BYTES(average));
1735
1736		if (average == 0) {
1737
1738			if (temp->auto_data_toggle == 0) {
1739
1740				/* update data toggle, ZLP case */
1741
1742				temp->qtd_status ^=
1743				    htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1744			}
1745			td->len = 0;
1746
1747			td->qtd_buffer[0] = 0;
1748			td->qtd_buffer_hi[0] = 0;
1749
1750			td->qtd_buffer[1] = 0;
1751			td->qtd_buffer_hi[1] = 0;
1752
1753		} else {
1754
1755			uint8_t x;
1756
1757			if (temp->auto_data_toggle == 0) {
1758
1759				/* update data toggle */
1760
1761				if (((average + temp->max_frame_size - 1) /
1762				    temp->max_frame_size) & 1) {
1763					temp->qtd_status ^=
1764					    htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1765				}
1766			}
1767			td->len = average;
1768
1769			/* update remaining length */
1770
1771			temp->len -= average;
1772
1773			/* fill out buffer pointers */
1774
1775			usbd_get_page(temp->pc, buf_offset, &buf_res);
1776			td->qtd_buffer[0] =
1777			    htohc32(temp->sc, buf_res.physaddr);
1778			td->qtd_buffer_hi[0] = 0;
1779
1780			x = 1;
1781
1782			while (average > EHCI_PAGE_SIZE) {
1783				average -= EHCI_PAGE_SIZE;
1784				buf_offset += EHCI_PAGE_SIZE;
1785				usbd_get_page(temp->pc, buf_offset, &buf_res);
1786				td->qtd_buffer[x] =
1787				    htohc32(temp->sc,
1788				    buf_res.physaddr & (~0xFFF));
1789				td->qtd_buffer_hi[x] = 0;
1790				x++;
1791			}
1792
1793			/*
1794			 * NOTE: The "average" variable is never zero after
1795			 * exiting the loop above !
1796			 *
1797			 * NOTE: We have to subtract one from the offset to
1798			 * ensure that we are computing the physical address
1799			 * of a valid page !
1800			 */
1801			buf_offset += average;
1802			usbd_get_page(temp->pc, buf_offset - 1, &buf_res);
1803			td->qtd_buffer[x] =
1804			    htohc32(temp->sc,
1805			    buf_res.physaddr & (~0xFFF));
1806			td->qtd_buffer_hi[x] = 0;
1807		}
1808
1809		if (td_next) {
1810			/* link the current TD with the next one */
1811			td->qtd_next = td_next->qtd_self;
1812		}
1813		td->qtd_altnext = qtd_altnext;
1814		td->alt_next = td_alt_next;
1815
1816		usb_pc_cpu_flush(td->page_cache);
1817	}
1818
1819	if (precompute) {
1820		precompute = 0;
1821
1822		/* setup alt next pointer, if any */
1823		if (temp->last_frame) {
1824			td_alt_next = NULL;
1825			qtd_altnext = terminate;
1826		} else {
1827			/* we use this field internally */
1828			td_alt_next = td_next;
1829			if (temp->setup_alt_next) {
1830				qtd_altnext = td_next->qtd_self;
1831			} else {
1832				qtd_altnext = terminate;
1833			}
1834		}
1835
1836		/* restore */
1837		temp->shortpkt = shortpkt_old;
1838		temp->len = len_old;
1839		goto restart;
1840	}
1841	temp->td = td;
1842	temp->td_next = td_next;
1843}
1844
1845static void
1846ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last)
1847{
1848	struct ehci_std_temp temp;
1849	struct usb_pipe_methods *methods;
1850	ehci_qh_t *qh;
1851	ehci_qtd_t *td;
1852	uint32_t qh_endp;
1853	uint32_t qh_endphub;
1854	uint32_t x;
1855
1856	DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1857	    xfer->address, UE_GET_ADDR(xfer->endpointno),
1858	    xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
1859
1860	temp.average = xfer->max_hc_frame_size;
1861	temp.max_frame_size = xfer->max_frame_size;
1862	temp.sc = EHCI_BUS2SC(xfer->xroot->bus);
1863
1864	/* toggle the DMA set we are using */
1865	xfer->flags_int.curr_dma_set ^= 1;
1866
1867	/* get next DMA set */
1868	td = xfer->td_start[xfer->flags_int.curr_dma_set];
1869
1870	xfer->td_transfer_first = td;
1871	xfer->td_transfer_cache = td;
1872
1873	temp.td = NULL;
1874	temp.td_next = td;
1875	temp.qtd_status = 0;
1876	temp.last_frame = 0;
1877	temp.setup_alt_next = xfer->flags_int.short_frames_ok;
1878
1879	if (xfer->flags_int.control_xfr) {
1880		if (xfer->endpoint->toggle_next) {
1881			/* DATA1 is next */
1882			temp.qtd_status |=
1883			    htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
1884		}
1885		temp.auto_data_toggle = 0;
1886	} else {
1887		temp.auto_data_toggle = 1;
1888	}
1889
1890	if ((xfer->xroot->udev->parent_hs_hub != NULL) ||
1891	    (xfer->xroot->udev->address != 0)) {
1892		/* max 3 retries */
1893		temp.qtd_status |=
1894		    htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1895	}
1896	/* check if we should prepend a setup message */
1897
1898	if (xfer->flags_int.control_xfr) {
1899		if (xfer->flags_int.control_hdr) {
1900
1901			xfer->endpoint->toggle_next = 0;
1902
1903			temp.qtd_status &=
1904			    htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1905			temp.qtd_status |= htohc32(temp.sc,
1906			    EHCI_QTD_ACTIVE |
1907			    EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) |
1908			    EHCI_QTD_SET_TOGGLE(0));
1909
1910			temp.len = xfer->frlengths[0];
1911			temp.pc = xfer->frbuffers + 0;
1912			temp.shortpkt = temp.len ? 1 : 0;
1913			/* check for last frame */
1914			if (xfer->nframes == 1) {
1915				/* no STATUS stage yet, SETUP is last */
1916				if (xfer->flags_int.control_act) {
1917					temp.last_frame = 1;
1918					temp.setup_alt_next = 0;
1919				}
1920			}
1921			ehci_setup_standard_chain_sub(&temp);
1922		}
1923		x = 1;
1924	} else {
1925		x = 0;
1926	}
1927
1928	while (x != xfer->nframes) {
1929
1930		/* DATA0 / DATA1 message */
1931
1932		temp.len = xfer->frlengths[x];
1933		temp.pc = xfer->frbuffers + x;
1934
1935		x++;
1936
1937		if (x == xfer->nframes) {
1938			if (xfer->flags_int.control_xfr) {
1939				/* no STATUS stage yet, DATA is last */
1940				if (xfer->flags_int.control_act) {
1941					temp.last_frame = 1;
1942					temp.setup_alt_next = 0;
1943				}
1944			} else {
1945				temp.last_frame = 1;
1946				temp.setup_alt_next = 0;
1947			}
1948		}
1949		/* keep previous data toggle and error count */
1950
1951		temp.qtd_status &=
1952		    htohc32(temp.sc, EHCI_QTD_SET_CERR(3) |
1953		    EHCI_QTD_SET_TOGGLE(1));
1954
1955		if (temp.len == 0) {
1956
1957			/* make sure that we send an USB packet */
1958
1959			temp.shortpkt = 0;
1960
1961		} else {
1962
1963			/* regular data transfer */
1964
1965			temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1966		}
1967
1968		/* set endpoint direction */
1969
1970		temp.qtd_status |=
1971		    (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ?
1972		    htohc32(temp.sc, EHCI_QTD_ACTIVE |
1973		    EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) :
1974		    htohc32(temp.sc, EHCI_QTD_ACTIVE |
1975		    EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT));
1976
1977		ehci_setup_standard_chain_sub(&temp);
1978	}
1979
1980	/* check if we should append a status stage */
1981
1982	if (xfer->flags_int.control_xfr &&
1983	    !xfer->flags_int.control_act) {
1984
1985		/*
1986		 * Send a DATA1 message and invert the current endpoint
1987		 * direction.
1988		 */
1989
1990		temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) |
1991		    EHCI_QTD_SET_TOGGLE(1));
1992		temp.qtd_status |=
1993		    (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ?
1994		    htohc32(temp.sc, EHCI_QTD_ACTIVE |
1995		    EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) |
1996		    EHCI_QTD_SET_TOGGLE(1)) :
1997		    htohc32(temp.sc, EHCI_QTD_ACTIVE |
1998		    EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) |
1999		    EHCI_QTD_SET_TOGGLE(1));
2000
2001		temp.len = 0;
2002		temp.pc = NULL;
2003		temp.shortpkt = 0;
2004		temp.last_frame = 1;
2005		temp.setup_alt_next = 0;
2006
2007		ehci_setup_standard_chain_sub(&temp);
2008	}
2009	td = temp.td;
2010
2011	/* the last TD terminates the transfer: */
2012	td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE);
2013	td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE);
2014
2015	usb_pc_cpu_flush(td->page_cache);
2016
2017	/* must have at least one frame! */
2018
2019	xfer->td_transfer_last = td;
2020
2021#ifdef USB_DEBUG
2022	if (ehcidebug > 8) {
2023		DPRINTF("nexttog=%d; data before transfer:\n",
2024		    xfer->endpoint->toggle_next);
2025		ehci_dump_sqtds(temp.sc,
2026		    xfer->td_transfer_first);
2027	}
2028#endif
2029
2030	methods = xfer->endpoint->methods;
2031
2032	qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
2033
2034	/* the "qh_link" field is filled when the QH is added */
2035
2036	qh_endp =
2037	    (EHCI_QH_SET_ADDR(xfer->address) |
2038	    EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) |
2039	    EHCI_QH_SET_MPL(xfer->max_packet_size));
2040
2041	if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
2042		qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH);
2043		if (methods != &ehci_device_intr_methods)
2044			qh_endp |= EHCI_QH_SET_NRL(8);
2045	} else {
2046
2047		if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) {
2048			qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL);
2049		} else {
2050			qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW);
2051		}
2052
2053		if (methods == &ehci_device_ctrl_methods) {
2054			qh_endp |= EHCI_QH_CTL;
2055		}
2056		if (methods != &ehci_device_intr_methods) {
2057			/* Only try one time per microframe! */
2058			qh_endp |= EHCI_QH_SET_NRL(1);
2059		}
2060	}
2061
2062	if (temp.auto_data_toggle == 0) {
2063		/* software computes the data toggle */
2064		qh_endp |= EHCI_QH_DTC;
2065	}
2066
2067	qh->qh_endp = htohc32(temp.sc, qh_endp);
2068
2069	qh_endphub =
2070	    (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) |
2071	    EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) |
2072	    EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) |
2073	    EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) |
2074	    EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no));
2075
2076	qh->qh_endphub = htohc32(temp.sc, qh_endphub);
2077	qh->qh_curqtd = 0;
2078
2079	/* fill the overlay qTD */
2080
2081	if (temp.auto_data_toggle && xfer->endpoint->toggle_next) {
2082		/* DATA1 is next */
2083		qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
2084	} else {
2085		qh->qh_qtd.qtd_status = 0;
2086	}
2087
2088	td = xfer->td_transfer_first;
2089
2090	qh->qh_qtd.qtd_next = td->qtd_self;
2091	qh->qh_qtd.qtd_altnext =
2092	    htohc32(temp.sc, EHCI_LINK_TERMINATE);
2093
2094	usb_pc_cpu_flush(qh->page_cache);
2095
2096	if (xfer->xroot->udev->flags.self_suspended == 0) {
2097		EHCI_APPEND_QH(qh, *qh_last);
2098	}
2099}
2100
2101static void
2102ehci_root_intr(ehci_softc_t *sc)
2103{
2104	uint16_t i;
2105	uint16_t m;
2106
2107	USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2108
2109	/* clear any old interrupt data */
2110	memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2111
2112	/* set bits */
2113	m = (sc->sc_noport + 1);
2114	if (m > (8 * sizeof(sc->sc_hub_idata))) {
2115		m = (8 * sizeof(sc->sc_hub_idata));
2116	}
2117	for (i = 1; i < m; i++) {
2118		/* pick out CHANGE bits from the status register */
2119		if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) {
2120			sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2121			DPRINTF("port %d changed\n", i);
2122		}
2123	}
2124	uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2125	    sizeof(sc->sc_hub_idata));
2126}
2127
2128static void
2129ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer)
2130{
2131	uint32_t nframes = xfer->nframes;
2132	uint32_t status;
2133	uint32_t *plen = xfer->frlengths;
2134	uint16_t len = 0;
2135	ehci_sitd_t *td = xfer->td_transfer_first;
2136	ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos];
2137
2138	DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2139	    xfer, xfer->endpoint);
2140
2141	while (nframes--) {
2142		if (td == NULL) {
2143			panic("%s:%d: out of TD's\n",
2144			    __FUNCTION__, __LINE__);
2145		}
2146		if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2147			pp_last = &sc->sc_isoc_fs_p_last[0];
2148		}
2149#ifdef USB_DEBUG
2150		if (ehcidebug > 15) {
2151			DPRINTF("isoc FS-TD\n");
2152			ehci_dump_sitd(sc, td);
2153		}
2154#endif
2155		usb_pc_cpu_invalidate(td->page_cache);
2156		status = hc32toh(sc, td->sitd_status);
2157
2158		len = EHCI_SITD_GET_LEN(status);
2159
2160		DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len);
2161
2162		if (*plen >= len) {
2163			len = *plen - len;
2164		} else {
2165			len = 0;
2166		}
2167
2168		*plen = len;
2169
2170		/* remove FS-TD from schedule */
2171		EHCI_REMOVE_FS_TD(td, *pp_last);
2172
2173		pp_last++;
2174		plen++;
2175		td = td->obj_next;
2176	}
2177
2178	xfer->aframes = xfer->nframes;
2179}
2180
2181static void
2182ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer)
2183{
2184	uint32_t nframes = xfer->nframes;
2185	uint32_t status;
2186	uint32_t *plen = xfer->frlengths;
2187	uint16_t len = 0;
2188	uint8_t td_no = 0;
2189	ehci_itd_t *td = xfer->td_transfer_first;
2190	ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos];
2191
2192	DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2193	    xfer, xfer->endpoint);
2194
2195	while (nframes) {
2196		if (td == NULL) {
2197			panic("%s:%d: out of TD's\n",
2198			    __FUNCTION__, __LINE__);
2199		}
2200		if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2201			pp_last = &sc->sc_isoc_hs_p_last[0];
2202		}
2203#ifdef USB_DEBUG
2204		if (ehcidebug > 15) {
2205			DPRINTF("isoc HS-TD\n");
2206			ehci_dump_itd(sc, td);
2207		}
2208#endif
2209
2210		usb_pc_cpu_invalidate(td->page_cache);
2211		status = hc32toh(sc, td->itd_status[td_no]);
2212
2213		len = EHCI_ITD_GET_LEN(status);
2214
2215		DPRINTFN(2, "status=0x%08x, len=%u\n", status, len);
2216
2217		if (xfer->endpoint->usb_smask & (1 << td_no)) {
2218
2219			if (*plen >= len) {
2220				/*
2221				 * The length is valid. NOTE: The
2222				 * complete length is written back
2223				 * into the status field, and not the
2224				 * remainder like with other transfer
2225				 * descriptor types.
2226				 */
2227			} else {
2228				/* Invalid length - truncate */
2229				len = 0;
2230			}
2231
2232			*plen = len;
2233			plen++;
2234			nframes--;
2235		}
2236
2237		td_no++;
2238
2239		if ((td_no == 8) || (nframes == 0)) {
2240			/* remove HS-TD from schedule */
2241			EHCI_REMOVE_HS_TD(td, *pp_last);
2242			pp_last++;
2243
2244			td_no = 0;
2245			td = td->obj_next;
2246		}
2247	}
2248	xfer->aframes = xfer->nframes;
2249}
2250
2251/* NOTE: "done" can be run two times in a row,
2252 * from close and from interrupt
2253 */
2254static void
2255ehci_device_done(struct usb_xfer *xfer, usb_error_t error)
2256{
2257	struct usb_pipe_methods *methods = xfer->endpoint->methods;
2258	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2259
2260	USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2261
2262	DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2263	    xfer, xfer->endpoint, error);
2264
2265	if ((methods == &ehci_device_bulk_methods) ||
2266	    (methods == &ehci_device_ctrl_methods)) {
2267#ifdef USB_DEBUG
2268		if (ehcidebug > 8) {
2269			DPRINTF("nexttog=%d; data after transfer:\n",
2270			    xfer->endpoint->toggle_next);
2271			ehci_dump_sqtds(sc,
2272			    xfer->td_transfer_first);
2273		}
2274#endif
2275
2276		EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2277		    sc->sc_async_p_last);
2278	}
2279	if (methods == &ehci_device_intr_methods) {
2280		EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2281		    sc->sc_intr_p_last[xfer->qh_pos]);
2282	}
2283	/*
2284	 * Only finish isochronous transfers once which will update
2285	 * "xfer->frlengths".
2286	 */
2287	if (xfer->td_transfer_first &&
2288	    xfer->td_transfer_last) {
2289		if (methods == &ehci_device_isoc_fs_methods) {
2290			ehci_isoc_fs_done(sc, xfer);
2291		}
2292		if (methods == &ehci_device_isoc_hs_methods) {
2293			ehci_isoc_hs_done(sc, xfer);
2294		}
2295		xfer->td_transfer_first = NULL;
2296		xfer->td_transfer_last = NULL;
2297	}
2298	/* dequeue transfer and start next transfer */
2299	usbd_transfer_done(xfer, error);
2300}
2301
2302/*------------------------------------------------------------------------*
2303 * ehci bulk support
2304 *------------------------------------------------------------------------*/
2305static void
2306ehci_device_bulk_open(struct usb_xfer *xfer)
2307{
2308	return;
2309}
2310
2311static void
2312ehci_device_bulk_close(struct usb_xfer *xfer)
2313{
2314	ehci_device_done(xfer, USB_ERR_CANCELLED);
2315}
2316
2317static void
2318ehci_device_bulk_enter(struct usb_xfer *xfer)
2319{
2320	return;
2321}
2322
2323static void
2324ehci_device_bulk_start(struct usb_xfer *xfer)
2325{
2326	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2327	uint32_t temp;
2328
2329	/* setup TD's and QH */
2330	ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2331
2332	/* put transfer on interrupt queue */
2333	ehci_transfer_intr_enqueue(xfer);
2334
2335	/*
2336	 * XXX Certain nVidia chipsets choke when using the IAAD
2337	 * feature too frequently.
2338	 */
2339	if (sc->sc_flags & EHCI_SCFLG_IAADBUG)
2340		return;
2341
2342	/* XXX Performance quirk: Some Host Controllers have a too low
2343	 * interrupt rate. Issue an IAAD to stimulate the Host
2344	 * Controller after queueing the BULK transfer.
2345	 */
2346	temp = EOREAD4(sc, EHCI_USBCMD);
2347	if (!(temp & EHCI_CMD_IAAD))
2348		EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD);
2349}
2350
2351struct usb_pipe_methods ehci_device_bulk_methods =
2352{
2353	.open = ehci_device_bulk_open,
2354	.close = ehci_device_bulk_close,
2355	.enter = ehci_device_bulk_enter,
2356	.start = ehci_device_bulk_start,
2357};
2358
2359/*------------------------------------------------------------------------*
2360 * ehci control support
2361 *------------------------------------------------------------------------*/
2362static void
2363ehci_device_ctrl_open(struct usb_xfer *xfer)
2364{
2365	return;
2366}
2367
2368static void
2369ehci_device_ctrl_close(struct usb_xfer *xfer)
2370{
2371	ehci_device_done(xfer, USB_ERR_CANCELLED);
2372}
2373
2374static void
2375ehci_device_ctrl_enter(struct usb_xfer *xfer)
2376{
2377	return;
2378}
2379
2380static void
2381ehci_device_ctrl_start(struct usb_xfer *xfer)
2382{
2383	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2384
2385	/* setup TD's and QH */
2386	ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2387
2388	/* put transfer on interrupt queue */
2389	ehci_transfer_intr_enqueue(xfer);
2390}
2391
2392struct usb_pipe_methods ehci_device_ctrl_methods =
2393{
2394	.open = ehci_device_ctrl_open,
2395	.close = ehci_device_ctrl_close,
2396	.enter = ehci_device_ctrl_enter,
2397	.start = ehci_device_ctrl_start,
2398};
2399
2400/*------------------------------------------------------------------------*
2401 * ehci interrupt support
2402 *------------------------------------------------------------------------*/
2403static void
2404ehci_device_intr_open(struct usb_xfer *xfer)
2405{
2406	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2407	uint16_t best;
2408	uint16_t bit;
2409	uint16_t x;
2410
2411	usb_hs_bandwidth_alloc(xfer);
2412
2413	/*
2414	 * Find the best QH position corresponding to the given interval:
2415	 */
2416
2417	best = 0;
2418	bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
2419	while (bit) {
2420		if (xfer->interval >= bit) {
2421			x = bit;
2422			best = bit;
2423			while (x & bit) {
2424				if (sc->sc_intr_stat[x] <
2425				    sc->sc_intr_stat[best]) {
2426					best = x;
2427				}
2428				x++;
2429			}
2430			break;
2431		}
2432		bit >>= 1;
2433	}
2434
2435	sc->sc_intr_stat[best]++;
2436	xfer->qh_pos = best;
2437
2438	DPRINTFN(3, "best=%d interval=%d\n",
2439	    best, xfer->interval);
2440}
2441
2442static void
2443ehci_device_intr_close(struct usb_xfer *xfer)
2444{
2445	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2446
2447	sc->sc_intr_stat[xfer->qh_pos]--;
2448
2449	ehci_device_done(xfer, USB_ERR_CANCELLED);
2450
2451	/* bandwidth must be freed after device done */
2452	usb_hs_bandwidth_free(xfer);
2453}
2454
2455static void
2456ehci_device_intr_enter(struct usb_xfer *xfer)
2457{
2458	return;
2459}
2460
2461static void
2462ehci_device_intr_start(struct usb_xfer *xfer)
2463{
2464	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2465
2466	/* setup TD's and QH */
2467	ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]);
2468
2469	/* put transfer on interrupt queue */
2470	ehci_transfer_intr_enqueue(xfer);
2471}
2472
2473struct usb_pipe_methods ehci_device_intr_methods =
2474{
2475	.open = ehci_device_intr_open,
2476	.close = ehci_device_intr_close,
2477	.enter = ehci_device_intr_enter,
2478	.start = ehci_device_intr_start,
2479};
2480
2481/*------------------------------------------------------------------------*
2482 * ehci full speed isochronous support
2483 *------------------------------------------------------------------------*/
2484static void
2485ehci_device_isoc_fs_open(struct usb_xfer *xfer)
2486{
2487	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2488	ehci_sitd_t *td;
2489	uint32_t sitd_portaddr;
2490	uint8_t ds;
2491
2492	sitd_portaddr =
2493	    EHCI_SITD_SET_ADDR(xfer->address) |
2494	    EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) |
2495	    EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) |
2496	    EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no);
2497
2498	if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) {
2499		sitd_portaddr |= EHCI_SITD_SET_DIR_IN;
2500	}
2501	sitd_portaddr = htohc32(sc, sitd_portaddr);
2502
2503	/* initialize all TD's */
2504
2505	for (ds = 0; ds != 2; ds++) {
2506
2507		for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2508
2509			td->sitd_portaddr = sitd_portaddr;
2510
2511			/*
2512			 * TODO: make some kind of automatic
2513			 * SMASK/CMASK selection based on micro-frame
2514			 * usage
2515			 *
2516			 * micro-frame usage (8 microframes per 1ms)
2517			 */
2518			td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE);
2519
2520			usb_pc_cpu_flush(td->page_cache);
2521		}
2522	}
2523}
2524
2525static void
2526ehci_device_isoc_fs_close(struct usb_xfer *xfer)
2527{
2528	ehci_device_done(xfer, USB_ERR_CANCELLED);
2529}
2530
2531static void
2532ehci_device_isoc_fs_enter(struct usb_xfer *xfer)
2533{
2534	struct usb_page_search buf_res;
2535	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2536	struct usb_fs_isoc_schedule *fss_start;
2537	struct usb_fs_isoc_schedule *fss_end;
2538	struct usb_fs_isoc_schedule *fss;
2539	ehci_sitd_t *td;
2540	ehci_sitd_t *td_last = NULL;
2541	ehci_sitd_t **pp_last;
2542	uint32_t *plen;
2543	uint32_t buf_offset;
2544	uint32_t nframes;
2545	uint32_t temp;
2546	uint32_t sitd_mask;
2547	uint16_t tlen;
2548	uint8_t sa;
2549	uint8_t sb;
2550	uint8_t error;
2551
2552#ifdef USB_DEBUG
2553	uint8_t once = 1;
2554
2555#endif
2556
2557	DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2558	    xfer, xfer->endpoint->isoc_next, xfer->nframes);
2559
2560	/* get the current frame index */
2561
2562	nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2563
2564	/*
2565	 * check if the frame index is within the window where the frames
2566	 * will be inserted
2567	 */
2568	buf_offset = (nframes - xfer->endpoint->isoc_next) &
2569	    (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2570
2571	if ((xfer->endpoint->is_synced == 0) ||
2572	    (buf_offset < xfer->nframes)) {
2573		/*
2574		 * If there is data underflow or the pipe queue is empty we
2575		 * schedule the transfer a few frames ahead of the current
2576		 * frame position. Else two isochronous transfers might
2577		 * overlap.
2578		 */
2579		xfer->endpoint->isoc_next = (nframes + 3) &
2580		    (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2581		xfer->endpoint->is_synced = 1;
2582		DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2583	}
2584	/*
2585	 * compute how many milliseconds the insertion is ahead of the
2586	 * current frame position:
2587	 */
2588	buf_offset = (xfer->endpoint->isoc_next - nframes) &
2589	    (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2590
2591	/*
2592	 * pre-compute when the isochronous transfer will be finished:
2593	 */
2594	xfer->isoc_time_complete =
2595	    usbd_fs_isoc_schedule_isoc_time_expand
2596	    (xfer->xroot->udev, &fss_start, &fss_end, nframes) + buf_offset +
2597	    xfer->nframes;
2598
2599	/* get the real number of frames */
2600
2601	nframes = xfer->nframes;
2602
2603	buf_offset = 0;
2604
2605	plen = xfer->frlengths;
2606
2607	/* toggle the DMA set we are using */
2608	xfer->flags_int.curr_dma_set ^= 1;
2609
2610	/* get next DMA set */
2611	td = xfer->td_start[xfer->flags_int.curr_dma_set];
2612	xfer->td_transfer_first = td;
2613
2614	pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next];
2615
2616	/* store starting position */
2617
2618	xfer->qh_pos = xfer->endpoint->isoc_next;
2619
2620	fss = fss_start + (xfer->qh_pos % USB_ISOC_TIME_MAX);
2621
2622	while (nframes--) {
2623		if (td == NULL) {
2624			panic("%s:%d: out of TD's\n",
2625			    __FUNCTION__, __LINE__);
2626		}
2627		if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2628			pp_last = &sc->sc_isoc_fs_p_last[0];
2629		}
2630		if (fss >= fss_end) {
2631			fss = fss_start;
2632		}
2633		/* reuse sitd_portaddr and sitd_back from last transfer */
2634
2635		if (*plen > xfer->max_frame_size) {
2636#ifdef USB_DEBUG
2637			if (once) {
2638				once = 0;
2639				printf("%s: frame length(%d) exceeds %d "
2640				    "bytes (frame truncated)\n",
2641				    __FUNCTION__, *plen,
2642				    xfer->max_frame_size);
2643			}
2644#endif
2645			*plen = xfer->max_frame_size;
2646		}
2647		/*
2648		 * We currently don't care if the ISOCHRONOUS schedule is
2649		 * full!
2650		 */
2651		error = usbd_fs_isoc_schedule_alloc(fss, &sa, *plen);
2652		if (error) {
2653			/*
2654			 * The FULL speed schedule is FULL! Set length
2655			 * to zero.
2656			 */
2657			*plen = 0;
2658		}
2659		if (*plen) {
2660			/*
2661			 * only call "usbd_get_page()" when we have a
2662			 * non-zero length
2663			 */
2664			usbd_get_page(xfer->frbuffers, buf_offset, &buf_res);
2665			td->sitd_bp[0] = htohc32(sc, buf_res.physaddr);
2666			buf_offset += *plen;
2667			/*
2668			 * NOTE: We need to subtract one from the offset so
2669			 * that we are on a valid page!
2670			 */
2671			usbd_get_page(xfer->frbuffers, buf_offset - 1,
2672			    &buf_res);
2673			temp = buf_res.physaddr & ~0xFFF;
2674		} else {
2675			td->sitd_bp[0] = 0;
2676			temp = 0;
2677		}
2678
2679		if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) {
2680			tlen = *plen;
2681			if (tlen <= 188) {
2682				temp |= 1;	/* T-count = 1, TP = ALL */
2683				tlen = 1;
2684			} else {
2685				tlen += 187;
2686				tlen /= 188;
2687				temp |= tlen;	/* T-count = [1..6] */
2688				temp |= 8;	/* TP = Begin */
2689			}
2690
2691			tlen += sa;
2692
2693			if (tlen >= 8) {
2694				sb = 0;
2695			} else {
2696				sb = (1 << tlen);
2697			}
2698
2699			sa = (1 << sa);
2700			sa = (sb - sa) & 0x3F;
2701			sb = 0;
2702		} else {
2703			sb = (-(4 << sa)) & 0xFE;
2704			sa = (1 << sa) & 0x3F;
2705		}
2706
2707		sitd_mask = (EHCI_SITD_SET_SMASK(sa) |
2708		    EHCI_SITD_SET_CMASK(sb));
2709
2710		td->sitd_bp[1] = htohc32(sc, temp);
2711
2712		td->sitd_mask = htohc32(sc, sitd_mask);
2713
2714		if (nframes == 0) {
2715			td->sitd_status = htohc32(sc,
2716			    EHCI_SITD_IOC |
2717			    EHCI_SITD_ACTIVE |
2718			    EHCI_SITD_SET_LEN(*plen));
2719		} else {
2720			td->sitd_status = htohc32(sc,
2721			    EHCI_SITD_ACTIVE |
2722			    EHCI_SITD_SET_LEN(*plen));
2723		}
2724		usb_pc_cpu_flush(td->page_cache);
2725
2726#ifdef USB_DEBUG
2727		if (ehcidebug > 15) {
2728			DPRINTF("FS-TD %d\n", nframes);
2729			ehci_dump_sitd(sc, td);
2730		}
2731#endif
2732		/* insert TD into schedule */
2733		EHCI_APPEND_FS_TD(td, *pp_last);
2734		pp_last++;
2735
2736		plen++;
2737		fss++;
2738		td_last = td;
2739		td = td->obj_next;
2740	}
2741
2742	xfer->td_transfer_last = td_last;
2743
2744	/* update isoc_next */
2745	xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) &
2746	    (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2747}
2748
2749static void
2750ehci_device_isoc_fs_start(struct usb_xfer *xfer)
2751{
2752	/* put transfer on interrupt queue */
2753	ehci_transfer_intr_enqueue(xfer);
2754}
2755
2756struct usb_pipe_methods ehci_device_isoc_fs_methods =
2757{
2758	.open = ehci_device_isoc_fs_open,
2759	.close = ehci_device_isoc_fs_close,
2760	.enter = ehci_device_isoc_fs_enter,
2761	.start = ehci_device_isoc_fs_start,
2762};
2763
2764/*------------------------------------------------------------------------*
2765 * ehci high speed isochronous support
2766 *------------------------------------------------------------------------*/
2767static void
2768ehci_device_isoc_hs_open(struct usb_xfer *xfer)
2769{
2770	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2771	ehci_itd_t *td;
2772	uint32_t temp;
2773	uint8_t ds;
2774
2775	usb_hs_bandwidth_alloc(xfer);
2776
2777	/* initialize all TD's */
2778
2779	for (ds = 0; ds != 2; ds++) {
2780
2781		for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2782
2783			/* set TD inactive */
2784			td->itd_status[0] = 0;
2785			td->itd_status[1] = 0;
2786			td->itd_status[2] = 0;
2787			td->itd_status[3] = 0;
2788			td->itd_status[4] = 0;
2789			td->itd_status[5] = 0;
2790			td->itd_status[6] = 0;
2791			td->itd_status[7] = 0;
2792
2793			/* set endpoint and address */
2794			td->itd_bp[0] = htohc32(sc,
2795			    EHCI_ITD_SET_ADDR(xfer->address) |
2796			    EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)));
2797
2798			temp =
2799			    EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF);
2800
2801			/* set direction */
2802			if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) {
2803				temp |= EHCI_ITD_SET_DIR_IN;
2804			}
2805			/* set maximum packet size */
2806			td->itd_bp[1] = htohc32(sc, temp);
2807
2808			/* set transfer multiplier */
2809			td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3);
2810
2811			usb_pc_cpu_flush(td->page_cache);
2812		}
2813	}
2814}
2815
2816static void
2817ehci_device_isoc_hs_close(struct usb_xfer *xfer)
2818{
2819	ehci_device_done(xfer, USB_ERR_CANCELLED);
2820
2821	/* bandwidth must be freed after device done */
2822	usb_hs_bandwidth_free(xfer);
2823}
2824
2825static void
2826ehci_device_isoc_hs_enter(struct usb_xfer *xfer)
2827{
2828	struct usb_page_search buf_res;
2829	ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2830	ehci_itd_t *td;
2831	ehci_itd_t *td_last = NULL;
2832	ehci_itd_t **pp_last;
2833	bus_size_t page_addr;
2834	uint32_t *plen;
2835	uint32_t status;
2836	uint32_t buf_offset;
2837	uint32_t nframes;
2838	uint32_t itd_offset[8 + 1];
2839	uint8_t x;
2840	uint8_t td_no;
2841	uint8_t page_no;
2842	uint8_t shift = usbd_xfer_get_fps_shift(xfer);
2843
2844#ifdef USB_DEBUG
2845	uint8_t once = 1;
2846
2847#endif
2848
2849	DPRINTFN(6, "xfer=%p next=%d nframes=%d shift=%d\n",
2850	    xfer, xfer->endpoint->isoc_next, xfer->nframes, (int)shift);
2851
2852	/* get the current frame index */
2853
2854	nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2855
2856	/*
2857	 * check if the frame index is within the window where the frames
2858	 * will be inserted
2859	 */
2860	buf_offset = (nframes - xfer->endpoint->isoc_next) &
2861	    (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2862
2863	if ((xfer->endpoint->is_synced == 0) ||
2864	    (buf_offset < (((xfer->nframes << shift) + 7) / 8))) {
2865		/*
2866		 * If there is data underflow or the pipe queue is empty we
2867		 * schedule the transfer a few frames ahead of the current
2868		 * frame position. Else two isochronous transfers might
2869		 * overlap.
2870		 */
2871		xfer->endpoint->isoc_next = (nframes + 3) &
2872		    (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2873		xfer->endpoint->is_synced = 1;
2874		DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2875	}
2876	/*
2877	 * compute how many milliseconds the insertion is ahead of the
2878	 * current frame position:
2879	 */
2880	buf_offset = (xfer->endpoint->isoc_next - nframes) &
2881	    (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2882
2883	/*
2884	 * pre-compute when the isochronous transfer will be finished:
2885	 */
2886	xfer->isoc_time_complete =
2887	    usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset +
2888	    (((xfer->nframes << shift) + 7) / 8);
2889
2890	/* get the real number of frames */
2891
2892	nframes = xfer->nframes;
2893
2894	buf_offset = 0;
2895	td_no = 0;
2896
2897	plen = xfer->frlengths;
2898
2899	/* toggle the DMA set we are using */
2900	xfer->flags_int.curr_dma_set ^= 1;
2901
2902	/* get next DMA set */
2903	td = xfer->td_start[xfer->flags_int.curr_dma_set];
2904	xfer->td_transfer_first = td;
2905
2906	pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next];
2907
2908	/* store starting position */
2909
2910	xfer->qh_pos = xfer->endpoint->isoc_next;
2911
2912	while (nframes) {
2913		if (td == NULL) {
2914			panic("%s:%d: out of TD's\n",
2915			    __FUNCTION__, __LINE__);
2916		}
2917		if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2918			pp_last = &sc->sc_isoc_hs_p_last[0];
2919		}
2920		/* range check */
2921		if (*plen > xfer->max_frame_size) {
2922#ifdef USB_DEBUG
2923			if (once) {
2924				once = 0;
2925				printf("%s: frame length(%d) exceeds %d bytes "
2926				    "(frame truncated)\n",
2927				    __FUNCTION__, *plen, xfer->max_frame_size);
2928			}
2929#endif
2930			*plen = xfer->max_frame_size;
2931		}
2932
2933		if (xfer->endpoint->usb_smask & (1 << td_no)) {
2934			status = (EHCI_ITD_SET_LEN(*plen) |
2935			    EHCI_ITD_ACTIVE |
2936			    EHCI_ITD_SET_PG(0));
2937			td->itd_status[td_no] = htohc32(sc, status);
2938			itd_offset[td_no] = buf_offset;
2939			buf_offset += *plen;
2940			plen++;
2941			nframes --;
2942		} else {
2943			td->itd_status[td_no] = 0;	/* not active */
2944			itd_offset[td_no] = buf_offset;
2945		}
2946
2947		td_no++;
2948
2949		if ((td_no == 8) || (nframes == 0)) {
2950
2951			/* the rest of the transfers are not active, if any */
2952			for (x = td_no; x != 8; x++) {
2953				td->itd_status[x] = 0;	/* not active */
2954			}
2955
2956			/* check if there is any data to be transferred */
2957			if (itd_offset[0] != buf_offset) {
2958				page_no = 0;
2959				itd_offset[td_no] = buf_offset;
2960
2961				/* get first page offset */
2962				usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res);
2963				/* get page address */
2964				page_addr = buf_res.physaddr & ~0xFFF;
2965				/* update page address */
2966				td->itd_bp[0] &= htohc32(sc, 0xFFF);
2967				td->itd_bp[0] |= htohc32(sc, page_addr);
2968
2969				for (x = 0; x != td_no; x++) {
2970					/* set page number and page offset */
2971					status = (EHCI_ITD_SET_PG(page_no) |
2972					    (buf_res.physaddr & 0xFFF));
2973					td->itd_status[x] |= htohc32(sc, status);
2974
2975					/* get next page offset */
2976					if (itd_offset[x + 1] == buf_offset) {
2977						/*
2978						 * We subtract one so that
2979						 * we don't go off the last
2980						 * page!
2981						 */
2982						usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res);
2983					} else {
2984						usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res);
2985					}
2986
2987					/* check if we need a new page */
2988					if ((buf_res.physaddr ^ page_addr) & ~0xFFF) {
2989						/* new page needed */
2990						page_addr = buf_res.physaddr & ~0xFFF;
2991						if (page_no == 6) {
2992							panic("%s: too many pages\n", __FUNCTION__);
2993						}
2994						page_no++;
2995						/* update page address */
2996						td->itd_bp[page_no] &= htohc32(sc, 0xFFF);
2997						td->itd_bp[page_no] |= htohc32(sc, page_addr);
2998					}
2999				}
3000			}
3001			/* set IOC bit if we are complete */
3002			if (nframes == 0) {
3003				td->itd_status[td_no - 1] |= htohc32(sc, EHCI_ITD_IOC);
3004			}
3005			usb_pc_cpu_flush(td->page_cache);
3006#ifdef USB_DEBUG
3007			if (ehcidebug > 15) {
3008				DPRINTF("HS-TD %d\n", nframes);
3009				ehci_dump_itd(sc, td);
3010			}
3011#endif
3012			/* insert TD into schedule */
3013			EHCI_APPEND_HS_TD(td, *pp_last);
3014			pp_last++;
3015
3016			td_no = 0;
3017			td_last = td;
3018			td = td->obj_next;
3019		}
3020	}
3021
3022	xfer->td_transfer_last = td_last;
3023
3024	/* update isoc_next */
3025	xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) &
3026	    (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
3027}
3028
3029static void
3030ehci_device_isoc_hs_start(struct usb_xfer *xfer)
3031{
3032	/* put transfer on interrupt queue */
3033	ehci_transfer_intr_enqueue(xfer);
3034}
3035
3036struct usb_pipe_methods ehci_device_isoc_hs_methods =
3037{
3038	.open = ehci_device_isoc_hs_open,
3039	.close = ehci_device_isoc_hs_close,
3040	.enter = ehci_device_isoc_hs_enter,
3041	.start = ehci_device_isoc_hs_start,
3042};
3043
3044/*------------------------------------------------------------------------*
3045 * ehci root control support
3046 *------------------------------------------------------------------------*
3047 * Simulate a hardware hub by handling all the necessary requests.
3048 *------------------------------------------------------------------------*/
3049
3050static const
3051struct usb_device_descriptor ehci_devd =
3052{
3053	sizeof(struct usb_device_descriptor),
3054	UDESC_DEVICE,			/* type */
3055	{0x00, 0x02},			/* USB version */
3056	UDCLASS_HUB,			/* class */
3057	UDSUBCLASS_HUB,			/* subclass */
3058	UDPROTO_HSHUBSTT,		/* protocol */
3059	64,				/* max packet */
3060	{0}, {0}, {0x00, 0x01},		/* device id */
3061	1, 2, 0,			/* string indicies */
3062	1				/* # of configurations */
3063};
3064
3065static const
3066struct usb_device_qualifier ehci_odevd =
3067{
3068	sizeof(struct usb_device_qualifier),
3069	UDESC_DEVICE_QUALIFIER,		/* type */
3070	{0x00, 0x02},			/* USB version */
3071	UDCLASS_HUB,			/* class */
3072	UDSUBCLASS_HUB,			/* subclass */
3073	UDPROTO_FSHUB,			/* protocol */
3074	0,				/* max packet */
3075	0,				/* # of configurations */
3076	0
3077};
3078
3079static const struct ehci_config_desc ehci_confd = {
3080	.confd = {
3081		.bLength = sizeof(struct usb_config_descriptor),
3082		.bDescriptorType = UDESC_CONFIG,
3083		.wTotalLength[0] = sizeof(ehci_confd),
3084		.bNumInterface = 1,
3085		.bConfigurationValue = 1,
3086		.iConfiguration = 0,
3087		.bmAttributes = UC_SELF_POWERED,
3088		.bMaxPower = 0		/* max power */
3089	},
3090	.ifcd = {
3091		.bLength = sizeof(struct usb_interface_descriptor),
3092		.bDescriptorType = UDESC_INTERFACE,
3093		.bNumEndpoints = 1,
3094		.bInterfaceClass = UICLASS_HUB,
3095		.bInterfaceSubClass = UISUBCLASS_HUB,
3096		.bInterfaceProtocol = 0,
3097	},
3098	.endpd = {
3099		.bLength = sizeof(struct usb_endpoint_descriptor),
3100		.bDescriptorType = UDESC_ENDPOINT,
3101		.bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT,
3102		.bmAttributes = UE_INTERRUPT,
3103		.wMaxPacketSize[0] = 8,	/* max packet (63 ports) */
3104		.bInterval = 255,
3105	},
3106};
3107
3108static const
3109struct usb_hub_descriptor ehci_hubd =
3110{
3111	0,				/* dynamic length */
3112	UDESC_HUB,
3113	0,
3114	{0, 0},
3115	0,
3116	0,
3117	{0},
3118};
3119
3120static void
3121ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed)
3122{
3123	uint32_t port;
3124	uint32_t v;
3125
3126	DPRINTF("index=%d lowspeed=%d\n", index, lowspeed);
3127
3128	port = EHCI_PORTSC(index);
3129	v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3130	EOWRITE4(sc, port, v | EHCI_PS_PO);
3131}
3132
3133static usb_error_t
3134ehci_roothub_exec(struct usb_device *udev,
3135    struct usb_device_request *req, const void **pptr, uint16_t *plength)
3136{
3137	ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3138	const char *str_ptr;
3139	const void *ptr;
3140	uint32_t port;
3141	uint32_t v;
3142	uint16_t len;
3143	uint16_t i;
3144	uint16_t value;
3145	uint16_t index;
3146	usb_error_t err;
3147
3148	USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3149
3150	/* buffer reset */
3151	ptr = (const void *)&sc->sc_hub_desc;
3152	len = 0;
3153	err = 0;
3154
3155	value = UGETW(req->wValue);
3156	index = UGETW(req->wIndex);
3157
3158	DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3159	    "wValue=0x%04x wIndex=0x%04x\n",
3160	    req->bmRequestType, req->bRequest,
3161	    UGETW(req->wLength), value, index);
3162
3163#define	C(x,y) ((x) | ((y) << 8))
3164	switch (C(req->bRequest, req->bmRequestType)) {
3165	case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3166	case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3167	case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3168		/*
3169		 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3170		 * for the integrated root hub.
3171		 */
3172		break;
3173	case C(UR_GET_CONFIG, UT_READ_DEVICE):
3174		len = 1;
3175		sc->sc_hub_desc.temp[0] = sc->sc_conf;
3176		break;
3177	case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3178		switch (value >> 8) {
3179		case UDESC_DEVICE:
3180			if ((value & 0xff) != 0) {
3181				err = USB_ERR_IOERROR;
3182				goto done;
3183			}
3184			len = sizeof(ehci_devd);
3185			ptr = (const void *)&ehci_devd;
3186			break;
3187			/*
3188			 * We can't really operate at another speed,
3189			 * but the specification says we need this
3190			 * descriptor:
3191			 */
3192		case UDESC_DEVICE_QUALIFIER:
3193			if ((value & 0xff) != 0) {
3194				err = USB_ERR_IOERROR;
3195				goto done;
3196			}
3197			len = sizeof(ehci_odevd);
3198			ptr = (const void *)&ehci_odevd;
3199			break;
3200
3201		case UDESC_CONFIG:
3202			if ((value & 0xff) != 0) {
3203				err = USB_ERR_IOERROR;
3204				goto done;
3205			}
3206			len = sizeof(ehci_confd);
3207			ptr = (const void *)&ehci_confd;
3208			break;
3209
3210		case UDESC_STRING:
3211			switch (value & 0xff) {
3212			case 0:	/* Language table */
3213				str_ptr = "\001";
3214				break;
3215
3216			case 1:	/* Vendor */
3217				str_ptr = sc->sc_vendor;
3218				break;
3219
3220			case 2:	/* Product */
3221				str_ptr = "EHCI root HUB";
3222				break;
3223
3224			default:
3225				str_ptr = "";
3226				break;
3227			}
3228
3229			len = usb_make_str_desc(
3230			    sc->sc_hub_desc.temp,
3231			    sizeof(sc->sc_hub_desc.temp),
3232			    str_ptr);
3233			break;
3234		default:
3235			err = USB_ERR_IOERROR;
3236			goto done;
3237		}
3238		break;
3239	case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3240		len = 1;
3241		sc->sc_hub_desc.temp[0] = 0;
3242		break;
3243	case C(UR_GET_STATUS, UT_READ_DEVICE):
3244		len = 2;
3245		USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3246		break;
3247	case C(UR_GET_STATUS, UT_READ_INTERFACE):
3248	case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3249		len = 2;
3250		USETW(sc->sc_hub_desc.stat.wStatus, 0);
3251		break;
3252	case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3253		if (value >= EHCI_MAX_DEVICES) {
3254			err = USB_ERR_IOERROR;
3255			goto done;
3256		}
3257		sc->sc_addr = value;
3258		break;
3259	case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3260		if ((value != 0) && (value != 1)) {
3261			err = USB_ERR_IOERROR;
3262			goto done;
3263		}
3264		sc->sc_conf = value;
3265		break;
3266	case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3267		break;
3268	case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3269	case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3270	case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3271		err = USB_ERR_IOERROR;
3272		goto done;
3273	case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3274		break;
3275	case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3276		break;
3277		/* Hub requests */
3278	case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3279		break;
3280	case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3281		DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3282
3283		if ((index < 1) ||
3284		    (index > sc->sc_noport)) {
3285			err = USB_ERR_IOERROR;
3286			goto done;
3287		}
3288		port = EHCI_PORTSC(index);
3289		v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3290		switch (value) {
3291		case UHF_PORT_ENABLE:
3292			EOWRITE4(sc, port, v & ~EHCI_PS_PE);
3293			break;
3294		case UHF_PORT_SUSPEND:
3295			if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) {
3296
3297				/*
3298				 * waking up a High Speed device is rather
3299				 * complicated if
3300				 */
3301				EOWRITE4(sc, port, v | EHCI_PS_FPR);
3302			}
3303			/* wait 20ms for resume sequence to complete */
3304			usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3305
3306			EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP |
3307			    EHCI_PS_FPR | (3 << 10) /* High Speed */ ));
3308
3309			/* 4ms settle time */
3310			usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3311			break;
3312		case UHF_PORT_POWER:
3313			EOWRITE4(sc, port, v & ~EHCI_PS_PP);
3314			break;
3315		case UHF_PORT_TEST:
3316			DPRINTFN(3, "clear port test "
3317			    "%d\n", index);
3318			break;
3319		case UHF_PORT_INDICATOR:
3320			DPRINTFN(3, "clear port ind "
3321			    "%d\n", index);
3322			EOWRITE4(sc, port, v & ~EHCI_PS_PIC);
3323			break;
3324		case UHF_C_PORT_CONNECTION:
3325			EOWRITE4(sc, port, v | EHCI_PS_CSC);
3326			break;
3327		case UHF_C_PORT_ENABLE:
3328			EOWRITE4(sc, port, v | EHCI_PS_PEC);
3329			break;
3330		case UHF_C_PORT_SUSPEND:
3331			EOWRITE4(sc, port, v | EHCI_PS_SUSP);
3332			break;
3333		case UHF_C_PORT_OVER_CURRENT:
3334			EOWRITE4(sc, port, v | EHCI_PS_OCC);
3335			break;
3336		case UHF_C_PORT_RESET:
3337			sc->sc_isreset = 0;
3338			break;
3339		default:
3340			err = USB_ERR_IOERROR;
3341			goto done;
3342		}
3343		break;
3344	case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3345		if ((value & 0xff) != 0) {
3346			err = USB_ERR_IOERROR;
3347			goto done;
3348		}
3349		v = EREAD4(sc, EHCI_HCSPARAMS);
3350
3351		sc->sc_hub_desc.hubd = ehci_hubd;
3352		sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3353
3354		if (EHCI_HCS_PPC(v))
3355			i = UHD_PWR_INDIVIDUAL;
3356		else
3357			i = UHD_PWR_NO_SWITCH;
3358
3359		if (EHCI_HCS_P_INDICATOR(v))
3360			i |= UHD_PORT_IND;
3361
3362		USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3363		/* XXX can't find out? */
3364		sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200;
3365		/* XXX don't know if ports are removable or not */
3366		sc->sc_hub_desc.hubd.bDescLength =
3367		    8 + ((sc->sc_noport + 7) / 8);
3368		len = sc->sc_hub_desc.hubd.bDescLength;
3369		break;
3370	case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3371		len = 16;
3372		bzero(sc->sc_hub_desc.temp, 16);
3373		break;
3374	case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3375		DPRINTFN(9, "get port status i=%d\n",
3376		    index);
3377		if ((index < 1) ||
3378		    (index > sc->sc_noport)) {
3379			err = USB_ERR_IOERROR;
3380			goto done;
3381		}
3382		v = EOREAD4(sc, EHCI_PORTSC(index));
3383		DPRINTFN(9, "port status=0x%04x\n", v);
3384		if (sc->sc_flags & (EHCI_SCFLG_FORCESPEED | EHCI_SCFLG_TT)) {
3385			if ((v & 0xc000000) == 0x8000000)
3386				i = UPS_HIGH_SPEED;
3387			else if ((v & 0xc000000) == 0x4000000)
3388				i = UPS_LOW_SPEED;
3389			else
3390				i = 0;
3391		} else {
3392			i = UPS_HIGH_SPEED;
3393		}
3394		if (v & EHCI_PS_CS)
3395			i |= UPS_CURRENT_CONNECT_STATUS;
3396		if (v & EHCI_PS_PE)
3397			i |= UPS_PORT_ENABLED;
3398		if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR))
3399			i |= UPS_SUSPEND;
3400		if (v & EHCI_PS_OCA)
3401			i |= UPS_OVERCURRENT_INDICATOR;
3402		if (v & EHCI_PS_PR)
3403			i |= UPS_RESET;
3404		if (v & EHCI_PS_PP)
3405			i |= UPS_PORT_POWER;
3406		USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3407		i = 0;
3408		if (v & EHCI_PS_CSC)
3409			i |= UPS_C_CONNECT_STATUS;
3410		if (v & EHCI_PS_PEC)
3411			i |= UPS_C_PORT_ENABLED;
3412		if (v & EHCI_PS_OCC)
3413			i |= UPS_C_OVERCURRENT_INDICATOR;
3414		if (v & EHCI_PS_FPR)
3415			i |= UPS_C_SUSPEND;
3416		if (sc->sc_isreset)
3417			i |= UPS_C_PORT_RESET;
3418		USETW(sc->sc_hub_desc.ps.wPortChange, i);
3419		len = sizeof(sc->sc_hub_desc.ps);
3420		break;
3421	case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3422		err = USB_ERR_IOERROR;
3423		goto done;
3424	case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3425		break;
3426	case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3427		if ((index < 1) ||
3428		    (index > sc->sc_noport)) {
3429			err = USB_ERR_IOERROR;
3430			goto done;
3431		}
3432		port = EHCI_PORTSC(index);
3433		v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3434		switch (value) {
3435		case UHF_PORT_ENABLE:
3436			EOWRITE4(sc, port, v | EHCI_PS_PE);
3437			break;
3438		case UHF_PORT_SUSPEND:
3439			EOWRITE4(sc, port, v | EHCI_PS_SUSP);
3440			break;
3441		case UHF_PORT_RESET:
3442			DPRINTFN(6, "reset port %d\n", index);
3443#ifdef USB_DEBUG
3444			if (ehcinohighspeed) {
3445				/*
3446				 * Connect USB device to companion
3447				 * controller.
3448				 */
3449				ehci_disown(sc, index, 1);
3450				break;
3451			}
3452#endif
3453			if (EHCI_PS_IS_LOWSPEED(v) &&
3454			    (sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3455				/* Low speed device, give up ownership. */
3456				ehci_disown(sc, index, 1);
3457				break;
3458			}
3459			/* Start reset sequence. */
3460			v &= ~(EHCI_PS_PE | EHCI_PS_PR);
3461			EOWRITE4(sc, port, v | EHCI_PS_PR);
3462
3463			/* Wait for reset to complete. */
3464			usb_pause_mtx(&sc->sc_bus.bus_mtx,
3465			    USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY));
3466
3467			/* Terminate reset sequence. */
3468			if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM))
3469				EOWRITE4(sc, port, v);
3470
3471			/* Wait for HC to complete reset. */
3472			usb_pause_mtx(&sc->sc_bus.bus_mtx,
3473			    USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE));
3474
3475			v = EOREAD4(sc, port);
3476			DPRINTF("ehci after reset, status=0x%08x\n", v);
3477			if (v & EHCI_PS_PR) {
3478				device_printf(sc->sc_bus.bdev,
3479				    "port reset timeout\n");
3480				err = USB_ERR_TIMEOUT;
3481				goto done;
3482			}
3483			if (!(v & EHCI_PS_PE) &&
3484			    (sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3485				/* Not a high speed device, give up ownership.*/
3486				ehci_disown(sc, index, 0);
3487				break;
3488			}
3489			sc->sc_isreset = 1;
3490			DPRINTF("ehci port %d reset, status = 0x%08x\n",
3491			    index, v);
3492			break;
3493
3494		case UHF_PORT_POWER:
3495			DPRINTFN(3, "set port power %d\n", index);
3496			EOWRITE4(sc, port, v | EHCI_PS_PP);
3497			break;
3498
3499		case UHF_PORT_TEST:
3500			DPRINTFN(3, "set port test %d\n", index);
3501			break;
3502
3503		case UHF_PORT_INDICATOR:
3504			DPRINTFN(3, "set port ind %d\n", index);
3505			EOWRITE4(sc, port, v | EHCI_PS_PIC);
3506			break;
3507
3508		default:
3509			err = USB_ERR_IOERROR;
3510			goto done;
3511		}
3512		break;
3513	case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3514	case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3515	case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3516	case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3517		break;
3518	default:
3519		err = USB_ERR_IOERROR;
3520		goto done;
3521	}
3522done:
3523	*plength = len;
3524	*pptr = ptr;
3525	return (err);
3526}
3527
3528static void
3529ehci_xfer_setup(struct usb_setup_params *parm)
3530{
3531	struct usb_page_search page_info;
3532	struct usb_page_cache *pc;
3533	ehci_softc_t *sc;
3534	struct usb_xfer *xfer;
3535	void *last_obj;
3536	uint32_t nqtd;
3537	uint32_t nqh;
3538	uint32_t nsitd;
3539	uint32_t nitd;
3540	uint32_t n;
3541
3542	sc = EHCI_BUS2SC(parm->udev->bus);
3543	xfer = parm->curr_xfer;
3544
3545	nqtd = 0;
3546	nqh = 0;
3547	nsitd = 0;
3548	nitd = 0;
3549
3550	/*
3551	 * compute maximum number of some structures
3552	 */
3553	if (parm->methods == &ehci_device_ctrl_methods) {
3554
3555		/*
3556		 * The proof for the "nqtd" formula is illustrated like
3557		 * this:
3558		 *
3559		 * +------------------------------------+
3560		 * |                                    |
3561		 * |         |remainder ->              |
3562		 * |   +-----+---+                      |
3563		 * |   | xxx | x | frm 0                |
3564		 * |   +-----+---++                     |
3565		 * |   | xxx | xx | frm 1               |
3566		 * |   +-----+----+                     |
3567		 * |            ...                     |
3568		 * +------------------------------------+
3569		 *
3570		 * "xxx" means a completely full USB transfer descriptor
3571		 *
3572		 * "x" and "xx" means a short USB packet
3573		 *
3574		 * For the remainder of an USB transfer modulo
3575		 * "max_data_length" we need two USB transfer descriptors.
3576		 * One to transfer the remaining data and one to finalise
3577		 * with a zero length packet in case the "force_short_xfer"
3578		 * flag is set. We only need two USB transfer descriptors in
3579		 * the case where the transfer length of the first one is a
3580		 * factor of "max_frame_size". The rest of the needed USB
3581		 * transfer descriptors is given by the buffer size divided
3582		 * by the maximum data payload.
3583		 */
3584		parm->hc_max_packet_size = 0x400;
3585		parm->hc_max_packet_count = 1;
3586		parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3587		xfer->flags_int.bdma_enable = 1;
3588
3589		usbd_transfer_setup_sub(parm);
3590
3591		nqh = 1;
3592		nqtd = ((2 * xfer->nframes) + 1	/* STATUS */
3593		    + (xfer->max_data_length / xfer->max_hc_frame_size));
3594
3595	} else if (parm->methods == &ehci_device_bulk_methods) {
3596
3597		parm->hc_max_packet_size = 0x400;
3598		parm->hc_max_packet_count = 1;
3599		parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3600		xfer->flags_int.bdma_enable = 1;
3601
3602		usbd_transfer_setup_sub(parm);
3603
3604		nqh = 1;
3605		nqtd = ((2 * xfer->nframes)
3606		    + (xfer->max_data_length / xfer->max_hc_frame_size));
3607
3608	} else if (parm->methods == &ehci_device_intr_methods) {
3609
3610		if (parm->speed == USB_SPEED_HIGH) {
3611			parm->hc_max_packet_size = 0x400;
3612			parm->hc_max_packet_count = 3;
3613		} else if (parm->speed == USB_SPEED_FULL) {
3614			parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME;
3615			parm->hc_max_packet_count = 1;
3616		} else {
3617			parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8;
3618			parm->hc_max_packet_count = 1;
3619		}
3620
3621		parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3622		xfer->flags_int.bdma_enable = 1;
3623
3624		usbd_transfer_setup_sub(parm);
3625
3626		nqh = 1;
3627		nqtd = ((2 * xfer->nframes)
3628		    + (xfer->max_data_length / xfer->max_hc_frame_size));
3629
3630	} else if (parm->methods == &ehci_device_isoc_fs_methods) {
3631
3632		parm->hc_max_packet_size = 0x3FF;
3633		parm->hc_max_packet_count = 1;
3634		parm->hc_max_frame_size = 0x3FF;
3635		xfer->flags_int.bdma_enable = 1;
3636
3637		usbd_transfer_setup_sub(parm);
3638
3639		nsitd = xfer->nframes;
3640
3641	} else if (parm->methods == &ehci_device_isoc_hs_methods) {
3642
3643		parm->hc_max_packet_size = 0x400;
3644		parm->hc_max_packet_count = 3;
3645		parm->hc_max_frame_size = 0xC00;
3646		xfer->flags_int.bdma_enable = 1;
3647
3648		usbd_transfer_setup_sub(parm);
3649
3650		nitd = ((xfer->nframes + 7) / 8) <<
3651		    usbd_xfer_get_fps_shift(xfer);
3652
3653	} else {
3654
3655		parm->hc_max_packet_size = 0x400;
3656		parm->hc_max_packet_count = 1;
3657		parm->hc_max_frame_size = 0x400;
3658
3659		usbd_transfer_setup_sub(parm);
3660	}
3661
3662alloc_dma_set:
3663
3664	if (parm->err) {
3665		return;
3666	}
3667	/*
3668	 * Allocate queue heads and transfer descriptors
3669	 */
3670	last_obj = NULL;
3671
3672	if (usbd_transfer_setup_sub_malloc(
3673	    parm, &pc, sizeof(ehci_itd_t),
3674	    EHCI_ITD_ALIGN, nitd)) {
3675		parm->err = USB_ERR_NOMEM;
3676		return;
3677	}
3678	if (parm->buf) {
3679		for (n = 0; n != nitd; n++) {
3680			ehci_itd_t *td;
3681
3682			usbd_get_page(pc + n, 0, &page_info);
3683
3684			td = page_info.buffer;
3685
3686			/* init TD */
3687			td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD);
3688			td->obj_next = last_obj;
3689			td->page_cache = pc + n;
3690
3691			last_obj = td;
3692
3693			usb_pc_cpu_flush(pc + n);
3694		}
3695	}
3696	if (usbd_transfer_setup_sub_malloc(
3697	    parm, &pc, sizeof(ehci_sitd_t),
3698	    EHCI_SITD_ALIGN, nsitd)) {
3699		parm->err = USB_ERR_NOMEM;
3700		return;
3701	}
3702	if (parm->buf) {
3703		for (n = 0; n != nsitd; n++) {
3704			ehci_sitd_t *td;
3705
3706			usbd_get_page(pc + n, 0, &page_info);
3707
3708			td = page_info.buffer;
3709
3710			/* init TD */
3711			td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD);
3712			td->obj_next = last_obj;
3713			td->page_cache = pc + n;
3714
3715			last_obj = td;
3716
3717			usb_pc_cpu_flush(pc + n);
3718		}
3719	}
3720	if (usbd_transfer_setup_sub_malloc(
3721	    parm, &pc, sizeof(ehci_qtd_t),
3722	    EHCI_QTD_ALIGN, nqtd)) {
3723		parm->err = USB_ERR_NOMEM;
3724		return;
3725	}
3726	if (parm->buf) {
3727		for (n = 0; n != nqtd; n++) {
3728			ehci_qtd_t *qtd;
3729
3730			usbd_get_page(pc + n, 0, &page_info);
3731
3732			qtd = page_info.buffer;
3733
3734			/* init TD */
3735			qtd->qtd_self = htohc32(sc, page_info.physaddr);
3736			qtd->obj_next = last_obj;
3737			qtd->page_cache = pc + n;
3738
3739			last_obj = qtd;
3740
3741			usb_pc_cpu_flush(pc + n);
3742		}
3743	}
3744	xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3745
3746	last_obj = NULL;
3747
3748	if (usbd_transfer_setup_sub_malloc(
3749	    parm, &pc, sizeof(ehci_qh_t),
3750	    EHCI_QH_ALIGN, nqh)) {
3751		parm->err = USB_ERR_NOMEM;
3752		return;
3753	}
3754	if (parm->buf) {
3755		for (n = 0; n != nqh; n++) {
3756			ehci_qh_t *qh;
3757
3758			usbd_get_page(pc + n, 0, &page_info);
3759
3760			qh = page_info.buffer;
3761
3762			/* init QH */
3763			qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH);
3764			qh->obj_next = last_obj;
3765			qh->page_cache = pc + n;
3766
3767			last_obj = qh;
3768
3769			usb_pc_cpu_flush(pc + n);
3770		}
3771	}
3772	xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj;
3773
3774	if (!xfer->flags_int.curr_dma_set) {
3775		xfer->flags_int.curr_dma_set = 1;
3776		goto alloc_dma_set;
3777	}
3778}
3779
3780static void
3781ehci_xfer_unsetup(struct usb_xfer *xfer)
3782{
3783	return;
3784}
3785
3786static void
3787ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3788    struct usb_endpoint *ep)
3789{
3790	ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3791
3792	DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
3793	    ep, udev->address,
3794	    edesc->bEndpointAddress, udev->flags.usb_mode,
3795	    sc->sc_addr);
3796
3797	if (udev->flags.usb_mode != USB_MODE_HOST) {
3798		/* not supported */
3799		return;
3800	}
3801	if (udev->device_index != sc->sc_addr) {
3802
3803		if ((udev->speed != USB_SPEED_HIGH) &&
3804		    ((udev->hs_hub_addr == 0) ||
3805		    (udev->hs_port_no == 0) ||
3806		    (udev->parent_hs_hub == NULL) ||
3807		    (udev->parent_hs_hub->hub == NULL))) {
3808			/* We need a transaction translator */
3809			goto done;
3810		}
3811		switch (edesc->bmAttributes & UE_XFERTYPE) {
3812		case UE_CONTROL:
3813			ep->methods = &ehci_device_ctrl_methods;
3814			break;
3815		case UE_INTERRUPT:
3816			ep->methods = &ehci_device_intr_methods;
3817			break;
3818		case UE_ISOCHRONOUS:
3819			if (udev->speed == USB_SPEED_HIGH) {
3820				ep->methods = &ehci_device_isoc_hs_methods;
3821			} else if (udev->speed == USB_SPEED_FULL) {
3822				ep->methods = &ehci_device_isoc_fs_methods;
3823			}
3824			break;
3825		case UE_BULK:
3826			ep->methods = &ehci_device_bulk_methods;
3827			break;
3828		default:
3829			/* do nothing */
3830			break;
3831		}
3832	}
3833done:
3834	return;
3835}
3836
3837static void
3838ehci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
3839{
3840	/*
3841	 * Wait until the hardware has finished any possible use of
3842	 * the transfer descriptor(s) and QH
3843	 */
3844	*pus = (188);			/* microseconds */
3845}
3846
3847static void
3848ehci_device_resume(struct usb_device *udev)
3849{
3850	ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3851	struct usb_xfer *xfer;
3852	struct usb_pipe_methods *methods;
3853
3854	DPRINTF("\n");
3855
3856	USB_BUS_LOCK(udev->bus);
3857
3858	TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3859
3860		if (xfer->xroot->udev == udev) {
3861
3862			methods = xfer->endpoint->methods;
3863
3864			if ((methods == &ehci_device_bulk_methods) ||
3865			    (methods == &ehci_device_ctrl_methods)) {
3866				EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3867				    sc->sc_async_p_last);
3868			}
3869			if (methods == &ehci_device_intr_methods) {
3870				EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3871				    sc->sc_intr_p_last[xfer->qh_pos]);
3872			}
3873		}
3874	}
3875
3876	USB_BUS_UNLOCK(udev->bus);
3877
3878	return;
3879}
3880
3881static void
3882ehci_device_suspend(struct usb_device *udev)
3883{
3884	ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3885	struct usb_xfer *xfer;
3886	struct usb_pipe_methods *methods;
3887
3888	DPRINTF("\n");
3889
3890	USB_BUS_LOCK(udev->bus);
3891
3892	TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3893
3894		if (xfer->xroot->udev == udev) {
3895
3896			methods = xfer->endpoint->methods;
3897
3898			if ((methods == &ehci_device_bulk_methods) ||
3899			    (methods == &ehci_device_ctrl_methods)) {
3900				EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3901				    sc->sc_async_p_last);
3902			}
3903			if (methods == &ehci_device_intr_methods) {
3904				EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3905				    sc->sc_intr_p_last[xfer->qh_pos]);
3906			}
3907		}
3908	}
3909
3910	USB_BUS_UNLOCK(udev->bus);
3911
3912	return;
3913}
3914
3915static void
3916ehci_set_hw_power(struct usb_bus *bus)
3917{
3918	ehci_softc_t *sc = EHCI_BUS2SC(bus);
3919	uint32_t temp;
3920	uint32_t flags;
3921
3922	DPRINTF("\n");
3923
3924	USB_BUS_LOCK(bus);
3925
3926	flags = bus->hw_power_state;
3927
3928	temp = EOREAD4(sc, EHCI_USBCMD);
3929
3930	temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
3931
3932	if (flags & (USB_HW_POWER_CONTROL |
3933	    USB_HW_POWER_BULK)) {
3934		DPRINTF("Async is active\n");
3935		temp |= EHCI_CMD_ASE;
3936	}
3937	if (flags & (USB_HW_POWER_INTERRUPT |
3938	    USB_HW_POWER_ISOC)) {
3939		DPRINTF("Periodic is active\n");
3940		temp |= EHCI_CMD_PSE;
3941	}
3942	EOWRITE4(sc, EHCI_USBCMD, temp);
3943
3944	USB_BUS_UNLOCK(bus);
3945
3946	return;
3947}
3948
3949struct usb_bus_methods ehci_bus_methods =
3950{
3951	.endpoint_init = ehci_ep_init,
3952	.xfer_setup = ehci_xfer_setup,
3953	.xfer_unsetup = ehci_xfer_unsetup,
3954	.get_dma_delay = ehci_get_dma_delay,
3955	.device_resume = ehci_device_resume,
3956	.device_suspend = ehci_device_suspend,
3957	.set_hw_power = ehci_set_hw_power,
3958	.roothub_exec = ehci_roothub_exec,
3959	.xfer_poll = ehci_do_poll,
3960};
3961