1/* $FreeBSD$ */ 2/*- 3 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved. 5 * Copyright (c) 2004 Lennart Augustsson. All rights reserved. 6 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30/* 31 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 32 * 33 * The EHCI 0.96 spec can be found at 34 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 35 * The EHCI 1.0 spec can be found at 36 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 37 * and the USB 2.0 spec at 38 * http://www.usb.org/developers/docs/usb_20.zip 39 * 40 */ 41 42/* 43 * TODO: 44 * 1) command failures are not recovered correctly 45 */ 46 47#ifdef USB_GLOBAL_INCLUDE_FILE 48#include USB_GLOBAL_INCLUDE_FILE 49#else 50#include <sys/stdint.h> 51#include <sys/stddef.h> 52#include <sys/param.h> 53#include <sys/queue.h> 54#include <sys/types.h> 55#include <sys/systm.h> 56#include <sys/kernel.h> 57#include <sys/bus.h> 58#include <sys/module.h> 59#include <sys/lock.h> 60#include <sys/mutex.h> 61#include <sys/condvar.h> 62#include <sys/sysctl.h> 63#include <sys/sx.h> 64#include <sys/unistd.h> 65#include <sys/callout.h> 66#include <sys/malloc.h> 67#include <sys/priv.h> 68 69#include <dev/usb/usb.h> 70#include <dev/usb/usbdi.h> 71 72#define USB_DEBUG_VAR ehcidebug 73 74#include <dev/usb/usb_core.h> 75#include <dev/usb/usb_debug.h> 76#include <dev/usb/usb_busdma.h> 77#include <dev/usb/usb_process.h> 78#include <dev/usb/usb_transfer.h> 79#include <dev/usb/usb_device.h> 80#include <dev/usb/usb_hub.h> 81#include <dev/usb/usb_util.h> 82 83#include <dev/usb/usb_controller.h> 84#include <dev/usb/usb_bus.h> 85#endif /* USB_GLOBAL_INCLUDE_FILE */ 86 87#include <dev/usb/controller/ehci.h> 88#include <dev/usb/controller/ehcireg.h> 89 90#define EHCI_BUS2SC(bus) \ 91 ((ehci_softc_t *)(((uint8_t *)(bus)) - \ 92 ((uint8_t *)&(((ehci_softc_t *)0)->sc_bus)))) 93 94#ifdef USB_DEBUG 95static int ehcidebug = 0; 96static int ehcinohighspeed = 0; 97static int ehciiaadbug = 0; 98static int ehcilostintrbug = 0; 99 100static SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci"); 101SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RWTUN, 102 &ehcidebug, 0, "Debug level"); 103SYSCTL_INT(_hw_usb_ehci, OID_AUTO, no_hs, CTLFLAG_RWTUN, 104 &ehcinohighspeed, 0, "Disable High Speed USB"); 105SYSCTL_INT(_hw_usb_ehci, OID_AUTO, iaadbug, CTLFLAG_RWTUN, 106 &ehciiaadbug, 0, "Enable doorbell bug workaround"); 107SYSCTL_INT(_hw_usb_ehci, OID_AUTO, lostintrbug, CTLFLAG_RWTUN, 108 &ehcilostintrbug, 0, "Enable lost interrupt bug workaround"); 109 110static void ehci_dump_regs(ehci_softc_t *sc); 111static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh); 112 113#endif 114 115#define EHCI_INTR_ENDPT 1 116 117static const struct usb_bus_methods ehci_bus_methods; 118static const struct usb_pipe_methods ehci_device_bulk_methods; 119static const struct usb_pipe_methods ehci_device_ctrl_methods; 120static const struct usb_pipe_methods ehci_device_intr_methods; 121static const struct usb_pipe_methods ehci_device_isoc_fs_methods; 122static const struct usb_pipe_methods ehci_device_isoc_hs_methods; 123 124static void ehci_do_poll(struct usb_bus *); 125static void ehci_device_done(struct usb_xfer *, usb_error_t); 126static uint8_t ehci_check_transfer(struct usb_xfer *); 127static void ehci_timeout(void *); 128static void ehci_poll_timeout(void *); 129 130static void ehci_root_intr(ehci_softc_t *sc); 131 132struct ehci_std_temp { 133 ehci_softc_t *sc; 134 struct usb_page_cache *pc; 135 ehci_qtd_t *td; 136 ehci_qtd_t *td_next; 137 uint32_t average; 138 uint32_t qtd_status; 139 uint32_t len; 140 uint16_t max_frame_size; 141 uint8_t shortpkt; 142 uint8_t auto_data_toggle; 143 uint8_t setup_alt_next; 144 uint8_t last_frame; 145}; 146 147void 148ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 149{ 150 ehci_softc_t *sc = EHCI_BUS2SC(bus); 151 uint32_t i; 152 153 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 154 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN); 155 156 cb(bus, &sc->sc_hw.terminate_pc, &sc->sc_hw.terminate_pg, 157 sizeof(struct ehci_qh_sub), EHCI_QH_ALIGN); 158 159 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg, 160 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 161 162 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 163 cb(bus, sc->sc_hw.intr_start_pc + i, 164 sc->sc_hw.intr_start_pg + i, 165 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 166 } 167 168 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 169 cb(bus, sc->sc_hw.isoc_hs_start_pc + i, 170 sc->sc_hw.isoc_hs_start_pg + i, 171 sizeof(ehci_itd_t), EHCI_ITD_ALIGN); 172 } 173 174 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 175 cb(bus, sc->sc_hw.isoc_fs_start_pc + i, 176 sc->sc_hw.isoc_fs_start_pg + i, 177 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN); 178 } 179} 180 181usb_error_t 182ehci_reset(ehci_softc_t *sc) 183{ 184 uint32_t hcr; 185 int i; 186 187 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 188 for (i = 0; i < 100; i++) { 189 usb_pause_mtx(NULL, hz / 128); 190 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 191 if (!hcr) { 192 if (sc->sc_vendor_post_reset != NULL) 193 sc->sc_vendor_post_reset(sc); 194 return (0); 195 } 196 } 197 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 198 return (USB_ERR_IOERROR); 199} 200 201static usb_error_t 202ehci_hcreset(ehci_softc_t *sc) 203{ 204 uint32_t hcr; 205 int i; 206 207 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 208 for (i = 0; i < 100; i++) { 209 usb_pause_mtx(NULL, hz / 128); 210 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 211 if (hcr) 212 break; 213 } 214 if (!hcr) 215 /* 216 * Fall through and try reset anyway even though 217 * Table 2-9 in the EHCI spec says this will result 218 * in undefined behavior. 219 */ 220 device_printf(sc->sc_bus.bdev, "stop timeout\n"); 221 222 return (ehci_reset(sc)); 223} 224 225static int 226ehci_init_sub(struct ehci_softc *sc) 227{ 228 struct usb_page_search buf_res; 229 uint32_t cparams; 230 uint32_t hcr; 231 uint8_t i; 232 233 cparams = EREAD4(sc, EHCI_HCCPARAMS); 234 235 DPRINTF("cparams=0x%x\n", cparams); 236 237 if (EHCI_HCC_64BIT(cparams)) { 238 DPRINTF("HCC uses 64-bit structures\n"); 239 240 /* MUST clear segment register if 64 bit capable */ 241 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 242 } 243 244 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 245 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 246 247 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 248 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 249 250 /* enable interrupts */ 251 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 252 253 /* turn on controller */ 254 EOWRITE4(sc, EHCI_USBCMD, 255 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */ 256 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 257 EHCI_CMD_ASE | 258 EHCI_CMD_PSE | 259 EHCI_CMD_RS); 260 261 /* Take over port ownership */ 262 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 263 264 for (i = 0; i < 100; i++) { 265 usb_pause_mtx(NULL, hz / 128); 266 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 267 if (!hcr) { 268 break; 269 } 270 } 271 if (hcr) { 272 device_printf(sc->sc_bus.bdev, "run timeout\n"); 273 return (USB_ERR_IOERROR); 274 } 275 return (USB_ERR_NORMAL_COMPLETION); 276} 277 278usb_error_t 279ehci_init(ehci_softc_t *sc) 280{ 281 struct usb_page_search buf_res; 282 uint32_t version; 283 uint32_t sparams; 284 uint16_t i; 285 uint16_t x; 286 uint16_t y; 287 uint16_t bit; 288 usb_error_t err = 0; 289 290 DPRINTF("start\n"); 291 292 usb_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0); 293 usb_callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_mtx, 0); 294 295 sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 296 297#ifdef USB_DEBUG 298 if (ehciiaadbug) 299 sc->sc_flags |= EHCI_SCFLG_IAADBUG; 300 if (ehcilostintrbug) 301 sc->sc_flags |= EHCI_SCFLG_LOSTINTRBUG; 302 if (ehcidebug > 2) { 303 ehci_dump_regs(sc); 304 } 305#endif 306 307 version = EHCI_HCIVERSION(EREAD4(sc, EHCI_CAPLEN_HCIVERSION)); 308 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n", 309 version >> 8, version & 0xff); 310 311 sparams = EREAD4(sc, EHCI_HCSPARAMS); 312 DPRINTF("sparams=0x%x\n", sparams); 313 314 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 315 sc->sc_bus.usbrev = USB_REV_2_0; 316 317 if (!(sc->sc_flags & EHCI_SCFLG_DONTRESET)) { 318 /* Reset the controller */ 319 DPRINTF("%s: resetting\n", 320 device_get_nameunit(sc->sc_bus.bdev)); 321 322 err = ehci_hcreset(sc); 323 if (err) { 324 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 325 return (err); 326 } 327 } 328 329 /* 330 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4 331 * bytes 2: 256*4 bytes 3: unknown 332 */ 333 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) { 334 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n"); 335 return (USB_ERR_IOERROR); 336 } 337 /* set up the bus struct */ 338 sc->sc_bus.methods = &ehci_bus_methods; 339 340 sc->sc_eintrs = EHCI_NORMAL_INTRS; 341 342 if (1) { 343 struct ehci_qh_sub *qh; 344 345 usbd_get_page(&sc->sc_hw.terminate_pc, 0, &buf_res); 346 347 qh = buf_res.buffer; 348 349 sc->sc_terminate_self = htohc32(sc, buf_res.physaddr); 350 351 /* init terminate TD */ 352 qh->qtd_next = 353 htohc32(sc, EHCI_LINK_TERMINATE); 354 qh->qtd_altnext = 355 htohc32(sc, EHCI_LINK_TERMINATE); 356 qh->qtd_status = 357 htohc32(sc, EHCI_QTD_HALTED); 358 } 359 360 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 361 ehci_qh_t *qh; 362 363 usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res); 364 365 qh = buf_res.buffer; 366 367 /* initialize page cache pointer */ 368 369 qh->page_cache = sc->sc_hw.intr_start_pc + i; 370 371 /* store a pointer to queue head */ 372 373 sc->sc_intr_p_last[i] = qh; 374 375 qh->qh_self = 376 htohc32(sc, buf_res.physaddr) | 377 htohc32(sc, EHCI_LINK_QH); 378 379 qh->qh_endp = 380 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 381 qh->qh_endphub = 382 htohc32(sc, EHCI_QH_SET_MULT(1)); 383 qh->qh_curqtd = 0; 384 385 qh->qh_qtd.qtd_next = 386 htohc32(sc, EHCI_LINK_TERMINATE); 387 qh->qh_qtd.qtd_altnext = 388 htohc32(sc, EHCI_LINK_TERMINATE); 389 qh->qh_qtd.qtd_status = 390 htohc32(sc, EHCI_QTD_HALTED); 391 } 392 393 /* 394 * the QHs are arranged to give poll intervals that are 395 * powers of 2 times 1ms 396 */ 397 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 398 while (bit) { 399 x = bit; 400 while (x & bit) { 401 ehci_qh_t *qh_x; 402 ehci_qh_t *qh_y; 403 404 y = (x ^ bit) | (bit / 2); 405 406 qh_x = sc->sc_intr_p_last[x]; 407 qh_y = sc->sc_intr_p_last[y]; 408 409 /* 410 * the next QH has half the poll interval 411 */ 412 qh_x->qh_link = qh_y->qh_self; 413 414 x++; 415 } 416 bit >>= 1; 417 } 418 419 if (1) { 420 ehci_qh_t *qh; 421 422 qh = sc->sc_intr_p_last[0]; 423 424 /* the last (1ms) QH terminates */ 425 qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE); 426 } 427 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 428 ehci_sitd_t *sitd; 429 ehci_itd_t *itd; 430 431 usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res); 432 433 sitd = buf_res.buffer; 434 435 /* initialize page cache pointer */ 436 437 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i; 438 439 /* store a pointer to the transfer descriptor */ 440 441 sc->sc_isoc_fs_p_last[i] = sitd; 442 443 /* initialize full speed isochronous */ 444 445 sitd->sitd_self = 446 htohc32(sc, buf_res.physaddr) | 447 htohc32(sc, EHCI_LINK_SITD); 448 449 sitd->sitd_back = 450 htohc32(sc, EHCI_LINK_TERMINATE); 451 452 sitd->sitd_next = 453 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self; 454 455 456 usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res); 457 458 itd = buf_res.buffer; 459 460 /* initialize page cache pointer */ 461 462 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i; 463 464 /* store a pointer to the transfer descriptor */ 465 466 sc->sc_isoc_hs_p_last[i] = itd; 467 468 /* initialize high speed isochronous */ 469 470 itd->itd_self = 471 htohc32(sc, buf_res.physaddr) | 472 htohc32(sc, EHCI_LINK_ITD); 473 474 itd->itd_next = 475 sitd->sitd_self; 476 } 477 478 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 479 480 if (1) { 481 uint32_t *pframes; 482 483 pframes = buf_res.buffer; 484 485 /* 486 * execution order: 487 * pframes -> high speed isochronous -> 488 * full speed isochronous -> interrupt QH's 489 */ 490 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) { 491 pframes[i] = sc->sc_isoc_hs_p_last 492 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self; 493 } 494 } 495 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 496 497 if (1) { 498 499 ehci_qh_t *qh; 500 501 qh = buf_res.buffer; 502 503 /* initialize page cache pointer */ 504 505 qh->page_cache = &sc->sc_hw.async_start_pc; 506 507 /* store a pointer to the queue head */ 508 509 sc->sc_async_p_last = qh; 510 511 /* init dummy QH that starts the async list */ 512 513 qh->qh_self = 514 htohc32(sc, buf_res.physaddr) | 515 htohc32(sc, EHCI_LINK_QH); 516 517 /* fill the QH */ 518 qh->qh_endp = 519 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 520 qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1)); 521 qh->qh_link = qh->qh_self; 522 qh->qh_curqtd = 0; 523 524 /* fill the overlay qTD */ 525 qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE); 526 qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE); 527 qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED); 528 } 529 /* flush all cache into memory */ 530 531 usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc); 532 533#ifdef USB_DEBUG 534 if (ehcidebug) { 535 ehci_dump_sqh(sc, sc->sc_async_p_last); 536 } 537#endif 538 539 /* finial setup */ 540 err = ehci_init_sub(sc); 541 542 if (!err) { 543 /* catch any lost interrupts */ 544 ehci_do_poll(&sc->sc_bus); 545 } 546 return (err); 547} 548 549/* 550 * shut down the controller when the system is going down 551 */ 552void 553ehci_detach(ehci_softc_t *sc) 554{ 555 USB_BUS_LOCK(&sc->sc_bus); 556 557 usb_callout_stop(&sc->sc_tmo_pcd); 558 usb_callout_stop(&sc->sc_tmo_poll); 559 560 EOWRITE4(sc, EHCI_USBINTR, 0); 561 USB_BUS_UNLOCK(&sc->sc_bus); 562 563 if (ehci_hcreset(sc)) { 564 DPRINTF("reset failed!\n"); 565 } 566 567 /* XXX let stray task complete */ 568 usb_pause_mtx(NULL, hz / 20); 569 570 usb_callout_drain(&sc->sc_tmo_pcd); 571 usb_callout_drain(&sc->sc_tmo_poll); 572} 573 574static void 575ehci_suspend(ehci_softc_t *sc) 576{ 577 DPRINTF("stopping the HC\n"); 578 579 /* reset HC */ 580 ehci_hcreset(sc); 581} 582 583static void 584ehci_resume(ehci_softc_t *sc) 585{ 586 /* reset HC */ 587 ehci_hcreset(sc); 588 589 /* setup HC */ 590 ehci_init_sub(sc); 591 592 /* catch any lost interrupts */ 593 ehci_do_poll(&sc->sc_bus); 594} 595 596#ifdef USB_DEBUG 597static void 598ehci_dump_regs(ehci_softc_t *sc) 599{ 600 uint32_t i; 601 602 i = EOREAD4(sc, EHCI_USBCMD); 603 printf("cmd=0x%08x\n", i); 604 605 if (i & EHCI_CMD_ITC_1) 606 printf(" EHCI_CMD_ITC_1\n"); 607 if (i & EHCI_CMD_ITC_2) 608 printf(" EHCI_CMD_ITC_2\n"); 609 if (i & EHCI_CMD_ITC_4) 610 printf(" EHCI_CMD_ITC_4\n"); 611 if (i & EHCI_CMD_ITC_8) 612 printf(" EHCI_CMD_ITC_8\n"); 613 if (i & EHCI_CMD_ITC_16) 614 printf(" EHCI_CMD_ITC_16\n"); 615 if (i & EHCI_CMD_ITC_32) 616 printf(" EHCI_CMD_ITC_32\n"); 617 if (i & EHCI_CMD_ITC_64) 618 printf(" EHCI_CMD_ITC_64\n"); 619 if (i & EHCI_CMD_ASPME) 620 printf(" EHCI_CMD_ASPME\n"); 621 if (i & EHCI_CMD_ASPMC) 622 printf(" EHCI_CMD_ASPMC\n"); 623 if (i & EHCI_CMD_LHCR) 624 printf(" EHCI_CMD_LHCR\n"); 625 if (i & EHCI_CMD_IAAD) 626 printf(" EHCI_CMD_IAAD\n"); 627 if (i & EHCI_CMD_ASE) 628 printf(" EHCI_CMD_ASE\n"); 629 if (i & EHCI_CMD_PSE) 630 printf(" EHCI_CMD_PSE\n"); 631 if (i & EHCI_CMD_FLS_M) 632 printf(" EHCI_CMD_FLS_M\n"); 633 if (i & EHCI_CMD_HCRESET) 634 printf(" EHCI_CMD_HCRESET\n"); 635 if (i & EHCI_CMD_RS) 636 printf(" EHCI_CMD_RS\n"); 637 638 i = EOREAD4(sc, EHCI_USBSTS); 639 640 printf("sts=0x%08x\n", i); 641 642 if (i & EHCI_STS_ASS) 643 printf(" EHCI_STS_ASS\n"); 644 if (i & EHCI_STS_PSS) 645 printf(" EHCI_STS_PSS\n"); 646 if (i & EHCI_STS_REC) 647 printf(" EHCI_STS_REC\n"); 648 if (i & EHCI_STS_HCH) 649 printf(" EHCI_STS_HCH\n"); 650 if (i & EHCI_STS_IAA) 651 printf(" EHCI_STS_IAA\n"); 652 if (i & EHCI_STS_HSE) 653 printf(" EHCI_STS_HSE\n"); 654 if (i & EHCI_STS_FLR) 655 printf(" EHCI_STS_FLR\n"); 656 if (i & EHCI_STS_PCD) 657 printf(" EHCI_STS_PCD\n"); 658 if (i & EHCI_STS_ERRINT) 659 printf(" EHCI_STS_ERRINT\n"); 660 if (i & EHCI_STS_INT) 661 printf(" EHCI_STS_INT\n"); 662 663 printf("ien=0x%08x\n", 664 EOREAD4(sc, EHCI_USBINTR)); 665 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 666 EOREAD4(sc, EHCI_FRINDEX), 667 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 668 EOREAD4(sc, EHCI_PERIODICLISTBASE), 669 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 670 for (i = 1; i <= sc->sc_noport; i++) { 671 printf("port %d status=0x%08x\n", i, 672 EOREAD4(sc, EHCI_PORTSC(i))); 673 } 674} 675 676static void 677ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type) 678{ 679 link = hc32toh(sc, link); 680 printf("0x%08x", link); 681 if (link & EHCI_LINK_TERMINATE) 682 printf("<T>"); 683 else { 684 printf("<"); 685 if (type) { 686 switch (EHCI_LINK_TYPE(link)) { 687 case EHCI_LINK_ITD: 688 printf("ITD"); 689 break; 690 case EHCI_LINK_QH: 691 printf("QH"); 692 break; 693 case EHCI_LINK_SITD: 694 printf("SITD"); 695 break; 696 case EHCI_LINK_FSTN: 697 printf("FSTN"); 698 break; 699 } 700 } 701 printf(">"); 702 } 703} 704 705static void 706ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd) 707{ 708 uint32_t s; 709 710 printf(" next="); 711 ehci_dump_link(sc, qtd->qtd_next, 0); 712 printf(" altnext="); 713 ehci_dump_link(sc, qtd->qtd_altnext, 0); 714 printf("\n"); 715 s = hc32toh(sc, qtd->qtd_status); 716 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 717 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 718 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 719 printf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n", 720 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), 721 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE", 722 (s & EHCI_QTD_HALTED) ? "-HALTED" : "", 723 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "", 724 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "", 725 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "", 726 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "", 727 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "", 728 (s & EHCI_QTD_PINGSTATE) ? "-PING" : ""); 729 730 for (s = 0; s < 5; s++) { 731 printf(" buffer[%d]=0x%08x\n", s, 732 hc32toh(sc, qtd->qtd_buffer[s])); 733 } 734 for (s = 0; s < 5; s++) { 735 printf(" buffer_hi[%d]=0x%08x\n", s, 736 hc32toh(sc, qtd->qtd_buffer_hi[s])); 737 } 738} 739 740static uint8_t 741ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd) 742{ 743 uint8_t temp; 744 745 usb_pc_cpu_invalidate(sqtd->page_cache); 746 printf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self)); 747 ehci_dump_qtd(sc, sqtd); 748 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0; 749 return (temp); 750} 751 752static void 753ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd) 754{ 755 uint16_t i; 756 uint8_t stop; 757 758 stop = 0; 759 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) { 760 stop = ehci_dump_sqtd(sc, sqtd); 761 } 762 if (sqtd) { 763 printf("dump aborted, too many TDs\n"); 764 } 765} 766 767static void 768ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh) 769{ 770 uint32_t endp; 771 uint32_t endphub; 772 773 usb_pc_cpu_invalidate(qh->page_cache); 774 printf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F); 775 printf(" link="); 776 ehci_dump_link(sc, qh->qh_link, 1); 777 printf("\n"); 778 endp = hc32toh(sc, qh->qh_endp); 779 printf(" endp=0x%08x\n", endp); 780 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 781 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 782 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 783 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 784 printf(" mpl=0x%x ctl=%d nrl=%d\n", 785 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 786 EHCI_QH_GET_NRL(endp)); 787 endphub = hc32toh(sc, qh->qh_endphub); 788 printf(" endphub=0x%08x\n", endphub); 789 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 790 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 791 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 792 EHCI_QH_GET_MULT(endphub)); 793 printf(" curqtd="); 794 ehci_dump_link(sc, qh->qh_curqtd, 0); 795 printf("\n"); 796 printf("Overlay qTD:\n"); 797 ehci_dump_qtd(sc, (void *)&qh->qh_qtd); 798} 799 800static void 801ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd) 802{ 803 usb_pc_cpu_invalidate(sitd->page_cache); 804 printf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F); 805 printf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next)); 806 printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n", 807 hc32toh(sc, sitd->sitd_portaddr), 808 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN)) 809 ? "in" : "out", 810 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)), 811 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)), 812 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)), 813 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr))); 814 printf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask)); 815 printf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status), 816 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "", 817 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status))); 818 printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n", 819 hc32toh(sc, sitd->sitd_back), 820 hc32toh(sc, sitd->sitd_bp[0]), 821 hc32toh(sc, sitd->sitd_bp[1]), 822 hc32toh(sc, sitd->sitd_bp_hi[0]), 823 hc32toh(sc, sitd->sitd_bp_hi[1])); 824} 825 826static void 827ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd) 828{ 829 usb_pc_cpu_invalidate(itd->page_cache); 830 printf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F); 831 printf(" next=0x%08x\n", hc32toh(sc, itd->itd_next)); 832 printf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]), 833 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 834 printf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]), 835 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 836 printf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]), 837 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 838 printf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]), 839 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 840 printf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]), 841 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 842 printf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]), 843 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 844 printf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]), 845 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 846 printf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]), 847 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 848 printf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0])); 849 printf(" addr=0x%02x; endpt=0x%01x\n", 850 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])), 851 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0]))); 852 printf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1])); 853 printf(" dir=%s; mpl=0x%02x\n", 854 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out", 855 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1]))); 856 printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n", 857 hc32toh(sc, itd->itd_bp[2]), 858 hc32toh(sc, itd->itd_bp[3]), 859 hc32toh(sc, itd->itd_bp[4]), 860 hc32toh(sc, itd->itd_bp[5]), 861 hc32toh(sc, itd->itd_bp[6])); 862 printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n" 863 " 0x%08x,0x%08x,0x%08x\n", 864 hc32toh(sc, itd->itd_bp_hi[0]), 865 hc32toh(sc, itd->itd_bp_hi[1]), 866 hc32toh(sc, itd->itd_bp_hi[2]), 867 hc32toh(sc, itd->itd_bp_hi[3]), 868 hc32toh(sc, itd->itd_bp_hi[4]), 869 hc32toh(sc, itd->itd_bp_hi[5]), 870 hc32toh(sc, itd->itd_bp_hi[6])); 871} 872 873static void 874ehci_dump_isoc(ehci_softc_t *sc) 875{ 876 ehci_itd_t *itd; 877 ehci_sitd_t *sitd; 878 uint16_t max = 1000; 879 uint16_t pos; 880 881 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) & 882 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 883 884 printf("%s: isochronous dump from frame 0x%03x:\n", 885 __FUNCTION__, pos); 886 887 itd = sc->sc_isoc_hs_p_last[pos]; 888 sitd = sc->sc_isoc_fs_p_last[pos]; 889 890 while (itd && max && max--) { 891 ehci_dump_itd(sc, itd); 892 itd = itd->prev; 893 } 894 895 while (sitd && max && max--) { 896 ehci_dump_sitd(sc, sitd); 897 sitd = sitd->prev; 898 } 899} 900 901#endif 902 903static void 904ehci_transfer_intr_enqueue(struct usb_xfer *xfer) 905{ 906 /* check for early completion */ 907 if (ehci_check_transfer(xfer)) { 908 return; 909 } 910 /* put transfer on interrupt queue */ 911 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 912 913 /* start timeout, if any */ 914 if (xfer->timeout != 0) { 915 usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout); 916 } 917} 918 919#define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last) 920static ehci_sitd_t * 921_ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 922{ 923 DPRINTFN(11, "%p to %p\n", std, last); 924 925 /* (sc->sc_bus.mtx) must be locked */ 926 927 std->next = last->next; 928 std->sitd_next = last->sitd_next; 929 930 std->prev = last; 931 932 usb_pc_cpu_flush(std->page_cache); 933 934 /* 935 * the last->next->prev is never followed: std->next->prev = std; 936 */ 937 last->next = std; 938 last->sitd_next = std->sitd_self; 939 940 usb_pc_cpu_flush(last->page_cache); 941 942 return (std); 943} 944 945#define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last) 946static ehci_itd_t * 947_ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last) 948{ 949 DPRINTFN(11, "%p to %p\n", std, last); 950 951 /* (sc->sc_bus.mtx) must be locked */ 952 953 std->next = last->next; 954 std->itd_next = last->itd_next; 955 956 std->prev = last; 957 958 usb_pc_cpu_flush(std->page_cache); 959 960 /* 961 * the last->next->prev is never followed: std->next->prev = std; 962 */ 963 last->next = std; 964 last->itd_next = std->itd_self; 965 966 usb_pc_cpu_flush(last->page_cache); 967 968 return (std); 969} 970 971#define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last) 972static ehci_qh_t * 973_ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last) 974{ 975 DPRINTFN(11, "%p to %p\n", sqh, last); 976 977 if (sqh->prev != NULL) { 978 /* should not happen */ 979 DPRINTFN(0, "QH already linked!\n"); 980 return (last); 981 } 982 /* (sc->sc_bus.mtx) must be locked */ 983 984 sqh->next = last->next; 985 sqh->qh_link = last->qh_link; 986 987 sqh->prev = last; 988 989 usb_pc_cpu_flush(sqh->page_cache); 990 991 /* 992 * the last->next->prev is never followed: sqh->next->prev = sqh; 993 */ 994 995 last->next = sqh; 996 last->qh_link = sqh->qh_self; 997 998 usb_pc_cpu_flush(last->page_cache); 999 1000 return (sqh); 1001} 1002 1003#define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last) 1004static ehci_sitd_t * 1005_ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 1006{ 1007 DPRINTFN(11, "%p from %p\n", std, last); 1008 1009 /* (sc->sc_bus.mtx) must be locked */ 1010 1011 std->prev->next = std->next; 1012 std->prev->sitd_next = std->sitd_next; 1013 1014 usb_pc_cpu_flush(std->prev->page_cache); 1015 1016 if (std->next) { 1017 std->next->prev = std->prev; 1018 usb_pc_cpu_flush(std->next->page_cache); 1019 } 1020 return ((last == std) ? std->prev : last); 1021} 1022 1023#define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last) 1024static ehci_itd_t * 1025_ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1026{ 1027 DPRINTFN(11, "%p from %p\n", std, last); 1028 1029 /* (sc->sc_bus.mtx) must be locked */ 1030 1031 std->prev->next = std->next; 1032 std->prev->itd_next = std->itd_next; 1033 1034 usb_pc_cpu_flush(std->prev->page_cache); 1035 1036 if (std->next) { 1037 std->next->prev = std->prev; 1038 usb_pc_cpu_flush(std->next->page_cache); 1039 } 1040 return ((last == std) ? std->prev : last); 1041} 1042 1043#define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last) 1044static ehci_qh_t * 1045_ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1046{ 1047 DPRINTFN(11, "%p from %p\n", sqh, last); 1048 1049 /* (sc->sc_bus.mtx) must be locked */ 1050 1051 /* only remove if not removed from a queue */ 1052 if (sqh->prev) { 1053 1054 sqh->prev->next = sqh->next; 1055 sqh->prev->qh_link = sqh->qh_link; 1056 1057 usb_pc_cpu_flush(sqh->prev->page_cache); 1058 1059 if (sqh->next) { 1060 sqh->next->prev = sqh->prev; 1061 usb_pc_cpu_flush(sqh->next->page_cache); 1062 } 1063 last = ((last == sqh) ? sqh->prev : last); 1064 1065 sqh->prev = 0; 1066 1067 usb_pc_cpu_flush(sqh->page_cache); 1068 } 1069 return (last); 1070} 1071 1072static void 1073ehci_data_toggle_update(struct usb_xfer *xfer, uint16_t actlen, uint16_t xlen) 1074{ 1075 uint16_t rem; 1076 uint8_t dt; 1077 1078 /* count number of full packets */ 1079 dt = (actlen / xfer->max_packet_size) & 1; 1080 1081 /* compute remainder */ 1082 rem = actlen % xfer->max_packet_size; 1083 1084 if (rem > 0) 1085 dt ^= 1; /* short packet at the end */ 1086 else if (actlen != xlen) 1087 dt ^= 1; /* zero length packet at the end */ 1088 else if (xlen == 0) 1089 dt ^= 1; /* zero length transfer */ 1090 1091 xfer->endpoint->toggle_next ^= dt; 1092} 1093 1094static usb_error_t 1095ehci_non_isoc_done_sub(struct usb_xfer *xfer) 1096{ 1097 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1098 ehci_qtd_t *td; 1099 ehci_qtd_t *td_alt_next; 1100 uint32_t status; 1101 uint16_t len; 1102 1103 td = xfer->td_transfer_cache; 1104 td_alt_next = td->alt_next; 1105 1106 if (xfer->aframes != xfer->nframes) { 1107 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 1108 } 1109 while (1) { 1110 1111 usb_pc_cpu_invalidate(td->page_cache); 1112 status = hc32toh(sc, td->qtd_status); 1113 1114 len = EHCI_QTD_GET_BYTES(status); 1115 1116 /* 1117 * Verify the status length and 1118 * add the length to "frlengths[]": 1119 */ 1120 if (len > td->len) { 1121 /* should not happen */ 1122 DPRINTF("Invalid status length, " 1123 "0x%04x/0x%04x bytes\n", len, td->len); 1124 status |= EHCI_QTD_HALTED; 1125 } else if (xfer->aframes != xfer->nframes) { 1126 xfer->frlengths[xfer->aframes] += td->len - len; 1127 /* manually update data toggle */ 1128 ehci_data_toggle_update(xfer, td->len - len, td->len); 1129 } 1130 1131 /* Check for last transfer */ 1132 if (((void *)td) == xfer->td_transfer_last) { 1133 td = NULL; 1134 break; 1135 } 1136 /* Check for transfer error */ 1137 if (status & EHCI_QTD_HALTED) { 1138 /* the transfer is finished */ 1139 td = NULL; 1140 break; 1141 } 1142 /* Check for short transfer */ 1143 if (len > 0) { 1144 if (xfer->flags_int.short_frames_ok) { 1145 /* follow alt next */ 1146 td = td->alt_next; 1147 } else { 1148 /* the transfer is finished */ 1149 td = NULL; 1150 } 1151 break; 1152 } 1153 td = td->obj_next; 1154 1155 if (td->alt_next != td_alt_next) { 1156 /* this USB frame is complete */ 1157 break; 1158 } 1159 } 1160 1161 /* update transfer cache */ 1162 1163 xfer->td_transfer_cache = td; 1164 1165#ifdef USB_DEBUG 1166 if (status & EHCI_QTD_STATERRS) { 1167 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x" 1168 "status=%s%s%s%s%s%s%s%s\n", 1169 xfer->address, xfer->endpointno, xfer->aframes, 1170 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1171 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "", 1172 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "", 1173 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "", 1174 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "", 1175 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "", 1176 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "", 1177 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : ""); 1178 } 1179#endif 1180 if (status & EHCI_QTD_HALTED) { 1181 if ((xfer->xroot->udev->parent_hs_hub != NULL) || 1182 (xfer->xroot->udev->address != 0)) { 1183 /* try to separate I/O errors from STALL */ 1184 if (EHCI_QTD_GET_CERR(status) == 0) 1185 return (USB_ERR_IOERROR); 1186 } 1187 return (USB_ERR_STALLED); 1188 } 1189 return (USB_ERR_NORMAL_COMPLETION); 1190} 1191 1192static void 1193ehci_non_isoc_done(struct usb_xfer *xfer) 1194{ 1195 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1196 ehci_qh_t *qh; 1197 uint32_t status; 1198 usb_error_t err = 0; 1199 1200 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1201 xfer, xfer->endpoint); 1202 1203#ifdef USB_DEBUG 1204 if (ehcidebug > 10) { 1205 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1206 1207 ehci_dump_sqtds(sc, xfer->td_transfer_first); 1208 } 1209#endif 1210 1211 /* extract data toggle directly from the QH's overlay area */ 1212 1213 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1214 1215 usb_pc_cpu_invalidate(qh->page_cache); 1216 1217 status = hc32toh(sc, qh->qh_qtd.qtd_status); 1218 1219 /* reset scanner */ 1220 1221 xfer->td_transfer_cache = xfer->td_transfer_first; 1222 1223 if (xfer->flags_int.control_xfr) { 1224 1225 if (xfer->flags_int.control_hdr) { 1226 1227 err = ehci_non_isoc_done_sub(xfer); 1228 } 1229 xfer->aframes = 1; 1230 1231 if (xfer->td_transfer_cache == NULL) { 1232 goto done; 1233 } 1234 } 1235 while (xfer->aframes != xfer->nframes) { 1236 1237 err = ehci_non_isoc_done_sub(xfer); 1238 xfer->aframes++; 1239 1240 if (xfer->td_transfer_cache == NULL) { 1241 goto done; 1242 } 1243 } 1244 1245 if (xfer->flags_int.control_xfr && 1246 !xfer->flags_int.control_act) { 1247 1248 err = ehci_non_isoc_done_sub(xfer); 1249 } 1250done: 1251 ehci_device_done(xfer, err); 1252} 1253 1254/*------------------------------------------------------------------------* 1255 * ehci_check_transfer 1256 * 1257 * Return values: 1258 * 0: USB transfer is not finished 1259 * Else: USB transfer is finished 1260 *------------------------------------------------------------------------*/ 1261static uint8_t 1262ehci_check_transfer(struct usb_xfer *xfer) 1263{ 1264 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 1265 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1266 1267 uint32_t status; 1268 1269 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1270 1271 if (methods == &ehci_device_isoc_fs_methods) { 1272 ehci_sitd_t *td; 1273 1274 /* isochronous full speed transfer */ 1275 1276 td = xfer->td_transfer_last; 1277 usb_pc_cpu_invalidate(td->page_cache); 1278 status = hc32toh(sc, td->sitd_status); 1279 1280 /* also check if first is complete */ 1281 1282 td = xfer->td_transfer_first; 1283 usb_pc_cpu_invalidate(td->page_cache); 1284 status |= hc32toh(sc, td->sitd_status); 1285 1286 if (!(status & EHCI_SITD_ACTIVE)) { 1287 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1288 goto transferred; 1289 } 1290 } else if (methods == &ehci_device_isoc_hs_methods) { 1291 ehci_itd_t *td; 1292 1293 /* isochronous high speed transfer */ 1294 1295 /* check last transfer */ 1296 td = xfer->td_transfer_last; 1297 usb_pc_cpu_invalidate(td->page_cache); 1298 status = td->itd_status[0]; 1299 status |= td->itd_status[1]; 1300 status |= td->itd_status[2]; 1301 status |= td->itd_status[3]; 1302 status |= td->itd_status[4]; 1303 status |= td->itd_status[5]; 1304 status |= td->itd_status[6]; 1305 status |= td->itd_status[7]; 1306 1307 /* also check first transfer */ 1308 td = xfer->td_transfer_first; 1309 usb_pc_cpu_invalidate(td->page_cache); 1310 status |= td->itd_status[0]; 1311 status |= td->itd_status[1]; 1312 status |= td->itd_status[2]; 1313 status |= td->itd_status[3]; 1314 status |= td->itd_status[4]; 1315 status |= td->itd_status[5]; 1316 status |= td->itd_status[6]; 1317 status |= td->itd_status[7]; 1318 1319 /* if no transactions are active we continue */ 1320 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) { 1321 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1322 goto transferred; 1323 } 1324 } else { 1325 ehci_qtd_t *td; 1326 ehci_qh_t *qh; 1327 1328 /* non-isochronous transfer */ 1329 1330 /* 1331 * check whether there is an error somewhere in the middle, 1332 * or whether there was a short packet (SPD and not ACTIVE) 1333 */ 1334 td = xfer->td_transfer_cache; 1335 1336 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1337 1338 usb_pc_cpu_invalidate(qh->page_cache); 1339 1340 status = hc32toh(sc, qh->qh_qtd.qtd_status); 1341 if (status & EHCI_QTD_ACTIVE) { 1342 /* transfer is pending */ 1343 goto done; 1344 } 1345 1346 while (1) { 1347 usb_pc_cpu_invalidate(td->page_cache); 1348 status = hc32toh(sc, td->qtd_status); 1349 1350 /* 1351 * Check if there is an active TD which 1352 * indicates that the transfer isn't done. 1353 */ 1354 if (status & EHCI_QTD_ACTIVE) { 1355 /* update cache */ 1356 xfer->td_transfer_cache = td; 1357 goto done; 1358 } 1359 /* 1360 * last transfer descriptor makes the transfer done 1361 */ 1362 if (((void *)td) == xfer->td_transfer_last) { 1363 break; 1364 } 1365 /* 1366 * any kind of error makes the transfer done 1367 */ 1368 if (status & EHCI_QTD_HALTED) { 1369 break; 1370 } 1371 /* 1372 * if there is no alternate next transfer, a short 1373 * packet also makes the transfer done 1374 */ 1375 if (EHCI_QTD_GET_BYTES(status)) { 1376 if (xfer->flags_int.short_frames_ok) { 1377 /* follow alt next */ 1378 if (td->alt_next) { 1379 td = td->alt_next; 1380 continue; 1381 } 1382 } 1383 /* transfer is done */ 1384 break; 1385 } 1386 td = td->obj_next; 1387 } 1388 ehci_non_isoc_done(xfer); 1389 goto transferred; 1390 } 1391 1392done: 1393 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1394 return (0); 1395 1396transferred: 1397 return (1); 1398} 1399 1400static void 1401ehci_pcd_enable(ehci_softc_t *sc) 1402{ 1403 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1404 1405 sc->sc_eintrs |= EHCI_STS_PCD; 1406 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1407 1408 /* acknowledge any PCD interrupt */ 1409 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD); 1410 1411 ehci_root_intr(sc); 1412} 1413 1414static void 1415ehci_interrupt_poll(ehci_softc_t *sc) 1416{ 1417 struct usb_xfer *xfer; 1418 1419repeat: 1420 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1421 /* 1422 * check if transfer is transferred 1423 */ 1424 if (ehci_check_transfer(xfer)) { 1425 /* queue has been modified */ 1426 goto repeat; 1427 } 1428 } 1429} 1430 1431/* 1432 * Some EHCI chips from VIA / ATI seem to trigger interrupts before 1433 * writing back the qTD status, or miss signalling occasionally under 1434 * heavy load. If the host machine is too fast, we can miss 1435 * transaction completion - when we scan the active list the 1436 * transaction still seems to be active. This generally exhibits 1437 * itself as a umass stall that never recovers. 1438 * 1439 * We work around this behaviour by setting up this callback after any 1440 * softintr that completes with transactions still pending, giving us 1441 * another chance to check for completion after the writeback has 1442 * taken place. 1443 */ 1444static void 1445ehci_poll_timeout(void *arg) 1446{ 1447 ehci_softc_t *sc = arg; 1448 1449 DPRINTFN(3, "\n"); 1450 ehci_interrupt_poll(sc); 1451} 1452 1453/*------------------------------------------------------------------------* 1454 * ehci_interrupt - EHCI interrupt handler 1455 * 1456 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1457 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1458 * is present ! 1459 *------------------------------------------------------------------------*/ 1460void 1461ehci_interrupt(ehci_softc_t *sc) 1462{ 1463 uint32_t status; 1464 1465 USB_BUS_LOCK(&sc->sc_bus); 1466 1467 DPRINTFN(16, "real interrupt\n"); 1468 1469#ifdef USB_DEBUG 1470 if (ehcidebug > 15) { 1471 ehci_dump_regs(sc); 1472 } 1473#endif 1474 1475 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1476 if (status == 0) { 1477 /* the interrupt was not for us */ 1478 goto done; 1479 } 1480 if (!(status & sc->sc_eintrs)) { 1481 goto done; 1482 } 1483 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */ 1484 1485 status &= sc->sc_eintrs; 1486 1487 if (status & EHCI_STS_HSE) { 1488 printf("%s: unrecoverable error, " 1489 "controller halted\n", __FUNCTION__); 1490#ifdef USB_DEBUG 1491 ehci_dump_regs(sc); 1492 ehci_dump_isoc(sc); 1493#endif 1494 } 1495 if (status & EHCI_STS_PCD) { 1496 /* 1497 * Disable PCD interrupt for now, because it will be 1498 * on until the port has been reset. 1499 */ 1500 sc->sc_eintrs &= ~EHCI_STS_PCD; 1501 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1502 1503 ehci_root_intr(sc); 1504 1505 /* do not allow RHSC interrupts > 1 per second */ 1506 usb_callout_reset(&sc->sc_tmo_pcd, hz, 1507 (void *)&ehci_pcd_enable, sc); 1508 } 1509 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA); 1510 1511 if (status != 0) { 1512 /* block unprocessed interrupts */ 1513 sc->sc_eintrs &= ~status; 1514 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1515 printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status); 1516 } 1517 /* poll all the USB transfers */ 1518 ehci_interrupt_poll(sc); 1519 1520 if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) { 1521 usb_callout_reset(&sc->sc_tmo_poll, hz / 128, 1522 (void *)&ehci_poll_timeout, sc); 1523 } 1524 1525done: 1526 USB_BUS_UNLOCK(&sc->sc_bus); 1527} 1528 1529/* 1530 * called when a request does not complete 1531 */ 1532static void 1533ehci_timeout(void *arg) 1534{ 1535 struct usb_xfer *xfer = arg; 1536 1537 DPRINTF("xfer=%p\n", xfer); 1538 1539 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1540 1541 /* transfer is transferred */ 1542 ehci_device_done(xfer, USB_ERR_TIMEOUT); 1543} 1544 1545static void 1546ehci_do_poll(struct usb_bus *bus) 1547{ 1548 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1549 1550 USB_BUS_LOCK(&sc->sc_bus); 1551 ehci_interrupt_poll(sc); 1552 USB_BUS_UNLOCK(&sc->sc_bus); 1553} 1554 1555static void 1556ehci_setup_standard_chain_sub(struct ehci_std_temp *temp) 1557{ 1558 struct usb_page_search buf_res; 1559 ehci_qtd_t *td; 1560 ehci_qtd_t *td_next; 1561 ehci_qtd_t *td_alt_next; 1562 uint32_t buf_offset; 1563 uint32_t average; 1564 uint32_t len_old; 1565 uint32_t terminate; 1566 uint32_t qtd_altnext; 1567 uint8_t shortpkt_old; 1568 uint8_t precompute; 1569 1570 terminate = temp->sc->sc_terminate_self; 1571 qtd_altnext = temp->sc->sc_terminate_self; 1572 td_alt_next = NULL; 1573 buf_offset = 0; 1574 shortpkt_old = temp->shortpkt; 1575 len_old = temp->len; 1576 precompute = 1; 1577 1578restart: 1579 1580 td = temp->td; 1581 td_next = temp->td_next; 1582 1583 while (1) { 1584 1585 if (temp->len == 0) { 1586 1587 if (temp->shortpkt) { 1588 break; 1589 } 1590 /* send a Zero Length Packet, ZLP, last */ 1591 1592 temp->shortpkt = 1; 1593 average = 0; 1594 1595 } else { 1596 1597 average = temp->average; 1598 1599 if (temp->len < average) { 1600 if (temp->len % temp->max_frame_size) { 1601 temp->shortpkt = 1; 1602 } 1603 average = temp->len; 1604 } 1605 } 1606 1607 if (td_next == NULL) { 1608 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__); 1609 } 1610 /* get next TD */ 1611 1612 td = td_next; 1613 td_next = td->obj_next; 1614 1615 /* check if we are pre-computing */ 1616 1617 if (precompute) { 1618 1619 /* update remaining length */ 1620 1621 temp->len -= average; 1622 1623 continue; 1624 } 1625 /* fill out current TD */ 1626 1627 td->qtd_status = 1628 temp->qtd_status | 1629 htohc32(temp->sc, EHCI_QTD_IOC | 1630 EHCI_QTD_SET_BYTES(average)); 1631 1632 if (average == 0) { 1633 1634 if (temp->auto_data_toggle == 0) { 1635 1636 /* update data toggle, ZLP case */ 1637 1638 temp->qtd_status ^= 1639 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1640 } 1641 td->len = 0; 1642 1643 /* properly reset reserved fields */ 1644 td->qtd_buffer[0] = 0; 1645 td->qtd_buffer[1] = 0; 1646 td->qtd_buffer[2] = 0; 1647 td->qtd_buffer[3] = 0; 1648 td->qtd_buffer[4] = 0; 1649 td->qtd_buffer_hi[0] = 0; 1650 td->qtd_buffer_hi[1] = 0; 1651 td->qtd_buffer_hi[2] = 0; 1652 td->qtd_buffer_hi[3] = 0; 1653 td->qtd_buffer_hi[4] = 0; 1654 } else { 1655 1656 uint8_t x; 1657 1658 if (temp->auto_data_toggle == 0) { 1659 1660 /* update data toggle */ 1661 1662 if (howmany(average, temp->max_frame_size) & 1) { 1663 temp->qtd_status ^= 1664 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1665 } 1666 } 1667 td->len = average; 1668 1669 /* update remaining length */ 1670 1671 temp->len -= average; 1672 1673 /* fill out buffer pointers */ 1674 1675 usbd_get_page(temp->pc, buf_offset, &buf_res); 1676 td->qtd_buffer[0] = 1677 htohc32(temp->sc, buf_res.physaddr); 1678 td->qtd_buffer_hi[0] = 0; 1679 1680 x = 1; 1681 1682 while (average > EHCI_PAGE_SIZE) { 1683 average -= EHCI_PAGE_SIZE; 1684 buf_offset += EHCI_PAGE_SIZE; 1685 usbd_get_page(temp->pc, buf_offset, &buf_res); 1686 td->qtd_buffer[x] = 1687 htohc32(temp->sc, 1688 buf_res.physaddr & (~0xFFF)); 1689 td->qtd_buffer_hi[x] = 0; 1690 x++; 1691 } 1692 1693 /* 1694 * NOTE: The "average" variable is never zero after 1695 * exiting the loop above ! 1696 * 1697 * NOTE: We have to subtract one from the offset to 1698 * ensure that we are computing the physical address 1699 * of a valid page ! 1700 */ 1701 buf_offset += average; 1702 usbd_get_page(temp->pc, buf_offset - 1, &buf_res); 1703 td->qtd_buffer[x] = 1704 htohc32(temp->sc, 1705 buf_res.physaddr & (~0xFFF)); 1706 td->qtd_buffer_hi[x] = 0; 1707 1708 /* properly reset reserved fields */ 1709 while (++x < EHCI_QTD_NBUFFERS) { 1710 td->qtd_buffer[x] = 0; 1711 td->qtd_buffer_hi[x] = 0; 1712 } 1713 } 1714 1715 if (td_next) { 1716 /* link the current TD with the next one */ 1717 td->qtd_next = td_next->qtd_self; 1718 } 1719 td->qtd_altnext = qtd_altnext; 1720 td->alt_next = td_alt_next; 1721 1722 usb_pc_cpu_flush(td->page_cache); 1723 } 1724 1725 if (precompute) { 1726 precompute = 0; 1727 1728 /* setup alt next pointer, if any */ 1729 if (temp->last_frame) { 1730 td_alt_next = NULL; 1731 qtd_altnext = terminate; 1732 } else { 1733 /* we use this field internally */ 1734 td_alt_next = td_next; 1735 if (temp->setup_alt_next) { 1736 qtd_altnext = td_next->qtd_self; 1737 } else { 1738 qtd_altnext = terminate; 1739 } 1740 } 1741 1742 /* restore */ 1743 temp->shortpkt = shortpkt_old; 1744 temp->len = len_old; 1745 goto restart; 1746 } 1747 temp->td = td; 1748 temp->td_next = td_next; 1749} 1750 1751static void 1752ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last) 1753{ 1754 struct ehci_std_temp temp; 1755 const struct usb_pipe_methods *methods; 1756 ehci_qh_t *qh; 1757 ehci_qtd_t *td; 1758 uint32_t qh_endp; 1759 uint32_t qh_endphub; 1760 uint32_t x; 1761 1762 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1763 xfer->address, UE_GET_ADDR(xfer->endpointno), 1764 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1765 1766 temp.average = xfer->max_hc_frame_size; 1767 temp.max_frame_size = xfer->max_frame_size; 1768 temp.sc = EHCI_BUS2SC(xfer->xroot->bus); 1769 1770 /* toggle the DMA set we are using */ 1771 xfer->flags_int.curr_dma_set ^= 1; 1772 1773 /* get next DMA set */ 1774 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1775 1776 xfer->td_transfer_first = td; 1777 xfer->td_transfer_cache = td; 1778 1779 temp.td = NULL; 1780 temp.td_next = td; 1781 temp.qtd_status = 0; 1782 temp.last_frame = 0; 1783 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1784 1785 if (xfer->flags_int.control_xfr) { 1786 if (xfer->endpoint->toggle_next) { 1787 /* DATA1 is next */ 1788 temp.qtd_status |= 1789 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1790 } 1791 temp.auto_data_toggle = 0; 1792 } else { 1793 temp.auto_data_toggle = 1; 1794 } 1795 1796 if ((xfer->xroot->udev->parent_hs_hub != NULL) || 1797 (xfer->xroot->udev->address != 0)) { 1798 /* max 3 retries */ 1799 temp.qtd_status |= 1800 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1801 } 1802 /* check if we should prepend a setup message */ 1803 1804 if (xfer->flags_int.control_xfr) { 1805 if (xfer->flags_int.control_hdr) { 1806 1807 xfer->endpoint->toggle_next = 0; 1808 1809 temp.qtd_status &= 1810 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1811 temp.qtd_status |= htohc32(temp.sc, 1812 EHCI_QTD_ACTIVE | 1813 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 1814 EHCI_QTD_SET_TOGGLE(0)); 1815 1816 temp.len = xfer->frlengths[0]; 1817 temp.pc = xfer->frbuffers + 0; 1818 temp.shortpkt = temp.len ? 1 : 0; 1819 /* check for last frame */ 1820 if (xfer->nframes == 1) { 1821 /* no STATUS stage yet, SETUP is last */ 1822 if (xfer->flags_int.control_act) { 1823 temp.last_frame = 1; 1824 temp.setup_alt_next = 0; 1825 } 1826 } 1827 ehci_setup_standard_chain_sub(&temp); 1828 } 1829 x = 1; 1830 } else { 1831 x = 0; 1832 } 1833 1834 while (x != xfer->nframes) { 1835 1836 /* DATA0 / DATA1 message */ 1837 1838 temp.len = xfer->frlengths[x]; 1839 temp.pc = xfer->frbuffers + x; 1840 1841 x++; 1842 1843 if (x == xfer->nframes) { 1844 if (xfer->flags_int.control_xfr) { 1845 /* no STATUS stage yet, DATA is last */ 1846 if (xfer->flags_int.control_act) { 1847 temp.last_frame = 1; 1848 temp.setup_alt_next = 0; 1849 } 1850 } else { 1851 temp.last_frame = 1; 1852 temp.setup_alt_next = 0; 1853 } 1854 } 1855 /* keep previous data toggle and error count */ 1856 1857 temp.qtd_status &= 1858 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1859 EHCI_QTD_SET_TOGGLE(1)); 1860 1861 if (temp.len == 0) { 1862 1863 /* make sure that we send an USB packet */ 1864 1865 temp.shortpkt = 0; 1866 1867 } else { 1868 1869 /* regular data transfer */ 1870 1871 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1872 } 1873 1874 /* set endpoint direction */ 1875 1876 temp.qtd_status |= 1877 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 1878 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1879 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) : 1880 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1881 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT)); 1882 1883 ehci_setup_standard_chain_sub(&temp); 1884 } 1885 1886 /* check if we should append a status stage */ 1887 1888 if (xfer->flags_int.control_xfr && 1889 !xfer->flags_int.control_act) { 1890 1891 /* 1892 * Send a DATA1 message and invert the current endpoint 1893 * direction. 1894 */ 1895 1896 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1897 EHCI_QTD_SET_TOGGLE(1)); 1898 temp.qtd_status |= 1899 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ? 1900 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1901 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) | 1902 EHCI_QTD_SET_TOGGLE(1)) : 1903 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1904 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) | 1905 EHCI_QTD_SET_TOGGLE(1)); 1906 1907 temp.len = 0; 1908 temp.pc = NULL; 1909 temp.shortpkt = 0; 1910 temp.last_frame = 1; 1911 temp.setup_alt_next = 0; 1912 1913 ehci_setup_standard_chain_sub(&temp); 1914 } 1915 td = temp.td; 1916 1917 /* the last TD terminates the transfer: */ 1918 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1919 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1920 1921 usb_pc_cpu_flush(td->page_cache); 1922 1923 /* must have at least one frame! */ 1924 1925 xfer->td_transfer_last = td; 1926 1927#ifdef USB_DEBUG 1928 if (ehcidebug > 8) { 1929 DPRINTF("nexttog=%d; data before transfer:\n", 1930 xfer->endpoint->toggle_next); 1931 ehci_dump_sqtds(temp.sc, 1932 xfer->td_transfer_first); 1933 } 1934#endif 1935 1936 methods = xfer->endpoint->methods; 1937 1938 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1939 1940 /* the "qh_link" field is filled when the QH is added */ 1941 1942 qh_endp = 1943 (EHCI_QH_SET_ADDR(xfer->address) | 1944 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 1945 EHCI_QH_SET_MPL(xfer->max_packet_size)); 1946 1947 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 1948 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH); 1949 if (methods != &ehci_device_intr_methods) 1950 qh_endp |= EHCI_QH_SET_NRL(8); 1951 } else { 1952 1953 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) { 1954 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL); 1955 } else { 1956 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW); 1957 } 1958 1959 if (methods == &ehci_device_ctrl_methods) { 1960 qh_endp |= EHCI_QH_CTL; 1961 } 1962 if (methods != &ehci_device_intr_methods) { 1963 /* Only try one time per microframe! */ 1964 qh_endp |= EHCI_QH_SET_NRL(1); 1965 } 1966 } 1967 1968 if (temp.auto_data_toggle == 0) { 1969 /* software computes the data toggle */ 1970 qh_endp |= EHCI_QH_DTC; 1971 } 1972 1973 qh->qh_endp = htohc32(temp.sc, qh_endp); 1974 1975 qh_endphub = 1976 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) | 1977 EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) | 1978 EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) | 1979 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 1980 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no)); 1981 1982 qh->qh_endphub = htohc32(temp.sc, qh_endphub); 1983 qh->qh_curqtd = 0; 1984 1985 /* fill the overlay qTD */ 1986 1987 if (temp.auto_data_toggle && xfer->endpoint->toggle_next) { 1988 /* DATA1 is next */ 1989 qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1990 } else { 1991 qh->qh_qtd.qtd_status = 0; 1992 } 1993 1994 td = xfer->td_transfer_first; 1995 1996 qh->qh_qtd.qtd_next = td->qtd_self; 1997 qh->qh_qtd.qtd_altnext = 1998 htohc32(temp.sc, EHCI_LINK_TERMINATE); 1999 2000 /* properly reset reserved fields */ 2001 qh->qh_qtd.qtd_buffer[0] = 0; 2002 qh->qh_qtd.qtd_buffer[1] = 0; 2003 qh->qh_qtd.qtd_buffer[2] = 0; 2004 qh->qh_qtd.qtd_buffer[3] = 0; 2005 qh->qh_qtd.qtd_buffer[4] = 0; 2006 qh->qh_qtd.qtd_buffer_hi[0] = 0; 2007 qh->qh_qtd.qtd_buffer_hi[1] = 0; 2008 qh->qh_qtd.qtd_buffer_hi[2] = 0; 2009 qh->qh_qtd.qtd_buffer_hi[3] = 0; 2010 qh->qh_qtd.qtd_buffer_hi[4] = 0; 2011 2012 usb_pc_cpu_flush(qh->page_cache); 2013 2014 if (xfer->xroot->udev->flags.self_suspended == 0) { 2015 EHCI_APPEND_QH(qh, *qh_last); 2016 } 2017} 2018 2019static void 2020ehci_root_intr(ehci_softc_t *sc) 2021{ 2022 uint16_t i; 2023 uint16_t m; 2024 2025 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2026 2027 /* clear any old interrupt data */ 2028 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2029 2030 /* set bits */ 2031 m = (sc->sc_noport + 1); 2032 if (m > (8 * sizeof(sc->sc_hub_idata))) { 2033 m = (8 * sizeof(sc->sc_hub_idata)); 2034 } 2035 for (i = 1; i < m; i++) { 2036 /* pick out CHANGE bits from the status register */ 2037 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) { 2038 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2039 DPRINTF("port %d changed\n", i); 2040 } 2041 } 2042 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2043 sizeof(sc->sc_hub_idata)); 2044} 2045 2046static void 2047ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2048{ 2049 uint32_t nframes = xfer->nframes; 2050 uint32_t status; 2051 uint32_t *plen = xfer->frlengths; 2052 uint16_t len = 0; 2053 ehci_sitd_t *td = xfer->td_transfer_first; 2054 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos]; 2055 2056 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2057 xfer, xfer->endpoint); 2058 2059 while (nframes--) { 2060 if (td == NULL) { 2061 panic("%s:%d: out of TD's\n", 2062 __FUNCTION__, __LINE__); 2063 } 2064 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2065 pp_last = &sc->sc_isoc_fs_p_last[0]; 2066 } 2067#ifdef USB_DEBUG 2068 if (ehcidebug > 15) { 2069 DPRINTF("isoc FS-TD\n"); 2070 ehci_dump_sitd(sc, td); 2071 } 2072#endif 2073 usb_pc_cpu_invalidate(td->page_cache); 2074 status = hc32toh(sc, td->sitd_status); 2075 2076 len = EHCI_SITD_GET_LEN(status); 2077 2078 DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len); 2079 2080 if (*plen >= len) { 2081 len = *plen - len; 2082 } else { 2083 len = 0; 2084 } 2085 2086 *plen = len; 2087 2088 /* remove FS-TD from schedule */ 2089 EHCI_REMOVE_FS_TD(td, *pp_last); 2090 2091 pp_last++; 2092 plen++; 2093 td = td->obj_next; 2094 } 2095 2096 xfer->aframes = xfer->nframes; 2097} 2098 2099static void 2100ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2101{ 2102 uint32_t nframes = xfer->nframes; 2103 uint32_t status; 2104 uint32_t *plen = xfer->frlengths; 2105 uint16_t len = 0; 2106 uint8_t td_no = 0; 2107 ehci_itd_t *td = xfer->td_transfer_first; 2108 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos]; 2109 2110 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2111 xfer, xfer->endpoint); 2112 2113 while (nframes) { 2114 if (td == NULL) { 2115 panic("%s:%d: out of TD's\n", 2116 __FUNCTION__, __LINE__); 2117 } 2118 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2119 pp_last = &sc->sc_isoc_hs_p_last[0]; 2120 } 2121#ifdef USB_DEBUG 2122 if (ehcidebug > 15) { 2123 DPRINTF("isoc HS-TD\n"); 2124 ehci_dump_itd(sc, td); 2125 } 2126#endif 2127 2128 usb_pc_cpu_invalidate(td->page_cache); 2129 status = hc32toh(sc, td->itd_status[td_no]); 2130 2131 len = EHCI_ITD_GET_LEN(status); 2132 2133 DPRINTFN(2, "status=0x%08x, len=%u\n", status, len); 2134 2135 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2136 2137 if (*plen >= len) { 2138 /* 2139 * The length is valid. NOTE: The 2140 * complete length is written back 2141 * into the status field, and not the 2142 * remainder like with other transfer 2143 * descriptor types. 2144 */ 2145 } else { 2146 /* Invalid length - truncate */ 2147 len = 0; 2148 } 2149 2150 *plen = len; 2151 plen++; 2152 nframes--; 2153 } 2154 2155 td_no++; 2156 2157 if ((td_no == 8) || (nframes == 0)) { 2158 /* remove HS-TD from schedule */ 2159 EHCI_REMOVE_HS_TD(td, *pp_last); 2160 pp_last++; 2161 2162 td_no = 0; 2163 td = td->obj_next; 2164 } 2165 } 2166 xfer->aframes = xfer->nframes; 2167} 2168 2169/* NOTE: "done" can be run two times in a row, 2170 * from close and from interrupt 2171 */ 2172static void 2173ehci_device_done(struct usb_xfer *xfer, usb_error_t error) 2174{ 2175 const struct usb_pipe_methods *methods = xfer->endpoint->methods; 2176 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2177 2178 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2179 2180 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2181 xfer, xfer->endpoint, error); 2182 2183 if ((methods == &ehci_device_bulk_methods) || 2184 (methods == &ehci_device_ctrl_methods)) { 2185#ifdef USB_DEBUG 2186 if (ehcidebug > 8) { 2187 DPRINTF("nexttog=%d; data after transfer:\n", 2188 xfer->endpoint->toggle_next); 2189 ehci_dump_sqtds(sc, 2190 xfer->td_transfer_first); 2191 } 2192#endif 2193 2194 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2195 sc->sc_async_p_last); 2196 } 2197 if (methods == &ehci_device_intr_methods) { 2198 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2199 sc->sc_intr_p_last[xfer->qh_pos]); 2200 } 2201 /* 2202 * Only finish isochronous transfers once which will update 2203 * "xfer->frlengths". 2204 */ 2205 if (xfer->td_transfer_first && 2206 xfer->td_transfer_last) { 2207 if (methods == &ehci_device_isoc_fs_methods) { 2208 ehci_isoc_fs_done(sc, xfer); 2209 } 2210 if (methods == &ehci_device_isoc_hs_methods) { 2211 ehci_isoc_hs_done(sc, xfer); 2212 } 2213 xfer->td_transfer_first = NULL; 2214 xfer->td_transfer_last = NULL; 2215 } 2216 /* dequeue transfer and start next transfer */ 2217 usbd_transfer_done(xfer, error); 2218} 2219 2220/*------------------------------------------------------------------------* 2221 * ehci bulk support 2222 *------------------------------------------------------------------------*/ 2223static void 2224ehci_device_bulk_open(struct usb_xfer *xfer) 2225{ 2226 return; 2227} 2228 2229static void 2230ehci_device_bulk_close(struct usb_xfer *xfer) 2231{ 2232 ehci_device_done(xfer, USB_ERR_CANCELLED); 2233} 2234 2235static void 2236ehci_device_bulk_enter(struct usb_xfer *xfer) 2237{ 2238 return; 2239} 2240 2241static void 2242ehci_doorbell_async(struct ehci_softc *sc) 2243{ 2244 uint32_t temp; 2245 2246 /* 2247 * XXX Performance quirk: Some Host Controllers have a too low 2248 * interrupt rate. Issue an IAAD to stimulate the Host 2249 * Controller after queueing the BULK transfer. 2250 * 2251 * XXX Force the host controller to refresh any QH caches. 2252 */ 2253 temp = EOREAD4(sc, EHCI_USBCMD); 2254 if (!(temp & EHCI_CMD_IAAD)) 2255 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD); 2256} 2257 2258static void 2259ehci_device_bulk_start(struct usb_xfer *xfer) 2260{ 2261 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2262 2263 /* setup TD's and QH */ 2264 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2265 2266 /* put transfer on interrupt queue */ 2267 ehci_transfer_intr_enqueue(xfer); 2268 2269 /* 2270 * XXX Certain nVidia chipsets choke when using the IAAD 2271 * feature too frequently. 2272 */ 2273 if (sc->sc_flags & EHCI_SCFLG_IAADBUG) 2274 return; 2275 2276 ehci_doorbell_async(sc); 2277} 2278 2279static const struct usb_pipe_methods ehci_device_bulk_methods = 2280{ 2281 .open = ehci_device_bulk_open, 2282 .close = ehci_device_bulk_close, 2283 .enter = ehci_device_bulk_enter, 2284 .start = ehci_device_bulk_start, 2285}; 2286 2287/*------------------------------------------------------------------------* 2288 * ehci control support 2289 *------------------------------------------------------------------------*/ 2290static void 2291ehci_device_ctrl_open(struct usb_xfer *xfer) 2292{ 2293 return; 2294} 2295 2296static void 2297ehci_device_ctrl_close(struct usb_xfer *xfer) 2298{ 2299 ehci_device_done(xfer, USB_ERR_CANCELLED); 2300} 2301 2302static void 2303ehci_device_ctrl_enter(struct usb_xfer *xfer) 2304{ 2305 return; 2306} 2307 2308static void 2309ehci_device_ctrl_start(struct usb_xfer *xfer) 2310{ 2311 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2312 2313 /* setup TD's and QH */ 2314 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2315 2316 /* put transfer on interrupt queue */ 2317 ehci_transfer_intr_enqueue(xfer); 2318} 2319 2320static const struct usb_pipe_methods ehci_device_ctrl_methods = 2321{ 2322 .open = ehci_device_ctrl_open, 2323 .close = ehci_device_ctrl_close, 2324 .enter = ehci_device_ctrl_enter, 2325 .start = ehci_device_ctrl_start, 2326}; 2327 2328/*------------------------------------------------------------------------* 2329 * ehci interrupt support 2330 *------------------------------------------------------------------------*/ 2331static void 2332ehci_device_intr_open(struct usb_xfer *xfer) 2333{ 2334 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2335 uint16_t best; 2336 uint16_t bit; 2337 uint16_t x; 2338 2339 usb_hs_bandwidth_alloc(xfer); 2340 2341 /* 2342 * Find the best QH position corresponding to the given interval: 2343 */ 2344 2345 best = 0; 2346 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 2347 while (bit) { 2348 if (xfer->interval >= bit) { 2349 x = bit; 2350 best = bit; 2351 while (x & bit) { 2352 if (sc->sc_intr_stat[x] < 2353 sc->sc_intr_stat[best]) { 2354 best = x; 2355 } 2356 x++; 2357 } 2358 break; 2359 } 2360 bit >>= 1; 2361 } 2362 2363 sc->sc_intr_stat[best]++; 2364 xfer->qh_pos = best; 2365 2366 DPRINTFN(3, "best=%d interval=%d\n", 2367 best, xfer->interval); 2368} 2369 2370static void 2371ehci_device_intr_close(struct usb_xfer *xfer) 2372{ 2373 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2374 2375 sc->sc_intr_stat[xfer->qh_pos]--; 2376 2377 ehci_device_done(xfer, USB_ERR_CANCELLED); 2378 2379 /* bandwidth must be freed after device done */ 2380 usb_hs_bandwidth_free(xfer); 2381} 2382 2383static void 2384ehci_device_intr_enter(struct usb_xfer *xfer) 2385{ 2386 return; 2387} 2388 2389static void 2390ehci_device_intr_start(struct usb_xfer *xfer) 2391{ 2392 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2393 2394 /* setup TD's and QH */ 2395 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 2396 2397 /* put transfer on interrupt queue */ 2398 ehci_transfer_intr_enqueue(xfer); 2399} 2400 2401static const struct usb_pipe_methods ehci_device_intr_methods = 2402{ 2403 .open = ehci_device_intr_open, 2404 .close = ehci_device_intr_close, 2405 .enter = ehci_device_intr_enter, 2406 .start = ehci_device_intr_start, 2407}; 2408 2409/*------------------------------------------------------------------------* 2410 * ehci full speed isochronous support 2411 *------------------------------------------------------------------------*/ 2412static void 2413ehci_device_isoc_fs_open(struct usb_xfer *xfer) 2414{ 2415 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2416 ehci_sitd_t *td; 2417 uint32_t sitd_portaddr; 2418 uint8_t ds; 2419 2420 sitd_portaddr = 2421 EHCI_SITD_SET_ADDR(xfer->address) | 2422 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 2423 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 2424 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no); 2425 2426 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 2427 sitd_portaddr |= EHCI_SITD_SET_DIR_IN; 2428 2429 sitd_portaddr = htohc32(sc, sitd_portaddr); 2430 2431 /* initialize all TD's */ 2432 2433 for (ds = 0; ds != 2; ds++) { 2434 2435 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2436 2437 td->sitd_portaddr = sitd_portaddr; 2438 2439 /* 2440 * TODO: make some kind of automatic 2441 * SMASK/CMASK selection based on micro-frame 2442 * usage 2443 * 2444 * micro-frame usage (8 microframes per 1ms) 2445 */ 2446 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE); 2447 2448 usb_pc_cpu_flush(td->page_cache); 2449 } 2450 } 2451} 2452 2453static void 2454ehci_device_isoc_fs_close(struct usb_xfer *xfer) 2455{ 2456 ehci_device_done(xfer, USB_ERR_CANCELLED); 2457} 2458 2459static void 2460ehci_device_isoc_fs_enter(struct usb_xfer *xfer) 2461{ 2462 struct usb_page_search buf_res; 2463 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2464 ehci_sitd_t *td; 2465 ehci_sitd_t *td_last = NULL; 2466 ehci_sitd_t **pp_last; 2467 uint32_t *plen; 2468 uint32_t buf_offset; 2469 uint32_t nframes; 2470 uint32_t temp; 2471 uint32_t sitd_mask; 2472 uint16_t tlen; 2473 uint8_t sa; 2474 uint8_t sb; 2475 2476#ifdef USB_DEBUG 2477 uint8_t once = 1; 2478 2479#endif 2480 2481 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2482 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2483 2484 /* get the current frame index */ 2485 2486 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2487 2488 /* 2489 * check if the frame index is within the window where the frames 2490 * will be inserted 2491 */ 2492 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2493 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2494 2495 if ((xfer->endpoint->is_synced == 0) || 2496 (buf_offset < xfer->nframes)) { 2497 /* 2498 * If there is data underflow or the pipe queue is empty we 2499 * schedule the transfer a few frames ahead of the current 2500 * frame position. Else two isochronous transfers might 2501 * overlap. 2502 */ 2503 xfer->endpoint->isoc_next = (nframes + 3) & 2504 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2505 xfer->endpoint->is_synced = 1; 2506 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2507 } 2508 /* 2509 * compute how many milliseconds the insertion is ahead of the 2510 * current frame position: 2511 */ 2512 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2513 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2514 2515 /* 2516 * pre-compute when the isochronous transfer will be finished: 2517 */ 2518 xfer->isoc_time_complete = 2519 usb_isoc_time_expand(&sc->sc_bus, nframes) + 2520 buf_offset + xfer->nframes; 2521 2522 /* get the real number of frames */ 2523 2524 nframes = xfer->nframes; 2525 2526 buf_offset = 0; 2527 2528 plen = xfer->frlengths; 2529 2530 /* toggle the DMA set we are using */ 2531 xfer->flags_int.curr_dma_set ^= 1; 2532 2533 /* get next DMA set */ 2534 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2535 xfer->td_transfer_first = td; 2536 2537 pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next]; 2538 2539 /* store starting position */ 2540 2541 xfer->qh_pos = xfer->endpoint->isoc_next; 2542 2543 while (nframes--) { 2544 if (td == NULL) { 2545 panic("%s:%d: out of TD's\n", 2546 __FUNCTION__, __LINE__); 2547 } 2548 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) 2549 pp_last = &sc->sc_isoc_fs_p_last[0]; 2550 2551 /* reuse sitd_portaddr and sitd_back from last transfer */ 2552 2553 if (*plen > xfer->max_frame_size) { 2554#ifdef USB_DEBUG 2555 if (once) { 2556 once = 0; 2557 printf("%s: frame length(%d) exceeds %d " 2558 "bytes (frame truncated)\n", 2559 __FUNCTION__, *plen, 2560 xfer->max_frame_size); 2561 } 2562#endif 2563 *plen = xfer->max_frame_size; 2564 } 2565 2566 /* allocate a slot */ 2567 2568 sa = usbd_fs_isoc_schedule_alloc_slot(xfer, 2569 xfer->isoc_time_complete - nframes - 1); 2570 2571 if (sa == 255) { 2572 /* 2573 * Schedule is FULL, set length to zero: 2574 */ 2575 2576 *plen = 0; 2577 sa = USB_FS_ISOC_UFRAME_MAX - 1; 2578 } 2579 if (*plen) { 2580 /* 2581 * only call "usbd_get_page()" when we have a 2582 * non-zero length 2583 */ 2584 usbd_get_page(xfer->frbuffers, buf_offset, &buf_res); 2585 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr); 2586 buf_offset += *plen; 2587 /* 2588 * NOTE: We need to subtract one from the offset so 2589 * that we are on a valid page! 2590 */ 2591 usbd_get_page(xfer->frbuffers, buf_offset - 1, 2592 &buf_res); 2593 temp = buf_res.physaddr & ~0xFFF; 2594 } else { 2595 td->sitd_bp[0] = 0; 2596 temp = 0; 2597 } 2598 2599 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) { 2600 tlen = *plen; 2601 if (tlen <= 188) { 2602 temp |= 1; /* T-count = 1, TP = ALL */ 2603 tlen = 1; 2604 } else { 2605 tlen += 187; 2606 tlen /= 188; 2607 temp |= tlen; /* T-count = [1..6] */ 2608 temp |= 8; /* TP = Begin */ 2609 } 2610 2611 tlen += sa; 2612 2613 if (tlen >= 8) { 2614 sb = 0; 2615 } else { 2616 sb = (1 << tlen); 2617 } 2618 2619 sa = (1 << sa); 2620 sa = (sb - sa) & 0x3F; 2621 sb = 0; 2622 } else { 2623 sb = (-(4 << sa)) & 0xFE; 2624 sa = (1 << sa) & 0x3F; 2625 } 2626 2627 sitd_mask = (EHCI_SITD_SET_SMASK(sa) | 2628 EHCI_SITD_SET_CMASK(sb)); 2629 2630 td->sitd_bp[1] = htohc32(sc, temp); 2631 2632 td->sitd_mask = htohc32(sc, sitd_mask); 2633 2634 if (nframes == 0) { 2635 td->sitd_status = htohc32(sc, 2636 EHCI_SITD_IOC | 2637 EHCI_SITD_ACTIVE | 2638 EHCI_SITD_SET_LEN(*plen)); 2639 } else { 2640 td->sitd_status = htohc32(sc, 2641 EHCI_SITD_ACTIVE | 2642 EHCI_SITD_SET_LEN(*plen)); 2643 } 2644 usb_pc_cpu_flush(td->page_cache); 2645 2646#ifdef USB_DEBUG 2647 if (ehcidebug > 15) { 2648 DPRINTF("FS-TD %d\n", nframes); 2649 ehci_dump_sitd(sc, td); 2650 } 2651#endif 2652 /* insert TD into schedule */ 2653 EHCI_APPEND_FS_TD(td, *pp_last); 2654 pp_last++; 2655 2656 plen++; 2657 td_last = td; 2658 td = td->obj_next; 2659 } 2660 2661 xfer->td_transfer_last = td_last; 2662 2663 /* update isoc_next */ 2664 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) & 2665 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2666 2667 /* 2668 * We don't allow cancelling of the SPLIT transaction USB FULL 2669 * speed transfer, because it disturbs the bandwidth 2670 * computation algorithm. 2671 */ 2672 xfer->flags_int.can_cancel_immed = 0; 2673} 2674 2675static void 2676ehci_device_isoc_fs_start(struct usb_xfer *xfer) 2677{ 2678 /* 2679 * We don't allow cancelling of the SPLIT transaction USB FULL 2680 * speed transfer, because it disturbs the bandwidth 2681 * computation algorithm. 2682 */ 2683 xfer->flags_int.can_cancel_immed = 0; 2684 2685 /* set a default timeout */ 2686 if (xfer->timeout == 0) 2687 xfer->timeout = 500; /* ms */ 2688 2689 /* put transfer on interrupt queue */ 2690 ehci_transfer_intr_enqueue(xfer); 2691} 2692 2693static const struct usb_pipe_methods ehci_device_isoc_fs_methods = 2694{ 2695 .open = ehci_device_isoc_fs_open, 2696 .close = ehci_device_isoc_fs_close, 2697 .enter = ehci_device_isoc_fs_enter, 2698 .start = ehci_device_isoc_fs_start, 2699}; 2700 2701/*------------------------------------------------------------------------* 2702 * ehci high speed isochronous support 2703 *------------------------------------------------------------------------*/ 2704static void 2705ehci_device_isoc_hs_open(struct usb_xfer *xfer) 2706{ 2707 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2708 ehci_itd_t *td; 2709 uint32_t temp; 2710 uint8_t ds; 2711 2712 usb_hs_bandwidth_alloc(xfer); 2713 2714 /* initialize all TD's */ 2715 2716 for (ds = 0; ds != 2; ds++) { 2717 2718 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2719 2720 /* set TD inactive */ 2721 td->itd_status[0] = 0; 2722 td->itd_status[1] = 0; 2723 td->itd_status[2] = 0; 2724 td->itd_status[3] = 0; 2725 td->itd_status[4] = 0; 2726 td->itd_status[5] = 0; 2727 td->itd_status[6] = 0; 2728 td->itd_status[7] = 0; 2729 2730 /* set endpoint and address */ 2731 td->itd_bp[0] = htohc32(sc, 2732 EHCI_ITD_SET_ADDR(xfer->address) | 2733 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno))); 2734 2735 temp = 2736 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF); 2737 2738 /* set direction */ 2739 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 2740 temp |= EHCI_ITD_SET_DIR_IN; 2741 } 2742 /* set maximum packet size */ 2743 td->itd_bp[1] = htohc32(sc, temp); 2744 2745 /* set transfer multiplier */ 2746 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3); 2747 2748 usb_pc_cpu_flush(td->page_cache); 2749 } 2750 } 2751} 2752 2753static void 2754ehci_device_isoc_hs_close(struct usb_xfer *xfer) 2755{ 2756 ehci_device_done(xfer, USB_ERR_CANCELLED); 2757 2758 /* bandwidth must be freed after device done */ 2759 usb_hs_bandwidth_free(xfer); 2760} 2761 2762static void 2763ehci_device_isoc_hs_enter(struct usb_xfer *xfer) 2764{ 2765 struct usb_page_search buf_res; 2766 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2767 ehci_itd_t *td; 2768 ehci_itd_t *td_last = NULL; 2769 ehci_itd_t **pp_last; 2770 bus_size_t page_addr; 2771 uint32_t *plen; 2772 uint32_t status; 2773 uint32_t buf_offset; 2774 uint32_t nframes; 2775 uint32_t itd_offset[8 + 1]; 2776 uint8_t x; 2777 uint8_t td_no; 2778 uint8_t page_no; 2779 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 2780 2781#ifdef USB_DEBUG 2782 uint8_t once = 1; 2783 2784#endif 2785 2786 DPRINTFN(6, "xfer=%p next=%d nframes=%d shift=%d\n", 2787 xfer, xfer->endpoint->isoc_next, xfer->nframes, (int)shift); 2788 2789 /* get the current frame index */ 2790 2791 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2792 2793 /* 2794 * check if the frame index is within the window where the frames 2795 * will be inserted 2796 */ 2797 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2798 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2799 2800 if ((xfer->endpoint->is_synced == 0) || 2801 (buf_offset < (((xfer->nframes << shift) + 7) / 8))) { 2802 /* 2803 * If there is data underflow or the pipe queue is empty we 2804 * schedule the transfer a few frames ahead of the current 2805 * frame position. Else two isochronous transfers might 2806 * overlap. 2807 */ 2808 xfer->endpoint->isoc_next = (nframes + 3) & 2809 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2810 xfer->endpoint->is_synced = 1; 2811 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2812 } 2813 /* 2814 * compute how many milliseconds the insertion is ahead of the 2815 * current frame position: 2816 */ 2817 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2818 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2819 2820 /* 2821 * pre-compute when the isochronous transfer will be finished: 2822 */ 2823 xfer->isoc_time_complete = 2824 usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 2825 (((xfer->nframes << shift) + 7) / 8); 2826 2827 /* get the real number of frames */ 2828 2829 nframes = xfer->nframes; 2830 2831 buf_offset = 0; 2832 td_no = 0; 2833 2834 plen = xfer->frlengths; 2835 2836 /* toggle the DMA set we are using */ 2837 xfer->flags_int.curr_dma_set ^= 1; 2838 2839 /* get next DMA set */ 2840 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2841 xfer->td_transfer_first = td; 2842 2843 pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next]; 2844 2845 /* store starting position */ 2846 2847 xfer->qh_pos = xfer->endpoint->isoc_next; 2848 2849 while (nframes) { 2850 if (td == NULL) { 2851 panic("%s:%d: out of TD's\n", 2852 __FUNCTION__, __LINE__); 2853 } 2854 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2855 pp_last = &sc->sc_isoc_hs_p_last[0]; 2856 } 2857 /* range check */ 2858 if (*plen > xfer->max_frame_size) { 2859#ifdef USB_DEBUG 2860 if (once) { 2861 once = 0; 2862 printf("%s: frame length(%d) exceeds %d bytes " 2863 "(frame truncated)\n", 2864 __FUNCTION__, *plen, xfer->max_frame_size); 2865 } 2866#endif 2867 *plen = xfer->max_frame_size; 2868 } 2869 2870 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2871 status = (EHCI_ITD_SET_LEN(*plen) | 2872 EHCI_ITD_ACTIVE | 2873 EHCI_ITD_SET_PG(0)); 2874 td->itd_status[td_no] = htohc32(sc, status); 2875 itd_offset[td_no] = buf_offset; 2876 buf_offset += *plen; 2877 plen++; 2878 nframes --; 2879 } else { 2880 td->itd_status[td_no] = 0; /* not active */ 2881 itd_offset[td_no] = buf_offset; 2882 } 2883 2884 td_no++; 2885 2886 if ((td_no == 8) || (nframes == 0)) { 2887 2888 /* the rest of the transfers are not active, if any */ 2889 for (x = td_no; x != 8; x++) { 2890 td->itd_status[x] = 0; /* not active */ 2891 } 2892 2893 /* check if there is any data to be transferred */ 2894 if (itd_offset[0] != buf_offset) { 2895 page_no = 0; 2896 itd_offset[td_no] = buf_offset; 2897 2898 /* get first page offset */ 2899 usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res); 2900 /* get page address */ 2901 page_addr = buf_res.physaddr & ~0xFFF; 2902 /* update page address */ 2903 td->itd_bp[0] &= htohc32(sc, 0xFFF); 2904 td->itd_bp[0] |= htohc32(sc, page_addr); 2905 2906 for (x = 0; x != td_no; x++) { 2907 /* set page number and page offset */ 2908 status = (EHCI_ITD_SET_PG(page_no) | 2909 (buf_res.physaddr & 0xFFF)); 2910 td->itd_status[x] |= htohc32(sc, status); 2911 2912 /* get next page offset */ 2913 if (itd_offset[x + 1] == buf_offset) { 2914 /* 2915 * We subtract one so that 2916 * we don't go off the last 2917 * page! 2918 */ 2919 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 2920 } else { 2921 usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res); 2922 } 2923 2924 /* check if we need a new page */ 2925 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) { 2926 /* new page needed */ 2927 page_addr = buf_res.physaddr & ~0xFFF; 2928 if (page_no == 6) { 2929 panic("%s: too many pages\n", __FUNCTION__); 2930 } 2931 page_no++; 2932 /* update page address */ 2933 td->itd_bp[page_no] &= htohc32(sc, 0xFFF); 2934 td->itd_bp[page_no] |= htohc32(sc, page_addr); 2935 } 2936 } 2937 } 2938 /* set IOC bit if we are complete */ 2939 if (nframes == 0) { 2940 td->itd_status[td_no - 1] |= htohc32(sc, EHCI_ITD_IOC); 2941 } 2942 usb_pc_cpu_flush(td->page_cache); 2943#ifdef USB_DEBUG 2944 if (ehcidebug > 15) { 2945 DPRINTF("HS-TD %d\n", nframes); 2946 ehci_dump_itd(sc, td); 2947 } 2948#endif 2949 /* insert TD into schedule */ 2950 EHCI_APPEND_HS_TD(td, *pp_last); 2951 pp_last++; 2952 2953 td_no = 0; 2954 td_last = td; 2955 td = td->obj_next; 2956 } 2957 } 2958 2959 xfer->td_transfer_last = td_last; 2960 2961 /* update isoc_next */ 2962 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) & 2963 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2964} 2965 2966static void 2967ehci_device_isoc_hs_start(struct usb_xfer *xfer) 2968{ 2969 /* put transfer on interrupt queue */ 2970 ehci_transfer_intr_enqueue(xfer); 2971} 2972 2973static const struct usb_pipe_methods ehci_device_isoc_hs_methods = 2974{ 2975 .open = ehci_device_isoc_hs_open, 2976 .close = ehci_device_isoc_hs_close, 2977 .enter = ehci_device_isoc_hs_enter, 2978 .start = ehci_device_isoc_hs_start, 2979}; 2980 2981/*------------------------------------------------------------------------* 2982 * ehci root control support 2983 *------------------------------------------------------------------------* 2984 * Simulate a hardware hub by handling all the necessary requests. 2985 *------------------------------------------------------------------------*/ 2986 2987static const 2988struct usb_device_descriptor ehci_devd = 2989{ 2990 sizeof(struct usb_device_descriptor), 2991 UDESC_DEVICE, /* type */ 2992 {0x00, 0x02}, /* USB version */ 2993 UDCLASS_HUB, /* class */ 2994 UDSUBCLASS_HUB, /* subclass */ 2995 UDPROTO_HSHUBSTT, /* protocol */ 2996 64, /* max packet */ 2997 {0}, {0}, {0x00, 0x01}, /* device id */ 2998 1, 2, 0, /* string indexes */ 2999 1 /* # of configurations */ 3000}; 3001 3002static const 3003struct usb_device_qualifier ehci_odevd = 3004{ 3005 sizeof(struct usb_device_qualifier), 3006 UDESC_DEVICE_QUALIFIER, /* type */ 3007 {0x00, 0x02}, /* USB version */ 3008 UDCLASS_HUB, /* class */ 3009 UDSUBCLASS_HUB, /* subclass */ 3010 UDPROTO_FSHUB, /* protocol */ 3011 0, /* max packet */ 3012 0, /* # of configurations */ 3013 0 3014}; 3015 3016static const struct ehci_config_desc ehci_confd = { 3017 .confd = { 3018 .bLength = sizeof(struct usb_config_descriptor), 3019 .bDescriptorType = UDESC_CONFIG, 3020 .wTotalLength[0] = sizeof(ehci_confd), 3021 .bNumInterface = 1, 3022 .bConfigurationValue = 1, 3023 .iConfiguration = 0, 3024 .bmAttributes = UC_SELF_POWERED, 3025 .bMaxPower = 0 /* max power */ 3026 }, 3027 .ifcd = { 3028 .bLength = sizeof(struct usb_interface_descriptor), 3029 .bDescriptorType = UDESC_INTERFACE, 3030 .bNumEndpoints = 1, 3031 .bInterfaceClass = UICLASS_HUB, 3032 .bInterfaceSubClass = UISUBCLASS_HUB, 3033 .bInterfaceProtocol = 0, 3034 }, 3035 .endpd = { 3036 .bLength = sizeof(struct usb_endpoint_descriptor), 3037 .bDescriptorType = UDESC_ENDPOINT, 3038 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT, 3039 .bmAttributes = UE_INTERRUPT, 3040 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 3041 .bInterval = 255, 3042 }, 3043}; 3044 3045static const 3046struct usb_hub_descriptor ehci_hubd = 3047{ 3048 .bDescLength = 0, /* dynamic length */ 3049 .bDescriptorType = UDESC_HUB, 3050}; 3051 3052uint16_t 3053ehci_get_port_speed_portsc(struct ehci_softc *sc, uint16_t index) 3054{ 3055 uint32_t v; 3056 3057 v = EOREAD4(sc, EHCI_PORTSC(index)); 3058 v = (v >> EHCI_PORTSC_PSPD_SHIFT) & EHCI_PORTSC_PSPD_MASK; 3059 3060 if (v == EHCI_PORT_SPEED_HIGH) 3061 return (UPS_HIGH_SPEED); 3062 if (v == EHCI_PORT_SPEED_LOW) 3063 return (UPS_LOW_SPEED); 3064 return (0); 3065} 3066 3067uint16_t 3068ehci_get_port_speed_hostc(struct ehci_softc *sc, uint16_t index) 3069{ 3070 uint32_t v; 3071 3072 v = EOREAD4(sc, EHCI_HOSTC(index)); 3073 v = (v >> EHCI_HOSTC_PSPD_SHIFT) & EHCI_HOSTC_PSPD_MASK; 3074 3075 if (v == EHCI_PORT_SPEED_HIGH) 3076 return (UPS_HIGH_SPEED); 3077 if (v == EHCI_PORT_SPEED_LOW) 3078 return (UPS_LOW_SPEED); 3079 return (0); 3080} 3081 3082static void 3083ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed) 3084{ 3085 uint32_t port; 3086 uint32_t v; 3087 3088 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed); 3089 3090 port = EHCI_PORTSC(index); 3091 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3092 EOWRITE4(sc, port, v | EHCI_PS_PO); 3093} 3094 3095static usb_error_t 3096ehci_roothub_exec(struct usb_device *udev, 3097 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3098{ 3099 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3100 const char *str_ptr; 3101 const void *ptr; 3102 uint32_t port; 3103 uint32_t v; 3104 uint16_t len; 3105 uint16_t i; 3106 uint16_t value; 3107 uint16_t index; 3108 usb_error_t err; 3109 3110 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3111 3112 /* buffer reset */ 3113 ptr = (const void *)&sc->sc_hub_desc; 3114 len = 0; 3115 err = 0; 3116 3117 value = UGETW(req->wValue); 3118 index = UGETW(req->wIndex); 3119 3120 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3121 "wValue=0x%04x wIndex=0x%04x\n", 3122 req->bmRequestType, req->bRequest, 3123 UGETW(req->wLength), value, index); 3124 3125#define C(x,y) ((x) | ((y) << 8)) 3126 switch (C(req->bRequest, req->bmRequestType)) { 3127 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3128 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3129 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3130 /* 3131 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3132 * for the integrated root hub. 3133 */ 3134 break; 3135 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3136 len = 1; 3137 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3138 break; 3139 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3140 switch (value >> 8) { 3141 case UDESC_DEVICE: 3142 if ((value & 0xff) != 0) { 3143 err = USB_ERR_IOERROR; 3144 goto done; 3145 } 3146 len = sizeof(ehci_devd); 3147 ptr = (const void *)&ehci_devd; 3148 break; 3149 /* 3150 * We can't really operate at another speed, 3151 * but the specification says we need this 3152 * descriptor: 3153 */ 3154 case UDESC_DEVICE_QUALIFIER: 3155 if ((value & 0xff) != 0) { 3156 err = USB_ERR_IOERROR; 3157 goto done; 3158 } 3159 len = sizeof(ehci_odevd); 3160 ptr = (const void *)&ehci_odevd; 3161 break; 3162 3163 case UDESC_CONFIG: 3164 if ((value & 0xff) != 0) { 3165 err = USB_ERR_IOERROR; 3166 goto done; 3167 } 3168 len = sizeof(ehci_confd); 3169 ptr = (const void *)&ehci_confd; 3170 break; 3171 3172 case UDESC_STRING: 3173 switch (value & 0xff) { 3174 case 0: /* Language table */ 3175 str_ptr = "\001"; 3176 break; 3177 3178 case 1: /* Vendor */ 3179 str_ptr = sc->sc_vendor; 3180 break; 3181 3182 case 2: /* Product */ 3183 str_ptr = "EHCI root HUB"; 3184 break; 3185 3186 default: 3187 str_ptr = ""; 3188 break; 3189 } 3190 3191 len = usb_make_str_desc( 3192 sc->sc_hub_desc.temp, 3193 sizeof(sc->sc_hub_desc.temp), 3194 str_ptr); 3195 break; 3196 default: 3197 err = USB_ERR_IOERROR; 3198 goto done; 3199 } 3200 break; 3201 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3202 len = 1; 3203 sc->sc_hub_desc.temp[0] = 0; 3204 break; 3205 case C(UR_GET_STATUS, UT_READ_DEVICE): 3206 len = 2; 3207 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3208 break; 3209 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3210 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3211 len = 2; 3212 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3213 break; 3214 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3215 if (value >= EHCI_MAX_DEVICES) { 3216 err = USB_ERR_IOERROR; 3217 goto done; 3218 } 3219 sc->sc_addr = value; 3220 break; 3221 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3222 if ((value != 0) && (value != 1)) { 3223 err = USB_ERR_IOERROR; 3224 goto done; 3225 } 3226 sc->sc_conf = value; 3227 break; 3228 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3229 break; 3230 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3231 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3232 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3233 err = USB_ERR_IOERROR; 3234 goto done; 3235 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3236 break; 3237 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3238 break; 3239 /* Hub requests */ 3240 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3241 break; 3242 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3243 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3244 3245 if ((index < 1) || 3246 (index > sc->sc_noport)) { 3247 err = USB_ERR_IOERROR; 3248 goto done; 3249 } 3250 port = EHCI_PORTSC(index); 3251 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3252 switch (value) { 3253 case UHF_PORT_ENABLE: 3254 EOWRITE4(sc, port, v & ~EHCI_PS_PE); 3255 break; 3256 case UHF_PORT_SUSPEND: 3257 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) { 3258 3259 /* 3260 * waking up a High Speed device is rather 3261 * complicated if 3262 */ 3263 EOWRITE4(sc, port, v | EHCI_PS_FPR); 3264 } 3265 /* wait 20ms for resume sequence to complete */ 3266 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3267 3268 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP | 3269 EHCI_PS_FPR | (3 << 10) /* High Speed */ )); 3270 3271 /* 4ms settle time */ 3272 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3273 break; 3274 case UHF_PORT_POWER: 3275 EOWRITE4(sc, port, v & ~EHCI_PS_PP); 3276 break; 3277 case UHF_PORT_TEST: 3278 DPRINTFN(3, "clear port test " 3279 "%d\n", index); 3280 break; 3281 case UHF_PORT_INDICATOR: 3282 DPRINTFN(3, "clear port ind " 3283 "%d\n", index); 3284 EOWRITE4(sc, port, v & ~EHCI_PS_PIC); 3285 break; 3286 case UHF_C_PORT_CONNECTION: 3287 EOWRITE4(sc, port, v | EHCI_PS_CSC); 3288 break; 3289 case UHF_C_PORT_ENABLE: 3290 EOWRITE4(sc, port, v | EHCI_PS_PEC); 3291 break; 3292 case UHF_C_PORT_SUSPEND: 3293 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3294 break; 3295 case UHF_C_PORT_OVER_CURRENT: 3296 EOWRITE4(sc, port, v | EHCI_PS_OCC); 3297 break; 3298 case UHF_C_PORT_RESET: 3299 sc->sc_isreset = 0; 3300 break; 3301 default: 3302 err = USB_ERR_IOERROR; 3303 goto done; 3304 } 3305 break; 3306 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3307 if ((value & 0xff) != 0) { 3308 err = USB_ERR_IOERROR; 3309 goto done; 3310 } 3311 v = EREAD4(sc, EHCI_HCSPARAMS); 3312 3313 sc->sc_hub_desc.hubd = ehci_hubd; 3314 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3315 3316 if (EHCI_HCS_PPC(v)) 3317 i = UHD_PWR_INDIVIDUAL; 3318 else 3319 i = UHD_PWR_NO_SWITCH; 3320 3321 if (EHCI_HCS_P_INDICATOR(v)) 3322 i |= UHD_PORT_IND; 3323 3324 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3325 /* XXX can't find out? */ 3326 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200; 3327 /* XXX don't know if ports are removable or not */ 3328 sc->sc_hub_desc.hubd.bDescLength = 3329 8 + ((sc->sc_noport + 7) / 8); 3330 len = sc->sc_hub_desc.hubd.bDescLength; 3331 break; 3332 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3333 len = 16; 3334 memset(sc->sc_hub_desc.temp, 0, 16); 3335 break; 3336 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3337 DPRINTFN(9, "get port status i=%d\n", 3338 index); 3339 if ((index < 1) || 3340 (index > sc->sc_noport)) { 3341 err = USB_ERR_IOERROR; 3342 goto done; 3343 } 3344 v = EOREAD4(sc, EHCI_PORTSC(index)); 3345 DPRINTFN(9, "port status=0x%04x\n", v); 3346 if (sc->sc_flags & EHCI_SCFLG_TT) { 3347 if (sc->sc_vendor_get_port_speed != NULL) { 3348 i = sc->sc_vendor_get_port_speed(sc, index); 3349 } else { 3350 device_printf(sc->sc_bus.bdev, 3351 "EHCI_SCFLG_TT quirk is set but " 3352 "sc_vendor_get_hub_speed() is NULL\n"); 3353 i = UPS_HIGH_SPEED; 3354 } 3355 } else { 3356 i = UPS_HIGH_SPEED; 3357 } 3358 if (v & EHCI_PS_CS) 3359 i |= UPS_CURRENT_CONNECT_STATUS; 3360 if (v & EHCI_PS_PE) 3361 i |= UPS_PORT_ENABLED; 3362 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR)) 3363 i |= UPS_SUSPEND; 3364 if (v & EHCI_PS_OCA) 3365 i |= UPS_OVERCURRENT_INDICATOR; 3366 if (v & EHCI_PS_PR) 3367 i |= UPS_RESET; 3368 if (v & EHCI_PS_PP) 3369 i |= UPS_PORT_POWER; 3370 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3371 i = 0; 3372 if (v & EHCI_PS_CSC) 3373 i |= UPS_C_CONNECT_STATUS; 3374 if (v & EHCI_PS_PEC) 3375 i |= UPS_C_PORT_ENABLED; 3376 if (v & EHCI_PS_OCC) 3377 i |= UPS_C_OVERCURRENT_INDICATOR; 3378 if (v & EHCI_PS_FPR) 3379 i |= UPS_C_SUSPEND; 3380 if (sc->sc_isreset) 3381 i |= UPS_C_PORT_RESET; 3382 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3383 len = sizeof(sc->sc_hub_desc.ps); 3384 break; 3385 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3386 err = USB_ERR_IOERROR; 3387 goto done; 3388 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3389 break; 3390 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3391 if ((index < 1) || 3392 (index > sc->sc_noport)) { 3393 err = USB_ERR_IOERROR; 3394 goto done; 3395 } 3396 port = EHCI_PORTSC(index); 3397 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3398 switch (value) { 3399 case UHF_PORT_ENABLE: 3400 EOWRITE4(sc, port, v | EHCI_PS_PE); 3401 break; 3402 case UHF_PORT_SUSPEND: 3403 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3404 break; 3405 case UHF_PORT_RESET: 3406 DPRINTFN(6, "reset port %d\n", index); 3407#ifdef USB_DEBUG 3408 if (ehcinohighspeed) { 3409 /* 3410 * Connect USB device to companion 3411 * controller. 3412 */ 3413 ehci_disown(sc, index, 1); 3414 break; 3415 } 3416#endif 3417 if (EHCI_PS_IS_LOWSPEED(v) && 3418 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3419 /* Low speed device, give up ownership. */ 3420 ehci_disown(sc, index, 1); 3421 break; 3422 } 3423 /* Start reset sequence. */ 3424 v &= ~(EHCI_PS_PE | EHCI_PS_PR); 3425 EOWRITE4(sc, port, v | EHCI_PS_PR); 3426 3427 /* Wait for reset to complete. */ 3428 usb_pause_mtx(&sc->sc_bus.bus_mtx, 3429 USB_MS_TO_TICKS(usb_port_root_reset_delay)); 3430 3431 /* Terminate reset sequence. */ 3432 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM)) 3433 EOWRITE4(sc, port, v); 3434 3435 /* Wait for HC to complete reset. */ 3436 usb_pause_mtx(&sc->sc_bus.bus_mtx, 3437 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE)); 3438 3439 v = EOREAD4(sc, port); 3440 DPRINTF("ehci after reset, status=0x%08x\n", v); 3441 if (v & EHCI_PS_PR) { 3442 device_printf(sc->sc_bus.bdev, 3443 "port reset timeout\n"); 3444 err = USB_ERR_TIMEOUT; 3445 goto done; 3446 } 3447 if (!(v & EHCI_PS_PE) && 3448 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3449 /* Not a high speed device, give up ownership.*/ 3450 ehci_disown(sc, index, 0); 3451 break; 3452 } 3453 sc->sc_isreset = 1; 3454 DPRINTF("ehci port %d reset, status = 0x%08x\n", 3455 index, v); 3456 break; 3457 3458 case UHF_PORT_POWER: 3459 DPRINTFN(3, "set port power %d\n", index); 3460 EOWRITE4(sc, port, v | EHCI_PS_PP); 3461 break; 3462 3463 case UHF_PORT_TEST: 3464 DPRINTFN(3, "set port test %d\n", index); 3465 break; 3466 3467 case UHF_PORT_INDICATOR: 3468 DPRINTFN(3, "set port ind %d\n", index); 3469 EOWRITE4(sc, port, v | EHCI_PS_PIC); 3470 break; 3471 3472 default: 3473 err = USB_ERR_IOERROR; 3474 goto done; 3475 } 3476 break; 3477 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3478 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3479 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3480 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3481 break; 3482 default: 3483 err = USB_ERR_IOERROR; 3484 goto done; 3485 } 3486done: 3487 *plength = len; 3488 *pptr = ptr; 3489 return (err); 3490} 3491 3492static void 3493ehci_xfer_setup(struct usb_setup_params *parm) 3494{ 3495 struct usb_page_search page_info; 3496 struct usb_page_cache *pc; 3497 ehci_softc_t *sc; 3498 struct usb_xfer *xfer; 3499 void *last_obj; 3500 uint32_t nqtd; 3501 uint32_t nqh; 3502 uint32_t nsitd; 3503 uint32_t nitd; 3504 uint32_t n; 3505 3506 sc = EHCI_BUS2SC(parm->udev->bus); 3507 xfer = parm->curr_xfer; 3508 3509 nqtd = 0; 3510 nqh = 0; 3511 nsitd = 0; 3512 nitd = 0; 3513 3514 /* 3515 * compute maximum number of some structures 3516 */ 3517 if (parm->methods == &ehci_device_ctrl_methods) { 3518 3519 /* 3520 * The proof for the "nqtd" formula is illustrated like 3521 * this: 3522 * 3523 * +------------------------------------+ 3524 * | | 3525 * | |remainder -> | 3526 * | +-----+---+ | 3527 * | | xxx | x | frm 0 | 3528 * | +-----+---++ | 3529 * | | xxx | xx | frm 1 | 3530 * | +-----+----+ | 3531 * | ... | 3532 * +------------------------------------+ 3533 * 3534 * "xxx" means a completely full USB transfer descriptor 3535 * 3536 * "x" and "xx" means a short USB packet 3537 * 3538 * For the remainder of an USB transfer modulo 3539 * "max_data_length" we need two USB transfer descriptors. 3540 * One to transfer the remaining data and one to finalise 3541 * with a zero length packet in case the "force_short_xfer" 3542 * flag is set. We only need two USB transfer descriptors in 3543 * the case where the transfer length of the first one is a 3544 * factor of "max_frame_size". The rest of the needed USB 3545 * transfer descriptors is given by the buffer size divided 3546 * by the maximum data payload. 3547 */ 3548 parm->hc_max_packet_size = 0x400; 3549 parm->hc_max_packet_count = 1; 3550 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3551 xfer->flags_int.bdma_enable = 1; 3552 3553 usbd_transfer_setup_sub(parm); 3554 3555 nqh = 1; 3556 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */ 3557 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3558 3559 } else if (parm->methods == &ehci_device_bulk_methods) { 3560 3561 parm->hc_max_packet_size = 0x400; 3562 parm->hc_max_packet_count = 1; 3563 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3564 xfer->flags_int.bdma_enable = 1; 3565 3566 usbd_transfer_setup_sub(parm); 3567 3568 nqh = 1; 3569 nqtd = ((2 * xfer->nframes) 3570 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3571 3572 } else if (parm->methods == &ehci_device_intr_methods) { 3573 3574 if (parm->speed == USB_SPEED_HIGH) { 3575 parm->hc_max_packet_size = 0x400; 3576 parm->hc_max_packet_count = 3; 3577 } else if (parm->speed == USB_SPEED_FULL) { 3578 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME; 3579 parm->hc_max_packet_count = 1; 3580 } else { 3581 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8; 3582 parm->hc_max_packet_count = 1; 3583 } 3584 3585 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3586 xfer->flags_int.bdma_enable = 1; 3587 3588 usbd_transfer_setup_sub(parm); 3589 3590 nqh = 1; 3591 nqtd = ((2 * xfer->nframes) 3592 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3593 3594 } else if (parm->methods == &ehci_device_isoc_fs_methods) { 3595 3596 parm->hc_max_packet_size = 0x3FF; 3597 parm->hc_max_packet_count = 1; 3598 parm->hc_max_frame_size = 0x3FF; 3599 xfer->flags_int.bdma_enable = 1; 3600 3601 usbd_transfer_setup_sub(parm); 3602 3603 nsitd = xfer->nframes; 3604 3605 } else if (parm->methods == &ehci_device_isoc_hs_methods) { 3606 3607 parm->hc_max_packet_size = 0x400; 3608 parm->hc_max_packet_count = 3; 3609 parm->hc_max_frame_size = 0xC00; 3610 xfer->flags_int.bdma_enable = 1; 3611 3612 usbd_transfer_setup_sub(parm); 3613 3614 nitd = ((xfer->nframes + 7) / 8) << 3615 usbd_xfer_get_fps_shift(xfer); 3616 3617 } else { 3618 3619 parm->hc_max_packet_size = 0x400; 3620 parm->hc_max_packet_count = 1; 3621 parm->hc_max_frame_size = 0x400; 3622 3623 usbd_transfer_setup_sub(parm); 3624 } 3625 3626alloc_dma_set: 3627 3628 if (parm->err) { 3629 return; 3630 } 3631 /* 3632 * Allocate queue heads and transfer descriptors 3633 */ 3634 last_obj = NULL; 3635 3636 if (usbd_transfer_setup_sub_malloc( 3637 parm, &pc, sizeof(ehci_itd_t), 3638 EHCI_ITD_ALIGN, nitd)) { 3639 parm->err = USB_ERR_NOMEM; 3640 return; 3641 } 3642 if (parm->buf) { 3643 for (n = 0; n != nitd; n++) { 3644 ehci_itd_t *td; 3645 3646 usbd_get_page(pc + n, 0, &page_info); 3647 3648 td = page_info.buffer; 3649 3650 /* init TD */ 3651 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD); 3652 td->obj_next = last_obj; 3653 td->page_cache = pc + n; 3654 3655 last_obj = td; 3656 3657 usb_pc_cpu_flush(pc + n); 3658 } 3659 } 3660 if (usbd_transfer_setup_sub_malloc( 3661 parm, &pc, sizeof(ehci_sitd_t), 3662 EHCI_SITD_ALIGN, nsitd)) { 3663 parm->err = USB_ERR_NOMEM; 3664 return; 3665 } 3666 if (parm->buf) { 3667 for (n = 0; n != nsitd; n++) { 3668 ehci_sitd_t *td; 3669 3670 usbd_get_page(pc + n, 0, &page_info); 3671 3672 td = page_info.buffer; 3673 3674 /* init TD */ 3675 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD); 3676 td->obj_next = last_obj; 3677 td->page_cache = pc + n; 3678 3679 last_obj = td; 3680 3681 usb_pc_cpu_flush(pc + n); 3682 } 3683 } 3684 if (usbd_transfer_setup_sub_malloc( 3685 parm, &pc, sizeof(ehci_qtd_t), 3686 EHCI_QTD_ALIGN, nqtd)) { 3687 parm->err = USB_ERR_NOMEM; 3688 return; 3689 } 3690 if (parm->buf) { 3691 for (n = 0; n != nqtd; n++) { 3692 ehci_qtd_t *qtd; 3693 3694 usbd_get_page(pc + n, 0, &page_info); 3695 3696 qtd = page_info.buffer; 3697 3698 /* init TD */ 3699 qtd->qtd_self = htohc32(sc, page_info.physaddr); 3700 qtd->obj_next = last_obj; 3701 qtd->page_cache = pc + n; 3702 3703 last_obj = qtd; 3704 3705 usb_pc_cpu_flush(pc + n); 3706 } 3707 } 3708 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3709 3710 last_obj = NULL; 3711 3712 if (usbd_transfer_setup_sub_malloc( 3713 parm, &pc, sizeof(ehci_qh_t), 3714 EHCI_QH_ALIGN, nqh)) { 3715 parm->err = USB_ERR_NOMEM; 3716 return; 3717 } 3718 if (parm->buf) { 3719 for (n = 0; n != nqh; n++) { 3720 ehci_qh_t *qh; 3721 3722 usbd_get_page(pc + n, 0, &page_info); 3723 3724 qh = page_info.buffer; 3725 3726 /* init QH */ 3727 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH); 3728 qh->obj_next = last_obj; 3729 qh->page_cache = pc + n; 3730 3731 last_obj = qh; 3732 3733 usb_pc_cpu_flush(pc + n); 3734 } 3735 } 3736 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3737 3738 if (!xfer->flags_int.curr_dma_set) { 3739 xfer->flags_int.curr_dma_set = 1; 3740 goto alloc_dma_set; 3741 } 3742} 3743 3744static void 3745ehci_xfer_unsetup(struct usb_xfer *xfer) 3746{ 3747 return; 3748} 3749 3750static void 3751ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3752 struct usb_endpoint *ep) 3753{ 3754 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3755 3756 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3757 ep, udev->address, 3758 edesc->bEndpointAddress, udev->flags.usb_mode, 3759 sc->sc_addr); 3760 3761 if (udev->device_index != sc->sc_addr) { 3762 3763 if ((udev->speed != USB_SPEED_HIGH) && 3764 ((udev->hs_hub_addr == 0) || 3765 (udev->hs_port_no == 0) || 3766 (udev->parent_hs_hub == NULL) || 3767 (udev->parent_hs_hub->hub == NULL))) { 3768 /* We need a transaction translator */ 3769 goto done; 3770 } 3771 switch (edesc->bmAttributes & UE_XFERTYPE) { 3772 case UE_CONTROL: 3773 ep->methods = &ehci_device_ctrl_methods; 3774 break; 3775 case UE_INTERRUPT: 3776 ep->methods = &ehci_device_intr_methods; 3777 break; 3778 case UE_ISOCHRONOUS: 3779 if (udev->speed == USB_SPEED_HIGH) { 3780 ep->methods = &ehci_device_isoc_hs_methods; 3781 } else if (udev->speed == USB_SPEED_FULL) { 3782 ep->methods = &ehci_device_isoc_fs_methods; 3783 } 3784 break; 3785 case UE_BULK: 3786 ep->methods = &ehci_device_bulk_methods; 3787 break; 3788 default: 3789 /* do nothing */ 3790 break; 3791 } 3792 } 3793done: 3794 return; 3795} 3796 3797static void 3798ehci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3799{ 3800 /* 3801 * Wait until the hardware has finished any possible use of 3802 * the transfer descriptor(s) and QH 3803 */ 3804 *pus = (1125); /* microseconds */ 3805} 3806 3807static void 3808ehci_device_resume(struct usb_device *udev) 3809{ 3810 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3811 struct usb_xfer *xfer; 3812 const struct usb_pipe_methods *methods; 3813 3814 DPRINTF("\n"); 3815 3816 USB_BUS_LOCK(udev->bus); 3817 3818 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3819 3820 if (xfer->xroot->udev == udev) { 3821 3822 methods = xfer->endpoint->methods; 3823 3824 if ((methods == &ehci_device_bulk_methods) || 3825 (methods == &ehci_device_ctrl_methods)) { 3826 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3827 sc->sc_async_p_last); 3828 } 3829 if (methods == &ehci_device_intr_methods) { 3830 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3831 sc->sc_intr_p_last[xfer->qh_pos]); 3832 } 3833 } 3834 } 3835 3836 USB_BUS_UNLOCK(udev->bus); 3837 3838 return; 3839} 3840 3841static void 3842ehci_device_suspend(struct usb_device *udev) 3843{ 3844 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3845 struct usb_xfer *xfer; 3846 const struct usb_pipe_methods *methods; 3847 3848 DPRINTF("\n"); 3849 3850 USB_BUS_LOCK(udev->bus); 3851 3852 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3853 3854 if (xfer->xroot->udev == udev) { 3855 3856 methods = xfer->endpoint->methods; 3857 3858 if ((methods == &ehci_device_bulk_methods) || 3859 (methods == &ehci_device_ctrl_methods)) { 3860 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3861 sc->sc_async_p_last); 3862 } 3863 if (methods == &ehci_device_intr_methods) { 3864 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3865 sc->sc_intr_p_last[xfer->qh_pos]); 3866 } 3867 } 3868 } 3869 3870 USB_BUS_UNLOCK(udev->bus); 3871} 3872 3873static void 3874ehci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 3875{ 3876 struct ehci_softc *sc = EHCI_BUS2SC(bus); 3877 3878 switch (state) { 3879 case USB_HW_POWER_SUSPEND: 3880 case USB_HW_POWER_SHUTDOWN: 3881 ehci_suspend(sc); 3882 break; 3883 case USB_HW_POWER_RESUME: 3884 ehci_resume(sc); 3885 break; 3886 default: 3887 break; 3888 } 3889} 3890 3891static void 3892ehci_set_hw_power(struct usb_bus *bus) 3893{ 3894 ehci_softc_t *sc = EHCI_BUS2SC(bus); 3895 uint32_t temp; 3896 uint32_t flags; 3897 3898 DPRINTF("\n"); 3899 3900 USB_BUS_LOCK(bus); 3901 3902 flags = bus->hw_power_state; 3903 3904 temp = EOREAD4(sc, EHCI_USBCMD); 3905 3906 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 3907 3908 if (flags & (USB_HW_POWER_CONTROL | 3909 USB_HW_POWER_BULK)) { 3910 DPRINTF("Async is active\n"); 3911 temp |= EHCI_CMD_ASE; 3912 } 3913 if (flags & (USB_HW_POWER_INTERRUPT | 3914 USB_HW_POWER_ISOC)) { 3915 DPRINTF("Periodic is active\n"); 3916 temp |= EHCI_CMD_PSE; 3917 } 3918 EOWRITE4(sc, EHCI_USBCMD, temp); 3919 3920 USB_BUS_UNLOCK(bus); 3921 3922 return; 3923} 3924 3925static void 3926ehci_start_dma_delay_second(struct usb_xfer *xfer) 3927{ 3928 struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus); 3929 3930 DPRINTF("\n"); 3931 3932 /* trigger doorbell */ 3933 ehci_doorbell_async(sc); 3934 3935 /* give the doorbell 4ms */ 3936 usbd_transfer_timeout_ms(xfer, 3937 (void (*)(void *))&usb_dma_delay_done_cb, 4); 3938} 3939 3940/* 3941 * Ring the doorbell twice before freeing any DMA descriptors. Some host 3942 * controllers apparently cache the QH descriptors and need a message 3943 * that the cache needs to be discarded. 3944 */ 3945static void 3946ehci_start_dma_delay(struct usb_xfer *xfer) 3947{ 3948 struct ehci_softc *sc = EHCI_BUS2SC(xfer->xroot->bus); 3949 3950 DPRINTF("\n"); 3951 3952 /* trigger doorbell */ 3953 ehci_doorbell_async(sc); 3954 3955 /* give the doorbell 4ms */ 3956 usbd_transfer_timeout_ms(xfer, 3957 (void (*)(void *))&ehci_start_dma_delay_second, 4); 3958} 3959 3960static const struct usb_bus_methods ehci_bus_methods = 3961{ 3962 .endpoint_init = ehci_ep_init, 3963 .xfer_setup = ehci_xfer_setup, 3964 .xfer_unsetup = ehci_xfer_unsetup, 3965 .get_dma_delay = ehci_get_dma_delay, 3966 .device_resume = ehci_device_resume, 3967 .device_suspend = ehci_device_suspend, 3968 .set_hw_power = ehci_set_hw_power, 3969 .set_hw_power_sleep = ehci_set_hw_power_sleep, 3970 .roothub_exec = ehci_roothub_exec, 3971 .xfer_poll = ehci_do_poll, 3972 .start_dma_delay = ehci_start_dma_delay, 3973}; 3974