ehci.c revision 199675
1/*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 2004 Lennart Augustsson. All rights reserved. 5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 31 * 32 * The EHCI 0.96 spec can be found at 33 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 34 * The EHCI 1.0 spec can be found at 35 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 36 * and the USB 2.0 spec at 37 * http://www.usb.org/developers/docs/usb_20.zip 38 * 39 */ 40 41/* 42 * TODO: 43 * 1) command failures are not recovered correctly 44 */ 45 46#include <sys/cdefs.h> 47__FBSDID("$FreeBSD: head/sys/dev/usb/controller/ehci.c 199675 2009-11-22 21:21:22Z thompsa $"); 48 49#include <sys/stdint.h> 50#include <sys/stddef.h> 51#include <sys/param.h> 52#include <sys/queue.h> 53#include <sys/types.h> 54#include <sys/systm.h> 55#include <sys/kernel.h> 56#include <sys/bus.h> 57#include <sys/linker_set.h> 58#include <sys/module.h> 59#include <sys/lock.h> 60#include <sys/mutex.h> 61#include <sys/condvar.h> 62#include <sys/sysctl.h> 63#include <sys/sx.h> 64#include <sys/unistd.h> 65#include <sys/callout.h> 66#include <sys/malloc.h> 67#include <sys/priv.h> 68 69#include <dev/usb/usb.h> 70#include <dev/usb/usbdi.h> 71 72#define USB_DEBUG_VAR ehcidebug 73 74#include <dev/usb/usb_core.h> 75#include <dev/usb/usb_debug.h> 76#include <dev/usb/usb_busdma.h> 77#include <dev/usb/usb_process.h> 78#include <dev/usb/usb_transfer.h> 79#include <dev/usb/usb_device.h> 80#include <dev/usb/usb_hub.h> 81#include <dev/usb/usb_util.h> 82 83#include <dev/usb/usb_controller.h> 84#include <dev/usb/usb_bus.h> 85#include <dev/usb/controller/ehci.h> 86#include <dev/usb/controller/ehcireg.h> 87 88#define EHCI_BUS2SC(bus) \ 89 ((ehci_softc_t *)(((uint8_t *)(bus)) - \ 90 ((uint8_t *)&(((ehci_softc_t *)0)->sc_bus)))) 91 92#if USB_DEBUG 93static int ehcidebug = 0; 94static int ehcinohighspeed = 0; 95 96SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci"); 97SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RW, 98 &ehcidebug, 0, "Debug level"); 99SYSCTL_INT(_hw_usb_ehci, OID_AUTO, no_hs, CTLFLAG_RW, 100 &ehcinohighspeed, 0, "Disable High Speed USB"); 101 102TUNABLE_INT("hw.usb.ehci.debug", &ehcidebug); 103TUNABLE_INT("hw.usb.ehci.no_hs", &ehcinohighspeed); 104 105static void ehci_dump_regs(ehci_softc_t *sc); 106static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh); 107 108#endif 109 110#define EHCI_INTR_ENDPT 1 111 112extern struct usb_bus_methods ehci_bus_methods; 113extern struct usb_pipe_methods ehci_device_bulk_methods; 114extern struct usb_pipe_methods ehci_device_ctrl_methods; 115extern struct usb_pipe_methods ehci_device_intr_methods; 116extern struct usb_pipe_methods ehci_device_isoc_fs_methods; 117extern struct usb_pipe_methods ehci_device_isoc_hs_methods; 118 119static void ehci_do_poll(struct usb_bus *); 120static void ehci_device_done(struct usb_xfer *, usb_error_t); 121static uint8_t ehci_check_transfer(struct usb_xfer *); 122static void ehci_timeout(void *); 123static void ehci_poll_timeout(void *); 124 125static void ehci_root_intr(ehci_softc_t *sc); 126 127struct ehci_std_temp { 128 ehci_softc_t *sc; 129 struct usb_page_cache *pc; 130 ehci_qtd_t *td; 131 ehci_qtd_t *td_next; 132 uint32_t average; 133 uint32_t qtd_status; 134 uint32_t len; 135 uint16_t max_frame_size; 136 uint8_t shortpkt; 137 uint8_t auto_data_toggle; 138 uint8_t setup_alt_next; 139 uint8_t last_frame; 140 uint8_t can_use_next; 141}; 142 143void 144ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 145{ 146 ehci_softc_t *sc = EHCI_BUS2SC(bus); 147 uint32_t i; 148 149 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 150 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN); 151 152 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg, 153 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 154 155 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 156 cb(bus, sc->sc_hw.intr_start_pc + i, 157 sc->sc_hw.intr_start_pg + i, 158 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 159 } 160 161 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 162 cb(bus, sc->sc_hw.isoc_hs_start_pc + i, 163 sc->sc_hw.isoc_hs_start_pg + i, 164 sizeof(ehci_itd_t), EHCI_ITD_ALIGN); 165 } 166 167 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 168 cb(bus, sc->sc_hw.isoc_fs_start_pc + i, 169 sc->sc_hw.isoc_fs_start_pg + i, 170 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN); 171 } 172} 173 174usb_error_t 175ehci_reset(ehci_softc_t *sc) 176{ 177 uint32_t hcr; 178 int i; 179 180 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 181 for (i = 0; i < 100; i++) { 182 usb_pause_mtx(NULL, hz / 1000); 183 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 184 if (!hcr) { 185 if (sc->sc_flags & (EHCI_SCFLG_SETMODE | EHCI_SCFLG_BIGEMMIO)) { 186 /* 187 * Force USBMODE as requested. Controllers 188 * may have multiple operating modes. 189 */ 190 uint32_t usbmode = EOREAD4(sc, EHCI_USBMODE); 191 if (sc->sc_flags & EHCI_SCFLG_SETMODE) { 192 usbmode = (usbmode &~ EHCI_UM_CM) | EHCI_UM_CM_HOST; 193 device_printf(sc->sc_bus.bdev, 194 "set host controller mode\n"); 195 } 196 if (sc->sc_flags & EHCI_SCFLG_BIGEMMIO) { 197 usbmode = (usbmode &~ EHCI_UM_ES) | EHCI_UM_ES_BE; 198 device_printf(sc->sc_bus.bdev, 199 "set big-endian mode\n"); 200 } 201 EOWRITE4(sc, EHCI_USBMODE, usbmode); 202 } 203 return (0); 204 } 205 } 206 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 207 return (USB_ERR_IOERROR); 208} 209 210static usb_error_t 211ehci_hcreset(ehci_softc_t *sc) 212{ 213 uint32_t hcr; 214 int i; 215 216 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 217 for (i = 0; i < 100; i++) { 218 usb_pause_mtx(NULL, hz / 1000); 219 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 220 if (hcr) 221 break; 222 } 223 if (!hcr) 224 /* 225 * Fall through and try reset anyway even though 226 * Table 2-9 in the EHCI spec says this will result 227 * in undefined behavior. 228 */ 229 device_printf(sc->sc_bus.bdev, "stop timeout\n"); 230 231 return ehci_reset(sc); 232} 233 234usb_error_t 235ehci_init(ehci_softc_t *sc) 236{ 237 struct usb_page_search buf_res; 238 uint32_t version; 239 uint32_t sparams; 240 uint32_t cparams; 241 uint32_t hcr; 242 uint16_t i; 243 uint16_t x; 244 uint16_t y; 245 uint16_t bit; 246 usb_error_t err = 0; 247 248 DPRINTF("start\n"); 249 250 usb_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0); 251 usb_callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_mtx, 0); 252 253#if USB_DEBUG 254 if (ehcidebug > 2) { 255 ehci_dump_regs(sc); 256 } 257#endif 258 259 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 260 261 version = EREAD2(sc, EHCI_HCIVERSION); 262 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n", 263 version >> 8, version & 0xff); 264 265 sparams = EREAD4(sc, EHCI_HCSPARAMS); 266 DPRINTF("sparams=0x%x\n", sparams); 267 268 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 269 cparams = EREAD4(sc, EHCI_HCCPARAMS); 270 DPRINTF("cparams=0x%x\n", cparams); 271 272 if (EHCI_HCC_64BIT(cparams)) { 273 DPRINTF("HCC uses 64-bit structures\n"); 274 275 /* MUST clear segment register if 64 bit capable */ 276 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 277 } 278 sc->sc_bus.usbrev = USB_REV_2_0; 279 280 /* Reset the controller */ 281 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)); 282 283 err = ehci_hcreset(sc); 284 if (err) { 285 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 286 return (err); 287 } 288 /* 289 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4 290 * bytes 2: 256*4 bytes 3: unknown 291 */ 292 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) { 293 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n"); 294 return (USB_ERR_IOERROR); 295 } 296 /* set up the bus struct */ 297 sc->sc_bus.methods = &ehci_bus_methods; 298 299 sc->sc_eintrs = EHCI_NORMAL_INTRS; 300 301 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 302 ehci_qh_t *qh; 303 304 usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res); 305 306 qh = buf_res.buffer; 307 308 /* initialize page cache pointer */ 309 310 qh->page_cache = sc->sc_hw.intr_start_pc + i; 311 312 /* store a pointer to queue head */ 313 314 sc->sc_intr_p_last[i] = qh; 315 316 qh->qh_self = 317 htohc32(sc, buf_res.physaddr) | 318 htohc32(sc, EHCI_LINK_QH); 319 320 qh->qh_endp = 321 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 322 qh->qh_endphub = 323 htohc32(sc, EHCI_QH_SET_MULT(1)); 324 qh->qh_curqtd = 0; 325 326 qh->qh_qtd.qtd_next = 327 htohc32(sc, EHCI_LINK_TERMINATE); 328 qh->qh_qtd.qtd_altnext = 329 htohc32(sc, EHCI_LINK_TERMINATE); 330 qh->qh_qtd.qtd_status = 331 htohc32(sc, EHCI_QTD_HALTED); 332 } 333 334 /* 335 * the QHs are arranged to give poll intervals that are 336 * powers of 2 times 1ms 337 */ 338 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 339 while (bit) { 340 x = bit; 341 while (x & bit) { 342 ehci_qh_t *qh_x; 343 ehci_qh_t *qh_y; 344 345 y = (x ^ bit) | (bit / 2); 346 347 qh_x = sc->sc_intr_p_last[x]; 348 qh_y = sc->sc_intr_p_last[y]; 349 350 /* 351 * the next QH has half the poll interval 352 */ 353 qh_x->qh_link = qh_y->qh_self; 354 355 x++; 356 } 357 bit >>= 1; 358 } 359 360 if (1) { 361 ehci_qh_t *qh; 362 363 qh = sc->sc_intr_p_last[0]; 364 365 /* the last (1ms) QH terminates */ 366 qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE); 367 } 368 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 369 ehci_sitd_t *sitd; 370 ehci_itd_t *itd; 371 372 usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res); 373 374 sitd = buf_res.buffer; 375 376 /* initialize page cache pointer */ 377 378 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i; 379 380 /* store a pointer to the transfer descriptor */ 381 382 sc->sc_isoc_fs_p_last[i] = sitd; 383 384 /* initialize full speed isochronous */ 385 386 sitd->sitd_self = 387 htohc32(sc, buf_res.physaddr) | 388 htohc32(sc, EHCI_LINK_SITD); 389 390 sitd->sitd_back = 391 htohc32(sc, EHCI_LINK_TERMINATE); 392 393 sitd->sitd_next = 394 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self; 395 396 397 usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res); 398 399 itd = buf_res.buffer; 400 401 /* initialize page cache pointer */ 402 403 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i; 404 405 /* store a pointer to the transfer descriptor */ 406 407 sc->sc_isoc_hs_p_last[i] = itd; 408 409 /* initialize high speed isochronous */ 410 411 itd->itd_self = 412 htohc32(sc, buf_res.physaddr) | 413 htohc32(sc, EHCI_LINK_ITD); 414 415 itd->itd_next = 416 sitd->sitd_self; 417 } 418 419 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 420 421 if (1) { 422 uint32_t *pframes; 423 424 pframes = buf_res.buffer; 425 426 /* 427 * execution order: 428 * pframes -> high speed isochronous -> 429 * full speed isochronous -> interrupt QH's 430 */ 431 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) { 432 pframes[i] = sc->sc_isoc_hs_p_last 433 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self; 434 } 435 } 436 /* setup sync list pointer */ 437 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 438 439 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 440 441 if (1) { 442 443 ehci_qh_t *qh; 444 445 qh = buf_res.buffer; 446 447 /* initialize page cache pointer */ 448 449 qh->page_cache = &sc->sc_hw.async_start_pc; 450 451 /* store a pointer to the queue head */ 452 453 sc->sc_async_p_last = qh; 454 455 /* init dummy QH that starts the async list */ 456 457 qh->qh_self = 458 htohc32(sc, buf_res.physaddr) | 459 htohc32(sc, EHCI_LINK_QH); 460 461 /* fill the QH */ 462 qh->qh_endp = 463 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 464 qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1)); 465 qh->qh_link = qh->qh_self; 466 qh->qh_curqtd = 0; 467 468 /* fill the overlay qTD */ 469 qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE); 470 qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE); 471 qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED); 472 } 473 /* flush all cache into memory */ 474 475 usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc); 476 477#if USB_DEBUG 478 if (ehcidebug) { 479 ehci_dump_sqh(sc, sc->sc_async_p_last); 480 } 481#endif 482 483 /* setup async list pointer */ 484 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 485 486 487 /* enable interrupts */ 488 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 489 490 /* turn on controller */ 491 EOWRITE4(sc, EHCI_USBCMD, 492 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */ 493 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 494 EHCI_CMD_ASE | 495 EHCI_CMD_PSE | 496 EHCI_CMD_RS); 497 498 /* Take over port ownership */ 499 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 500 501 for (i = 0; i < 100; i++) { 502 usb_pause_mtx(NULL, hz / 1000); 503 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 504 if (!hcr) { 505 break; 506 } 507 } 508 if (hcr) { 509 device_printf(sc->sc_bus.bdev, "run timeout\n"); 510 return (USB_ERR_IOERROR); 511 } 512 513 if (!err) { 514 /* catch any lost interrupts */ 515 ehci_do_poll(&sc->sc_bus); 516 } 517 return (err); 518} 519 520/* 521 * shut down the controller when the system is going down 522 */ 523void 524ehci_detach(ehci_softc_t *sc) 525{ 526 USB_BUS_LOCK(&sc->sc_bus); 527 528 usb_callout_stop(&sc->sc_tmo_pcd); 529 usb_callout_stop(&sc->sc_tmo_poll); 530 531 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 532 USB_BUS_UNLOCK(&sc->sc_bus); 533 534 if (ehci_hcreset(sc)) { 535 DPRINTF("reset failed!\n"); 536 } 537 538 /* XXX let stray task complete */ 539 usb_pause_mtx(NULL, hz / 20); 540 541 usb_callout_drain(&sc->sc_tmo_pcd); 542 usb_callout_drain(&sc->sc_tmo_poll); 543} 544 545void 546ehci_suspend(ehci_softc_t *sc) 547{ 548 uint32_t cmd; 549 uint32_t hcr; 550 uint8_t i; 551 552 USB_BUS_LOCK(&sc->sc_bus); 553 554 for (i = 1; i <= sc->sc_noport; i++) { 555 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 556 if (((cmd & EHCI_PS_PO) == 0) && 557 ((cmd & EHCI_PS_PE) == EHCI_PS_PE)) { 558 EOWRITE4(sc, EHCI_PORTSC(i), 559 cmd | EHCI_PS_SUSP); 560 } 561 } 562 563 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 564 565 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 566 EOWRITE4(sc, EHCI_USBCMD, cmd); 567 568 for (i = 0; i < 100; i++) { 569 hcr = EOREAD4(sc, EHCI_USBSTS) & 570 (EHCI_STS_ASS | EHCI_STS_PSS); 571 572 if (hcr == 0) { 573 break; 574 } 575 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 576 } 577 578 if (hcr != 0) { 579 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 580 } 581 cmd &= ~EHCI_CMD_RS; 582 EOWRITE4(sc, EHCI_USBCMD, cmd); 583 584 for (i = 0; i < 100; i++) { 585 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 586 if (hcr == EHCI_STS_HCH) { 587 break; 588 } 589 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 590 } 591 592 if (hcr != EHCI_STS_HCH) { 593 device_printf(sc->sc_bus.bdev, 594 "config timeout\n"); 595 } 596 USB_BUS_UNLOCK(&sc->sc_bus); 597} 598 599void 600ehci_resume(ehci_softc_t *sc) 601{ 602 struct usb_page_search buf_res; 603 uint32_t cmd; 604 uint32_t hcr; 605 uint8_t i; 606 607 USB_BUS_LOCK(&sc->sc_bus); 608 609 /* restore things in case the bios doesn't */ 610 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 611 612 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 613 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 614 615 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 616 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 617 618 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 619 620 hcr = 0; 621 for (i = 1; i <= sc->sc_noport; i++) { 622 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 623 if (((cmd & EHCI_PS_PO) == 0) && 624 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) { 625 EOWRITE4(sc, EHCI_PORTSC(i), 626 cmd | EHCI_PS_FPR); 627 hcr = 1; 628 } 629 } 630 631 if (hcr) { 632 usb_pause_mtx(&sc->sc_bus.bus_mtx, 633 USB_MS_TO_TICKS(USB_RESUME_WAIT)); 634 635 for (i = 1; i <= sc->sc_noport; i++) { 636 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 637 if (((cmd & EHCI_PS_PO) == 0) && 638 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) { 639 EOWRITE4(sc, EHCI_PORTSC(i), 640 cmd & ~EHCI_PS_FPR); 641 } 642 } 643 } 644 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 645 646 for (i = 0; i < 100; i++) { 647 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 648 if (hcr != EHCI_STS_HCH) { 649 break; 650 } 651 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000); 652 } 653 if (hcr == EHCI_STS_HCH) { 654 device_printf(sc->sc_bus.bdev, "config timeout\n"); 655 } 656 657 USB_BUS_UNLOCK(&sc->sc_bus); 658 659 usb_pause_mtx(NULL, 660 USB_MS_TO_TICKS(USB_RESUME_WAIT)); 661 662 /* catch any lost interrupts */ 663 ehci_do_poll(&sc->sc_bus); 664} 665 666void 667ehci_shutdown(ehci_softc_t *sc) 668{ 669 DPRINTF("stopping the HC\n"); 670 671 if (ehci_hcreset(sc)) { 672 DPRINTF("reset failed!\n"); 673 } 674} 675 676#if USB_DEBUG 677static void 678ehci_dump_regs(ehci_softc_t *sc) 679{ 680 uint32_t i; 681 682 i = EOREAD4(sc, EHCI_USBCMD); 683 printf("cmd=0x%08x\n", i); 684 685 if (i & EHCI_CMD_ITC_1) 686 printf(" EHCI_CMD_ITC_1\n"); 687 if (i & EHCI_CMD_ITC_2) 688 printf(" EHCI_CMD_ITC_2\n"); 689 if (i & EHCI_CMD_ITC_4) 690 printf(" EHCI_CMD_ITC_4\n"); 691 if (i & EHCI_CMD_ITC_8) 692 printf(" EHCI_CMD_ITC_8\n"); 693 if (i & EHCI_CMD_ITC_16) 694 printf(" EHCI_CMD_ITC_16\n"); 695 if (i & EHCI_CMD_ITC_32) 696 printf(" EHCI_CMD_ITC_32\n"); 697 if (i & EHCI_CMD_ITC_64) 698 printf(" EHCI_CMD_ITC_64\n"); 699 if (i & EHCI_CMD_ASPME) 700 printf(" EHCI_CMD_ASPME\n"); 701 if (i & EHCI_CMD_ASPMC) 702 printf(" EHCI_CMD_ASPMC\n"); 703 if (i & EHCI_CMD_LHCR) 704 printf(" EHCI_CMD_LHCR\n"); 705 if (i & EHCI_CMD_IAAD) 706 printf(" EHCI_CMD_IAAD\n"); 707 if (i & EHCI_CMD_ASE) 708 printf(" EHCI_CMD_ASE\n"); 709 if (i & EHCI_CMD_PSE) 710 printf(" EHCI_CMD_PSE\n"); 711 if (i & EHCI_CMD_FLS_M) 712 printf(" EHCI_CMD_FLS_M\n"); 713 if (i & EHCI_CMD_HCRESET) 714 printf(" EHCI_CMD_HCRESET\n"); 715 if (i & EHCI_CMD_RS) 716 printf(" EHCI_CMD_RS\n"); 717 718 i = EOREAD4(sc, EHCI_USBSTS); 719 720 printf("sts=0x%08x\n", i); 721 722 if (i & EHCI_STS_ASS) 723 printf(" EHCI_STS_ASS\n"); 724 if (i & EHCI_STS_PSS) 725 printf(" EHCI_STS_PSS\n"); 726 if (i & EHCI_STS_REC) 727 printf(" EHCI_STS_REC\n"); 728 if (i & EHCI_STS_HCH) 729 printf(" EHCI_STS_HCH\n"); 730 if (i & EHCI_STS_IAA) 731 printf(" EHCI_STS_IAA\n"); 732 if (i & EHCI_STS_HSE) 733 printf(" EHCI_STS_HSE\n"); 734 if (i & EHCI_STS_FLR) 735 printf(" EHCI_STS_FLR\n"); 736 if (i & EHCI_STS_PCD) 737 printf(" EHCI_STS_PCD\n"); 738 if (i & EHCI_STS_ERRINT) 739 printf(" EHCI_STS_ERRINT\n"); 740 if (i & EHCI_STS_INT) 741 printf(" EHCI_STS_INT\n"); 742 743 printf("ien=0x%08x\n", 744 EOREAD4(sc, EHCI_USBINTR)); 745 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 746 EOREAD4(sc, EHCI_FRINDEX), 747 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 748 EOREAD4(sc, EHCI_PERIODICLISTBASE), 749 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 750 for (i = 1; i <= sc->sc_noport; i++) { 751 printf("port %d status=0x%08x\n", i, 752 EOREAD4(sc, EHCI_PORTSC(i))); 753 } 754} 755 756static void 757ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type) 758{ 759 link = hc32toh(sc, link); 760 printf("0x%08x", link); 761 if (link & EHCI_LINK_TERMINATE) 762 printf("<T>"); 763 else { 764 printf("<"); 765 if (type) { 766 switch (EHCI_LINK_TYPE(link)) { 767 case EHCI_LINK_ITD: 768 printf("ITD"); 769 break; 770 case EHCI_LINK_QH: 771 printf("QH"); 772 break; 773 case EHCI_LINK_SITD: 774 printf("SITD"); 775 break; 776 case EHCI_LINK_FSTN: 777 printf("FSTN"); 778 break; 779 } 780 } 781 printf(">"); 782 } 783} 784 785static void 786ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd) 787{ 788 uint32_t s; 789 790 printf(" next="); 791 ehci_dump_link(sc, qtd->qtd_next, 0); 792 printf(" altnext="); 793 ehci_dump_link(sc, qtd->qtd_altnext, 0); 794 printf("\n"); 795 s = hc32toh(sc, qtd->qtd_status); 796 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 797 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 798 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 799 printf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n", 800 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), 801 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE", 802 (s & EHCI_QTD_HALTED) ? "-HALTED" : "", 803 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "", 804 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "", 805 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "", 806 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "", 807 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "", 808 (s & EHCI_QTD_PINGSTATE) ? "-PING" : ""); 809 810 for (s = 0; s < 5; s++) { 811 printf(" buffer[%d]=0x%08x\n", s, 812 hc32toh(sc, qtd->qtd_buffer[s])); 813 } 814 for (s = 0; s < 5; s++) { 815 printf(" buffer_hi[%d]=0x%08x\n", s, 816 hc32toh(sc, qtd->qtd_buffer_hi[s])); 817 } 818} 819 820static uint8_t 821ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd) 822{ 823 uint8_t temp; 824 825 usb_pc_cpu_invalidate(sqtd->page_cache); 826 printf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self)); 827 ehci_dump_qtd(sc, sqtd); 828 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0; 829 return (temp); 830} 831 832static void 833ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd) 834{ 835 uint16_t i; 836 uint8_t stop; 837 838 stop = 0; 839 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) { 840 stop = ehci_dump_sqtd(sc, sqtd); 841 } 842 if (sqtd) { 843 printf("dump aborted, too many TDs\n"); 844 } 845} 846 847static void 848ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh) 849{ 850 uint32_t endp; 851 uint32_t endphub; 852 853 usb_pc_cpu_invalidate(qh->page_cache); 854 printf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F); 855 printf(" link="); 856 ehci_dump_link(sc, qh->qh_link, 1); 857 printf("\n"); 858 endp = hc32toh(sc, qh->qh_endp); 859 printf(" endp=0x%08x\n", endp); 860 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 861 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 862 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 863 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 864 printf(" mpl=0x%x ctl=%d nrl=%d\n", 865 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 866 EHCI_QH_GET_NRL(endp)); 867 endphub = hc32toh(sc, qh->qh_endphub); 868 printf(" endphub=0x%08x\n", endphub); 869 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 870 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 871 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 872 EHCI_QH_GET_MULT(endphub)); 873 printf(" curqtd="); 874 ehci_dump_link(sc, qh->qh_curqtd, 0); 875 printf("\n"); 876 printf("Overlay qTD:\n"); 877 ehci_dump_qtd(sc, (void *)&qh->qh_qtd); 878} 879 880static void 881ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd) 882{ 883 usb_pc_cpu_invalidate(sitd->page_cache); 884 printf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F); 885 printf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next)); 886 printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n", 887 hc32toh(sc, sitd->sitd_portaddr), 888 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN)) 889 ? "in" : "out", 890 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)), 891 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)), 892 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)), 893 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr))); 894 printf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask)); 895 printf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status), 896 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "", 897 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status))); 898 printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n", 899 hc32toh(sc, sitd->sitd_back), 900 hc32toh(sc, sitd->sitd_bp[0]), 901 hc32toh(sc, sitd->sitd_bp[1]), 902 hc32toh(sc, sitd->sitd_bp_hi[0]), 903 hc32toh(sc, sitd->sitd_bp_hi[1])); 904} 905 906static void 907ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd) 908{ 909 usb_pc_cpu_invalidate(itd->page_cache); 910 printf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F); 911 printf(" next=0x%08x\n", hc32toh(sc, itd->itd_next)); 912 printf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]), 913 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 914 printf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]), 915 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 916 printf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]), 917 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 918 printf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]), 919 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 920 printf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]), 921 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 922 printf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]), 923 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 924 printf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]), 925 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 926 printf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]), 927 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 928 printf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0])); 929 printf(" addr=0x%02x; endpt=0x%01x\n", 930 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])), 931 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0]))); 932 printf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1])); 933 printf(" dir=%s; mpl=0x%02x\n", 934 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out", 935 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1]))); 936 printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n", 937 hc32toh(sc, itd->itd_bp[2]), 938 hc32toh(sc, itd->itd_bp[3]), 939 hc32toh(sc, itd->itd_bp[4]), 940 hc32toh(sc, itd->itd_bp[5]), 941 hc32toh(sc, itd->itd_bp[6])); 942 printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n" 943 " 0x%08x,0x%08x,0x%08x\n", 944 hc32toh(sc, itd->itd_bp_hi[0]), 945 hc32toh(sc, itd->itd_bp_hi[1]), 946 hc32toh(sc, itd->itd_bp_hi[2]), 947 hc32toh(sc, itd->itd_bp_hi[3]), 948 hc32toh(sc, itd->itd_bp_hi[4]), 949 hc32toh(sc, itd->itd_bp_hi[5]), 950 hc32toh(sc, itd->itd_bp_hi[6])); 951} 952 953static void 954ehci_dump_isoc(ehci_softc_t *sc) 955{ 956 ehci_itd_t *itd; 957 ehci_sitd_t *sitd; 958 uint16_t max = 1000; 959 uint16_t pos; 960 961 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) & 962 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 963 964 printf("%s: isochronous dump from frame 0x%03x:\n", 965 __FUNCTION__, pos); 966 967 itd = sc->sc_isoc_hs_p_last[pos]; 968 sitd = sc->sc_isoc_fs_p_last[pos]; 969 970 while (itd && max && max--) { 971 ehci_dump_itd(sc, itd); 972 itd = itd->prev; 973 } 974 975 while (sitd && max && max--) { 976 ehci_dump_sitd(sc, sitd); 977 sitd = sitd->prev; 978 } 979} 980 981#endif 982 983static void 984ehci_transfer_intr_enqueue(struct usb_xfer *xfer) 985{ 986 /* check for early completion */ 987 if (ehci_check_transfer(xfer)) { 988 return; 989 } 990 /* put transfer on interrupt queue */ 991 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 992 993 /* start timeout, if any */ 994 if (xfer->timeout != 0) { 995 usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout); 996 } 997} 998 999#define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last) 1000static ehci_sitd_t * 1001_ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 1002{ 1003 DPRINTFN(11, "%p to %p\n", std, last); 1004 1005 /* (sc->sc_bus.mtx) must be locked */ 1006 1007 std->next = last->next; 1008 std->sitd_next = last->sitd_next; 1009 1010 std->prev = last; 1011 1012 usb_pc_cpu_flush(std->page_cache); 1013 1014 /* 1015 * the last->next->prev is never followed: std->next->prev = std; 1016 */ 1017 last->next = std; 1018 last->sitd_next = std->sitd_self; 1019 1020 usb_pc_cpu_flush(last->page_cache); 1021 1022 return (std); 1023} 1024 1025#define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last) 1026static ehci_itd_t * 1027_ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1028{ 1029 DPRINTFN(11, "%p to %p\n", std, last); 1030 1031 /* (sc->sc_bus.mtx) must be locked */ 1032 1033 std->next = last->next; 1034 std->itd_next = last->itd_next; 1035 1036 std->prev = last; 1037 1038 usb_pc_cpu_flush(std->page_cache); 1039 1040 /* 1041 * the last->next->prev is never followed: std->next->prev = std; 1042 */ 1043 last->next = std; 1044 last->itd_next = std->itd_self; 1045 1046 usb_pc_cpu_flush(last->page_cache); 1047 1048 return (std); 1049} 1050 1051#define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last) 1052static ehci_qh_t * 1053_ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1054{ 1055 DPRINTFN(11, "%p to %p\n", sqh, last); 1056 1057 if (sqh->prev != NULL) { 1058 /* should not happen */ 1059 DPRINTFN(0, "QH already linked!\n"); 1060 return (last); 1061 } 1062 /* (sc->sc_bus.mtx) must be locked */ 1063 1064 sqh->next = last->next; 1065 sqh->qh_link = last->qh_link; 1066 1067 sqh->prev = last; 1068 1069 usb_pc_cpu_flush(sqh->page_cache); 1070 1071 /* 1072 * the last->next->prev is never followed: sqh->next->prev = sqh; 1073 */ 1074 1075 last->next = sqh; 1076 last->qh_link = sqh->qh_self; 1077 1078 usb_pc_cpu_flush(last->page_cache); 1079 1080 return (sqh); 1081} 1082 1083#define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last) 1084static ehci_sitd_t * 1085_ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 1086{ 1087 DPRINTFN(11, "%p from %p\n", std, last); 1088 1089 /* (sc->sc_bus.mtx) must be locked */ 1090 1091 std->prev->next = std->next; 1092 std->prev->sitd_next = std->sitd_next; 1093 1094 usb_pc_cpu_flush(std->prev->page_cache); 1095 1096 if (std->next) { 1097 std->next->prev = std->prev; 1098 usb_pc_cpu_flush(std->next->page_cache); 1099 } 1100 return ((last == std) ? std->prev : last); 1101} 1102 1103#define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last) 1104static ehci_itd_t * 1105_ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1106{ 1107 DPRINTFN(11, "%p from %p\n", std, last); 1108 1109 /* (sc->sc_bus.mtx) must be locked */ 1110 1111 std->prev->next = std->next; 1112 std->prev->itd_next = std->itd_next; 1113 1114 usb_pc_cpu_flush(std->prev->page_cache); 1115 1116 if (std->next) { 1117 std->next->prev = std->prev; 1118 usb_pc_cpu_flush(std->next->page_cache); 1119 } 1120 return ((last == std) ? std->prev : last); 1121} 1122 1123#define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last) 1124static ehci_qh_t * 1125_ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1126{ 1127 DPRINTFN(11, "%p from %p\n", sqh, last); 1128 1129 /* (sc->sc_bus.mtx) must be locked */ 1130 1131 /* only remove if not removed from a queue */ 1132 if (sqh->prev) { 1133 1134 sqh->prev->next = sqh->next; 1135 sqh->prev->qh_link = sqh->qh_link; 1136 1137 usb_pc_cpu_flush(sqh->prev->page_cache); 1138 1139 if (sqh->next) { 1140 sqh->next->prev = sqh->prev; 1141 usb_pc_cpu_flush(sqh->next->page_cache); 1142 } 1143 last = ((last == sqh) ? sqh->prev : last); 1144 1145 sqh->prev = 0; 1146 1147 usb_pc_cpu_flush(sqh->page_cache); 1148 } 1149 return (last); 1150} 1151 1152static usb_error_t 1153ehci_non_isoc_done_sub(struct usb_xfer *xfer) 1154{ 1155 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1156 ehci_qtd_t *td; 1157 ehci_qtd_t *td_alt_next; 1158 uint32_t status; 1159 uint16_t len; 1160 1161 td = xfer->td_transfer_cache; 1162 td_alt_next = td->alt_next; 1163 1164 if (xfer->aframes != xfer->nframes) { 1165 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 1166 } 1167 while (1) { 1168 1169 usb_pc_cpu_invalidate(td->page_cache); 1170 status = hc32toh(sc, td->qtd_status); 1171 1172 len = EHCI_QTD_GET_BYTES(status); 1173 1174 /* 1175 * Verify the status length and 1176 * add the length to "frlengths[]": 1177 */ 1178 if (len > td->len) { 1179 /* should not happen */ 1180 DPRINTF("Invalid status length, " 1181 "0x%04x/0x%04x bytes\n", len, td->len); 1182 status |= EHCI_QTD_HALTED; 1183 } else if (xfer->aframes != xfer->nframes) { 1184 xfer->frlengths[xfer->aframes] += td->len - len; 1185 } 1186 /* Check for last transfer */ 1187 if (((void *)td) == xfer->td_transfer_last) { 1188 td = NULL; 1189 break; 1190 } 1191 /* Check for transfer error */ 1192 if (status & EHCI_QTD_HALTED) { 1193 /* the transfer is finished */ 1194 td = NULL; 1195 break; 1196 } 1197 /* Check for short transfer */ 1198 if (len > 0) { 1199 if (xfer->flags_int.short_frames_ok) { 1200 /* follow alt next */ 1201 td = td->alt_next; 1202 } else { 1203 /* the transfer is finished */ 1204 td = NULL; 1205 } 1206 break; 1207 } 1208 td = td->obj_next; 1209 1210 if (td->alt_next != td_alt_next) { 1211 /* this USB frame is complete */ 1212 break; 1213 } 1214 } 1215 1216 /* update transfer cache */ 1217 1218 xfer->td_transfer_cache = td; 1219 1220#if USB_DEBUG 1221 if (status & EHCI_QTD_STATERRS) { 1222 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x" 1223 "status=%s%s%s%s%s%s%s%s\n", 1224 xfer->address, xfer->endpointno, xfer->aframes, 1225 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1226 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "", 1227 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "", 1228 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "", 1229 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "", 1230 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "", 1231 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "", 1232 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : ""); 1233 } 1234#endif 1235 1236 return ((status & EHCI_QTD_HALTED) ? 1237 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1238} 1239 1240static void 1241ehci_non_isoc_done(struct usb_xfer *xfer) 1242{ 1243 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1244 ehci_qh_t *qh; 1245 uint32_t status; 1246 usb_error_t err = 0; 1247 1248 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1249 xfer, xfer->endpoint); 1250 1251#if USB_DEBUG 1252 if (ehcidebug > 10) { 1253 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1254 1255 ehci_dump_sqtds(sc, xfer->td_transfer_first); 1256 } 1257#endif 1258 1259 /* extract data toggle directly from the QH's overlay area */ 1260 1261 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1262 1263 usb_pc_cpu_invalidate(qh->page_cache); 1264 1265 status = hc32toh(sc, qh->qh_qtd.qtd_status); 1266 1267 xfer->endpoint->toggle_next = 1268 (status & EHCI_QTD_TOGGLE_MASK) ? 1 : 0; 1269 1270 /* reset scanner */ 1271 1272 xfer->td_transfer_cache = xfer->td_transfer_first; 1273 1274 if (xfer->flags_int.control_xfr) { 1275 1276 if (xfer->flags_int.control_hdr) { 1277 1278 err = ehci_non_isoc_done_sub(xfer); 1279 } 1280 xfer->aframes = 1; 1281 1282 if (xfer->td_transfer_cache == NULL) { 1283 goto done; 1284 } 1285 } 1286 while (xfer->aframes != xfer->nframes) { 1287 1288 err = ehci_non_isoc_done_sub(xfer); 1289 xfer->aframes++; 1290 1291 if (xfer->td_transfer_cache == NULL) { 1292 goto done; 1293 } 1294 } 1295 1296 if (xfer->flags_int.control_xfr && 1297 !xfer->flags_int.control_act) { 1298 1299 err = ehci_non_isoc_done_sub(xfer); 1300 } 1301done: 1302 ehci_device_done(xfer, err); 1303} 1304 1305/*------------------------------------------------------------------------* 1306 * ehci_check_transfer 1307 * 1308 * Return values: 1309 * 0: USB transfer is not finished 1310 * Else: USB transfer is finished 1311 *------------------------------------------------------------------------*/ 1312static uint8_t 1313ehci_check_transfer(struct usb_xfer *xfer) 1314{ 1315 struct usb_pipe_methods *methods = xfer->endpoint->methods; 1316 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1317 1318 uint32_t status; 1319 1320 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1321 1322 if (methods == &ehci_device_isoc_fs_methods) { 1323 ehci_sitd_t *td; 1324 1325 /* isochronous full speed transfer */ 1326 1327 td = xfer->td_transfer_last; 1328 usb_pc_cpu_invalidate(td->page_cache); 1329 status = hc32toh(sc, td->sitd_status); 1330 1331 /* also check if first is complete */ 1332 1333 td = xfer->td_transfer_first; 1334 usb_pc_cpu_invalidate(td->page_cache); 1335 status |= hc32toh(sc, td->sitd_status); 1336 1337 if (!(status & EHCI_SITD_ACTIVE)) { 1338 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1339 goto transferred; 1340 } 1341 } else if (methods == &ehci_device_isoc_hs_methods) { 1342 ehci_itd_t *td; 1343 1344 /* isochronous high speed transfer */ 1345 1346 td = xfer->td_transfer_last; 1347 usb_pc_cpu_invalidate(td->page_cache); 1348 status = 1349 td->itd_status[0] | td->itd_status[1] | 1350 td->itd_status[2] | td->itd_status[3] | 1351 td->itd_status[4] | td->itd_status[5] | 1352 td->itd_status[6] | td->itd_status[7]; 1353 1354 /* also check first transfer */ 1355 td = xfer->td_transfer_first; 1356 usb_pc_cpu_invalidate(td->page_cache); 1357 status |= 1358 td->itd_status[0] | td->itd_status[1] | 1359 td->itd_status[2] | td->itd_status[3] | 1360 td->itd_status[4] | td->itd_status[5] | 1361 td->itd_status[6] | td->itd_status[7]; 1362 1363 /* if no transactions are active we continue */ 1364 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) { 1365 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1366 goto transferred; 1367 } 1368 } else { 1369 ehci_qtd_t *td; 1370 ehci_qh_t *qh; 1371 1372 /* non-isochronous transfer */ 1373 1374 /* 1375 * check whether there is an error somewhere in the middle, 1376 * or whether there was a short packet (SPD and not ACTIVE) 1377 */ 1378 td = xfer->td_transfer_cache; 1379 1380 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1381 1382 usb_pc_cpu_invalidate(qh->page_cache); 1383 1384 status = hc32toh(sc, qh->qh_qtd.qtd_status); 1385 if (status & EHCI_QTD_ACTIVE) { 1386 /* transfer is pending */ 1387 goto done; 1388 } 1389 1390 while (1) { 1391 usb_pc_cpu_invalidate(td->page_cache); 1392 status = hc32toh(sc, td->qtd_status); 1393 1394 /* 1395 * Check if there is an active TD which 1396 * indicates that the transfer isn't done. 1397 */ 1398 if (status & EHCI_QTD_ACTIVE) { 1399 /* update cache */ 1400 if (xfer->td_transfer_cache != td) { 1401 xfer->td_transfer_cache = td; 1402 if (qh->qh_qtd.qtd_next & 1403 htohc32(sc, EHCI_LINK_TERMINATE)) { 1404 /* XXX - manually advance to next frame */ 1405 qh->qh_qtd.qtd_next = td->qtd_self; 1406 usb_pc_cpu_flush(td->page_cache); 1407 } 1408 } 1409 goto done; 1410 } 1411 /* 1412 * last transfer descriptor makes the transfer done 1413 */ 1414 if (((void *)td) == xfer->td_transfer_last) { 1415 break; 1416 } 1417 /* 1418 * any kind of error makes the transfer done 1419 */ 1420 if (status & EHCI_QTD_HALTED) { 1421 break; 1422 } 1423 /* 1424 * if there is no alternate next transfer, a short 1425 * packet also makes the transfer done 1426 */ 1427 if (EHCI_QTD_GET_BYTES(status)) { 1428 if (xfer->flags_int.short_frames_ok) { 1429 /* follow alt next */ 1430 if (td->alt_next) { 1431 td = td->alt_next; 1432 continue; 1433 } 1434 } 1435 /* transfer is done */ 1436 break; 1437 } 1438 td = td->obj_next; 1439 } 1440 ehci_non_isoc_done(xfer); 1441 goto transferred; 1442 } 1443 1444done: 1445 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1446 return (0); 1447 1448transferred: 1449 return (1); 1450} 1451 1452static void 1453ehci_pcd_enable(ehci_softc_t *sc) 1454{ 1455 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1456 1457 sc->sc_eintrs |= EHCI_STS_PCD; 1458 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1459 1460 /* acknowledge any PCD interrupt */ 1461 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD); 1462 1463 ehci_root_intr(sc); 1464} 1465 1466static void 1467ehci_interrupt_poll(ehci_softc_t *sc) 1468{ 1469 struct usb_xfer *xfer; 1470 1471repeat: 1472 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1473 /* 1474 * check if transfer is transferred 1475 */ 1476 if (ehci_check_transfer(xfer)) { 1477 /* queue has been modified */ 1478 goto repeat; 1479 } 1480 } 1481} 1482 1483/* 1484 * Some EHCI chips from VIA / ATI seem to trigger interrupts before 1485 * writing back the qTD status, or miss signalling occasionally under 1486 * heavy load. If the host machine is too fast, we can miss 1487 * transaction completion - when we scan the active list the 1488 * transaction still seems to be active. This generally exhibits 1489 * itself as a umass stall that never recovers. 1490 * 1491 * We work around this behaviour by setting up this callback after any 1492 * softintr that completes with transactions still pending, giving us 1493 * another chance to check for completion after the writeback has 1494 * taken place. 1495 */ 1496static void 1497ehci_poll_timeout(void *arg) 1498{ 1499 ehci_softc_t *sc = arg; 1500 1501 DPRINTFN(3, "\n"); 1502 ehci_interrupt_poll(sc); 1503} 1504 1505/*------------------------------------------------------------------------* 1506 * ehci_interrupt - EHCI interrupt handler 1507 * 1508 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1509 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1510 * is present ! 1511 *------------------------------------------------------------------------*/ 1512void 1513ehci_interrupt(ehci_softc_t *sc) 1514{ 1515 uint32_t status; 1516 1517 USB_BUS_LOCK(&sc->sc_bus); 1518 1519 DPRINTFN(16, "real interrupt\n"); 1520 1521#if USB_DEBUG 1522 if (ehcidebug > 15) { 1523 ehci_dump_regs(sc); 1524 } 1525#endif 1526 1527 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1528 if (status == 0) { 1529 /* the interrupt was not for us */ 1530 goto done; 1531 } 1532 if (!(status & sc->sc_eintrs)) { 1533 goto done; 1534 } 1535 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */ 1536 1537 status &= sc->sc_eintrs; 1538 1539 if (status & EHCI_STS_HSE) { 1540 printf("%s: unrecoverable error, " 1541 "controller halted\n", __FUNCTION__); 1542#if USB_DEBUG 1543 ehci_dump_regs(sc); 1544 ehci_dump_isoc(sc); 1545#endif 1546 } 1547 if (status & EHCI_STS_PCD) { 1548 /* 1549 * Disable PCD interrupt for now, because it will be 1550 * on until the port has been reset. 1551 */ 1552 sc->sc_eintrs &= ~EHCI_STS_PCD; 1553 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1554 1555 ehci_root_intr(sc); 1556 1557 /* do not allow RHSC interrupts > 1 per second */ 1558 usb_callout_reset(&sc->sc_tmo_pcd, hz, 1559 (void *)&ehci_pcd_enable, sc); 1560 } 1561 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA); 1562 1563 if (status != 0) { 1564 /* block unprocessed interrupts */ 1565 sc->sc_eintrs &= ~status; 1566 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1567 printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status); 1568 } 1569 /* poll all the USB transfers */ 1570 ehci_interrupt_poll(sc); 1571 1572 if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) { 1573 usb_callout_reset(&sc->sc_tmo_poll, hz / 128, 1574 (void *)&ehci_poll_timeout, sc); 1575 } 1576 1577done: 1578 USB_BUS_UNLOCK(&sc->sc_bus); 1579} 1580 1581/* 1582 * called when a request does not complete 1583 */ 1584static void 1585ehci_timeout(void *arg) 1586{ 1587 struct usb_xfer *xfer = arg; 1588 1589 DPRINTF("xfer=%p\n", xfer); 1590 1591 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1592 1593 /* transfer is transferred */ 1594 ehci_device_done(xfer, USB_ERR_TIMEOUT); 1595} 1596 1597static void 1598ehci_do_poll(struct usb_bus *bus) 1599{ 1600 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1601 1602 USB_BUS_LOCK(&sc->sc_bus); 1603 ehci_interrupt_poll(sc); 1604 USB_BUS_UNLOCK(&sc->sc_bus); 1605} 1606 1607static void 1608ehci_setup_standard_chain_sub(struct ehci_std_temp *temp) 1609{ 1610 struct usb_page_search buf_res; 1611 ehci_qtd_t *td; 1612 ehci_qtd_t *td_next; 1613 ehci_qtd_t *td_alt_next; 1614 uint32_t buf_offset; 1615 uint32_t average; 1616 uint32_t len_old; 1617 uint32_t terminate; 1618 uint8_t shortpkt_old; 1619 uint8_t precompute; 1620 1621 terminate = htohc32(temp->sc, EHCI_LINK_TERMINATE); 1622 td_alt_next = NULL; 1623 buf_offset = 0; 1624 shortpkt_old = temp->shortpkt; 1625 len_old = temp->len; 1626 precompute = 1; 1627 1628restart: 1629 1630 td = temp->td; 1631 td_next = temp->td_next; 1632 1633 while (1) { 1634 1635 if (temp->len == 0) { 1636 1637 if (temp->shortpkt) { 1638 break; 1639 } 1640 /* send a Zero Length Packet, ZLP, last */ 1641 1642 temp->shortpkt = 1; 1643 average = 0; 1644 1645 } else { 1646 1647 average = temp->average; 1648 1649 if (temp->len < average) { 1650 if (temp->len % temp->max_frame_size) { 1651 temp->shortpkt = 1; 1652 } 1653 average = temp->len; 1654 } 1655 } 1656 1657 if (td_next == NULL) { 1658 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__); 1659 } 1660 /* get next TD */ 1661 1662 td = td_next; 1663 td_next = td->obj_next; 1664 1665 /* check if we are pre-computing */ 1666 1667 if (precompute) { 1668 1669 /* update remaining length */ 1670 1671 temp->len -= average; 1672 1673 continue; 1674 } 1675 /* fill out current TD */ 1676 1677 td->qtd_status = 1678 temp->qtd_status | 1679 htohc32(temp->sc, EHCI_QTD_IOC | 1680 EHCI_QTD_SET_BYTES(average)); 1681 1682 if (average == 0) { 1683 1684 if (temp->auto_data_toggle == 0) { 1685 1686 /* update data toggle, ZLP case */ 1687 1688 temp->qtd_status ^= 1689 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1690 } 1691 td->len = 0; 1692 1693 td->qtd_buffer[0] = 0; 1694 td->qtd_buffer_hi[0] = 0; 1695 1696 td->qtd_buffer[1] = 0; 1697 td->qtd_buffer_hi[1] = 0; 1698 1699 } else { 1700 1701 uint8_t x; 1702 1703 if (temp->auto_data_toggle == 0) { 1704 1705 /* update data toggle */ 1706 1707 if (((average + temp->max_frame_size - 1) / 1708 temp->max_frame_size) & 1) { 1709 temp->qtd_status ^= 1710 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1711 } 1712 } 1713 td->len = average; 1714 1715 /* update remaining length */ 1716 1717 temp->len -= average; 1718 1719 /* fill out buffer pointers */ 1720 1721 usbd_get_page(temp->pc, buf_offset, &buf_res); 1722 td->qtd_buffer[0] = 1723 htohc32(temp->sc, buf_res.physaddr); 1724 td->qtd_buffer_hi[0] = 0; 1725 1726 x = 1; 1727 1728 while (average > EHCI_PAGE_SIZE) { 1729 average -= EHCI_PAGE_SIZE; 1730 buf_offset += EHCI_PAGE_SIZE; 1731 usbd_get_page(temp->pc, buf_offset, &buf_res); 1732 td->qtd_buffer[x] = 1733 htohc32(temp->sc, 1734 buf_res.physaddr & (~0xFFF)); 1735 td->qtd_buffer_hi[x] = 0; 1736 x++; 1737 } 1738 1739 /* 1740 * NOTE: The "average" variable is never zero after 1741 * exiting the loop above ! 1742 * 1743 * NOTE: We have to subtract one from the offset to 1744 * ensure that we are computing the physical address 1745 * of a valid page ! 1746 */ 1747 buf_offset += average; 1748 usbd_get_page(temp->pc, buf_offset - 1, &buf_res); 1749 td->qtd_buffer[x] = 1750 htohc32(temp->sc, 1751 buf_res.physaddr & (~0xFFF)); 1752 td->qtd_buffer_hi[x] = 0; 1753 } 1754 1755 if (temp->can_use_next) { 1756 if (td_next) { 1757 /* link the current TD with the next one */ 1758 td->qtd_next = td_next->qtd_self; 1759 } 1760 } else { 1761 /* 1762 * BUG WARNING: The EHCI HW can use the 1763 * qtd_next field instead of qtd_altnext when 1764 * a short packet is received! We work this 1765 * around in software by not queueing more 1766 * than one job/TD at a time! 1767 */ 1768 td->qtd_next = terminate; 1769 } 1770 1771 td->qtd_altnext = terminate; 1772 td->alt_next = td_alt_next; 1773 1774 usb_pc_cpu_flush(td->page_cache); 1775 } 1776 1777 if (precompute) { 1778 precompute = 0; 1779 1780 /* setup alt next pointer, if any */ 1781 if (temp->last_frame) { 1782 td_alt_next = NULL; 1783 } else { 1784 /* we use this field internally */ 1785 td_alt_next = td_next; 1786 } 1787 1788 /* restore */ 1789 temp->shortpkt = shortpkt_old; 1790 temp->len = len_old; 1791 goto restart; 1792 } 1793 temp->td = td; 1794 temp->td_next = td_next; 1795} 1796 1797static void 1798ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last) 1799{ 1800 struct ehci_std_temp temp; 1801 struct usb_pipe_methods *methods; 1802 ehci_qh_t *qh; 1803 ehci_qtd_t *td; 1804 uint32_t qh_endp; 1805 uint32_t qh_endphub; 1806 uint32_t x; 1807 1808 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1809 xfer->address, UE_GET_ADDR(xfer->endpointno), 1810 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1811 1812 temp.average = xfer->max_hc_frame_size; 1813 temp.max_frame_size = xfer->max_frame_size; 1814 temp.sc = EHCI_BUS2SC(xfer->xroot->bus); 1815 1816 /* toggle the DMA set we are using */ 1817 xfer->flags_int.curr_dma_set ^= 1; 1818 1819 /* get next DMA set */ 1820 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1821 1822 xfer->td_transfer_first = td; 1823 xfer->td_transfer_cache = td; 1824 1825 temp.td = NULL; 1826 temp.td_next = td; 1827 temp.qtd_status = 0; 1828 temp.last_frame = 0; 1829 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1830 temp.can_use_next = (xfer->flags_int.control_xfr || 1831 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT)); 1832 1833 if (xfer->flags_int.control_xfr) { 1834 if (xfer->endpoint->toggle_next) { 1835 /* DATA1 is next */ 1836 temp.qtd_status |= 1837 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1838 } 1839 temp.auto_data_toggle = 0; 1840 } else { 1841 temp.auto_data_toggle = 1; 1842 } 1843 1844 if (usbd_get_speed(xfer->xroot->udev) != USB_SPEED_HIGH) { 1845 /* max 3 retries */ 1846 temp.qtd_status |= 1847 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1848 } 1849 /* check if we should prepend a setup message */ 1850 1851 if (xfer->flags_int.control_xfr) { 1852 if (xfer->flags_int.control_hdr) { 1853 1854 temp.qtd_status &= 1855 htohc32(temp.sc, EHCI_QTD_SET_CERR(3)); 1856 temp.qtd_status |= htohc32(temp.sc, 1857 EHCI_QTD_ACTIVE | 1858 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 1859 EHCI_QTD_SET_TOGGLE(0)); 1860 1861 temp.len = xfer->frlengths[0]; 1862 temp.pc = xfer->frbuffers + 0; 1863 temp.shortpkt = temp.len ? 1 : 0; 1864 /* check for last frame */ 1865 if (xfer->nframes == 1) { 1866 /* no STATUS stage yet, SETUP is last */ 1867 if (xfer->flags_int.control_act) { 1868 temp.last_frame = 1; 1869 temp.setup_alt_next = 0; 1870 } 1871 } 1872 ehci_setup_standard_chain_sub(&temp); 1873 } 1874 x = 1; 1875 } else { 1876 x = 0; 1877 } 1878 1879 while (x != xfer->nframes) { 1880 1881 /* DATA0 / DATA1 message */ 1882 1883 temp.len = xfer->frlengths[x]; 1884 temp.pc = xfer->frbuffers + x; 1885 1886 x++; 1887 1888 if (x == xfer->nframes) { 1889 if (xfer->flags_int.control_xfr) { 1890 /* no STATUS stage yet, DATA is last */ 1891 if (xfer->flags_int.control_act) { 1892 temp.last_frame = 1; 1893 temp.setup_alt_next = 0; 1894 } 1895 } else { 1896 temp.last_frame = 1; 1897 temp.setup_alt_next = 0; 1898 } 1899 } 1900 /* keep previous data toggle and error count */ 1901 1902 temp.qtd_status &= 1903 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1904 EHCI_QTD_SET_TOGGLE(1)); 1905 1906 if (temp.len == 0) { 1907 1908 /* make sure that we send an USB packet */ 1909 1910 temp.shortpkt = 0; 1911 1912 } else { 1913 1914 /* regular data transfer */ 1915 1916 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1917 } 1918 1919 /* set endpoint direction */ 1920 1921 temp.qtd_status |= 1922 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ? 1923 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1924 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) : 1925 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1926 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT)); 1927 1928 ehci_setup_standard_chain_sub(&temp); 1929 } 1930 1931 /* check if we should append a status stage */ 1932 1933 if (xfer->flags_int.control_xfr && 1934 !xfer->flags_int.control_act) { 1935 1936 /* 1937 * Send a DATA1 message and invert the current endpoint 1938 * direction. 1939 */ 1940 1941 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) | 1942 EHCI_QTD_SET_TOGGLE(1)); 1943 temp.qtd_status |= 1944 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ? 1945 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1946 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) | 1947 EHCI_QTD_SET_TOGGLE(1)) : 1948 htohc32(temp.sc, EHCI_QTD_ACTIVE | 1949 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) | 1950 EHCI_QTD_SET_TOGGLE(1)); 1951 1952 temp.len = 0; 1953 temp.pc = NULL; 1954 temp.shortpkt = 0; 1955 temp.last_frame = 1; 1956 temp.setup_alt_next = 0; 1957 1958 ehci_setup_standard_chain_sub(&temp); 1959 } 1960 td = temp.td; 1961 1962 /* the last TD terminates the transfer: */ 1963 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1964 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE); 1965 1966 usb_pc_cpu_flush(td->page_cache); 1967 1968 /* must have at least one frame! */ 1969 1970 xfer->td_transfer_last = td; 1971 1972#if USB_DEBUG 1973 if (ehcidebug > 8) { 1974 DPRINTF("nexttog=%d; data before transfer:\n", 1975 xfer->endpoint->toggle_next); 1976 ehci_dump_sqtds(temp.sc, 1977 xfer->td_transfer_first); 1978 } 1979#endif 1980 1981 methods = xfer->endpoint->methods; 1982 1983 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1984 1985 /* the "qh_link" field is filled when the QH is added */ 1986 1987 qh_endp = 1988 (EHCI_QH_SET_ADDR(xfer->address) | 1989 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 1990 EHCI_QH_SET_MPL(xfer->max_packet_size)); 1991 1992 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 1993 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH); 1994 if (methods != &ehci_device_intr_methods) 1995 qh_endp |= EHCI_QH_SET_NRL(8); 1996 } else { 1997 1998 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) { 1999 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL); 2000 } else { 2001 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW); 2002 } 2003 2004 if (methods == &ehci_device_ctrl_methods) { 2005 qh_endp |= EHCI_QH_CTL; 2006 } 2007 if (methods != &ehci_device_intr_methods) { 2008 /* Only try one time per microframe! */ 2009 qh_endp |= EHCI_QH_SET_NRL(1); 2010 } 2011 } 2012 2013 if (temp.auto_data_toggle == 0) { 2014 /* software computes the data toggle */ 2015 qh_endp |= EHCI_QH_DTC; 2016 } 2017 2018 qh->qh_endp = htohc32(temp.sc, qh_endp); 2019 2020 qh_endphub = 2021 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) | 2022 EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) | 2023 EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) | 2024 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 2025 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no)); 2026 2027 qh->qh_endphub = htohc32(temp.sc, qh_endphub); 2028 qh->qh_curqtd = 0; 2029 2030 /* fill the overlay qTD */ 2031 2032 if (temp.auto_data_toggle && xfer->endpoint->toggle_next) { 2033 /* DATA1 is next */ 2034 qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 2035 } else { 2036 qh->qh_qtd.qtd_status = 0; 2037 } 2038 2039 td = xfer->td_transfer_first; 2040 2041 qh->qh_qtd.qtd_next = td->qtd_self; 2042 qh->qh_qtd.qtd_altnext = 2043 htohc32(temp.sc, EHCI_LINK_TERMINATE); 2044 2045 usb_pc_cpu_flush(qh->page_cache); 2046 2047 if (xfer->xroot->udev->flags.self_suspended == 0) { 2048 EHCI_APPEND_QH(qh, *qh_last); 2049 } 2050} 2051 2052static void 2053ehci_root_intr(ehci_softc_t *sc) 2054{ 2055 uint16_t i; 2056 uint16_t m; 2057 2058 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2059 2060 /* clear any old interrupt data */ 2061 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2062 2063 /* set bits */ 2064 m = (sc->sc_noport + 1); 2065 if (m > (8 * sizeof(sc->sc_hub_idata))) { 2066 m = (8 * sizeof(sc->sc_hub_idata)); 2067 } 2068 for (i = 1; i < m; i++) { 2069 /* pick out CHANGE bits from the status register */ 2070 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) { 2071 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2072 DPRINTF("port %d changed\n", i); 2073 } 2074 } 2075 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2076 sizeof(sc->sc_hub_idata)); 2077} 2078 2079static void 2080ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2081{ 2082 uint32_t nframes = xfer->nframes; 2083 uint32_t status; 2084 uint32_t *plen = xfer->frlengths; 2085 uint16_t len = 0; 2086 ehci_sitd_t *td = xfer->td_transfer_first; 2087 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos]; 2088 2089 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2090 xfer, xfer->endpoint); 2091 2092 while (nframes--) { 2093 if (td == NULL) { 2094 panic("%s:%d: out of TD's\n", 2095 __FUNCTION__, __LINE__); 2096 } 2097 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2098 pp_last = &sc->sc_isoc_fs_p_last[0]; 2099 } 2100#if USB_DEBUG 2101 if (ehcidebug > 15) { 2102 DPRINTF("isoc FS-TD\n"); 2103 ehci_dump_sitd(sc, td); 2104 } 2105#endif 2106 usb_pc_cpu_invalidate(td->page_cache); 2107 status = hc32toh(sc, td->sitd_status); 2108 2109 len = EHCI_SITD_GET_LEN(status); 2110 2111 DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len); 2112 2113 if (*plen >= len) { 2114 len = *plen - len; 2115 } else { 2116 len = 0; 2117 } 2118 2119 *plen = len; 2120 2121 /* remove FS-TD from schedule */ 2122 EHCI_REMOVE_FS_TD(td, *pp_last); 2123 2124 pp_last++; 2125 plen++; 2126 td = td->obj_next; 2127 } 2128 2129 xfer->aframes = xfer->nframes; 2130} 2131 2132static void 2133ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer) 2134{ 2135 uint32_t nframes = xfer->nframes; 2136 uint32_t status; 2137 uint32_t *plen = xfer->frlengths; 2138 uint16_t len = 0; 2139 uint8_t td_no = 0; 2140 ehci_itd_t *td = xfer->td_transfer_first; 2141 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos]; 2142 2143 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 2144 xfer, xfer->endpoint); 2145 2146 while (nframes) { 2147 if (td == NULL) { 2148 panic("%s:%d: out of TD's\n", 2149 __FUNCTION__, __LINE__); 2150 } 2151 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2152 pp_last = &sc->sc_isoc_hs_p_last[0]; 2153 } 2154#if USB_DEBUG 2155 if (ehcidebug > 15) { 2156 DPRINTF("isoc HS-TD\n"); 2157 ehci_dump_itd(sc, td); 2158 } 2159#endif 2160 2161 usb_pc_cpu_invalidate(td->page_cache); 2162 status = hc32toh(sc, td->itd_status[td_no]); 2163 2164 len = EHCI_ITD_GET_LEN(status); 2165 2166 DPRINTFN(2, "status=0x%08x, len=%u\n", status, len); 2167 2168 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2169 2170 if (*plen >= len) { 2171 /* 2172 * The length is valid. NOTE: The 2173 * complete length is written back 2174 * into the status field, and not the 2175 * remainder like with other transfer 2176 * descriptor types. 2177 */ 2178 } else { 2179 /* Invalid length - truncate */ 2180 len = 0; 2181 } 2182 2183 *plen = len; 2184 plen++; 2185 nframes--; 2186 } 2187 2188 td_no++; 2189 2190 if ((td_no == 8) || (nframes == 0)) { 2191 /* remove HS-TD from schedule */ 2192 EHCI_REMOVE_HS_TD(td, *pp_last); 2193 pp_last++; 2194 2195 td_no = 0; 2196 td = td->obj_next; 2197 } 2198 } 2199 xfer->aframes = xfer->nframes; 2200} 2201 2202/* NOTE: "done" can be run two times in a row, 2203 * from close and from interrupt 2204 */ 2205static void 2206ehci_device_done(struct usb_xfer *xfer, usb_error_t error) 2207{ 2208 struct usb_pipe_methods *methods = xfer->endpoint->methods; 2209 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2210 2211 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2212 2213 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2214 xfer, xfer->endpoint, error); 2215 2216 if ((methods == &ehci_device_bulk_methods) || 2217 (methods == &ehci_device_ctrl_methods)) { 2218#if USB_DEBUG 2219 if (ehcidebug > 8) { 2220 DPRINTF("nexttog=%d; data after transfer:\n", 2221 xfer->endpoint->toggle_next); 2222 ehci_dump_sqtds(sc, 2223 xfer->td_transfer_first); 2224 } 2225#endif 2226 2227 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2228 sc->sc_async_p_last); 2229 } 2230 if (methods == &ehci_device_intr_methods) { 2231 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2232 sc->sc_intr_p_last[xfer->qh_pos]); 2233 } 2234 /* 2235 * Only finish isochronous transfers once which will update 2236 * "xfer->frlengths". 2237 */ 2238 if (xfer->td_transfer_first && 2239 xfer->td_transfer_last) { 2240 if (methods == &ehci_device_isoc_fs_methods) { 2241 ehci_isoc_fs_done(sc, xfer); 2242 } 2243 if (methods == &ehci_device_isoc_hs_methods) { 2244 ehci_isoc_hs_done(sc, xfer); 2245 } 2246 xfer->td_transfer_first = NULL; 2247 xfer->td_transfer_last = NULL; 2248 } 2249 /* dequeue transfer and start next transfer */ 2250 usbd_transfer_done(xfer, error); 2251} 2252 2253/*------------------------------------------------------------------------* 2254 * ehci bulk support 2255 *------------------------------------------------------------------------*/ 2256static void 2257ehci_device_bulk_open(struct usb_xfer *xfer) 2258{ 2259 return; 2260} 2261 2262static void 2263ehci_device_bulk_close(struct usb_xfer *xfer) 2264{ 2265 ehci_device_done(xfer, USB_ERR_CANCELLED); 2266} 2267 2268static void 2269ehci_device_bulk_enter(struct usb_xfer *xfer) 2270{ 2271 return; 2272} 2273 2274static void 2275ehci_device_bulk_start(struct usb_xfer *xfer) 2276{ 2277 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2278 uint32_t temp; 2279 2280 /* setup TD's and QH */ 2281 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2282 2283 /* put transfer on interrupt queue */ 2284 ehci_transfer_intr_enqueue(xfer); 2285 2286 /* XXX Performance quirk: Some Host Controllers have a too low 2287 * interrupt rate. Issue an IAAD to stimulate the Host 2288 * Controller after queueing the BULK transfer. 2289 */ 2290 temp = EOREAD4(sc, EHCI_USBCMD); 2291 if (!(temp & EHCI_CMD_IAAD)) 2292 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD); 2293} 2294 2295struct usb_pipe_methods ehci_device_bulk_methods = 2296{ 2297 .open = ehci_device_bulk_open, 2298 .close = ehci_device_bulk_close, 2299 .enter = ehci_device_bulk_enter, 2300 .start = ehci_device_bulk_start, 2301}; 2302 2303/*------------------------------------------------------------------------* 2304 * ehci control support 2305 *------------------------------------------------------------------------*/ 2306static void 2307ehci_device_ctrl_open(struct usb_xfer *xfer) 2308{ 2309 return; 2310} 2311 2312static void 2313ehci_device_ctrl_close(struct usb_xfer *xfer) 2314{ 2315 ehci_device_done(xfer, USB_ERR_CANCELLED); 2316} 2317 2318static void 2319ehci_device_ctrl_enter(struct usb_xfer *xfer) 2320{ 2321 return; 2322} 2323 2324static void 2325ehci_device_ctrl_start(struct usb_xfer *xfer) 2326{ 2327 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2328 2329 /* setup TD's and QH */ 2330 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2331 2332 /* put transfer on interrupt queue */ 2333 ehci_transfer_intr_enqueue(xfer); 2334} 2335 2336struct usb_pipe_methods ehci_device_ctrl_methods = 2337{ 2338 .open = ehci_device_ctrl_open, 2339 .close = ehci_device_ctrl_close, 2340 .enter = ehci_device_ctrl_enter, 2341 .start = ehci_device_ctrl_start, 2342}; 2343 2344/*------------------------------------------------------------------------* 2345 * ehci interrupt support 2346 *------------------------------------------------------------------------*/ 2347static void 2348ehci_device_intr_open(struct usb_xfer *xfer) 2349{ 2350 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2351 uint16_t best; 2352 uint16_t bit; 2353 uint16_t x; 2354 2355 usb_hs_bandwidth_alloc(xfer); 2356 2357 /* 2358 * Find the best QH position corresponding to the given interval: 2359 */ 2360 2361 best = 0; 2362 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 2363 while (bit) { 2364 if (xfer->interval >= bit) { 2365 x = bit; 2366 best = bit; 2367 while (x & bit) { 2368 if (sc->sc_intr_stat[x] < 2369 sc->sc_intr_stat[best]) { 2370 best = x; 2371 } 2372 x++; 2373 } 2374 break; 2375 } 2376 bit >>= 1; 2377 } 2378 2379 sc->sc_intr_stat[best]++; 2380 xfer->qh_pos = best; 2381 2382 DPRINTFN(3, "best=%d interval=%d\n", 2383 best, xfer->interval); 2384} 2385 2386static void 2387ehci_device_intr_close(struct usb_xfer *xfer) 2388{ 2389 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2390 2391 sc->sc_intr_stat[xfer->qh_pos]--; 2392 2393 ehci_device_done(xfer, USB_ERR_CANCELLED); 2394 2395 /* bandwidth must be freed after device done */ 2396 usb_hs_bandwidth_free(xfer); 2397} 2398 2399static void 2400ehci_device_intr_enter(struct usb_xfer *xfer) 2401{ 2402 return; 2403} 2404 2405static void 2406ehci_device_intr_start(struct usb_xfer *xfer) 2407{ 2408 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2409 2410 /* setup TD's and QH */ 2411 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 2412 2413 /* put transfer on interrupt queue */ 2414 ehci_transfer_intr_enqueue(xfer); 2415} 2416 2417struct usb_pipe_methods ehci_device_intr_methods = 2418{ 2419 .open = ehci_device_intr_open, 2420 .close = ehci_device_intr_close, 2421 .enter = ehci_device_intr_enter, 2422 .start = ehci_device_intr_start, 2423}; 2424 2425/*------------------------------------------------------------------------* 2426 * ehci full speed isochronous support 2427 *------------------------------------------------------------------------*/ 2428static void 2429ehci_device_isoc_fs_open(struct usb_xfer *xfer) 2430{ 2431 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2432 ehci_sitd_t *td; 2433 uint32_t sitd_portaddr; 2434 uint8_t ds; 2435 2436 sitd_portaddr = 2437 EHCI_SITD_SET_ADDR(xfer->address) | 2438 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) | 2439 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 2440 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no); 2441 2442 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 2443 sitd_portaddr |= EHCI_SITD_SET_DIR_IN; 2444 } 2445 sitd_portaddr = htohc32(sc, sitd_portaddr); 2446 2447 /* initialize all TD's */ 2448 2449 for (ds = 0; ds != 2; ds++) { 2450 2451 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2452 2453 td->sitd_portaddr = sitd_portaddr; 2454 2455 /* 2456 * TODO: make some kind of automatic 2457 * SMASK/CMASK selection based on micro-frame 2458 * usage 2459 * 2460 * micro-frame usage (8 microframes per 1ms) 2461 */ 2462 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE); 2463 2464 usb_pc_cpu_flush(td->page_cache); 2465 } 2466 } 2467} 2468 2469static void 2470ehci_device_isoc_fs_close(struct usb_xfer *xfer) 2471{ 2472 ehci_device_done(xfer, USB_ERR_CANCELLED); 2473} 2474 2475static void 2476ehci_device_isoc_fs_enter(struct usb_xfer *xfer) 2477{ 2478 struct usb_page_search buf_res; 2479 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2480 struct usb_fs_isoc_schedule *fss_start; 2481 struct usb_fs_isoc_schedule *fss_end; 2482 struct usb_fs_isoc_schedule *fss; 2483 ehci_sitd_t *td; 2484 ehci_sitd_t *td_last = NULL; 2485 ehci_sitd_t **pp_last; 2486 uint32_t *plen; 2487 uint32_t buf_offset; 2488 uint32_t nframes; 2489 uint32_t temp; 2490 uint32_t sitd_mask; 2491 uint16_t tlen; 2492 uint8_t sa; 2493 uint8_t sb; 2494 uint8_t error; 2495 2496#if USB_DEBUG 2497 uint8_t once = 1; 2498 2499#endif 2500 2501 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2502 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2503 2504 /* get the current frame index */ 2505 2506 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2507 2508 /* 2509 * check if the frame index is within the window where the frames 2510 * will be inserted 2511 */ 2512 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2513 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2514 2515 if ((xfer->endpoint->is_synced == 0) || 2516 (buf_offset < xfer->nframes)) { 2517 /* 2518 * If there is data underflow or the pipe queue is empty we 2519 * schedule the transfer a few frames ahead of the current 2520 * frame position. Else two isochronous transfers might 2521 * overlap. 2522 */ 2523 xfer->endpoint->isoc_next = (nframes + 3) & 2524 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2525 xfer->endpoint->is_synced = 1; 2526 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2527 } 2528 /* 2529 * compute how many milliseconds the insertion is ahead of the 2530 * current frame position: 2531 */ 2532 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2533 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2534 2535 /* 2536 * pre-compute when the isochronous transfer will be finished: 2537 */ 2538 xfer->isoc_time_complete = 2539 usbd_fs_isoc_schedule_isoc_time_expand 2540 (xfer->xroot->udev, &fss_start, &fss_end, nframes) + buf_offset + 2541 xfer->nframes; 2542 2543 /* get the real number of frames */ 2544 2545 nframes = xfer->nframes; 2546 2547 buf_offset = 0; 2548 2549 plen = xfer->frlengths; 2550 2551 /* toggle the DMA set we are using */ 2552 xfer->flags_int.curr_dma_set ^= 1; 2553 2554 /* get next DMA set */ 2555 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2556 xfer->td_transfer_first = td; 2557 2558 pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next]; 2559 2560 /* store starting position */ 2561 2562 xfer->qh_pos = xfer->endpoint->isoc_next; 2563 2564 fss = fss_start + (xfer->qh_pos % USB_ISOC_TIME_MAX); 2565 2566 while (nframes--) { 2567 if (td == NULL) { 2568 panic("%s:%d: out of TD's\n", 2569 __FUNCTION__, __LINE__); 2570 } 2571 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2572 pp_last = &sc->sc_isoc_fs_p_last[0]; 2573 } 2574 if (fss >= fss_end) { 2575 fss = fss_start; 2576 } 2577 /* reuse sitd_portaddr and sitd_back from last transfer */ 2578 2579 if (*plen > xfer->max_frame_size) { 2580#if USB_DEBUG 2581 if (once) { 2582 once = 0; 2583 printf("%s: frame length(%d) exceeds %d " 2584 "bytes (frame truncated)\n", 2585 __FUNCTION__, *plen, 2586 xfer->max_frame_size); 2587 } 2588#endif 2589 *plen = xfer->max_frame_size; 2590 } 2591 /* 2592 * We currently don't care if the ISOCHRONOUS schedule is 2593 * full! 2594 */ 2595 error = usbd_fs_isoc_schedule_alloc(fss, &sa, *plen); 2596 if (error) { 2597 /* 2598 * The FULL speed schedule is FULL! Set length 2599 * to zero. 2600 */ 2601 *plen = 0; 2602 } 2603 if (*plen) { 2604 /* 2605 * only call "usbd_get_page()" when we have a 2606 * non-zero length 2607 */ 2608 usbd_get_page(xfer->frbuffers, buf_offset, &buf_res); 2609 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr); 2610 buf_offset += *plen; 2611 /* 2612 * NOTE: We need to subtract one from the offset so 2613 * that we are on a valid page! 2614 */ 2615 usbd_get_page(xfer->frbuffers, buf_offset - 1, 2616 &buf_res); 2617 temp = buf_res.physaddr & ~0xFFF; 2618 } else { 2619 td->sitd_bp[0] = 0; 2620 temp = 0; 2621 } 2622 2623 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) { 2624 tlen = *plen; 2625 if (tlen <= 188) { 2626 temp |= 1; /* T-count = 1, TP = ALL */ 2627 tlen = 1; 2628 } else { 2629 tlen += 187; 2630 tlen /= 188; 2631 temp |= tlen; /* T-count = [1..6] */ 2632 temp |= 8; /* TP = Begin */ 2633 } 2634 2635 tlen += sa; 2636 2637 if (tlen >= 8) { 2638 sb = 0; 2639 } else { 2640 sb = (1 << tlen); 2641 } 2642 2643 sa = (1 << sa); 2644 sa = (sb - sa) & 0x3F; 2645 sb = 0; 2646 } else { 2647 sb = (-(4 << sa)) & 0xFE; 2648 sa = (1 << sa) & 0x3F; 2649 } 2650 2651 sitd_mask = (EHCI_SITD_SET_SMASK(sa) | 2652 EHCI_SITD_SET_CMASK(sb)); 2653 2654 td->sitd_bp[1] = htohc32(sc, temp); 2655 2656 td->sitd_mask = htohc32(sc, sitd_mask); 2657 2658 if (nframes == 0) { 2659 td->sitd_status = htohc32(sc, 2660 EHCI_SITD_IOC | 2661 EHCI_SITD_ACTIVE | 2662 EHCI_SITD_SET_LEN(*plen)); 2663 } else { 2664 td->sitd_status = htohc32(sc, 2665 EHCI_SITD_ACTIVE | 2666 EHCI_SITD_SET_LEN(*plen)); 2667 } 2668 usb_pc_cpu_flush(td->page_cache); 2669 2670#if USB_DEBUG 2671 if (ehcidebug > 15) { 2672 DPRINTF("FS-TD %d\n", nframes); 2673 ehci_dump_sitd(sc, td); 2674 } 2675#endif 2676 /* insert TD into schedule */ 2677 EHCI_APPEND_FS_TD(td, *pp_last); 2678 pp_last++; 2679 2680 plen++; 2681 fss++; 2682 td_last = td; 2683 td = td->obj_next; 2684 } 2685 2686 xfer->td_transfer_last = td_last; 2687 2688 /* update isoc_next */ 2689 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) & 2690 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2691} 2692 2693static void 2694ehci_device_isoc_fs_start(struct usb_xfer *xfer) 2695{ 2696 /* put transfer on interrupt queue */ 2697 ehci_transfer_intr_enqueue(xfer); 2698} 2699 2700struct usb_pipe_methods ehci_device_isoc_fs_methods = 2701{ 2702 .open = ehci_device_isoc_fs_open, 2703 .close = ehci_device_isoc_fs_close, 2704 .enter = ehci_device_isoc_fs_enter, 2705 .start = ehci_device_isoc_fs_start, 2706}; 2707 2708/*------------------------------------------------------------------------* 2709 * ehci high speed isochronous support 2710 *------------------------------------------------------------------------*/ 2711static void 2712ehci_device_isoc_hs_open(struct usb_xfer *xfer) 2713{ 2714 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2715 ehci_itd_t *td; 2716 uint32_t temp; 2717 uint8_t ds; 2718 2719 usb_hs_bandwidth_alloc(xfer); 2720 2721 /* initialize all TD's */ 2722 2723 for (ds = 0; ds != 2; ds++) { 2724 2725 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2726 2727 /* set TD inactive */ 2728 td->itd_status[0] = 0; 2729 td->itd_status[1] = 0; 2730 td->itd_status[2] = 0; 2731 td->itd_status[3] = 0; 2732 td->itd_status[4] = 0; 2733 td->itd_status[5] = 0; 2734 td->itd_status[6] = 0; 2735 td->itd_status[7] = 0; 2736 2737 /* set endpoint and address */ 2738 td->itd_bp[0] = htohc32(sc, 2739 EHCI_ITD_SET_ADDR(xfer->address) | 2740 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno))); 2741 2742 temp = 2743 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF); 2744 2745 /* set direction */ 2746 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) { 2747 temp |= EHCI_ITD_SET_DIR_IN; 2748 } 2749 /* set maximum packet size */ 2750 td->itd_bp[1] = htohc32(sc, temp); 2751 2752 /* set transfer multiplier */ 2753 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3); 2754 2755 usb_pc_cpu_flush(td->page_cache); 2756 } 2757 } 2758} 2759 2760static void 2761ehci_device_isoc_hs_close(struct usb_xfer *xfer) 2762{ 2763 ehci_device_done(xfer, USB_ERR_CANCELLED); 2764 2765 /* bandwidth must be freed after device done */ 2766 usb_hs_bandwidth_free(xfer); 2767} 2768 2769static void 2770ehci_device_isoc_hs_enter(struct usb_xfer *xfer) 2771{ 2772 struct usb_page_search buf_res; 2773 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2774 ehci_itd_t *td; 2775 ehci_itd_t *td_last = NULL; 2776 ehci_itd_t **pp_last; 2777 bus_size_t page_addr; 2778 uint32_t *plen; 2779 uint32_t status; 2780 uint32_t buf_offset; 2781 uint32_t nframes; 2782 uint32_t itd_offset[8 + 1]; 2783 uint8_t x; 2784 uint8_t td_no; 2785 uint8_t page_no; 2786 2787#if USB_DEBUG 2788 uint8_t once = 1; 2789 2790#endif 2791 2792 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2793 xfer, xfer->endpoint->isoc_next, xfer->nframes); 2794 2795 /* get the current frame index */ 2796 2797 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2798 2799 /* 2800 * check if the frame index is within the window where the frames 2801 * will be inserted 2802 */ 2803 buf_offset = (nframes - xfer->endpoint->isoc_next) & 2804 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2805 2806 if ((xfer->endpoint->is_synced == 0) || 2807 (buf_offset < ((xfer->nframes + 7) / 8))) { 2808 /* 2809 * If there is data underflow or the pipe queue is empty we 2810 * schedule the transfer a few frames ahead of the current 2811 * frame position. Else two isochronous transfers might 2812 * overlap. 2813 */ 2814 xfer->endpoint->isoc_next = (nframes + 3) & 2815 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2816 xfer->endpoint->is_synced = 1; 2817 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2818 } 2819 /* 2820 * compute how many milliseconds the insertion is ahead of the 2821 * current frame position: 2822 */ 2823 buf_offset = (xfer->endpoint->isoc_next - nframes) & 2824 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2825 2826 /* 2827 * pre-compute when the isochronous transfer will be finished: 2828 */ 2829 xfer->isoc_time_complete = 2830 usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 2831 ((xfer->nframes + 7) / 8); 2832 2833 /* get the real number of frames */ 2834 2835 nframes = xfer->nframes; 2836 2837 buf_offset = 0; 2838 td_no = 0; 2839 2840 plen = xfer->frlengths; 2841 2842 /* toggle the DMA set we are using */ 2843 xfer->flags_int.curr_dma_set ^= 1; 2844 2845 /* get next DMA set */ 2846 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2847 xfer->td_transfer_first = td; 2848 2849 pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next]; 2850 2851 /* store starting position */ 2852 2853 xfer->qh_pos = xfer->endpoint->isoc_next; 2854 2855 while (nframes) { 2856 if (td == NULL) { 2857 panic("%s:%d: out of TD's\n", 2858 __FUNCTION__, __LINE__); 2859 } 2860 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2861 pp_last = &sc->sc_isoc_hs_p_last[0]; 2862 } 2863 /* range check */ 2864 if (*plen > xfer->max_frame_size) { 2865#if USB_DEBUG 2866 if (once) { 2867 once = 0; 2868 printf("%s: frame length(%d) exceeds %d bytes " 2869 "(frame truncated)\n", 2870 __FUNCTION__, *plen, xfer->max_frame_size); 2871 } 2872#endif 2873 *plen = xfer->max_frame_size; 2874 } 2875 2876 if (xfer->endpoint->usb_smask & (1 << td_no)) { 2877 status = (EHCI_ITD_SET_LEN(*plen) | 2878 EHCI_ITD_ACTIVE | 2879 EHCI_ITD_SET_PG(0)); 2880 td->itd_status[td_no] = htohc32(sc, status); 2881 itd_offset[td_no] = buf_offset; 2882 buf_offset += *plen; 2883 plen++; 2884 nframes --; 2885 } else { 2886 td->itd_status[td_no] = 0; /* not active */ 2887 itd_offset[td_no] = buf_offset; 2888 } 2889 2890 td_no++; 2891 2892 if ((td_no == 8) || (nframes == 0)) { 2893 2894 /* the rest of the transfers are not active, if any */ 2895 for (x = td_no; x != 8; x++) { 2896 td->itd_status[x] = 0; /* not active */ 2897 } 2898 2899 /* check if there is any data to be transferred */ 2900 if (itd_offset[0] != buf_offset) { 2901 page_no = 0; 2902 itd_offset[td_no] = buf_offset; 2903 2904 /* get first page offset */ 2905 usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res); 2906 /* get page address */ 2907 page_addr = buf_res.physaddr & ~0xFFF; 2908 /* update page address */ 2909 td->itd_bp[0] &= htohc32(sc, 0xFFF); 2910 td->itd_bp[0] |= htohc32(sc, page_addr); 2911 2912 for (x = 0; x != td_no; x++) { 2913 /* set page number and page offset */ 2914 status = (EHCI_ITD_SET_PG(page_no) | 2915 (buf_res.physaddr & 0xFFF)); 2916 td->itd_status[x] |= htohc32(sc, status); 2917 2918 /* get next page offset */ 2919 if (itd_offset[x + 1] == buf_offset) { 2920 /* 2921 * We subtract one so that 2922 * we don't go off the last 2923 * page! 2924 */ 2925 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 2926 } else { 2927 usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res); 2928 } 2929 2930 /* check if we need a new page */ 2931 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) { 2932 /* new page needed */ 2933 page_addr = buf_res.physaddr & ~0xFFF; 2934 if (page_no == 6) { 2935 panic("%s: too many pages\n", __FUNCTION__); 2936 } 2937 page_no++; 2938 /* update page address */ 2939 td->itd_bp[page_no] &= htohc32(sc, 0xFFF); 2940 td->itd_bp[page_no] |= htohc32(sc, page_addr); 2941 } 2942 } 2943 } 2944 /* set IOC bit if we are complete */ 2945 if (nframes == 0) { 2946 td->itd_status[td_no - 1] |= htohc32(sc, EHCI_ITD_IOC); 2947 } 2948 usb_pc_cpu_flush(td->page_cache); 2949#if USB_DEBUG 2950 if (ehcidebug > 15) { 2951 DPRINTF("HS-TD %d\n", nframes); 2952 ehci_dump_itd(sc, td); 2953 } 2954#endif 2955 /* insert TD into schedule */ 2956 EHCI_APPEND_HS_TD(td, *pp_last); 2957 pp_last++; 2958 2959 td_no = 0; 2960 td_last = td; 2961 td = td->obj_next; 2962 } 2963 } 2964 2965 xfer->td_transfer_last = td_last; 2966 2967 /* update isoc_next */ 2968 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) & 2969 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2970} 2971 2972static void 2973ehci_device_isoc_hs_start(struct usb_xfer *xfer) 2974{ 2975 /* put transfer on interrupt queue */ 2976 ehci_transfer_intr_enqueue(xfer); 2977} 2978 2979struct usb_pipe_methods ehci_device_isoc_hs_methods = 2980{ 2981 .open = ehci_device_isoc_hs_open, 2982 .close = ehci_device_isoc_hs_close, 2983 .enter = ehci_device_isoc_hs_enter, 2984 .start = ehci_device_isoc_hs_start, 2985}; 2986 2987/*------------------------------------------------------------------------* 2988 * ehci root control support 2989 *------------------------------------------------------------------------* 2990 * Simulate a hardware hub by handling all the necessary requests. 2991 *------------------------------------------------------------------------*/ 2992 2993static const 2994struct usb_device_descriptor ehci_devd = 2995{ 2996 sizeof(struct usb_device_descriptor), 2997 UDESC_DEVICE, /* type */ 2998 {0x00, 0x02}, /* USB version */ 2999 UDCLASS_HUB, /* class */ 3000 UDSUBCLASS_HUB, /* subclass */ 3001 UDPROTO_HSHUBSTT, /* protocol */ 3002 64, /* max packet */ 3003 {0}, {0}, {0x00, 0x01}, /* device id */ 3004 1, 2, 0, /* string indicies */ 3005 1 /* # of configurations */ 3006}; 3007 3008static const 3009struct usb_device_qualifier ehci_odevd = 3010{ 3011 sizeof(struct usb_device_qualifier), 3012 UDESC_DEVICE_QUALIFIER, /* type */ 3013 {0x00, 0x02}, /* USB version */ 3014 UDCLASS_HUB, /* class */ 3015 UDSUBCLASS_HUB, /* subclass */ 3016 UDPROTO_FSHUB, /* protocol */ 3017 0, /* max packet */ 3018 0, /* # of configurations */ 3019 0 3020}; 3021 3022static const struct ehci_config_desc ehci_confd = { 3023 .confd = { 3024 .bLength = sizeof(struct usb_config_descriptor), 3025 .bDescriptorType = UDESC_CONFIG, 3026 .wTotalLength[0] = sizeof(ehci_confd), 3027 .bNumInterface = 1, 3028 .bConfigurationValue = 1, 3029 .iConfiguration = 0, 3030 .bmAttributes = UC_SELF_POWERED, 3031 .bMaxPower = 0 /* max power */ 3032 }, 3033 .ifcd = { 3034 .bLength = sizeof(struct usb_interface_descriptor), 3035 .bDescriptorType = UDESC_INTERFACE, 3036 .bNumEndpoints = 1, 3037 .bInterfaceClass = UICLASS_HUB, 3038 .bInterfaceSubClass = UISUBCLASS_HUB, 3039 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 3040 0 3041 }, 3042 .endpd = { 3043 .bLength = sizeof(struct usb_endpoint_descriptor), 3044 .bDescriptorType = UDESC_ENDPOINT, 3045 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT, 3046 .bmAttributes = UE_INTERRUPT, 3047 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 3048 .bInterval = 255, 3049 }, 3050}; 3051 3052static const 3053struct usb_hub_descriptor ehci_hubd = 3054{ 3055 0, /* dynamic length */ 3056 UDESC_HUB, 3057 0, 3058 {0, 0}, 3059 0, 3060 0, 3061 {0}, 3062}; 3063 3064static void 3065ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed) 3066{ 3067 uint32_t port; 3068 uint32_t v; 3069 3070 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed); 3071 3072 port = EHCI_PORTSC(index); 3073 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3074 EOWRITE4(sc, port, v | EHCI_PS_PO); 3075} 3076 3077static usb_error_t 3078ehci_roothub_exec(struct usb_device *udev, 3079 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3080{ 3081 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3082 const char *str_ptr; 3083 const void *ptr; 3084 uint32_t port; 3085 uint32_t v; 3086 uint16_t len; 3087 uint16_t i; 3088 uint16_t value; 3089 uint16_t index; 3090 uint8_t l; 3091 usb_error_t err; 3092 3093 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3094 3095 /* buffer reset */ 3096 ptr = (const void *)&sc->sc_hub_desc; 3097 len = 0; 3098 err = 0; 3099 3100 value = UGETW(req->wValue); 3101 index = UGETW(req->wIndex); 3102 3103 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3104 "wValue=0x%04x wIndex=0x%04x\n", 3105 req->bmRequestType, req->bRequest, 3106 UGETW(req->wLength), value, index); 3107 3108#define C(x,y) ((x) | ((y) << 8)) 3109 switch (C(req->bRequest, req->bmRequestType)) { 3110 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3111 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3112 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3113 /* 3114 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3115 * for the integrated root hub. 3116 */ 3117 break; 3118 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3119 len = 1; 3120 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3121 break; 3122 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3123 switch (value >> 8) { 3124 case UDESC_DEVICE: 3125 if ((value & 0xff) != 0) { 3126 err = USB_ERR_IOERROR; 3127 goto done; 3128 } 3129 len = sizeof(ehci_devd); 3130 ptr = (const void *)&ehci_devd; 3131 break; 3132 /* 3133 * We can't really operate at another speed, 3134 * but the specification says we need this 3135 * descriptor: 3136 */ 3137 case UDESC_DEVICE_QUALIFIER: 3138 if ((value & 0xff) != 0) { 3139 err = USB_ERR_IOERROR; 3140 goto done; 3141 } 3142 len = sizeof(ehci_odevd); 3143 ptr = (const void *)&ehci_odevd; 3144 break; 3145 3146 case UDESC_CONFIG: 3147 if ((value & 0xff) != 0) { 3148 err = USB_ERR_IOERROR; 3149 goto done; 3150 } 3151 len = sizeof(ehci_confd); 3152 ptr = (const void *)&ehci_confd; 3153 break; 3154 3155 case UDESC_STRING: 3156 switch (value & 0xff) { 3157 case 0: /* Language table */ 3158 str_ptr = "\001"; 3159 break; 3160 3161 case 1: /* Vendor */ 3162 str_ptr = sc->sc_vendor; 3163 break; 3164 3165 case 2: /* Product */ 3166 str_ptr = "EHCI root HUB"; 3167 break; 3168 3169 default: 3170 str_ptr = ""; 3171 break; 3172 } 3173 3174 len = usb_make_str_desc( 3175 sc->sc_hub_desc.temp, 3176 sizeof(sc->sc_hub_desc.temp), 3177 str_ptr); 3178 break; 3179 default: 3180 err = USB_ERR_IOERROR; 3181 goto done; 3182 } 3183 break; 3184 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3185 len = 1; 3186 sc->sc_hub_desc.temp[0] = 0; 3187 break; 3188 case C(UR_GET_STATUS, UT_READ_DEVICE): 3189 len = 2; 3190 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3191 break; 3192 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3193 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3194 len = 2; 3195 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3196 break; 3197 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3198 if (value >= EHCI_MAX_DEVICES) { 3199 err = USB_ERR_IOERROR; 3200 goto done; 3201 } 3202 sc->sc_addr = value; 3203 break; 3204 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3205 if ((value != 0) && (value != 1)) { 3206 err = USB_ERR_IOERROR; 3207 goto done; 3208 } 3209 sc->sc_conf = value; 3210 break; 3211 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3212 break; 3213 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3214 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3215 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3216 err = USB_ERR_IOERROR; 3217 goto done; 3218 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3219 break; 3220 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3221 break; 3222 /* Hub requests */ 3223 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3224 break; 3225 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3226 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3227 3228 if ((index < 1) || 3229 (index > sc->sc_noport)) { 3230 err = USB_ERR_IOERROR; 3231 goto done; 3232 } 3233 port = EHCI_PORTSC(index); 3234 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3235 switch (value) { 3236 case UHF_PORT_ENABLE: 3237 EOWRITE4(sc, port, v & ~EHCI_PS_PE); 3238 break; 3239 case UHF_PORT_SUSPEND: 3240 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) { 3241 3242 /* 3243 * waking up a High Speed device is rather 3244 * complicated if 3245 */ 3246 EOWRITE4(sc, port, v | EHCI_PS_FPR); 3247 } 3248 /* wait 20ms for resume sequence to complete */ 3249 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3250 3251 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP | 3252 EHCI_PS_FPR | (3 << 10) /* High Speed */ )); 3253 3254 /* 4ms settle time */ 3255 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3256 break; 3257 case UHF_PORT_POWER: 3258 EOWRITE4(sc, port, v & ~EHCI_PS_PP); 3259 break; 3260 case UHF_PORT_TEST: 3261 DPRINTFN(3, "clear port test " 3262 "%d\n", index); 3263 break; 3264 case UHF_PORT_INDICATOR: 3265 DPRINTFN(3, "clear port ind " 3266 "%d\n", index); 3267 EOWRITE4(sc, port, v & ~EHCI_PS_PIC); 3268 break; 3269 case UHF_C_PORT_CONNECTION: 3270 EOWRITE4(sc, port, v | EHCI_PS_CSC); 3271 break; 3272 case UHF_C_PORT_ENABLE: 3273 EOWRITE4(sc, port, v | EHCI_PS_PEC); 3274 break; 3275 case UHF_C_PORT_SUSPEND: 3276 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3277 break; 3278 case UHF_C_PORT_OVER_CURRENT: 3279 EOWRITE4(sc, port, v | EHCI_PS_OCC); 3280 break; 3281 case UHF_C_PORT_RESET: 3282 sc->sc_isreset = 0; 3283 break; 3284 default: 3285 err = USB_ERR_IOERROR; 3286 goto done; 3287 } 3288 break; 3289 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3290 if ((value & 0xff) != 0) { 3291 err = USB_ERR_IOERROR; 3292 goto done; 3293 } 3294 v = EOREAD4(sc, EHCI_HCSPARAMS); 3295 3296 sc->sc_hub_desc.hubd = ehci_hubd; 3297 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3298 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, 3299 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) | 3300 (EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) ? 3301 UHD_PORT_IND : 0)); 3302 /* XXX can't find out? */ 3303 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200; 3304 for (l = 0; l < sc->sc_noport; l++) { 3305 /* XXX can't find out? */ 3306 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] &= ~(1 << (l % 8)); 3307 } 3308 sc->sc_hub_desc.hubd.bDescLength = 3309 8 + ((sc->sc_noport + 7) / 8); 3310 len = sc->sc_hub_desc.hubd.bDescLength; 3311 break; 3312 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3313 len = 16; 3314 bzero(sc->sc_hub_desc.temp, 16); 3315 break; 3316 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3317 DPRINTFN(9, "get port status i=%d\n", 3318 index); 3319 if ((index < 1) || 3320 (index > sc->sc_noport)) { 3321 err = USB_ERR_IOERROR; 3322 goto done; 3323 } 3324 v = EOREAD4(sc, EHCI_PORTSC(index)); 3325 DPRINTFN(9, "port status=0x%04x\n", v); 3326 if (sc->sc_flags & (EHCI_SCFLG_FORCESPEED | EHCI_SCFLG_TT)) { 3327 if ((v & 0xc000000) == 0x8000000) 3328 i = UPS_HIGH_SPEED; 3329 else if ((v & 0xc000000) == 0x4000000) 3330 i = UPS_LOW_SPEED; 3331 else 3332 i = 0; 3333 } else { 3334 i = UPS_HIGH_SPEED; 3335 } 3336 if (v & EHCI_PS_CS) 3337 i |= UPS_CURRENT_CONNECT_STATUS; 3338 if (v & EHCI_PS_PE) 3339 i |= UPS_PORT_ENABLED; 3340 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR)) 3341 i |= UPS_SUSPEND; 3342 if (v & EHCI_PS_OCA) 3343 i |= UPS_OVERCURRENT_INDICATOR; 3344 if (v & EHCI_PS_PR) 3345 i |= UPS_RESET; 3346 if (v & EHCI_PS_PP) 3347 i |= UPS_PORT_POWER; 3348 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3349 i = 0; 3350 if (v & EHCI_PS_CSC) 3351 i |= UPS_C_CONNECT_STATUS; 3352 if (v & EHCI_PS_PEC) 3353 i |= UPS_C_PORT_ENABLED; 3354 if (v & EHCI_PS_OCC) 3355 i |= UPS_C_OVERCURRENT_INDICATOR; 3356 if (v & EHCI_PS_FPR) 3357 i |= UPS_C_SUSPEND; 3358 if (sc->sc_isreset) 3359 i |= UPS_C_PORT_RESET; 3360 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3361 len = sizeof(sc->sc_hub_desc.ps); 3362 break; 3363 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3364 err = USB_ERR_IOERROR; 3365 goto done; 3366 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3367 break; 3368 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3369 if ((index < 1) || 3370 (index > sc->sc_noport)) { 3371 err = USB_ERR_IOERROR; 3372 goto done; 3373 } 3374 port = EHCI_PORTSC(index); 3375 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3376 switch (value) { 3377 case UHF_PORT_ENABLE: 3378 EOWRITE4(sc, port, v | EHCI_PS_PE); 3379 break; 3380 case UHF_PORT_SUSPEND: 3381 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3382 break; 3383 case UHF_PORT_RESET: 3384 DPRINTFN(6, "reset port %d\n", index); 3385#if USB_DEBUG 3386 if (ehcinohighspeed) { 3387 /* 3388 * Connect USB device to companion 3389 * controller. 3390 */ 3391 ehci_disown(sc, index, 1); 3392 break; 3393 } 3394#endif 3395 if (EHCI_PS_IS_LOWSPEED(v) && 3396 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3397 /* Low speed device, give up ownership. */ 3398 ehci_disown(sc, index, 1); 3399 break; 3400 } 3401 /* Start reset sequence. */ 3402 v &= ~(EHCI_PS_PE | EHCI_PS_PR); 3403 EOWRITE4(sc, port, v | EHCI_PS_PR); 3404 3405 /* Wait for reset to complete. */ 3406 usb_pause_mtx(&sc->sc_bus.bus_mtx, 3407 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY)); 3408 3409 /* Terminate reset sequence. */ 3410 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM)) 3411 EOWRITE4(sc, port, v); 3412 3413 /* Wait for HC to complete reset. */ 3414 usb_pause_mtx(&sc->sc_bus.bus_mtx, 3415 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE)); 3416 3417 v = EOREAD4(sc, port); 3418 DPRINTF("ehci after reset, status=0x%08x\n", v); 3419 if (v & EHCI_PS_PR) { 3420 device_printf(sc->sc_bus.bdev, 3421 "port reset timeout\n"); 3422 err = USB_ERR_TIMEOUT; 3423 goto done; 3424 } 3425 if (!(v & EHCI_PS_PE) && 3426 (sc->sc_flags & EHCI_SCFLG_TT) == 0) { 3427 /* Not a high speed device, give up ownership.*/ 3428 ehci_disown(sc, index, 0); 3429 break; 3430 } 3431 sc->sc_isreset = 1; 3432 DPRINTF("ehci port %d reset, status = 0x%08x\n", 3433 index, v); 3434 break; 3435 3436 case UHF_PORT_POWER: 3437 DPRINTFN(3, "set port power %d\n", index); 3438 EOWRITE4(sc, port, v | EHCI_PS_PP); 3439 break; 3440 3441 case UHF_PORT_TEST: 3442 DPRINTFN(3, "set port test %d\n", index); 3443 break; 3444 3445 case UHF_PORT_INDICATOR: 3446 DPRINTFN(3, "set port ind %d\n", index); 3447 EOWRITE4(sc, port, v | EHCI_PS_PIC); 3448 break; 3449 3450 default: 3451 err = USB_ERR_IOERROR; 3452 goto done; 3453 } 3454 break; 3455 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3456 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3457 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3458 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3459 break; 3460 default: 3461 err = USB_ERR_IOERROR; 3462 goto done; 3463 } 3464done: 3465 *plength = len; 3466 *pptr = ptr; 3467 return (err); 3468} 3469 3470static void 3471ehci_xfer_setup(struct usb_setup_params *parm) 3472{ 3473 struct usb_page_search page_info; 3474 struct usb_page_cache *pc; 3475 ehci_softc_t *sc; 3476 struct usb_xfer *xfer; 3477 void *last_obj; 3478 uint32_t nqtd; 3479 uint32_t nqh; 3480 uint32_t nsitd; 3481 uint32_t nitd; 3482 uint32_t n; 3483 3484 sc = EHCI_BUS2SC(parm->udev->bus); 3485 xfer = parm->curr_xfer; 3486 3487 nqtd = 0; 3488 nqh = 0; 3489 nsitd = 0; 3490 nitd = 0; 3491 3492 /* 3493 * compute maximum number of some structures 3494 */ 3495 if (parm->methods == &ehci_device_ctrl_methods) { 3496 3497 /* 3498 * The proof for the "nqtd" formula is illustrated like 3499 * this: 3500 * 3501 * +------------------------------------+ 3502 * | | 3503 * | |remainder -> | 3504 * | +-----+---+ | 3505 * | | xxx | x | frm 0 | 3506 * | +-----+---++ | 3507 * | | xxx | xx | frm 1 | 3508 * | +-----+----+ | 3509 * | ... | 3510 * +------------------------------------+ 3511 * 3512 * "xxx" means a completely full USB transfer descriptor 3513 * 3514 * "x" and "xx" means a short USB packet 3515 * 3516 * For the remainder of an USB transfer modulo 3517 * "max_data_length" we need two USB transfer descriptors. 3518 * One to transfer the remaining data and one to finalise 3519 * with a zero length packet in case the "force_short_xfer" 3520 * flag is set. We only need two USB transfer descriptors in 3521 * the case where the transfer length of the first one is a 3522 * factor of "max_frame_size". The rest of the needed USB 3523 * transfer descriptors is given by the buffer size divided 3524 * by the maximum data payload. 3525 */ 3526 parm->hc_max_packet_size = 0x400; 3527 parm->hc_max_packet_count = 1; 3528 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3529 xfer->flags_int.bdma_enable = 1; 3530 3531 usbd_transfer_setup_sub(parm); 3532 3533 nqh = 1; 3534 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */ 3535 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3536 3537 } else if (parm->methods == &ehci_device_bulk_methods) { 3538 3539 parm->hc_max_packet_size = 0x400; 3540 parm->hc_max_packet_count = 1; 3541 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3542 xfer->flags_int.bdma_enable = 1; 3543 3544 usbd_transfer_setup_sub(parm); 3545 3546 nqh = 1; 3547 nqtd = ((2 * xfer->nframes) 3548 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3549 3550 } else if (parm->methods == &ehci_device_intr_methods) { 3551 3552 if (parm->speed == USB_SPEED_HIGH) { 3553 parm->hc_max_packet_size = 0x400; 3554 parm->hc_max_packet_count = 3; 3555 } else if (parm->speed == USB_SPEED_FULL) { 3556 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME; 3557 parm->hc_max_packet_count = 1; 3558 } else { 3559 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8; 3560 parm->hc_max_packet_count = 1; 3561 } 3562 3563 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3564 xfer->flags_int.bdma_enable = 1; 3565 3566 usbd_transfer_setup_sub(parm); 3567 3568 nqh = 1; 3569 nqtd = ((2 * xfer->nframes) 3570 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3571 3572 } else if (parm->methods == &ehci_device_isoc_fs_methods) { 3573 3574 parm->hc_max_packet_size = 0x3FF; 3575 parm->hc_max_packet_count = 1; 3576 parm->hc_max_frame_size = 0x3FF; 3577 xfer->flags_int.bdma_enable = 1; 3578 3579 usbd_transfer_setup_sub(parm); 3580 3581 nsitd = xfer->nframes; 3582 3583 } else if (parm->methods == &ehci_device_isoc_hs_methods) { 3584 3585 parm->hc_max_packet_size = 0x400; 3586 parm->hc_max_packet_count = 3; 3587 parm->hc_max_frame_size = 0xC00; 3588 xfer->flags_int.bdma_enable = 1; 3589 3590 usbd_transfer_setup_sub(parm); 3591 3592 nitd = ((xfer->nframes + 7) / 8) << 3593 usbd_xfer_get_fps_shift(xfer); 3594 3595 } else { 3596 3597 parm->hc_max_packet_size = 0x400; 3598 parm->hc_max_packet_count = 1; 3599 parm->hc_max_frame_size = 0x400; 3600 3601 usbd_transfer_setup_sub(parm); 3602 } 3603 3604alloc_dma_set: 3605 3606 if (parm->err) { 3607 return; 3608 } 3609 /* 3610 * Allocate queue heads and transfer descriptors 3611 */ 3612 last_obj = NULL; 3613 3614 if (usbd_transfer_setup_sub_malloc( 3615 parm, &pc, sizeof(ehci_itd_t), 3616 EHCI_ITD_ALIGN, nitd)) { 3617 parm->err = USB_ERR_NOMEM; 3618 return; 3619 } 3620 if (parm->buf) { 3621 for (n = 0; n != nitd; n++) { 3622 ehci_itd_t *td; 3623 3624 usbd_get_page(pc + n, 0, &page_info); 3625 3626 td = page_info.buffer; 3627 3628 /* init TD */ 3629 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD); 3630 td->obj_next = last_obj; 3631 td->page_cache = pc + n; 3632 3633 last_obj = td; 3634 3635 usb_pc_cpu_flush(pc + n); 3636 } 3637 } 3638 if (usbd_transfer_setup_sub_malloc( 3639 parm, &pc, sizeof(ehci_sitd_t), 3640 EHCI_SITD_ALIGN, nsitd)) { 3641 parm->err = USB_ERR_NOMEM; 3642 return; 3643 } 3644 if (parm->buf) { 3645 for (n = 0; n != nsitd; n++) { 3646 ehci_sitd_t *td; 3647 3648 usbd_get_page(pc + n, 0, &page_info); 3649 3650 td = page_info.buffer; 3651 3652 /* init TD */ 3653 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD); 3654 td->obj_next = last_obj; 3655 td->page_cache = pc + n; 3656 3657 last_obj = td; 3658 3659 usb_pc_cpu_flush(pc + n); 3660 } 3661 } 3662 if (usbd_transfer_setup_sub_malloc( 3663 parm, &pc, sizeof(ehci_qtd_t), 3664 EHCI_QTD_ALIGN, nqtd)) { 3665 parm->err = USB_ERR_NOMEM; 3666 return; 3667 } 3668 if (parm->buf) { 3669 for (n = 0; n != nqtd; n++) { 3670 ehci_qtd_t *qtd; 3671 3672 usbd_get_page(pc + n, 0, &page_info); 3673 3674 qtd = page_info.buffer; 3675 3676 /* init TD */ 3677 qtd->qtd_self = htohc32(sc, page_info.physaddr); 3678 qtd->obj_next = last_obj; 3679 qtd->page_cache = pc + n; 3680 3681 last_obj = qtd; 3682 3683 usb_pc_cpu_flush(pc + n); 3684 } 3685 } 3686 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3687 3688 last_obj = NULL; 3689 3690 if (usbd_transfer_setup_sub_malloc( 3691 parm, &pc, sizeof(ehci_qh_t), 3692 EHCI_QH_ALIGN, nqh)) { 3693 parm->err = USB_ERR_NOMEM; 3694 return; 3695 } 3696 if (parm->buf) { 3697 for (n = 0; n != nqh; n++) { 3698 ehci_qh_t *qh; 3699 3700 usbd_get_page(pc + n, 0, &page_info); 3701 3702 qh = page_info.buffer; 3703 3704 /* init QH */ 3705 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH); 3706 qh->obj_next = last_obj; 3707 qh->page_cache = pc + n; 3708 3709 last_obj = qh; 3710 3711 usb_pc_cpu_flush(pc + n); 3712 } 3713 } 3714 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3715 3716 if (!xfer->flags_int.curr_dma_set) { 3717 xfer->flags_int.curr_dma_set = 1; 3718 goto alloc_dma_set; 3719 } 3720} 3721 3722static void 3723ehci_xfer_unsetup(struct usb_xfer *xfer) 3724{ 3725 return; 3726} 3727 3728static void 3729ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3730 struct usb_endpoint *ep) 3731{ 3732 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3733 3734 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3735 ep, udev->address, 3736 edesc->bEndpointAddress, udev->flags.usb_mode, 3737 sc->sc_addr); 3738 3739 if (udev->flags.usb_mode != USB_MODE_HOST) { 3740 /* not supported */ 3741 return; 3742 } 3743 if (udev->device_index != sc->sc_addr) { 3744 3745 if ((udev->speed != USB_SPEED_HIGH) && 3746 ((udev->hs_hub_addr == 0) || 3747 (udev->hs_port_no == 0) || 3748 (udev->parent_hs_hub == NULL) || 3749 (udev->parent_hs_hub->hub == NULL))) { 3750 /* We need a transaction translator */ 3751 goto done; 3752 } 3753 switch (edesc->bmAttributes & UE_XFERTYPE) { 3754 case UE_CONTROL: 3755 ep->methods = &ehci_device_ctrl_methods; 3756 break; 3757 case UE_INTERRUPT: 3758 ep->methods = &ehci_device_intr_methods; 3759 break; 3760 case UE_ISOCHRONOUS: 3761 if (udev->speed == USB_SPEED_HIGH) { 3762 ep->methods = &ehci_device_isoc_hs_methods; 3763 } else if (udev->speed == USB_SPEED_FULL) { 3764 ep->methods = &ehci_device_isoc_fs_methods; 3765 } 3766 break; 3767 case UE_BULK: 3768 if (udev->speed != USB_SPEED_LOW) { 3769 ep->methods = &ehci_device_bulk_methods; 3770 } 3771 break; 3772 default: 3773 /* do nothing */ 3774 break; 3775 } 3776 } 3777done: 3778 return; 3779} 3780 3781static void 3782ehci_get_dma_delay(struct usb_bus *bus, uint32_t *pus) 3783{ 3784 /* 3785 * Wait until the hardware has finished any possible use of 3786 * the transfer descriptor(s) and QH 3787 */ 3788 *pus = (188); /* microseconds */ 3789} 3790 3791static void 3792ehci_device_resume(struct usb_device *udev) 3793{ 3794 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3795 struct usb_xfer *xfer; 3796 struct usb_pipe_methods *methods; 3797 3798 DPRINTF("\n"); 3799 3800 USB_BUS_LOCK(udev->bus); 3801 3802 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3803 3804 if (xfer->xroot->udev == udev) { 3805 3806 methods = xfer->endpoint->methods; 3807 3808 if ((methods == &ehci_device_bulk_methods) || 3809 (methods == &ehci_device_ctrl_methods)) { 3810 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3811 sc->sc_async_p_last); 3812 } 3813 if (methods == &ehci_device_intr_methods) { 3814 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3815 sc->sc_intr_p_last[xfer->qh_pos]); 3816 } 3817 } 3818 } 3819 3820 USB_BUS_UNLOCK(udev->bus); 3821 3822 return; 3823} 3824 3825static void 3826ehci_device_suspend(struct usb_device *udev) 3827{ 3828 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3829 struct usb_xfer *xfer; 3830 struct usb_pipe_methods *methods; 3831 3832 DPRINTF("\n"); 3833 3834 USB_BUS_LOCK(udev->bus); 3835 3836 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3837 3838 if (xfer->xroot->udev == udev) { 3839 3840 methods = xfer->endpoint->methods; 3841 3842 if ((methods == &ehci_device_bulk_methods) || 3843 (methods == &ehci_device_ctrl_methods)) { 3844 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3845 sc->sc_async_p_last); 3846 } 3847 if (methods == &ehci_device_intr_methods) { 3848 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3849 sc->sc_intr_p_last[xfer->qh_pos]); 3850 } 3851 } 3852 } 3853 3854 USB_BUS_UNLOCK(udev->bus); 3855 3856 return; 3857} 3858 3859static void 3860ehci_set_hw_power(struct usb_bus *bus) 3861{ 3862 ehci_softc_t *sc = EHCI_BUS2SC(bus); 3863 uint32_t temp; 3864 uint32_t flags; 3865 3866 DPRINTF("\n"); 3867 3868 USB_BUS_LOCK(bus); 3869 3870 flags = bus->hw_power_state; 3871 3872 temp = EOREAD4(sc, EHCI_USBCMD); 3873 3874 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 3875 3876 if (flags & (USB_HW_POWER_CONTROL | 3877 USB_HW_POWER_BULK)) { 3878 DPRINTF("Async is active\n"); 3879 temp |= EHCI_CMD_ASE; 3880 } 3881 if (flags & (USB_HW_POWER_INTERRUPT | 3882 USB_HW_POWER_ISOC)) { 3883 DPRINTF("Periodic is active\n"); 3884 temp |= EHCI_CMD_PSE; 3885 } 3886 EOWRITE4(sc, EHCI_USBCMD, temp); 3887 3888 USB_BUS_UNLOCK(bus); 3889 3890 return; 3891} 3892 3893struct usb_bus_methods ehci_bus_methods = 3894{ 3895 .endpoint_init = ehci_ep_init, 3896 .xfer_setup = ehci_xfer_setup, 3897 .xfer_unsetup = ehci_xfer_unsetup, 3898 .get_dma_delay = ehci_get_dma_delay, 3899 .device_resume = ehci_device_resume, 3900 .device_suspend = ehci_device_suspend, 3901 .set_hw_power = ehci_set_hw_power, 3902 .roothub_exec = ehci_roothub_exec, 3903 .xfer_poll = ehci_do_poll, 3904}; 3905