ehci.c revision 188336
1/*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 2004 Lennart Augustsson. All rights reserved. 5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 31 * 32 * The EHCI 0.96 spec can be found at 33 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 34 * The EHCI 1.0 spec can be found at 35 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 36 * and the USB 2.0 spec at 37 * http://www.usb.org/developers/docs/usb_20.zip 38 * 39 */ 40 41/* 42 * TODO: 43 * 1) command failures are not recovered correctly 44 */ 45 46#include <sys/cdefs.h> 47__FBSDID("$FreeBSD: head/sys/dev/usb2/controller/ehci2.c 188336 2009-02-08 21:08:00Z thompsa $"); 48 49#include <dev/usb2/include/usb2_standard.h> 50#include <dev/usb2/include/usb2_mfunc.h> 51#include <dev/usb2/include/usb2_error.h> 52#include <dev/usb2/include/usb2_defs.h> 53 54#define USB_DEBUG_VAR ehcidebug 55 56#include <dev/usb2/core/usb2_core.h> 57#include <dev/usb2/core/usb2_debug.h> 58#include <dev/usb2/core/usb2_busdma.h> 59#include <dev/usb2/core/usb2_process.h> 60#include <dev/usb2/core/usb2_sw_transfer.h> 61#include <dev/usb2/core/usb2_transfer.h> 62#include <dev/usb2/core/usb2_device.h> 63#include <dev/usb2/core/usb2_hub.h> 64#include <dev/usb2/core/usb2_util.h> 65 66#include <dev/usb2/controller/usb2_controller.h> 67#include <dev/usb2/controller/usb2_bus.h> 68#include <dev/usb2/controller/ehci2.h> 69 70#define EHCI_BUS2SC(bus) ((ehci_softc_t *)(((uint8_t *)(bus)) - \ 71 USB_P2U(&(((ehci_softc_t *)0)->sc_bus)))) 72 73#if USB_DEBUG 74static int ehcidebug = 0; 75static int ehcinohighspeed = 0; 76 77SYSCTL_NODE(_hw_usb2, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci"); 78SYSCTL_INT(_hw_usb2_ehci, OID_AUTO, debug, CTLFLAG_RW, 79 &ehcidebug, 0, "Debug level"); 80SYSCTL_INT(_hw_usb2_ehci, OID_AUTO, no_hs, CTLFLAG_RW, 81 &ehcinohighspeed, 0, "Disable High Speed USB"); 82 83static void ehci_dump_regs(ehci_softc_t *sc); 84static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh); 85 86#endif 87 88#define EHCI_INTR_ENDPT 1 89 90extern struct usb2_bus_methods ehci_bus_methods; 91extern struct usb2_pipe_methods ehci_device_bulk_methods; 92extern struct usb2_pipe_methods ehci_device_ctrl_methods; 93extern struct usb2_pipe_methods ehci_device_intr_methods; 94extern struct usb2_pipe_methods ehci_device_isoc_fs_methods; 95extern struct usb2_pipe_methods ehci_device_isoc_hs_methods; 96extern struct usb2_pipe_methods ehci_root_ctrl_methods; 97extern struct usb2_pipe_methods ehci_root_intr_methods; 98 99static void ehci_do_poll(struct usb2_bus *bus); 100static void ehci_root_ctrl_poll(ehci_softc_t *sc); 101static void ehci_device_done(struct usb2_xfer *xfer, usb2_error_t error); 102static uint8_t ehci_check_transfer(struct usb2_xfer *xfer); 103static void ehci_timeout(void *arg); 104 105static usb2_sw_transfer_func_t ehci_root_intr_done; 106static usb2_sw_transfer_func_t ehci_root_ctrl_done; 107 108struct ehci_std_temp { 109 ehci_softc_t *sc; 110 struct usb2_page_cache *pc; 111 ehci_qtd_t *td; 112 ehci_qtd_t *td_next; 113 uint32_t average; 114 uint32_t qtd_status; 115 uint32_t len; 116 uint16_t max_frame_size; 117 uint8_t shortpkt; 118 uint8_t auto_data_toggle; 119 uint8_t setup_alt_next; 120 uint8_t short_frames_ok; 121}; 122 123/* 124 * Byte-order conversion functions. 125 */ 126static uint32_t 127htoehci32(ehci_softc_t *sc, const uint32_t v) 128{ 129 return ((sc->sc_flags & EHCI_SCFLG_BIGEDESC) ? 130 htobe32(v) : htole32(v)); 131} 132 133static uint32_t 134ehci32toh(ehci_softc_t *sc, const uint32_t v) 135{ 136 return ((sc->sc_flags & EHCI_SCFLG_BIGEDESC) ? 137 be32toh(v) : le32toh(v)); 138} 139 140void 141ehci_iterate_hw_softc(struct usb2_bus *bus, usb2_bus_mem_sub_cb_t *cb) 142{ 143 ehci_softc_t *sc = EHCI_BUS2SC(bus); 144 uint32_t i; 145 146 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 147 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN); 148 149 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg, 150 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 151 152 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 153 cb(bus, sc->sc_hw.intr_start_pc + i, 154 sc->sc_hw.intr_start_pg + i, 155 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 156 } 157 158 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 159 cb(bus, sc->sc_hw.isoc_hs_start_pc + i, 160 sc->sc_hw.isoc_hs_start_pg + i, 161 sizeof(ehci_itd_t), EHCI_ITD_ALIGN); 162 } 163 164 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 165 cb(bus, sc->sc_hw.isoc_fs_start_pc + i, 166 sc->sc_hw.isoc_fs_start_pg + i, 167 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN); 168 } 169} 170 171static usb2_error_t 172ehci_hc_reset(ehci_softc_t *sc) 173{ 174 uint32_t hcr; 175 uint32_t n; 176 177 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 178 179 for (n = 0; n != 100; n++) { 180 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 1); 181 hcr = EOREAD4(sc, EHCI_USBSTS); 182 if (hcr & EHCI_STS_HCH) { 183 hcr = 0; 184 break; 185 } 186 } 187 188 /* 189 * Fall through and try reset anyway even though 190 * Table 2-9 in the EHCI spec says this will result 191 * in undefined behavior. 192 */ 193 194 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 195 for (n = 0; n != 100; n++) { 196 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 1); 197 hcr = EOREAD4(sc, EHCI_USBCMD); 198 if (!(hcr & EHCI_CMD_HCRESET)) { 199 if (sc->sc_flags & EHCI_SCFLG_SETMODE) 200 EOWRITE4(sc, 0x68, 0x3); 201 hcr = 0; 202 break; 203 } 204 } 205 206 if (hcr) { 207 return (USB_ERR_IOERROR); 208 } 209 return (0); 210} 211 212usb2_error_t 213ehci_init(ehci_softc_t *sc) 214{ 215 struct usb2_page_search buf_res; 216 uint32_t version; 217 uint32_t sparams; 218 uint32_t cparams; 219 uint32_t hcr; 220 uint16_t i; 221 uint16_t x; 222 uint16_t y; 223 uint16_t bit; 224 usb2_error_t err = 0; 225 226 DPRINTF("start\n"); 227 228 usb2_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0); 229 230#if USB_DEBUG 231 if (ehcidebug > 2) { 232 ehci_dump_regs(sc); 233 } 234#endif 235 236 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 237 238 version = EREAD2(sc, EHCI_HCIVERSION); 239 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n", 240 version >> 8, version & 0xff); 241 242 sparams = EREAD4(sc, EHCI_HCSPARAMS); 243 DPRINTF("sparams=0x%x\n", sparams); 244 245 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 246 cparams = EREAD4(sc, EHCI_HCCPARAMS); 247 DPRINTF("cparams=0x%x\n", cparams); 248 249 if (EHCI_HCC_64BIT(cparams)) { 250 DPRINTF("HCC uses 64-bit structures\n"); 251 252 /* MUST clear segment register if 64 bit capable */ 253 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 254 } 255 sc->sc_bus.usbrev = USB_REV_2_0; 256 257 /* Reset the controller */ 258 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)); 259 260 USB_BUS_LOCK(&sc->sc_bus); 261 err = ehci_hc_reset(sc); 262 USB_BUS_UNLOCK(&sc->sc_bus); 263 if (err) { 264 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 265 return (err); 266 } 267 /* 268 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4 269 * bytes 2: 256*4 bytes 3: unknown 270 */ 271 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) { 272 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n"); 273 return (USB_ERR_IOERROR); 274 } 275 /* set up the bus struct */ 276 sc->sc_bus.methods = &ehci_bus_methods; 277 278 sc->sc_eintrs = EHCI_NORMAL_INTRS; 279 280 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 281 ehci_qh_t *qh; 282 283 usb2_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res); 284 285 qh = buf_res.buffer; 286 287 /* initialize page cache pointer */ 288 289 qh->page_cache = sc->sc_hw.intr_start_pc + i; 290 291 /* store a pointer to queue head */ 292 293 sc->sc_intr_p_last[i] = qh; 294 295 qh->qh_self = 296 htoehci32(sc, buf_res.physaddr) | 297 htoehci32(sc, EHCI_LINK_QH); 298 299 qh->qh_endp = 300 htoehci32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 301 qh->qh_endphub = 302 htoehci32(sc, EHCI_QH_SET_MULT(1)); 303 qh->qh_curqtd = 0; 304 305 qh->qh_qtd.qtd_next = 306 htoehci32(sc, EHCI_LINK_TERMINATE); 307 qh->qh_qtd.qtd_altnext = 308 htoehci32(sc, EHCI_LINK_TERMINATE); 309 qh->qh_qtd.qtd_status = 310 htoehci32(sc, EHCI_QTD_HALTED); 311 } 312 313 /* 314 * the QHs are arranged to give poll intervals that are 315 * powers of 2 times 1ms 316 */ 317 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 318 while (bit) { 319 x = bit; 320 while (x & bit) { 321 ehci_qh_t *qh_x; 322 ehci_qh_t *qh_y; 323 324 y = (x ^ bit) | (bit / 2); 325 326 qh_x = sc->sc_intr_p_last[x]; 327 qh_y = sc->sc_intr_p_last[y]; 328 329 /* 330 * the next QH has half the poll interval 331 */ 332 qh_x->qh_link = qh_y->qh_self; 333 334 x++; 335 } 336 bit >>= 1; 337 } 338 339 if (1) { 340 ehci_qh_t *qh; 341 342 qh = sc->sc_intr_p_last[0]; 343 344 /* the last (1ms) QH terminates */ 345 qh->qh_link = htoehci32(sc, EHCI_LINK_TERMINATE); 346 } 347 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 348 ehci_sitd_t *sitd; 349 ehci_itd_t *itd; 350 351 usb2_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res); 352 353 sitd = buf_res.buffer; 354 355 /* initialize page cache pointer */ 356 357 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i; 358 359 /* store a pointer to the transfer descriptor */ 360 361 sc->sc_isoc_fs_p_last[i] = sitd; 362 363 /* initialize full speed isochronous */ 364 365 sitd->sitd_self = 366 htoehci32(sc, buf_res.physaddr) | 367 htoehci32(sc, EHCI_LINK_SITD); 368 369 sitd->sitd_back = 370 htoehci32(sc, EHCI_LINK_TERMINATE); 371 372 sitd->sitd_next = 373 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self; 374 375 376 usb2_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res); 377 378 itd = buf_res.buffer; 379 380 /* initialize page cache pointer */ 381 382 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i; 383 384 /* store a pointer to the transfer descriptor */ 385 386 sc->sc_isoc_hs_p_last[i] = itd; 387 388 /* initialize high speed isochronous */ 389 390 itd->itd_self = 391 htoehci32(sc, buf_res.physaddr) | 392 htoehci32(sc, EHCI_LINK_ITD); 393 394 itd->itd_next = 395 sitd->sitd_self; 396 } 397 398 usb2_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 399 400 if (1) { 401 uint32_t *pframes; 402 403 pframes = buf_res.buffer; 404 405 /* 406 * execution order: 407 * pframes -> high speed isochronous -> 408 * full speed isochronous -> interrupt QH's 409 */ 410 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) { 411 pframes[i] = sc->sc_isoc_hs_p_last 412 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self; 413 } 414 } 415 /* setup sync list pointer */ 416 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 417 418 usb2_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 419 420 if (1) { 421 422 ehci_qh_t *qh; 423 424 qh = buf_res.buffer; 425 426 /* initialize page cache pointer */ 427 428 qh->page_cache = &sc->sc_hw.async_start_pc; 429 430 /* store a pointer to the queue head */ 431 432 sc->sc_async_p_last = qh; 433 434 /* init dummy QH that starts the async list */ 435 436 qh->qh_self = 437 htoehci32(sc, buf_res.physaddr) | 438 htoehci32(sc, EHCI_LINK_QH); 439 440 /* fill the QH */ 441 qh->qh_endp = 442 htoehci32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 443 qh->qh_endphub = htoehci32(sc, EHCI_QH_SET_MULT(1)); 444 qh->qh_link = qh->qh_self; 445 qh->qh_curqtd = 0; 446 447 /* fill the overlay qTD */ 448 qh->qh_qtd.qtd_next = htoehci32(sc, EHCI_LINK_TERMINATE); 449 qh->qh_qtd.qtd_altnext = htoehci32(sc, EHCI_LINK_TERMINATE); 450 qh->qh_qtd.qtd_status = htoehci32(sc, EHCI_QTD_HALTED); 451 } 452 /* flush all cache into memory */ 453 454 usb2_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc); 455 456#if USB_DEBUG 457 if (ehcidebug) { 458 ehci_dump_sqh(sc, sc->sc_async_p_last); 459 } 460#endif 461 462 /* setup async list pointer */ 463 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 464 465 466 /* enable interrupts */ 467 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 468 469 /* turn on controller */ 470 EOWRITE4(sc, EHCI_USBCMD, 471 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */ 472 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 473 EHCI_CMD_ASE | 474 EHCI_CMD_PSE | 475 EHCI_CMD_RS); 476 477 /* Take over port ownership */ 478 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 479 480 for (i = 0; i < 100; i++) { 481 usb2_pause_mtx(NULL, 1); 482 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 483 if (!hcr) { 484 break; 485 } 486 } 487 if (hcr) { 488 device_printf(sc->sc_bus.bdev, "run timeout\n"); 489 return (USB_ERR_IOERROR); 490 } 491 492 if (!err) { 493 /* catch any lost interrupts */ 494 ehci_do_poll(&sc->sc_bus); 495 } 496 return (err); 497} 498 499/* 500 * shut down the controller when the system is going down 501 */ 502void 503ehci_detach(ehci_softc_t *sc) 504{ 505 USB_BUS_LOCK(&sc->sc_bus); 506 507 usb2_callout_stop(&sc->sc_tmo_pcd); 508 509 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 510 511 if (ehci_hc_reset(sc)) { 512 DPRINTF("reset failed!\n"); 513 } 514 /* XXX let stray task complete */ 515 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 50); 516 517 USB_BUS_UNLOCK(&sc->sc_bus); 518 519 usb2_callout_drain(&sc->sc_tmo_pcd); 520} 521 522void 523ehci_suspend(ehci_softc_t *sc) 524{ 525 uint32_t cmd; 526 uint32_t hcr; 527 uint8_t i; 528 529 USB_BUS_LOCK(&sc->sc_bus); 530 531 for (i = 1; i <= sc->sc_noport; i++) { 532 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 533 if (((cmd & EHCI_PS_PO) == 0) && 534 ((cmd & EHCI_PS_PE) == EHCI_PS_PE)) { 535 EOWRITE4(sc, EHCI_PORTSC(i), 536 cmd | EHCI_PS_SUSP); 537 } 538 } 539 540 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 541 542 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 543 EOWRITE4(sc, EHCI_USBCMD, cmd); 544 545 for (i = 0; i < 100; i++) { 546 hcr = EOREAD4(sc, EHCI_USBSTS) & 547 (EHCI_STS_ASS | EHCI_STS_PSS); 548 549 if (hcr == 0) { 550 break; 551 } 552 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 1); 553 } 554 555 if (hcr != 0) { 556 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 557 } 558 cmd &= ~EHCI_CMD_RS; 559 EOWRITE4(sc, EHCI_USBCMD, cmd); 560 561 for (i = 0; i < 100; i++) { 562 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 563 if (hcr == EHCI_STS_HCH) { 564 break; 565 } 566 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 1); 567 } 568 569 if (hcr != EHCI_STS_HCH) { 570 device_printf(sc->sc_bus.bdev, 571 "config timeout\n"); 572 } 573 USB_BUS_UNLOCK(&sc->sc_bus); 574} 575 576void 577ehci_resume(ehci_softc_t *sc) 578{ 579 struct usb2_page_search buf_res; 580 uint32_t cmd; 581 uint32_t hcr; 582 uint8_t i; 583 584 USB_BUS_LOCK(&sc->sc_bus); 585 586 /* restore things in case the bios doesn't */ 587 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 588 589 usb2_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 590 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 591 592 usb2_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 593 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 594 595 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 596 597 hcr = 0; 598 for (i = 1; i <= sc->sc_noport; i++) { 599 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 600 if (((cmd & EHCI_PS_PO) == 0) && 601 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) { 602 EOWRITE4(sc, EHCI_PORTSC(i), 603 cmd | EHCI_PS_FPR); 604 hcr = 1; 605 } 606 } 607 608 if (hcr) { 609 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 610 USB_RESUME_WAIT); 611 612 for (i = 1; i <= sc->sc_noport; i++) { 613 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 614 if (((cmd & EHCI_PS_PO) == 0) && 615 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) { 616 EOWRITE4(sc, EHCI_PORTSC(i), 617 cmd & ~EHCI_PS_FPR); 618 } 619 } 620 } 621 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 622 623 for (i = 0; i < 100; i++) { 624 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 625 if (hcr != EHCI_STS_HCH) { 626 break; 627 } 628 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 1); 629 } 630 if (hcr == EHCI_STS_HCH) { 631 device_printf(sc->sc_bus.bdev, "config timeout\n"); 632 } 633 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 634 USB_RESUME_WAIT); 635 636 USB_BUS_UNLOCK(&sc->sc_bus); 637 638 /* catch any lost interrupts */ 639 ehci_do_poll(&sc->sc_bus); 640} 641 642void 643ehci_shutdown(ehci_softc_t *sc) 644{ 645 DPRINTF("stopping the HC\n"); 646 647 USB_BUS_LOCK(&sc->sc_bus); 648 649 if (ehci_hc_reset(sc)) { 650 DPRINTF("reset failed!\n"); 651 } 652 USB_BUS_UNLOCK(&sc->sc_bus); 653} 654 655#if USB_DEBUG 656static void 657ehci_dump_regs(ehci_softc_t *sc) 658{ 659 uint32_t i; 660 661 i = EOREAD4(sc, EHCI_USBCMD); 662 printf("cmd=0x%08x\n", i); 663 664 if (i & EHCI_CMD_ITC_1) 665 printf(" EHCI_CMD_ITC_1\n"); 666 if (i & EHCI_CMD_ITC_2) 667 printf(" EHCI_CMD_ITC_2\n"); 668 if (i & EHCI_CMD_ITC_4) 669 printf(" EHCI_CMD_ITC_4\n"); 670 if (i & EHCI_CMD_ITC_8) 671 printf(" EHCI_CMD_ITC_8\n"); 672 if (i & EHCI_CMD_ITC_16) 673 printf(" EHCI_CMD_ITC_16\n"); 674 if (i & EHCI_CMD_ITC_32) 675 printf(" EHCI_CMD_ITC_32\n"); 676 if (i & EHCI_CMD_ITC_64) 677 printf(" EHCI_CMD_ITC_64\n"); 678 if (i & EHCI_CMD_ASPME) 679 printf(" EHCI_CMD_ASPME\n"); 680 if (i & EHCI_CMD_ASPMC) 681 printf(" EHCI_CMD_ASPMC\n"); 682 if (i & EHCI_CMD_LHCR) 683 printf(" EHCI_CMD_LHCR\n"); 684 if (i & EHCI_CMD_IAAD) 685 printf(" EHCI_CMD_IAAD\n"); 686 if (i & EHCI_CMD_ASE) 687 printf(" EHCI_CMD_ASE\n"); 688 if (i & EHCI_CMD_PSE) 689 printf(" EHCI_CMD_PSE\n"); 690 if (i & EHCI_CMD_FLS_M) 691 printf(" EHCI_CMD_FLS_M\n"); 692 if (i & EHCI_CMD_HCRESET) 693 printf(" EHCI_CMD_HCRESET\n"); 694 if (i & EHCI_CMD_RS) 695 printf(" EHCI_CMD_RS\n"); 696 697 i = EOREAD4(sc, EHCI_USBSTS); 698 699 printf("sts=0x%08x\n", i); 700 701 if (i & EHCI_STS_ASS) 702 printf(" EHCI_STS_ASS\n"); 703 if (i & EHCI_STS_PSS) 704 printf(" EHCI_STS_PSS\n"); 705 if (i & EHCI_STS_REC) 706 printf(" EHCI_STS_REC\n"); 707 if (i & EHCI_STS_HCH) 708 printf(" EHCI_STS_HCH\n"); 709 if (i & EHCI_STS_IAA) 710 printf(" EHCI_STS_IAA\n"); 711 if (i & EHCI_STS_HSE) 712 printf(" EHCI_STS_HSE\n"); 713 if (i & EHCI_STS_FLR) 714 printf(" EHCI_STS_FLR\n"); 715 if (i & EHCI_STS_PCD) 716 printf(" EHCI_STS_PCD\n"); 717 if (i & EHCI_STS_ERRINT) 718 printf(" EHCI_STS_ERRINT\n"); 719 if (i & EHCI_STS_INT) 720 printf(" EHCI_STS_INT\n"); 721 722 printf("ien=0x%08x\n", 723 EOREAD4(sc, EHCI_USBINTR)); 724 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 725 EOREAD4(sc, EHCI_FRINDEX), 726 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 727 EOREAD4(sc, EHCI_PERIODICLISTBASE), 728 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 729 for (i = 1; i <= sc->sc_noport; i++) { 730 printf("port %d status=0x%08x\n", i, 731 EOREAD4(sc, EHCI_PORTSC(i))); 732 } 733} 734 735static void 736ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type) 737{ 738 link = ehci32toh(sc, link); 739 printf("0x%08x", link); 740 if (link & EHCI_LINK_TERMINATE) 741 printf("<T>"); 742 else { 743 printf("<"); 744 if (type) { 745 switch (EHCI_LINK_TYPE(link)) { 746 case EHCI_LINK_ITD: 747 printf("ITD"); 748 break; 749 case EHCI_LINK_QH: 750 printf("QH"); 751 break; 752 case EHCI_LINK_SITD: 753 printf("SITD"); 754 break; 755 case EHCI_LINK_FSTN: 756 printf("FSTN"); 757 break; 758 } 759 } 760 printf(">"); 761 } 762} 763 764static void 765ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd) 766{ 767 uint32_t s; 768 769 printf(" next="); 770 ehci_dump_link(sc, qtd->qtd_next, 0); 771 printf(" altnext="); 772 ehci_dump_link(sc, qtd->qtd_altnext, 0); 773 printf("\n"); 774 s = ehci32toh(sc, qtd->qtd_status); 775 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 776 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 777 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 778 printf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n", 779 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), 780 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE", 781 (s & EHCI_QTD_HALTED) ? "-HALTED" : "", 782 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "", 783 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "", 784 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "", 785 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "", 786 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "", 787 (s & EHCI_QTD_PINGSTATE) ? "-PING" : ""); 788 789 for (s = 0; s < 5; s++) { 790 printf(" buffer[%d]=0x%08x\n", s, 791 ehci32toh(sc, qtd->qtd_buffer[s])); 792 } 793 for (s = 0; s < 5; s++) { 794 printf(" buffer_hi[%d]=0x%08x\n", s, 795 ehci32toh(sc, qtd->qtd_buffer_hi[s])); 796 } 797} 798 799static uint8_t 800ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd) 801{ 802 uint8_t temp; 803 804 usb2_pc_cpu_invalidate(sqtd->page_cache); 805 printf("QTD(%p) at 0x%08x:\n", sqtd, ehci32toh(sc, sqtd->qtd_self)); 806 ehci_dump_qtd(sc, sqtd); 807 temp = (sqtd->qtd_next & htoehci32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0; 808 return (temp); 809} 810 811static void 812ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd) 813{ 814 uint16_t i; 815 uint8_t stop; 816 817 stop = 0; 818 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) { 819 stop = ehci_dump_sqtd(sc, sqtd); 820 } 821 if (sqtd) { 822 printf("dump aborted, too many TDs\n"); 823 } 824} 825 826static void 827ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh) 828{ 829 uint32_t endp; 830 uint32_t endphub; 831 832 usb2_pc_cpu_invalidate(qh->page_cache); 833 printf("QH(%p) at 0x%08x:\n", qh, ehci32toh(sc, qh->qh_self) & ~0x1F); 834 printf(" link="); 835 ehci_dump_link(sc, qh->qh_link, 1); 836 printf("\n"); 837 endp = ehci32toh(sc, qh->qh_endp); 838 printf(" endp=0x%08x\n", endp); 839 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 840 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 841 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 842 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 843 printf(" mpl=0x%x ctl=%d nrl=%d\n", 844 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 845 EHCI_QH_GET_NRL(endp)); 846 endphub = ehci32toh(sc, qh->qh_endphub); 847 printf(" endphub=0x%08x\n", endphub); 848 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 849 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 850 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 851 EHCI_QH_GET_MULT(endphub)); 852 printf(" curqtd="); 853 ehci_dump_link(sc, qh->qh_curqtd, 0); 854 printf("\n"); 855 printf("Overlay qTD:\n"); 856 ehci_dump_qtd(sc, (void *)&qh->qh_qtd); 857} 858 859static void 860ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd) 861{ 862 usb2_pc_cpu_invalidate(sitd->page_cache); 863 printf("SITD(%p) at 0x%08x\n", sitd, ehci32toh(sc, sitd->sitd_self) & ~0x1F); 864 printf(" next=0x%08x\n", ehci32toh(sc, sitd->sitd_next)); 865 printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n", 866 ehci32toh(sc, sitd->sitd_portaddr), 867 (sitd->sitd_portaddr & htoehci32(sc, EHCI_SITD_SET_DIR_IN)) 868 ? "in" : "out", 869 EHCI_SITD_GET_ADDR(ehci32toh(sc, sitd->sitd_portaddr)), 870 EHCI_SITD_GET_ENDPT(ehci32toh(sc, sitd->sitd_portaddr)), 871 EHCI_SITD_GET_PORT(ehci32toh(sc, sitd->sitd_portaddr)), 872 EHCI_SITD_GET_HUBA(ehci32toh(sc, sitd->sitd_portaddr))); 873 printf(" mask=0x%08x\n", ehci32toh(sc, sitd->sitd_mask)); 874 printf(" status=0x%08x <%s> len=0x%x\n", ehci32toh(sc, sitd->sitd_status), 875 (sitd->sitd_status & htoehci32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "", 876 EHCI_SITD_GET_LEN(ehci32toh(sc, sitd->sitd_status))); 877 printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n", 878 ehci32toh(sc, sitd->sitd_back), 879 ehci32toh(sc, sitd->sitd_bp[0]), 880 ehci32toh(sc, sitd->sitd_bp[1]), 881 ehci32toh(sc, sitd->sitd_bp_hi[0]), 882 ehci32toh(sc, sitd->sitd_bp_hi[1])); 883} 884 885static void 886ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd) 887{ 888 usb2_pc_cpu_invalidate(itd->page_cache); 889 printf("ITD(%p) at 0x%08x\n", itd, ehci32toh(sc, itd->itd_self) & ~0x1F); 890 printf(" next=0x%08x\n", ehci32toh(sc, itd->itd_next)); 891 printf(" status[0]=0x%08x; <%s>\n", ehci32toh(sc, itd->itd_status[0]), 892 (itd->itd_status[0] & htoehci32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 893 printf(" status[1]=0x%08x; <%s>\n", ehci32toh(sc, itd->itd_status[1]), 894 (itd->itd_status[1] & htoehci32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 895 printf(" status[2]=0x%08x; <%s>\n", ehci32toh(sc, itd->itd_status[2]), 896 (itd->itd_status[2] & htoehci32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 897 printf(" status[3]=0x%08x; <%s>\n", ehci32toh(sc, itd->itd_status[3]), 898 (itd->itd_status[3] & htoehci32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 899 printf(" status[4]=0x%08x; <%s>\n", ehci32toh(sc, itd->itd_status[4]), 900 (itd->itd_status[4] & htoehci32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 901 printf(" status[5]=0x%08x; <%s>\n", ehci32toh(sc, itd->itd_status[5]), 902 (itd->itd_status[5] & htoehci32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 903 printf(" status[6]=0x%08x; <%s>\n", ehci32toh(sc, itd->itd_status[6]), 904 (itd->itd_status[6] & htoehci32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 905 printf(" status[7]=0x%08x; <%s>\n", ehci32toh(sc, itd->itd_status[7]), 906 (itd->itd_status[7] & htoehci32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 907 printf(" bp[0]=0x%08x\n", ehci32toh(sc, itd->itd_bp[0])); 908 printf(" addr=0x%02x; endpt=0x%01x\n", 909 EHCI_ITD_GET_ADDR(ehci32toh(sc, itd->itd_bp[0])), 910 EHCI_ITD_GET_ENDPT(ehci32toh(sc, itd->itd_bp[0]))); 911 printf(" bp[1]=0x%08x\n", ehci32toh(sc, itd->itd_bp[1])); 912 printf(" dir=%s; mpl=0x%02x\n", 913 (ehci32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out", 914 EHCI_ITD_GET_MPL(ehci32toh(sc, itd->itd_bp[1]))); 915 printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n", 916 ehci32toh(sc, itd->itd_bp[2]), 917 ehci32toh(sc, itd->itd_bp[3]), 918 ehci32toh(sc, itd->itd_bp[4]), 919 ehci32toh(sc, itd->itd_bp[5]), 920 ehci32toh(sc, itd->itd_bp[6])); 921 printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n" 922 " 0x%08x,0x%08x,0x%08x\n", 923 ehci32toh(sc, itd->itd_bp_hi[0]), 924 ehci32toh(sc, itd->itd_bp_hi[1]), 925 ehci32toh(sc, itd->itd_bp_hi[2]), 926 ehci32toh(sc, itd->itd_bp_hi[3]), 927 ehci32toh(sc, itd->itd_bp_hi[4]), 928 ehci32toh(sc, itd->itd_bp_hi[5]), 929 ehci32toh(sc, itd->itd_bp_hi[6])); 930} 931 932static void 933ehci_dump_isoc(ehci_softc_t *sc) 934{ 935 ehci_itd_t *itd; 936 ehci_sitd_t *sitd; 937 uint16_t max = 1000; 938 uint16_t pos; 939 940 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) & 941 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 942 943 printf("%s: isochronous dump from frame 0x%03x:\n", 944 __FUNCTION__, pos); 945 946 itd = sc->sc_isoc_hs_p_last[pos]; 947 sitd = sc->sc_isoc_fs_p_last[pos]; 948 949 while (itd && max && max--) { 950 ehci_dump_itd(sc, itd); 951 itd = itd->prev; 952 } 953 954 while (sitd && max && max--) { 955 ehci_dump_sitd(sc, sitd); 956 sitd = sitd->prev; 957 } 958} 959 960#endif 961 962static void 963ehci_transfer_intr_enqueue(struct usb2_xfer *xfer) 964{ 965 /* check for early completion */ 966 if (ehci_check_transfer(xfer)) { 967 return; 968 } 969 /* put transfer on interrupt queue */ 970 usb2_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 971 972 /* start timeout, if any */ 973 if (xfer->timeout != 0) { 974 usb2_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout); 975 } 976} 977 978#define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last) 979static ehci_sitd_t * 980_ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 981{ 982 DPRINTFN(11, "%p to %p\n", std, last); 983 984 /* (sc->sc_bus.mtx) must be locked */ 985 986 std->next = last->next; 987 std->sitd_next = last->sitd_next; 988 989 std->prev = last; 990 991 usb2_pc_cpu_flush(std->page_cache); 992 993 /* 994 * the last->next->prev is never followed: std->next->prev = std; 995 */ 996 last->next = std; 997 last->sitd_next = std->sitd_self; 998 999 usb2_pc_cpu_flush(last->page_cache); 1000 1001 return (std); 1002} 1003 1004#define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last) 1005static ehci_itd_t * 1006_ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1007{ 1008 DPRINTFN(11, "%p to %p\n", std, last); 1009 1010 /* (sc->sc_bus.mtx) must be locked */ 1011 1012 std->next = last->next; 1013 std->itd_next = last->itd_next; 1014 1015 std->prev = last; 1016 1017 usb2_pc_cpu_flush(std->page_cache); 1018 1019 /* 1020 * the last->next->prev is never followed: std->next->prev = std; 1021 */ 1022 last->next = std; 1023 last->itd_next = std->itd_self; 1024 1025 usb2_pc_cpu_flush(last->page_cache); 1026 1027 return (std); 1028} 1029 1030#define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last) 1031static ehci_qh_t * 1032_ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1033{ 1034 DPRINTFN(11, "%p to %p\n", sqh, last); 1035 1036 if (sqh->prev != NULL) { 1037 /* should not happen */ 1038 DPRINTFN(0, "QH already linked!\n"); 1039 return (last); 1040 } 1041 /* (sc->sc_bus.mtx) must be locked */ 1042 1043 sqh->next = last->next; 1044 sqh->qh_link = last->qh_link; 1045 1046 sqh->prev = last; 1047 1048 usb2_pc_cpu_flush(sqh->page_cache); 1049 1050 /* 1051 * the last->next->prev is never followed: sqh->next->prev = sqh; 1052 */ 1053 1054 last->next = sqh; 1055 last->qh_link = sqh->qh_self; 1056 1057 usb2_pc_cpu_flush(last->page_cache); 1058 1059 return (sqh); 1060} 1061 1062#define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last) 1063static ehci_sitd_t * 1064_ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 1065{ 1066 DPRINTFN(11, "%p from %p\n", std, last); 1067 1068 /* (sc->sc_bus.mtx) must be locked */ 1069 1070 std->prev->next = std->next; 1071 std->prev->sitd_next = std->sitd_next; 1072 1073 usb2_pc_cpu_flush(std->prev->page_cache); 1074 1075 if (std->next) { 1076 std->next->prev = std->prev; 1077 usb2_pc_cpu_flush(std->next->page_cache); 1078 } 1079 return ((last == std) ? std->prev : last); 1080} 1081 1082#define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last) 1083static ehci_itd_t * 1084_ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1085{ 1086 DPRINTFN(11, "%p from %p\n", std, last); 1087 1088 /* (sc->sc_bus.mtx) must be locked */ 1089 1090 std->prev->next = std->next; 1091 std->prev->itd_next = std->itd_next; 1092 1093 usb2_pc_cpu_flush(std->prev->page_cache); 1094 1095 if (std->next) { 1096 std->next->prev = std->prev; 1097 usb2_pc_cpu_flush(std->next->page_cache); 1098 } 1099 return ((last == std) ? std->prev : last); 1100} 1101 1102#define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last) 1103static ehci_qh_t * 1104_ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1105{ 1106 DPRINTFN(11, "%p from %p\n", sqh, last); 1107 1108 /* (sc->sc_bus.mtx) must be locked */ 1109 1110 /* only remove if not removed from a queue */ 1111 if (sqh->prev) { 1112 1113 sqh->prev->next = sqh->next; 1114 sqh->prev->qh_link = sqh->qh_link; 1115 1116 usb2_pc_cpu_flush(sqh->prev->page_cache); 1117 1118 if (sqh->next) { 1119 sqh->next->prev = sqh->prev; 1120 usb2_pc_cpu_flush(sqh->next->page_cache); 1121 } 1122 last = ((last == sqh) ? sqh->prev : last); 1123 1124 sqh->prev = 0; 1125 1126 usb2_pc_cpu_flush(sqh->page_cache); 1127 } 1128 return (last); 1129} 1130 1131static usb2_error_t 1132ehci_non_isoc_done_sub(struct usb2_xfer *xfer) 1133{ 1134 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1135 ehci_qtd_t *td; 1136 ehci_qtd_t *td_alt_next; 1137 uint32_t status; 1138 uint16_t len; 1139 1140 td = xfer->td_transfer_cache; 1141 td_alt_next = td->alt_next; 1142 1143 while (1) { 1144 1145 usb2_pc_cpu_invalidate(td->page_cache); 1146 status = ehci32toh(sc, td->qtd_status); 1147 1148 len = EHCI_QTD_GET_BYTES(status); 1149 1150 /* 1151 * Verify the status length and subtract 1152 * the remainder from "frlengths[]": 1153 */ 1154 if (len > td->len) { 1155 /* should not happen */ 1156 DPRINTF("Invalid status length, " 1157 "0x%04x/0x%04x bytes\n", len, td->len); 1158 status |= EHCI_QTD_HALTED; 1159 } else if (xfer->aframes != xfer->nframes) { 1160 xfer->frlengths[xfer->aframes] -= len; 1161 } 1162 /* Check for last transfer */ 1163 if (((void *)td) == xfer->td_transfer_last) { 1164 if (len == 0) { 1165 /* 1166 * Halt is ok if descriptor is last, 1167 * and complete: 1168 */ 1169 status &= ~EHCI_QTD_HALTED; 1170 } 1171 td = NULL; 1172 break; 1173 } 1174 /* Check for transfer error */ 1175 if (status & EHCI_QTD_HALTED) { 1176 /* the transfer is finished */ 1177 td = NULL; 1178 break; 1179 } 1180 /* Check for short transfer */ 1181 if (len > 0) { 1182 if (xfer->flags_int.short_frames_ok) { 1183 /* follow alt next */ 1184 td = td->alt_next; 1185 } else { 1186 /* the transfer is finished */ 1187 td = NULL; 1188 } 1189 break; 1190 } 1191 td = td->obj_next; 1192 1193 if (td->alt_next != td_alt_next) { 1194 /* this USB frame is complete */ 1195 break; 1196 } 1197 } 1198 1199 /* update transfer cache */ 1200 1201 xfer->td_transfer_cache = td; 1202 1203 /* update data toggle */ 1204 1205 xfer->pipe->toggle_next = 1206 (status & EHCI_QTD_TOGGLE_MASK) ? 1 : 0; 1207 1208#if USB_DEBUG 1209 if (status & EHCI_QTD_STATERRS) { 1210 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x" 1211 "status=%s%s%s%s%s%s%s%s\n", 1212 xfer->address, xfer->endpoint, xfer->aframes, 1213 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1214 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "", 1215 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "", 1216 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "", 1217 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "", 1218 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "", 1219 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "", 1220 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : ""); 1221 } 1222#endif 1223 1224 return ((status & EHCI_QTD_HALTED) ? 1225 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1226} 1227 1228static void 1229ehci_non_isoc_done(struct usb2_xfer *xfer) 1230{ 1231 usb2_error_t err = 0; 1232 1233 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1234 xfer, xfer->pipe); 1235 1236#if USB_DEBUG 1237 if (ehcidebug > 10) { 1238 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1239 1240 ehci_dump_sqtds(sc, xfer->td_transfer_first); 1241 } 1242#endif 1243 1244 /* reset scanner */ 1245 1246 xfer->td_transfer_cache = xfer->td_transfer_first; 1247 1248 if (xfer->flags_int.control_xfr) { 1249 1250 if (xfer->flags_int.control_hdr) { 1251 1252 err = ehci_non_isoc_done_sub(xfer); 1253 } 1254 xfer->aframes = 1; 1255 1256 if (xfer->td_transfer_cache == NULL) { 1257 goto done; 1258 } 1259 } 1260 while (xfer->aframes != xfer->nframes) { 1261 1262 err = ehci_non_isoc_done_sub(xfer); 1263 xfer->aframes++; 1264 1265 if (xfer->td_transfer_cache == NULL) { 1266 goto done; 1267 } 1268 } 1269 1270 if (xfer->flags_int.control_xfr && 1271 !xfer->flags_int.control_act) { 1272 1273 err = ehci_non_isoc_done_sub(xfer); 1274 } 1275done: 1276 ehci_device_done(xfer, err); 1277} 1278 1279/*------------------------------------------------------------------------* 1280 * ehci_check_transfer 1281 * 1282 * Return values: 1283 * 0: USB transfer is not finished 1284 * Else: USB transfer is finished 1285 *------------------------------------------------------------------------*/ 1286static uint8_t 1287ehci_check_transfer(struct usb2_xfer *xfer) 1288{ 1289 struct usb2_pipe_methods *methods = xfer->pipe->methods; 1290 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1291 1292 uint32_t status; 1293 1294 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1295 1296 if (methods == &ehci_device_isoc_fs_methods) { 1297 ehci_sitd_t *td; 1298 1299 /* isochronous full speed transfer */ 1300 1301 td = xfer->td_transfer_last; 1302 usb2_pc_cpu_invalidate(td->page_cache); 1303 status = ehci32toh(sc, td->sitd_status); 1304 1305 /* also check if first is complete */ 1306 1307 td = xfer->td_transfer_first; 1308 usb2_pc_cpu_invalidate(td->page_cache); 1309 status |= ehci32toh(sc, td->sitd_status); 1310 1311 if (!(status & EHCI_SITD_ACTIVE)) { 1312 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1313 goto transferred; 1314 } 1315 } else if (methods == &ehci_device_isoc_hs_methods) { 1316 ehci_itd_t *td; 1317 1318 /* isochronous high speed transfer */ 1319 1320 td = xfer->td_transfer_last; 1321 usb2_pc_cpu_invalidate(td->page_cache); 1322 status = 1323 td->itd_status[0] | td->itd_status[1] | 1324 td->itd_status[2] | td->itd_status[3] | 1325 td->itd_status[4] | td->itd_status[5] | 1326 td->itd_status[6] | td->itd_status[7]; 1327 1328 /* also check first transfer */ 1329 td = xfer->td_transfer_first; 1330 usb2_pc_cpu_invalidate(td->page_cache); 1331 status |= 1332 td->itd_status[0] | td->itd_status[1] | 1333 td->itd_status[2] | td->itd_status[3] | 1334 td->itd_status[4] | td->itd_status[5] | 1335 td->itd_status[6] | td->itd_status[7]; 1336 1337 /* if no transactions are active we continue */ 1338 if (!(status & htoehci32(sc, EHCI_ITD_ACTIVE))) { 1339 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1340 goto transferred; 1341 } 1342 } else { 1343 ehci_qtd_t *td; 1344 1345 /* non-isochronous transfer */ 1346 1347 /* 1348 * check whether there is an error somewhere in the middle, 1349 * or whether there was a short packet (SPD and not ACTIVE) 1350 */ 1351 td = xfer->td_transfer_cache; 1352 1353 while (1) { 1354 usb2_pc_cpu_invalidate(td->page_cache); 1355 status = ehci32toh(sc, td->qtd_status); 1356 1357 /* 1358 * if there is an active TD the transfer isn't done 1359 */ 1360 if (status & EHCI_QTD_ACTIVE) { 1361 /* update cache */ 1362 xfer->td_transfer_cache = td; 1363 goto done; 1364 } 1365 /* 1366 * last transfer descriptor makes the transfer done 1367 */ 1368 if (((void *)td) == xfer->td_transfer_last) { 1369 break; 1370 } 1371 /* 1372 * any kind of error makes the transfer done 1373 */ 1374 if (status & EHCI_QTD_HALTED) { 1375 break; 1376 } 1377 /* 1378 * if there is no alternate next transfer, a short 1379 * packet also makes the transfer done 1380 */ 1381 if (EHCI_QTD_GET_BYTES(status)) { 1382 if (xfer->flags_int.short_frames_ok) { 1383 /* follow alt next */ 1384 if (td->alt_next) { 1385 td = td->alt_next; 1386 continue; 1387 } 1388 } 1389 /* transfer is done */ 1390 break; 1391 } 1392 td = td->obj_next; 1393 } 1394 ehci_non_isoc_done(xfer); 1395 goto transferred; 1396 } 1397 1398done: 1399 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1400 return (0); 1401 1402transferred: 1403 return (1); 1404} 1405 1406static void 1407ehci_pcd_enable(ehci_softc_t *sc) 1408{ 1409 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1410 1411 sc->sc_eintrs |= EHCI_STS_PCD; 1412 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1413 1414 /* acknowledge any PCD interrupt */ 1415 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD); 1416 1417 usb2_sw_transfer(&sc->sc_root_intr, 1418 &ehci_root_intr_done); 1419} 1420 1421static void 1422ehci_interrupt_poll(ehci_softc_t *sc) 1423{ 1424 struct usb2_xfer *xfer; 1425 1426repeat: 1427 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1428 /* 1429 * check if transfer is transferred 1430 */ 1431 if (ehci_check_transfer(xfer)) { 1432 /* queue has been modified */ 1433 goto repeat; 1434 } 1435 } 1436} 1437 1438/*------------------------------------------------------------------------* 1439 * ehci_interrupt - EHCI interrupt handler 1440 * 1441 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1442 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1443 * is present ! 1444 *------------------------------------------------------------------------*/ 1445void 1446ehci_interrupt(ehci_softc_t *sc) 1447{ 1448 uint32_t status; 1449 1450 USB_BUS_LOCK(&sc->sc_bus); 1451 1452 DPRINTFN(16, "real interrupt\n"); 1453 1454#if USB_DEBUG 1455 if (ehcidebug > 15) { 1456 ehci_dump_regs(sc); 1457 } 1458#endif 1459 1460 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1461 if (status == 0) { 1462 /* the interrupt was not for us */ 1463 goto done; 1464 } 1465 if (!(status & sc->sc_eintrs)) { 1466 goto done; 1467 } 1468 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */ 1469 1470 status &= sc->sc_eintrs; 1471 1472 if (status & EHCI_STS_HSE) { 1473 printf("%s: unrecoverable error, " 1474 "controller halted\n", __FUNCTION__); 1475#if USB_DEBUG 1476 ehci_dump_regs(sc); 1477 ehci_dump_isoc(sc); 1478#endif 1479 } 1480 if (status & EHCI_STS_PCD) { 1481 /* 1482 * Disable PCD interrupt for now, because it will be 1483 * on until the port has been reset. 1484 */ 1485 sc->sc_eintrs &= ~EHCI_STS_PCD; 1486 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1487 1488 usb2_sw_transfer(&sc->sc_root_intr, 1489 &ehci_root_intr_done); 1490 1491 /* do not allow RHSC interrupts > 1 per second */ 1492 usb2_callout_reset(&sc->sc_tmo_pcd, hz, 1493 (void *)&ehci_pcd_enable, sc); 1494 } 1495 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA); 1496 1497 if (status != 0) { 1498 /* block unprocessed interrupts */ 1499 sc->sc_eintrs &= ~status; 1500 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1501 printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status); 1502 } 1503 /* poll all the USB transfers */ 1504 ehci_interrupt_poll(sc); 1505 1506done: 1507 USB_BUS_UNLOCK(&sc->sc_bus); 1508} 1509 1510/* 1511 * called when a request does not complete 1512 */ 1513static void 1514ehci_timeout(void *arg) 1515{ 1516 struct usb2_xfer *xfer = arg; 1517 1518 DPRINTF("xfer=%p\n", xfer); 1519 1520 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1521 1522 /* transfer is transferred */ 1523 ehci_device_done(xfer, USB_ERR_TIMEOUT); 1524} 1525 1526static void 1527ehci_do_poll(struct usb2_bus *bus) 1528{ 1529 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1530 1531 USB_BUS_LOCK(&sc->sc_bus); 1532 ehci_interrupt_poll(sc); 1533 ehci_root_ctrl_poll(sc); 1534 USB_BUS_UNLOCK(&sc->sc_bus); 1535} 1536 1537static void 1538ehci_setup_standard_chain_sub(struct ehci_std_temp *temp) 1539{ 1540 struct usb2_page_search buf_res; 1541 ehci_qtd_t *td; 1542 ehci_qtd_t *td_next; 1543 ehci_qtd_t *td_alt_next; 1544 uint32_t qtd_altnext; 1545 uint32_t buf_offset; 1546 uint32_t average; 1547 uint32_t len_old; 1548 uint8_t shortpkt_old; 1549 uint8_t precompute; 1550 1551 qtd_altnext = htoehci32(temp->sc, EHCI_LINK_TERMINATE); 1552 td_alt_next = NULL; 1553 buf_offset = 0; 1554 shortpkt_old = temp->shortpkt; 1555 len_old = temp->len; 1556 precompute = 1; 1557 1558restart: 1559 1560 td = temp->td; 1561 td_next = temp->td_next; 1562 1563 while (1) { 1564 1565 if (temp->len == 0) { 1566 1567 if (temp->shortpkt) { 1568 break; 1569 } 1570 /* send a Zero Length Packet, ZLP, last */ 1571 1572 temp->shortpkt = 1; 1573 average = 0; 1574 1575 } else { 1576 1577 average = temp->average; 1578 1579 if (temp->len < average) { 1580 if (temp->len % temp->max_frame_size) { 1581 temp->shortpkt = 1; 1582 } 1583 average = temp->len; 1584 } 1585 } 1586 1587 if (td_next == NULL) { 1588 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__); 1589 } 1590 /* get next TD */ 1591 1592 td = td_next; 1593 td_next = td->obj_next; 1594 1595 /* check if we are pre-computing */ 1596 1597 if (precompute) { 1598 1599 /* update remaining length */ 1600 1601 temp->len -= average; 1602 1603 continue; 1604 } 1605 /* fill out current TD */ 1606 1607 td->qtd_status = 1608 temp->qtd_status | 1609 htoehci32(temp->sc, EHCI_QTD_SET_BYTES(average)); 1610 1611 if (average == 0) { 1612 1613 if (temp->auto_data_toggle == 0) { 1614 1615 /* update data toggle, ZLP case */ 1616 1617 temp->qtd_status ^= 1618 htoehci32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1619 } 1620 td->len = 0; 1621 1622 td->qtd_buffer[0] = 0; 1623 td->qtd_buffer_hi[0] = 0; 1624 1625 td->qtd_buffer[1] = 0; 1626 td->qtd_buffer_hi[1] = 0; 1627 1628 } else { 1629 1630 uint8_t x; 1631 1632 if (temp->auto_data_toggle == 0) { 1633 1634 /* update data toggle */ 1635 1636 if (((average + temp->max_frame_size - 1) / 1637 temp->max_frame_size) & 1) { 1638 temp->qtd_status ^= 1639 htoehci32(temp->sc, EHCI_QTD_TOGGLE_MASK); 1640 } 1641 } 1642 td->len = average; 1643 1644 /* update remaining length */ 1645 1646 temp->len -= average; 1647 1648 /* fill out buffer pointers */ 1649 1650 usb2_get_page(temp->pc, buf_offset, &buf_res); 1651 td->qtd_buffer[0] = 1652 htoehci32(temp->sc, buf_res.physaddr); 1653 td->qtd_buffer_hi[0] = 0; 1654 1655 x = 1; 1656 1657 while (average > EHCI_PAGE_SIZE) { 1658 average -= EHCI_PAGE_SIZE; 1659 buf_offset += EHCI_PAGE_SIZE; 1660 usb2_get_page(temp->pc, buf_offset, &buf_res); 1661 td->qtd_buffer[x] = 1662 htoehci32(temp->sc, 1663 buf_res.physaddr & (~0xFFF)); 1664 td->qtd_buffer_hi[x] = 0; 1665 x++; 1666 } 1667 1668 /* 1669 * NOTE: The "average" variable is never zero after 1670 * exiting the loop above ! 1671 * 1672 * NOTE: We have to subtract one from the offset to 1673 * ensure that we are computing the physical address 1674 * of a valid page ! 1675 */ 1676 buf_offset += average; 1677 usb2_get_page(temp->pc, buf_offset - 1, &buf_res); 1678 td->qtd_buffer[x] = 1679 htoehci32(temp->sc, 1680 buf_res.physaddr & (~0xFFF)); 1681 td->qtd_buffer_hi[x] = 0; 1682 } 1683 1684 if (td_next) { 1685 /* link the current TD with the next one */ 1686 td->qtd_next = td_next->qtd_self; 1687 } 1688 td->qtd_altnext = qtd_altnext; 1689 td->alt_next = td_alt_next; 1690 1691 usb2_pc_cpu_flush(td->page_cache); 1692 } 1693 1694 if (precompute) { 1695 precompute = 0; 1696 1697 /* setup alt next pointer, if any */ 1698 if (temp->short_frames_ok) { 1699 if (temp->setup_alt_next) { 1700 td_alt_next = td_next; 1701 qtd_altnext = td_next->qtd_self; 1702 } 1703 } else { 1704 /* we use this field internally */ 1705 td_alt_next = td_next; 1706 } 1707 1708 /* restore */ 1709 temp->shortpkt = shortpkt_old; 1710 temp->len = len_old; 1711 goto restart; 1712 } 1713 temp->td = td; 1714 temp->td_next = td_next; 1715} 1716 1717static void 1718ehci_setup_standard_chain(struct usb2_xfer *xfer, ehci_qh_t **qh_last) 1719{ 1720 struct ehci_std_temp temp; 1721 struct usb2_pipe_methods *methods; 1722 ehci_qh_t *qh; 1723 ehci_qtd_t *td; 1724 uint32_t qh_endp; 1725 uint32_t qh_endphub; 1726 uint32_t x; 1727 1728 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1729 xfer->address, UE_GET_ADDR(xfer->endpoint), 1730 xfer->sumlen, usb2_get_speed(xfer->xroot->udev)); 1731 1732 temp.average = xfer->max_usb2_frame_size; 1733 temp.max_frame_size = xfer->max_frame_size; 1734 temp.sc = EHCI_BUS2SC(xfer->xroot->bus); 1735 1736 /* toggle the DMA set we are using */ 1737 xfer->flags_int.curr_dma_set ^= 1; 1738 1739 /* get next DMA set */ 1740 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1741 1742 xfer->td_transfer_first = td; 1743 xfer->td_transfer_cache = td; 1744 1745 temp.td = NULL; 1746 temp.td_next = td; 1747 temp.qtd_status = 0; 1748 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1749 temp.short_frames_ok = xfer->flags_int.short_frames_ok; 1750 1751 if (xfer->flags_int.control_xfr) { 1752 if (xfer->pipe->toggle_next) { 1753 /* DATA1 is next */ 1754 temp.qtd_status |= 1755 htoehci32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1756 } 1757 temp.auto_data_toggle = 0; 1758 } else { 1759 temp.auto_data_toggle = 1; 1760 } 1761 1762 if (usb2_get_speed(xfer->xroot->udev) != USB_SPEED_HIGH) { 1763 /* max 3 retries */ 1764 temp.qtd_status |= 1765 htoehci32(temp.sc, EHCI_QTD_SET_CERR(3)); 1766 } 1767 /* check if we should prepend a setup message */ 1768 1769 if (xfer->flags_int.control_xfr) { 1770 if (xfer->flags_int.control_hdr) { 1771 1772 temp.qtd_status &= 1773 htoehci32(temp.sc, EHCI_QTD_SET_CERR(3)); 1774 temp.qtd_status |= htole32 1775 (EHCI_QTD_ACTIVE | 1776 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 1777 EHCI_QTD_SET_TOGGLE(0)); 1778 1779 temp.len = xfer->frlengths[0]; 1780 temp.pc = xfer->frbuffers + 0; 1781 temp.shortpkt = temp.len ? 1 : 0; 1782 1783 ehci_setup_standard_chain_sub(&temp); 1784 } 1785 x = 1; 1786 } else { 1787 x = 0; 1788 } 1789 1790 while (x != xfer->nframes) { 1791 1792 /* DATA0 / DATA1 message */ 1793 1794 temp.len = xfer->frlengths[x]; 1795 temp.pc = xfer->frbuffers + x; 1796 1797 x++; 1798 1799 if (x == xfer->nframes) { 1800 temp.setup_alt_next = 0; 1801 } 1802 /* keep previous data toggle and error count */ 1803 1804 temp.qtd_status &= 1805 htoehci32(temp.sc, EHCI_QTD_SET_CERR(3) | 1806 EHCI_QTD_SET_TOGGLE(1)); 1807 1808 if (temp.len == 0) { 1809 1810 /* make sure that we send an USB packet */ 1811 1812 temp.shortpkt = 0; 1813 1814 } else { 1815 1816 /* regular data transfer */ 1817 1818 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1819 } 1820 1821 /* set endpoint direction */ 1822 1823 temp.qtd_status |= 1824 (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) ? 1825 htoehci32(temp.sc, EHCI_QTD_ACTIVE | 1826 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) : 1827 htoehci32(temp.sc, EHCI_QTD_ACTIVE | 1828 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT)); 1829 1830 ehci_setup_standard_chain_sub(&temp); 1831 } 1832 1833 /* check if we should append a status stage */ 1834 1835 if (xfer->flags_int.control_xfr && 1836 !xfer->flags_int.control_act) { 1837 1838 /* 1839 * Send a DATA1 message and invert the current endpoint 1840 * direction. 1841 */ 1842 1843 temp.qtd_status &= htoehci32(temp.sc, EHCI_QTD_SET_CERR(3) | 1844 EHCI_QTD_SET_TOGGLE(1)); 1845 temp.qtd_status |= 1846 (UE_GET_DIR(xfer->endpoint) == UE_DIR_OUT) ? 1847 htoehci32(temp.sc, EHCI_QTD_ACTIVE | 1848 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) | 1849 EHCI_QTD_SET_TOGGLE(1)) : 1850 htoehci32(temp.sc, EHCI_QTD_ACTIVE | 1851 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) | 1852 EHCI_QTD_SET_TOGGLE(1)); 1853 1854 temp.len = 0; 1855 temp.pc = NULL; 1856 temp.shortpkt = 0; 1857 1858 ehci_setup_standard_chain_sub(&temp); 1859 } 1860 td = temp.td; 1861 1862 /* the last TD terminates the transfer: */ 1863 td->qtd_next = htoehci32(temp.sc, EHCI_LINK_TERMINATE); 1864 td->qtd_altnext = htoehci32(temp.sc, EHCI_LINK_TERMINATE); 1865 td->qtd_status |= htoehci32(temp.sc, EHCI_QTD_IOC); 1866 1867 usb2_pc_cpu_flush(td->page_cache); 1868 1869 /* must have at least one frame! */ 1870 1871 xfer->td_transfer_last = td; 1872 1873#if USB_DEBUG 1874 if (ehcidebug > 8) { 1875 DPRINTF("nexttog=%d; data before transfer:\n", 1876 xfer->pipe->toggle_next); 1877 ehci_dump_sqtds(temp.sc, 1878 xfer->td_transfer_first); 1879 } 1880#endif 1881 1882 methods = xfer->pipe->methods; 1883 1884 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1885 1886 /* the "qh_link" field is filled when the QH is added */ 1887 1888 qh_endp = 1889 (EHCI_QH_SET_ADDR(xfer->address) | 1890 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpoint)) | 1891 EHCI_QH_SET_MPL(xfer->max_packet_size)); 1892 1893 if (usb2_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 1894 qh_endp |= (EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | 1895 EHCI_QH_DTC); 1896 if (methods != &ehci_device_intr_methods) 1897 qh_endp |= EHCI_QH_SET_NRL(8); 1898 } else { 1899 1900 if (usb2_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) { 1901 qh_endp |= (EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL) | 1902 EHCI_QH_DTC); 1903 } else { 1904 qh_endp |= (EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW) | 1905 EHCI_QH_DTC); 1906 } 1907 1908 if (methods == &ehci_device_ctrl_methods) { 1909 qh_endp |= EHCI_QH_CTL; 1910 } 1911 if (methods != &ehci_device_intr_methods) { 1912 /* Only try one time per microframe! */ 1913 qh_endp |= EHCI_QH_SET_NRL(1); 1914 } 1915 } 1916 1917 qh->qh_endp = htoehci32(temp.sc, qh_endp); 1918 1919 qh_endphub = 1920 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) | 1921 EHCI_QH_SET_CMASK(xfer->usb2_cmask) | 1922 EHCI_QH_SET_SMASK(xfer->usb2_smask) | 1923 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 1924 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no)); 1925 1926 qh->qh_endphub = htoehci32(temp.sc, qh_endphub); 1927 qh->qh_curqtd = htoehci32(temp.sc, 0); 1928 1929 /* fill the overlay qTD */ 1930 qh->qh_qtd.qtd_status = htoehci32(temp.sc, 0); 1931 1932 if (temp.auto_data_toggle) { 1933 1934 /* let the hardware compute the data toggle */ 1935 1936 qh->qh_endp &= htoehci32(temp.sc, ~EHCI_QH_DTC); 1937 1938 if (xfer->pipe->toggle_next) { 1939 /* DATA1 is next */ 1940 qh->qh_qtd.qtd_status |= 1941 htoehci32(temp.sc, EHCI_QTD_SET_TOGGLE(1)); 1942 } 1943 } 1944 td = xfer->td_transfer_first; 1945 1946 qh->qh_qtd.qtd_next = td->qtd_self; 1947 qh->qh_qtd.qtd_altnext = 1948 htoehci32(temp.sc, EHCI_LINK_TERMINATE); 1949 1950 usb2_pc_cpu_flush(qh->page_cache); 1951 1952 if (xfer->xroot->udev->pwr_save.suspended == 0) { 1953 EHCI_APPEND_QH(qh, *qh_last); 1954 } 1955} 1956 1957static void 1958ehci_root_intr_done(struct usb2_xfer *xfer, 1959 struct usb2_sw_transfer *std) 1960{ 1961 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 1962 uint16_t i; 1963 uint16_t m; 1964 1965 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1966 1967 if (std->state != USB_SW_TR_PRE_DATA) { 1968 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1969 /* transfer transferred */ 1970 ehci_device_done(xfer, std->err); 1971 } 1972 goto done; 1973 } 1974 /* setup buffer */ 1975 std->ptr = sc->sc_hub_idata; 1976 std->len = sizeof(sc->sc_hub_idata); 1977 1978 /* clear any old interrupt data */ 1979 bzero(sc->sc_hub_idata, sizeof(sc->sc_hub_idata)); 1980 1981 /* set bits */ 1982 m = (sc->sc_noport + 1); 1983 if (m > (8 * sizeof(sc->sc_hub_idata))) { 1984 m = (8 * sizeof(sc->sc_hub_idata)); 1985 } 1986 for (i = 1; i < m; i++) { 1987 /* pick out CHANGE bits from the status register */ 1988 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) { 1989 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 1990 DPRINTF("port %d changed\n", i); 1991 } 1992 } 1993done: 1994 return; 1995} 1996 1997static void 1998ehci_isoc_fs_done(ehci_softc_t *sc, struct usb2_xfer *xfer) 1999{ 2000 uint32_t nframes = xfer->nframes; 2001 uint32_t status; 2002 uint32_t *plen = xfer->frlengths; 2003 uint16_t len = 0; 2004 ehci_sitd_t *td = xfer->td_transfer_first; 2005 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos]; 2006 2007 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 2008 xfer, xfer->pipe); 2009 2010 while (nframes--) { 2011 if (td == NULL) { 2012 panic("%s:%d: out of TD's\n", 2013 __FUNCTION__, __LINE__); 2014 } 2015 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2016 pp_last = &sc->sc_isoc_fs_p_last[0]; 2017 } 2018#if USB_DEBUG 2019 if (ehcidebug > 15) { 2020 DPRINTF("isoc FS-TD\n"); 2021 ehci_dump_sitd(sc, td); 2022 } 2023#endif 2024 usb2_pc_cpu_invalidate(td->page_cache); 2025 status = ehci32toh(sc, td->sitd_status); 2026 2027 len = EHCI_SITD_GET_LEN(status); 2028 2029 if (*plen >= len) { 2030 len = *plen - len; 2031 } else { 2032 len = 0; 2033 } 2034 2035 *plen = len; 2036 2037 /* remove FS-TD from schedule */ 2038 EHCI_REMOVE_FS_TD(td, *pp_last); 2039 2040 pp_last++; 2041 plen++; 2042 td = td->obj_next; 2043 } 2044 2045 xfer->aframes = xfer->nframes; 2046} 2047 2048static void 2049ehci_isoc_hs_done(ehci_softc_t *sc, struct usb2_xfer *xfer) 2050{ 2051 uint32_t nframes = xfer->nframes; 2052 uint32_t status; 2053 uint32_t *plen = xfer->frlengths; 2054 uint16_t len = 0; 2055 uint8_t td_no = 0; 2056 ehci_itd_t *td = xfer->td_transfer_first; 2057 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos]; 2058 2059 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 2060 xfer, xfer->pipe); 2061 2062 while (nframes--) { 2063 if (td == NULL) { 2064 panic("%s:%d: out of TD's\n", 2065 __FUNCTION__, __LINE__); 2066 } 2067 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2068 pp_last = &sc->sc_isoc_hs_p_last[0]; 2069 } 2070#if USB_DEBUG 2071 if (ehcidebug > 15) { 2072 DPRINTF("isoc HS-TD\n"); 2073 ehci_dump_itd(sc, td); 2074 } 2075#endif 2076 2077 usb2_pc_cpu_invalidate(td->page_cache); 2078 status = ehci32toh(sc, td->itd_status[td_no]); 2079 2080 len = EHCI_ITD_GET_LEN(status); 2081 2082 if (*plen >= len) { 2083 /* 2084 * The length is valid. NOTE: The complete 2085 * length is written back into the status 2086 * field, and not the remainder like with 2087 * other transfer descriptor types. 2088 */ 2089 } else { 2090 /* Invalid length - truncate */ 2091 len = 0; 2092 } 2093 2094 *plen = len; 2095 2096 plen++; 2097 td_no++; 2098 2099 if ((td_no == 8) || (nframes == 0)) { 2100 /* remove HS-TD from schedule */ 2101 EHCI_REMOVE_HS_TD(td, *pp_last); 2102 pp_last++; 2103 2104 td_no = 0; 2105 td = td->obj_next; 2106 } 2107 } 2108 xfer->aframes = xfer->nframes; 2109} 2110 2111/* NOTE: "done" can be run two times in a row, 2112 * from close and from interrupt 2113 */ 2114static void 2115ehci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 2116{ 2117 struct usb2_pipe_methods *methods = xfer->pipe->methods; 2118 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2119 2120 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2121 2122 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 2123 xfer, xfer->pipe, error); 2124 2125 if ((methods == &ehci_device_bulk_methods) || 2126 (methods == &ehci_device_ctrl_methods)) { 2127#if USB_DEBUG 2128 if (ehcidebug > 8) { 2129 DPRINTF("nexttog=%d; data after transfer:\n", 2130 xfer->pipe->toggle_next); 2131 ehci_dump_sqtds(sc, 2132 xfer->td_transfer_first); 2133 } 2134#endif 2135 2136 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2137 sc->sc_async_p_last); 2138 } 2139 if (methods == &ehci_device_intr_methods) { 2140 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2141 sc->sc_intr_p_last[xfer->qh_pos]); 2142 } 2143 /* 2144 * Only finish isochronous transfers once which will update 2145 * "xfer->frlengths". 2146 */ 2147 if (xfer->td_transfer_first && 2148 xfer->td_transfer_last) { 2149 if (methods == &ehci_device_isoc_fs_methods) { 2150 ehci_isoc_fs_done(sc, xfer); 2151 } 2152 if (methods == &ehci_device_isoc_hs_methods) { 2153 ehci_isoc_hs_done(sc, xfer); 2154 } 2155 xfer->td_transfer_first = NULL; 2156 xfer->td_transfer_last = NULL; 2157 } 2158 /* dequeue transfer and start next transfer */ 2159 usb2_transfer_done(xfer, error); 2160} 2161 2162/*------------------------------------------------------------------------* 2163 * ehci bulk support 2164 *------------------------------------------------------------------------*/ 2165static void 2166ehci_device_bulk_open(struct usb2_xfer *xfer) 2167{ 2168 return; 2169} 2170 2171static void 2172ehci_device_bulk_close(struct usb2_xfer *xfer) 2173{ 2174 ehci_device_done(xfer, USB_ERR_CANCELLED); 2175} 2176 2177static void 2178ehci_device_bulk_enter(struct usb2_xfer *xfer) 2179{ 2180 return; 2181} 2182 2183static void 2184ehci_device_bulk_start(struct usb2_xfer *xfer) 2185{ 2186 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2187 2188 /* setup TD's and QH */ 2189 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2190 2191 /* put transfer on interrupt queue */ 2192 ehci_transfer_intr_enqueue(xfer); 2193} 2194 2195struct usb2_pipe_methods ehci_device_bulk_methods = 2196{ 2197 .open = ehci_device_bulk_open, 2198 .close = ehci_device_bulk_close, 2199 .enter = ehci_device_bulk_enter, 2200 .start = ehci_device_bulk_start, 2201 .enter_is_cancelable = 1, 2202 .start_is_cancelable = 1, 2203}; 2204 2205/*------------------------------------------------------------------------* 2206 * ehci control support 2207 *------------------------------------------------------------------------*/ 2208static void 2209ehci_device_ctrl_open(struct usb2_xfer *xfer) 2210{ 2211 return; 2212} 2213 2214static void 2215ehci_device_ctrl_close(struct usb2_xfer *xfer) 2216{ 2217 ehci_device_done(xfer, USB_ERR_CANCELLED); 2218} 2219 2220static void 2221ehci_device_ctrl_enter(struct usb2_xfer *xfer) 2222{ 2223 return; 2224} 2225 2226static void 2227ehci_device_ctrl_start(struct usb2_xfer *xfer) 2228{ 2229 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2230 2231 /* setup TD's and QH */ 2232 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2233 2234 /* put transfer on interrupt queue */ 2235 ehci_transfer_intr_enqueue(xfer); 2236} 2237 2238struct usb2_pipe_methods ehci_device_ctrl_methods = 2239{ 2240 .open = ehci_device_ctrl_open, 2241 .close = ehci_device_ctrl_close, 2242 .enter = ehci_device_ctrl_enter, 2243 .start = ehci_device_ctrl_start, 2244 .enter_is_cancelable = 1, 2245 .start_is_cancelable = 1, 2246}; 2247 2248/*------------------------------------------------------------------------* 2249 * ehci interrupt support 2250 *------------------------------------------------------------------------*/ 2251static void 2252ehci_device_intr_open(struct usb2_xfer *xfer) 2253{ 2254 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2255 uint16_t best; 2256 uint16_t bit; 2257 uint16_t x; 2258 uint8_t slot; 2259 2260 /* Allocate a microframe slot first: */ 2261 2262 slot = usb2_intr_schedule_adjust 2263 (xfer->xroot->udev, xfer->max_frame_size, USB_HS_MICRO_FRAMES_MAX); 2264 2265 if (usb2_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) { 2266 xfer->usb2_uframe = slot; 2267 xfer->usb2_smask = (1 << slot) & 0xFF; 2268 xfer->usb2_cmask = 0; 2269 } else { 2270 xfer->usb2_uframe = slot; 2271 xfer->usb2_smask = (1 << slot) & 0x3F; 2272 xfer->usb2_cmask = (-(4 << slot)) & 0xFE; 2273 } 2274 2275 /* 2276 * Find the best QH position corresponding to the given interval: 2277 */ 2278 2279 best = 0; 2280 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 2281 while (bit) { 2282 if (xfer->interval >= bit) { 2283 x = bit; 2284 best = bit; 2285 while (x & bit) { 2286 if (sc->sc_intr_stat[x] < 2287 sc->sc_intr_stat[best]) { 2288 best = x; 2289 } 2290 x++; 2291 } 2292 break; 2293 } 2294 bit >>= 1; 2295 } 2296 2297 sc->sc_intr_stat[best]++; 2298 xfer->qh_pos = best; 2299 2300 DPRINTFN(3, "best=%d interval=%d\n", 2301 best, xfer->interval); 2302} 2303 2304static void 2305ehci_device_intr_close(struct usb2_xfer *xfer) 2306{ 2307 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2308 uint8_t slot; 2309 2310 slot = usb2_intr_schedule_adjust 2311 (xfer->xroot->udev, -(xfer->max_frame_size), xfer->usb2_uframe); 2312 2313 sc->sc_intr_stat[xfer->qh_pos]--; 2314 2315 ehci_device_done(xfer, USB_ERR_CANCELLED); 2316} 2317 2318static void 2319ehci_device_intr_enter(struct usb2_xfer *xfer) 2320{ 2321 return; 2322} 2323 2324static void 2325ehci_device_intr_start(struct usb2_xfer *xfer) 2326{ 2327 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2328 2329 /* setup TD's and QH */ 2330 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 2331 2332 /* put transfer on interrupt queue */ 2333 ehci_transfer_intr_enqueue(xfer); 2334} 2335 2336struct usb2_pipe_methods ehci_device_intr_methods = 2337{ 2338 .open = ehci_device_intr_open, 2339 .close = ehci_device_intr_close, 2340 .enter = ehci_device_intr_enter, 2341 .start = ehci_device_intr_start, 2342 .enter_is_cancelable = 1, 2343 .start_is_cancelable = 1, 2344}; 2345 2346/*------------------------------------------------------------------------* 2347 * ehci full speed isochronous support 2348 *------------------------------------------------------------------------*/ 2349static void 2350ehci_device_isoc_fs_open(struct usb2_xfer *xfer) 2351{ 2352 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2353 ehci_sitd_t *td; 2354 uint32_t sitd_portaddr; 2355 uint8_t ds; 2356 2357 sitd_portaddr = 2358 EHCI_SITD_SET_ADDR(xfer->address) | 2359 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpoint)) | 2360 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) | 2361 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no); 2362 2363 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 2364 sitd_portaddr |= EHCI_SITD_SET_DIR_IN; 2365 } 2366 sitd_portaddr = htoehci32(sc, sitd_portaddr); 2367 2368 /* initialize all TD's */ 2369 2370 for (ds = 0; ds != 2; ds++) { 2371 2372 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2373 2374 td->sitd_portaddr = sitd_portaddr; 2375 2376 /* 2377 * TODO: make some kind of automatic 2378 * SMASK/CMASK selection based on micro-frame 2379 * usage 2380 * 2381 * micro-frame usage (8 microframes per 1ms) 2382 */ 2383 td->sitd_back = htoehci32(sc, EHCI_LINK_TERMINATE); 2384 2385 usb2_pc_cpu_flush(td->page_cache); 2386 } 2387 } 2388} 2389 2390static void 2391ehci_device_isoc_fs_close(struct usb2_xfer *xfer) 2392{ 2393 ehci_device_done(xfer, USB_ERR_CANCELLED); 2394} 2395 2396static void 2397ehci_device_isoc_fs_enter(struct usb2_xfer *xfer) 2398{ 2399 struct usb2_page_search buf_res; 2400 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2401 struct usb2_fs_isoc_schedule *fss_start; 2402 struct usb2_fs_isoc_schedule *fss_end; 2403 struct usb2_fs_isoc_schedule *fss; 2404 ehci_sitd_t *td; 2405 ehci_sitd_t *td_last = NULL; 2406 ehci_sitd_t **pp_last; 2407 uint32_t *plen; 2408 uint32_t buf_offset; 2409 uint32_t nframes; 2410 uint32_t temp; 2411 uint32_t sitd_mask; 2412 uint16_t tlen; 2413 uint8_t sa; 2414 uint8_t sb; 2415 uint8_t error; 2416 2417#if USB_DEBUG 2418 uint8_t once = 1; 2419 2420#endif 2421 2422 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2423 xfer, xfer->pipe->isoc_next, xfer->nframes); 2424 2425 /* get the current frame index */ 2426 2427 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2428 2429 /* 2430 * check if the frame index is within the window where the frames 2431 * will be inserted 2432 */ 2433 buf_offset = (nframes - xfer->pipe->isoc_next) & 2434 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2435 2436 if ((xfer->pipe->is_synced == 0) || 2437 (buf_offset < xfer->nframes)) { 2438 /* 2439 * If there is data underflow or the pipe queue is empty we 2440 * schedule the transfer a few frames ahead of the current 2441 * frame position. Else two isochronous transfers might 2442 * overlap. 2443 */ 2444 xfer->pipe->isoc_next = (nframes + 3) & 2445 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2446 xfer->pipe->is_synced = 1; 2447 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 2448 } 2449 /* 2450 * compute how many milliseconds the insertion is ahead of the 2451 * current frame position: 2452 */ 2453 buf_offset = (xfer->pipe->isoc_next - nframes) & 2454 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2455 2456 /* 2457 * pre-compute when the isochronous transfer will be finished: 2458 */ 2459 xfer->isoc_time_complete = 2460 usb2_fs_isoc_schedule_isoc_time_expand 2461 (xfer->xroot->udev, &fss_start, &fss_end, nframes) + buf_offset + 2462 xfer->nframes; 2463 2464 /* get the real number of frames */ 2465 2466 nframes = xfer->nframes; 2467 2468 buf_offset = 0; 2469 2470 plen = xfer->frlengths; 2471 2472 /* toggle the DMA set we are using */ 2473 xfer->flags_int.curr_dma_set ^= 1; 2474 2475 /* get next DMA set */ 2476 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2477 xfer->td_transfer_first = td; 2478 2479 pp_last = &sc->sc_isoc_fs_p_last[xfer->pipe->isoc_next]; 2480 2481 /* store starting position */ 2482 2483 xfer->qh_pos = xfer->pipe->isoc_next; 2484 2485 fss = fss_start + (xfer->qh_pos % USB_ISOC_TIME_MAX); 2486 2487 while (nframes--) { 2488 if (td == NULL) { 2489 panic("%s:%d: out of TD's\n", 2490 __FUNCTION__, __LINE__); 2491 } 2492 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2493 pp_last = &sc->sc_isoc_fs_p_last[0]; 2494 } 2495 if (fss >= fss_end) { 2496 fss = fss_start; 2497 } 2498 /* reuse sitd_portaddr and sitd_back from last transfer */ 2499 2500 if (*plen > xfer->max_frame_size) { 2501#if USB_DEBUG 2502 if (once) { 2503 once = 0; 2504 printf("%s: frame length(%d) exceeds %d " 2505 "bytes (frame truncated)\n", 2506 __FUNCTION__, *plen, 2507 xfer->max_frame_size); 2508 } 2509#endif 2510 *plen = xfer->max_frame_size; 2511 } 2512 /* 2513 * We currently don't care if the ISOCHRONOUS schedule is 2514 * full! 2515 */ 2516 error = usb2_fs_isoc_schedule_alloc(fss, &sa, *plen); 2517 if (error) { 2518 /* 2519 * The FULL speed schedule is FULL! Set length 2520 * to zero. 2521 */ 2522 *plen = 0; 2523 } 2524 if (*plen) { 2525 /* 2526 * only call "usb2_get_page()" when we have a 2527 * non-zero length 2528 */ 2529 usb2_get_page(xfer->frbuffers, buf_offset, &buf_res); 2530 td->sitd_bp[0] = htoehci32(sc, buf_res.physaddr); 2531 buf_offset += *plen; 2532 /* 2533 * NOTE: We need to subtract one from the offset so 2534 * that we are on a valid page! 2535 */ 2536 usb2_get_page(xfer->frbuffers, buf_offset - 1, 2537 &buf_res); 2538 temp = buf_res.physaddr & ~0xFFF; 2539 } else { 2540 td->sitd_bp[0] = 0; 2541 temp = 0; 2542 } 2543 2544 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_OUT) { 2545 tlen = *plen; 2546 if (tlen <= 188) { 2547 temp |= 1; /* T-count = 1, TP = ALL */ 2548 tlen = 1; 2549 } else { 2550 tlen += 187; 2551 tlen /= 188; 2552 temp |= tlen; /* T-count = [1..6] */ 2553 temp |= 8; /* TP = Begin */ 2554 } 2555 2556 tlen += sa; 2557 2558 if (tlen >= 8) { 2559 sb = 0; 2560 } else { 2561 sb = (1 << tlen); 2562 } 2563 2564 sa = (1 << sa); 2565 sa = (sb - sa) & 0x3F; 2566 sb = 0; 2567 } else { 2568 sb = (-(4 << sa)) & 0xFE; 2569 sa = (1 << sa) & 0x3F; 2570 } 2571 2572 sitd_mask = (EHCI_SITD_SET_SMASK(sa) | 2573 EHCI_SITD_SET_CMASK(sb)); 2574 2575 td->sitd_bp[1] = htoehci32(sc, temp); 2576 2577 td->sitd_mask = htoehci32(sc, sitd_mask); 2578 2579 if (nframes == 0) { 2580 td->sitd_status = htole32 2581 (EHCI_SITD_IOC | 2582 EHCI_SITD_ACTIVE | 2583 EHCI_SITD_SET_LEN(*plen)); 2584 } else { 2585 td->sitd_status = htole32 2586 (EHCI_SITD_ACTIVE | 2587 EHCI_SITD_SET_LEN(*plen)); 2588 } 2589 usb2_pc_cpu_flush(td->page_cache); 2590 2591#if USB_DEBUG 2592 if (ehcidebug > 15) { 2593 DPRINTF("FS-TD %d\n", nframes); 2594 ehci_dump_sitd(sc, td); 2595 } 2596#endif 2597 /* insert TD into schedule */ 2598 EHCI_APPEND_FS_TD(td, *pp_last); 2599 pp_last++; 2600 2601 plen++; 2602 fss++; 2603 td_last = td; 2604 td = td->obj_next; 2605 } 2606 2607 xfer->td_transfer_last = td_last; 2608 2609 /* update isoc_next */ 2610 xfer->pipe->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) & 2611 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2612} 2613 2614static void 2615ehci_device_isoc_fs_start(struct usb2_xfer *xfer) 2616{ 2617 /* put transfer on interrupt queue */ 2618 ehci_transfer_intr_enqueue(xfer); 2619} 2620 2621struct usb2_pipe_methods ehci_device_isoc_fs_methods = 2622{ 2623 .open = ehci_device_isoc_fs_open, 2624 .close = ehci_device_isoc_fs_close, 2625 .enter = ehci_device_isoc_fs_enter, 2626 .start = ehci_device_isoc_fs_start, 2627 .enter_is_cancelable = 1, 2628 .start_is_cancelable = 1, 2629}; 2630 2631/*------------------------------------------------------------------------* 2632 * ehci high speed isochronous support 2633 *------------------------------------------------------------------------*/ 2634static void 2635ehci_device_isoc_hs_open(struct usb2_xfer *xfer) 2636{ 2637 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2638 ehci_itd_t *td; 2639 uint32_t temp; 2640 uint8_t ds; 2641 2642 /* initialize all TD's */ 2643 2644 for (ds = 0; ds != 2; ds++) { 2645 2646 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2647 2648 /* set TD inactive */ 2649 td->itd_status[0] = 0; 2650 td->itd_status[1] = 0; 2651 td->itd_status[2] = 0; 2652 td->itd_status[3] = 0; 2653 td->itd_status[4] = 0; 2654 td->itd_status[5] = 0; 2655 td->itd_status[6] = 0; 2656 td->itd_status[7] = 0; 2657 2658 /* set endpoint and address */ 2659 td->itd_bp[0] = htole32 2660 (EHCI_ITD_SET_ADDR(xfer->address) | 2661 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpoint))); 2662 2663 temp = 2664 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF); 2665 2666 /* set direction */ 2667 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 2668 temp |= EHCI_ITD_SET_DIR_IN; 2669 } 2670 /* set maximum packet size */ 2671 td->itd_bp[1] = htoehci32(sc, temp); 2672 2673 /* set transfer multiplier */ 2674 td->itd_bp[2] = htoehci32(sc, xfer->max_packet_count & 3); 2675 2676 usb2_pc_cpu_flush(td->page_cache); 2677 } 2678 } 2679} 2680 2681static void 2682ehci_device_isoc_hs_close(struct usb2_xfer *xfer) 2683{ 2684 ehci_device_done(xfer, USB_ERR_CANCELLED); 2685} 2686 2687static void 2688ehci_device_isoc_hs_enter(struct usb2_xfer *xfer) 2689{ 2690 struct usb2_page_search buf_res; 2691 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2692 ehci_itd_t *td; 2693 ehci_itd_t *td_last = NULL; 2694 ehci_itd_t **pp_last; 2695 bus_size_t page_addr; 2696 uint32_t *plen; 2697 uint32_t status; 2698 uint32_t buf_offset; 2699 uint32_t nframes; 2700 uint32_t itd_offset[8 + 1]; 2701 uint8_t x; 2702 uint8_t td_no; 2703 uint8_t page_no; 2704 2705#if USB_DEBUG 2706 uint8_t once = 1; 2707 2708#endif 2709 2710 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2711 xfer, xfer->pipe->isoc_next, xfer->nframes); 2712 2713 /* get the current frame index */ 2714 2715 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2716 2717 /* 2718 * check if the frame index is within the window where the frames 2719 * will be inserted 2720 */ 2721 buf_offset = (nframes - xfer->pipe->isoc_next) & 2722 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2723 2724 if ((xfer->pipe->is_synced == 0) || 2725 (buf_offset < ((xfer->nframes + 7) / 8))) { 2726 /* 2727 * If there is data underflow or the pipe queue is empty we 2728 * schedule the transfer a few frames ahead of the current 2729 * frame position. Else two isochronous transfers might 2730 * overlap. 2731 */ 2732 xfer->pipe->isoc_next = (nframes + 3) & 2733 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2734 xfer->pipe->is_synced = 1; 2735 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 2736 } 2737 /* 2738 * compute how many milliseconds the insertion is ahead of the 2739 * current frame position: 2740 */ 2741 buf_offset = (xfer->pipe->isoc_next - nframes) & 2742 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2743 2744 /* 2745 * pre-compute when the isochronous transfer will be finished: 2746 */ 2747 xfer->isoc_time_complete = 2748 usb2_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 2749 ((xfer->nframes + 7) / 8); 2750 2751 /* get the real number of frames */ 2752 2753 nframes = xfer->nframes; 2754 2755 buf_offset = 0; 2756 td_no = 0; 2757 2758 plen = xfer->frlengths; 2759 2760 /* toggle the DMA set we are using */ 2761 xfer->flags_int.curr_dma_set ^= 1; 2762 2763 /* get next DMA set */ 2764 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2765 xfer->td_transfer_first = td; 2766 2767 pp_last = &sc->sc_isoc_hs_p_last[xfer->pipe->isoc_next]; 2768 2769 /* store starting position */ 2770 2771 xfer->qh_pos = xfer->pipe->isoc_next; 2772 2773 while (nframes--) { 2774 if (td == NULL) { 2775 panic("%s:%d: out of TD's\n", 2776 __FUNCTION__, __LINE__); 2777 } 2778 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2779 pp_last = &sc->sc_isoc_hs_p_last[0]; 2780 } 2781 /* range check */ 2782 if (*plen > xfer->max_frame_size) { 2783#if USB_DEBUG 2784 if (once) { 2785 once = 0; 2786 printf("%s: frame length(%d) exceeds %d bytes " 2787 "(frame truncated)\n", 2788 __FUNCTION__, *plen, xfer->max_frame_size); 2789 } 2790#endif 2791 *plen = xfer->max_frame_size; 2792 } 2793 status = (EHCI_ITD_SET_LEN(*plen) | 2794 EHCI_ITD_ACTIVE | 2795 EHCI_ITD_SET_PG(0)); 2796 td->itd_status[td_no] = htoehci32(sc, status); 2797 itd_offset[td_no] = buf_offset; 2798 buf_offset += *plen; 2799 plen++; 2800 td_no++; 2801 2802 if ((td_no == 8) || (nframes == 0)) { 2803 2804 /* the rest of the transfers are not active, if any */ 2805 for (x = td_no; x != 8; x++) { 2806 td->itd_status[x] = 0; /* not active */ 2807 } 2808 2809 /* check if there is any data to be transferred */ 2810 if (itd_offset[0] != buf_offset) { 2811 page_no = 0; 2812 itd_offset[td_no] = buf_offset; 2813 2814 /* get first page offset */ 2815 usb2_get_page(xfer->frbuffers, itd_offset[0], &buf_res); 2816 /* get page address */ 2817 page_addr = buf_res.physaddr & ~0xFFF; 2818 /* update page address */ 2819 td->itd_bp[0] &= htoehci32(sc, 0xFFF); 2820 td->itd_bp[0] |= htoehci32(sc, page_addr); 2821 2822 for (x = 0; x != td_no; x++) { 2823 /* set page number and page offset */ 2824 status = (EHCI_ITD_SET_PG(page_no) | 2825 (buf_res.physaddr & 0xFFF)); 2826 td->itd_status[x] |= htoehci32(sc, status); 2827 2828 /* get next page offset */ 2829 if (itd_offset[x + 1] == buf_offset) { 2830 /* 2831 * We subtract one so that 2832 * we don't go off the last 2833 * page! 2834 */ 2835 usb2_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 2836 } else { 2837 usb2_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res); 2838 } 2839 2840 /* check if we need a new page */ 2841 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) { 2842 /* new page needed */ 2843 page_addr = buf_res.physaddr & ~0xFFF; 2844 if (page_no == 6) { 2845 panic("%s: too many pages\n", __FUNCTION__); 2846 } 2847 page_no++; 2848 /* update page address */ 2849 td->itd_bp[page_no] &= htoehci32(sc, 0xFFF); 2850 td->itd_bp[page_no] |= htoehci32(sc, page_addr); 2851 } 2852 } 2853 } 2854 /* set IOC bit if we are complete */ 2855 if (nframes == 0) { 2856 td->itd_status[7] |= htoehci32(sc, EHCI_ITD_IOC); 2857 } 2858 usb2_pc_cpu_flush(td->page_cache); 2859#if USB_DEBUG 2860 if (ehcidebug > 15) { 2861 DPRINTF("HS-TD %d\n", nframes); 2862 ehci_dump_itd(sc, td); 2863 } 2864#endif 2865 /* insert TD into schedule */ 2866 EHCI_APPEND_HS_TD(td, *pp_last); 2867 pp_last++; 2868 2869 td_no = 0; 2870 td_last = td; 2871 td = td->obj_next; 2872 } 2873 } 2874 2875 xfer->td_transfer_last = td_last; 2876 2877 /* update isoc_next */ 2878 xfer->pipe->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) & 2879 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2880} 2881 2882static void 2883ehci_device_isoc_hs_start(struct usb2_xfer *xfer) 2884{ 2885 /* put transfer on interrupt queue */ 2886 ehci_transfer_intr_enqueue(xfer); 2887} 2888 2889struct usb2_pipe_methods ehci_device_isoc_hs_methods = 2890{ 2891 .open = ehci_device_isoc_hs_open, 2892 .close = ehci_device_isoc_hs_close, 2893 .enter = ehci_device_isoc_hs_enter, 2894 .start = ehci_device_isoc_hs_start, 2895 .enter_is_cancelable = 1, 2896 .start_is_cancelable = 1, 2897}; 2898 2899/*------------------------------------------------------------------------* 2900 * ehci root control support 2901 *------------------------------------------------------------------------* 2902 * simulate a hardware hub by handling 2903 * all the necessary requests 2904 *------------------------------------------------------------------------*/ 2905 2906static void 2907ehci_root_ctrl_open(struct usb2_xfer *xfer) 2908{ 2909 return; 2910} 2911 2912static void 2913ehci_root_ctrl_close(struct usb2_xfer *xfer) 2914{ 2915 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 2916 2917 if (sc->sc_root_ctrl.xfer == xfer) { 2918 sc->sc_root_ctrl.xfer = NULL; 2919 } 2920 ehci_device_done(xfer, USB_ERR_CANCELLED); 2921} 2922 2923/* data structures and routines 2924 * to emulate the root hub: 2925 */ 2926 2927static const 2928struct usb2_device_descriptor ehci_devd = 2929{ 2930 sizeof(struct usb2_device_descriptor), 2931 UDESC_DEVICE, /* type */ 2932 {0x00, 0x02}, /* USB version */ 2933 UDCLASS_HUB, /* class */ 2934 UDSUBCLASS_HUB, /* subclass */ 2935 UDPROTO_HSHUBSTT, /* protocol */ 2936 64, /* max packet */ 2937 {0}, {0}, {0x00, 0x01}, /* device id */ 2938 1, 2, 0, /* string indicies */ 2939 1 /* # of configurations */ 2940}; 2941 2942static const 2943struct usb2_device_qualifier ehci_odevd = 2944{ 2945 sizeof(struct usb2_device_qualifier), 2946 UDESC_DEVICE_QUALIFIER, /* type */ 2947 {0x00, 0x02}, /* USB version */ 2948 UDCLASS_HUB, /* class */ 2949 UDSUBCLASS_HUB, /* subclass */ 2950 UDPROTO_FSHUB, /* protocol */ 2951 0, /* max packet */ 2952 0, /* # of configurations */ 2953 0 2954}; 2955 2956static const struct ehci_config_desc ehci_confd = { 2957 .confd = { 2958 .bLength = sizeof(struct usb2_config_descriptor), 2959 .bDescriptorType = UDESC_CONFIG, 2960 .wTotalLength[0] = sizeof(ehci_confd), 2961 .bNumInterface = 1, 2962 .bConfigurationValue = 1, 2963 .iConfiguration = 0, 2964 .bmAttributes = UC_SELF_POWERED, 2965 .bMaxPower = 0 /* max power */ 2966 }, 2967 2968 .ifcd = { 2969 .bLength = sizeof(struct usb2_interface_descriptor), 2970 .bDescriptorType = UDESC_INTERFACE, 2971 .bNumEndpoints = 1, 2972 .bInterfaceClass = UICLASS_HUB, 2973 .bInterfaceSubClass = UISUBCLASS_HUB, 2974 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 2975 0 2976 }, 2977 2978 .endpd = { 2979 .bLength = sizeof(struct usb2_endpoint_descriptor), 2980 .bDescriptorType = UDESC_ENDPOINT, 2981 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT, 2982 .bmAttributes = UE_INTERRUPT, 2983 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 2984 .bInterval = 255, 2985 }, 2986}; 2987 2988static const 2989struct usb2_hub_descriptor ehci_hubd = 2990{ 2991 0, /* dynamic length */ 2992 UDESC_HUB, 2993 0, 2994 {0, 0}, 2995 0, 2996 0, 2997 {0}, 2998}; 2999 3000static void 3001ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed) 3002{ 3003 uint32_t port; 3004 uint32_t v; 3005 3006 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed); 3007 3008 port = EHCI_PORTSC(index); 3009 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3010 EOWRITE4(sc, port, v | EHCI_PS_PO); 3011} 3012 3013static void 3014ehci_root_ctrl_enter(struct usb2_xfer *xfer) 3015{ 3016 return; 3017} 3018 3019static void 3020ehci_root_ctrl_start(struct usb2_xfer *xfer) 3021{ 3022 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 3023 3024 DPRINTF("\n"); 3025 3026 sc->sc_root_ctrl.xfer = xfer; 3027 3028 usb2_bus_roothub_exec(xfer->xroot->bus); 3029} 3030 3031static void 3032ehci_root_ctrl_task(struct usb2_bus *bus) 3033{ 3034 ehci_root_ctrl_poll(EHCI_BUS2SC(bus)); 3035} 3036 3037static void 3038ehci_root_ctrl_done(struct usb2_xfer *xfer, 3039 struct usb2_sw_transfer *std) 3040{ 3041 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 3042 char *ptr; 3043 uint32_t port; 3044 uint32_t v; 3045 uint16_t i; 3046 uint16_t value; 3047 uint16_t index; 3048 uint8_t l; 3049 uint8_t use_polling; 3050 3051 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3052 3053 if (std->state != USB_SW_TR_SETUP) { 3054 if (std->state == USB_SW_TR_PRE_CALLBACK) { 3055 /* transfer transferred */ 3056 ehci_device_done(xfer, std->err); 3057 } 3058 goto done; 3059 } 3060 /* buffer reset */ 3061 std->ptr = sc->sc_hub_desc.temp; 3062 std->len = 0; 3063 3064 value = UGETW(std->req.wValue); 3065 index = UGETW(std->req.wIndex); 3066 3067 use_polling = mtx_owned(xfer->xroot->xfer_mtx) ? 1 : 0; 3068 3069 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3070 "wValue=0x%04x wIndex=0x%04x\n", 3071 std->req.bmRequestType, std->req.bRequest, 3072 UGETW(std->req.wLength), value, index); 3073 3074#define C(x,y) ((x) | ((y) << 8)) 3075 switch (C(std->req.bRequest, std->req.bmRequestType)) { 3076 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3077 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3078 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3079 /* 3080 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3081 * for the integrated root hub. 3082 */ 3083 break; 3084 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3085 std->len = 1; 3086 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3087 break; 3088 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3089 switch (value >> 8) { 3090 case UDESC_DEVICE: 3091 if ((value & 0xff) != 0) { 3092 std->err = USB_ERR_IOERROR; 3093 goto done; 3094 } 3095 std->len = sizeof(ehci_devd); 3096 sc->sc_hub_desc.devd = ehci_devd; 3097 break; 3098 /* 3099 * We can't really operate at another speed, 3100 * but the specification says we need this 3101 * descriptor: 3102 */ 3103 case UDESC_DEVICE_QUALIFIER: 3104 if ((value & 0xff) != 0) { 3105 std->err = USB_ERR_IOERROR; 3106 goto done; 3107 } 3108 std->len = sizeof(ehci_odevd); 3109 sc->sc_hub_desc.odevd = ehci_odevd; 3110 break; 3111 3112 case UDESC_CONFIG: 3113 if ((value & 0xff) != 0) { 3114 std->err = USB_ERR_IOERROR; 3115 goto done; 3116 } 3117 std->len = sizeof(ehci_confd); 3118 std->ptr = USB_ADD_BYTES(&ehci_confd, 0); 3119 break; 3120 3121 case UDESC_STRING: 3122 switch (value & 0xff) { 3123 case 0: /* Language table */ 3124 ptr = "\001"; 3125 break; 3126 3127 case 1: /* Vendor */ 3128 ptr = sc->sc_vendor; 3129 break; 3130 3131 case 2: /* Product */ 3132 ptr = "EHCI root HUB"; 3133 break; 3134 3135 default: 3136 ptr = ""; 3137 break; 3138 } 3139 3140 std->len = usb2_make_str_desc 3141 (sc->sc_hub_desc.temp, 3142 sizeof(sc->sc_hub_desc.temp), 3143 ptr); 3144 break; 3145 default: 3146 std->err = USB_ERR_IOERROR; 3147 goto done; 3148 } 3149 break; 3150 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3151 std->len = 1; 3152 sc->sc_hub_desc.temp[0] = 0; 3153 break; 3154 case C(UR_GET_STATUS, UT_READ_DEVICE): 3155 std->len = 2; 3156 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3157 break; 3158 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3159 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3160 std->len = 2; 3161 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3162 break; 3163 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3164 if (value >= USB_MAX_DEVICES) { 3165 std->err = USB_ERR_IOERROR; 3166 goto done; 3167 } 3168 sc->sc_addr = value; 3169 break; 3170 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3171 if ((value != 0) && (value != 1)) { 3172 std->err = USB_ERR_IOERROR; 3173 goto done; 3174 } 3175 sc->sc_conf = value; 3176 break; 3177 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3178 break; 3179 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3180 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3181 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3182 std->err = USB_ERR_IOERROR; 3183 goto done; 3184 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3185 break; 3186 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3187 break; 3188 /* Hub requests */ 3189 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3190 break; 3191 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3192 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3193 3194 if ((index < 1) || 3195 (index > sc->sc_noport)) { 3196 std->err = USB_ERR_IOERROR; 3197 goto done; 3198 } 3199 port = EHCI_PORTSC(index); 3200 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3201 switch (value) { 3202 case UHF_PORT_ENABLE: 3203 EOWRITE4(sc, port, v & ~EHCI_PS_PE); 3204 break; 3205 case UHF_PORT_SUSPEND: 3206 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) { 3207 3208 /* 3209 * waking up a High Speed device is rather 3210 * complicated if 3211 */ 3212 EOWRITE4(sc, port, v | EHCI_PS_FPR); 3213 } 3214 /* wait 20ms for resume sequence to complete */ 3215 if (use_polling) { 3216 /* polling */ 3217 DELAY(20 * 1000); 3218 } else { 3219 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 20); 3220 } 3221 3222 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP | 3223 EHCI_PS_FPR | (3 << 10) /* High Speed */ )); 3224 3225 /* settle time */ 3226 if (use_polling) { 3227 /* polling */ 3228 DELAY(4 * 1000); 3229 } else { 3230 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 4); 3231 } 3232 break; 3233 case UHF_PORT_POWER: 3234 EOWRITE4(sc, port, v & ~EHCI_PS_PP); 3235 break; 3236 case UHF_PORT_TEST: 3237 DPRINTFN(3, "clear port test " 3238 "%d\n", index); 3239 break; 3240 case UHF_PORT_INDICATOR: 3241 DPRINTFN(3, "clear port ind " 3242 "%d\n", index); 3243 EOWRITE4(sc, port, v & ~EHCI_PS_PIC); 3244 break; 3245 case UHF_C_PORT_CONNECTION: 3246 EOWRITE4(sc, port, v | EHCI_PS_CSC); 3247 break; 3248 case UHF_C_PORT_ENABLE: 3249 EOWRITE4(sc, port, v | EHCI_PS_PEC); 3250 break; 3251 case UHF_C_PORT_SUSPEND: 3252 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3253 break; 3254 case UHF_C_PORT_OVER_CURRENT: 3255 EOWRITE4(sc, port, v | EHCI_PS_OCC); 3256 break; 3257 case UHF_C_PORT_RESET: 3258 sc->sc_isreset = 0; 3259 break; 3260 default: 3261 std->err = USB_ERR_IOERROR; 3262 goto done; 3263 } 3264 break; 3265 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3266 if ((value & 0xff) != 0) { 3267 std->err = USB_ERR_IOERROR; 3268 goto done; 3269 } 3270 v = EOREAD4(sc, EHCI_HCSPARAMS); 3271 3272 sc->sc_hub_desc.hubd = ehci_hubd; 3273 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3274 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, 3275 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) | 3276 (EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) ? 3277 UHD_PORT_IND : 0)); 3278 /* XXX can't find out? */ 3279 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200; 3280 for (l = 0; l < sc->sc_noport; l++) { 3281 /* XXX can't find out? */ 3282 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] &= ~(1 << (l % 8)); 3283 } 3284 sc->sc_hub_desc.hubd.bDescLength = 3285 8 + ((sc->sc_noport + 7) / 8); 3286 std->len = sc->sc_hub_desc.hubd.bDescLength; 3287 break; 3288 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3289 std->len = 16; 3290 bzero(sc->sc_hub_desc.temp, 16); 3291 break; 3292 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3293 DPRINTFN(9, "get port status i=%d\n", 3294 index); 3295 if ((index < 1) || 3296 (index > sc->sc_noport)) { 3297 std->err = USB_ERR_IOERROR; 3298 goto done; 3299 } 3300 v = EOREAD4(sc, EHCI_PORTSC(index)); 3301 DPRINTFN(9, "port status=0x%04x\n", v); 3302 if (sc->sc_flags & EHCI_SCFLG_FORCESPEED) { 3303 if ((v & 0xc000000) == 0x8000000) 3304 i = UPS_HIGH_SPEED; 3305 else if ((v & 0xc000000) == 0x4000000) 3306 i = UPS_LOW_SPEED; 3307 else 3308 i = 0; 3309 } else { 3310 i = UPS_HIGH_SPEED; 3311 } 3312 if (v & EHCI_PS_CS) 3313 i |= UPS_CURRENT_CONNECT_STATUS; 3314 if (v & EHCI_PS_PE) 3315 i |= UPS_PORT_ENABLED; 3316 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR)) 3317 i |= UPS_SUSPEND; 3318 if (v & EHCI_PS_OCA) 3319 i |= UPS_OVERCURRENT_INDICATOR; 3320 if (v & EHCI_PS_PR) 3321 i |= UPS_RESET; 3322 if (v & EHCI_PS_PP) 3323 i |= UPS_PORT_POWER; 3324 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3325 i = 0; 3326 if (v & EHCI_PS_CSC) 3327 i |= UPS_C_CONNECT_STATUS; 3328 if (v & EHCI_PS_PEC) 3329 i |= UPS_C_PORT_ENABLED; 3330 if (v & EHCI_PS_OCC) 3331 i |= UPS_C_OVERCURRENT_INDICATOR; 3332 if (v & EHCI_PS_FPR) 3333 i |= UPS_C_SUSPEND; 3334 if (sc->sc_isreset) 3335 i |= UPS_C_PORT_RESET; 3336 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3337 std->len = sizeof(sc->sc_hub_desc.ps); 3338 break; 3339 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3340 std->err = USB_ERR_IOERROR; 3341 goto done; 3342 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3343 break; 3344 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3345 if ((index < 1) || 3346 (index > sc->sc_noport)) { 3347 std->err = USB_ERR_IOERROR; 3348 goto done; 3349 } 3350 port = EHCI_PORTSC(index); 3351 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3352 switch (value) { 3353 case UHF_PORT_ENABLE: 3354 EOWRITE4(sc, port, v | EHCI_PS_PE); 3355 break; 3356 case UHF_PORT_SUSPEND: 3357 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3358 break; 3359 case UHF_PORT_RESET: 3360 DPRINTFN(6, "reset port %d\n", index); 3361#if USB_DEBUG 3362 if (ehcinohighspeed) { 3363 /* 3364 * Connect USB device to companion 3365 * controller. 3366 */ 3367 ehci_disown(sc, index, 1); 3368 break; 3369 } 3370#endif 3371 if (EHCI_PS_IS_LOWSPEED(v)) { 3372 /* Low speed device, give up ownership. */ 3373 ehci_disown(sc, index, 1); 3374 break; 3375 } 3376 /* Start reset sequence. */ 3377 v &= ~(EHCI_PS_PE | EHCI_PS_PR); 3378 EOWRITE4(sc, port, v | EHCI_PS_PR); 3379 3380 if (use_polling) { 3381 /* polling */ 3382 DELAY(USB_PORT_ROOT_RESET_DELAY * 1000); 3383 } else { 3384 /* Wait for reset to complete. */ 3385 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 3386 USB_PORT_ROOT_RESET_DELAY); 3387 } 3388 3389 /* Terminate reset sequence. */ 3390 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM)) 3391 EOWRITE4(sc, port, v); 3392 3393 if (use_polling) { 3394 /* polling */ 3395 DELAY(EHCI_PORT_RESET_COMPLETE * 1000); 3396 } else { 3397 /* Wait for HC to complete reset. */ 3398 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 3399 EHCI_PORT_RESET_COMPLETE); 3400 } 3401 3402 v = EOREAD4(sc, port); 3403 DPRINTF("ehci after reset, status=0x%08x\n", v); 3404 if (v & EHCI_PS_PR) { 3405 device_printf(sc->sc_bus.bdev, 3406 "port reset timeout\n"); 3407 std->err = USB_ERR_TIMEOUT; 3408 goto done; 3409 } 3410 if (!(v & EHCI_PS_PE)) { 3411 /* 3412 * Not a high speed device, give up 3413 * ownership. 3414 */ 3415 ehci_disown(sc, index, 0); 3416 break; 3417 } 3418 sc->sc_isreset = 1; 3419 DPRINTF("ehci port %d reset, status = 0x%08x\n", 3420 index, v); 3421 break; 3422 3423 case UHF_PORT_POWER: 3424 DPRINTFN(3, "set port power %d\n", index); 3425 EOWRITE4(sc, port, v | EHCI_PS_PP); 3426 break; 3427 3428 case UHF_PORT_TEST: 3429 DPRINTFN(3, "set port test %d\n", index); 3430 break; 3431 3432 case UHF_PORT_INDICATOR: 3433 DPRINTFN(3, "set port ind %d\n", index); 3434 EOWRITE4(sc, port, v | EHCI_PS_PIC); 3435 break; 3436 3437 default: 3438 std->err = USB_ERR_IOERROR; 3439 goto done; 3440 } 3441 break; 3442 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3443 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3444 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3445 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3446 break; 3447 default: 3448 std->err = USB_ERR_IOERROR; 3449 goto done; 3450 } 3451done: 3452 return; 3453} 3454 3455static void 3456ehci_root_ctrl_poll(ehci_softc_t *sc) 3457{ 3458 usb2_sw_transfer(&sc->sc_root_ctrl, 3459 &ehci_root_ctrl_done); 3460} 3461 3462struct usb2_pipe_methods ehci_root_ctrl_methods = 3463{ 3464 .open = ehci_root_ctrl_open, 3465 .close = ehci_root_ctrl_close, 3466 .enter = ehci_root_ctrl_enter, 3467 .start = ehci_root_ctrl_start, 3468 .enter_is_cancelable = 1, 3469 .start_is_cancelable = 0, 3470}; 3471 3472/*------------------------------------------------------------------------* 3473 * ehci root interrupt support 3474 *------------------------------------------------------------------------*/ 3475static void 3476ehci_root_intr_open(struct usb2_xfer *xfer) 3477{ 3478 return; 3479} 3480 3481static void 3482ehci_root_intr_close(struct usb2_xfer *xfer) 3483{ 3484 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 3485 3486 if (sc->sc_root_intr.xfer == xfer) { 3487 sc->sc_root_intr.xfer = NULL; 3488 } 3489 ehci_device_done(xfer, USB_ERR_CANCELLED); 3490} 3491 3492static void 3493ehci_root_intr_enter(struct usb2_xfer *xfer) 3494{ 3495 return; 3496} 3497 3498static void 3499ehci_root_intr_start(struct usb2_xfer *xfer) 3500{ 3501 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus); 3502 3503 sc->sc_root_intr.xfer = xfer; 3504} 3505 3506struct usb2_pipe_methods ehci_root_intr_methods = 3507{ 3508 .open = ehci_root_intr_open, 3509 .close = ehci_root_intr_close, 3510 .enter = ehci_root_intr_enter, 3511 .start = ehci_root_intr_start, 3512 .enter_is_cancelable = 1, 3513 .start_is_cancelable = 1, 3514}; 3515 3516static void 3517ehci_xfer_setup(struct usb2_setup_params *parm) 3518{ 3519 struct usb2_page_search page_info; 3520 struct usb2_page_cache *pc; 3521 ehci_softc_t *sc; 3522 struct usb2_xfer *xfer; 3523 void *last_obj; 3524 uint32_t nqtd; 3525 uint32_t nqh; 3526 uint32_t nsitd; 3527 uint32_t nitd; 3528 uint32_t n; 3529 3530 sc = EHCI_BUS2SC(parm->udev->bus); 3531 xfer = parm->curr_xfer; 3532 3533 nqtd = 0; 3534 nqh = 0; 3535 nsitd = 0; 3536 nitd = 0; 3537 3538 /* 3539 * compute maximum number of some structures 3540 */ 3541 if (parm->methods == &ehci_device_ctrl_methods) { 3542 3543 /* 3544 * The proof for the "nqtd" formula is illustrated like 3545 * this: 3546 * 3547 * +------------------------------------+ 3548 * | | 3549 * | |remainder -> | 3550 * | +-----+---+ | 3551 * | | xxx | x | frm 0 | 3552 * | +-----+---++ | 3553 * | | xxx | xx | frm 1 | 3554 * | +-----+----+ | 3555 * | ... | 3556 * +------------------------------------+ 3557 * 3558 * "xxx" means a completely full USB transfer descriptor 3559 * 3560 * "x" and "xx" means a short USB packet 3561 * 3562 * For the remainder of an USB transfer modulo 3563 * "max_data_length" we need two USB transfer descriptors. 3564 * One to transfer the remaining data and one to finalise 3565 * with a zero length packet in case the "force_short_xfer" 3566 * flag is set. We only need two USB transfer descriptors in 3567 * the case where the transfer length of the first one is a 3568 * factor of "max_frame_size". The rest of the needed USB 3569 * transfer descriptors is given by the buffer size divided 3570 * by the maximum data payload. 3571 */ 3572 parm->hc_max_packet_size = 0x400; 3573 parm->hc_max_packet_count = 1; 3574 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3575 xfer->flags_int.bdma_enable = 1; 3576 3577 usb2_transfer_setup_sub(parm); 3578 3579 nqh = 1; 3580 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */ 3581 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 3582 3583 } else if (parm->methods == &ehci_device_bulk_methods) { 3584 3585 parm->hc_max_packet_size = 0x400; 3586 parm->hc_max_packet_count = 1; 3587 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3588 xfer->flags_int.bdma_enable = 1; 3589 3590 usb2_transfer_setup_sub(parm); 3591 3592 nqh = 1; 3593 nqtd = ((2 * xfer->nframes) 3594 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 3595 3596 } else if (parm->methods == &ehci_device_intr_methods) { 3597 3598 if (parm->speed == USB_SPEED_HIGH) { 3599 parm->hc_max_packet_size = 0x400; 3600 parm->hc_max_packet_count = 3; 3601 } else if (parm->speed == USB_SPEED_FULL) { 3602 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME; 3603 parm->hc_max_packet_count = 1; 3604 } else { 3605 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8; 3606 parm->hc_max_packet_count = 1; 3607 } 3608 3609 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3610 xfer->flags_int.bdma_enable = 1; 3611 3612 usb2_transfer_setup_sub(parm); 3613 3614 nqh = 1; 3615 nqtd = ((2 * xfer->nframes) 3616 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 3617 3618 } else if (parm->methods == &ehci_device_isoc_fs_methods) { 3619 3620 parm->hc_max_packet_size = 0x3FF; 3621 parm->hc_max_packet_count = 1; 3622 parm->hc_max_frame_size = 0x3FF; 3623 xfer->flags_int.bdma_enable = 1; 3624 3625 usb2_transfer_setup_sub(parm); 3626 3627 nsitd = xfer->nframes; 3628 3629 } else if (parm->methods == &ehci_device_isoc_hs_methods) { 3630 3631 parm->hc_max_packet_size = 0x400; 3632 parm->hc_max_packet_count = 3; 3633 parm->hc_max_frame_size = 0xC00; 3634 xfer->flags_int.bdma_enable = 1; 3635 3636 usb2_transfer_setup_sub(parm); 3637 3638 nitd = (xfer->nframes + 7) / 8; 3639 3640 } else { 3641 3642 parm->hc_max_packet_size = 0x400; 3643 parm->hc_max_packet_count = 1; 3644 parm->hc_max_frame_size = 0x400; 3645 3646 usb2_transfer_setup_sub(parm); 3647 } 3648 3649alloc_dma_set: 3650 3651 if (parm->err) { 3652 return; 3653 } 3654 /* 3655 * Allocate queue heads and transfer descriptors 3656 */ 3657 last_obj = NULL; 3658 3659 if (usb2_transfer_setup_sub_malloc( 3660 parm, &pc, sizeof(ehci_itd_t), 3661 EHCI_ITD_ALIGN, nitd)) { 3662 parm->err = USB_ERR_NOMEM; 3663 return; 3664 } 3665 if (parm->buf) { 3666 for (n = 0; n != nitd; n++) { 3667 ehci_itd_t *td; 3668 3669 usb2_get_page(pc + n, 0, &page_info); 3670 3671 td = page_info.buffer; 3672 3673 /* init TD */ 3674 td->itd_self = htoehci32(sc, page_info.physaddr | EHCI_LINK_ITD); 3675 td->obj_next = last_obj; 3676 td->page_cache = pc + n; 3677 3678 last_obj = td; 3679 3680 usb2_pc_cpu_flush(pc + n); 3681 } 3682 } 3683 if (usb2_transfer_setup_sub_malloc( 3684 parm, &pc, sizeof(ehci_sitd_t), 3685 EHCI_SITD_ALIGN, nsitd)) { 3686 parm->err = USB_ERR_NOMEM; 3687 return; 3688 } 3689 if (parm->buf) { 3690 for (n = 0; n != nsitd; n++) { 3691 ehci_sitd_t *td; 3692 3693 usb2_get_page(pc + n, 0, &page_info); 3694 3695 td = page_info.buffer; 3696 3697 /* init TD */ 3698 td->sitd_self = htoehci32(sc, page_info.physaddr | EHCI_LINK_SITD); 3699 td->obj_next = last_obj; 3700 td->page_cache = pc + n; 3701 3702 last_obj = td; 3703 3704 usb2_pc_cpu_flush(pc + n); 3705 } 3706 } 3707 if (usb2_transfer_setup_sub_malloc( 3708 parm, &pc, sizeof(ehci_qtd_t), 3709 EHCI_QTD_ALIGN, nqtd)) { 3710 parm->err = USB_ERR_NOMEM; 3711 return; 3712 } 3713 if (parm->buf) { 3714 for (n = 0; n != nqtd; n++) { 3715 ehci_qtd_t *qtd; 3716 3717 usb2_get_page(pc + n, 0, &page_info); 3718 3719 qtd = page_info.buffer; 3720 3721 /* init TD */ 3722 qtd->qtd_self = htoehci32(sc, page_info.physaddr); 3723 qtd->obj_next = last_obj; 3724 qtd->page_cache = pc + n; 3725 3726 last_obj = qtd; 3727 3728 usb2_pc_cpu_flush(pc + n); 3729 } 3730 } 3731 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3732 3733 last_obj = NULL; 3734 3735 if (usb2_transfer_setup_sub_malloc( 3736 parm, &pc, sizeof(ehci_qh_t), 3737 EHCI_QH_ALIGN, nqh)) { 3738 parm->err = USB_ERR_NOMEM; 3739 return; 3740 } 3741 if (parm->buf) { 3742 for (n = 0; n != nqh; n++) { 3743 ehci_qh_t *qh; 3744 3745 usb2_get_page(pc + n, 0, &page_info); 3746 3747 qh = page_info.buffer; 3748 3749 /* init QH */ 3750 qh->qh_self = htoehci32(sc, page_info.physaddr | EHCI_LINK_QH); 3751 qh->obj_next = last_obj; 3752 qh->page_cache = pc + n; 3753 3754 last_obj = qh; 3755 3756 usb2_pc_cpu_flush(pc + n); 3757 } 3758 } 3759 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3760 3761 if (!xfer->flags_int.curr_dma_set) { 3762 xfer->flags_int.curr_dma_set = 1; 3763 goto alloc_dma_set; 3764 } 3765} 3766 3767static void 3768ehci_xfer_unsetup(struct usb2_xfer *xfer) 3769{ 3770 return; 3771} 3772 3773static void 3774ehci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 3775 struct usb2_pipe *pipe) 3776{ 3777 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3778 3779 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3780 pipe, udev->address, 3781 edesc->bEndpointAddress, udev->flags.usb2_mode, 3782 sc->sc_addr); 3783 3784 if (udev->flags.usb2_mode != USB_MODE_HOST) { 3785 /* not supported */ 3786 return; 3787 } 3788 if (udev->device_index == sc->sc_addr) { 3789 switch (edesc->bEndpointAddress) { 3790 case USB_CONTROL_ENDPOINT: 3791 pipe->methods = &ehci_root_ctrl_methods; 3792 break; 3793 case UE_DIR_IN | EHCI_INTR_ENDPT: 3794 pipe->methods = &ehci_root_intr_methods; 3795 break; 3796 default: 3797 /* do nothing */ 3798 break; 3799 } 3800 } else { 3801 if ((udev->speed != USB_SPEED_HIGH) && 3802 ((udev->hs_hub_addr == 0) || 3803 (udev->hs_port_no == 0) || 3804 (udev->bus->devices[udev->hs_hub_addr] == NULL) || 3805 (udev->bus->devices[udev->hs_hub_addr]->hub == NULL))) { 3806 /* We need a transaction translator */ 3807 goto done; 3808 } 3809 switch (edesc->bmAttributes & UE_XFERTYPE) { 3810 case UE_CONTROL: 3811 pipe->methods = &ehci_device_ctrl_methods; 3812 break; 3813 case UE_INTERRUPT: 3814 pipe->methods = &ehci_device_intr_methods; 3815 break; 3816 case UE_ISOCHRONOUS: 3817 if (udev->speed == USB_SPEED_HIGH) { 3818 pipe->methods = &ehci_device_isoc_hs_methods; 3819 } else if (udev->speed == USB_SPEED_FULL) { 3820 pipe->methods = &ehci_device_isoc_fs_methods; 3821 } 3822 break; 3823 case UE_BULK: 3824 if (udev->speed != USB_SPEED_LOW) { 3825 pipe->methods = &ehci_device_bulk_methods; 3826 } 3827 break; 3828 default: 3829 /* do nothing */ 3830 break; 3831 } 3832 } 3833done: 3834 return; 3835} 3836 3837static void 3838ehci_get_dma_delay(struct usb2_bus *bus, uint32_t *pus) 3839{ 3840 /* 3841 * Wait until the hardware has finished any possible use of 3842 * the transfer descriptor(s) and QH 3843 */ 3844 *pus = (188); /* microseconds */ 3845} 3846 3847static void 3848ehci_device_resume(struct usb2_device *udev) 3849{ 3850 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3851 struct usb2_xfer *xfer; 3852 struct usb2_pipe_methods *methods; 3853 3854 DPRINTF("\n"); 3855 3856 USB_BUS_LOCK(udev->bus); 3857 3858 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3859 3860 if (xfer->xroot->udev == udev) { 3861 3862 methods = xfer->pipe->methods; 3863 3864 if ((methods == &ehci_device_bulk_methods) || 3865 (methods == &ehci_device_ctrl_methods)) { 3866 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3867 sc->sc_async_p_last); 3868 } 3869 if (methods == &ehci_device_intr_methods) { 3870 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3871 sc->sc_intr_p_last[xfer->qh_pos]); 3872 } 3873 } 3874 } 3875 3876 USB_BUS_UNLOCK(udev->bus); 3877 3878 return; 3879} 3880 3881static void 3882ehci_device_suspend(struct usb2_device *udev) 3883{ 3884 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3885 struct usb2_xfer *xfer; 3886 struct usb2_pipe_methods *methods; 3887 3888 DPRINTF("\n"); 3889 3890 USB_BUS_LOCK(udev->bus); 3891 3892 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3893 3894 if (xfer->xroot->udev == udev) { 3895 3896 methods = xfer->pipe->methods; 3897 3898 if ((methods == &ehci_device_bulk_methods) || 3899 (methods == &ehci_device_ctrl_methods)) { 3900 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3901 sc->sc_async_p_last); 3902 } 3903 if (methods == &ehci_device_intr_methods) { 3904 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 3905 sc->sc_intr_p_last[xfer->qh_pos]); 3906 } 3907 } 3908 } 3909 3910 USB_BUS_UNLOCK(udev->bus); 3911 3912 return; 3913} 3914 3915static void 3916ehci_set_hw_power(struct usb2_bus *bus) 3917{ 3918 ehci_softc_t *sc = EHCI_BUS2SC(bus); 3919 uint32_t temp; 3920 uint32_t flags; 3921 3922 DPRINTF("\n"); 3923 3924 USB_BUS_LOCK(bus); 3925 3926 flags = bus->hw_power_state; 3927 3928 temp = EOREAD4(sc, EHCI_USBCMD); 3929 3930 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 3931 3932 if (flags & (USB_HW_POWER_CONTROL | 3933 USB_HW_POWER_BULK)) { 3934 DPRINTF("Async is active\n"); 3935 temp |= EHCI_CMD_ASE; 3936 } 3937 if (flags & (USB_HW_POWER_INTERRUPT | 3938 USB_HW_POWER_ISOC)) { 3939 DPRINTF("Periodic is active\n"); 3940 temp |= EHCI_CMD_PSE; 3941 } 3942 EOWRITE4(sc, EHCI_USBCMD, temp); 3943 3944 USB_BUS_UNLOCK(bus); 3945 3946 return; 3947} 3948 3949struct usb2_bus_methods ehci_bus_methods = 3950{ 3951 .pipe_init = ehci_pipe_init, 3952 .xfer_setup = ehci_xfer_setup, 3953 .xfer_unsetup = ehci_xfer_unsetup, 3954 .do_poll = ehci_do_poll, 3955 .get_dma_delay = ehci_get_dma_delay, 3956 .device_resume = ehci_device_resume, 3957 .device_suspend = ehci_device_suspend, 3958 .set_hw_power = ehci_set_hw_power, 3959 .roothub_exec = ehci_root_ctrl_task, 3960}; 3961