ehci.c revision 186454
1/*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 2004 Lennart Augustsson. All rights reserved. 5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 31 * 32 * The EHCI 0.96 spec can be found at 33 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 34 * The EHCI 1.0 spec can be found at 35 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 36 * and the USB 2.0 spec at 37 * http://www.usb.org/developers/docs/usb_20.zip 38 * 39 */ 40 41/* 42 * TODO: 43 * 1) command failures are not recovered correctly 44 */ 45 46#include <sys/cdefs.h> 47__FBSDID("$FreeBSD: head/sys/dev/usb2/controller/ehci2.c 186454 2008-12-23 19:59:21Z thompsa $"); 48 49#include <dev/usb2/include/usb2_standard.h> 50#include <dev/usb2/include/usb2_mfunc.h> 51#include <dev/usb2/include/usb2_error.h> 52#include <dev/usb2/include/usb2_defs.h> 53 54#define USB_DEBUG_VAR ehcidebug 55#define usb2_config_td_cc ehci_config_copy 56#define usb2_config_td_softc ehci_softc 57 58#include <dev/usb2/core/usb2_core.h> 59#include <dev/usb2/core/usb2_debug.h> 60#include <dev/usb2/core/usb2_busdma.h> 61#include <dev/usb2/core/usb2_process.h> 62#include <dev/usb2/core/usb2_config_td.h> 63#include <dev/usb2/core/usb2_sw_transfer.h> 64#include <dev/usb2/core/usb2_transfer.h> 65#include <dev/usb2/core/usb2_device.h> 66#include <dev/usb2/core/usb2_hub.h> 67#include <dev/usb2/core/usb2_util.h> 68 69#include <dev/usb2/controller/usb2_controller.h> 70#include <dev/usb2/controller/usb2_bus.h> 71#include <dev/usb2/controller/ehci2.h> 72 73#define EHCI_BUS2SC(bus) ((ehci_softc_t *)(((uint8_t *)(bus)) - \ 74 USB_P2U(&(((ehci_softc_t *)0)->sc_bus)))) 75 76#if USB_DEBUG 77static int ehcidebug = 0; 78static int ehcinohighspeed = 0; 79 80SYSCTL_NODE(_hw_usb2, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci"); 81SYSCTL_INT(_hw_usb2_ehci, OID_AUTO, debug, CTLFLAG_RW, 82 &ehcidebug, 0, "Debug level"); 83SYSCTL_INT(_hw_usb2_ehci, OID_AUTO, no_hs, CTLFLAG_RW, 84 &ehcinohighspeed, 0, "Disable High Speed USB"); 85 86static void ehci_dump_regs(ehci_softc_t *sc); 87static void ehci_dump_sqh(ehci_qh_t *sqh); 88 89#endif 90 91#define EHCI_INTR_ENDPT 1 92 93extern struct usb2_bus_methods ehci_bus_methods; 94extern struct usb2_pipe_methods ehci_device_bulk_methods; 95extern struct usb2_pipe_methods ehci_device_ctrl_methods; 96extern struct usb2_pipe_methods ehci_device_intr_methods; 97extern struct usb2_pipe_methods ehci_device_isoc_fs_methods; 98extern struct usb2_pipe_methods ehci_device_isoc_hs_methods; 99extern struct usb2_pipe_methods ehci_root_ctrl_methods; 100extern struct usb2_pipe_methods ehci_root_intr_methods; 101 102static usb2_config_td_command_t ehci_root_ctrl_task; 103static void ehci_do_poll(struct usb2_bus *bus); 104static void ehci_root_ctrl_poll(struct ehci_softc *sc); 105static void ehci_device_done(struct usb2_xfer *xfer, usb2_error_t error); 106static uint8_t ehci_check_transfer(struct usb2_xfer *xfer); 107static void ehci_timeout(void *arg); 108 109static usb2_sw_transfer_func_t ehci_root_intr_done; 110static usb2_sw_transfer_func_t ehci_root_ctrl_done; 111 112struct ehci_std_temp { 113 struct usb2_page_cache *pc; 114 ehci_qtd_t *td; 115 ehci_qtd_t *td_next; 116 uint32_t average; 117 uint32_t qtd_status; 118 uint32_t len; 119 uint16_t max_frame_size; 120 uint8_t shortpkt; 121 uint8_t auto_data_toggle; 122 uint8_t setup_alt_next; 123 uint8_t short_frames_ok; 124}; 125 126void 127ehci_iterate_hw_softc(struct usb2_bus *bus, usb2_bus_mem_sub_cb_t *cb) 128{ 129 struct ehci_softc *sc = EHCI_BUS2SC(bus); 130 uint32_t i; 131 132 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 133 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN); 134 135 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg, 136 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 137 138 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 139 cb(bus, sc->sc_hw.intr_start_pc + i, 140 sc->sc_hw.intr_start_pg + i, 141 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 142 } 143 144 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 145 cb(bus, sc->sc_hw.isoc_hs_start_pc + i, 146 sc->sc_hw.isoc_hs_start_pg + i, 147 sizeof(ehci_itd_t), EHCI_ITD_ALIGN); 148 } 149 150 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 151 cb(bus, sc->sc_hw.isoc_fs_start_pc + i, 152 sc->sc_hw.isoc_fs_start_pg + i, 153 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN); 154 } 155} 156 157static usb2_error_t 158ehci_hc_reset(ehci_softc_t *sc) 159{ 160 uint32_t hcr; 161 uint32_t n; 162 163 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 164 165 for (n = 0; n != 100; n++) { 166 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 1); 167 hcr = EOREAD4(sc, EHCI_USBSTS); 168 if (hcr & EHCI_STS_HCH) { 169 hcr = 0; 170 break; 171 } 172 } 173 174 /* 175 * Fall through and try reset anyway even though 176 * Table 2-9 in the EHCI spec says this will result 177 * in undefined behavior. 178 */ 179 180 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 181 for (n = 0; n != 100; n++) { 182 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 1); 183 hcr = EOREAD4(sc, EHCI_USBCMD); 184 if (!(hcr & EHCI_CMD_HCRESET)) { 185 if (sc->sc_flags & EHCI_SCFLG_SETMODE) 186 EOWRITE4(sc, 0x68, 0x3); 187 hcr = 0; 188 break; 189 } 190 } 191 192 if (hcr) { 193 return (USB_ERR_IOERROR); 194 } 195 return (0); 196} 197 198usb2_error_t 199ehci_init(ehci_softc_t *sc) 200{ 201 struct usb2_page_search buf_res; 202 uint32_t version; 203 uint32_t sparams; 204 uint32_t cparams; 205 uint32_t hcr; 206 uint16_t i; 207 uint16_t x; 208 uint16_t y; 209 uint16_t bit; 210 usb2_error_t err = 0; 211 212 USB_BUS_LOCK(&sc->sc_bus); 213 214 DPRINTF("start\n"); 215 216 usb2_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0); 217 218#if USB_DEBUG 219 if (ehcidebug > 2) { 220 ehci_dump_regs(sc); 221 } 222#endif 223 224 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 225 226 version = EREAD2(sc, EHCI_HCIVERSION); 227 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n", 228 version >> 8, version & 0xff); 229 230 sparams = EREAD4(sc, EHCI_HCSPARAMS); 231 DPRINTF("sparams=0x%x\n", sparams); 232 233 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 234 cparams = EREAD4(sc, EHCI_HCCPARAMS); 235 DPRINTF("cparams=0x%x\n", cparams); 236 237 if (EHCI_HCC_64BIT(cparams)) { 238 DPRINTF("HCC uses 64-bit structures\n"); 239 240 /* MUST clear segment register if 64 bit capable */ 241 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 242 } 243 sc->sc_bus.usbrev = USB_REV_2_0; 244 245 /* Reset the controller */ 246 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)); 247 248 err = ehci_hc_reset(sc); 249 if (err) { 250 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 251 goto done; 252 } 253 /* 254 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4 255 * bytes 2: 256*4 bytes 3: unknown 256 */ 257 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) { 258 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n"); 259 err = USB_ERR_IOERROR; 260 goto done; 261 } 262 /* set up the bus struct */ 263 sc->sc_bus.methods = &ehci_bus_methods; 264 265 sc->sc_eintrs = EHCI_NORMAL_INTRS; 266 267 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 268 ehci_qh_t *qh; 269 270 usb2_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res); 271 272 qh = buf_res.buffer; 273 274 /* initialize page cache pointer */ 275 276 qh->page_cache = sc->sc_hw.intr_start_pc + i; 277 278 /* store a pointer to queue head */ 279 280 sc->sc_intr_p_last[i] = qh; 281 282 qh->qh_self = 283 htole32(buf_res.physaddr) | 284 htole32(EHCI_LINK_QH); 285 286 qh->qh_endp = 287 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 288 qh->qh_endphub = 289 htole32(EHCI_QH_SET_MULT(1)); 290 qh->qh_curqtd = 0; 291 292 qh->qh_qtd.qtd_next = 293 htole32(EHCI_LINK_TERMINATE); 294 qh->qh_qtd.qtd_altnext = 295 htole32(EHCI_LINK_TERMINATE); 296 qh->qh_qtd.qtd_status = 297 htole32(EHCI_QTD_HALTED); 298 } 299 300 /* 301 * the QHs are arranged to give poll intervals that are 302 * powers of 2 times 1ms 303 */ 304 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 305 while (bit) { 306 x = bit; 307 while (x & bit) { 308 ehci_qh_t *qh_x; 309 ehci_qh_t *qh_y; 310 311 y = (x ^ bit) | (bit / 2); 312 313 qh_x = sc->sc_intr_p_last[x]; 314 qh_y = sc->sc_intr_p_last[y]; 315 316 /* 317 * the next QH has half the poll interval 318 */ 319 qh_x->qh_link = qh_y->qh_self; 320 321 x++; 322 } 323 bit >>= 1; 324 } 325 326 if (1) { 327 ehci_qh_t *qh; 328 329 qh = sc->sc_intr_p_last[0]; 330 331 /* the last (1ms) QH terminates */ 332 qh->qh_link = htole32(EHCI_LINK_TERMINATE); 333 } 334 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 335 ehci_sitd_t *sitd; 336 ehci_itd_t *itd; 337 338 usb2_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res); 339 340 sitd = buf_res.buffer; 341 342 /* initialize page cache pointer */ 343 344 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i; 345 346 /* store a pointer to the transfer descriptor */ 347 348 sc->sc_isoc_fs_p_last[i] = sitd; 349 350 /* initialize full speed isochronous */ 351 352 sitd->sitd_self = 353 htole32(buf_res.physaddr) | 354 htole32(EHCI_LINK_SITD); 355 356 sitd->sitd_back = 357 htole32(EHCI_LINK_TERMINATE); 358 359 sitd->sitd_next = 360 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self; 361 362 363 usb2_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res); 364 365 itd = buf_res.buffer; 366 367 /* initialize page cache pointer */ 368 369 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i; 370 371 /* store a pointer to the transfer descriptor */ 372 373 sc->sc_isoc_hs_p_last[i] = itd; 374 375 /* initialize high speed isochronous */ 376 377 itd->itd_self = 378 htole32(buf_res.physaddr) | 379 htole32(EHCI_LINK_ITD); 380 381 itd->itd_next = 382 sitd->sitd_self; 383 } 384 385 usb2_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 386 387 if (1) { 388 uint32_t *pframes; 389 390 pframes = buf_res.buffer; 391 392 /* 393 * execution order: 394 * pframes -> high speed isochronous -> 395 * full speed isochronous -> interrupt QH's 396 */ 397 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) { 398 pframes[i] = sc->sc_isoc_hs_p_last 399 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self; 400 } 401 } 402 /* setup sync list pointer */ 403 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 404 405 usb2_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 406 407 if (1) { 408 409 ehci_qh_t *qh; 410 411 qh = buf_res.buffer; 412 413 /* initialize page cache pointer */ 414 415 qh->page_cache = &sc->sc_hw.async_start_pc; 416 417 /* store a pointer to the queue head */ 418 419 sc->sc_async_p_last = qh; 420 421 /* init dummy QH that starts the async list */ 422 423 qh->qh_self = 424 htole32(buf_res.physaddr) | 425 htole32(EHCI_LINK_QH); 426 427 /* fill the QH */ 428 qh->qh_endp = 429 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 430 qh->qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 431 qh->qh_link = qh->qh_self; 432 qh->qh_curqtd = 0; 433 434 /* fill the overlay qTD */ 435 qh->qh_qtd.qtd_next = htole32(EHCI_LINK_TERMINATE); 436 qh->qh_qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 437 qh->qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 438 } 439 /* flush all cache into memory */ 440 441 usb2_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc); 442 443#if USB_DEBUG 444 if (ehcidebug) { 445 ehci_dump_sqh(sc->sc_async_p_last); 446 } 447#endif 448 449 /* setup async list pointer */ 450 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 451 452 453 /* enable interrupts */ 454 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 455 456 /* turn on controller */ 457 EOWRITE4(sc, EHCI_USBCMD, 458 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */ 459 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 460 EHCI_CMD_ASE | 461 EHCI_CMD_PSE | 462 EHCI_CMD_RS); 463 464 /* Take over port ownership */ 465 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 466 467 for (i = 0; i < 100; i++) { 468 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 1); 469 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 470 if (!hcr) { 471 break; 472 } 473 } 474 if (hcr) { 475 device_printf(sc->sc_bus.bdev, "run timeout\n"); 476 err = USB_ERR_IOERROR; 477 goto done; 478 } 479done: 480 USB_BUS_UNLOCK(&sc->sc_bus); 481 482 if (!err) { 483 /* catch any lost interrupts */ 484 ehci_do_poll(&sc->sc_bus); 485 } 486 return (err); 487} 488 489/* 490 * shut down the controller when the system is going down 491 */ 492void 493ehci_detach(struct ehci_softc *sc) 494{ 495 USB_BUS_LOCK(&sc->sc_bus); 496 497 usb2_callout_stop(&sc->sc_tmo_pcd); 498 499 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 500 501 if (ehci_hc_reset(sc)) { 502 DPRINTF("reset failed!\n"); 503 } 504 /* XXX let stray task complete */ 505 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 50); 506 507 USB_BUS_UNLOCK(&sc->sc_bus); 508 509 usb2_callout_drain(&sc->sc_tmo_pcd); 510} 511 512void 513ehci_suspend(struct ehci_softc *sc) 514{ 515 uint32_t cmd; 516 uint32_t hcr; 517 uint8_t i; 518 519 USB_BUS_LOCK(&sc->sc_bus); 520 521 for (i = 1; i <= sc->sc_noport; i++) { 522 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 523 if (((cmd & EHCI_PS_PO) == 0) && 524 ((cmd & EHCI_PS_PE) == EHCI_PS_PE)) { 525 EOWRITE4(sc, EHCI_PORTSC(i), 526 cmd | EHCI_PS_SUSP); 527 } 528 } 529 530 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 531 532 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 533 EOWRITE4(sc, EHCI_USBCMD, cmd); 534 535 for (i = 0; i < 100; i++) { 536 hcr = EOREAD4(sc, EHCI_USBSTS) & 537 (EHCI_STS_ASS | EHCI_STS_PSS); 538 539 if (hcr == 0) { 540 break; 541 } 542 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 1); 543 } 544 545 if (hcr != 0) { 546 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 547 } 548 cmd &= ~EHCI_CMD_RS; 549 EOWRITE4(sc, EHCI_USBCMD, cmd); 550 551 for (i = 0; i < 100; i++) { 552 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 553 if (hcr == EHCI_STS_HCH) { 554 break; 555 } 556 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 1); 557 } 558 559 if (hcr != EHCI_STS_HCH) { 560 device_printf(sc->sc_bus.bdev, 561 "config timeout\n"); 562 } 563 USB_BUS_UNLOCK(&sc->sc_bus); 564} 565 566void 567ehci_resume(struct ehci_softc *sc) 568{ 569 struct usb2_page_search buf_res; 570 uint32_t cmd; 571 uint32_t hcr; 572 uint8_t i; 573 574 USB_BUS_LOCK(&sc->sc_bus); 575 576 /* restore things in case the bios doesn't */ 577 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 578 579 usb2_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 580 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 581 582 usb2_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 583 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 584 585 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 586 587 hcr = 0; 588 for (i = 1; i <= sc->sc_noport; i++) { 589 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 590 if (((cmd & EHCI_PS_PO) == 0) && 591 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) { 592 EOWRITE4(sc, EHCI_PORTSC(i), 593 cmd | EHCI_PS_FPR); 594 hcr = 1; 595 } 596 } 597 598 if (hcr) { 599 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 600 USB_RESUME_WAIT); 601 602 for (i = 1; i <= sc->sc_noport; i++) { 603 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 604 if (((cmd & EHCI_PS_PO) == 0) && 605 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) { 606 EOWRITE4(sc, EHCI_PORTSC(i), 607 cmd & ~EHCI_PS_FPR); 608 } 609 } 610 } 611 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 612 613 for (i = 0; i < 100; i++) { 614 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 615 if (hcr != EHCI_STS_HCH) { 616 break; 617 } 618 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 1); 619 } 620 if (hcr == EHCI_STS_HCH) { 621 device_printf(sc->sc_bus.bdev, "config timeout\n"); 622 } 623 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 624 USB_RESUME_WAIT); 625 626 USB_BUS_UNLOCK(&sc->sc_bus); 627 628 /* catch any lost interrupts */ 629 ehci_do_poll(&sc->sc_bus); 630} 631 632void 633ehci_shutdown(ehci_softc_t *sc) 634{ 635 DPRINTF("stopping the HC\n"); 636 637 USB_BUS_LOCK(&sc->sc_bus); 638 639 if (ehci_hc_reset(sc)) { 640 DPRINTF("reset failed!\n"); 641 } 642 USB_BUS_UNLOCK(&sc->sc_bus); 643} 644 645#if USB_DEBUG 646static void 647ehci_dump_regs(ehci_softc_t *sc) 648{ 649 uint32_t i; 650 651 i = EOREAD4(sc, EHCI_USBCMD); 652 printf("cmd=0x%08x\n", i); 653 654 if (i & EHCI_CMD_ITC_1) 655 printf(" EHCI_CMD_ITC_1\n"); 656 if (i & EHCI_CMD_ITC_2) 657 printf(" EHCI_CMD_ITC_2\n"); 658 if (i & EHCI_CMD_ITC_4) 659 printf(" EHCI_CMD_ITC_4\n"); 660 if (i & EHCI_CMD_ITC_8) 661 printf(" EHCI_CMD_ITC_8\n"); 662 if (i & EHCI_CMD_ITC_16) 663 printf(" EHCI_CMD_ITC_16\n"); 664 if (i & EHCI_CMD_ITC_32) 665 printf(" EHCI_CMD_ITC_32\n"); 666 if (i & EHCI_CMD_ITC_64) 667 printf(" EHCI_CMD_ITC_64\n"); 668 if (i & EHCI_CMD_ASPME) 669 printf(" EHCI_CMD_ASPME\n"); 670 if (i & EHCI_CMD_ASPMC) 671 printf(" EHCI_CMD_ASPMC\n"); 672 if (i & EHCI_CMD_LHCR) 673 printf(" EHCI_CMD_LHCR\n"); 674 if (i & EHCI_CMD_IAAD) 675 printf(" EHCI_CMD_IAAD\n"); 676 if (i & EHCI_CMD_ASE) 677 printf(" EHCI_CMD_ASE\n"); 678 if (i & EHCI_CMD_PSE) 679 printf(" EHCI_CMD_PSE\n"); 680 if (i & EHCI_CMD_FLS_M) 681 printf(" EHCI_CMD_FLS_M\n"); 682 if (i & EHCI_CMD_HCRESET) 683 printf(" EHCI_CMD_HCRESET\n"); 684 if (i & EHCI_CMD_RS) 685 printf(" EHCI_CMD_RS\n"); 686 687 i = EOREAD4(sc, EHCI_USBSTS); 688 689 printf("sts=0x%08x\n", i); 690 691 if (i & EHCI_STS_ASS) 692 printf(" EHCI_STS_ASS\n"); 693 if (i & EHCI_STS_PSS) 694 printf(" EHCI_STS_PSS\n"); 695 if (i & EHCI_STS_REC) 696 printf(" EHCI_STS_REC\n"); 697 if (i & EHCI_STS_HCH) 698 printf(" EHCI_STS_HCH\n"); 699 if (i & EHCI_STS_IAA) 700 printf(" EHCI_STS_IAA\n"); 701 if (i & EHCI_STS_HSE) 702 printf(" EHCI_STS_HSE\n"); 703 if (i & EHCI_STS_FLR) 704 printf(" EHCI_STS_FLR\n"); 705 if (i & EHCI_STS_PCD) 706 printf(" EHCI_STS_PCD\n"); 707 if (i & EHCI_STS_ERRINT) 708 printf(" EHCI_STS_ERRINT\n"); 709 if (i & EHCI_STS_INT) 710 printf(" EHCI_STS_INT\n"); 711 712 printf("ien=0x%08x\n", 713 EOREAD4(sc, EHCI_USBINTR)); 714 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 715 EOREAD4(sc, EHCI_FRINDEX), 716 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 717 EOREAD4(sc, EHCI_PERIODICLISTBASE), 718 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 719 for (i = 1; i <= sc->sc_noport; i++) { 720 printf("port %d status=0x%08x\n", i, 721 EOREAD4(sc, EHCI_PORTSC(i))); 722 } 723} 724 725static void 726ehci_dump_link(uint32_t link, int type) 727{ 728 link = le32toh(link); 729 printf("0x%08x", link); 730 if (link & EHCI_LINK_TERMINATE) 731 printf("<T>"); 732 else { 733 printf("<"); 734 if (type) { 735 switch (EHCI_LINK_TYPE(link)) { 736 case EHCI_LINK_ITD: 737 printf("ITD"); 738 break; 739 case EHCI_LINK_QH: 740 printf("QH"); 741 break; 742 case EHCI_LINK_SITD: 743 printf("SITD"); 744 break; 745 case EHCI_LINK_FSTN: 746 printf("FSTN"); 747 break; 748 } 749 } 750 printf(">"); 751 } 752} 753 754static void 755ehci_dump_qtd(ehci_qtd_t *qtd) 756{ 757 uint32_t s; 758 759 printf(" next="); 760 ehci_dump_link(qtd->qtd_next, 0); 761 printf(" altnext="); 762 ehci_dump_link(qtd->qtd_altnext, 0); 763 printf("\n"); 764 s = le32toh(qtd->qtd_status); 765 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 766 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 767 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 768 printf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n", 769 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), 770 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE", 771 (s & EHCI_QTD_HALTED) ? "-HALTED" : "", 772 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "", 773 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "", 774 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "", 775 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "", 776 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "", 777 (s & EHCI_QTD_PINGSTATE) ? "-PING" : ""); 778 779 for (s = 0; s < 5; s++) { 780 printf(" buffer[%d]=0x%08x\n", s, 781 le32toh(qtd->qtd_buffer[s])); 782 } 783 for (s = 0; s < 5; s++) { 784 printf(" buffer_hi[%d]=0x%08x\n", s, 785 le32toh(qtd->qtd_buffer_hi[s])); 786 } 787} 788 789static uint8_t 790ehci_dump_sqtd(ehci_qtd_t *sqtd) 791{ 792 uint8_t temp; 793 794 usb2_pc_cpu_invalidate(sqtd->page_cache); 795 printf("QTD(%p) at 0x%08x:\n", sqtd, le32toh(sqtd->qtd_self)); 796 ehci_dump_qtd(sqtd); 797 temp = (sqtd->qtd_next & htole32(EHCI_LINK_TERMINATE)) ? 1 : 0; 798 return (temp); 799} 800 801static void 802ehci_dump_sqtds(ehci_qtd_t *sqtd) 803{ 804 uint16_t i; 805 uint8_t stop; 806 807 stop = 0; 808 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) { 809 stop = ehci_dump_sqtd(sqtd); 810 } 811 if (sqtd) { 812 printf("dump aborted, too many TDs\n"); 813 } 814} 815 816static void 817ehci_dump_sqh(ehci_qh_t *qh) 818{ 819 uint32_t endp, endphub; 820 821 usb2_pc_cpu_invalidate(qh->page_cache); 822 printf("QH(%p) at 0x%08x:\n", qh, le32toh(qh->qh_self) & ~0x1F); 823 printf(" link="); 824 ehci_dump_link(qh->qh_link, 1); 825 printf("\n"); 826 endp = le32toh(qh->qh_endp); 827 printf(" endp=0x%08x\n", endp); 828 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 829 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 830 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 831 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 832 printf(" mpl=0x%x ctl=%d nrl=%d\n", 833 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 834 EHCI_QH_GET_NRL(endp)); 835 endphub = le32toh(qh->qh_endphub); 836 printf(" endphub=0x%08x\n", endphub); 837 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 838 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 839 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 840 EHCI_QH_GET_MULT(endphub)); 841 printf(" curqtd="); 842 ehci_dump_link(qh->qh_curqtd, 0); 843 printf("\n"); 844 printf("Overlay qTD:\n"); 845 ehci_dump_qtd((void *)&qh->qh_qtd); 846} 847 848static void 849ehci_dump_sitd(ehci_sitd_t *sitd) 850{ 851 usb2_pc_cpu_invalidate(sitd->page_cache); 852 printf("SITD(%p) at 0x%08x\n", sitd, le32toh(sitd->sitd_self) & ~0x1F); 853 printf(" next=0x%08x\n", le32toh(sitd->sitd_next)); 854 printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n", 855 le32toh(sitd->sitd_portaddr), 856 (sitd->sitd_portaddr & htole32(EHCI_SITD_SET_DIR_IN)) 857 ? "in" : "out", 858 EHCI_SITD_GET_ADDR(le32toh(sitd->sitd_portaddr)), 859 EHCI_SITD_GET_ENDPT(le32toh(sitd->sitd_portaddr)), 860 EHCI_SITD_GET_PORT(le32toh(sitd->sitd_portaddr)), 861 EHCI_SITD_GET_HUBA(le32toh(sitd->sitd_portaddr))); 862 printf(" mask=0x%08x\n", le32toh(sitd->sitd_mask)); 863 printf(" status=0x%08x <%s> len=0x%x\n", le32toh(sitd->sitd_status), 864 (sitd->sitd_status & htole32(EHCI_SITD_ACTIVE)) ? "ACTIVE" : "", 865 EHCI_SITD_GET_LEN(le32toh(sitd->sitd_status))); 866 printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n", 867 le32toh(sitd->sitd_back), 868 le32toh(sitd->sitd_bp[0]), 869 le32toh(sitd->sitd_bp[1]), 870 le32toh(sitd->sitd_bp_hi[0]), 871 le32toh(sitd->sitd_bp_hi[1])); 872} 873 874static void 875ehci_dump_itd(ehci_itd_t *itd) 876{ 877 usb2_pc_cpu_invalidate(itd->page_cache); 878 printf("ITD(%p) at 0x%08x\n", itd, le32toh(itd->itd_self) & ~0x1F); 879 printf(" next=0x%08x\n", le32toh(itd->itd_next)); 880 printf(" status[0]=0x%08x; <%s>\n", le32toh(itd->itd_status[0]), 881 (itd->itd_status[0] & htole32(EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 882 printf(" status[1]=0x%08x; <%s>\n", le32toh(itd->itd_status[1]), 883 (itd->itd_status[1] & htole32(EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 884 printf(" status[2]=0x%08x; <%s>\n", le32toh(itd->itd_status[2]), 885 (itd->itd_status[2] & htole32(EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 886 printf(" status[3]=0x%08x; <%s>\n", le32toh(itd->itd_status[3]), 887 (itd->itd_status[3] & htole32(EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 888 printf(" status[4]=0x%08x; <%s>\n", le32toh(itd->itd_status[4]), 889 (itd->itd_status[4] & htole32(EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 890 printf(" status[5]=0x%08x; <%s>\n", le32toh(itd->itd_status[5]), 891 (itd->itd_status[5] & htole32(EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 892 printf(" status[6]=0x%08x; <%s>\n", le32toh(itd->itd_status[6]), 893 (itd->itd_status[6] & htole32(EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 894 printf(" status[7]=0x%08x; <%s>\n", le32toh(itd->itd_status[7]), 895 (itd->itd_status[7] & htole32(EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 896 printf(" bp[0]=0x%08x\n", le32toh(itd->itd_bp[0])); 897 printf(" addr=0x%02x; endpt=0x%01x\n", 898 EHCI_ITD_GET_ADDR(le32toh(itd->itd_bp[0])), 899 EHCI_ITD_GET_ENDPT(le32toh(itd->itd_bp[0]))); 900 printf(" bp[1]=0x%08x\n", le32toh(itd->itd_bp[1])); 901 printf(" dir=%s; mpl=0x%02x\n", 902 (le32toh(itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out", 903 EHCI_ITD_GET_MPL(le32toh(itd->itd_bp[1]))); 904 printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n", 905 le32toh(itd->itd_bp[2]), 906 le32toh(itd->itd_bp[3]), 907 le32toh(itd->itd_bp[4]), 908 le32toh(itd->itd_bp[5]), 909 le32toh(itd->itd_bp[6])); 910 printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n" 911 " 0x%08x,0x%08x,0x%08x\n", 912 le32toh(itd->itd_bp_hi[0]), 913 le32toh(itd->itd_bp_hi[1]), 914 le32toh(itd->itd_bp_hi[2]), 915 le32toh(itd->itd_bp_hi[3]), 916 le32toh(itd->itd_bp_hi[4]), 917 le32toh(itd->itd_bp_hi[5]), 918 le32toh(itd->itd_bp_hi[6])); 919} 920 921static void 922ehci_dump_isoc(ehci_softc_t *sc) 923{ 924 ehci_itd_t *itd; 925 ehci_sitd_t *sitd; 926 uint16_t max = 1000; 927 uint16_t pos; 928 929 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) & 930 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 931 932 printf("%s: isochronous dump from frame 0x%03x:\n", 933 __FUNCTION__, pos); 934 935 itd = sc->sc_isoc_hs_p_last[pos]; 936 sitd = sc->sc_isoc_fs_p_last[pos]; 937 938 while (itd && max && max--) { 939 ehci_dump_itd(itd); 940 itd = itd->prev; 941 } 942 943 while (sitd && max && max--) { 944 ehci_dump_sitd(sitd); 945 sitd = sitd->prev; 946 } 947} 948 949#endif 950 951static void 952ehci_transfer_intr_enqueue(struct usb2_xfer *xfer) 953{ 954 /* check for early completion */ 955 if (ehci_check_transfer(xfer)) { 956 return; 957 } 958 /* put transfer on interrupt queue */ 959 usb2_transfer_enqueue(&xfer->udev->bus->intr_q, xfer); 960 961 /* start timeout, if any */ 962 if (xfer->timeout != 0) { 963 usb2_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout); 964 } 965} 966 967#define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last) 968static ehci_sitd_t * 969_ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 970{ 971 DPRINTFN(11, "%p to %p\n", std, last); 972 973 /* (sc->sc_bus.mtx) must be locked */ 974 975 std->next = last->next; 976 std->sitd_next = last->sitd_next; 977 978 std->prev = last; 979 980 usb2_pc_cpu_flush(std->page_cache); 981 982 /* 983 * the last->next->prev is never followed: std->next->prev = std; 984 */ 985 last->next = std; 986 last->sitd_next = std->sitd_self; 987 988 usb2_pc_cpu_flush(last->page_cache); 989 990 return (std); 991} 992 993#define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last) 994static ehci_itd_t * 995_ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last) 996{ 997 DPRINTFN(11, "%p to %p\n", std, last); 998 999 /* (sc->sc_bus.mtx) must be locked */ 1000 1001 std->next = last->next; 1002 std->itd_next = last->itd_next; 1003 1004 std->prev = last; 1005 1006 usb2_pc_cpu_flush(std->page_cache); 1007 1008 /* 1009 * the last->next->prev is never followed: std->next->prev = std; 1010 */ 1011 last->next = std; 1012 last->itd_next = std->itd_self; 1013 1014 usb2_pc_cpu_flush(last->page_cache); 1015 1016 return (std); 1017} 1018 1019#define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last) 1020static ehci_qh_t * 1021_ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1022{ 1023 DPRINTFN(11, "%p to %p\n", sqh, last); 1024 1025 /* (sc->sc_bus.mtx) must be locked */ 1026 1027 sqh->next = last->next; 1028 sqh->qh_link = last->qh_link; 1029 1030 sqh->prev = last; 1031 1032 usb2_pc_cpu_flush(sqh->page_cache); 1033 1034 /* 1035 * the last->next->prev is never followed: sqh->next->prev = sqh; 1036 */ 1037 1038 last->next = sqh; 1039 last->qh_link = sqh->qh_self; 1040 1041 usb2_pc_cpu_flush(last->page_cache); 1042 1043#if USB_DEBUG 1044 if (ehcidebug > 5) { 1045 printf("%s:\n", __FUNCTION__); 1046 ehci_dump_sqh(sqh); 1047 } 1048#endif 1049 return (sqh); 1050} 1051 1052#define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last) 1053static ehci_sitd_t * 1054_ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 1055{ 1056 DPRINTFN(11, "%p from %p\n", std, last); 1057 1058 /* (sc->sc_bus.mtx) must be locked */ 1059 1060 std->prev->next = std->next; 1061 std->prev->sitd_next = std->sitd_next; 1062 1063 usb2_pc_cpu_flush(std->prev->page_cache); 1064 1065 if (std->next) { 1066 std->next->prev = std->prev; 1067 usb2_pc_cpu_flush(std->next->page_cache); 1068 } 1069 return ((last == std) ? std->prev : last); 1070} 1071 1072#define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last) 1073static ehci_itd_t * 1074_ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1075{ 1076 DPRINTFN(11, "%p from %p\n", std, last); 1077 1078 /* (sc->sc_bus.mtx) must be locked */ 1079 1080 std->prev->next = std->next; 1081 std->prev->itd_next = std->itd_next; 1082 1083 usb2_pc_cpu_flush(std->prev->page_cache); 1084 1085 if (std->next) { 1086 std->next->prev = std->prev; 1087 usb2_pc_cpu_flush(std->next->page_cache); 1088 } 1089 return ((last == std) ? std->prev : last); 1090} 1091 1092#define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last) 1093static ehci_qh_t * 1094_ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1095{ 1096 DPRINTFN(11, "%p from %p\n", sqh, last); 1097 1098 /* (sc->sc_bus.mtx) must be locked */ 1099 1100 /* only remove if not removed from a queue */ 1101 if (sqh->prev) { 1102 1103 sqh->prev->next = sqh->next; 1104 sqh->prev->qh_link = sqh->qh_link; 1105 1106 usb2_pc_cpu_flush(sqh->prev->page_cache); 1107 1108 if (sqh->next) { 1109 sqh->next->prev = sqh->prev; 1110 usb2_pc_cpu_flush(sqh->next->page_cache); 1111 } 1112 /* 1113 * set the Terminate-bit in the e_next of the QH, in case 1114 * the transferred packet was short so that the QH still 1115 * points at the last used TD 1116 */ 1117 1118 sqh->qh_qtd.qtd_next = htole32(EHCI_LINK_TERMINATE); 1119 1120 last = ((last == sqh) ? sqh->prev : last); 1121 1122 sqh->prev = 0; 1123 1124 usb2_pc_cpu_flush(sqh->page_cache); 1125 } 1126 return (last); 1127} 1128 1129static usb2_error_t 1130ehci_non_isoc_done_sub(struct usb2_xfer *xfer) 1131{ 1132 ehci_qtd_t *td; 1133 ehci_qtd_t *td_alt_next; 1134 uint32_t status; 1135 uint16_t len; 1136 1137 td = xfer->td_transfer_cache; 1138 td_alt_next = td->alt_next; 1139 1140 while (1) { 1141 1142 usb2_pc_cpu_invalidate(td->page_cache); 1143 status = le32toh(td->qtd_status); 1144 1145 len = EHCI_QTD_GET_BYTES(status); 1146 1147 /* 1148 * Verify the status length and subtract 1149 * the remainder from "frlengths[]": 1150 */ 1151 if (len > td->len) { 1152 /* should not happen */ 1153 DPRINTF("Invalid status length, " 1154 "0x%04x/0x%04x bytes\n", len, td->len); 1155 status |= EHCI_QTD_HALTED; 1156 } else if (xfer->aframes != xfer->nframes) { 1157 xfer->frlengths[xfer->aframes] -= len; 1158 } 1159 /* Check for last transfer */ 1160 if (((void *)td) == xfer->td_transfer_last) { 1161 if (len == 0) { 1162 /* 1163 * Halt is ok if descriptor is last, 1164 * and complete: 1165 */ 1166 status &= ~EHCI_QTD_HALTED; 1167 } 1168 td = NULL; 1169 break; 1170 } 1171 /* Check for transfer error */ 1172 if (status & EHCI_QTD_HALTED) { 1173 /* the transfer is finished */ 1174 td = NULL; 1175 break; 1176 } 1177 /* Check for short transfer */ 1178 if (len > 0) { 1179 if (xfer->flags_int.short_frames_ok) { 1180 /* follow alt next */ 1181 td = td->alt_next; 1182 } else { 1183 /* the transfer is finished */ 1184 td = NULL; 1185 } 1186 break; 1187 } 1188 td = td->obj_next; 1189 1190 if (td->alt_next != td_alt_next) { 1191 /* this USB frame is complete */ 1192 break; 1193 } 1194 } 1195 1196 /* update transfer cache */ 1197 1198 xfer->td_transfer_cache = td; 1199 1200 /* update data toggle */ 1201 1202 xfer->pipe->toggle_next = 1203 (status & EHCI_QTD_TOGGLE_MASK) ? 1 : 0; 1204 1205#if USB_DEBUG 1206 if (status & EHCI_QTD_STATERRS) { 1207 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x" 1208 "status=%s%s%s%s%s%s%s%s\n", 1209 xfer->address, xfer->endpoint, xfer->aframes, 1210 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1211 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "", 1212 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "", 1213 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "", 1214 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "", 1215 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "", 1216 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "", 1217 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : ""); 1218 } 1219#endif 1220 1221 return ((status & EHCI_QTD_HALTED) ? 1222 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1223} 1224 1225static void 1226ehci_non_isoc_done(struct usb2_xfer *xfer) 1227{ 1228 usb2_error_t err = 0; 1229 1230 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1231 xfer, xfer->pipe); 1232 1233#if USB_DEBUG 1234 if (ehcidebug > 10) { 1235 ehci_dump_sqtds(xfer->td_transfer_first); 1236 } 1237#endif 1238 1239 /* reset scanner */ 1240 1241 xfer->td_transfer_cache = xfer->td_transfer_first; 1242 1243 if (xfer->flags_int.control_xfr) { 1244 1245 if (xfer->flags_int.control_hdr) { 1246 1247 err = ehci_non_isoc_done_sub(xfer); 1248 } 1249 xfer->aframes = 1; 1250 1251 if (xfer->td_transfer_cache == NULL) { 1252 goto done; 1253 } 1254 } 1255 while (xfer->aframes != xfer->nframes) { 1256 1257 err = ehci_non_isoc_done_sub(xfer); 1258 xfer->aframes++; 1259 1260 if (xfer->td_transfer_cache == NULL) { 1261 goto done; 1262 } 1263 } 1264 1265 if (xfer->flags_int.control_xfr && 1266 !xfer->flags_int.control_act) { 1267 1268 err = ehci_non_isoc_done_sub(xfer); 1269 } 1270done: 1271 ehci_device_done(xfer, err); 1272} 1273 1274/*------------------------------------------------------------------------* 1275 * ehci_check_transfer 1276 * 1277 * Return values: 1278 * 0: USB transfer is not finished 1279 * Else: USB transfer is finished 1280 *------------------------------------------------------------------------*/ 1281static uint8_t 1282ehci_check_transfer(struct usb2_xfer *xfer) 1283{ 1284 struct usb2_pipe_methods *methods = xfer->pipe->methods; 1285 1286 uint32_t status; 1287 1288 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1289 1290 if (methods == &ehci_device_isoc_fs_methods) { 1291 ehci_sitd_t *td; 1292 1293 /* isochronous full speed transfer */ 1294 1295 td = xfer->td_transfer_last; 1296 usb2_pc_cpu_invalidate(td->page_cache); 1297 status = le32toh(td->sitd_status); 1298 1299 /* also check if first is complete */ 1300 1301 td = xfer->td_transfer_first; 1302 usb2_pc_cpu_invalidate(td->page_cache); 1303 status |= le32toh(td->sitd_status); 1304 1305 if (!(status & EHCI_SITD_ACTIVE)) { 1306 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1307 goto transferred; 1308 } 1309 } else if (methods == &ehci_device_isoc_hs_methods) { 1310 ehci_itd_t *td; 1311 1312 /* isochronous high speed transfer */ 1313 1314 td = xfer->td_transfer_last; 1315 usb2_pc_cpu_invalidate(td->page_cache); 1316 status = 1317 td->itd_status[0] | td->itd_status[1] | 1318 td->itd_status[2] | td->itd_status[3] | 1319 td->itd_status[4] | td->itd_status[5] | 1320 td->itd_status[6] | td->itd_status[7]; 1321 1322 /* also check first transfer */ 1323 td = xfer->td_transfer_first; 1324 usb2_pc_cpu_invalidate(td->page_cache); 1325 status |= 1326 td->itd_status[0] | td->itd_status[1] | 1327 td->itd_status[2] | td->itd_status[3] | 1328 td->itd_status[4] | td->itd_status[5] | 1329 td->itd_status[6] | td->itd_status[7]; 1330 1331 /* if no transactions are active we continue */ 1332 if (!(status & htole32(EHCI_ITD_ACTIVE))) { 1333 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1334 goto transferred; 1335 } 1336 } else { 1337 ehci_qtd_t *td; 1338 1339 /* non-isochronous transfer */ 1340 1341 /* 1342 * check whether there is an error somewhere in the middle, 1343 * or whether there was a short packet (SPD and not ACTIVE) 1344 */ 1345 td = xfer->td_transfer_cache; 1346 1347 while (1) { 1348 usb2_pc_cpu_invalidate(td->page_cache); 1349 status = le32toh(td->qtd_status); 1350 1351 /* 1352 * if there is an active TD the transfer isn't done 1353 */ 1354 if (status & EHCI_QTD_ACTIVE) { 1355 /* update cache */ 1356 xfer->td_transfer_cache = td; 1357 goto done; 1358 } 1359 /* 1360 * last transfer descriptor makes the transfer done 1361 */ 1362 if (((void *)td) == xfer->td_transfer_last) { 1363 break; 1364 } 1365 /* 1366 * any kind of error makes the transfer done 1367 */ 1368 if (status & EHCI_QTD_HALTED) { 1369 break; 1370 } 1371 /* 1372 * if there is no alternate next transfer, a short 1373 * packet also makes the transfer done 1374 */ 1375 if (EHCI_QTD_GET_BYTES(status)) { 1376 if (xfer->flags_int.short_frames_ok) { 1377 /* follow alt next */ 1378 if (td->alt_next) { 1379 td = td->alt_next; 1380 continue; 1381 } 1382 } 1383 /* transfer is done */ 1384 break; 1385 } 1386 td = td->obj_next; 1387 } 1388 ehci_non_isoc_done(xfer); 1389 goto transferred; 1390 } 1391 1392done: 1393 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1394 return (0); 1395 1396transferred: 1397 return (1); 1398} 1399 1400static void 1401ehci_pcd_enable(ehci_softc_t *sc) 1402{ 1403 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1404 1405 sc->sc_eintrs |= EHCI_STS_PCD; 1406 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1407 1408 /* acknowledge any PCD interrupt */ 1409 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD); 1410 1411 usb2_sw_transfer(&sc->sc_root_intr, 1412 &ehci_root_intr_done); 1413} 1414 1415static void 1416ehci_interrupt_poll(ehci_softc_t *sc) 1417{ 1418 struct usb2_xfer *xfer; 1419 1420repeat: 1421 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1422 /* 1423 * check if transfer is transferred 1424 */ 1425 if (ehci_check_transfer(xfer)) { 1426 /* queue has been modified */ 1427 goto repeat; 1428 } 1429 } 1430} 1431 1432/*------------------------------------------------------------------------* 1433 * ehci_interrupt - EHCI interrupt handler 1434 * 1435 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1436 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1437 * is present ! 1438 *------------------------------------------------------------------------*/ 1439void 1440ehci_interrupt(ehci_softc_t *sc) 1441{ 1442 uint32_t status; 1443 1444 USB_BUS_LOCK(&sc->sc_bus); 1445 1446 DPRINTFN(16, "real interrupt\n"); 1447 1448#if USB_DEBUG 1449 if (ehcidebug > 15) { 1450 ehci_dump_regs(sc); 1451 } 1452#endif 1453 1454 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1455 if (status == 0) { 1456 /* the interrupt was not for us */ 1457 goto done; 1458 } 1459 if (!(status & sc->sc_eintrs)) { 1460 goto done; 1461 } 1462 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */ 1463 1464 status &= sc->sc_eintrs; 1465 1466 if (status & EHCI_STS_HSE) { 1467 printf("%s: unrecoverable error, " 1468 "controller halted\n", __FUNCTION__); 1469#if USB_DEBUG 1470 ehci_dump_regs(sc); 1471 ehci_dump_isoc(sc); 1472#endif 1473 } 1474 if (status & EHCI_STS_PCD) { 1475 /* 1476 * Disable PCD interrupt for now, because it will be 1477 * on until the port has been reset. 1478 */ 1479 sc->sc_eintrs &= ~EHCI_STS_PCD; 1480 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1481 1482 usb2_sw_transfer(&sc->sc_root_intr, 1483 &ehci_root_intr_done); 1484 1485 /* do not allow RHSC interrupts > 1 per second */ 1486 usb2_callout_reset(&sc->sc_tmo_pcd, hz, 1487 (void *)&ehci_pcd_enable, sc); 1488 } 1489 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA); 1490 1491 if (status != 0) { 1492 /* block unprocessed interrupts */ 1493 sc->sc_eintrs &= ~status; 1494 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1495 printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status); 1496 } 1497 /* poll all the USB transfers */ 1498 ehci_interrupt_poll(sc); 1499 1500done: 1501 USB_BUS_UNLOCK(&sc->sc_bus); 1502} 1503 1504/* 1505 * called when a request does not complete 1506 */ 1507static void 1508ehci_timeout(void *arg) 1509{ 1510 struct usb2_xfer *xfer = arg; 1511 1512 DPRINTF("xfer=%p\n", xfer); 1513 1514 USB_BUS_LOCK_ASSERT(xfer->udev->bus, MA_OWNED); 1515 1516 /* transfer is transferred */ 1517 ehci_device_done(xfer, USB_ERR_TIMEOUT); 1518} 1519 1520static void 1521ehci_do_poll(struct usb2_bus *bus) 1522{ 1523 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1524 1525 USB_BUS_LOCK(&sc->sc_bus); 1526 ehci_interrupt_poll(sc); 1527 ehci_root_ctrl_poll(sc); 1528 USB_BUS_UNLOCK(&sc->sc_bus); 1529} 1530 1531static void 1532ehci_setup_standard_chain_sub(struct ehci_std_temp *temp) 1533{ 1534 struct usb2_page_search buf_res; 1535 ehci_qtd_t *td; 1536 ehci_qtd_t *td_next; 1537 ehci_qtd_t *td_alt_next; 1538 uint32_t qtd_altnext; 1539 uint32_t buf_offset; 1540 uint32_t average; 1541 uint32_t len_old; 1542 uint8_t shortpkt_old; 1543 uint8_t precompute; 1544 1545 qtd_altnext = htole32(EHCI_LINK_TERMINATE); 1546 td_alt_next = NULL; 1547 buf_offset = 0; 1548 shortpkt_old = temp->shortpkt; 1549 len_old = temp->len; 1550 precompute = 1; 1551 1552restart: 1553 1554 td = temp->td; 1555 td_next = temp->td_next; 1556 1557 while (1) { 1558 1559 if (temp->len == 0) { 1560 1561 if (temp->shortpkt) { 1562 break; 1563 } 1564 /* send a Zero Length Packet, ZLP, last */ 1565 1566 temp->shortpkt = 1; 1567 average = 0; 1568 1569 } else { 1570 1571 average = temp->average; 1572 1573 if (temp->len < average) { 1574 if (temp->len % temp->max_frame_size) { 1575 temp->shortpkt = 1; 1576 } 1577 average = temp->len; 1578 } 1579 } 1580 1581 if (td_next == NULL) { 1582 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__); 1583 } 1584 /* get next TD */ 1585 1586 td = td_next; 1587 td_next = td->obj_next; 1588 1589 /* check if we are pre-computing */ 1590 1591 if (precompute) { 1592 1593 /* update remaining length */ 1594 1595 temp->len -= average; 1596 1597 continue; 1598 } 1599 /* fill out current TD */ 1600 1601 td->qtd_status = 1602 temp->qtd_status | htole32(EHCI_QTD_SET_BYTES(average)); 1603 1604 if (average == 0) { 1605 1606 if (temp->auto_data_toggle == 0) { 1607 1608 /* update data toggle, ZLP case */ 1609 1610 temp->qtd_status ^= htole32(EHCI_QTD_TOGGLE_MASK); 1611 } 1612 td->len = 0; 1613 1614 td->qtd_buffer[0] = 0; 1615 td->qtd_buffer_hi[0] = 0; 1616 1617 td->qtd_buffer[1] = 0; 1618 td->qtd_buffer_hi[1] = 0; 1619 1620 } else { 1621 1622 uint8_t x; 1623 1624 if (temp->auto_data_toggle == 0) { 1625 1626 /* update data toggle */ 1627 1628 if (((average + temp->max_frame_size - 1) / 1629 temp->max_frame_size) & 1) { 1630 temp->qtd_status ^= htole32(EHCI_QTD_TOGGLE_MASK); 1631 } 1632 } 1633 td->len = average; 1634 1635 /* update remaining length */ 1636 1637 temp->len -= average; 1638 1639 /* fill out buffer pointers */ 1640 1641 usb2_get_page(temp->pc, buf_offset, &buf_res); 1642 td->qtd_buffer[0] = htole32(buf_res.physaddr); 1643 td->qtd_buffer_hi[0] = 0; 1644 1645 x = 1; 1646 1647 while (average > EHCI_PAGE_SIZE) { 1648 average -= EHCI_PAGE_SIZE; 1649 buf_offset += EHCI_PAGE_SIZE; 1650 usb2_get_page(temp->pc, buf_offset, &buf_res); 1651 td->qtd_buffer[x] = htole32(buf_res.physaddr & (~0xFFF)); 1652 td->qtd_buffer_hi[x] = 0; 1653 x++; 1654 } 1655 1656 /* 1657 * NOTE: The "average" variable is never zero after 1658 * exiting the loop above ! 1659 * 1660 * NOTE: We have to subtract one from the offset to 1661 * ensure that we are computing the physical address 1662 * of a valid page ! 1663 */ 1664 buf_offset += average; 1665 usb2_get_page(temp->pc, buf_offset - 1, &buf_res); 1666 td->qtd_buffer[x] = htole32(buf_res.physaddr & (~0xFFF)); 1667 td->qtd_buffer_hi[x] = 0; 1668 } 1669 1670 if (td_next) { 1671 /* link the current TD with the next one */ 1672 td->qtd_next = td_next->qtd_self; 1673 } 1674 td->qtd_altnext = qtd_altnext; 1675 td->alt_next = td_alt_next; 1676 1677 usb2_pc_cpu_flush(td->page_cache); 1678 } 1679 1680 if (precompute) { 1681 precompute = 0; 1682 1683 /* setup alt next pointer, if any */ 1684 if (temp->short_frames_ok) { 1685 if (temp->setup_alt_next) { 1686 td_alt_next = td_next; 1687 qtd_altnext = td_next->qtd_self; 1688 } 1689 } else { 1690 /* we use this field internally */ 1691 td_alt_next = td_next; 1692 } 1693 1694 /* restore */ 1695 temp->shortpkt = shortpkt_old; 1696 temp->len = len_old; 1697 goto restart; 1698 } 1699 temp->td = td; 1700 temp->td_next = td_next; 1701} 1702 1703static void 1704ehci_setup_standard_chain(struct usb2_xfer *xfer, ehci_qh_t **qh_last) 1705{ 1706 struct ehci_std_temp temp; 1707 struct usb2_pipe_methods *methods; 1708 ehci_qh_t *qh; 1709 ehci_qtd_t *td; 1710 uint32_t qh_endp; 1711 uint32_t qh_endphub; 1712 uint32_t x; 1713 1714 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1715 xfer->address, UE_GET_ADDR(xfer->endpoint), 1716 xfer->sumlen, usb2_get_speed(xfer->udev)); 1717 1718 temp.average = xfer->max_usb2_frame_size; 1719 temp.max_frame_size = xfer->max_frame_size; 1720 1721 /* toggle the DMA set we are using */ 1722 xfer->flags_int.curr_dma_set ^= 1; 1723 1724 /* get next DMA set */ 1725 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1726 1727 xfer->td_transfer_first = td; 1728 xfer->td_transfer_cache = td; 1729 1730 temp.td = NULL; 1731 temp.td_next = td; 1732 temp.qtd_status = 0; 1733 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1734 temp.short_frames_ok = xfer->flags_int.short_frames_ok; 1735 1736 if (xfer->flags_int.control_xfr) { 1737 if (xfer->pipe->toggle_next) { 1738 /* DATA1 is next */ 1739 temp.qtd_status |= htole32(EHCI_QTD_SET_TOGGLE(1)); 1740 } 1741 temp.auto_data_toggle = 0; 1742 } else { 1743 temp.auto_data_toggle = 1; 1744 } 1745 1746 if (usb2_get_speed(xfer->udev) != USB_SPEED_HIGH) { 1747 /* max 3 retries */ 1748 temp.qtd_status |= htole32(EHCI_QTD_SET_CERR(3)); 1749 } 1750 /* check if we should prepend a setup message */ 1751 1752 if (xfer->flags_int.control_xfr) { 1753 if (xfer->flags_int.control_hdr) { 1754 1755 temp.qtd_status &= htole32(EHCI_QTD_SET_CERR(3)); 1756 temp.qtd_status |= htole32 1757 (EHCI_QTD_ACTIVE | 1758 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 1759 EHCI_QTD_SET_TOGGLE(0)); 1760 1761 temp.len = xfer->frlengths[0]; 1762 temp.pc = xfer->frbuffers + 0; 1763 temp.shortpkt = temp.len ? 1 : 0; 1764 1765 ehci_setup_standard_chain_sub(&temp); 1766 } 1767 x = 1; 1768 } else { 1769 x = 0; 1770 } 1771 1772 while (x != xfer->nframes) { 1773 1774 /* DATA0 / DATA1 message */ 1775 1776 temp.len = xfer->frlengths[x]; 1777 temp.pc = xfer->frbuffers + x; 1778 1779 x++; 1780 1781 if (x == xfer->nframes) { 1782 temp.setup_alt_next = 0; 1783 } 1784 /* keep previous data toggle and error count */ 1785 1786 temp.qtd_status &= htole32(EHCI_QTD_SET_CERR(3) | 1787 EHCI_QTD_SET_TOGGLE(1)); 1788 1789 if (temp.len == 0) { 1790 1791 /* make sure that we send an USB packet */ 1792 1793 temp.shortpkt = 0; 1794 1795 } else { 1796 1797 /* regular data transfer */ 1798 1799 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1800 } 1801 1802 /* set endpoint direction */ 1803 1804 temp.qtd_status |= 1805 (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) ? 1806 htole32(EHCI_QTD_ACTIVE | 1807 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) : 1808 htole32(EHCI_QTD_ACTIVE | 1809 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT)); 1810 1811 ehci_setup_standard_chain_sub(&temp); 1812 } 1813 1814 /* check if we should append a status stage */ 1815 1816 if (xfer->flags_int.control_xfr && 1817 !xfer->flags_int.control_act) { 1818 1819 /* 1820 * Send a DATA1 message and invert the current endpoint 1821 * direction. 1822 */ 1823 1824 temp.qtd_status &= htole32(EHCI_QTD_SET_CERR(3) | 1825 EHCI_QTD_SET_TOGGLE(1)); 1826 temp.qtd_status |= 1827 (UE_GET_DIR(xfer->endpoint) == UE_DIR_OUT) ? 1828 htole32(EHCI_QTD_ACTIVE | 1829 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) | 1830 EHCI_QTD_SET_TOGGLE(1)) : 1831 htole32(EHCI_QTD_ACTIVE | 1832 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) | 1833 EHCI_QTD_SET_TOGGLE(1)); 1834 1835 temp.len = 0; 1836 temp.pc = NULL; 1837 temp.shortpkt = 0; 1838 1839 ehci_setup_standard_chain_sub(&temp); 1840 } 1841 td = temp.td; 1842 1843 /* the last TD terminates the transfer: */ 1844 td->qtd_next = htole32(EHCI_LINK_TERMINATE); 1845 td->qtd_altnext = htole32(EHCI_LINK_TERMINATE); 1846 td->qtd_status |= htole32(EHCI_QTD_IOC); 1847 1848 usb2_pc_cpu_flush(td->page_cache); 1849 1850 /* must have at least one frame! */ 1851 1852 xfer->td_transfer_last = td; 1853 1854#if USB_DEBUG 1855 if (ehcidebug > 8) { 1856 DPRINTF("nexttog=%d; data before transfer:\n", 1857 xfer->pipe->toggle_next); 1858 ehci_dump_sqtds(xfer->td_transfer_first); 1859 } 1860#endif 1861 1862 methods = xfer->pipe->methods; 1863 1864 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1865 1866 /* the "qh_link" field is filled when the QH is added */ 1867 1868 qh_endp = 1869 (EHCI_QH_SET_ADDR(xfer->address) | 1870 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpoint)) | 1871 EHCI_QH_SET_MPL(xfer->max_packet_size)); 1872 1873 if (usb2_get_speed(xfer->udev) == USB_SPEED_HIGH) { 1874 qh_endp |= (EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | 1875 EHCI_QH_DTC | EHCI_QH_SET_NRL(8)); 1876 } else { 1877 1878 if (usb2_get_speed(xfer->udev) == USB_SPEED_FULL) { 1879 qh_endp |= (EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL) | 1880 EHCI_QH_DTC); 1881 } else { 1882 qh_endp |= (EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW) | 1883 EHCI_QH_DTC); 1884 } 1885 1886 if (methods == &ehci_device_ctrl_methods) { 1887 qh_endp |= EHCI_QH_CTL; 1888 } 1889 if (methods != &ehci_device_intr_methods) { 1890 /* Only try one time per microframe! */ 1891 qh_endp |= EHCI_QH_SET_NRL(1); 1892 } 1893 } 1894 1895 qh->qh_endp = htole32(qh_endp); 1896 1897 qh_endphub = 1898 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) | 1899 EHCI_QH_SET_CMASK(xfer->usb2_cmask) | 1900 EHCI_QH_SET_SMASK(xfer->usb2_smask) | 1901 EHCI_QH_SET_HUBA(xfer->udev->hs_hub_addr) | 1902 EHCI_QH_SET_PORT(xfer->udev->hs_port_no)); 1903 1904 qh->qh_endphub = htole32(qh_endphub); 1905 qh->qh_curqtd = htole32(0); 1906 1907 /* fill the overlay qTD */ 1908 qh->qh_qtd.qtd_status = htole32(0); 1909 1910 if (temp.auto_data_toggle) { 1911 1912 /* let the hardware compute the data toggle */ 1913 1914 qh->qh_endp &= ~htole32(EHCI_QH_DTC); 1915 1916 if (xfer->pipe->toggle_next) { 1917 /* DATA1 is next */ 1918 qh->qh_qtd.qtd_status |= htole32(EHCI_QTD_SET_TOGGLE(1)); 1919 } 1920 } 1921 td = xfer->td_transfer_first; 1922 1923 qh->qh_qtd.qtd_next = td->qtd_self; 1924 qh->qh_qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 1925 1926 usb2_pc_cpu_flush(qh->page_cache); 1927 1928 EHCI_APPEND_QH(qh, *qh_last); 1929} 1930 1931static void 1932ehci_root_intr_done(struct usb2_xfer *xfer, 1933 struct usb2_sw_transfer *std) 1934{ 1935 struct ehci_softc *sc = xfer->usb2_sc; 1936 uint16_t i; 1937 uint16_t m; 1938 1939 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1940 1941 if (std->state != USB_SW_TR_PRE_DATA) { 1942 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1943 /* transfer transferred */ 1944 ehci_device_done(xfer, std->err); 1945 } 1946 goto done; 1947 } 1948 /* setup buffer */ 1949 std->ptr = sc->sc_hub_idata; 1950 std->len = sizeof(sc->sc_hub_idata); 1951 1952 /* clear any old interrupt data */ 1953 bzero(sc->sc_hub_idata, sizeof(sc->sc_hub_idata)); 1954 1955 /* set bits */ 1956 m = (sc->sc_noport + 1); 1957 if (m > (8 * sizeof(sc->sc_hub_idata))) { 1958 m = (8 * sizeof(sc->sc_hub_idata)); 1959 } 1960 for (i = 1; i < m; i++) { 1961 /* pick out CHANGE bits from the status register */ 1962 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) { 1963 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 1964 DPRINTF("port %d changed\n", i); 1965 } 1966 } 1967done: 1968 return; 1969} 1970 1971static void 1972ehci_isoc_fs_done(ehci_softc_t *sc, struct usb2_xfer *xfer) 1973{ 1974 uint32_t nframes = xfer->nframes; 1975 uint32_t status; 1976 uint32_t *plen = xfer->frlengths; 1977 uint16_t len = 0; 1978 ehci_sitd_t *td = xfer->td_transfer_first; 1979 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos]; 1980 1981 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1982 xfer, xfer->pipe); 1983 1984 while (nframes--) { 1985 if (td == NULL) { 1986 panic("%s:%d: out of TD's\n", 1987 __FUNCTION__, __LINE__); 1988 } 1989 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 1990 pp_last = &sc->sc_isoc_fs_p_last[0]; 1991 } 1992#if USB_DEBUG 1993 if (ehcidebug > 15) { 1994 DPRINTF("isoc FS-TD\n"); 1995 ehci_dump_sitd(td); 1996 } 1997#endif 1998 usb2_pc_cpu_invalidate(td->page_cache); 1999 status = le32toh(td->sitd_status); 2000 2001 len = EHCI_SITD_GET_LEN(status); 2002 2003 if (*plen >= len) { 2004 len = *plen - len; 2005 } else { 2006 len = 0; 2007 } 2008 2009 *plen = len; 2010 2011 /* remove FS-TD from schedule */ 2012 EHCI_REMOVE_FS_TD(td, *pp_last); 2013 2014 pp_last++; 2015 plen++; 2016 td = td->obj_next; 2017 } 2018 2019 xfer->aframes = xfer->nframes; 2020} 2021 2022static void 2023ehci_isoc_hs_done(ehci_softc_t *sc, struct usb2_xfer *xfer) 2024{ 2025 uint32_t nframes = xfer->nframes; 2026 uint32_t status; 2027 uint32_t *plen = xfer->frlengths; 2028 uint16_t len = 0; 2029 uint8_t td_no = 0; 2030 ehci_itd_t *td = xfer->td_transfer_first; 2031 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos]; 2032 2033 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 2034 xfer, xfer->pipe); 2035 2036 while (nframes--) { 2037 if (td == NULL) { 2038 panic("%s:%d: out of TD's\n", 2039 __FUNCTION__, __LINE__); 2040 } 2041 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2042 pp_last = &sc->sc_isoc_hs_p_last[0]; 2043 } 2044#if USB_DEBUG 2045 if (ehcidebug > 15) { 2046 DPRINTF("isoc HS-TD\n"); 2047 ehci_dump_itd(td); 2048 } 2049#endif 2050 2051 usb2_pc_cpu_invalidate(td->page_cache); 2052 status = le32toh(td->itd_status[td_no]); 2053 2054 len = EHCI_ITD_GET_LEN(status); 2055 2056 if (*plen >= len) { 2057 /* 2058 * The length is valid. NOTE: The complete 2059 * length is written back into the status 2060 * field, and not the remainder like with 2061 * other transfer descriptor types. 2062 */ 2063 } else { 2064 /* Invalid length - truncate */ 2065 len = 0; 2066 } 2067 2068 *plen = len; 2069 2070 plen++; 2071 td_no++; 2072 2073 if ((td_no == 8) || (nframes == 0)) { 2074 /* remove HS-TD from schedule */ 2075 EHCI_REMOVE_HS_TD(td, *pp_last); 2076 pp_last++; 2077 2078 td_no = 0; 2079 td = td->obj_next; 2080 } 2081 } 2082 xfer->aframes = xfer->nframes; 2083} 2084 2085/* NOTE: "done" can be run two times in a row, 2086 * from close and from interrupt 2087 */ 2088static void 2089ehci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 2090{ 2091 struct usb2_pipe_methods *methods = xfer->pipe->methods; 2092 ehci_softc_t *sc = xfer->usb2_sc; 2093 2094 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2095 2096 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 2097 xfer, xfer->pipe, error); 2098 2099 if ((methods == &ehci_device_bulk_methods) || 2100 (methods == &ehci_device_ctrl_methods)) { 2101#if USB_DEBUG 2102 if (ehcidebug > 8) { 2103 DPRINTF("nexttog=%d; data after transfer:\n", 2104 xfer->pipe->toggle_next); 2105 ehci_dump_sqtds(xfer->td_transfer_first); 2106 } 2107#endif 2108 2109 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2110 sc->sc_async_p_last); 2111 } 2112 if (methods == &ehci_device_intr_methods) { 2113 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2114 sc->sc_intr_p_last[xfer->qh_pos]); 2115 } 2116 /* 2117 * Only finish isochronous transfers once which will update 2118 * "xfer->frlengths". 2119 */ 2120 if (xfer->td_transfer_first && 2121 xfer->td_transfer_last) { 2122 if (methods == &ehci_device_isoc_fs_methods) { 2123 ehci_isoc_fs_done(sc, xfer); 2124 } 2125 if (methods == &ehci_device_isoc_hs_methods) { 2126 ehci_isoc_hs_done(sc, xfer); 2127 } 2128 xfer->td_transfer_first = NULL; 2129 xfer->td_transfer_last = NULL; 2130 } 2131 /* dequeue transfer and start next transfer */ 2132 usb2_transfer_done(xfer, error); 2133} 2134 2135/*------------------------------------------------------------------------* 2136 * ehci bulk support 2137 *------------------------------------------------------------------------*/ 2138static void 2139ehci_device_bulk_open(struct usb2_xfer *xfer) 2140{ 2141 return; 2142} 2143 2144static void 2145ehci_device_bulk_close(struct usb2_xfer *xfer) 2146{ 2147 ehci_device_done(xfer, USB_ERR_CANCELLED); 2148} 2149 2150static void 2151ehci_device_bulk_enter(struct usb2_xfer *xfer) 2152{ 2153 return; 2154} 2155 2156static void 2157ehci_device_bulk_start(struct usb2_xfer *xfer) 2158{ 2159 ehci_softc_t *sc = xfer->usb2_sc; 2160 2161 /* setup TD's and QH */ 2162 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2163 2164 /* put transfer on interrupt queue */ 2165 ehci_transfer_intr_enqueue(xfer); 2166} 2167 2168struct usb2_pipe_methods ehci_device_bulk_methods = 2169{ 2170 .open = ehci_device_bulk_open, 2171 .close = ehci_device_bulk_close, 2172 .enter = ehci_device_bulk_enter, 2173 .start = ehci_device_bulk_start, 2174 .enter_is_cancelable = 1, 2175 .start_is_cancelable = 1, 2176}; 2177 2178/*------------------------------------------------------------------------* 2179 * ehci control support 2180 *------------------------------------------------------------------------*/ 2181static void 2182ehci_device_ctrl_open(struct usb2_xfer *xfer) 2183{ 2184 return; 2185} 2186 2187static void 2188ehci_device_ctrl_close(struct usb2_xfer *xfer) 2189{ 2190 ehci_device_done(xfer, USB_ERR_CANCELLED); 2191} 2192 2193static void 2194ehci_device_ctrl_enter(struct usb2_xfer *xfer) 2195{ 2196 return; 2197} 2198 2199static void 2200ehci_device_ctrl_start(struct usb2_xfer *xfer) 2201{ 2202 ehci_softc_t *sc = xfer->usb2_sc; 2203 2204 /* setup TD's and QH */ 2205 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2206 2207 /* put transfer on interrupt queue */ 2208 ehci_transfer_intr_enqueue(xfer); 2209} 2210 2211struct usb2_pipe_methods ehci_device_ctrl_methods = 2212{ 2213 .open = ehci_device_ctrl_open, 2214 .close = ehci_device_ctrl_close, 2215 .enter = ehci_device_ctrl_enter, 2216 .start = ehci_device_ctrl_start, 2217 .enter_is_cancelable = 1, 2218 .start_is_cancelable = 1, 2219}; 2220 2221/*------------------------------------------------------------------------* 2222 * ehci interrupt support 2223 *------------------------------------------------------------------------*/ 2224static void 2225ehci_device_intr_open(struct usb2_xfer *xfer) 2226{ 2227 ehci_softc_t *sc = xfer->usb2_sc; 2228 uint16_t best; 2229 uint16_t bit; 2230 uint16_t x; 2231 uint8_t slot; 2232 2233 /* Allocate a microframe slot first: */ 2234 2235 slot = usb2_intr_schedule_adjust 2236 (xfer->udev, xfer->max_frame_size, USB_HS_MICRO_FRAMES_MAX); 2237 2238 if (usb2_get_speed(xfer->udev) == USB_SPEED_HIGH) { 2239 xfer->usb2_uframe = slot; 2240 xfer->usb2_smask = (1 << slot) & 0xFF; 2241 xfer->usb2_cmask = 0; 2242 } else { 2243 xfer->usb2_uframe = slot; 2244 xfer->usb2_smask = (1 << slot) & 0x3F; 2245 xfer->usb2_cmask = (-(4 << slot)) & 0xFE; 2246 } 2247 2248 /* 2249 * Find the best QH position corresponding to the given interval: 2250 */ 2251 2252 best = 0; 2253 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 2254 while (bit) { 2255 if (xfer->interval >= bit) { 2256 x = bit; 2257 best = bit; 2258 while (x & bit) { 2259 if (sc->sc_intr_stat[x] < 2260 sc->sc_intr_stat[best]) { 2261 best = x; 2262 } 2263 x++; 2264 } 2265 break; 2266 } 2267 bit >>= 1; 2268 } 2269 2270 sc->sc_intr_stat[best]++; 2271 xfer->qh_pos = best; 2272 2273 DPRINTFN(3, "best=%d interval=%d\n", 2274 best, xfer->interval); 2275} 2276 2277static void 2278ehci_device_intr_close(struct usb2_xfer *xfer) 2279{ 2280 ehci_softc_t *sc = xfer->usb2_sc; 2281 uint8_t slot; 2282 2283 slot = usb2_intr_schedule_adjust 2284 (xfer->udev, -(xfer->max_frame_size), xfer->usb2_uframe); 2285 2286 sc->sc_intr_stat[xfer->qh_pos]--; 2287 2288 ehci_device_done(xfer, USB_ERR_CANCELLED); 2289} 2290 2291static void 2292ehci_device_intr_enter(struct usb2_xfer *xfer) 2293{ 2294 return; 2295} 2296 2297static void 2298ehci_device_intr_start(struct usb2_xfer *xfer) 2299{ 2300 ehci_softc_t *sc = xfer->usb2_sc; 2301 2302 /* setup TD's and QH */ 2303 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 2304 2305 /* put transfer on interrupt queue */ 2306 ehci_transfer_intr_enqueue(xfer); 2307} 2308 2309struct usb2_pipe_methods ehci_device_intr_methods = 2310{ 2311 .open = ehci_device_intr_open, 2312 .close = ehci_device_intr_close, 2313 .enter = ehci_device_intr_enter, 2314 .start = ehci_device_intr_start, 2315 .enter_is_cancelable = 1, 2316 .start_is_cancelable = 1, 2317}; 2318 2319/*------------------------------------------------------------------------* 2320 * ehci full speed isochronous support 2321 *------------------------------------------------------------------------*/ 2322static void 2323ehci_device_isoc_fs_open(struct usb2_xfer *xfer) 2324{ 2325 ehci_sitd_t *td; 2326 uint32_t sitd_portaddr; 2327 uint8_t ds; 2328 2329 sitd_portaddr = 2330 EHCI_SITD_SET_ADDR(xfer->address) | 2331 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpoint)) | 2332 EHCI_SITD_SET_HUBA(xfer->udev->hs_hub_addr) | 2333 EHCI_SITD_SET_PORT(xfer->udev->hs_port_no); 2334 2335 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 2336 sitd_portaddr |= EHCI_SITD_SET_DIR_IN; 2337 } 2338 sitd_portaddr = htole32(sitd_portaddr); 2339 2340 /* initialize all TD's */ 2341 2342 for (ds = 0; ds != 2; ds++) { 2343 2344 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2345 2346 td->sitd_portaddr = sitd_portaddr; 2347 2348 /* 2349 * TODO: make some kind of automatic 2350 * SMASK/CMASK selection based on micro-frame 2351 * usage 2352 * 2353 * micro-frame usage (8 microframes per 1ms) 2354 */ 2355 td->sitd_back = htole32(EHCI_LINK_TERMINATE); 2356 2357 usb2_pc_cpu_flush(td->page_cache); 2358 } 2359 } 2360} 2361 2362static void 2363ehci_device_isoc_fs_close(struct usb2_xfer *xfer) 2364{ 2365 ehci_device_done(xfer, USB_ERR_CANCELLED); 2366} 2367 2368static void 2369ehci_device_isoc_fs_enter(struct usb2_xfer *xfer) 2370{ 2371 struct usb2_page_search buf_res; 2372 ehci_softc_t *sc = xfer->usb2_sc; 2373 struct usb2_fs_isoc_schedule *fss_start; 2374 struct usb2_fs_isoc_schedule *fss_end; 2375 struct usb2_fs_isoc_schedule *fss; 2376 ehci_sitd_t *td; 2377 ehci_sitd_t *td_last = NULL; 2378 ehci_sitd_t **pp_last; 2379 uint32_t *plen; 2380 uint32_t buf_offset; 2381 uint32_t nframes; 2382 uint32_t temp; 2383 uint32_t sitd_mask; 2384 uint16_t tlen; 2385 uint8_t sa; 2386 uint8_t sb; 2387 uint8_t error; 2388 2389#if USB_DEBUG 2390 uint8_t once = 1; 2391 2392#endif 2393 2394 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2395 xfer, xfer->pipe->isoc_next, xfer->nframes); 2396 2397 /* get the current frame index */ 2398 2399 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2400 2401 /* 2402 * check if the frame index is within the window where the frames 2403 * will be inserted 2404 */ 2405 buf_offset = (nframes - xfer->pipe->isoc_next) & 2406 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2407 2408 if ((xfer->pipe->is_synced == 0) || 2409 (buf_offset < xfer->nframes)) { 2410 /* 2411 * If there is data underflow or the pipe queue is empty we 2412 * schedule the transfer a few frames ahead of the current 2413 * frame position. Else two isochronous transfers might 2414 * overlap. 2415 */ 2416 xfer->pipe->isoc_next = (nframes + 3) & 2417 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2418 xfer->pipe->is_synced = 1; 2419 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 2420 } 2421 /* 2422 * compute how many milliseconds the insertion is ahead of the 2423 * current frame position: 2424 */ 2425 buf_offset = (xfer->pipe->isoc_next - nframes) & 2426 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2427 2428 /* 2429 * pre-compute when the isochronous transfer will be finished: 2430 */ 2431 xfer->isoc_time_complete = 2432 usb2_fs_isoc_schedule_isoc_time_expand 2433 (xfer->udev, &fss_start, &fss_end, nframes) + buf_offset + 2434 xfer->nframes; 2435 2436 /* get the real number of frames */ 2437 2438 nframes = xfer->nframes; 2439 2440 buf_offset = 0; 2441 2442 plen = xfer->frlengths; 2443 2444 /* toggle the DMA set we are using */ 2445 xfer->flags_int.curr_dma_set ^= 1; 2446 2447 /* get next DMA set */ 2448 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2449 xfer->td_transfer_first = td; 2450 2451 pp_last = &sc->sc_isoc_fs_p_last[xfer->pipe->isoc_next]; 2452 2453 /* store starting position */ 2454 2455 xfer->qh_pos = xfer->pipe->isoc_next; 2456 2457 fss = fss_start + (xfer->qh_pos % USB_ISOC_TIME_MAX); 2458 2459 while (nframes--) { 2460 if (td == NULL) { 2461 panic("%s:%d: out of TD's\n", 2462 __FUNCTION__, __LINE__); 2463 } 2464 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2465 pp_last = &sc->sc_isoc_fs_p_last[0]; 2466 } 2467 if (fss >= fss_end) { 2468 fss = fss_start; 2469 } 2470 /* reuse sitd_portaddr and sitd_back from last transfer */ 2471 2472 if (*plen > xfer->max_frame_size) { 2473#if USB_DEBUG 2474 if (once) { 2475 once = 0; 2476 printf("%s: frame length(%d) exceeds %d " 2477 "bytes (frame truncated)\n", 2478 __FUNCTION__, *plen, 2479 xfer->max_frame_size); 2480 } 2481#endif 2482 *plen = xfer->max_frame_size; 2483 } 2484 /* 2485 * We currently don't care if the ISOCHRONOUS schedule is 2486 * full! 2487 */ 2488 error = usb2_fs_isoc_schedule_alloc(fss, &sa, *plen); 2489 if (error) { 2490 /* 2491 * The FULL speed schedule is FULL! Set length 2492 * to zero. 2493 */ 2494 *plen = 0; 2495 } 2496 if (*plen) { 2497 /* 2498 * only call "usb2_get_page()" when we have a 2499 * non-zero length 2500 */ 2501 usb2_get_page(xfer->frbuffers, buf_offset, &buf_res); 2502 td->sitd_bp[0] = htole32(buf_res.physaddr); 2503 buf_offset += *plen; 2504 /* 2505 * NOTE: We need to subtract one from the offset so 2506 * that we are on a valid page! 2507 */ 2508 usb2_get_page(xfer->frbuffers, buf_offset - 1, 2509 &buf_res); 2510 temp = buf_res.physaddr & ~0xFFF; 2511 } else { 2512 td->sitd_bp[0] = 0; 2513 temp = 0; 2514 } 2515 2516 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_OUT) { 2517 tlen = *plen; 2518 if (tlen <= 188) { 2519 temp |= 1; /* T-count = 1, TP = ALL */ 2520 tlen = 1; 2521 } else { 2522 tlen += 187; 2523 tlen /= 188; 2524 temp |= tlen; /* T-count = [1..6] */ 2525 temp |= 8; /* TP = Begin */ 2526 } 2527 2528 tlen += sa; 2529 2530 if (tlen >= 8) { 2531 sb = 0; 2532 } else { 2533 sb = (1 << tlen); 2534 } 2535 2536 sa = (1 << sa); 2537 sa = (sb - sa) & 0x3F; 2538 sb = 0; 2539 } else { 2540 sb = (-(4 << sa)) & 0xFE; 2541 sa = (1 << sa) & 0x3F; 2542 } 2543 2544 sitd_mask = (EHCI_SITD_SET_SMASK(sa) | 2545 EHCI_SITD_SET_CMASK(sb)); 2546 2547 td->sitd_bp[1] = htole32(temp); 2548 2549 td->sitd_mask = htole32(sitd_mask); 2550 2551 if (nframes == 0) { 2552 td->sitd_status = htole32 2553 (EHCI_SITD_IOC | 2554 EHCI_SITD_ACTIVE | 2555 EHCI_SITD_SET_LEN(*plen)); 2556 } else { 2557 td->sitd_status = htole32 2558 (EHCI_SITD_ACTIVE | 2559 EHCI_SITD_SET_LEN(*plen)); 2560 } 2561 usb2_pc_cpu_flush(td->page_cache); 2562 2563#if USB_DEBUG 2564 if (ehcidebug > 15) { 2565 DPRINTF("FS-TD %d\n", nframes); 2566 ehci_dump_sitd(td); 2567 } 2568#endif 2569 /* insert TD into schedule */ 2570 EHCI_APPEND_FS_TD(td, *pp_last); 2571 pp_last++; 2572 2573 plen++; 2574 fss++; 2575 td_last = td; 2576 td = td->obj_next; 2577 } 2578 2579 xfer->td_transfer_last = td_last; 2580 2581 /* update isoc_next */ 2582 xfer->pipe->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) & 2583 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2584} 2585 2586static void 2587ehci_device_isoc_fs_start(struct usb2_xfer *xfer) 2588{ 2589 /* put transfer on interrupt queue */ 2590 ehci_transfer_intr_enqueue(xfer); 2591} 2592 2593struct usb2_pipe_methods ehci_device_isoc_fs_methods = 2594{ 2595 .open = ehci_device_isoc_fs_open, 2596 .close = ehci_device_isoc_fs_close, 2597 .enter = ehci_device_isoc_fs_enter, 2598 .start = ehci_device_isoc_fs_start, 2599 .enter_is_cancelable = 1, 2600 .start_is_cancelable = 1, 2601}; 2602 2603/*------------------------------------------------------------------------* 2604 * ehci high speed isochronous support 2605 *------------------------------------------------------------------------*/ 2606static void 2607ehci_device_isoc_hs_open(struct usb2_xfer *xfer) 2608{ 2609 ehci_itd_t *td; 2610 uint32_t temp; 2611 uint8_t ds; 2612 2613 /* initialize all TD's */ 2614 2615 for (ds = 0; ds != 2; ds++) { 2616 2617 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2618 2619 /* set TD inactive */ 2620 td->itd_status[0] = 0; 2621 td->itd_status[1] = 0; 2622 td->itd_status[2] = 0; 2623 td->itd_status[3] = 0; 2624 td->itd_status[4] = 0; 2625 td->itd_status[5] = 0; 2626 td->itd_status[6] = 0; 2627 td->itd_status[7] = 0; 2628 2629 /* set endpoint and address */ 2630 td->itd_bp[0] = htole32 2631 (EHCI_ITD_SET_ADDR(xfer->address) | 2632 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpoint))); 2633 2634 temp = 2635 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF); 2636 2637 /* set direction */ 2638 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 2639 temp |= EHCI_ITD_SET_DIR_IN; 2640 } 2641 /* set maximum packet size */ 2642 td->itd_bp[1] = htole32(temp); 2643 2644 /* set transfer multiplier */ 2645 td->itd_bp[2] = htole32(xfer->max_packet_count & 3); 2646 2647 usb2_pc_cpu_flush(td->page_cache); 2648 } 2649 } 2650} 2651 2652static void 2653ehci_device_isoc_hs_close(struct usb2_xfer *xfer) 2654{ 2655 ehci_device_done(xfer, USB_ERR_CANCELLED); 2656} 2657 2658static void 2659ehci_device_isoc_hs_enter(struct usb2_xfer *xfer) 2660{ 2661 struct usb2_page_search buf_res; 2662 ehci_softc_t *sc = xfer->usb2_sc; 2663 ehci_itd_t *td; 2664 ehci_itd_t *td_last = NULL; 2665 ehci_itd_t **pp_last; 2666 bus_size_t page_addr; 2667 uint32_t *plen; 2668 uint32_t status; 2669 uint32_t buf_offset; 2670 uint32_t nframes; 2671 uint32_t itd_offset[8 + 1]; 2672 uint8_t x; 2673 uint8_t td_no; 2674 uint8_t page_no; 2675 2676#if USB_DEBUG 2677 uint8_t once = 1; 2678 2679#endif 2680 2681 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2682 xfer, xfer->pipe->isoc_next, xfer->nframes); 2683 2684 /* get the current frame index */ 2685 2686 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2687 2688 /* 2689 * check if the frame index is within the window where the frames 2690 * will be inserted 2691 */ 2692 buf_offset = (nframes - xfer->pipe->isoc_next) & 2693 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2694 2695 if ((xfer->pipe->is_synced == 0) || 2696 (buf_offset < ((xfer->nframes + 7) / 8))) { 2697 /* 2698 * If there is data underflow or the pipe queue is empty we 2699 * schedule the transfer a few frames ahead of the current 2700 * frame position. Else two isochronous transfers might 2701 * overlap. 2702 */ 2703 xfer->pipe->isoc_next = (nframes + 3) & 2704 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2705 xfer->pipe->is_synced = 1; 2706 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 2707 } 2708 /* 2709 * compute how many milliseconds the insertion is ahead of the 2710 * current frame position: 2711 */ 2712 buf_offset = (xfer->pipe->isoc_next - nframes) & 2713 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2714 2715 /* 2716 * pre-compute when the isochronous transfer will be finished: 2717 */ 2718 xfer->isoc_time_complete = 2719 usb2_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 2720 ((xfer->nframes + 7) / 8); 2721 2722 /* get the real number of frames */ 2723 2724 nframes = xfer->nframes; 2725 2726 buf_offset = 0; 2727 td_no = 0; 2728 2729 plen = xfer->frlengths; 2730 2731 /* toggle the DMA set we are using */ 2732 xfer->flags_int.curr_dma_set ^= 1; 2733 2734 /* get next DMA set */ 2735 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2736 xfer->td_transfer_first = td; 2737 2738 pp_last = &sc->sc_isoc_hs_p_last[xfer->pipe->isoc_next]; 2739 2740 /* store starting position */ 2741 2742 xfer->qh_pos = xfer->pipe->isoc_next; 2743 2744 while (nframes--) { 2745 if (td == NULL) { 2746 panic("%s:%d: out of TD's\n", 2747 __FUNCTION__, __LINE__); 2748 } 2749 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2750 pp_last = &sc->sc_isoc_hs_p_last[0]; 2751 } 2752 /* range check */ 2753 if (*plen > xfer->max_frame_size) { 2754#if USB_DEBUG 2755 if (once) { 2756 once = 0; 2757 printf("%s: frame length(%d) exceeds %d bytes " 2758 "(frame truncated)\n", 2759 __FUNCTION__, *plen, xfer->max_frame_size); 2760 } 2761#endif 2762 *plen = xfer->max_frame_size; 2763 } 2764 status = (EHCI_ITD_SET_LEN(*plen) | 2765 EHCI_ITD_ACTIVE | 2766 EHCI_ITD_SET_PG(0)); 2767 td->itd_status[td_no] = htole32(status); 2768 itd_offset[td_no] = buf_offset; 2769 buf_offset += *plen; 2770 plen++; 2771 td_no++; 2772 2773 if ((td_no == 8) || (nframes == 0)) { 2774 2775 /* the rest of the transfers are not active, if any */ 2776 for (x = td_no; x != 8; x++) { 2777 td->itd_status[x] = 0; /* not active */ 2778 } 2779 2780 /* check if there is any data to be transferred */ 2781 if (itd_offset[0] != buf_offset) { 2782 page_no = 0; 2783 itd_offset[td_no] = buf_offset; 2784 2785 /* get first page offset */ 2786 usb2_get_page(xfer->frbuffers, itd_offset[0], &buf_res); 2787 /* get page address */ 2788 page_addr = buf_res.physaddr & ~0xFFF; 2789 /* update page address */ 2790 td->itd_bp[0] &= htole32(0xFFF); 2791 td->itd_bp[0] |= htole32(page_addr); 2792 2793 for (x = 0; x != td_no; x++) { 2794 /* set page number and page offset */ 2795 status = (EHCI_ITD_SET_PG(page_no) | 2796 (buf_res.physaddr & 0xFFF)); 2797 td->itd_status[x] |= htole32(status); 2798 2799 /* get next page offset */ 2800 if (itd_offset[x + 1] == buf_offset) { 2801 /* 2802 * We subtract one so that 2803 * we don't go off the last 2804 * page! 2805 */ 2806 usb2_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 2807 } else { 2808 usb2_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res); 2809 } 2810 2811 /* check if we need a new page */ 2812 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) { 2813 /* new page needed */ 2814 page_addr = buf_res.physaddr & ~0xFFF; 2815 if (page_no == 6) { 2816 panic("%s: too many pages\n", __FUNCTION__); 2817 } 2818 page_no++; 2819 /* update page address */ 2820 td->itd_bp[page_no] &= htole32(0xFFF); 2821 td->itd_bp[page_no] |= htole32(page_addr); 2822 } 2823 } 2824 } 2825 /* set IOC bit if we are complete */ 2826 if (nframes == 0) { 2827 td->itd_status[7] |= htole32(EHCI_ITD_IOC); 2828 } 2829 usb2_pc_cpu_flush(td->page_cache); 2830#if USB_DEBUG 2831 if (ehcidebug > 15) { 2832 DPRINTF("HS-TD %d\n", nframes); 2833 ehci_dump_itd(td); 2834 } 2835#endif 2836 /* insert TD into schedule */ 2837 EHCI_APPEND_HS_TD(td, *pp_last); 2838 pp_last++; 2839 2840 td_no = 0; 2841 td_last = td; 2842 td = td->obj_next; 2843 } 2844 } 2845 2846 xfer->td_transfer_last = td_last; 2847 2848 /* update isoc_next */ 2849 xfer->pipe->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) & 2850 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2851} 2852 2853static void 2854ehci_device_isoc_hs_start(struct usb2_xfer *xfer) 2855{ 2856 /* put transfer on interrupt queue */ 2857 ehci_transfer_intr_enqueue(xfer); 2858} 2859 2860struct usb2_pipe_methods ehci_device_isoc_hs_methods = 2861{ 2862 .open = ehci_device_isoc_hs_open, 2863 .close = ehci_device_isoc_hs_close, 2864 .enter = ehci_device_isoc_hs_enter, 2865 .start = ehci_device_isoc_hs_start, 2866 .enter_is_cancelable = 1, 2867 .start_is_cancelable = 1, 2868}; 2869 2870/*------------------------------------------------------------------------* 2871 * ehci root control support 2872 *------------------------------------------------------------------------* 2873 * simulate a hardware hub by handling 2874 * all the necessary requests 2875 *------------------------------------------------------------------------*/ 2876 2877static void 2878ehci_root_ctrl_open(struct usb2_xfer *xfer) 2879{ 2880 return; 2881} 2882 2883static void 2884ehci_root_ctrl_close(struct usb2_xfer *xfer) 2885{ 2886 ehci_softc_t *sc = xfer->usb2_sc; 2887 2888 if (sc->sc_root_ctrl.xfer == xfer) { 2889 sc->sc_root_ctrl.xfer = NULL; 2890 } 2891 ehci_device_done(xfer, USB_ERR_CANCELLED); 2892} 2893 2894/* data structures and routines 2895 * to emulate the root hub: 2896 */ 2897 2898static const 2899struct usb2_device_descriptor ehci_devd = 2900{ 2901 sizeof(struct usb2_device_descriptor), 2902 UDESC_DEVICE, /* type */ 2903 {0x00, 0x02}, /* USB version */ 2904 UDCLASS_HUB, /* class */ 2905 UDSUBCLASS_HUB, /* subclass */ 2906 UDPROTO_HSHUBSTT, /* protocol */ 2907 64, /* max packet */ 2908 {0}, {0}, {0x00, 0x01}, /* device id */ 2909 1, 2, 0, /* string indicies */ 2910 1 /* # of configurations */ 2911}; 2912 2913static const 2914struct usb2_device_qualifier ehci_odevd = 2915{ 2916 sizeof(struct usb2_device_qualifier), 2917 UDESC_DEVICE_QUALIFIER, /* type */ 2918 {0x00, 0x02}, /* USB version */ 2919 UDCLASS_HUB, /* class */ 2920 UDSUBCLASS_HUB, /* subclass */ 2921 UDPROTO_FSHUB, /* protocol */ 2922 0, /* max packet */ 2923 0, /* # of configurations */ 2924 0 2925}; 2926 2927static const struct ehci_config_desc ehci_confd = { 2928 .confd = { 2929 .bLength = sizeof(struct usb2_config_descriptor), 2930 .bDescriptorType = UDESC_CONFIG, 2931 .wTotalLength[0] = sizeof(ehci_confd), 2932 .bNumInterface = 1, 2933 .bConfigurationValue = 1, 2934 .iConfiguration = 0, 2935 .bmAttributes = UC_SELF_POWERED, 2936 .bMaxPower = 0 /* max power */ 2937 }, 2938 2939 .ifcd = { 2940 .bLength = sizeof(struct usb2_interface_descriptor), 2941 .bDescriptorType = UDESC_INTERFACE, 2942 .bNumEndpoints = 1, 2943 .bInterfaceClass = UICLASS_HUB, 2944 .bInterfaceSubClass = UISUBCLASS_HUB, 2945 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 2946 0 2947 }, 2948 2949 .endpd = { 2950 .bLength = sizeof(struct usb2_endpoint_descriptor), 2951 .bDescriptorType = UDESC_ENDPOINT, 2952 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT, 2953 .bmAttributes = UE_INTERRUPT, 2954 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 2955 .bInterval = 255, 2956 }, 2957}; 2958 2959static const 2960struct usb2_hub_descriptor ehci_hubd = 2961{ 2962 0, /* dynamic length */ 2963 UDESC_HUB, 2964 0, 2965 {0, 0}, 2966 0, 2967 0, 2968 {0}, 2969}; 2970 2971static void 2972ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed) 2973{ 2974 uint32_t port; 2975 uint32_t v; 2976 2977 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed); 2978 2979 port = EHCI_PORTSC(index); 2980 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 2981 EOWRITE4(sc, port, v | EHCI_PS_PO); 2982} 2983 2984static void 2985ehci_root_ctrl_enter(struct usb2_xfer *xfer) 2986{ 2987 return; 2988} 2989 2990static void 2991ehci_root_ctrl_start(struct usb2_xfer *xfer) 2992{ 2993 ehci_softc_t *sc = xfer->usb2_sc; 2994 2995 DPRINTF("\n"); 2996 2997 sc->sc_root_ctrl.xfer = xfer; 2998 2999 usb2_config_td_queue_command 3000 (&sc->sc_config_td, NULL, &ehci_root_ctrl_task, 0, 0); 3001} 3002 3003static void 3004ehci_root_ctrl_task(struct ehci_softc *sc, 3005 struct usb2_config_td_cc *cc, uint16_t refcount) 3006{ 3007 ehci_root_ctrl_poll(sc); 3008} 3009 3010static void 3011ehci_root_ctrl_done(struct usb2_xfer *xfer, 3012 struct usb2_sw_transfer *std) 3013{ 3014 struct ehci_softc *sc = xfer->usb2_sc; 3015 char *ptr; 3016 uint32_t port; 3017 uint32_t v; 3018 uint16_t i; 3019 uint16_t value; 3020 uint16_t index; 3021 uint8_t l; 3022 uint8_t use_polling; 3023 3024 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3025 3026 if (std->state != USB_SW_TR_SETUP) { 3027 if (std->state == USB_SW_TR_PRE_CALLBACK) { 3028 /* transfer transferred */ 3029 ehci_device_done(xfer, std->err); 3030 } 3031 goto done; 3032 } 3033 /* buffer reset */ 3034 std->ptr = sc->sc_hub_desc.temp; 3035 std->len = 0; 3036 3037 value = UGETW(std->req.wValue); 3038 index = UGETW(std->req.wIndex); 3039 3040 use_polling = mtx_owned(xfer->xfer_mtx) ? 1 : 0; 3041 3042 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3043 "wValue=0x%04x wIndex=0x%04x\n", 3044 std->req.bmRequestType, std->req.bRequest, 3045 UGETW(std->req.wLength), value, index); 3046 3047#define C(x,y) ((x) | ((y) << 8)) 3048 switch (C(std->req.bRequest, std->req.bmRequestType)) { 3049 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3050 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3051 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3052 /* 3053 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3054 * for the integrated root hub. 3055 */ 3056 break; 3057 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3058 std->len = 1; 3059 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3060 break; 3061 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3062 switch (value >> 8) { 3063 case UDESC_DEVICE: 3064 if ((value & 0xff) != 0) { 3065 std->err = USB_ERR_IOERROR; 3066 goto done; 3067 } 3068 std->len = sizeof(ehci_devd); 3069 sc->sc_hub_desc.devd = ehci_devd; 3070 break; 3071 /* 3072 * We can't really operate at another speed, 3073 * but the specification says we need this 3074 * descriptor: 3075 */ 3076 case UDESC_DEVICE_QUALIFIER: 3077 if ((value & 0xff) != 0) { 3078 std->err = USB_ERR_IOERROR; 3079 goto done; 3080 } 3081 std->len = sizeof(ehci_odevd); 3082 sc->sc_hub_desc.odevd = ehci_odevd; 3083 break; 3084 3085 case UDESC_CONFIG: 3086 if ((value & 0xff) != 0) { 3087 std->err = USB_ERR_IOERROR; 3088 goto done; 3089 } 3090 std->len = sizeof(ehci_confd); 3091 std->ptr = USB_ADD_BYTES(&ehci_confd, 0); 3092 break; 3093 3094 case UDESC_STRING: 3095 switch (value & 0xff) { 3096 case 0: /* Language table */ 3097 ptr = "\001"; 3098 break; 3099 3100 case 1: /* Vendor */ 3101 ptr = sc->sc_vendor; 3102 break; 3103 3104 case 2: /* Product */ 3105 ptr = "EHCI root HUB"; 3106 break; 3107 3108 default: 3109 ptr = ""; 3110 break; 3111 } 3112 3113 std->len = usb2_make_str_desc 3114 (sc->sc_hub_desc.temp, 3115 sizeof(sc->sc_hub_desc.temp), 3116 ptr); 3117 break; 3118 default: 3119 std->err = USB_ERR_IOERROR; 3120 goto done; 3121 } 3122 break; 3123 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3124 std->len = 1; 3125 sc->sc_hub_desc.temp[0] = 0; 3126 break; 3127 case C(UR_GET_STATUS, UT_READ_DEVICE): 3128 std->len = 2; 3129 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3130 break; 3131 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3132 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3133 std->len = 2; 3134 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3135 break; 3136 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3137 if (value >= USB_MAX_DEVICES) { 3138 std->err = USB_ERR_IOERROR; 3139 goto done; 3140 } 3141 sc->sc_addr = value; 3142 break; 3143 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3144 if ((value != 0) && (value != 1)) { 3145 std->err = USB_ERR_IOERROR; 3146 goto done; 3147 } 3148 sc->sc_conf = value; 3149 break; 3150 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3151 break; 3152 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3153 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3154 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3155 std->err = USB_ERR_IOERROR; 3156 goto done; 3157 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3158 break; 3159 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3160 break; 3161 /* Hub requests */ 3162 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3163 break; 3164 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3165 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3166 3167 if ((index < 1) || 3168 (index > sc->sc_noport)) { 3169 std->err = USB_ERR_IOERROR; 3170 goto done; 3171 } 3172 port = EHCI_PORTSC(index); 3173 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3174 switch (value) { 3175 case UHF_PORT_ENABLE: 3176 EOWRITE4(sc, port, v & ~EHCI_PS_PE); 3177 break; 3178 case UHF_PORT_SUSPEND: 3179 EOWRITE4(sc, port, v & ~EHCI_PS_SUSP); 3180 break; 3181 case UHF_PORT_POWER: 3182 EOWRITE4(sc, port, v & ~EHCI_PS_PP); 3183 break; 3184 case UHF_PORT_TEST: 3185 DPRINTFN(3, "clear port test " 3186 "%d\n", index); 3187 break; 3188 case UHF_PORT_INDICATOR: 3189 DPRINTFN(3, "clear port ind " 3190 "%d\n", index); 3191 EOWRITE4(sc, port, v & ~EHCI_PS_PIC); 3192 break; 3193 case UHF_C_PORT_CONNECTION: 3194 EOWRITE4(sc, port, v | EHCI_PS_CSC); 3195 break; 3196 case UHF_C_PORT_ENABLE: 3197 EOWRITE4(sc, port, v | EHCI_PS_PEC); 3198 break; 3199 case UHF_C_PORT_SUSPEND: 3200 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3201 break; 3202 case UHF_C_PORT_OVER_CURRENT: 3203 EOWRITE4(sc, port, v | EHCI_PS_OCC); 3204 break; 3205 case UHF_C_PORT_RESET: 3206 sc->sc_isreset = 0; 3207 break; 3208 default: 3209 std->err = USB_ERR_IOERROR; 3210 goto done; 3211 } 3212 break; 3213 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3214 if ((value & 0xff) != 0) { 3215 std->err = USB_ERR_IOERROR; 3216 goto done; 3217 } 3218 v = EOREAD4(sc, EHCI_HCSPARAMS); 3219 3220 sc->sc_hub_desc.hubd = ehci_hubd; 3221 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3222 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, 3223 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) | 3224 (EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) ? 3225 UHD_PORT_IND : 0)); 3226 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 3227 for (l = 0; l < sc->sc_noport; l++) { 3228 /* XXX can't find out? */ 3229 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] &= ~(1 << (l % 8)); 3230 } 3231 sc->sc_hub_desc.hubd.bDescLength = 3232 8 + ((sc->sc_noport + 7) / 8); 3233 std->len = sc->sc_hub_desc.hubd.bDescLength; 3234 break; 3235 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3236 std->len = 16; 3237 bzero(sc->sc_hub_desc.temp, 16); 3238 break; 3239 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3240 DPRINTFN(9, "get port status i=%d\n", 3241 index); 3242 if ((index < 1) || 3243 (index > sc->sc_noport)) { 3244 std->err = USB_ERR_IOERROR; 3245 goto done; 3246 } 3247 v = EOREAD4(sc, EHCI_PORTSC(index)); 3248 DPRINTFN(9, "port status=0x%04x\n", v); 3249 if (sc->sc_flags & EHCI_SCFLG_FORCESPEED) { 3250 if ((v & 0xc000000) == 0x8000000) 3251 i = UPS_HIGH_SPEED; 3252 else if ((v & 0xc000000) == 0x4000000) 3253 i = UPS_LOW_SPEED; 3254 else 3255 i = 0; 3256 } else { 3257 i = UPS_HIGH_SPEED; 3258 } 3259 if (v & EHCI_PS_CS) 3260 i |= UPS_CURRENT_CONNECT_STATUS; 3261 if (v & EHCI_PS_PE) 3262 i |= UPS_PORT_ENABLED; 3263 if (v & EHCI_PS_SUSP) 3264 i |= UPS_SUSPEND; 3265 if (v & EHCI_PS_OCA) 3266 i |= UPS_OVERCURRENT_INDICATOR; 3267 if (v & EHCI_PS_PR) 3268 i |= UPS_RESET; 3269 if (v & EHCI_PS_PP) 3270 i |= UPS_PORT_POWER; 3271 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3272 i = 0; 3273 if (v & EHCI_PS_CSC) 3274 i |= UPS_C_CONNECT_STATUS; 3275 if (v & EHCI_PS_PEC) 3276 i |= UPS_C_PORT_ENABLED; 3277 if (v & EHCI_PS_OCC) 3278 i |= UPS_C_OVERCURRENT_INDICATOR; 3279 if (sc->sc_isreset) 3280 i |= UPS_C_PORT_RESET; 3281 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3282 std->len = sizeof(sc->sc_hub_desc.ps); 3283 break; 3284 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3285 std->err = USB_ERR_IOERROR; 3286 goto done; 3287 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3288 break; 3289 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3290 if ((index < 1) || 3291 (index > sc->sc_noport)) { 3292 std->err = USB_ERR_IOERROR; 3293 goto done; 3294 } 3295 port = EHCI_PORTSC(index); 3296 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3297 switch (value) { 3298 case UHF_PORT_ENABLE: 3299 EOWRITE4(sc, port, v | EHCI_PS_PE); 3300 break; 3301 case UHF_PORT_SUSPEND: 3302 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3303 break; 3304 case UHF_PORT_RESET: 3305 DPRINTFN(6, "reset port %d\n", index); 3306#if USB_DEBUG 3307 if (ehcinohighspeed) { 3308 /* 3309 * Connect USB device to companion 3310 * controller. 3311 */ 3312 ehci_disown(sc, index, 1); 3313 break; 3314 } 3315#endif 3316 if (EHCI_PS_IS_LOWSPEED(v)) { 3317 /* Low speed device, give up ownership. */ 3318 ehci_disown(sc, index, 1); 3319 break; 3320 } 3321 /* Start reset sequence. */ 3322 v &= ~(EHCI_PS_PE | EHCI_PS_PR); 3323 EOWRITE4(sc, port, v | EHCI_PS_PR); 3324 3325 if (use_polling) { 3326 /* polling */ 3327 DELAY(USB_PORT_ROOT_RESET_DELAY * 1000); 3328 } else { 3329 /* Wait for reset to complete. */ 3330 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 3331 USB_PORT_ROOT_RESET_DELAY); 3332 } 3333 3334 /* Terminate reset sequence. */ 3335 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM)) 3336 EOWRITE4(sc, port, v); 3337 3338 if (use_polling) { 3339 /* polling */ 3340 DELAY(EHCI_PORT_RESET_COMPLETE * 1000); 3341 } else { 3342 /* Wait for HC to complete reset. */ 3343 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 3344 EHCI_PORT_RESET_COMPLETE); 3345 } 3346 3347 v = EOREAD4(sc, port); 3348 DPRINTF("ehci after reset, status=0x%08x\n", v); 3349 if (v & EHCI_PS_PR) { 3350 device_printf(sc->sc_bus.bdev, 3351 "port reset timeout\n"); 3352 std->err = USB_ERR_TIMEOUT; 3353 goto done; 3354 } 3355 if (!(v & EHCI_PS_PE)) { 3356 /* 3357 * Not a high speed device, give up 3358 * ownership. 3359 */ 3360 ehci_disown(sc, index, 0); 3361 break; 3362 } 3363 sc->sc_isreset = 1; 3364 DPRINTF("ehci port %d reset, status = 0x%08x\n", 3365 index, v); 3366 break; 3367 3368 case UHF_PORT_POWER: 3369 DPRINTFN(3, "set port power %d\n", index); 3370 EOWRITE4(sc, port, v | EHCI_PS_PP); 3371 break; 3372 3373 case UHF_PORT_TEST: 3374 DPRINTFN(3, "set port test %d\n", index); 3375 break; 3376 3377 case UHF_PORT_INDICATOR: 3378 DPRINTFN(3, "set port ind %d\n", index); 3379 EOWRITE4(sc, port, v | EHCI_PS_PIC); 3380 break; 3381 3382 default: 3383 std->err = USB_ERR_IOERROR; 3384 goto done; 3385 } 3386 break; 3387 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3388 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3389 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3390 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3391 break; 3392 default: 3393 std->err = USB_ERR_IOERROR; 3394 goto done; 3395 } 3396done: 3397 return; 3398} 3399 3400static void 3401ehci_root_ctrl_poll(struct ehci_softc *sc) 3402{ 3403 usb2_sw_transfer(&sc->sc_root_ctrl, 3404 &ehci_root_ctrl_done); 3405} 3406 3407struct usb2_pipe_methods ehci_root_ctrl_methods = 3408{ 3409 .open = ehci_root_ctrl_open, 3410 .close = ehci_root_ctrl_close, 3411 .enter = ehci_root_ctrl_enter, 3412 .start = ehci_root_ctrl_start, 3413 .enter_is_cancelable = 1, 3414 .start_is_cancelable = 0, 3415}; 3416 3417/*------------------------------------------------------------------------* 3418 * ehci root interrupt support 3419 *------------------------------------------------------------------------*/ 3420static void 3421ehci_root_intr_open(struct usb2_xfer *xfer) 3422{ 3423 return; 3424} 3425 3426static void 3427ehci_root_intr_close(struct usb2_xfer *xfer) 3428{ 3429 ehci_softc_t *sc = xfer->usb2_sc; 3430 3431 if (sc->sc_root_intr.xfer == xfer) { 3432 sc->sc_root_intr.xfer = NULL; 3433 } 3434 ehci_device_done(xfer, USB_ERR_CANCELLED); 3435} 3436 3437static void 3438ehci_root_intr_enter(struct usb2_xfer *xfer) 3439{ 3440 return; 3441} 3442 3443static void 3444ehci_root_intr_start(struct usb2_xfer *xfer) 3445{ 3446 ehci_softc_t *sc = xfer->usb2_sc; 3447 3448 sc->sc_root_intr.xfer = xfer; 3449} 3450 3451struct usb2_pipe_methods ehci_root_intr_methods = 3452{ 3453 .open = ehci_root_intr_open, 3454 .close = ehci_root_intr_close, 3455 .enter = ehci_root_intr_enter, 3456 .start = ehci_root_intr_start, 3457 .enter_is_cancelable = 1, 3458 .start_is_cancelable = 1, 3459}; 3460 3461static void 3462ehci_xfer_setup(struct usb2_setup_params *parm) 3463{ 3464 struct usb2_page_search page_info; 3465 struct usb2_page_cache *pc; 3466 ehci_softc_t *sc; 3467 struct usb2_xfer *xfer; 3468 void *last_obj; 3469 uint32_t nqtd; 3470 uint32_t nqh; 3471 uint32_t nsitd; 3472 uint32_t nitd; 3473 uint32_t n; 3474 3475 sc = EHCI_BUS2SC(parm->udev->bus); 3476 xfer = parm->curr_xfer; 3477 3478 nqtd = 0; 3479 nqh = 0; 3480 nsitd = 0; 3481 nitd = 0; 3482 3483 /* 3484 * setup xfer 3485 */ 3486 xfer->usb2_sc = sc; 3487 3488 /* 3489 * compute maximum number of some structures 3490 */ 3491 if (parm->methods == &ehci_device_ctrl_methods) { 3492 3493 /* 3494 * The proof for the "nqtd" formula is illustrated like 3495 * this: 3496 * 3497 * +------------------------------------+ 3498 * | | 3499 * | |remainder -> | 3500 * | +-----+---+ | 3501 * | | xxx | x | frm 0 | 3502 * | +-----+---++ | 3503 * | | xxx | xx | frm 1 | 3504 * | +-----+----+ | 3505 * | ... | 3506 * +------------------------------------+ 3507 * 3508 * "xxx" means a completely full USB transfer descriptor 3509 * 3510 * "x" and "xx" means a short USB packet 3511 * 3512 * For the remainder of an USB transfer modulo 3513 * "max_data_length" we need two USB transfer descriptors. 3514 * One to transfer the remaining data and one to finalise 3515 * with a zero length packet in case the "force_short_xfer" 3516 * flag is set. We only need two USB transfer descriptors in 3517 * the case where the transfer length of the first one is a 3518 * factor of "max_frame_size". The rest of the needed USB 3519 * transfer descriptors is given by the buffer size divided 3520 * by the maximum data payload. 3521 */ 3522 parm->hc_max_packet_size = 0x400; 3523 parm->hc_max_packet_count = 1; 3524 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3525 xfer->flags_int.bdma_enable = 1; 3526 3527 usb2_transfer_setup_sub(parm); 3528 3529 nqh = 1; 3530 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */ 3531 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 3532 3533 } else if (parm->methods == &ehci_device_bulk_methods) { 3534 3535 parm->hc_max_packet_size = 0x400; 3536 parm->hc_max_packet_count = 1; 3537 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3538 xfer->flags_int.bdma_enable = 1; 3539 3540 usb2_transfer_setup_sub(parm); 3541 3542 nqh = 1; 3543 nqtd = ((2 * xfer->nframes) 3544 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 3545 3546 } else if (parm->methods == &ehci_device_intr_methods) { 3547 3548 if (parm->speed == USB_SPEED_HIGH) { 3549 parm->hc_max_packet_size = 0x400; 3550 parm->hc_max_packet_count = 3; 3551 } else if (parm->speed == USB_SPEED_FULL) { 3552 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME; 3553 parm->hc_max_packet_count = 1; 3554 } else { 3555 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8; 3556 parm->hc_max_packet_count = 1; 3557 } 3558 3559 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3560 xfer->flags_int.bdma_enable = 1; 3561 3562 usb2_transfer_setup_sub(parm); 3563 3564 nqh = 1; 3565 nqtd = ((2 * xfer->nframes) 3566 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 3567 3568 } else if (parm->methods == &ehci_device_isoc_fs_methods) { 3569 3570 parm->hc_max_packet_size = 0x3FF; 3571 parm->hc_max_packet_count = 1; 3572 parm->hc_max_frame_size = 0x3FF; 3573 xfer->flags_int.bdma_enable = 1; 3574 3575 usb2_transfer_setup_sub(parm); 3576 3577 nsitd = xfer->nframes; 3578 3579 } else if (parm->methods == &ehci_device_isoc_hs_methods) { 3580 3581 parm->hc_max_packet_size = 0x400; 3582 parm->hc_max_packet_count = 3; 3583 parm->hc_max_frame_size = 0xC00; 3584 xfer->flags_int.bdma_enable = 1; 3585 3586 usb2_transfer_setup_sub(parm); 3587 3588 nitd = (xfer->nframes + 7) / 8; 3589 3590 } else { 3591 3592 parm->hc_max_packet_size = 0x400; 3593 parm->hc_max_packet_count = 1; 3594 parm->hc_max_frame_size = 0x400; 3595 3596 usb2_transfer_setup_sub(parm); 3597 } 3598 3599alloc_dma_set: 3600 3601 if (parm->err) { 3602 return; 3603 } 3604 /* 3605 * Allocate queue heads and transfer descriptors 3606 */ 3607 last_obj = NULL; 3608 3609 if (usb2_transfer_setup_sub_malloc( 3610 parm, &pc, sizeof(ehci_itd_t), 3611 EHCI_ITD_ALIGN, nitd)) { 3612 parm->err = USB_ERR_NOMEM; 3613 return; 3614 } 3615 if (parm->buf) { 3616 for (n = 0; n != nitd; n++) { 3617 ehci_itd_t *td; 3618 3619 usb2_get_page(pc + n, 0, &page_info); 3620 3621 td = page_info.buffer; 3622 3623 /* init TD */ 3624 td->itd_self = htole32(page_info.physaddr | EHCI_LINK_ITD); 3625 td->obj_next = last_obj; 3626 td->page_cache = pc + n; 3627 3628 last_obj = td; 3629 3630 usb2_pc_cpu_flush(pc + n); 3631 } 3632 } 3633 if (usb2_transfer_setup_sub_malloc( 3634 parm, &pc, sizeof(ehci_sitd_t), 3635 EHCI_SITD_ALIGN, nsitd)) { 3636 parm->err = USB_ERR_NOMEM; 3637 return; 3638 } 3639 if (parm->buf) { 3640 for (n = 0; n != nsitd; n++) { 3641 ehci_sitd_t *td; 3642 3643 usb2_get_page(pc + n, 0, &page_info); 3644 3645 td = page_info.buffer; 3646 3647 /* init TD */ 3648 td->sitd_self = htole32(page_info.physaddr | EHCI_LINK_SITD); 3649 td->obj_next = last_obj; 3650 td->page_cache = pc + n; 3651 3652 last_obj = td; 3653 3654 usb2_pc_cpu_flush(pc + n); 3655 } 3656 } 3657 if (usb2_transfer_setup_sub_malloc( 3658 parm, &pc, sizeof(ehci_qtd_t), 3659 EHCI_QTD_ALIGN, nqtd)) { 3660 parm->err = USB_ERR_NOMEM; 3661 return; 3662 } 3663 if (parm->buf) { 3664 for (n = 0; n != nqtd; n++) { 3665 ehci_qtd_t *qtd; 3666 3667 usb2_get_page(pc + n, 0, &page_info); 3668 3669 qtd = page_info.buffer; 3670 3671 /* init TD */ 3672 qtd->qtd_self = htole32(page_info.physaddr); 3673 qtd->obj_next = last_obj; 3674 qtd->page_cache = pc + n; 3675 3676 last_obj = qtd; 3677 3678 usb2_pc_cpu_flush(pc + n); 3679 } 3680 } 3681 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3682 3683 last_obj = NULL; 3684 3685 if (usb2_transfer_setup_sub_malloc( 3686 parm, &pc, sizeof(ehci_qh_t), 3687 EHCI_QH_ALIGN, nqh)) { 3688 parm->err = USB_ERR_NOMEM; 3689 return; 3690 } 3691 if (parm->buf) { 3692 for (n = 0; n != nqh; n++) { 3693 ehci_qh_t *qh; 3694 3695 usb2_get_page(pc + n, 0, &page_info); 3696 3697 qh = page_info.buffer; 3698 3699 /* init QH */ 3700 qh->qh_self = htole32(page_info.physaddr | EHCI_LINK_QH); 3701 qh->obj_next = last_obj; 3702 qh->page_cache = pc + n; 3703 3704 last_obj = qh; 3705 3706 usb2_pc_cpu_flush(pc + n); 3707 } 3708 } 3709 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3710 3711 if (!xfer->flags_int.curr_dma_set) { 3712 xfer->flags_int.curr_dma_set = 1; 3713 goto alloc_dma_set; 3714 } 3715} 3716 3717static void 3718ehci_xfer_unsetup(struct usb2_xfer *xfer) 3719{ 3720 return; 3721} 3722 3723static void 3724ehci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 3725 struct usb2_pipe *pipe) 3726{ 3727 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3728 3729 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3730 pipe, udev->address, 3731 edesc->bEndpointAddress, udev->flags.usb2_mode, 3732 sc->sc_addr); 3733 3734 if (udev->flags.usb2_mode != USB_MODE_HOST) { 3735 /* not supported */ 3736 return; 3737 } 3738 if (udev->device_index == sc->sc_addr) { 3739 switch (edesc->bEndpointAddress) { 3740 case USB_CONTROL_ENDPOINT: 3741 pipe->methods = &ehci_root_ctrl_methods; 3742 break; 3743 case UE_DIR_IN | EHCI_INTR_ENDPT: 3744 pipe->methods = &ehci_root_intr_methods; 3745 break; 3746 default: 3747 /* do nothing */ 3748 break; 3749 } 3750 } else { 3751 if ((udev->speed != USB_SPEED_HIGH) && 3752 ((udev->hs_hub_addr == 0) || 3753 (udev->hs_port_no == 0) || 3754 (udev->bus->devices[udev->hs_hub_addr] == NULL) || 3755 (udev->bus->devices[udev->hs_hub_addr]->hub == NULL))) { 3756 /* We need a transaction translator */ 3757 goto done; 3758 } 3759 switch (edesc->bmAttributes & UE_XFERTYPE) { 3760 case UE_CONTROL: 3761 pipe->methods = &ehci_device_ctrl_methods; 3762 break; 3763 case UE_INTERRUPT: 3764 pipe->methods = &ehci_device_intr_methods; 3765 break; 3766 case UE_ISOCHRONOUS: 3767 if (udev->speed == USB_SPEED_HIGH) { 3768 pipe->methods = &ehci_device_isoc_hs_methods; 3769 } else if (udev->speed == USB_SPEED_FULL) { 3770 pipe->methods = &ehci_device_isoc_fs_methods; 3771 } 3772 break; 3773 case UE_BULK: 3774 if (udev->speed != USB_SPEED_LOW) { 3775 pipe->methods = &ehci_device_bulk_methods; 3776 } 3777 break; 3778 default: 3779 /* do nothing */ 3780 break; 3781 } 3782 } 3783done: 3784 return; 3785} 3786 3787static void 3788ehci_get_dma_delay(struct usb2_bus *bus, uint32_t *pus) 3789{ 3790 /* 3791 * Wait until the hardware has finished any possible use of 3792 * the transfer descriptor(s) and QH 3793 */ 3794 *pus = (188); /* microseconds */ 3795} 3796 3797struct usb2_bus_methods ehci_bus_methods = 3798{ 3799 .pipe_init = ehci_pipe_init, 3800 .xfer_setup = ehci_xfer_setup, 3801 .xfer_unsetup = ehci_xfer_unsetup, 3802 .do_poll = ehci_do_poll, 3803 .get_dma_delay = ehci_get_dma_delay, 3804}; 3805