ehci.c revision 184610
1/*- 2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved. 3 * Copyright (c) 2004 The NetBSD Foundation, Inc. All rights reserved. 4 * Copyright (c) 2004 Lennart Augustsson. All rights reserved. 5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 31 * 32 * The EHCI 0.96 spec can be found at 33 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 34 * The EHCI 1.0 spec can be found at 35 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 36 * and the USB 2.0 spec at 37 * http://www.usb.org/developers/docs/usb_20.zip 38 * 39 */ 40 41/* 42 * TODO: 43 * 1) command failures are not recovered correctly 44 */ 45 46#include <sys/cdefs.h> 47__FBSDID("$FreeBSD: head/sys/dev/usb2/controller/ehci2.c 184610 2008-11-04 02:31:03Z alfred $"); 48 49#include <dev/usb2/include/usb2_standard.h> 50#include <dev/usb2/include/usb2_mfunc.h> 51#include <dev/usb2/include/usb2_error.h> 52#include <dev/usb2/include/usb2_defs.h> 53 54#define USB_DEBUG_VAR ehcidebug 55#define usb2_config_td_cc ehci_config_copy 56#define usb2_config_td_softc ehci_softc 57 58#include <dev/usb2/core/usb2_core.h> 59#include <dev/usb2/core/usb2_debug.h> 60#include <dev/usb2/core/usb2_busdma.h> 61#include <dev/usb2/core/usb2_process.h> 62#include <dev/usb2/core/usb2_config_td.h> 63#include <dev/usb2/core/usb2_sw_transfer.h> 64#include <dev/usb2/core/usb2_transfer.h> 65#include <dev/usb2/core/usb2_device.h> 66#include <dev/usb2/core/usb2_hub.h> 67#include <dev/usb2/core/usb2_util.h> 68 69#include <dev/usb2/controller/usb2_controller.h> 70#include <dev/usb2/controller/usb2_bus.h> 71#include <dev/usb2/controller/ehci2.h> 72 73#define EHCI_BUS2SC(bus) ((ehci_softc_t *)(((uint8_t *)(bus)) - \ 74 USB_P2U(&(((ehci_softc_t *)0)->sc_bus)))) 75 76#if USB_DEBUG 77static int ehcidebug = 0; 78static int ehcinohighspeed = 0; 79 80SYSCTL_NODE(_hw_usb2, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci"); 81SYSCTL_INT(_hw_usb2_ehci, OID_AUTO, debug, CTLFLAG_RW, 82 &ehcidebug, 0, "Debug level"); 83SYSCTL_INT(_hw_usb2_ehci, OID_AUTO, no_hs, CTLFLAG_RW, 84 &ehcinohighspeed, 0, "Disable High Speed USB"); 85 86static void ehci_dump_regs(ehci_softc_t *sc); 87static void ehci_dump_sqh(ehci_qh_t *sqh); 88 89#endif 90 91#define EHCI_INTR_ENDPT 1 92 93extern struct usb2_bus_methods ehci_bus_methods; 94extern struct usb2_pipe_methods ehci_device_bulk_methods; 95extern struct usb2_pipe_methods ehci_device_ctrl_methods; 96extern struct usb2_pipe_methods ehci_device_intr_methods; 97extern struct usb2_pipe_methods ehci_device_isoc_fs_methods; 98extern struct usb2_pipe_methods ehci_device_isoc_hs_methods; 99extern struct usb2_pipe_methods ehci_root_ctrl_methods; 100extern struct usb2_pipe_methods ehci_root_intr_methods; 101 102static usb2_config_td_command_t ehci_root_ctrl_task; 103static void ehci_do_poll(struct usb2_bus *bus); 104static void ehci_root_ctrl_poll(struct ehci_softc *sc); 105static void ehci_device_done(struct usb2_xfer *xfer, usb2_error_t error); 106static uint8_t ehci_check_transfer(struct usb2_xfer *xfer); 107static void ehci_timeout(void *arg); 108 109static usb2_sw_transfer_func_t ehci_root_intr_done; 110static usb2_sw_transfer_func_t ehci_root_ctrl_done; 111 112struct ehci_std_temp { 113 struct usb2_page_cache *pc; 114 ehci_qtd_t *td; 115 ehci_qtd_t *td_next; 116 uint32_t average; 117 uint32_t qtd_status; 118 uint32_t len; 119 uint16_t max_frame_size; 120 uint8_t shortpkt; 121 uint8_t auto_data_toggle; 122 uint8_t setup_alt_next; 123 uint8_t short_frames_ok; 124}; 125 126void 127ehci_iterate_hw_softc(struct usb2_bus *bus, usb2_bus_mem_sub_cb_t *cb) 128{ 129 struct ehci_softc *sc = EHCI_BUS2SC(bus); 130 uint32_t i; 131 132 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg, 133 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN); 134 135 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg, 136 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 137 138 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 139 cb(bus, sc->sc_hw.intr_start_pc + i, 140 sc->sc_hw.intr_start_pg + i, 141 sizeof(ehci_qh_t), EHCI_QH_ALIGN); 142 } 143 144 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 145 cb(bus, sc->sc_hw.isoc_hs_start_pc + i, 146 sc->sc_hw.isoc_hs_start_pg + i, 147 sizeof(ehci_itd_t), EHCI_ITD_ALIGN); 148 } 149 150 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 151 cb(bus, sc->sc_hw.isoc_fs_start_pc + i, 152 sc->sc_hw.isoc_fs_start_pg + i, 153 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN); 154 } 155 return; 156} 157 158static usb2_error_t 159ehci_hc_reset(ehci_softc_t *sc) 160{ 161 uint32_t hcr; 162 uint32_t n; 163 164 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 165 166 for (n = 0; n != 100; n++) { 167 usb2_pause_mtx(&sc->sc_bus.mtx, 1); 168 hcr = EOREAD4(sc, EHCI_USBSTS); 169 if (hcr & EHCI_STS_HCH) { 170 hcr = 0; 171 break; 172 } 173 } 174 175 /* 176 * Fall through and try reset anyway even though 177 * Table 2-9 in the EHCI spec says this will result 178 * in undefined behavior. 179 */ 180 181 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 182 for (n = 0; n != 100; n++) { 183 usb2_pause_mtx(&sc->sc_bus.mtx, 1); 184 hcr = EOREAD4(sc, EHCI_USBCMD); 185 if (!(hcr & EHCI_CMD_HCRESET)) { 186 hcr = 0; 187 break; 188 } 189 } 190 191 if (hcr) { 192 return (USB_ERR_IOERROR); 193 } 194 return (0); 195} 196 197usb2_error_t 198ehci_init(ehci_softc_t *sc) 199{ 200 struct usb2_page_search buf_res; 201 uint32_t version; 202 uint32_t sparams; 203 uint32_t cparams; 204 uint32_t hcr; 205 uint16_t i; 206 uint16_t x; 207 uint16_t y; 208 uint16_t bit; 209 usb2_error_t err = 0; 210 211 mtx_lock(&sc->sc_bus.mtx); 212 213 DPRINTF("start\n"); 214 215 usb2_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.mtx, 216 CALLOUT_RETURNUNLOCKED); 217 218#if USB_DEBUG 219 if (ehcidebug > 2) { 220 ehci_dump_regs(sc); 221 } 222#endif 223 224 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 225 226 version = EREAD2(sc, EHCI_HCIVERSION); 227 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n", 228 version >> 8, version & 0xff); 229 230 sparams = EREAD4(sc, EHCI_HCSPARAMS); 231 DPRINTF("sparams=0x%x\n", sparams); 232 233 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 234 cparams = EREAD4(sc, EHCI_HCCPARAMS); 235 DPRINTF("cparams=0x%x\n", cparams); 236 237 if (EHCI_HCC_64BIT(cparams)) { 238 DPRINTF("HCC uses 64-bit structures\n"); 239 240 /* MUST clear segment register if 64 bit capable */ 241 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 242 } 243 sc->sc_bus.usbrev = USB_REV_2_0; 244 245 /* Reset the controller */ 246 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev)); 247 248 err = ehci_hc_reset(sc); 249 if (err) { 250 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 251 goto done; 252 } 253 /* 254 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4 255 * bytes 2: 256*4 bytes 3: unknown 256 */ 257 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) { 258 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n"); 259 err = USB_ERR_IOERROR; 260 goto done; 261 } 262 /* set up the bus struct */ 263 sc->sc_bus.methods = &ehci_bus_methods; 264 265 sc->sc_eintrs = EHCI_NORMAL_INTRS; 266 267 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 268 ehci_qh_t *qh; 269 270 usb2_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res); 271 272 qh = buf_res.buffer; 273 274 /* initialize page cache pointer */ 275 276 qh->page_cache = sc->sc_hw.intr_start_pc + i; 277 278 /* store a pointer to queue head */ 279 280 sc->sc_intr_p_last[i] = qh; 281 282 qh->qh_self = 283 htole32(buf_res.physaddr) | 284 htole32(EHCI_LINK_QH); 285 286 qh->qh_endp = 287 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 288 qh->qh_endphub = 289 htole32(EHCI_QH_SET_MULT(1)); 290 qh->qh_curqtd = 0; 291 292 qh->qh_qtd.qtd_next = 293 htole32(EHCI_LINK_TERMINATE); 294 qh->qh_qtd.qtd_altnext = 295 htole32(EHCI_LINK_TERMINATE); 296 qh->qh_qtd.qtd_status = 297 htole32(EHCI_QTD_HALTED); 298 } 299 300 /* 301 * the QHs are arranged to give poll intervals that are 302 * powers of 2 times 1ms 303 */ 304 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 305 while (bit) { 306 x = bit; 307 while (x & bit) { 308 ehci_qh_t *qh_x; 309 ehci_qh_t *qh_y; 310 311 y = (x ^ bit) | (bit / 2); 312 313 qh_x = sc->sc_intr_p_last[x]; 314 qh_y = sc->sc_intr_p_last[y]; 315 316 /* 317 * the next QH has half the poll interval 318 */ 319 qh_x->qh_link = qh_y->qh_self; 320 321 x++; 322 } 323 bit >>= 1; 324 } 325 326 if (1) { 327 ehci_qh_t *qh; 328 329 qh = sc->sc_intr_p_last[0]; 330 331 /* the last (1ms) QH terminates */ 332 qh->qh_link = htole32(EHCI_LINK_TERMINATE); 333 } 334 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) { 335 ehci_sitd_t *sitd; 336 ehci_itd_t *itd; 337 338 usb2_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res); 339 340 sitd = buf_res.buffer; 341 342 /* initialize page cache pointer */ 343 344 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i; 345 346 /* store a pointer to the transfer descriptor */ 347 348 sc->sc_isoc_fs_p_last[i] = sitd; 349 350 /* initialize full speed isochronous */ 351 352 sitd->sitd_self = 353 htole32(buf_res.physaddr) | 354 htole32(EHCI_LINK_SITD); 355 356 sitd->sitd_back = 357 htole32(EHCI_LINK_TERMINATE); 358 359 sitd->sitd_next = 360 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self; 361 362 363 usb2_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res); 364 365 itd = buf_res.buffer; 366 367 /* initialize page cache pointer */ 368 369 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i; 370 371 /* store a pointer to the transfer descriptor */ 372 373 sc->sc_isoc_hs_p_last[i] = itd; 374 375 /* initialize high speed isochronous */ 376 377 itd->itd_self = 378 htole32(buf_res.physaddr) | 379 htole32(EHCI_LINK_ITD); 380 381 itd->itd_next = 382 sitd->sitd_self; 383 } 384 385 usb2_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 386 387 if (1) { 388 uint32_t *pframes; 389 390 pframes = buf_res.buffer; 391 392 /* 393 * execution order: 394 * pframes -> high speed isochronous -> 395 * full speed isochronous -> interrupt QH's 396 */ 397 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) { 398 pframes[i] = sc->sc_isoc_hs_p_last 399 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self; 400 } 401 } 402 /* setup sync list pointer */ 403 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 404 405 usb2_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 406 407 if (1) { 408 409 ehci_qh_t *qh; 410 411 qh = buf_res.buffer; 412 413 /* initialize page cache pointer */ 414 415 qh->page_cache = &sc->sc_hw.async_start_pc; 416 417 /* store a pointer to the queue head */ 418 419 sc->sc_async_p_last = qh; 420 421 /* init dummy QH that starts the async list */ 422 423 qh->qh_self = 424 htole32(buf_res.physaddr) | 425 htole32(EHCI_LINK_QH); 426 427 /* fill the QH */ 428 qh->qh_endp = 429 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 430 qh->qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 431 qh->qh_link = qh->qh_self; 432 qh->qh_curqtd = 0; 433 434 /* fill the overlay qTD */ 435 qh->qh_qtd.qtd_next = htole32(EHCI_LINK_TERMINATE); 436 qh->qh_qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 437 qh->qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 438 } 439 /* flush all cache into memory */ 440 441 usb2_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc); 442 443#if USB_DEBUG 444 if (ehcidebug) { 445 ehci_dump_sqh(sc->sc_async_p_last); 446 } 447#endif 448 449 /* setup async list pointer */ 450 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 451 452 453 /* enable interrupts */ 454 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 455 456 /* turn on controller */ 457 EOWRITE4(sc, EHCI_USBCMD, 458 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */ 459 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 460 EHCI_CMD_ASE | 461 EHCI_CMD_PSE | 462 EHCI_CMD_RS); 463 464 /* Take over port ownership */ 465 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 466 467 for (i = 0; i < 100; i++) { 468 usb2_pause_mtx(&sc->sc_bus.mtx, 1); 469 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 470 if (!hcr) { 471 break; 472 } 473 } 474 if (hcr) { 475 device_printf(sc->sc_bus.bdev, "run timeout\n"); 476 err = USB_ERR_IOERROR; 477 goto done; 478 } 479done: 480 mtx_unlock(&sc->sc_bus.mtx); 481 482 if (!err) { 483 /* catch any lost interrupts */ 484 ehci_do_poll(&sc->sc_bus); 485 } 486 return (err); 487} 488 489/* 490 * shut down the controller when the system is going down 491 */ 492void 493ehci_detach(struct ehci_softc *sc) 494{ 495 mtx_lock(&sc->sc_bus.mtx); 496 497 usb2_callout_stop(&sc->sc_tmo_pcd); 498 499 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 500 501 if (ehci_hc_reset(sc)) { 502 DPRINTF("reset failed!\n"); 503 } 504 /* XXX let stray task complete */ 505 usb2_pause_mtx(&sc->sc_bus.mtx, 50); 506 507 mtx_unlock(&sc->sc_bus.mtx); 508 509 usb2_callout_drain(&sc->sc_tmo_pcd); 510 511 return; 512} 513 514void 515ehci_suspend(struct ehci_softc *sc) 516{ 517 uint32_t cmd; 518 uint32_t hcr; 519 uint8_t i; 520 521 mtx_lock(&sc->sc_bus.mtx); 522 523 for (i = 1; i <= sc->sc_noport; i++) { 524 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 525 if (((cmd & EHCI_PS_PO) == 0) && 526 ((cmd & EHCI_PS_PE) == EHCI_PS_PE)) { 527 EOWRITE4(sc, EHCI_PORTSC(i), 528 cmd | EHCI_PS_SUSP); 529 } 530 } 531 532 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 533 534 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 535 EOWRITE4(sc, EHCI_USBCMD, cmd); 536 537 for (i = 0; i < 100; i++) { 538 hcr = EOREAD4(sc, EHCI_USBSTS) & 539 (EHCI_STS_ASS | EHCI_STS_PSS); 540 541 if (hcr == 0) { 542 break; 543 } 544 usb2_pause_mtx(&sc->sc_bus.mtx, 1); 545 } 546 547 if (hcr != 0) { 548 device_printf(sc->sc_bus.bdev, "reset timeout\n"); 549 } 550 cmd &= ~EHCI_CMD_RS; 551 EOWRITE4(sc, EHCI_USBCMD, cmd); 552 553 for (i = 0; i < 100; i++) { 554 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 555 if (hcr == EHCI_STS_HCH) { 556 break; 557 } 558 usb2_pause_mtx(&sc->sc_bus.mtx, 1); 559 } 560 561 if (hcr != EHCI_STS_HCH) { 562 device_printf(sc->sc_bus.bdev, 563 "config timeout\n"); 564 } 565 mtx_unlock(&sc->sc_bus.mtx); 566 return; 567} 568 569void 570ehci_resume(struct ehci_softc *sc) 571{ 572 struct usb2_page_search buf_res; 573 uint32_t cmd; 574 uint32_t hcr; 575 uint8_t i; 576 577 mtx_lock(&sc->sc_bus.mtx); 578 579 /* restore things in case the bios doesn't */ 580 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 581 582 usb2_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res); 583 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr); 584 585 usb2_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res); 586 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH); 587 588 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 589 590 hcr = 0; 591 for (i = 1; i <= sc->sc_noport; i++) { 592 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 593 if (((cmd & EHCI_PS_PO) == 0) && 594 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) { 595 EOWRITE4(sc, EHCI_PORTSC(i), 596 cmd | EHCI_PS_FPR); 597 hcr = 1; 598 } 599 } 600 601 if (hcr) { 602 usb2_pause_mtx(&sc->sc_bus.mtx, 603 USB_RESUME_WAIT); 604 605 for (i = 1; i <= sc->sc_noport; i++) { 606 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 607 if (((cmd & EHCI_PS_PO) == 0) && 608 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) { 609 EOWRITE4(sc, EHCI_PORTSC(i), 610 cmd & ~EHCI_PS_FPR); 611 } 612 } 613 } 614 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 615 616 for (i = 0; i < 100; i++) { 617 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 618 if (hcr != EHCI_STS_HCH) { 619 break; 620 } 621 usb2_pause_mtx(&sc->sc_bus.mtx, 1); 622 } 623 if (hcr == EHCI_STS_HCH) { 624 device_printf(sc->sc_bus.bdev, "config timeout\n"); 625 } 626 usb2_pause_mtx(&sc->sc_bus.mtx, 627 USB_RESUME_WAIT); 628 629 mtx_unlock(&sc->sc_bus.mtx); 630 631 /* catch any lost interrupts */ 632 ehci_do_poll(&sc->sc_bus); 633 634 return; 635} 636 637void 638ehci_shutdown(ehci_softc_t *sc) 639{ 640 DPRINTF("stopping the HC\n"); 641 642 mtx_lock(&sc->sc_bus.mtx); 643 644 if (ehci_hc_reset(sc)) { 645 DPRINTF("reset failed!\n"); 646 } 647 mtx_unlock(&sc->sc_bus.mtx); 648} 649 650#if USB_DEBUG 651static void 652ehci_dump_regs(ehci_softc_t *sc) 653{ 654 uint32_t i; 655 656 i = EOREAD4(sc, EHCI_USBCMD); 657 printf("cmd=0x%08x\n", i); 658 659 if (i & EHCI_CMD_ITC_1) 660 printf(" EHCI_CMD_ITC_1\n"); 661 if (i & EHCI_CMD_ITC_2) 662 printf(" EHCI_CMD_ITC_2\n"); 663 if (i & EHCI_CMD_ITC_4) 664 printf(" EHCI_CMD_ITC_4\n"); 665 if (i & EHCI_CMD_ITC_8) 666 printf(" EHCI_CMD_ITC_8\n"); 667 if (i & EHCI_CMD_ITC_16) 668 printf(" EHCI_CMD_ITC_16\n"); 669 if (i & EHCI_CMD_ITC_32) 670 printf(" EHCI_CMD_ITC_32\n"); 671 if (i & EHCI_CMD_ITC_64) 672 printf(" EHCI_CMD_ITC_64\n"); 673 if (i & EHCI_CMD_ASPME) 674 printf(" EHCI_CMD_ASPME\n"); 675 if (i & EHCI_CMD_ASPMC) 676 printf(" EHCI_CMD_ASPMC\n"); 677 if (i & EHCI_CMD_LHCR) 678 printf(" EHCI_CMD_LHCR\n"); 679 if (i & EHCI_CMD_IAAD) 680 printf(" EHCI_CMD_IAAD\n"); 681 if (i & EHCI_CMD_ASE) 682 printf(" EHCI_CMD_ASE\n"); 683 if (i & EHCI_CMD_PSE) 684 printf(" EHCI_CMD_PSE\n"); 685 if (i & EHCI_CMD_FLS_M) 686 printf(" EHCI_CMD_FLS_M\n"); 687 if (i & EHCI_CMD_HCRESET) 688 printf(" EHCI_CMD_HCRESET\n"); 689 if (i & EHCI_CMD_RS) 690 printf(" EHCI_CMD_RS\n"); 691 692 i = EOREAD4(sc, EHCI_USBSTS); 693 694 printf("sts=0x%08x\n", i); 695 696 if (i & EHCI_STS_ASS) 697 printf(" EHCI_STS_ASS\n"); 698 if (i & EHCI_STS_PSS) 699 printf(" EHCI_STS_PSS\n"); 700 if (i & EHCI_STS_REC) 701 printf(" EHCI_STS_REC\n"); 702 if (i & EHCI_STS_HCH) 703 printf(" EHCI_STS_HCH\n"); 704 if (i & EHCI_STS_IAA) 705 printf(" EHCI_STS_IAA\n"); 706 if (i & EHCI_STS_HSE) 707 printf(" EHCI_STS_HSE\n"); 708 if (i & EHCI_STS_FLR) 709 printf(" EHCI_STS_FLR\n"); 710 if (i & EHCI_STS_PCD) 711 printf(" EHCI_STS_PCD\n"); 712 if (i & EHCI_STS_ERRINT) 713 printf(" EHCI_STS_ERRINT\n"); 714 if (i & EHCI_STS_INT) 715 printf(" EHCI_STS_INT\n"); 716 717 printf("ien=0x%08x\n", 718 EOREAD4(sc, EHCI_USBINTR)); 719 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 720 EOREAD4(sc, EHCI_FRINDEX), 721 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 722 EOREAD4(sc, EHCI_PERIODICLISTBASE), 723 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 724 for (i = 1; i <= sc->sc_noport; i++) { 725 printf("port %d status=0x%08x\n", i, 726 EOREAD4(sc, EHCI_PORTSC(i))); 727 } 728 return; 729} 730 731static void 732ehci_dump_link(uint32_t link, int type) 733{ 734 link = le32toh(link); 735 printf("0x%08x", link); 736 if (link & EHCI_LINK_TERMINATE) 737 printf("<T>"); 738 else { 739 printf("<"); 740 if (type) { 741 switch (EHCI_LINK_TYPE(link)) { 742 case EHCI_LINK_ITD: 743 printf("ITD"); 744 break; 745 case EHCI_LINK_QH: 746 printf("QH"); 747 break; 748 case EHCI_LINK_SITD: 749 printf("SITD"); 750 break; 751 case EHCI_LINK_FSTN: 752 printf("FSTN"); 753 break; 754 } 755 } 756 printf(">"); 757 } 758 return; 759} 760 761static void 762ehci_dump_qtd(ehci_qtd_t *qtd) 763{ 764 uint32_t s; 765 766 printf(" next="); 767 ehci_dump_link(qtd->qtd_next, 0); 768 printf(" altnext="); 769 ehci_dump_link(qtd->qtd_altnext, 0); 770 printf("\n"); 771 s = le32toh(qtd->qtd_status); 772 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 773 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 774 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 775 printf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n", 776 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), 777 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE", 778 (s & EHCI_QTD_HALTED) ? "-HALTED" : "", 779 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "", 780 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "", 781 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "", 782 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "", 783 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "", 784 (s & EHCI_QTD_PINGSTATE) ? "-PING" : ""); 785 786 for (s = 0; s < 5; s++) { 787 printf(" buffer[%d]=0x%08x\n", s, 788 le32toh(qtd->qtd_buffer[s])); 789 } 790 for (s = 0; s < 5; s++) { 791 printf(" buffer_hi[%d]=0x%08x\n", s, 792 le32toh(qtd->qtd_buffer_hi[s])); 793 } 794 return; 795} 796 797static uint8_t 798ehci_dump_sqtd(ehci_qtd_t *sqtd) 799{ 800 uint8_t temp; 801 802 usb2_pc_cpu_invalidate(sqtd->page_cache); 803 printf("QTD(%p) at 0x%08x:\n", sqtd, le32toh(sqtd->qtd_self)); 804 ehci_dump_qtd(sqtd); 805 temp = (sqtd->qtd_next & htole32(EHCI_LINK_TERMINATE)) ? 1 : 0; 806 return (temp); 807} 808 809static void 810ehci_dump_sqtds(ehci_qtd_t *sqtd) 811{ 812 uint16_t i; 813 uint8_t stop; 814 815 stop = 0; 816 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) { 817 stop = ehci_dump_sqtd(sqtd); 818 } 819 if (sqtd) { 820 printf("dump aborted, too many TDs\n"); 821 } 822 return; 823} 824 825static void 826ehci_dump_sqh(ehci_qh_t *qh) 827{ 828 uint32_t endp, endphub; 829 830 usb2_pc_cpu_invalidate(qh->page_cache); 831 printf("QH(%p) at 0x%08x:\n", qh, le32toh(qh->qh_self) & ~0x1F); 832 printf(" link="); 833 ehci_dump_link(qh->qh_link, 1); 834 printf("\n"); 835 endp = le32toh(qh->qh_endp); 836 printf(" endp=0x%08x\n", endp); 837 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 838 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 839 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 840 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 841 printf(" mpl=0x%x ctl=%d nrl=%d\n", 842 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 843 EHCI_QH_GET_NRL(endp)); 844 endphub = le32toh(qh->qh_endphub); 845 printf(" endphub=0x%08x\n", endphub); 846 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 847 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 848 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 849 EHCI_QH_GET_MULT(endphub)); 850 printf(" curqtd="); 851 ehci_dump_link(qh->qh_curqtd, 0); 852 printf("\n"); 853 printf("Overlay qTD:\n"); 854 ehci_dump_qtd((void *)&qh->qh_qtd); 855 return; 856} 857 858static void 859ehci_dump_sitd(ehci_sitd_t *sitd) 860{ 861 usb2_pc_cpu_invalidate(sitd->page_cache); 862 printf("SITD(%p) at 0x%08x\n", sitd, le32toh(sitd->sitd_self) & ~0x1F); 863 printf(" next=0x%08x\n", le32toh(sitd->sitd_next)); 864 printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n", 865 le32toh(sitd->sitd_portaddr), 866 (sitd->sitd_portaddr & htole32(EHCI_SITD_SET_DIR_IN)) 867 ? "in" : "out", 868 EHCI_SITD_GET_ADDR(le32toh(sitd->sitd_portaddr)), 869 EHCI_SITD_GET_ENDPT(le32toh(sitd->sitd_portaddr)), 870 EHCI_SITD_GET_PORT(le32toh(sitd->sitd_portaddr)), 871 EHCI_SITD_GET_HUBA(le32toh(sitd->sitd_portaddr))); 872 printf(" mask=0x%08x\n", le32toh(sitd->sitd_mask)); 873 printf(" status=0x%08x <%s> len=0x%x\n", le32toh(sitd->sitd_status), 874 (sitd->sitd_status & htole32(EHCI_SITD_ACTIVE)) ? "ACTIVE" : "", 875 EHCI_SITD_GET_LEN(le32toh(sitd->sitd_status))); 876 printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n", 877 le32toh(sitd->sitd_back), 878 le32toh(sitd->sitd_bp[0]), 879 le32toh(sitd->sitd_bp[1]), 880 le32toh(sitd->sitd_bp_hi[0]), 881 le32toh(sitd->sitd_bp_hi[1])); 882 return; 883} 884 885static void 886ehci_dump_itd(ehci_itd_t *itd) 887{ 888 usb2_pc_cpu_invalidate(itd->page_cache); 889 printf("ITD(%p) at 0x%08x\n", itd, le32toh(itd->itd_self) & ~0x1F); 890 printf(" next=0x%08x\n", le32toh(itd->itd_next)); 891 printf(" status[0]=0x%08x; <%s>\n", le32toh(itd->itd_status[0]), 892 (itd->itd_status[0] & htole32(EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 893 printf(" status[1]=0x%08x; <%s>\n", le32toh(itd->itd_status[1]), 894 (itd->itd_status[1] & htole32(EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 895 printf(" status[2]=0x%08x; <%s>\n", le32toh(itd->itd_status[2]), 896 (itd->itd_status[2] & htole32(EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 897 printf(" status[3]=0x%08x; <%s>\n", le32toh(itd->itd_status[3]), 898 (itd->itd_status[3] & htole32(EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 899 printf(" status[4]=0x%08x; <%s>\n", le32toh(itd->itd_status[4]), 900 (itd->itd_status[4] & htole32(EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 901 printf(" status[5]=0x%08x; <%s>\n", le32toh(itd->itd_status[5]), 902 (itd->itd_status[5] & htole32(EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 903 printf(" status[6]=0x%08x; <%s>\n", le32toh(itd->itd_status[6]), 904 (itd->itd_status[6] & htole32(EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 905 printf(" status[7]=0x%08x; <%s>\n", le32toh(itd->itd_status[7]), 906 (itd->itd_status[7] & htole32(EHCI_ITD_ACTIVE)) ? "ACTIVE" : ""); 907 printf(" bp[0]=0x%08x\n", le32toh(itd->itd_bp[0])); 908 printf(" addr=0x%02x; endpt=0x%01x\n", 909 EHCI_ITD_GET_ADDR(le32toh(itd->itd_bp[0])), 910 EHCI_ITD_GET_ENDPT(le32toh(itd->itd_bp[0]))); 911 printf(" bp[1]=0x%08x\n", le32toh(itd->itd_bp[1])); 912 printf(" dir=%s; mpl=0x%02x\n", 913 (le32toh(itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out", 914 EHCI_ITD_GET_MPL(le32toh(itd->itd_bp[1]))); 915 printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n", 916 le32toh(itd->itd_bp[2]), 917 le32toh(itd->itd_bp[3]), 918 le32toh(itd->itd_bp[4]), 919 le32toh(itd->itd_bp[5]), 920 le32toh(itd->itd_bp[6])); 921 printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n" 922 " 0x%08x,0x%08x,0x%08x\n", 923 le32toh(itd->itd_bp_hi[0]), 924 le32toh(itd->itd_bp_hi[1]), 925 le32toh(itd->itd_bp_hi[2]), 926 le32toh(itd->itd_bp_hi[3]), 927 le32toh(itd->itd_bp_hi[4]), 928 le32toh(itd->itd_bp_hi[5]), 929 le32toh(itd->itd_bp_hi[6])); 930 return; 931} 932 933static void 934ehci_dump_isoc(ehci_softc_t *sc) 935{ 936 ehci_itd_t *itd; 937 ehci_sitd_t *sitd; 938 uint16_t max = 1000; 939 uint16_t pos; 940 941 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) & 942 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 943 944 printf("%s: isochronous dump from frame 0x%03x:\n", 945 __FUNCTION__, pos); 946 947 itd = sc->sc_isoc_hs_p_last[pos]; 948 sitd = sc->sc_isoc_fs_p_last[pos]; 949 950 while (itd && max && max--) { 951 ehci_dump_itd(itd); 952 itd = itd->prev; 953 } 954 955 while (sitd && max && max--) { 956 ehci_dump_sitd(sitd); 957 sitd = sitd->prev; 958 } 959 return; 960} 961 962#endif 963 964static void 965ehci_transfer_intr_enqueue(struct usb2_xfer *xfer) 966{ 967 /* check for early completion */ 968 if (ehci_check_transfer(xfer)) { 969 return; 970 } 971 /* put transfer on interrupt queue */ 972 usb2_transfer_enqueue(&xfer->udev->bus->intr_q, xfer); 973 974 /* start timeout, if any */ 975 if (xfer->timeout != 0) { 976 usb2_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout); 977 } 978 return; 979} 980 981#define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last) 982static ehci_sitd_t * 983_ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 984{ 985 DPRINTFN(11, "%p to %p\n", std, last); 986 987 /* (sc->sc_bus.mtx) must be locked */ 988 989 std->next = last->next; 990 std->sitd_next = last->sitd_next; 991 992 std->prev = last; 993 994 usb2_pc_cpu_flush(std->page_cache); 995 996 /* 997 * the last->next->prev is never followed: std->next->prev = std; 998 */ 999 last->next = std; 1000 last->sitd_next = std->sitd_self; 1001 1002 usb2_pc_cpu_flush(last->page_cache); 1003 1004 return (std); 1005} 1006 1007#define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last) 1008static ehci_itd_t * 1009_ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1010{ 1011 DPRINTFN(11, "%p to %p\n", std, last); 1012 1013 /* (sc->sc_bus.mtx) must be locked */ 1014 1015 std->next = last->next; 1016 std->itd_next = last->itd_next; 1017 1018 std->prev = last; 1019 1020 usb2_pc_cpu_flush(std->page_cache); 1021 1022 /* 1023 * the last->next->prev is never followed: std->next->prev = std; 1024 */ 1025 last->next = std; 1026 last->itd_next = std->itd_self; 1027 1028 usb2_pc_cpu_flush(last->page_cache); 1029 1030 return (std); 1031} 1032 1033#define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last) 1034static ehci_qh_t * 1035_ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1036{ 1037 DPRINTFN(11, "%p to %p\n", sqh, last); 1038 1039 /* (sc->sc_bus.mtx) must be locked */ 1040 1041 sqh->next = last->next; 1042 sqh->qh_link = last->qh_link; 1043 1044 sqh->prev = last; 1045 1046 usb2_pc_cpu_flush(sqh->page_cache); 1047 1048 /* 1049 * the last->next->prev is never followed: sqh->next->prev = sqh; 1050 */ 1051 1052 last->next = sqh; 1053 last->qh_link = sqh->qh_self; 1054 1055 usb2_pc_cpu_flush(last->page_cache); 1056 1057#if USB_DEBUG 1058 if (ehcidebug > 5) { 1059 printf("%s:\n", __FUNCTION__); 1060 ehci_dump_sqh(sqh); 1061 } 1062#endif 1063 return (sqh); 1064} 1065 1066#define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last) 1067static ehci_sitd_t * 1068_ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last) 1069{ 1070 DPRINTFN(11, "%p from %p\n", std, last); 1071 1072 /* (sc->sc_bus.mtx) must be locked */ 1073 1074 std->prev->next = std->next; 1075 std->prev->sitd_next = std->sitd_next; 1076 1077 usb2_pc_cpu_flush(std->prev->page_cache); 1078 1079 if (std->next) { 1080 std->next->prev = std->prev; 1081 usb2_pc_cpu_flush(std->next->page_cache); 1082 } 1083 return ((last == std) ? std->prev : last); 1084} 1085 1086#define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last) 1087static ehci_itd_t * 1088_ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last) 1089{ 1090 DPRINTFN(11, "%p from %p\n", std, last); 1091 1092 /* (sc->sc_bus.mtx) must be locked */ 1093 1094 std->prev->next = std->next; 1095 std->prev->itd_next = std->itd_next; 1096 1097 usb2_pc_cpu_flush(std->prev->page_cache); 1098 1099 if (std->next) { 1100 std->next->prev = std->prev; 1101 usb2_pc_cpu_flush(std->next->page_cache); 1102 } 1103 return ((last == std) ? std->prev : last); 1104} 1105 1106#define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last) 1107static ehci_qh_t * 1108_ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last) 1109{ 1110 DPRINTFN(11, "%p from %p\n", sqh, last); 1111 1112 /* (sc->sc_bus.mtx) must be locked */ 1113 1114 /* only remove if not removed from a queue */ 1115 if (sqh->prev) { 1116 1117 sqh->prev->next = sqh->next; 1118 sqh->prev->qh_link = sqh->qh_link; 1119 1120 usb2_pc_cpu_flush(sqh->prev->page_cache); 1121 1122 if (sqh->next) { 1123 sqh->next->prev = sqh->prev; 1124 usb2_pc_cpu_flush(sqh->next->page_cache); 1125 } 1126 /* 1127 * set the Terminate-bit in the e_next of the QH, in case 1128 * the transferred packet was short so that the QH still 1129 * points at the last used TD 1130 */ 1131 1132 sqh->qh_qtd.qtd_next = htole32(EHCI_LINK_TERMINATE); 1133 1134 last = ((last == sqh) ? sqh->prev : last); 1135 1136 sqh->prev = 0; 1137 1138 usb2_pc_cpu_flush(sqh->page_cache); 1139 } 1140 return (last); 1141} 1142 1143static usb2_error_t 1144ehci_non_isoc_done_sub(struct usb2_xfer *xfer) 1145{ 1146 ehci_qtd_t *td; 1147 ehci_qtd_t *td_alt_next; 1148 uint32_t status; 1149 uint16_t len; 1150 1151 td = xfer->td_transfer_cache; 1152 td_alt_next = td->alt_next; 1153 1154 while (1) { 1155 1156 usb2_pc_cpu_invalidate(td->page_cache); 1157 status = le32toh(td->qtd_status); 1158 1159 len = EHCI_QTD_GET_BYTES(status); 1160 1161 /* 1162 * Verify the status length and subtract 1163 * the remainder from "frlengths[]": 1164 */ 1165 if (len > td->len) { 1166 /* should not happen */ 1167 DPRINTF("Invalid status length, " 1168 "0x%04x/0x%04x bytes\n", len, td->len); 1169 status |= EHCI_QTD_HALTED; 1170 } else if (xfer->aframes != xfer->nframes) { 1171 xfer->frlengths[xfer->aframes] -= len; 1172 } 1173 /* Check for last transfer */ 1174 if (((void *)td) == xfer->td_transfer_last) { 1175 if (len == 0) { 1176 /* 1177 * Halt is ok if descriptor is last, 1178 * and complete: 1179 */ 1180 status &= ~EHCI_QTD_HALTED; 1181 } 1182 td = NULL; 1183 break; 1184 } 1185 /* Check for transfer error */ 1186 if (status & EHCI_QTD_HALTED) { 1187 /* the transfer is finished */ 1188 td = NULL; 1189 break; 1190 } 1191 /* Check for short transfer */ 1192 if (len > 0) { 1193 if (xfer->flags_int.short_frames_ok) { 1194 /* follow alt next */ 1195 td = td->alt_next; 1196 } else { 1197 /* the transfer is finished */ 1198 td = NULL; 1199 } 1200 break; 1201 } 1202 td = td->obj_next; 1203 1204 if (td->alt_next != td_alt_next) { 1205 /* this USB frame is complete */ 1206 break; 1207 } 1208 } 1209 1210 /* update transfer cache */ 1211 1212 xfer->td_transfer_cache = td; 1213 1214 /* update data toggle */ 1215 1216 xfer->pipe->toggle_next = 1217 (status & EHCI_QTD_TOGGLE_MASK) ? 1 : 0; 1218 1219#if USB_DEBUG 1220 if (status & EHCI_QTD_STATERRS) { 1221 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x" 1222 "status=%s%s%s%s%s%s%s%s\n", 1223 xfer->address, xfer->endpoint, xfer->aframes, 1224 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]", 1225 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "", 1226 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "", 1227 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "", 1228 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "", 1229 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "", 1230 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "", 1231 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : ""); 1232 } 1233#endif 1234 1235 return ((status & EHCI_QTD_HALTED) ? 1236 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1237} 1238 1239static void 1240ehci_non_isoc_done(struct usb2_xfer *xfer) 1241{ 1242 usb2_error_t err = 0; 1243 1244 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 1245 xfer, xfer->pipe); 1246 1247#if USB_DEBUG 1248 if (ehcidebug > 10) { 1249 ehci_dump_sqtds(xfer->td_transfer_first); 1250 } 1251#endif 1252 1253 /* reset scanner */ 1254 1255 xfer->td_transfer_cache = xfer->td_transfer_first; 1256 1257 if (xfer->flags_int.control_xfr) { 1258 1259 if (xfer->flags_int.control_hdr) { 1260 1261 err = ehci_non_isoc_done_sub(xfer); 1262 } 1263 xfer->aframes = 1; 1264 1265 if (xfer->td_transfer_cache == NULL) { 1266 goto done; 1267 } 1268 } 1269 while (xfer->aframes != xfer->nframes) { 1270 1271 err = ehci_non_isoc_done_sub(xfer); 1272 xfer->aframes++; 1273 1274 if (xfer->td_transfer_cache == NULL) { 1275 goto done; 1276 } 1277 } 1278 1279 if (xfer->flags_int.control_xfr && 1280 !xfer->flags_int.control_act) { 1281 1282 err = ehci_non_isoc_done_sub(xfer); 1283 } 1284done: 1285 ehci_device_done(xfer, err); 1286 return; 1287} 1288 1289/*------------------------------------------------------------------------* 1290 * ehci_check_transfer 1291 * 1292 * Return values: 1293 * 0: USB transfer is not finished 1294 * Else: USB transfer is finished 1295 *------------------------------------------------------------------------*/ 1296static uint8_t 1297ehci_check_transfer(struct usb2_xfer *xfer) 1298{ 1299 struct usb2_pipe_methods *methods = xfer->pipe->methods; 1300 1301 uint32_t status; 1302 1303 DPRINTFN(13, "xfer=%p checking transfer\n", xfer); 1304 1305 if (methods == &ehci_device_isoc_fs_methods) { 1306 ehci_sitd_t *td; 1307 1308 /* isochronous full speed transfer */ 1309 1310 td = xfer->td_transfer_last; 1311 usb2_pc_cpu_invalidate(td->page_cache); 1312 status = le32toh(td->sitd_status); 1313 1314 /* also check if first is complete */ 1315 1316 td = xfer->td_transfer_first; 1317 usb2_pc_cpu_invalidate(td->page_cache); 1318 status |= le32toh(td->sitd_status); 1319 1320 if (!(status & EHCI_SITD_ACTIVE)) { 1321 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1322 goto transferred; 1323 } 1324 } else if (methods == &ehci_device_isoc_hs_methods) { 1325 ehci_itd_t *td; 1326 1327 /* isochronous high speed transfer */ 1328 1329 td = xfer->td_transfer_last; 1330 usb2_pc_cpu_invalidate(td->page_cache); 1331 status = 1332 td->itd_status[0] | td->itd_status[1] | 1333 td->itd_status[2] | td->itd_status[3] | 1334 td->itd_status[4] | td->itd_status[5] | 1335 td->itd_status[6] | td->itd_status[7]; 1336 1337 /* also check first transfer */ 1338 td = xfer->td_transfer_first; 1339 usb2_pc_cpu_invalidate(td->page_cache); 1340 status |= 1341 td->itd_status[0] | td->itd_status[1] | 1342 td->itd_status[2] | td->itd_status[3] | 1343 td->itd_status[4] | td->itd_status[5] | 1344 td->itd_status[6] | td->itd_status[7]; 1345 1346 /* if no transactions are active we continue */ 1347 if (!(status & htole32(EHCI_ITD_ACTIVE))) { 1348 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION); 1349 goto transferred; 1350 } 1351 } else { 1352 ehci_qtd_t *td; 1353 1354 /* non-isochronous transfer */ 1355 1356 /* 1357 * check whether there is an error somewhere in the middle, 1358 * or whether there was a short packet (SPD and not ACTIVE) 1359 */ 1360 td = xfer->td_transfer_cache; 1361 1362 while (1) { 1363 usb2_pc_cpu_invalidate(td->page_cache); 1364 status = le32toh(td->qtd_status); 1365 1366 /* 1367 * if there is an active TD the transfer isn't done 1368 */ 1369 if (status & EHCI_QTD_ACTIVE) { 1370 /* update cache */ 1371 xfer->td_transfer_cache = td; 1372 goto done; 1373 } 1374 /* 1375 * last transfer descriptor makes the transfer done 1376 */ 1377 if (((void *)td) == xfer->td_transfer_last) { 1378 break; 1379 } 1380 /* 1381 * any kind of error makes the transfer done 1382 */ 1383 if (status & EHCI_QTD_HALTED) { 1384 break; 1385 } 1386 /* 1387 * if there is no alternate next transfer, a short 1388 * packet also makes the transfer done 1389 */ 1390 if (EHCI_QTD_GET_BYTES(status)) { 1391 if (xfer->flags_int.short_frames_ok) { 1392 /* follow alt next */ 1393 if (td->alt_next) { 1394 td = td->alt_next; 1395 continue; 1396 } 1397 } 1398 /* transfer is done */ 1399 break; 1400 } 1401 td = td->obj_next; 1402 } 1403 ehci_non_isoc_done(xfer); 1404 goto transferred; 1405 } 1406 1407done: 1408 DPRINTFN(13, "xfer=%p is still active\n", xfer); 1409 return (0); 1410 1411transferred: 1412 return (1); 1413} 1414 1415static void 1416ehci_pcd_enable(ehci_softc_t *sc) 1417{ 1418 mtx_assert(&sc->sc_bus.mtx, MA_OWNED); 1419 1420 sc->sc_eintrs |= EHCI_STS_PCD; 1421 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1422 1423 /* acknowledge any PCD interrupt */ 1424 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD); 1425 1426 usb2_sw_transfer(&sc->sc_root_intr, 1427 &ehci_root_intr_done); 1428 1429 mtx_unlock(&sc->sc_bus.mtx); 1430 return; 1431} 1432 1433static void 1434ehci_interrupt_poll(ehci_softc_t *sc) 1435{ 1436 struct usb2_xfer *xfer; 1437 1438repeat: 1439 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 1440 /* 1441 * check if transfer is transferred 1442 */ 1443 if (ehci_check_transfer(xfer)) { 1444 /* queue has been modified */ 1445 goto repeat; 1446 } 1447 } 1448 return; 1449} 1450 1451/*------------------------------------------------------------------------* 1452 * ehci_interrupt - EHCI interrupt handler 1453 * 1454 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler, 1455 * hence the interrupt handler will be setup before "sc->sc_bus.bdev" 1456 * is present ! 1457 *------------------------------------------------------------------------*/ 1458void 1459ehci_interrupt(ehci_softc_t *sc) 1460{ 1461 uint32_t status; 1462 1463 mtx_lock(&sc->sc_bus.mtx); 1464 1465 DPRINTFN(16, "real interrupt\n"); 1466 1467#if USB_DEBUG 1468 if (ehcidebug > 15) { 1469 ehci_dump_regs(sc); 1470 } 1471#endif 1472 1473 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1474 if (status == 0) { 1475 /* the interrupt was not for us */ 1476 goto done; 1477 } 1478 if (!(status & sc->sc_eintrs)) { 1479 goto done; 1480 } 1481 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */ 1482 1483 status &= sc->sc_eintrs; 1484 1485 if (status & EHCI_STS_HSE) { 1486 printf("%s: unrecoverable error, " 1487 "controller halted\n", __FUNCTION__); 1488#if USB_DEBUG 1489 ehci_dump_regs(sc); 1490 ehci_dump_isoc(sc); 1491#endif 1492 } 1493 if (status & EHCI_STS_PCD) { 1494 /* 1495 * Disable PCD interrupt for now, because it will be 1496 * on until the port has been reset. 1497 */ 1498 sc->sc_eintrs &= ~EHCI_STS_PCD; 1499 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1500 1501 usb2_sw_transfer(&sc->sc_root_intr, 1502 &ehci_root_intr_done); 1503 1504 /* do not allow RHSC interrupts > 1 per second */ 1505 usb2_callout_reset(&sc->sc_tmo_pcd, hz, 1506 (void *)&ehci_pcd_enable, sc); 1507 } 1508 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA); 1509 1510 if (status != 0) { 1511 /* block unprocessed interrupts */ 1512 sc->sc_eintrs &= ~status; 1513 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1514 printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status); 1515 } 1516 /* poll all the USB transfers */ 1517 ehci_interrupt_poll(sc); 1518 1519done: 1520 mtx_unlock(&sc->sc_bus.mtx); 1521 return; 1522} 1523 1524/* 1525 * called when a request does not complete 1526 */ 1527static void 1528ehci_timeout(void *arg) 1529{ 1530 struct usb2_xfer *xfer = arg; 1531 ehci_softc_t *sc = xfer->usb2_sc; 1532 1533 DPRINTF("xfer=%p\n", xfer); 1534 1535 mtx_assert(&sc->sc_bus.mtx, MA_OWNED); 1536 1537 /* transfer is transferred */ 1538 ehci_device_done(xfer, USB_ERR_TIMEOUT); 1539 1540 mtx_unlock(&sc->sc_bus.mtx); 1541 1542 return; 1543} 1544 1545static void 1546ehci_do_poll(struct usb2_bus *bus) 1547{ 1548 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1549 1550 mtx_lock(&sc->sc_bus.mtx); 1551 ehci_interrupt_poll(sc); 1552 ehci_root_ctrl_poll(sc); 1553 mtx_unlock(&sc->sc_bus.mtx); 1554 return; 1555} 1556 1557static void 1558ehci_setup_standard_chain_sub(struct ehci_std_temp *temp) 1559{ 1560 struct usb2_page_search buf_res; 1561 ehci_qtd_t *td; 1562 ehci_qtd_t *td_next; 1563 ehci_qtd_t *td_alt_next; 1564 uint32_t qtd_altnext; 1565 uint32_t buf_offset; 1566 uint32_t average; 1567 uint32_t len_old; 1568 uint8_t shortpkt_old; 1569 uint8_t precompute; 1570 1571 qtd_altnext = htole32(EHCI_LINK_TERMINATE); 1572 td_alt_next = NULL; 1573 buf_offset = 0; 1574 shortpkt_old = temp->shortpkt; 1575 len_old = temp->len; 1576 precompute = 1; 1577 1578restart: 1579 1580 td = temp->td; 1581 td_next = temp->td_next; 1582 1583 while (1) { 1584 1585 if (temp->len == 0) { 1586 1587 if (temp->shortpkt) { 1588 break; 1589 } 1590 /* send a Zero Length Packet, ZLP, last */ 1591 1592 temp->shortpkt = 1; 1593 average = 0; 1594 1595 } else { 1596 1597 average = temp->average; 1598 1599 if (temp->len < average) { 1600 if (temp->len % temp->max_frame_size) { 1601 temp->shortpkt = 1; 1602 } 1603 average = temp->len; 1604 } 1605 } 1606 1607 if (td_next == NULL) { 1608 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__); 1609 } 1610 /* get next TD */ 1611 1612 td = td_next; 1613 td_next = td->obj_next; 1614 1615 /* check if we are pre-computing */ 1616 1617 if (precompute) { 1618 1619 /* update remaining length */ 1620 1621 temp->len -= average; 1622 1623 continue; 1624 } 1625 /* fill out current TD */ 1626 1627 td->qtd_status = 1628 temp->qtd_status | htole32(EHCI_QTD_SET_BYTES(average)); 1629 1630 if (average == 0) { 1631 1632 if (temp->auto_data_toggle == 0) { 1633 1634 /* update data toggle, ZLP case */ 1635 1636 temp->qtd_status ^= htole32(EHCI_QTD_TOGGLE_MASK); 1637 } 1638 td->len = 0; 1639 1640 td->qtd_buffer[0] = 0; 1641 td->qtd_buffer_hi[0] = 0; 1642 1643 td->qtd_buffer[1] = 0; 1644 td->qtd_buffer_hi[1] = 0; 1645 1646 } else { 1647 1648 uint8_t x; 1649 1650 if (temp->auto_data_toggle == 0) { 1651 1652 /* update data toggle */ 1653 1654 if (((average + temp->max_frame_size - 1) / 1655 temp->max_frame_size) & 1) { 1656 temp->qtd_status ^= htole32(EHCI_QTD_TOGGLE_MASK); 1657 } 1658 } 1659 td->len = average; 1660 1661 /* update remaining length */ 1662 1663 temp->len -= average; 1664 1665 /* fill out buffer pointers */ 1666 1667 usb2_get_page(temp->pc, buf_offset, &buf_res); 1668 td->qtd_buffer[0] = htole32(buf_res.physaddr); 1669 td->qtd_buffer_hi[0] = 0; 1670 1671 x = 1; 1672 1673 while (average > EHCI_PAGE_SIZE) { 1674 average -= EHCI_PAGE_SIZE; 1675 buf_offset += EHCI_PAGE_SIZE; 1676 usb2_get_page(temp->pc, buf_offset, &buf_res); 1677 td->qtd_buffer[x] = htole32(buf_res.physaddr & (~0xFFF)); 1678 td->qtd_buffer_hi[x] = 0; 1679 x++; 1680 } 1681 1682 /* 1683 * NOTE: The "average" variable is never zero after 1684 * exiting the loop above ! 1685 * 1686 * NOTE: We have to subtract one from the offset to 1687 * ensure that we are computing the physical address 1688 * of a valid page ! 1689 */ 1690 buf_offset += average; 1691 usb2_get_page(temp->pc, buf_offset - 1, &buf_res); 1692 td->qtd_buffer[x] = htole32(buf_res.physaddr & (~0xFFF)); 1693 td->qtd_buffer_hi[x] = 0; 1694 } 1695 1696 if (td_next) { 1697 /* link the current TD with the next one */ 1698 td->qtd_next = td_next->qtd_self; 1699 } 1700 td->qtd_altnext = qtd_altnext; 1701 td->alt_next = td_alt_next; 1702 1703 usb2_pc_cpu_flush(td->page_cache); 1704 } 1705 1706 if (precompute) { 1707 precompute = 0; 1708 1709 /* setup alt next pointer, if any */ 1710 if (temp->short_frames_ok) { 1711 if (temp->setup_alt_next) { 1712 td_alt_next = td_next; 1713 qtd_altnext = td_next->qtd_self; 1714 } 1715 } else { 1716 /* we use this field internally */ 1717 td_alt_next = td_next; 1718 } 1719 1720 /* restore */ 1721 temp->shortpkt = shortpkt_old; 1722 temp->len = len_old; 1723 goto restart; 1724 } 1725 temp->td = td; 1726 temp->td_next = td_next; 1727 1728 return; 1729} 1730 1731static void 1732ehci_setup_standard_chain(struct usb2_xfer *xfer, ehci_qh_t **qh_last) 1733{ 1734 struct ehci_std_temp temp; 1735 struct usb2_pipe_methods *methods; 1736 ehci_qh_t *qh; 1737 ehci_qtd_t *td; 1738 uint32_t qh_endp; 1739 uint32_t qh_endphub; 1740 uint32_t x; 1741 1742 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1743 xfer->address, UE_GET_ADDR(xfer->endpoint), 1744 xfer->sumlen, usb2_get_speed(xfer->udev)); 1745 1746 temp.average = xfer->max_usb2_frame_size; 1747 temp.max_frame_size = xfer->max_frame_size; 1748 1749 /* toggle the DMA set we are using */ 1750 xfer->flags_int.curr_dma_set ^= 1; 1751 1752 /* get next DMA set */ 1753 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1754 1755 xfer->td_transfer_first = td; 1756 xfer->td_transfer_cache = td; 1757 1758 temp.td = NULL; 1759 temp.td_next = td; 1760 temp.qtd_status = 0; 1761 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1762 temp.short_frames_ok = xfer->flags_int.short_frames_ok; 1763 1764 if (xfer->flags_int.control_xfr) { 1765 if (xfer->pipe->toggle_next) { 1766 /* DATA1 is next */ 1767 temp.qtd_status |= htole32(EHCI_QTD_SET_TOGGLE(1)); 1768 } 1769 temp.auto_data_toggle = 0; 1770 } else { 1771 temp.auto_data_toggle = 1; 1772 } 1773 1774 if (usb2_get_speed(xfer->udev) != USB_SPEED_HIGH) { 1775 /* max 3 retries */ 1776 temp.qtd_status |= htole32(EHCI_QTD_SET_CERR(3)); 1777 } 1778 /* check if we should prepend a setup message */ 1779 1780 if (xfer->flags_int.control_xfr) { 1781 if (xfer->flags_int.control_hdr) { 1782 1783 temp.qtd_status &= htole32(EHCI_QTD_SET_CERR(3)); 1784 temp.qtd_status |= htole32 1785 (EHCI_QTD_ACTIVE | 1786 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 1787 EHCI_QTD_SET_TOGGLE(0)); 1788 1789 temp.len = xfer->frlengths[0]; 1790 temp.pc = xfer->frbuffers + 0; 1791 temp.shortpkt = temp.len ? 1 : 0; 1792 1793 ehci_setup_standard_chain_sub(&temp); 1794 } 1795 x = 1; 1796 } else { 1797 x = 0; 1798 } 1799 1800 while (x != xfer->nframes) { 1801 1802 /* DATA0 / DATA1 message */ 1803 1804 temp.len = xfer->frlengths[x]; 1805 temp.pc = xfer->frbuffers + x; 1806 1807 x++; 1808 1809 if (x == xfer->nframes) { 1810 temp.setup_alt_next = 0; 1811 } 1812 /* keep previous data toggle and error count */ 1813 1814 temp.qtd_status &= htole32(EHCI_QTD_SET_CERR(3) | 1815 EHCI_QTD_SET_TOGGLE(1)); 1816 1817 if (temp.len == 0) { 1818 1819 /* make sure that we send an USB packet */ 1820 1821 temp.shortpkt = 0; 1822 1823 } else { 1824 1825 /* regular data transfer */ 1826 1827 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1; 1828 } 1829 1830 /* set endpoint direction */ 1831 1832 temp.qtd_status |= 1833 (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) ? 1834 htole32(EHCI_QTD_ACTIVE | 1835 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) : 1836 htole32(EHCI_QTD_ACTIVE | 1837 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT)); 1838 1839 ehci_setup_standard_chain_sub(&temp); 1840 } 1841 1842 /* check if we should append a status stage */ 1843 1844 if (xfer->flags_int.control_xfr && 1845 !xfer->flags_int.control_act) { 1846 1847 /* 1848 * Send a DATA1 message and invert the current endpoint 1849 * direction. 1850 */ 1851 1852 temp.qtd_status &= htole32(EHCI_QTD_SET_CERR(3) | 1853 EHCI_QTD_SET_TOGGLE(1)); 1854 temp.qtd_status |= 1855 (UE_GET_DIR(xfer->endpoint) == UE_DIR_OUT) ? 1856 htole32(EHCI_QTD_ACTIVE | 1857 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) | 1858 EHCI_QTD_SET_TOGGLE(1)) : 1859 htole32(EHCI_QTD_ACTIVE | 1860 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) | 1861 EHCI_QTD_SET_TOGGLE(1)); 1862 1863 temp.len = 0; 1864 temp.pc = NULL; 1865 temp.shortpkt = 0; 1866 1867 ehci_setup_standard_chain_sub(&temp); 1868 } 1869 td = temp.td; 1870 1871 /* the last TD terminates the transfer: */ 1872 td->qtd_next = htole32(EHCI_LINK_TERMINATE); 1873 td->qtd_altnext = htole32(EHCI_LINK_TERMINATE); 1874 td->qtd_status |= htole32(EHCI_QTD_IOC); 1875 1876 usb2_pc_cpu_flush(td->page_cache); 1877 1878 /* must have at least one frame! */ 1879 1880 xfer->td_transfer_last = td; 1881 1882#if USB_DEBUG 1883 if (ehcidebug > 8) { 1884 DPRINTF("nexttog=%d; data before transfer:\n", 1885 xfer->pipe->toggle_next); 1886 ehci_dump_sqtds(xfer->td_transfer_first); 1887 } 1888#endif 1889 1890 methods = xfer->pipe->methods; 1891 1892 qh = xfer->qh_start[xfer->flags_int.curr_dma_set]; 1893 1894 /* the "qh_link" field is filled when the QH is added */ 1895 1896 qh_endp = 1897 (EHCI_QH_SET_ADDR(xfer->address) | 1898 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpoint)) | 1899 EHCI_QH_SET_MPL(xfer->max_packet_size)); 1900 1901 if (usb2_get_speed(xfer->udev) == USB_SPEED_HIGH) { 1902 qh_endp |= (EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | 1903 EHCI_QH_DTC | EHCI_QH_SET_NRL(8)); 1904 } else { 1905 1906 if (usb2_get_speed(xfer->udev) == USB_SPEED_FULL) { 1907 qh_endp |= (EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL) | 1908 EHCI_QH_DTC); 1909 } else { 1910 qh_endp |= (EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW) | 1911 EHCI_QH_DTC); 1912 } 1913 1914 if (methods == &ehci_device_ctrl_methods) { 1915 qh_endp |= EHCI_QH_CTL; 1916 } 1917 if (methods != &ehci_device_intr_methods) { 1918 /* Only try one time per microframe! */ 1919 qh_endp |= EHCI_QH_SET_NRL(1); 1920 } 1921 } 1922 1923 qh->qh_endp = htole32(qh_endp); 1924 1925 qh_endphub = 1926 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) | 1927 EHCI_QH_SET_CMASK(xfer->usb2_cmask) | 1928 EHCI_QH_SET_SMASK(xfer->usb2_smask) | 1929 EHCI_QH_SET_HUBA(xfer->udev->hs_hub_addr) | 1930 EHCI_QH_SET_PORT(xfer->udev->hs_port_no)); 1931 1932 qh->qh_endphub = htole32(qh_endphub); 1933 qh->qh_curqtd = htole32(0); 1934 1935 /* fill the overlay qTD */ 1936 qh->qh_qtd.qtd_status = htole32(0); 1937 1938 if (temp.auto_data_toggle) { 1939 1940 /* let the hardware compute the data toggle */ 1941 1942 qh->qh_endp &= ~htole32(EHCI_QH_DTC); 1943 1944 if (xfer->pipe->toggle_next) { 1945 /* DATA1 is next */ 1946 qh->qh_qtd.qtd_status |= htole32(EHCI_QTD_SET_TOGGLE(1)); 1947 } 1948 } 1949 td = xfer->td_transfer_first; 1950 1951 qh->qh_qtd.qtd_next = td->qtd_self; 1952 qh->qh_qtd.qtd_altnext = htole32(EHCI_LINK_TERMINATE); 1953 1954 usb2_pc_cpu_flush(qh->page_cache); 1955 1956 EHCI_APPEND_QH(qh, *qh_last); 1957 return; 1958} 1959 1960static void 1961ehci_root_intr_done(struct usb2_xfer *xfer, 1962 struct usb2_sw_transfer *std) 1963{ 1964 struct ehci_softc *sc = xfer->usb2_sc; 1965 uint16_t i; 1966 uint16_t m; 1967 1968 mtx_assert(&sc->sc_bus.mtx, MA_OWNED); 1969 1970 if (std->state != USB_SW_TR_PRE_DATA) { 1971 if (std->state == USB_SW_TR_PRE_CALLBACK) { 1972 /* transfer transferred */ 1973 ehci_device_done(xfer, std->err); 1974 } 1975 goto done; 1976 } 1977 /* setup buffer */ 1978 std->ptr = sc->sc_hub_idata; 1979 std->len = sizeof(sc->sc_hub_idata); 1980 1981 /* clear any old interrupt data */ 1982 bzero(sc->sc_hub_idata, sizeof(sc->sc_hub_idata)); 1983 1984 /* set bits */ 1985 m = (sc->sc_noport + 1); 1986 if (m > (8 * sizeof(sc->sc_hub_idata))) { 1987 m = (8 * sizeof(sc->sc_hub_idata)); 1988 } 1989 for (i = 1; i < m; i++) { 1990 /* pick out CHANGE bits from the status register */ 1991 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) { 1992 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 1993 DPRINTF("port %d changed\n", i); 1994 } 1995 } 1996done: 1997 return; 1998} 1999 2000static void 2001ehci_isoc_fs_done(ehci_softc_t *sc, struct usb2_xfer *xfer) 2002{ 2003 uint32_t nframes = xfer->nframes; 2004 uint32_t status; 2005 uint32_t *plen = xfer->frlengths; 2006 uint16_t len = 0; 2007 ehci_sitd_t *td = xfer->td_transfer_first; 2008 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos]; 2009 2010 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 2011 xfer, xfer->pipe); 2012 2013 while (nframes--) { 2014 if (td == NULL) { 2015 panic("%s:%d: out of TD's\n", 2016 __FUNCTION__, __LINE__); 2017 } 2018 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2019 pp_last = &sc->sc_isoc_fs_p_last[0]; 2020 } 2021#if USB_DEBUG 2022 if (ehcidebug > 15) { 2023 DPRINTF("isoc FS-TD\n"); 2024 ehci_dump_sitd(td); 2025 } 2026#endif 2027 usb2_pc_cpu_invalidate(td->page_cache); 2028 status = le32toh(td->sitd_status); 2029 2030 len = EHCI_SITD_GET_LEN(status); 2031 2032 if (*plen >= len) { 2033 len = *plen - len; 2034 } else { 2035 len = 0; 2036 } 2037 2038 *plen = len; 2039 2040 /* remove FS-TD from schedule */ 2041 EHCI_REMOVE_FS_TD(td, *pp_last); 2042 2043 pp_last++; 2044 plen++; 2045 td = td->obj_next; 2046 } 2047 2048 xfer->aframes = xfer->nframes; 2049 2050 return; 2051} 2052 2053static void 2054ehci_isoc_hs_done(ehci_softc_t *sc, struct usb2_xfer *xfer) 2055{ 2056 uint32_t nframes = xfer->nframes; 2057 uint32_t status; 2058 uint32_t *plen = xfer->frlengths; 2059 uint16_t len = 0; 2060 uint8_t td_no = 0; 2061 ehci_itd_t *td = xfer->td_transfer_first; 2062 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos]; 2063 2064 DPRINTFN(13, "xfer=%p pipe=%p transfer done\n", 2065 xfer, xfer->pipe); 2066 2067 while (nframes--) { 2068 if (td == NULL) { 2069 panic("%s:%d: out of TD's\n", 2070 __FUNCTION__, __LINE__); 2071 } 2072 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2073 pp_last = &sc->sc_isoc_hs_p_last[0]; 2074 } 2075#if USB_DEBUG 2076 if (ehcidebug > 15) { 2077 DPRINTF("isoc HS-TD\n"); 2078 ehci_dump_itd(td); 2079 } 2080#endif 2081 2082 usb2_pc_cpu_invalidate(td->page_cache); 2083 status = le32toh(td->itd_status[td_no]); 2084 2085 len = EHCI_ITD_GET_LEN(status); 2086 2087 if (*plen >= len) { 2088 /* 2089 * The length is valid. NOTE: The complete 2090 * length is written back into the status 2091 * field, and not the remainder like with 2092 * other transfer descriptor types. 2093 */ 2094 } else { 2095 /* Invalid length - truncate */ 2096 len = 0; 2097 } 2098 2099 *plen = len; 2100 2101 plen++; 2102 td_no++; 2103 2104 if ((td_no == 8) || (nframes == 0)) { 2105 /* remove HS-TD from schedule */ 2106 EHCI_REMOVE_HS_TD(td, *pp_last); 2107 pp_last++; 2108 2109 td_no = 0; 2110 td = td->obj_next; 2111 } 2112 } 2113 xfer->aframes = xfer->nframes; 2114 2115 return; 2116} 2117 2118/* NOTE: "done" can be run two times in a row, 2119 * from close and from interrupt 2120 */ 2121static void 2122ehci_device_done(struct usb2_xfer *xfer, usb2_error_t error) 2123{ 2124 struct usb2_pipe_methods *methods = xfer->pipe->methods; 2125 ehci_softc_t *sc = xfer->usb2_sc; 2126 2127 mtx_assert(&sc->sc_bus.mtx, MA_OWNED); 2128 2129 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n", 2130 xfer, xfer->pipe, error); 2131 2132 if ((methods == &ehci_device_bulk_methods) || 2133 (methods == &ehci_device_ctrl_methods)) { 2134#if USB_DEBUG 2135 if (ehcidebug > 8) { 2136 DPRINTF("nexttog=%d; data after transfer:\n", 2137 xfer->pipe->toggle_next); 2138 ehci_dump_sqtds(xfer->td_transfer_first); 2139 } 2140#endif 2141 2142 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2143 sc->sc_async_p_last); 2144 } 2145 if (methods == &ehci_device_intr_methods) { 2146 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set], 2147 sc->sc_intr_p_last[xfer->qh_pos]); 2148 } 2149 /* 2150 * Only finish isochronous transfers once which will update 2151 * "xfer->frlengths". 2152 */ 2153 if (xfer->td_transfer_first && 2154 xfer->td_transfer_last) { 2155 if (methods == &ehci_device_isoc_fs_methods) { 2156 ehci_isoc_fs_done(sc, xfer); 2157 } 2158 if (methods == &ehci_device_isoc_hs_methods) { 2159 ehci_isoc_hs_done(sc, xfer); 2160 } 2161 xfer->td_transfer_first = NULL; 2162 xfer->td_transfer_last = NULL; 2163 } 2164 /* dequeue transfer and start next transfer */ 2165 usb2_transfer_done(xfer, error); 2166 return; 2167} 2168 2169/*------------------------------------------------------------------------* 2170 * ehci bulk support 2171 *------------------------------------------------------------------------*/ 2172static void 2173ehci_device_bulk_open(struct usb2_xfer *xfer) 2174{ 2175 return; 2176} 2177 2178static void 2179ehci_device_bulk_close(struct usb2_xfer *xfer) 2180{ 2181 ehci_device_done(xfer, USB_ERR_CANCELLED); 2182 return; 2183} 2184 2185static void 2186ehci_device_bulk_enter(struct usb2_xfer *xfer) 2187{ 2188 return; 2189} 2190 2191static void 2192ehci_device_bulk_start(struct usb2_xfer *xfer) 2193{ 2194 ehci_softc_t *sc = xfer->usb2_sc; 2195 2196 /* setup TD's and QH */ 2197 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2198 2199 /* put transfer on interrupt queue */ 2200 ehci_transfer_intr_enqueue(xfer); 2201 return; 2202} 2203 2204struct usb2_pipe_methods ehci_device_bulk_methods = 2205{ 2206 .open = ehci_device_bulk_open, 2207 .close = ehci_device_bulk_close, 2208 .enter = ehci_device_bulk_enter, 2209 .start = ehci_device_bulk_start, 2210 .enter_is_cancelable = 1, 2211 .start_is_cancelable = 1, 2212}; 2213 2214/*------------------------------------------------------------------------* 2215 * ehci control support 2216 *------------------------------------------------------------------------*/ 2217static void 2218ehci_device_ctrl_open(struct usb2_xfer *xfer) 2219{ 2220 return; 2221} 2222 2223static void 2224ehci_device_ctrl_close(struct usb2_xfer *xfer) 2225{ 2226 ehci_device_done(xfer, USB_ERR_CANCELLED); 2227 return; 2228} 2229 2230static void 2231ehci_device_ctrl_enter(struct usb2_xfer *xfer) 2232{ 2233 return; 2234} 2235 2236static void 2237ehci_device_ctrl_start(struct usb2_xfer *xfer) 2238{ 2239 ehci_softc_t *sc = xfer->usb2_sc; 2240 2241 /* setup TD's and QH */ 2242 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last); 2243 2244 /* put transfer on interrupt queue */ 2245 ehci_transfer_intr_enqueue(xfer); 2246 return; 2247} 2248 2249struct usb2_pipe_methods ehci_device_ctrl_methods = 2250{ 2251 .open = ehci_device_ctrl_open, 2252 .close = ehci_device_ctrl_close, 2253 .enter = ehci_device_ctrl_enter, 2254 .start = ehci_device_ctrl_start, 2255 .enter_is_cancelable = 1, 2256 .start_is_cancelable = 1, 2257}; 2258 2259/*------------------------------------------------------------------------* 2260 * ehci interrupt support 2261 *------------------------------------------------------------------------*/ 2262static void 2263ehci_device_intr_open(struct usb2_xfer *xfer) 2264{ 2265 ehci_softc_t *sc = xfer->usb2_sc; 2266 uint16_t best; 2267 uint16_t bit; 2268 uint16_t x; 2269 uint8_t slot; 2270 2271 /* Allocate a microframe slot first: */ 2272 2273 slot = usb2_intr_schedule_adjust 2274 (xfer->udev, xfer->max_frame_size, USB_HS_MICRO_FRAMES_MAX); 2275 2276 if (usb2_get_speed(xfer->udev) == USB_SPEED_HIGH) { 2277 xfer->usb2_uframe = slot; 2278 xfer->usb2_smask = (1 << slot) & 0xFF; 2279 xfer->usb2_cmask = 0; 2280 } else { 2281 xfer->usb2_uframe = slot; 2282 xfer->usb2_smask = (1 << slot) & 0x3F; 2283 xfer->usb2_cmask = (-(4 << slot)) & 0xFE; 2284 } 2285 2286 /* 2287 * Find the best QH position corresponding to the given interval: 2288 */ 2289 2290 best = 0; 2291 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2; 2292 while (bit) { 2293 if (xfer->interval >= bit) { 2294 x = bit; 2295 best = bit; 2296 while (x & bit) { 2297 if (sc->sc_intr_stat[x] < 2298 sc->sc_intr_stat[best]) { 2299 best = x; 2300 } 2301 x++; 2302 } 2303 break; 2304 } 2305 bit >>= 1; 2306 } 2307 2308 sc->sc_intr_stat[best]++; 2309 xfer->qh_pos = best; 2310 2311 DPRINTFN(3, "best=%d interval=%d\n", 2312 best, xfer->interval); 2313 return; 2314} 2315 2316static void 2317ehci_device_intr_close(struct usb2_xfer *xfer) 2318{ 2319 ehci_softc_t *sc = xfer->usb2_sc; 2320 uint8_t slot; 2321 2322 slot = usb2_intr_schedule_adjust 2323 (xfer->udev, -(xfer->max_frame_size), xfer->usb2_uframe); 2324 2325 sc->sc_intr_stat[xfer->qh_pos]--; 2326 2327 ehci_device_done(xfer, USB_ERR_CANCELLED); 2328 return; 2329} 2330 2331static void 2332ehci_device_intr_enter(struct usb2_xfer *xfer) 2333{ 2334 return; 2335} 2336 2337static void 2338ehci_device_intr_start(struct usb2_xfer *xfer) 2339{ 2340 ehci_softc_t *sc = xfer->usb2_sc; 2341 2342 /* setup TD's and QH */ 2343 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]); 2344 2345 /* put transfer on interrupt queue */ 2346 ehci_transfer_intr_enqueue(xfer); 2347 return; 2348} 2349 2350struct usb2_pipe_methods ehci_device_intr_methods = 2351{ 2352 .open = ehci_device_intr_open, 2353 .close = ehci_device_intr_close, 2354 .enter = ehci_device_intr_enter, 2355 .start = ehci_device_intr_start, 2356 .enter_is_cancelable = 1, 2357 .start_is_cancelable = 1, 2358}; 2359 2360/*------------------------------------------------------------------------* 2361 * ehci full speed isochronous support 2362 *------------------------------------------------------------------------*/ 2363static void 2364ehci_device_isoc_fs_open(struct usb2_xfer *xfer) 2365{ 2366 ehci_sitd_t *td; 2367 uint32_t sitd_portaddr; 2368 uint8_t ds; 2369 2370 sitd_portaddr = 2371 EHCI_SITD_SET_ADDR(xfer->address) | 2372 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpoint)) | 2373 EHCI_SITD_SET_HUBA(xfer->udev->hs_hub_addr) | 2374 EHCI_SITD_SET_PORT(xfer->udev->hs_port_no); 2375 2376 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 2377 sitd_portaddr |= EHCI_SITD_SET_DIR_IN; 2378 } 2379 sitd_portaddr = htole32(sitd_portaddr); 2380 2381 /* initialize all TD's */ 2382 2383 for (ds = 0; ds != 2; ds++) { 2384 2385 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2386 2387 td->sitd_portaddr = sitd_portaddr; 2388 2389 /* 2390 * TODO: make some kind of automatic 2391 * SMASK/CMASK selection based on micro-frame 2392 * usage 2393 * 2394 * micro-frame usage (8 microframes per 1ms) 2395 */ 2396 td->sitd_back = htole32(EHCI_LINK_TERMINATE); 2397 2398 usb2_pc_cpu_flush(td->page_cache); 2399 } 2400 } 2401 return; 2402} 2403 2404static void 2405ehci_device_isoc_fs_close(struct usb2_xfer *xfer) 2406{ 2407 ehci_device_done(xfer, USB_ERR_CANCELLED); 2408 return; 2409} 2410 2411static void 2412ehci_device_isoc_fs_enter(struct usb2_xfer *xfer) 2413{ 2414 struct usb2_page_search buf_res; 2415 ehci_softc_t *sc = xfer->usb2_sc; 2416 struct usb2_fs_isoc_schedule *fss_start; 2417 struct usb2_fs_isoc_schedule *fss_end; 2418 struct usb2_fs_isoc_schedule *fss; 2419 ehci_sitd_t *td; 2420 ehci_sitd_t *td_last = NULL; 2421 ehci_sitd_t **pp_last; 2422 uint32_t *plen; 2423 uint32_t buf_offset; 2424 uint32_t nframes; 2425 uint32_t temp; 2426 uint32_t sitd_mask; 2427 uint16_t tlen; 2428 uint8_t sa; 2429 uint8_t sb; 2430 uint8_t error; 2431 2432#if USB_DEBUG 2433 uint8_t once = 1; 2434 2435#endif 2436 2437 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2438 xfer, xfer->pipe->isoc_next, xfer->nframes); 2439 2440 /* get the current frame index */ 2441 2442 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2443 2444 /* 2445 * check if the frame index is within the window where the frames 2446 * will be inserted 2447 */ 2448 buf_offset = (nframes - xfer->pipe->isoc_next) & 2449 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2450 2451 if ((xfer->pipe->is_synced == 0) || 2452 (buf_offset < xfer->nframes)) { 2453 /* 2454 * If there is data underflow or the pipe queue is empty we 2455 * schedule the transfer a few frames ahead of the current 2456 * frame position. Else two isochronous transfers might 2457 * overlap. 2458 */ 2459 xfer->pipe->isoc_next = (nframes + 3) & 2460 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2461 xfer->pipe->is_synced = 1; 2462 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 2463 } 2464 /* 2465 * compute how many milliseconds the insertion is ahead of the 2466 * current frame position: 2467 */ 2468 buf_offset = (xfer->pipe->isoc_next - nframes) & 2469 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2470 2471 /* 2472 * pre-compute when the isochronous transfer will be finished: 2473 */ 2474 xfer->isoc_time_complete = 2475 usb2_fs_isoc_schedule_isoc_time_expand 2476 (xfer->udev, &fss_start, &fss_end, nframes) + buf_offset + 2477 xfer->nframes; 2478 2479 /* get the real number of frames */ 2480 2481 nframes = xfer->nframes; 2482 2483 buf_offset = 0; 2484 2485 plen = xfer->frlengths; 2486 2487 /* toggle the DMA set we are using */ 2488 xfer->flags_int.curr_dma_set ^= 1; 2489 2490 /* get next DMA set */ 2491 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2492 xfer->td_transfer_first = td; 2493 2494 pp_last = &sc->sc_isoc_fs_p_last[xfer->pipe->isoc_next]; 2495 2496 /* store starting position */ 2497 2498 xfer->qh_pos = xfer->pipe->isoc_next; 2499 2500 fss = fss_start + (xfer->qh_pos % USB_ISOC_TIME_MAX); 2501 2502 while (nframes--) { 2503 if (td == NULL) { 2504 panic("%s:%d: out of TD's\n", 2505 __FUNCTION__, __LINE__); 2506 } 2507 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2508 pp_last = &sc->sc_isoc_fs_p_last[0]; 2509 } 2510 if (fss >= fss_end) { 2511 fss = fss_start; 2512 } 2513 /* reuse sitd_portaddr and sitd_back from last transfer */ 2514 2515 if (*plen > xfer->max_frame_size) { 2516#if USB_DEBUG 2517 if (once) { 2518 once = 0; 2519 printf("%s: frame length(%d) exceeds %d " 2520 "bytes (frame truncated)\n", 2521 __FUNCTION__, *plen, 2522 xfer->max_frame_size); 2523 } 2524#endif 2525 *plen = xfer->max_frame_size; 2526 } 2527 /* 2528 * We currently don't care if the ISOCHRONOUS schedule is 2529 * full! 2530 */ 2531 error = usb2_fs_isoc_schedule_alloc(fss, &sa, *plen); 2532 if (error) { 2533 /* 2534 * The FULL speed schedule is FULL! Set length 2535 * to zero. 2536 */ 2537 *plen = 0; 2538 } 2539 if (*plen) { 2540 /* 2541 * only call "usb2_get_page()" when we have a 2542 * non-zero length 2543 */ 2544 usb2_get_page(xfer->frbuffers, buf_offset, &buf_res); 2545 td->sitd_bp[0] = htole32(buf_res.physaddr); 2546 buf_offset += *plen; 2547 /* 2548 * NOTE: We need to subtract one from the offset so 2549 * that we are on a valid page! 2550 */ 2551 usb2_get_page(xfer->frbuffers, buf_offset - 1, 2552 &buf_res); 2553 temp = buf_res.physaddr & ~0xFFF; 2554 } else { 2555 td->sitd_bp[0] = 0; 2556 temp = 0; 2557 } 2558 2559 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_OUT) { 2560 tlen = *plen; 2561 if (tlen <= 188) { 2562 temp |= 1; /* T-count = 1, TP = ALL */ 2563 tlen = 1; 2564 } else { 2565 tlen += 187; 2566 tlen /= 188; 2567 temp |= tlen; /* T-count = [1..6] */ 2568 temp |= 8; /* TP = Begin */ 2569 } 2570 2571 tlen += sa; 2572 2573 if (tlen >= 8) { 2574 sb = 0; 2575 } else { 2576 sb = (1 << tlen); 2577 } 2578 2579 sa = (1 << sa); 2580 sa = (sb - sa) & 0x3F; 2581 sb = 0; 2582 } else { 2583 sb = (-(4 << sa)) & 0xFE; 2584 sa = (1 << sa) & 0x3F; 2585 } 2586 2587 sitd_mask = (EHCI_SITD_SET_SMASK(sa) | 2588 EHCI_SITD_SET_CMASK(sb)); 2589 2590 td->sitd_bp[1] = htole32(temp); 2591 2592 td->sitd_mask = htole32(sitd_mask); 2593 2594 if (nframes == 0) { 2595 td->sitd_status = htole32 2596 (EHCI_SITD_IOC | 2597 EHCI_SITD_ACTIVE | 2598 EHCI_SITD_SET_LEN(*plen)); 2599 } else { 2600 td->sitd_status = htole32 2601 (EHCI_SITD_ACTIVE | 2602 EHCI_SITD_SET_LEN(*plen)); 2603 } 2604 usb2_pc_cpu_flush(td->page_cache); 2605 2606#if USB_DEBUG 2607 if (ehcidebug > 15) { 2608 DPRINTF("FS-TD %d\n", nframes); 2609 ehci_dump_sitd(td); 2610 } 2611#endif 2612 /* insert TD into schedule */ 2613 EHCI_APPEND_FS_TD(td, *pp_last); 2614 pp_last++; 2615 2616 plen++; 2617 fss++; 2618 td_last = td; 2619 td = td->obj_next; 2620 } 2621 2622 xfer->td_transfer_last = td_last; 2623 2624 /* update isoc_next */ 2625 xfer->pipe->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) & 2626 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2627 2628 return; 2629} 2630 2631static void 2632ehci_device_isoc_fs_start(struct usb2_xfer *xfer) 2633{ 2634 /* put transfer on interrupt queue */ 2635 ehci_transfer_intr_enqueue(xfer); 2636 return; 2637} 2638 2639struct usb2_pipe_methods ehci_device_isoc_fs_methods = 2640{ 2641 .open = ehci_device_isoc_fs_open, 2642 .close = ehci_device_isoc_fs_close, 2643 .enter = ehci_device_isoc_fs_enter, 2644 .start = ehci_device_isoc_fs_start, 2645 .enter_is_cancelable = 1, 2646 .start_is_cancelable = 1, 2647}; 2648 2649/*------------------------------------------------------------------------* 2650 * ehci high speed isochronous support 2651 *------------------------------------------------------------------------*/ 2652static void 2653ehci_device_isoc_hs_open(struct usb2_xfer *xfer) 2654{ 2655 ehci_itd_t *td; 2656 uint32_t temp; 2657 uint8_t ds; 2658 2659 /* initialize all TD's */ 2660 2661 for (ds = 0; ds != 2; ds++) { 2662 2663 for (td = xfer->td_start[ds]; td; td = td->obj_next) { 2664 2665 /* set TD inactive */ 2666 td->itd_status[0] = 0; 2667 td->itd_status[1] = 0; 2668 td->itd_status[2] = 0; 2669 td->itd_status[3] = 0; 2670 td->itd_status[4] = 0; 2671 td->itd_status[5] = 0; 2672 td->itd_status[6] = 0; 2673 td->itd_status[7] = 0; 2674 2675 /* set endpoint and address */ 2676 td->itd_bp[0] = htole32 2677 (EHCI_ITD_SET_ADDR(xfer->address) | 2678 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpoint))); 2679 2680 temp = 2681 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF); 2682 2683 /* set direction */ 2684 if (UE_GET_DIR(xfer->endpoint) == UE_DIR_IN) { 2685 temp |= EHCI_ITD_SET_DIR_IN; 2686 } 2687 /* set maximum packet size */ 2688 td->itd_bp[1] = htole32(temp); 2689 2690 /* set transfer multiplier */ 2691 td->itd_bp[2] = htole32(xfer->max_packet_count & 3); 2692 2693 usb2_pc_cpu_flush(td->page_cache); 2694 } 2695 } 2696 return; 2697} 2698 2699static void 2700ehci_device_isoc_hs_close(struct usb2_xfer *xfer) 2701{ 2702 ehci_device_done(xfer, USB_ERR_CANCELLED); 2703 return; 2704} 2705 2706static void 2707ehci_device_isoc_hs_enter(struct usb2_xfer *xfer) 2708{ 2709 struct usb2_page_search buf_res; 2710 ehci_softc_t *sc = xfer->usb2_sc; 2711 ehci_itd_t *td; 2712 ehci_itd_t *td_last = NULL; 2713 ehci_itd_t **pp_last; 2714 bus_size_t page_addr; 2715 uint32_t *plen; 2716 uint32_t status; 2717 uint32_t buf_offset; 2718 uint32_t nframes; 2719 uint32_t itd_offset[8 + 1]; 2720 uint8_t x; 2721 uint8_t td_no; 2722 uint8_t page_no; 2723 2724#if USB_DEBUG 2725 uint8_t once = 1; 2726 2727#endif 2728 2729 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 2730 xfer, xfer->pipe->isoc_next, xfer->nframes); 2731 2732 /* get the current frame index */ 2733 2734 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8; 2735 2736 /* 2737 * check if the frame index is within the window where the frames 2738 * will be inserted 2739 */ 2740 buf_offset = (nframes - xfer->pipe->isoc_next) & 2741 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2742 2743 if ((xfer->pipe->is_synced == 0) || 2744 (buf_offset < ((xfer->nframes + 7) / 8))) { 2745 /* 2746 * If there is data underflow or the pipe queue is empty we 2747 * schedule the transfer a few frames ahead of the current 2748 * frame position. Else two isochronous transfers might 2749 * overlap. 2750 */ 2751 xfer->pipe->isoc_next = (nframes + 3) & 2752 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2753 xfer->pipe->is_synced = 1; 2754 DPRINTFN(3, "start next=%d\n", xfer->pipe->isoc_next); 2755 } 2756 /* 2757 * compute how many milliseconds the insertion is ahead of the 2758 * current frame position: 2759 */ 2760 buf_offset = (xfer->pipe->isoc_next - nframes) & 2761 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2762 2763 /* 2764 * pre-compute when the isochronous transfer will be finished: 2765 */ 2766 xfer->isoc_time_complete = 2767 usb2_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset + 2768 ((xfer->nframes + 7) / 8); 2769 2770 /* get the real number of frames */ 2771 2772 nframes = xfer->nframes; 2773 2774 buf_offset = 0; 2775 td_no = 0; 2776 2777 plen = xfer->frlengths; 2778 2779 /* toggle the DMA set we are using */ 2780 xfer->flags_int.curr_dma_set ^= 1; 2781 2782 /* get next DMA set */ 2783 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2784 xfer->td_transfer_first = td; 2785 2786 pp_last = &sc->sc_isoc_hs_p_last[xfer->pipe->isoc_next]; 2787 2788 /* store starting position */ 2789 2790 xfer->qh_pos = xfer->pipe->isoc_next; 2791 2792 while (nframes--) { 2793 if (td == NULL) { 2794 panic("%s:%d: out of TD's\n", 2795 __FUNCTION__, __LINE__); 2796 } 2797 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) { 2798 pp_last = &sc->sc_isoc_hs_p_last[0]; 2799 } 2800 /* range check */ 2801 if (*plen > xfer->max_frame_size) { 2802#if USB_DEBUG 2803 if (once) { 2804 once = 0; 2805 printf("%s: frame length(%d) exceeds %d bytes " 2806 "(frame truncated)\n", 2807 __FUNCTION__, *plen, xfer->max_frame_size); 2808 } 2809#endif 2810 *plen = xfer->max_frame_size; 2811 } 2812 status = (EHCI_ITD_SET_LEN(*plen) | 2813 EHCI_ITD_ACTIVE | 2814 EHCI_ITD_SET_PG(0)); 2815 td->itd_status[td_no] = htole32(status); 2816 itd_offset[td_no] = buf_offset; 2817 buf_offset += *plen; 2818 plen++; 2819 td_no++; 2820 2821 if ((td_no == 8) || (nframes == 0)) { 2822 2823 /* the rest of the transfers are not active, if any */ 2824 for (x = td_no; x != 8; x++) { 2825 td->itd_status[x] = 0; /* not active */ 2826 } 2827 2828 /* check if there is any data to be transferred */ 2829 if (itd_offset[0] != buf_offset) { 2830 page_no = 0; 2831 itd_offset[td_no] = buf_offset; 2832 2833 /* get first page offset */ 2834 usb2_get_page(xfer->frbuffers, itd_offset[0], &buf_res); 2835 /* get page address */ 2836 page_addr = buf_res.physaddr & ~0xFFF; 2837 /* update page address */ 2838 td->itd_bp[0] &= htole32(0xFFF); 2839 td->itd_bp[0] |= htole32(page_addr); 2840 2841 for (x = 0; x != td_no; x++) { 2842 /* set page number and page offset */ 2843 status = (EHCI_ITD_SET_PG(page_no) | 2844 (buf_res.physaddr & 0xFFF)); 2845 td->itd_status[x] |= htole32(status); 2846 2847 /* get next page offset */ 2848 if (itd_offset[x + 1] == buf_offset) { 2849 /* 2850 * We subtract one so that 2851 * we don't go off the last 2852 * page! 2853 */ 2854 usb2_get_page(xfer->frbuffers, buf_offset - 1, &buf_res); 2855 } else { 2856 usb2_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res); 2857 } 2858 2859 /* check if we need a new page */ 2860 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) { 2861 /* new page needed */ 2862 page_addr = buf_res.physaddr & ~0xFFF; 2863 if (page_no == 6) { 2864 panic("%s: too many pages\n", __FUNCTION__); 2865 } 2866 page_no++; 2867 /* update page address */ 2868 td->itd_bp[page_no] &= htole32(0xFFF); 2869 td->itd_bp[page_no] |= htole32(page_addr); 2870 } 2871 } 2872 } 2873 /* set IOC bit if we are complete */ 2874 if (nframes == 0) { 2875 td->itd_status[7] |= htole32(EHCI_ITD_IOC); 2876 } 2877 usb2_pc_cpu_flush(td->page_cache); 2878#if USB_DEBUG 2879 if (ehcidebug > 15) { 2880 DPRINTF("HS-TD %d\n", nframes); 2881 ehci_dump_itd(td); 2882 } 2883#endif 2884 /* insert TD into schedule */ 2885 EHCI_APPEND_HS_TD(td, *pp_last); 2886 pp_last++; 2887 2888 td_no = 0; 2889 td_last = td; 2890 td = td->obj_next; 2891 } 2892 } 2893 2894 xfer->td_transfer_last = td_last; 2895 2896 /* update isoc_next */ 2897 xfer->pipe->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) & 2898 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1); 2899 2900 return; 2901} 2902 2903static void 2904ehci_device_isoc_hs_start(struct usb2_xfer *xfer) 2905{ 2906 /* put transfer on interrupt queue */ 2907 ehci_transfer_intr_enqueue(xfer); 2908 return; 2909} 2910 2911struct usb2_pipe_methods ehci_device_isoc_hs_methods = 2912{ 2913 .open = ehci_device_isoc_hs_open, 2914 .close = ehci_device_isoc_hs_close, 2915 .enter = ehci_device_isoc_hs_enter, 2916 .start = ehci_device_isoc_hs_start, 2917 .enter_is_cancelable = 1, 2918 .start_is_cancelable = 1, 2919}; 2920 2921/*------------------------------------------------------------------------* 2922 * ehci root control support 2923 *------------------------------------------------------------------------* 2924 * simulate a hardware hub by handling 2925 * all the necessary requests 2926 *------------------------------------------------------------------------*/ 2927 2928static void 2929ehci_root_ctrl_open(struct usb2_xfer *xfer) 2930{ 2931 return; 2932} 2933 2934static void 2935ehci_root_ctrl_close(struct usb2_xfer *xfer) 2936{ 2937 ehci_softc_t *sc = xfer->usb2_sc; 2938 2939 if (sc->sc_root_ctrl.xfer == xfer) { 2940 sc->sc_root_ctrl.xfer = NULL; 2941 } 2942 ehci_device_done(xfer, USB_ERR_CANCELLED); 2943 return; 2944} 2945 2946/* data structures and routines 2947 * to emulate the root hub: 2948 */ 2949 2950static const 2951struct usb2_device_descriptor ehci_devd = 2952{ 2953 sizeof(struct usb2_device_descriptor), 2954 UDESC_DEVICE, /* type */ 2955 {0x00, 0x02}, /* USB version */ 2956 UDCLASS_HUB, /* class */ 2957 UDSUBCLASS_HUB, /* subclass */ 2958 UDPROTO_HSHUBSTT, /* protocol */ 2959 64, /* max packet */ 2960 {0}, {0}, {0x00, 0x01}, /* device id */ 2961 1, 2, 0, /* string indicies */ 2962 1 /* # of configurations */ 2963}; 2964 2965static const 2966struct usb2_device_qualifier ehci_odevd = 2967{ 2968 sizeof(struct usb2_device_qualifier), 2969 UDESC_DEVICE_QUALIFIER, /* type */ 2970 {0x00, 0x02}, /* USB version */ 2971 UDCLASS_HUB, /* class */ 2972 UDSUBCLASS_HUB, /* subclass */ 2973 UDPROTO_FSHUB, /* protocol */ 2974 0, /* max packet */ 2975 0, /* # of configurations */ 2976 0 2977}; 2978 2979static const struct ehci_config_desc ehci_confd = { 2980 .confd = { 2981 .bLength = sizeof(struct usb2_config_descriptor), 2982 .bDescriptorType = UDESC_CONFIG, 2983 .wTotalLength[0] = sizeof(ehci_confd), 2984 .bNumInterface = 1, 2985 .bConfigurationValue = 1, 2986 .iConfiguration = 0, 2987 .bmAttributes = UC_SELF_POWERED, 2988 .bMaxPower = 0 /* max power */ 2989 }, 2990 2991 .ifcd = { 2992 .bLength = sizeof(struct usb2_interface_descriptor), 2993 .bDescriptorType = UDESC_INTERFACE, 2994 .bNumEndpoints = 1, 2995 .bInterfaceClass = UICLASS_HUB, 2996 .bInterfaceSubClass = UISUBCLASS_HUB, 2997 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 2998 0 2999 }, 3000 3001 .endpd = { 3002 .bLength = sizeof(struct usb2_endpoint_descriptor), 3003 .bDescriptorType = UDESC_ENDPOINT, 3004 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT, 3005 .bmAttributes = UE_INTERRUPT, 3006 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */ 3007 .bInterval = 255, 3008 }, 3009}; 3010 3011static const 3012struct usb2_hub_descriptor ehci_hubd = 3013{ 3014 0, /* dynamic length */ 3015 UDESC_HUB, 3016 0, 3017 {0, 0}, 3018 0, 3019 0, 3020 {0}, 3021}; 3022 3023static void 3024ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed) 3025{ 3026 uint32_t port; 3027 uint32_t v; 3028 3029 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed); 3030 3031 port = EHCI_PORTSC(index); 3032 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3033 EOWRITE4(sc, port, v | EHCI_PS_PO); 3034} 3035 3036static void 3037ehci_root_ctrl_enter(struct usb2_xfer *xfer) 3038{ 3039 return; 3040} 3041 3042static void 3043ehci_root_ctrl_start(struct usb2_xfer *xfer) 3044{ 3045 ehci_softc_t *sc = xfer->usb2_sc; 3046 3047 DPRINTF("\n"); 3048 3049 sc->sc_root_ctrl.xfer = xfer; 3050 3051 usb2_config_td_queue_command 3052 (&sc->sc_config_td, NULL, &ehci_root_ctrl_task, 0, 0); 3053 3054 return; 3055} 3056 3057static void 3058ehci_root_ctrl_task(struct ehci_softc *sc, 3059 struct usb2_config_td_cc *cc, uint16_t refcount) 3060{ 3061 ehci_root_ctrl_poll(sc); 3062 return; 3063} 3064 3065static void 3066ehci_root_ctrl_done(struct usb2_xfer *xfer, 3067 struct usb2_sw_transfer *std) 3068{ 3069 struct ehci_softc *sc = xfer->usb2_sc; 3070 char *ptr; 3071 uint32_t port; 3072 uint32_t v; 3073 uint16_t i; 3074 uint16_t value; 3075 uint16_t index; 3076 uint8_t l; 3077 uint8_t use_polling; 3078 3079 mtx_assert(&sc->sc_bus.mtx, MA_OWNED); 3080 3081 if (std->state != USB_SW_TR_SETUP) { 3082 if (std->state == USB_SW_TR_PRE_CALLBACK) { 3083 /* transfer transferred */ 3084 ehci_device_done(xfer, std->err); 3085 } 3086 goto done; 3087 } 3088 /* buffer reset */ 3089 std->ptr = sc->sc_hub_desc.temp; 3090 std->len = 0; 3091 3092 value = UGETW(std->req.wValue); 3093 index = UGETW(std->req.wIndex); 3094 3095 use_polling = mtx_owned(xfer->priv_mtx) ? 1 : 0; 3096 3097 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3098 "wValue=0x%04x wIndex=0x%04x\n", 3099 std->req.bmRequestType, std->req.bRequest, 3100 UGETW(std->req.wLength), value, index); 3101 3102#define C(x,y) ((x) | ((y) << 8)) 3103 switch (C(std->req.bRequest, std->req.bmRequestType)) { 3104 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3105 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3106 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3107 /* 3108 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3109 * for the integrated root hub. 3110 */ 3111 break; 3112 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3113 std->len = 1; 3114 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3115 break; 3116 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3117 switch (value >> 8) { 3118 case UDESC_DEVICE: 3119 if ((value & 0xff) != 0) { 3120 std->err = USB_ERR_IOERROR; 3121 goto done; 3122 } 3123 std->len = sizeof(ehci_devd); 3124 sc->sc_hub_desc.devd = ehci_devd; 3125 break; 3126 /* 3127 * We can't really operate at another speed, 3128 * but the specification says we need this 3129 * descriptor: 3130 */ 3131 case UDESC_DEVICE_QUALIFIER: 3132 if ((value & 0xff) != 0) { 3133 std->err = USB_ERR_IOERROR; 3134 goto done; 3135 } 3136 std->len = sizeof(ehci_odevd); 3137 sc->sc_hub_desc.odevd = ehci_odevd; 3138 break; 3139 3140 case UDESC_CONFIG: 3141 if ((value & 0xff) != 0) { 3142 std->err = USB_ERR_IOERROR; 3143 goto done; 3144 } 3145 std->len = sizeof(ehci_confd); 3146 std->ptr = USB_ADD_BYTES(&ehci_confd, 0); 3147 break; 3148 3149 case UDESC_STRING: 3150 switch (value & 0xff) { 3151 case 0: /* Language table */ 3152 ptr = "\001"; 3153 break; 3154 3155 case 1: /* Vendor */ 3156 ptr = sc->sc_vendor; 3157 break; 3158 3159 case 2: /* Product */ 3160 ptr = "EHCI root HUB"; 3161 break; 3162 3163 default: 3164 ptr = ""; 3165 break; 3166 } 3167 3168 std->len = usb2_make_str_desc 3169 (sc->sc_hub_desc.temp, 3170 sizeof(sc->sc_hub_desc.temp), 3171 ptr); 3172 break; 3173 default: 3174 std->err = USB_ERR_IOERROR; 3175 goto done; 3176 } 3177 break; 3178 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3179 std->len = 1; 3180 sc->sc_hub_desc.temp[0] = 0; 3181 break; 3182 case C(UR_GET_STATUS, UT_READ_DEVICE): 3183 std->len = 2; 3184 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3185 break; 3186 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3187 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3188 std->len = 2; 3189 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3190 break; 3191 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3192 if (value >= USB_MAX_DEVICES) { 3193 std->err = USB_ERR_IOERROR; 3194 goto done; 3195 } 3196 sc->sc_addr = value; 3197 break; 3198 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3199 if ((value != 0) && (value != 1)) { 3200 std->err = USB_ERR_IOERROR; 3201 goto done; 3202 } 3203 sc->sc_conf = value; 3204 break; 3205 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3206 break; 3207 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3208 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3209 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3210 std->err = USB_ERR_IOERROR; 3211 goto done; 3212 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3213 break; 3214 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3215 break; 3216 /* Hub requests */ 3217 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3218 break; 3219 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3220 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3221 3222 if ((index < 1) || 3223 (index > sc->sc_noport)) { 3224 std->err = USB_ERR_IOERROR; 3225 goto done; 3226 } 3227 port = EHCI_PORTSC(index); 3228 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3229 switch (value) { 3230 case UHF_PORT_ENABLE: 3231 EOWRITE4(sc, port, v & ~EHCI_PS_PE); 3232 break; 3233 case UHF_PORT_SUSPEND: 3234 EOWRITE4(sc, port, v & ~EHCI_PS_SUSP); 3235 break; 3236 case UHF_PORT_POWER: 3237 EOWRITE4(sc, port, v & ~EHCI_PS_PP); 3238 break; 3239 case UHF_PORT_TEST: 3240 DPRINTFN(3, "clear port test " 3241 "%d\n", index); 3242 break; 3243 case UHF_PORT_INDICATOR: 3244 DPRINTFN(3, "clear port ind " 3245 "%d\n", index); 3246 EOWRITE4(sc, port, v & ~EHCI_PS_PIC); 3247 break; 3248 case UHF_C_PORT_CONNECTION: 3249 EOWRITE4(sc, port, v | EHCI_PS_CSC); 3250 break; 3251 case UHF_C_PORT_ENABLE: 3252 EOWRITE4(sc, port, v | EHCI_PS_PEC); 3253 break; 3254 case UHF_C_PORT_SUSPEND: 3255 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3256 break; 3257 case UHF_C_PORT_OVER_CURRENT: 3258 EOWRITE4(sc, port, v | EHCI_PS_OCC); 3259 break; 3260 case UHF_C_PORT_RESET: 3261 sc->sc_isreset = 0; 3262 break; 3263 default: 3264 std->err = USB_ERR_IOERROR; 3265 goto done; 3266 } 3267 break; 3268 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3269 if ((value & 0xff) != 0) { 3270 std->err = USB_ERR_IOERROR; 3271 goto done; 3272 } 3273 v = EOREAD4(sc, EHCI_HCSPARAMS); 3274 3275 sc->sc_hub_desc.hubd = ehci_hubd; 3276 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3277 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, 3278 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) | 3279 (EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) ? 3280 UHD_PORT_IND : 0)); 3281 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 3282 for (l = 0; l < sc->sc_noport; l++) { 3283 /* XXX can't find out? */ 3284 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] &= ~(1 << (l % 8)); 3285 } 3286 sc->sc_hub_desc.hubd.bDescLength = 3287 8 + ((sc->sc_noport + 7) / 8); 3288 std->len = sc->sc_hub_desc.hubd.bDescLength; 3289 break; 3290 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3291 std->len = 16; 3292 bzero(sc->sc_hub_desc.temp, 16); 3293 break; 3294 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3295 DPRINTFN(9, "get port status i=%d\n", 3296 index); 3297 if ((index < 1) || 3298 (index > sc->sc_noport)) { 3299 std->err = USB_ERR_IOERROR; 3300 goto done; 3301 } 3302 v = EOREAD4(sc, EHCI_PORTSC(index)); 3303 DPRINTFN(9, "port status=0x%04x\n", v); 3304 i = UPS_HIGH_SPEED; 3305 if (v & EHCI_PS_CS) 3306 i |= UPS_CURRENT_CONNECT_STATUS; 3307 if (v & EHCI_PS_PE) 3308 i |= UPS_PORT_ENABLED; 3309 if (v & EHCI_PS_SUSP) 3310 i |= UPS_SUSPEND; 3311 if (v & EHCI_PS_OCA) 3312 i |= UPS_OVERCURRENT_INDICATOR; 3313 if (v & EHCI_PS_PR) 3314 i |= UPS_RESET; 3315 if (v & EHCI_PS_PP) 3316 i |= UPS_PORT_POWER; 3317 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3318 i = 0; 3319 if (v & EHCI_PS_CSC) 3320 i |= UPS_C_CONNECT_STATUS; 3321 if (v & EHCI_PS_PEC) 3322 i |= UPS_C_PORT_ENABLED; 3323 if (v & EHCI_PS_OCC) 3324 i |= UPS_C_OVERCURRENT_INDICATOR; 3325 if (sc->sc_isreset) 3326 i |= UPS_C_PORT_RESET; 3327 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3328 std->len = sizeof(sc->sc_hub_desc.ps); 3329 break; 3330 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3331 std->err = USB_ERR_IOERROR; 3332 goto done; 3333 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3334 break; 3335 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3336 if ((index < 1) || 3337 (index > sc->sc_noport)) { 3338 std->err = USB_ERR_IOERROR; 3339 goto done; 3340 } 3341 port = EHCI_PORTSC(index); 3342 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR; 3343 switch (value) { 3344 case UHF_PORT_ENABLE: 3345 EOWRITE4(sc, port, v | EHCI_PS_PE); 3346 break; 3347 case UHF_PORT_SUSPEND: 3348 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 3349 break; 3350 case UHF_PORT_RESET: 3351 DPRINTFN(6, "reset port %d\n", index); 3352#if USB_DEBUG 3353 if (ehcinohighspeed) { 3354 /* 3355 * Connect USB device to companion 3356 * controller. 3357 */ 3358 ehci_disown(sc, index, 1); 3359 break; 3360 } 3361#endif 3362 if (EHCI_PS_IS_LOWSPEED(v)) { 3363 /* Low speed device, give up ownership. */ 3364 ehci_disown(sc, index, 1); 3365 break; 3366 } 3367 /* Start reset sequence. */ 3368 v &= ~(EHCI_PS_PE | EHCI_PS_PR); 3369 EOWRITE4(sc, port, v | EHCI_PS_PR); 3370 3371 if (use_polling) { 3372 /* polling */ 3373 DELAY(USB_PORT_ROOT_RESET_DELAY * 1000); 3374 } else { 3375 /* Wait for reset to complete. */ 3376 usb2_pause_mtx(&sc->sc_bus.mtx, 3377 USB_PORT_ROOT_RESET_DELAY); 3378 } 3379 3380 /* Terminate reset sequence. */ 3381 EOWRITE4(sc, port, v); 3382 3383 if (use_polling) { 3384 /* polling */ 3385 DELAY(EHCI_PORT_RESET_COMPLETE * 1000); 3386 } else { 3387 /* Wait for HC to complete reset. */ 3388 usb2_pause_mtx(&sc->sc_bus.mtx, 3389 EHCI_PORT_RESET_COMPLETE); 3390 } 3391 3392 v = EOREAD4(sc, port); 3393 DPRINTF("ehci after reset, status=0x%08x\n", v); 3394 if (v & EHCI_PS_PR) { 3395 device_printf(sc->sc_bus.bdev, 3396 "port reset timeout\n"); 3397 std->err = USB_ERR_TIMEOUT; 3398 goto done; 3399 } 3400 if (!(v & EHCI_PS_PE)) { 3401 /* 3402 * Not a high speed device, give up 3403 * ownership. 3404 */ 3405 ehci_disown(sc, index, 0); 3406 break; 3407 } 3408 sc->sc_isreset = 1; 3409 DPRINTF("ehci port %d reset, status = 0x%08x\n", 3410 index, v); 3411 break; 3412 3413 case UHF_PORT_POWER: 3414 DPRINTFN(3, "set port power %d\n", index); 3415 EOWRITE4(sc, port, v | EHCI_PS_PP); 3416 break; 3417 3418 case UHF_PORT_TEST: 3419 DPRINTFN(3, "set port test %d\n", index); 3420 break; 3421 3422 case UHF_PORT_INDICATOR: 3423 DPRINTFN(3, "set port ind %d\n", index); 3424 EOWRITE4(sc, port, v | EHCI_PS_PIC); 3425 break; 3426 3427 default: 3428 std->err = USB_ERR_IOERROR; 3429 goto done; 3430 } 3431 break; 3432 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3433 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3434 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3435 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3436 break; 3437 default: 3438 std->err = USB_ERR_IOERROR; 3439 goto done; 3440 } 3441done: 3442 return; 3443} 3444 3445static void 3446ehci_root_ctrl_poll(struct ehci_softc *sc) 3447{ 3448 usb2_sw_transfer(&sc->sc_root_ctrl, 3449 &ehci_root_ctrl_done); 3450 return; 3451} 3452 3453struct usb2_pipe_methods ehci_root_ctrl_methods = 3454{ 3455 .open = ehci_root_ctrl_open, 3456 .close = ehci_root_ctrl_close, 3457 .enter = ehci_root_ctrl_enter, 3458 .start = ehci_root_ctrl_start, 3459 .enter_is_cancelable = 1, 3460 .start_is_cancelable = 0, 3461}; 3462 3463/*------------------------------------------------------------------------* 3464 * ehci root interrupt support 3465 *------------------------------------------------------------------------*/ 3466static void 3467ehci_root_intr_open(struct usb2_xfer *xfer) 3468{ 3469 return; 3470} 3471 3472static void 3473ehci_root_intr_close(struct usb2_xfer *xfer) 3474{ 3475 ehci_softc_t *sc = xfer->usb2_sc; 3476 3477 if (sc->sc_root_intr.xfer == xfer) { 3478 sc->sc_root_intr.xfer = NULL; 3479 } 3480 ehci_device_done(xfer, USB_ERR_CANCELLED); 3481 return; 3482} 3483 3484static void 3485ehci_root_intr_enter(struct usb2_xfer *xfer) 3486{ 3487 return; 3488} 3489 3490static void 3491ehci_root_intr_start(struct usb2_xfer *xfer) 3492{ 3493 ehci_softc_t *sc = xfer->usb2_sc; 3494 3495 sc->sc_root_intr.xfer = xfer; 3496 return; 3497} 3498 3499struct usb2_pipe_methods ehci_root_intr_methods = 3500{ 3501 .open = ehci_root_intr_open, 3502 .close = ehci_root_intr_close, 3503 .enter = ehci_root_intr_enter, 3504 .start = ehci_root_intr_start, 3505 .enter_is_cancelable = 1, 3506 .start_is_cancelable = 1, 3507}; 3508 3509static void 3510ehci_xfer_setup(struct usb2_setup_params *parm) 3511{ 3512 struct usb2_page_search page_info; 3513 struct usb2_page_cache *pc; 3514 ehci_softc_t *sc; 3515 struct usb2_xfer *xfer; 3516 void *last_obj; 3517 uint32_t nqtd; 3518 uint32_t nqh; 3519 uint32_t nsitd; 3520 uint32_t nitd; 3521 uint32_t n; 3522 3523 sc = EHCI_BUS2SC(parm->udev->bus); 3524 xfer = parm->curr_xfer; 3525 3526 nqtd = 0; 3527 nqh = 0; 3528 nsitd = 0; 3529 nitd = 0; 3530 3531 /* 3532 * setup xfer 3533 */ 3534 xfer->usb2_sc = sc; 3535 3536 /* 3537 * compute maximum number of some structures 3538 */ 3539 if (parm->methods == &ehci_device_ctrl_methods) { 3540 3541 /* 3542 * The proof for the "nqtd" formula is illustrated like 3543 * this: 3544 * 3545 * +------------------------------------+ 3546 * | | 3547 * | |remainder -> | 3548 * | +-----+---+ | 3549 * | | xxx | x | frm 0 | 3550 * | +-----+---++ | 3551 * | | xxx | xx | frm 1 | 3552 * | +-----+----+ | 3553 * | ... | 3554 * +------------------------------------+ 3555 * 3556 * "xxx" means a completely full USB transfer descriptor 3557 * 3558 * "x" and "xx" means a short USB packet 3559 * 3560 * For the remainder of an USB transfer modulo 3561 * "max_data_length" we need two USB transfer descriptors. 3562 * One to transfer the remaining data and one to finalise 3563 * with a zero length packet in case the "force_short_xfer" 3564 * flag is set. We only need two USB transfer descriptors in 3565 * the case where the transfer length of the first one is a 3566 * factor of "max_frame_size". The rest of the needed USB 3567 * transfer descriptors is given by the buffer size divided 3568 * by the maximum data payload. 3569 */ 3570 parm->hc_max_packet_size = 0x400; 3571 parm->hc_max_packet_count = 1; 3572 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3573 xfer->flags_int.bdma_enable = 1; 3574 3575 usb2_transfer_setup_sub(parm); 3576 3577 nqh = 1; 3578 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */ 3579 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 3580 3581 } else if (parm->methods == &ehci_device_bulk_methods) { 3582 3583 parm->hc_max_packet_size = 0x400; 3584 parm->hc_max_packet_count = 1; 3585 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3586 xfer->flags_int.bdma_enable = 1; 3587 3588 usb2_transfer_setup_sub(parm); 3589 3590 nqh = 1; 3591 nqtd = ((2 * xfer->nframes) 3592 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 3593 3594 } else if (parm->methods == &ehci_device_intr_methods) { 3595 3596 if (parm->speed == USB_SPEED_HIGH) { 3597 parm->hc_max_packet_size = 0x400; 3598 parm->hc_max_packet_count = 3; 3599 } else if (parm->speed == USB_SPEED_FULL) { 3600 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME; 3601 parm->hc_max_packet_count = 1; 3602 } else { 3603 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8; 3604 parm->hc_max_packet_count = 1; 3605 } 3606 3607 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX; 3608 xfer->flags_int.bdma_enable = 1; 3609 3610 usb2_transfer_setup_sub(parm); 3611 3612 nqh = 1; 3613 nqtd = ((2 * xfer->nframes) 3614 + (xfer->max_data_length / xfer->max_usb2_frame_size)); 3615 3616 } else if (parm->methods == &ehci_device_isoc_fs_methods) { 3617 3618 parm->hc_max_packet_size = 0x3FF; 3619 parm->hc_max_packet_count = 1; 3620 parm->hc_max_frame_size = 0x3FF; 3621 xfer->flags_int.bdma_enable = 1; 3622 3623 usb2_transfer_setup_sub(parm); 3624 3625 nsitd = xfer->nframes; 3626 3627 } else if (parm->methods == &ehci_device_isoc_hs_methods) { 3628 3629 parm->hc_max_packet_size = 0x400; 3630 parm->hc_max_packet_count = 3; 3631 parm->hc_max_frame_size = 0xC00; 3632 xfer->flags_int.bdma_enable = 1; 3633 3634 usb2_transfer_setup_sub(parm); 3635 3636 nitd = (xfer->nframes + 7) / 8; 3637 3638 } else { 3639 3640 parm->hc_max_packet_size = 0x400; 3641 parm->hc_max_packet_count = 1; 3642 parm->hc_max_frame_size = 0x400; 3643 3644 usb2_transfer_setup_sub(parm); 3645 } 3646 3647alloc_dma_set: 3648 3649 if (parm->err) { 3650 return; 3651 } 3652 /* 3653 * Allocate queue heads and transfer descriptors 3654 */ 3655 last_obj = NULL; 3656 3657 if (usb2_transfer_setup_sub_malloc( 3658 parm, &pc, sizeof(ehci_itd_t), 3659 EHCI_ITD_ALIGN, nitd)) { 3660 parm->err = USB_ERR_NOMEM; 3661 return; 3662 } 3663 if (parm->buf) { 3664 for (n = 0; n != nitd; n++) { 3665 ehci_itd_t *td; 3666 3667 usb2_get_page(pc + n, 0, &page_info); 3668 3669 td = page_info.buffer; 3670 3671 /* init TD */ 3672 td->itd_self = htole32(page_info.physaddr | EHCI_LINK_ITD); 3673 td->obj_next = last_obj; 3674 td->page_cache = pc + n; 3675 3676 last_obj = td; 3677 3678 usb2_pc_cpu_flush(pc + n); 3679 } 3680 } 3681 if (usb2_transfer_setup_sub_malloc( 3682 parm, &pc, sizeof(ehci_sitd_t), 3683 EHCI_SITD_ALIGN, nsitd)) { 3684 parm->err = USB_ERR_NOMEM; 3685 return; 3686 } 3687 if (parm->buf) { 3688 for (n = 0; n != nsitd; n++) { 3689 ehci_sitd_t *td; 3690 3691 usb2_get_page(pc + n, 0, &page_info); 3692 3693 td = page_info.buffer; 3694 3695 /* init TD */ 3696 td->sitd_self = htole32(page_info.physaddr | EHCI_LINK_SITD); 3697 td->obj_next = last_obj; 3698 td->page_cache = pc + n; 3699 3700 last_obj = td; 3701 3702 usb2_pc_cpu_flush(pc + n); 3703 } 3704 } 3705 if (usb2_transfer_setup_sub_malloc( 3706 parm, &pc, sizeof(ehci_qtd_t), 3707 EHCI_QTD_ALIGN, nqtd)) { 3708 parm->err = USB_ERR_NOMEM; 3709 return; 3710 } 3711 if (parm->buf) { 3712 for (n = 0; n != nqtd; n++) { 3713 ehci_qtd_t *qtd; 3714 3715 usb2_get_page(pc + n, 0, &page_info); 3716 3717 qtd = page_info.buffer; 3718 3719 /* init TD */ 3720 qtd->qtd_self = htole32(page_info.physaddr); 3721 qtd->obj_next = last_obj; 3722 qtd->page_cache = pc + n; 3723 3724 last_obj = qtd; 3725 3726 usb2_pc_cpu_flush(pc + n); 3727 } 3728 } 3729 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3730 3731 last_obj = NULL; 3732 3733 if (usb2_transfer_setup_sub_malloc( 3734 parm, &pc, sizeof(ehci_qh_t), 3735 EHCI_QH_ALIGN, nqh)) { 3736 parm->err = USB_ERR_NOMEM; 3737 return; 3738 } 3739 if (parm->buf) { 3740 for (n = 0; n != nqh; n++) { 3741 ehci_qh_t *qh; 3742 3743 usb2_get_page(pc + n, 0, &page_info); 3744 3745 qh = page_info.buffer; 3746 3747 /* init QH */ 3748 qh->qh_self = htole32(page_info.physaddr | EHCI_LINK_QH); 3749 qh->obj_next = last_obj; 3750 qh->page_cache = pc + n; 3751 3752 last_obj = qh; 3753 3754 usb2_pc_cpu_flush(pc + n); 3755 } 3756 } 3757 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj; 3758 3759 if (!xfer->flags_int.curr_dma_set) { 3760 xfer->flags_int.curr_dma_set = 1; 3761 goto alloc_dma_set; 3762 } 3763 return; 3764} 3765 3766static void 3767ehci_xfer_unsetup(struct usb2_xfer *xfer) 3768{ 3769 return; 3770} 3771 3772static void 3773ehci_pipe_init(struct usb2_device *udev, struct usb2_endpoint_descriptor *edesc, 3774 struct usb2_pipe *pipe) 3775{ 3776 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus); 3777 3778 DPRINTFN(2, "pipe=%p, addr=%d, endpt=%d, mode=%d (%d)\n", 3779 pipe, udev->address, 3780 edesc->bEndpointAddress, udev->flags.usb2_mode, 3781 sc->sc_addr); 3782 3783 if (udev->flags.usb2_mode != USB_MODE_HOST) { 3784 /* not supported */ 3785 return; 3786 } 3787 if (udev->device_index == sc->sc_addr) { 3788 switch (edesc->bEndpointAddress) { 3789 case USB_CONTROL_ENDPOINT: 3790 pipe->methods = &ehci_root_ctrl_methods; 3791 break; 3792 case UE_DIR_IN | EHCI_INTR_ENDPT: 3793 pipe->methods = &ehci_root_intr_methods; 3794 break; 3795 default: 3796 /* do nothing */ 3797 break; 3798 } 3799 } else { 3800 if ((udev->speed != USB_SPEED_HIGH) && 3801 ((udev->hs_hub_addr == 0) || 3802 (udev->hs_port_no == 0) || 3803 (udev->bus->devices[udev->hs_hub_addr] == NULL) || 3804 (udev->bus->devices[udev->hs_hub_addr]->hub == NULL))) { 3805 /* We need a transaction translator */ 3806 goto done; 3807 } 3808 switch (edesc->bmAttributes & UE_XFERTYPE) { 3809 case UE_CONTROL: 3810 pipe->methods = &ehci_device_ctrl_methods; 3811 break; 3812 case UE_INTERRUPT: 3813 pipe->methods = &ehci_device_intr_methods; 3814 break; 3815 case UE_ISOCHRONOUS: 3816 if (udev->speed == USB_SPEED_HIGH) { 3817 pipe->methods = &ehci_device_isoc_hs_methods; 3818 } else if (udev->speed == USB_SPEED_FULL) { 3819 pipe->methods = &ehci_device_isoc_fs_methods; 3820 } 3821 break; 3822 case UE_BULK: 3823 if (udev->speed != USB_SPEED_LOW) { 3824 pipe->methods = &ehci_device_bulk_methods; 3825 } 3826 break; 3827 default: 3828 /* do nothing */ 3829 break; 3830 } 3831 } 3832done: 3833 return; 3834} 3835 3836static void 3837ehci_get_dma_delay(struct usb2_bus *bus, uint32_t *pus) 3838{ 3839 /* 3840 * Wait until the hardware has finished any possible use of 3841 * the transfer descriptor(s) and QH 3842 */ 3843 *pus = (188); /* microseconds */ 3844 return; 3845} 3846 3847struct usb2_bus_methods ehci_bus_methods = 3848{ 3849 .pipe_init = ehci_pipe_init, 3850 .xfer_setup = ehci_xfer_setup, 3851 .xfer_unsetup = ehci_xfer_unsetup, 3852 .do_poll = ehci_do_poll, 3853 .get_dma_delay = ehci_get_dma_delay, 3854}; 3855