dwc_otg.h revision 267120
1/* $FreeBSD: head/sys/dev/usb/controller/dwc_otg.h 267120 2014-06-05 18:17:40Z hselasky $ */ 2/*- 3 * Copyright (c) 2012 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#ifndef _DWC_OTG_H_ 28#define _DWC_OTG_H_ 29 30#define DWC_OTG_MAX_DEVICES MIN(USB_MAX_DEVICES, 32) 31#define DWC_OTG_FRAME_MASK 0x7FF 32#define DWC_OTG_MAX_TXP 4 33#define DWC_OTG_MAX_TXN (0x200 * DWC_OTG_MAX_TXP) 34#define DWC_OTG_MAX_CHANNELS 16 35#define DWC_OTG_MAX_ENDPOINTS 16 36#define DWC_OTG_HOST_TIMER_RATE 10 /* ms */ 37#define DWC_OTG_TT_SLOT_MAX 8 38#define DWC_OTG_SLOT_IDLE_MAX 4 39#define DWC_OTG_SLOT_IDLE_MIN 2 40#define DWC_OTG_NAK_MAX 8 /* 1 ms */ 41 42#define DWC_OTG_READ_4(sc, reg) \ 43 bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg) 44 45#define DWC_OTG_WRITE_4(sc, reg, data) \ 46 bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data) 47 48struct dwc_otg_td; 49struct dwc_otg_softc; 50 51typedef uint8_t (dwc_otg_cmd_t)(struct dwc_otg_softc *sc, struct dwc_otg_td *td); 52 53struct dwc_otg_td { 54 struct dwc_otg_td *obj_next; 55 dwc_otg_cmd_t *func; 56 struct usb_page_cache *pc; 57 uint32_t tx_bytes; 58 uint32_t offset; 59 uint32_t remainder; 60 uint32_t hcchar; /* HOST CFG */ 61 uint32_t hcsplt; /* HOST CFG */ 62 uint16_t max_packet_size; /* packet_size */ 63 uint16_t npkt; 64 uint8_t max_packet_count; /* packet_count */ 65 uint8_t errcnt; 66 uint8_t tmr_res; 67 uint8_t tmr_val; 68 uint8_t did_nak; /* NAK counter */ 69 uint8_t ep_no; 70 uint8_t ep_type; 71 uint8_t channel; 72 uint8_t tt_index; /* TT data */ 73 uint8_t tt_start_slot; /* TT data */ 74 uint8_t tt_complete_slot; /* TT data */ 75 uint8_t tt_xactpos; /* TT data */ 76 uint8_t state; 77#define DWC_CHAN_ST_START 0 78#define DWC_CHAN_ST_WAIT_ANE 1 79#define DWC_CHAN_ST_WAIT_S_ANE 2 80#define DWC_CHAN_ST_WAIT_C_ANE 3 81#define DWC_CHAN_ST_WAIT_C_PKT 4 82#define DWC_CHAN_ST_TX_PKT_ISOC 5 83#define DWC_CHAN_ST_TX_WAIT_ISOC 6 84 uint8_t error_any:1; 85 uint8_t error_stall:1; 86 uint8_t alt_next:1; 87 uint8_t short_pkt:1; 88 uint8_t did_stall:1; 89 uint8_t toggle:1; 90 uint8_t set_toggle:1; 91 uint8_t got_short:1; 92 uint8_t tt_scheduled:1; 93}; 94 95struct dwc_otg_tt_info { 96 uint16_t bytes_used; 97 uint8_t slot_index; 98 uint8_t dummy; 99}; 100 101struct dwc_otg_std_temp { 102 dwc_otg_cmd_t *func; 103 struct usb_page_cache *pc; 104 struct dwc_otg_td *td; 105 struct dwc_otg_td *td_next; 106 uint32_t len; 107 uint32_t offset; 108 uint16_t max_frame_size; 109 uint8_t short_pkt; 110 111 /* 112 * short_pkt = 0: transfer should be short terminated 113 * short_pkt = 1: transfer should not be short terminated 114 */ 115 uint8_t setup_alt_next; 116 uint8_t did_stall; 117 uint8_t bulk_or_control; 118}; 119 120struct dwc_otg_config_desc { 121 struct usb_config_descriptor confd; 122 struct usb_interface_descriptor ifcd; 123 struct usb_endpoint_descriptor endpd; 124} __packed; 125 126union dwc_otg_hub_temp { 127 uWord wValue; 128 struct usb_port_status ps; 129}; 130 131struct dwc_otg_flags { 132 uint8_t change_connect:1; 133 uint8_t change_suspend:1; 134 uint8_t change_reset:1; 135 uint8_t change_enabled:1; 136 uint8_t change_over_current:1; 137 uint8_t status_suspend:1; /* set if suspended */ 138 uint8_t status_vbus:1; /* set if present */ 139 uint8_t status_bus_reset:1; /* set if reset complete */ 140 uint8_t status_high_speed:1; /* set if High Speed is selected */ 141 uint8_t status_low_speed:1; /* set if Low Speed is selected */ 142 uint8_t status_device_mode:1; /* set if device mode */ 143 uint8_t self_powered:1; 144 uint8_t clocks_off:1; 145 uint8_t port_powered:1; 146 uint8_t port_enabled:1; 147 uint8_t port_over_current:1; 148 uint8_t d_pulled_up:1; 149}; 150 151struct dwc_otg_profile { 152 struct usb_hw_ep_profile usb; 153 uint16_t max_buffer; 154}; 155 156struct dwc_otg_chan_state { 157 uint16_t allocated; 158 uint16_t wait_sof; 159 uint32_t hcint; 160 uint16_t tx_p_size; /* periodic */ 161 uint16_t tx_np_size; /* non-periodic */ 162}; 163 164struct dwc_otg_softc { 165 struct usb_bus sc_bus; 166 union dwc_otg_hub_temp sc_hub_temp; 167 struct dwc_otg_profile sc_hw_ep_profile[DWC_OTG_MAX_ENDPOINTS]; 168 struct dwc_otg_tt_info sc_tt_info[DWC_OTG_MAX_DEVICES]; 169 struct usb_callout sc_timer; 170 171 struct usb_device *sc_devices[DWC_OTG_MAX_DEVICES]; 172 struct resource *sc_io_res; 173 struct resource *sc_irq_res; 174 void *sc_intr_hdl; 175 bus_size_t sc_io_size; 176 bus_space_tag_t sc_io_tag; 177 bus_space_handle_t sc_io_hdl; 178 179 uint32_t sc_rx_bounce_buffer[1024 / 4]; 180 uint32_t sc_tx_bounce_buffer[MAX(512 * DWC_OTG_MAX_TXP, 1024) / 4]; 181 182 uint32_t sc_fifo_size; 183 uint32_t sc_tx_max_size; 184 uint32_t sc_tx_cur_p_level; /* periodic */ 185 uint32_t sc_tx_cur_np_level; /* non-periodic */ 186 uint32_t sc_irq_mask; 187 uint32_t sc_last_rx_status; 188 uint32_t sc_out_ctl[DWC_OTG_MAX_ENDPOINTS]; 189 uint32_t sc_in_ctl[DWC_OTG_MAX_ENDPOINTS]; 190 struct dwc_otg_chan_state sc_chan_state[DWC_OTG_MAX_CHANNELS]; 191 uint32_t sc_tmr_val; 192 uint32_t sc_hprt_val; 193 uint32_t sc_xfer_complete; 194 195 uint16_t sc_active_rx_ep; 196 uint16_t sc_last_frame_num; 197 198 uint8_t sc_timer_active; 199 uint8_t sc_dev_ep_max; 200 uint8_t sc_dev_in_ep_max; 201 uint8_t sc_host_ch_max; 202 uint8_t sc_needsof; 203 uint8_t sc_rt_addr; /* root HUB address */ 204 uint8_t sc_conf; /* root HUB config */ 205 uint8_t sc_mode; /* mode of operation */ 206#define DWC_MODE_OTG 0 /* both modes */ 207#define DWC_MODE_DEVICE 1 /* device only */ 208#define DWC_MODE_HOST 2 /* host only */ 209 210 uint8_t sc_hub_idata[1]; 211 212 struct dwc_otg_flags sc_flags; 213}; 214 215/* prototypes */ 216 217driver_filter_t dwc_otg_filter_interrupt; 218driver_intr_t dwc_otg_interrupt; 219int dwc_otg_init(struct dwc_otg_softc *); 220void dwc_otg_uninit(struct dwc_otg_softc *); 221 222#endif /* _DWC_OTG_H_ */ 223