1/* $FreeBSD$ */ 2/*- 3 * Copyright (c) 2009 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#ifndef _AVR32DCI_H_ 28#define _AVR32DCI_H_ 29 30#define AVR32_MAX_DEVICES (USB_MIN_DEVICES + 1) 31 32/* Register definitions */ 33 34#define AVR32_CTRL 0x00 /* Control */ 35#define AVR32_CTRL_DEV_ADDR 0x7F 36#define AVR32_CTRL_DEV_FADDR_EN 0x80 37#define AVR32_CTRL_DEV_EN_USBA 0x100 38#define AVR32_CTRL_DEV_DETACH 0x200 39#define AVR32_CTRL_DEV_REWAKEUP 0x400 40 41#define AVR32_FNUM 0x04 /* Frame Number */ 42#define AVR32_FNUM_MASK 0x3FFF 43#define AVR32_FRAME_MASK 0x7FF 44 45/* 0x08 - 0x0C Reserved */ 46#define AVR32_IEN 0x10 /* Interrupt Enable */ 47#define AVR32_INTSTA 0x14 /* Interrupt Status */ 48#define AVR32_CLRINT 0x18 /* Clear Interrupt */ 49 50#define AVR32_INT_SPEED 0x00000001 /* set if High Speed else Full Speed */ 51#define AVR32_INT_DET_SUSPD 0x00000002 52#define AVR32_INT_MICRO_SOF 0x00000004 53#define AVR32_INT_INT_SOF 0x00000008 54#define AVR32_INT_ENDRESET 0x00000010 55#define AVR32_INT_WAKE_UP 0x00000020 56#define AVR32_INT_ENDOFRSM 0x00000040 57#define AVR32_INT_UPSTR_RES 0x00000080 58#define AVR32_INT_EPT_INT(n) (0x00000100 << (n)) 59#define AVR32_INT_DMA_INT(n) (0x01000000 << (n)) 60 61#define AVR32_EPTRST 0x1C /* Endpoints Reset */ 62#define AVR32_EPTRST_MASK(n) (0x00000001 << (n)) 63 64/* 0x20 - 0xCC Reserved */ 65#define AVR32_TSTSOFCNT 0xD0 /* Test SOF Counter */ 66#define AVR32_TSTCNTA 0xD4 /* Test A Counter */ 67#define AVR32_TSTCNTB 0xD8 /* Test B Counter */ 68#define AVR32_TSTMODEREG 0xDC /* Test Mode */ 69#define AVR32_TST 0xE0 /* Test */ 70#define AVR32_TST_NORMAL 0x00000000 71#define AVR32_TST_HS_ONLY 0x00000002 72#define AVR32_TST_FS_ONLY 0x00000003 73 74/* 0xE4 - 0xE8 Reserved */ 75#define AVR32_IPPADDRSIZE 0xEC /* PADDRSIZE */ 76#define AVR32_IPNAME1 0xF0 /* Name1 */ 77#define AVR32_IPNAME2 0xF4 /* Name2 */ 78#define AVR32_IPFEATURES 0xF8 /* Features */ 79#define AVR32_IPFEATURES_NEP(x) (((x) & 0xF) ? ((x) & 0xF) : 0x10) 80 81#define AVR32_IPVERSION 0xFC /* IP Version */ 82 83#define _A(base,n) ((base) + (0x20*(n))) 84#define AVR32_EPTCFG(n) _A(0x100, n) /* Endpoint Configuration */ 85#define AVR32_EPTCFG_EPSIZE(n) ((n)-3) /* power of two */ 86#define AVR32_EPTCFG_EPDIR_OUT 0x00000000 87#define AVR32_EPTCFG_EPDIR_IN 0x00000008 88#define AVR32_EPTCFG_TYPE_CTRL 0x00000000 89#define AVR32_EPTCFG_TYPE_ISOC 0x00000100 90#define AVR32_EPTCFG_TYPE_BULK 0x00000200 91#define AVR32_EPTCFG_TYPE_INTR 0x00000300 92#define AVR32_EPTCFG_NBANK(n) (0x00000400*(n)) 93#define AVR32_EPTCFG_NB_TRANS(n) (0x00001000*(n)) 94#define AVR32_EPTCFG_EPT_MAPD 0x80000000 95 96#define AVR32_EPTCTLENB(n) _A(0x104, n) /* Endpoint Control Enable */ 97#define AVR32_EPTCTLDIS(n) _A(0x108, n) /* Endpoint Control Disable */ 98#define AVR32_EPTCTL(n) _A(0x10C, n) /* Endpoint Control */ 99#define AVR32_EPTCTL_EPT_ENABL 0x00000001 100#define AVR32_EPTCTL_AUTO_VALID 0x00000002 101#define AVR32_EPTCTL_INTDIS_DMA 0x00000008 102#define AVR32_EPTCTL_NYET_DIS 0x00000010 103#define AVR32_EPTCTL_DATAX_RX 0x00000040 104#define AVR32_EPTCTL_MDATA_RX 0x00000080 105#define AVR32_EPTCTL_ERR_OVFLW 0x00000100 106#define AVR32_EPTCTL_RX_BK_RDY 0x00000200 107#define AVR32_EPTCTL_TX_COMPLT 0x00000400 108#define AVR32_EPTCTL_TX_PK_RDY 0x00000800 109#define AVR32_EPTCTL_RX_SETUP 0x00001000 110#define AVR32_EPTCTL_STALL_SNT 0x00002000 111#define AVR32_EPTCTL_NAK_IN 0x00004000 112#define AVR32_EPTCTL_NAK_OUT 0x00008000 113#define AVR32_EPTCTL_BUSY_BANK 0x00040000 114#define AVR32_EPTCTL_SHORT_PCKT 0x80000000 115 116/* 0x110 Reserved */ 117#define AVR32_EPTSETSTA(n) _A(0x114, n) /* Endpoint Set Status */ 118#define AVR32_EPTCLRSTA(n) _A(0x118, n) /* Endpoint Clear Status */ 119#define AVR32_EPTSTA(n) _A(0x11C, n) /* Endpoint Status */ 120#define AVR32_EPTSTA_FRCESTALL 0x00000020 121#define AVR32_EPTSTA_TOGGLESQ_STA(x) (((x) & 0xC0) >> 6) 122#define AVR32_EPTSTA_TOGGLESQ 0x00000040 123#define AVR32_EPTSTA_ERR_OVFLW 0x00000100 124#define AVR32_EPTSTA_RX_BK_RDY 0x00000200 125#define AVR32_EPTSTA_TX_COMPLT 0x00000400 126#define AVR32_EPTSTA_TX_PK_RDY 0x00000800 127#define AVR32_EPTSTA_RX_SETUP 0x00001000 128#define AVR32_EPTSTA_STALL_SNT 0x00002000 129#define AVR32_EPTSTA_NAK_IN 0x00004000 130#define AVR32_EPTSTA_NAK_OUT 0x00008000 131#define AVR32_EPTSTA_CURRENT_BANK(x) (((x) & 0x00030000) >> 16) 132#define AVR32_EPTSTA_BUSY_BANK_STA(x) (((x) & 0x000C0000) >> 18) 133#define AVR32_EPTSTA_BYTE_COUNT(x) (((x) & 0x7FF00000) >> 20) 134#define AVR32_EPTSTA_SHRT_PCKT 0x80000000 135 136/* 0x300 - 0x30C Reserved */ 137#define AVR32_DMANXTDSC 0x310 /* DMA Next Descriptor Address */ 138#define AVR32_DMAADDRESS 0x314 /* DMA Channel Address */ 139 140#define AVR32_READ_4(sc, reg) \ 141 bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg) 142 143#define AVR32_WRITE_4(sc, reg, data) \ 144 bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data) 145 146#define AVR32_WRITE_MULTI_4(sc, reg, ptr, len) \ 147 bus_space_write_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len) 148 149#define AVR32_READ_MULTI_4(sc, reg, ptr, len) \ 150 bus_space_read_multi_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, ptr, len) 151 152/* 153 * Maximum number of endpoints supported: 154 */ 155#define AVR32_EP_MAX 7 156 157struct avr32dci_td; 158 159typedef uint8_t (avr32dci_cmd_t)(struct avr32dci_td *td); 160typedef void (avr32dci_clocks_t)(struct usb_bus *); 161 162struct avr32dci_td { 163 struct avr32dci_td *obj_next; 164 avr32dci_cmd_t *func; 165 struct usb_page_cache *pc; 166 uint32_t offset; 167 uint32_t remainder; 168 uint16_t max_packet_size; 169 uint8_t bank_shift; 170 uint8_t error:1; 171 uint8_t alt_next:1; 172 uint8_t short_pkt:1; 173 uint8_t support_multi_buffer:1; 174 uint8_t did_stall:1; 175 uint8_t ep_no:3; 176}; 177 178struct avr32dci_std_temp { 179 avr32dci_cmd_t *func; 180 struct usb_page_cache *pc; 181 struct avr32dci_td *td; 182 struct avr32dci_td *td_next; 183 uint32_t len; 184 uint32_t offset; 185 uint16_t max_frame_size; 186 uint8_t bank_shift; 187 uint8_t short_pkt; 188 /* 189 * short_pkt = 0: transfer should be short terminated 190 * short_pkt = 1: transfer should not be short terminated 191 */ 192 uint8_t setup_alt_next; 193 uint8_t did_stall; 194}; 195 196struct avr32dci_config_desc { 197 struct usb_config_descriptor confd; 198 struct usb_interface_descriptor ifcd; 199 struct usb_endpoint_descriptor endpd; 200} __packed; 201 202union avr32dci_hub_temp { 203 uWord wValue; 204 struct usb_port_status ps; 205}; 206 207struct avr32dci_flags { 208 uint8_t change_connect:1; 209 uint8_t change_suspend:1; 210 uint8_t status_suspend:1; /* set if suspended */ 211 uint8_t status_vbus:1; /* set if present */ 212 uint8_t status_bus_reset:1; /* set if reset complete */ 213 uint8_t remote_wakeup:1; 214 uint8_t self_powered:1; 215 uint8_t clocks_off:1; 216 uint8_t port_powered:1; 217 uint8_t port_enabled:1; 218 uint8_t d_pulled_up:1; 219}; 220 221struct avr32dci_softc { 222 struct usb_bus sc_bus; 223 union avr32dci_hub_temp sc_hub_temp; 224 225 /* must be set by by the bus interface layer */ 226 avr32dci_clocks_t *sc_clocks_on; 227 avr32dci_clocks_t *sc_clocks_off; 228 229 struct usb_device *sc_devices[AVR32_MAX_DEVICES]; 230 struct resource *sc_irq_res; 231 void *sc_intr_hdl; 232 struct resource *sc_io_res; 233 bus_space_tag_t sc_io_tag; 234 bus_space_handle_t sc_io_hdl; 235 uint8_t *physdata; 236 237 uint8_t sc_rt_addr; /* root hub address */ 238 uint8_t sc_dv_addr; /* device address */ 239 uint8_t sc_conf; /* root hub config */ 240 241 uint8_t sc_hub_idata[1]; 242 243 struct avr32dci_flags sc_flags; 244}; 245 246/* prototypes */ 247 248usb_error_t avr32dci_init(struct avr32dci_softc *sc); 249void avr32dci_uninit(struct avr32dci_softc *sc); 250void avr32dci_interrupt(struct avr32dci_softc *sc); 251void avr32dci_vbus_interrupt(struct avr32dci_softc *sc, uint8_t is_on); 252 253#endif /* _AVR32DCI_H_ */ 254