if_urtwn.c revision 289758
1251538Srpaulo/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2251538Srpaulo 3251538Srpaulo/*- 4251538Srpaulo * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5264912Skevlo * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6251538Srpaulo * 7251538Srpaulo * Permission to use, copy, modify, and distribute this software for any 8251538Srpaulo * purpose with or without fee is hereby granted, provided that the above 9251538Srpaulo * copyright notice and this permission notice appear in all copies. 10251538Srpaulo * 11251538Srpaulo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12251538Srpaulo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13251538Srpaulo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14251538Srpaulo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15251538Srpaulo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16251538Srpaulo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17251538Srpaulo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18251538Srpaulo */ 19251538Srpaulo 20251538Srpaulo#include <sys/cdefs.h> 21251538Srpaulo__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 289758 2015-10-22 15:42:53Z avos $"); 22251538Srpaulo 23251538Srpaulo/* 24264912Skevlo * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 25251538Srpaulo */ 26251538Srpaulo 27288353Sadrian#include "opt_wlan.h" 28288353Sadrian 29251538Srpaulo#include <sys/param.h> 30251538Srpaulo#include <sys/sockio.h> 31251538Srpaulo#include <sys/sysctl.h> 32251538Srpaulo#include <sys/lock.h> 33251538Srpaulo#include <sys/mutex.h> 34251538Srpaulo#include <sys/mbuf.h> 35251538Srpaulo#include <sys/kernel.h> 36251538Srpaulo#include <sys/socket.h> 37251538Srpaulo#include <sys/systm.h> 38251538Srpaulo#include <sys/malloc.h> 39251538Srpaulo#include <sys/module.h> 40251538Srpaulo#include <sys/bus.h> 41251538Srpaulo#include <sys/endian.h> 42251538Srpaulo#include <sys/linker.h> 43251538Srpaulo#include <sys/firmware.h> 44251538Srpaulo#include <sys/kdb.h> 45251538Srpaulo 46251538Srpaulo#include <machine/bus.h> 47251538Srpaulo#include <machine/resource.h> 48251538Srpaulo#include <sys/rman.h> 49251538Srpaulo 50251538Srpaulo#include <net/bpf.h> 51251538Srpaulo#include <net/if.h> 52257176Sglebius#include <net/if_var.h> 53251538Srpaulo#include <net/if_arp.h> 54251538Srpaulo#include <net/ethernet.h> 55251538Srpaulo#include <net/if_dl.h> 56251538Srpaulo#include <net/if_media.h> 57251538Srpaulo#include <net/if_types.h> 58251538Srpaulo 59251538Srpaulo#include <netinet/in.h> 60251538Srpaulo#include <netinet/in_systm.h> 61251538Srpaulo#include <netinet/in_var.h> 62251538Srpaulo#include <netinet/if_ether.h> 63251538Srpaulo#include <netinet/ip.h> 64251538Srpaulo 65251538Srpaulo#include <net80211/ieee80211_var.h> 66288088Sadrian#include <net80211/ieee80211_input.h> 67251538Srpaulo#include <net80211/ieee80211_regdomain.h> 68251538Srpaulo#include <net80211/ieee80211_radiotap.h> 69251538Srpaulo#include <net80211/ieee80211_ratectl.h> 70251538Srpaulo 71251538Srpaulo#include <dev/usb/usb.h> 72251538Srpaulo#include <dev/usb/usbdi.h> 73251538Srpaulo#include "usbdevs.h" 74251538Srpaulo 75251538Srpaulo#define USB_DEBUG_VAR urtwn_debug 76251538Srpaulo#include <dev/usb/usb_debug.h> 77251538Srpaulo 78251538Srpaulo#include <dev/usb/wlan/if_urtwnreg.h> 79289167Sadrian#include <dev/usb/wlan/if_urtwnvar.h> 80251538Srpaulo 81251538Srpaulo#ifdef USB_DEBUG 82251538Srpaulostatic int urtwn_debug = 0; 83251538Srpaulo 84251538SrpauloSYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 85276701ShselaskySYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RWTUN, &urtwn_debug, 0, 86251538Srpaulo "Debug level"); 87251538Srpaulo#endif 88251538Srpaulo 89252406Srpaulo#define URTWN_RSSI(r) (r) - 110 90288088Sadrian#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 91251538Srpaulo 92251538Srpaulo/* various supported device vendors/products */ 93251596Srpaulostatic const STRUCT_USB_HOST_ID urtwn_devs[] = { 94251538Srpaulo#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 95264912Skevlo#define URTWN_RTL8188E_DEV(v,p) \ 96264912Skevlo { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 97264912Skevlo#define URTWN_RTL8188E 1 98251538Srpaulo URTWN_DEV(ABOCOM, RTL8188CU_1), 99251538Srpaulo URTWN_DEV(ABOCOM, RTL8188CU_2), 100251538Srpaulo URTWN_DEV(ABOCOM, RTL8192CU), 101251538Srpaulo URTWN_DEV(ASUS, RTL8192CU), 102266721Skevlo URTWN_DEV(ASUS, USBN10NANO), 103251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CE_1), 104251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CE_2), 105251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CU), 106251538Srpaulo URTWN_DEV(BELKIN, F7D2102), 107251538Srpaulo URTWN_DEV(BELKIN, RTL8188CU), 108251538Srpaulo URTWN_DEV(BELKIN, RTL8192CU), 109251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_1), 110251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_2), 111251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_3), 112251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_4), 113251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_5), 114251538Srpaulo URTWN_DEV(COREGA, RTL8192CU), 115251538Srpaulo URTWN_DEV(DLINK, RTL8188CU), 116251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_1), 117251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_2), 118251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_3), 119252196Skevlo URTWN_DEV(DLINK, DWA131B), 120251538Srpaulo URTWN_DEV(EDIMAX, EW7811UN), 121251538Srpaulo URTWN_DEV(EDIMAX, RTL8192CU), 122251538Srpaulo URTWN_DEV(FEIXUN, RTL8188CU), 123251538Srpaulo URTWN_DEV(FEIXUN, RTL8192CU), 124251538Srpaulo URTWN_DEV(GUILLEMOT, HWNUP150), 125251538Srpaulo URTWN_DEV(HAWKING, RTL8192CU), 126251538Srpaulo URTWN_DEV(HP3, RTL8188CU), 127251538Srpaulo URTWN_DEV(NETGEAR, WNA1000M), 128251538Srpaulo URTWN_DEV(NETGEAR, RTL8192CU), 129251538Srpaulo URTWN_DEV(NETGEAR4, RTL8188CU), 130251538Srpaulo URTWN_DEV(NOVATECH, RTL8188CU), 131251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_1), 132251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_2), 133251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_3), 134251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_4), 135251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CUS), 136251538Srpaulo URTWN_DEV(PLANEX2, RTL8192CU), 137251538Srpaulo URTWN_DEV(REALTEK, RTL8188CE_0), 138251538Srpaulo URTWN_DEV(REALTEK, RTL8188CE_1), 139251538Srpaulo URTWN_DEV(REALTEK, RTL8188CTV), 140251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_0), 141251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_1), 142251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_2), 143282119Skevlo URTWN_DEV(REALTEK, RTL8188CU_3), 144251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_COMBO), 145251538Srpaulo URTWN_DEV(REALTEK, RTL8188CUS), 146251538Srpaulo URTWN_DEV(REALTEK, RTL8188RU_1), 147251538Srpaulo URTWN_DEV(REALTEK, RTL8188RU_2), 148272410Shselasky URTWN_DEV(REALTEK, RTL8188RU_3), 149251538Srpaulo URTWN_DEV(REALTEK, RTL8191CU), 150251538Srpaulo URTWN_DEV(REALTEK, RTL8192CE), 151251538Srpaulo URTWN_DEV(REALTEK, RTL8192CU), 152251538Srpaulo URTWN_DEV(SITECOMEU, RTL8188CU_1), 153251538Srpaulo URTWN_DEV(SITECOMEU, RTL8188CU_2), 154251538Srpaulo URTWN_DEV(SITECOMEU, RTL8192CU), 155251538Srpaulo URTWN_DEV(TRENDNET, RTL8188CU), 156251538Srpaulo URTWN_DEV(TRENDNET, RTL8192CU), 157251538Srpaulo URTWN_DEV(ZYXEL, RTL8192CU), 158264912Skevlo /* URTWN_RTL8188E */ 159273589Skevlo URTWN_RTL8188E_DEV(DLINK, DWA123D1), 160270191Skevlo URTWN_RTL8188E_DEV(DLINK, DWA125D1), 161273589Skevlo URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 162264912Skevlo URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 163264912Skevlo URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 164264912Skevlo#undef URTWN_RTL8188E_DEV 165251538Srpaulo#undef URTWN_DEV 166251538Srpaulo}; 167251538Srpaulo 168251538Srpaulostatic device_probe_t urtwn_match; 169251538Srpaulostatic device_attach_t urtwn_attach; 170251538Srpaulostatic device_detach_t urtwn_detach; 171251538Srpaulo 172251538Srpaulostatic usb_callback_t urtwn_bulk_tx_callback; 173251538Srpaulostatic usb_callback_t urtwn_bulk_rx_callback; 174251538Srpaulo 175288353Sadrianstatic void urtwn_drain_mbufq(struct urtwn_softc *sc); 176287197Sglebiusstatic usb_error_t urtwn_do_request(struct urtwn_softc *, 177287197Sglebius struct usb_device_request *, void *); 178251538Srpaulostatic struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 179251538Srpaulo const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 180251538Srpaulo const uint8_t [IEEE80211_ADDR_LEN], 181251538Srpaulo const uint8_t [IEEE80211_ADDR_LEN]); 182251538Srpaulostatic void urtwn_vap_delete(struct ieee80211vap *); 183281069Srpaulostatic struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 184251538Srpaulo int *); 185281069Srpaulostatic struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *, 186251538Srpaulo int *, int8_t *); 187251538Srpaulostatic void urtwn_txeof(struct usb_xfer *, struct urtwn_data *); 188281069Srpaulostatic int urtwn_alloc_list(struct urtwn_softc *, 189251538Srpaulo struct urtwn_data[], int, int); 190251538Srpaulostatic int urtwn_alloc_rx_list(struct urtwn_softc *); 191251538Srpaulostatic int urtwn_alloc_tx_list(struct urtwn_softc *); 192251538Srpaulostatic void urtwn_free_list(struct urtwn_softc *, 193251538Srpaulo struct urtwn_data data[], int); 194289066Skevlostatic void urtwn_free_rx_list(struct urtwn_softc *); 195289066Skevlostatic void urtwn_free_tx_list(struct urtwn_softc *); 196251538Srpaulostatic struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 197251538Srpaulostatic struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 198281069Srpaulostatic int urtwn_write_region_1(struct urtwn_softc *, uint16_t, 199251538Srpaulo uint8_t *, int); 200251538Srpaulostatic void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 201251538Srpaulostatic void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 202251538Srpaulostatic void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 203281069Srpaulostatic int urtwn_read_region_1(struct urtwn_softc *, uint16_t, 204251538Srpaulo uint8_t *, int); 205251538Srpaulostatic uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 206251538Srpaulostatic uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 207251538Srpaulostatic uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 208281069Srpaulostatic int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 209251538Srpaulo const void *, int); 210264912Skevlostatic void urtwn_r92c_rf_write(struct urtwn_softc *, int, 211264912Skevlo uint8_t, uint32_t); 212281069Srpaulostatic void urtwn_r88e_rf_write(struct urtwn_softc *, int, 213264912Skevlo uint8_t, uint32_t); 214251538Srpaulostatic uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 215281069Srpaulostatic int urtwn_llt_write(struct urtwn_softc *, uint32_t, 216251538Srpaulo uint32_t); 217251538Srpaulostatic uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 218251538Srpaulostatic void urtwn_efuse_read(struct urtwn_softc *); 219264912Skevlostatic void urtwn_efuse_switch_power(struct urtwn_softc *); 220251538Srpaulostatic int urtwn_read_chipid(struct urtwn_softc *); 221251538Srpaulostatic void urtwn_read_rom(struct urtwn_softc *); 222264912Skevlostatic void urtwn_r88e_read_rom(struct urtwn_softc *); 223251538Srpaulostatic int urtwn_ra_init(struct urtwn_softc *); 224251538Srpaulostatic void urtwn_tsf_sync_enable(struct urtwn_softc *); 225251538Srpaulostatic void urtwn_set_led(struct urtwn_softc *, int, int); 226281069Srpaulostatic int urtwn_newstate(struct ieee80211vap *, 227251538Srpaulo enum ieee80211_state, int); 228251538Srpaulostatic void urtwn_watchdog(void *); 229251538Srpaulostatic void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 230251538Srpaulostatic int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 231264912Skevlostatic int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 232251538Srpaulostatic int urtwn_tx_start(struct urtwn_softc *, 233251538Srpaulo struct ieee80211_node *, struct mbuf *, 234251538Srpaulo struct urtwn_data *); 235287197Sglebiusstatic int urtwn_transmit(struct ieee80211com *, struct mbuf *); 236287197Sglebiusstatic void urtwn_start(struct urtwn_softc *); 237287197Sglebiusstatic void urtwn_parent(struct ieee80211com *); 238264912Skevlostatic int urtwn_r92c_power_on(struct urtwn_softc *); 239264912Skevlostatic int urtwn_r88e_power_on(struct urtwn_softc *); 240251538Srpaulostatic int urtwn_llt_init(struct urtwn_softc *); 241251538Srpaulostatic void urtwn_fw_reset(struct urtwn_softc *); 242264912Skevlostatic void urtwn_r88e_fw_reset(struct urtwn_softc *); 243281069Srpaulostatic int urtwn_fw_loadpage(struct urtwn_softc *, int, 244251538Srpaulo const uint8_t *, int); 245251538Srpaulostatic int urtwn_load_firmware(struct urtwn_softc *); 246264912Skevlostatic int urtwn_r92c_dma_init(struct urtwn_softc *); 247264912Skevlostatic int urtwn_r88e_dma_init(struct urtwn_softc *); 248251538Srpaulostatic void urtwn_mac_init(struct urtwn_softc *); 249251538Srpaulostatic void urtwn_bb_init(struct urtwn_softc *); 250251538Srpaulostatic void urtwn_rf_init(struct urtwn_softc *); 251251538Srpaulostatic void urtwn_cam_init(struct urtwn_softc *); 252251538Srpaulostatic void urtwn_pa_bias_init(struct urtwn_softc *); 253251538Srpaulostatic void urtwn_rxfilter_init(struct urtwn_softc *); 254251538Srpaulostatic void urtwn_edca_init(struct urtwn_softc *); 255281069Srpaulostatic void urtwn_write_txpower(struct urtwn_softc *, int, 256251538Srpaulo uint16_t[]); 257251538Srpaulostatic void urtwn_get_txpower(struct urtwn_softc *, int, 258281069Srpaulo struct ieee80211_channel *, 259251538Srpaulo struct ieee80211_channel *, uint16_t[]); 260264912Skevlostatic void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 261281069Srpaulo struct ieee80211_channel *, 262264912Skevlo struct ieee80211_channel *, uint16_t[]); 263251538Srpaulostatic void urtwn_set_txpower(struct urtwn_softc *, 264281069Srpaulo struct ieee80211_channel *, 265251538Srpaulo struct ieee80211_channel *); 266251538Srpaulostatic void urtwn_scan_start(struct ieee80211com *); 267251538Srpaulostatic void urtwn_scan_end(struct ieee80211com *); 268251538Srpaulostatic void urtwn_set_channel(struct ieee80211com *); 269289066Skevlostatic void urtwn_update_mcast(struct ieee80211com *); 270251538Srpaulostatic void urtwn_set_chan(struct urtwn_softc *, 271281069Srpaulo struct ieee80211_channel *, 272251538Srpaulo struct ieee80211_channel *); 273251538Srpaulostatic void urtwn_iq_calib(struct urtwn_softc *); 274251538Srpaulostatic void urtwn_lc_calib(struct urtwn_softc *); 275287197Sglebiusstatic void urtwn_init(struct urtwn_softc *); 276287197Sglebiusstatic void urtwn_stop(struct urtwn_softc *); 277251538Srpaulostatic void urtwn_abort_xfers(struct urtwn_softc *); 278251538Srpaulostatic int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 279251538Srpaulo const struct ieee80211_bpf_params *); 280266472Shselaskystatic void urtwn_ms_delay(struct urtwn_softc *); 281251538Srpaulo 282251538Srpaulo/* Aliases. */ 283251538Srpaulo#define urtwn_bb_write urtwn_write_4 284251538Srpaulo#define urtwn_bb_read urtwn_read_4 285251538Srpaulo 286251538Srpaulostatic const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 287251538Srpaulo [URTWN_BULK_RX] = { 288251538Srpaulo .type = UE_BULK, 289251538Srpaulo .endpoint = UE_ADDR_ANY, 290251538Srpaulo .direction = UE_DIR_IN, 291251538Srpaulo .bufsize = URTWN_RXBUFSZ, 292251538Srpaulo .flags = { 293251538Srpaulo .pipe_bof = 1, 294251538Srpaulo .short_xfer_ok = 1 295251538Srpaulo }, 296251538Srpaulo .callback = urtwn_bulk_rx_callback, 297251538Srpaulo }, 298251538Srpaulo [URTWN_BULK_TX_BE] = { 299251538Srpaulo .type = UE_BULK, 300251538Srpaulo .endpoint = 0x03, 301251538Srpaulo .direction = UE_DIR_OUT, 302251538Srpaulo .bufsize = URTWN_TXBUFSZ, 303251538Srpaulo .flags = { 304251538Srpaulo .ext_buffer = 1, 305251538Srpaulo .pipe_bof = 1, 306251538Srpaulo .force_short_xfer = 1 307251538Srpaulo }, 308251538Srpaulo .callback = urtwn_bulk_tx_callback, 309251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 310251538Srpaulo }, 311251538Srpaulo [URTWN_BULK_TX_BK] = { 312251538Srpaulo .type = UE_BULK, 313251538Srpaulo .endpoint = 0x03, 314251538Srpaulo .direction = UE_DIR_OUT, 315251538Srpaulo .bufsize = URTWN_TXBUFSZ, 316251538Srpaulo .flags = { 317251538Srpaulo .ext_buffer = 1, 318251538Srpaulo .pipe_bof = 1, 319251538Srpaulo .force_short_xfer = 1, 320251538Srpaulo }, 321251538Srpaulo .callback = urtwn_bulk_tx_callback, 322251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 323251538Srpaulo }, 324251538Srpaulo [URTWN_BULK_TX_VI] = { 325251538Srpaulo .type = UE_BULK, 326251538Srpaulo .endpoint = 0x02, 327251538Srpaulo .direction = UE_DIR_OUT, 328251538Srpaulo .bufsize = URTWN_TXBUFSZ, 329251538Srpaulo .flags = { 330251538Srpaulo .ext_buffer = 1, 331251538Srpaulo .pipe_bof = 1, 332251538Srpaulo .force_short_xfer = 1 333251538Srpaulo }, 334251538Srpaulo .callback = urtwn_bulk_tx_callback, 335251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 336251538Srpaulo }, 337251538Srpaulo [URTWN_BULK_TX_VO] = { 338251538Srpaulo .type = UE_BULK, 339251538Srpaulo .endpoint = 0x02, 340251538Srpaulo .direction = UE_DIR_OUT, 341251538Srpaulo .bufsize = URTWN_TXBUFSZ, 342251538Srpaulo .flags = { 343251538Srpaulo .ext_buffer = 1, 344251538Srpaulo .pipe_bof = 1, 345251538Srpaulo .force_short_xfer = 1 346251538Srpaulo }, 347251538Srpaulo .callback = urtwn_bulk_tx_callback, 348251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 349251538Srpaulo }, 350251538Srpaulo}; 351251538Srpaulo 352251538Srpaulostatic int 353251538Srpaulourtwn_match(device_t self) 354251538Srpaulo{ 355251538Srpaulo struct usb_attach_arg *uaa = device_get_ivars(self); 356251538Srpaulo 357251538Srpaulo if (uaa->usb_mode != USB_MODE_HOST) 358251538Srpaulo return (ENXIO); 359251538Srpaulo if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 360251538Srpaulo return (ENXIO); 361251538Srpaulo if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 362251538Srpaulo return (ENXIO); 363251538Srpaulo 364251538Srpaulo return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 365251538Srpaulo} 366251538Srpaulo 367251538Srpaulostatic int 368251538Srpaulourtwn_attach(device_t self) 369251538Srpaulo{ 370251538Srpaulo struct usb_attach_arg *uaa = device_get_ivars(self); 371251538Srpaulo struct urtwn_softc *sc = device_get_softc(self); 372287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 373251538Srpaulo uint8_t iface_index, bands; 374251538Srpaulo int error; 375251538Srpaulo 376251538Srpaulo device_set_usb_desc(self); 377251538Srpaulo sc->sc_udev = uaa->device; 378251538Srpaulo sc->sc_dev = self; 379264912Skevlo if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 380264912Skevlo sc->chip |= URTWN_CHIP_88E; 381251538Srpaulo 382251538Srpaulo mtx_init(&sc->sc_mtx, device_get_nameunit(self), 383251538Srpaulo MTX_NETWORK_LOCK, MTX_DEF); 384251538Srpaulo callout_init(&sc->sc_watchdog_ch, 0); 385287197Sglebius mbufq_init(&sc->sc_snd, ifqmaxlen); 386251538Srpaulo 387251538Srpaulo iface_index = URTWN_IFACE_INDEX; 388251538Srpaulo error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 389251538Srpaulo urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 390251538Srpaulo if (error) { 391251538Srpaulo device_printf(self, "could not allocate USB transfers, " 392251538Srpaulo "err=%s\n", usbd_errstr(error)); 393251538Srpaulo goto detach; 394251538Srpaulo } 395251538Srpaulo 396251538Srpaulo URTWN_LOCK(sc); 397251538Srpaulo 398251538Srpaulo error = urtwn_read_chipid(sc); 399251538Srpaulo if (error) { 400251538Srpaulo device_printf(sc->sc_dev, "unsupported test chip\n"); 401251538Srpaulo URTWN_UNLOCK(sc); 402251538Srpaulo goto detach; 403251538Srpaulo } 404251538Srpaulo 405251538Srpaulo /* Determine number of Tx/Rx chains. */ 406251538Srpaulo if (sc->chip & URTWN_CHIP_92C) { 407251538Srpaulo sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 408251538Srpaulo sc->nrxchains = 2; 409251538Srpaulo } else { 410251538Srpaulo sc->ntxchains = 1; 411251538Srpaulo sc->nrxchains = 1; 412251538Srpaulo } 413251538Srpaulo 414264912Skevlo if (sc->chip & URTWN_CHIP_88E) 415264912Skevlo urtwn_r88e_read_rom(sc); 416264912Skevlo else 417264912Skevlo urtwn_read_rom(sc); 418264912Skevlo 419251538Srpaulo device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 420251538Srpaulo (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 421264912Skevlo (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 422251538Srpaulo (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 423251538Srpaulo (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 424251538Srpaulo "8188CUS", sc->ntxchains, sc->nrxchains); 425251538Srpaulo 426251538Srpaulo URTWN_UNLOCK(sc); 427251538Srpaulo 428283537Sglebius ic->ic_softc = sc; 429283527Sglebius ic->ic_name = device_get_nameunit(self); 430251538Srpaulo ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 431251538Srpaulo ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 432251538Srpaulo 433251538Srpaulo /* set device capabilities */ 434251538Srpaulo ic->ic_caps = 435251538Srpaulo IEEE80211_C_STA /* station mode */ 436251538Srpaulo | IEEE80211_C_MONITOR /* monitor mode */ 437251538Srpaulo | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 438251538Srpaulo | IEEE80211_C_SHSLOT /* short slot time supported */ 439251538Srpaulo | IEEE80211_C_BGSCAN /* capable of bg scanning */ 440251538Srpaulo | IEEE80211_C_WPA /* 802.11i */ 441251538Srpaulo ; 442251538Srpaulo 443251538Srpaulo bands = 0; 444251538Srpaulo setbit(&bands, IEEE80211_MODE_11B); 445251538Srpaulo setbit(&bands, IEEE80211_MODE_11G); 446251538Srpaulo ieee80211_init_channels(ic, NULL, &bands); 447251538Srpaulo 448287197Sglebius ieee80211_ifattach(ic); 449251538Srpaulo ic->ic_raw_xmit = urtwn_raw_xmit; 450251538Srpaulo ic->ic_scan_start = urtwn_scan_start; 451251538Srpaulo ic->ic_scan_end = urtwn_scan_end; 452251538Srpaulo ic->ic_set_channel = urtwn_set_channel; 453287197Sglebius ic->ic_transmit = urtwn_transmit; 454287197Sglebius ic->ic_parent = urtwn_parent; 455251538Srpaulo ic->ic_vap_create = urtwn_vap_create; 456251538Srpaulo ic->ic_vap_delete = urtwn_vap_delete; 457251538Srpaulo ic->ic_update_mcast = urtwn_update_mcast; 458251538Srpaulo 459281069Srpaulo ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 460251538Srpaulo sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 461251538Srpaulo &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 462251538Srpaulo URTWN_RX_RADIOTAP_PRESENT); 463251538Srpaulo 464251538Srpaulo if (bootverbose) 465251538Srpaulo ieee80211_announce(ic); 466251538Srpaulo 467251538Srpaulo return (0); 468251538Srpaulo 469251538Srpaulodetach: 470251538Srpaulo urtwn_detach(self); 471251538Srpaulo return (ENXIO); /* failure */ 472251538Srpaulo} 473251538Srpaulo 474251538Srpaulostatic int 475251538Srpaulourtwn_detach(device_t self) 476251538Srpaulo{ 477251538Srpaulo struct urtwn_softc *sc = device_get_softc(self); 478287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 479263153Skevlo unsigned int x; 480281069Srpaulo 481263153Skevlo /* Prevent further ioctls. */ 482263153Skevlo URTWN_LOCK(sc); 483263153Skevlo sc->sc_flags |= URTWN_DETACHED; 484287197Sglebius urtwn_stop(sc); 485263153Skevlo URTWN_UNLOCK(sc); 486251538Srpaulo 487251538Srpaulo callout_drain(&sc->sc_watchdog_ch); 488251538Srpaulo 489288353Sadrian /* stop all USB transfers */ 490288353Sadrian usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 491288353Sadrian 492263153Skevlo /* Prevent further allocations from RX/TX data lists. */ 493263153Skevlo URTWN_LOCK(sc); 494263153Skevlo STAILQ_INIT(&sc->sc_tx_active); 495263153Skevlo STAILQ_INIT(&sc->sc_tx_inactive); 496263153Skevlo STAILQ_INIT(&sc->sc_tx_pending); 497263153Skevlo 498263153Skevlo STAILQ_INIT(&sc->sc_rx_active); 499263153Skevlo STAILQ_INIT(&sc->sc_rx_inactive); 500263153Skevlo URTWN_UNLOCK(sc); 501263153Skevlo 502263153Skevlo /* drain USB transfers */ 503263153Skevlo for (x = 0; x != URTWN_N_TRANSFER; x++) 504263153Skevlo usbd_transfer_drain(sc->sc_xfer[x]); 505263153Skevlo 506263153Skevlo /* Free data buffers. */ 507263153Skevlo URTWN_LOCK(sc); 508263153Skevlo urtwn_free_tx_list(sc); 509263153Skevlo urtwn_free_rx_list(sc); 510263153Skevlo URTWN_UNLOCK(sc); 511263153Skevlo 512251538Srpaulo ieee80211_ifdetach(ic); 513251538Srpaulo mtx_destroy(&sc->sc_mtx); 514251538Srpaulo 515251538Srpaulo return (0); 516251538Srpaulo} 517251538Srpaulo 518251538Srpaulostatic void 519289066Skevlourtwn_drain_mbufq(struct urtwn_softc *sc) 520251538Srpaulo{ 521289066Skevlo struct mbuf *m; 522289066Skevlo struct ieee80211_node *ni; 523289066Skevlo URTWN_ASSERT_LOCKED(sc); 524289066Skevlo while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 525289066Skevlo ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 526289066Skevlo m->m_pkthdr.rcvif = NULL; 527289066Skevlo ieee80211_free_node(ni); 528289066Skevlo m_freem(m); 529251538Srpaulo } 530251538Srpaulo} 531251538Srpaulo 532251538Srpaulostatic usb_error_t 533251538Srpaulourtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 534251538Srpaulo void *data) 535251538Srpaulo{ 536251538Srpaulo usb_error_t err; 537251538Srpaulo int ntries = 10; 538251538Srpaulo 539251538Srpaulo URTWN_ASSERT_LOCKED(sc); 540251538Srpaulo 541251538Srpaulo while (ntries--) { 542251538Srpaulo err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 543251538Srpaulo req, data, 0, NULL, 250 /* ms */); 544251538Srpaulo if (err == 0) 545251538Srpaulo break; 546251538Srpaulo 547251538Srpaulo DPRINTFN(1, "Control request failed, %s (retrying)\n", 548251538Srpaulo usbd_errstr(err)); 549251538Srpaulo usb_pause_mtx(&sc->sc_mtx, hz / 100); 550251538Srpaulo } 551251538Srpaulo return (err); 552251538Srpaulo} 553251538Srpaulo 554251538Srpaulostatic struct ieee80211vap * 555251538Srpaulourtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 556251538Srpaulo enum ieee80211_opmode opmode, int flags, 557251538Srpaulo const uint8_t bssid[IEEE80211_ADDR_LEN], 558251538Srpaulo const uint8_t mac[IEEE80211_ADDR_LEN]) 559251538Srpaulo{ 560251538Srpaulo struct urtwn_vap *uvp; 561251538Srpaulo struct ieee80211vap *vap; 562251538Srpaulo 563251538Srpaulo if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 564251538Srpaulo return (NULL); 565251538Srpaulo 566287197Sglebius uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 567251538Srpaulo vap = &uvp->vap; 568251538Srpaulo /* enable s/w bmiss handling for sta mode */ 569251538Srpaulo 570281069Srpaulo if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 571287197Sglebius flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 572257743Shselasky /* out of memory */ 573257743Shselasky free(uvp, M_80211_VAP); 574257743Shselasky return (NULL); 575257743Shselasky } 576257743Shselasky 577251538Srpaulo /* override state transition machine */ 578251538Srpaulo uvp->newstate = vap->iv_newstate; 579251538Srpaulo vap->iv_newstate = urtwn_newstate; 580251538Srpaulo 581251538Srpaulo /* complete setup */ 582251538Srpaulo ieee80211_vap_attach(vap, ieee80211_media_change, 583287197Sglebius ieee80211_media_status, mac); 584251538Srpaulo ic->ic_opmode = opmode; 585251538Srpaulo return (vap); 586251538Srpaulo} 587251538Srpaulo 588251538Srpaulostatic void 589251538Srpaulourtwn_vap_delete(struct ieee80211vap *vap) 590251538Srpaulo{ 591251538Srpaulo struct urtwn_vap *uvp = URTWN_VAP(vap); 592251538Srpaulo 593251538Srpaulo ieee80211_vap_detach(vap); 594251538Srpaulo free(uvp, M_80211_VAP); 595251538Srpaulo} 596251538Srpaulo 597251538Srpaulostatic struct mbuf * 598251538Srpaulourtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 599251538Srpaulo{ 600287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 601251538Srpaulo struct ieee80211_frame *wh; 602251538Srpaulo struct mbuf *m; 603251538Srpaulo struct r92c_rx_stat *stat; 604251538Srpaulo uint32_t rxdw0, rxdw3; 605251538Srpaulo uint8_t rate; 606251538Srpaulo int8_t rssi = 0; 607251538Srpaulo int infosz; 608251538Srpaulo 609251538Srpaulo /* 610251538Srpaulo * don't pass packets to the ieee80211 framework if the driver isn't 611251538Srpaulo * RUNNING. 612251538Srpaulo */ 613287197Sglebius if (!(sc->sc_flags & URTWN_RUNNING)) 614251538Srpaulo return (NULL); 615251538Srpaulo 616251538Srpaulo stat = (struct r92c_rx_stat *)buf; 617251538Srpaulo rxdw0 = le32toh(stat->rxdw0); 618251538Srpaulo rxdw3 = le32toh(stat->rxdw3); 619251538Srpaulo 620251538Srpaulo if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 621251538Srpaulo /* 622251538Srpaulo * This should not happen since we setup our Rx filter 623251538Srpaulo * to not receive these frames. 624251538Srpaulo */ 625287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 626251538Srpaulo return (NULL); 627251538Srpaulo } 628271303Skevlo if (pktlen < sizeof(*wh) || pktlen > MCLBYTES) { 629287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 630271303Skevlo return (NULL); 631271303Skevlo } 632251538Srpaulo 633251538Srpaulo rate = MS(rxdw3, R92C_RXDW3_RATE); 634251538Srpaulo infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 635251538Srpaulo 636251538Srpaulo /* Get RSSI from PHY status descriptor if present. */ 637251538Srpaulo if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 638281069Srpaulo if (sc->chip & URTWN_CHIP_88E) 639264912Skevlo rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 640264912Skevlo else 641264912Skevlo rssi = urtwn_get_rssi(sc, rate, &stat[1]); 642251538Srpaulo /* Update our average RSSI. */ 643251538Srpaulo urtwn_update_avgrssi(sc, rate, rssi); 644252405Srpaulo /* 645252405Srpaulo * Convert the RSSI to a range that will be accepted 646252405Srpaulo * by net80211. 647252405Srpaulo */ 648252405Srpaulo rssi = URTWN_RSSI(rssi); 649251538Srpaulo } 650251538Srpaulo 651260463Skevlo m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 652251538Srpaulo if (m == NULL) { 653251538Srpaulo device_printf(sc->sc_dev, "could not create RX mbuf\n"); 654251538Srpaulo return (NULL); 655251538Srpaulo } 656251538Srpaulo 657251538Srpaulo /* Finalize mbuf. */ 658251538Srpaulo wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 659251538Srpaulo memcpy(mtod(m, uint8_t *), wh, pktlen); 660251538Srpaulo m->m_pkthdr.len = m->m_len = pktlen; 661251538Srpaulo 662251538Srpaulo if (ieee80211_radiotap_active(ic)) { 663251538Srpaulo struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 664251538Srpaulo 665251538Srpaulo tap->wr_flags = 0; 666251538Srpaulo /* Map HW rate index to 802.11 rate. */ 667251538Srpaulo if (!(rxdw3 & R92C_RXDW3_HT)) { 668289758Savos tap->wr_rate = ridx2rate[rate]; 669251538Srpaulo } else if (rate >= 12) { /* MCS0~15. */ 670251538Srpaulo /* Bit 7 set means HT MCS instead of rate. */ 671251538Srpaulo tap->wr_rate = 0x80 | (rate - 12); 672251538Srpaulo } 673251538Srpaulo tap->wr_dbm_antsignal = rssi; 674251538Srpaulo tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 675251538Srpaulo tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 676251538Srpaulo } 677251538Srpaulo 678251538Srpaulo *rssi_p = rssi; 679251538Srpaulo 680251538Srpaulo return (m); 681251538Srpaulo} 682251538Srpaulo 683251538Srpaulostatic struct mbuf * 684251538Srpaulourtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 685251538Srpaulo int8_t *nf) 686251538Srpaulo{ 687251538Srpaulo struct urtwn_softc *sc = data->sc; 688287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 689251538Srpaulo struct r92c_rx_stat *stat; 690251538Srpaulo struct mbuf *m, *m0 = NULL, *prevm = NULL; 691251538Srpaulo uint32_t rxdw0; 692251538Srpaulo uint8_t *buf; 693251538Srpaulo int len, totlen, pktlen, infosz, npkts; 694251538Srpaulo 695251538Srpaulo usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 696251538Srpaulo 697251538Srpaulo if (len < sizeof(*stat)) { 698287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 699251538Srpaulo return (NULL); 700251538Srpaulo } 701251538Srpaulo 702251538Srpaulo buf = data->buf; 703251538Srpaulo /* Get the number of encapsulated frames. */ 704251538Srpaulo stat = (struct r92c_rx_stat *)buf; 705251538Srpaulo npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 706251538Srpaulo DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 707251538Srpaulo 708251538Srpaulo /* Process all of them. */ 709251538Srpaulo while (npkts-- > 0) { 710251538Srpaulo if (len < sizeof(*stat)) 711251538Srpaulo break; 712251538Srpaulo stat = (struct r92c_rx_stat *)buf; 713251538Srpaulo rxdw0 = le32toh(stat->rxdw0); 714251538Srpaulo 715251538Srpaulo pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 716251538Srpaulo if (pktlen == 0) 717251538Srpaulo break; 718251538Srpaulo 719251538Srpaulo infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 720251538Srpaulo 721251538Srpaulo /* Make sure everything fits in xfer. */ 722251538Srpaulo totlen = sizeof(*stat) + infosz + pktlen; 723251538Srpaulo if (totlen > len) 724251538Srpaulo break; 725251538Srpaulo 726251538Srpaulo m = urtwn_rx_frame(sc, buf, pktlen, rssi); 727251538Srpaulo if (m0 == NULL) 728251538Srpaulo m0 = m; 729251538Srpaulo if (prevm == NULL) 730251538Srpaulo prevm = m; 731251538Srpaulo else { 732251538Srpaulo prevm->m_next = m; 733251538Srpaulo prevm = m; 734251538Srpaulo } 735251538Srpaulo 736251538Srpaulo /* Next chunk is 128-byte aligned. */ 737251538Srpaulo totlen = (totlen + 127) & ~127; 738251538Srpaulo buf += totlen; 739251538Srpaulo len -= totlen; 740251538Srpaulo } 741251538Srpaulo 742251538Srpaulo return (m0); 743251538Srpaulo} 744251538Srpaulo 745251538Srpaulostatic void 746251538Srpaulourtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 747251538Srpaulo{ 748251538Srpaulo struct urtwn_softc *sc = usbd_xfer_softc(xfer); 749287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 750251538Srpaulo struct ieee80211_frame *wh; 751251538Srpaulo struct ieee80211_node *ni; 752251538Srpaulo struct mbuf *m = NULL, *next; 753251538Srpaulo struct urtwn_data *data; 754251538Srpaulo int8_t nf; 755251538Srpaulo int rssi = 1; 756251538Srpaulo 757251538Srpaulo URTWN_ASSERT_LOCKED(sc); 758251538Srpaulo 759251538Srpaulo switch (USB_GET_STATE(xfer)) { 760251538Srpaulo case USB_ST_TRANSFERRED: 761251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_active); 762251538Srpaulo if (data == NULL) 763251538Srpaulo goto tr_setup; 764251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 765251538Srpaulo m = urtwn_rxeof(xfer, data, &rssi, &nf); 766251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 767251538Srpaulo /* FALLTHROUGH */ 768251538Srpaulo case USB_ST_SETUP: 769251538Srpaulotr_setup: 770251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_inactive); 771251538Srpaulo if (data == NULL) { 772251538Srpaulo KASSERT(m == NULL, ("mbuf isn't NULL")); 773251538Srpaulo return; 774251538Srpaulo } 775251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 776251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 777251538Srpaulo usbd_xfer_set_frame_data(xfer, 0, data->buf, 778251538Srpaulo usbd_xfer_max_len(xfer)); 779251538Srpaulo usbd_transfer_submit(xfer); 780251538Srpaulo 781251538Srpaulo /* 782251538Srpaulo * To avoid LOR we should unlock our private mutex here to call 783251538Srpaulo * ieee80211_input() because here is at the end of a USB 784251538Srpaulo * callback and safe to unlock. 785251538Srpaulo */ 786251538Srpaulo URTWN_UNLOCK(sc); 787251538Srpaulo while (m != NULL) { 788251538Srpaulo next = m->m_next; 789251538Srpaulo m->m_next = NULL; 790251538Srpaulo wh = mtod(m, struct ieee80211_frame *); 791251538Srpaulo ni = ieee80211_find_rxnode(ic, 792251538Srpaulo (struct ieee80211_frame_min *)wh); 793251538Srpaulo nf = URTWN_NOISE_FLOOR; 794251538Srpaulo if (ni != NULL) { 795251538Srpaulo (void)ieee80211_input(ni, m, rssi, nf); 796251538Srpaulo ieee80211_free_node(ni); 797251538Srpaulo } else 798251538Srpaulo (void)ieee80211_input_all(ic, m, rssi, nf); 799251538Srpaulo m = next; 800251538Srpaulo } 801251538Srpaulo URTWN_LOCK(sc); 802251538Srpaulo break; 803251538Srpaulo default: 804251538Srpaulo /* needs it to the inactive queue due to a error. */ 805251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_active); 806251538Srpaulo if (data != NULL) { 807251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 808251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 809251538Srpaulo } 810251538Srpaulo if (error != USB_ERR_CANCELLED) { 811251538Srpaulo usbd_xfer_set_stall(xfer); 812287197Sglebius counter_u64_add(ic->ic_ierrors, 1); 813251538Srpaulo goto tr_setup; 814251538Srpaulo } 815251538Srpaulo break; 816251538Srpaulo } 817251538Srpaulo} 818251538Srpaulo 819251538Srpaulostatic void 820251538Srpaulourtwn_txeof(struct usb_xfer *xfer, struct urtwn_data *data) 821251538Srpaulo{ 822251538Srpaulo struct urtwn_softc *sc = usbd_xfer_softc(xfer); 823251538Srpaulo 824251538Srpaulo URTWN_ASSERT_LOCKED(sc); 825287197Sglebius /* XXX status? */ 826287197Sglebius ieee80211_tx_complete(data->ni, data->m, 0); 827287197Sglebius data->ni = NULL; 828287197Sglebius data->m = NULL; 829251538Srpaulo sc->sc_txtimer = 0; 830251538Srpaulo} 831251538Srpaulo 832289066Skevlostatic int 833289066Skevlourtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 834289066Skevlo int ndata, int maxsz) 835289066Skevlo{ 836289066Skevlo int i, error; 837289066Skevlo 838289066Skevlo for (i = 0; i < ndata; i++) { 839289066Skevlo struct urtwn_data *dp = &data[i]; 840289066Skevlo dp->sc = sc; 841289066Skevlo dp->m = NULL; 842289066Skevlo dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 843289066Skevlo if (dp->buf == NULL) { 844289066Skevlo device_printf(sc->sc_dev, 845289066Skevlo "could not allocate buffer\n"); 846289066Skevlo error = ENOMEM; 847289066Skevlo goto fail; 848289066Skevlo } 849289066Skevlo dp->ni = NULL; 850289066Skevlo } 851289066Skevlo 852289066Skevlo return (0); 853289066Skevlofail: 854289066Skevlo urtwn_free_list(sc, data, ndata); 855289066Skevlo return (error); 856289066Skevlo} 857289066Skevlo 858289066Skevlostatic int 859289066Skevlourtwn_alloc_rx_list(struct urtwn_softc *sc) 860289066Skevlo{ 861289066Skevlo int error, i; 862289066Skevlo 863289066Skevlo error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 864289066Skevlo URTWN_RXBUFSZ); 865289066Skevlo if (error != 0) 866289066Skevlo return (error); 867289066Skevlo 868289066Skevlo STAILQ_INIT(&sc->sc_rx_active); 869289066Skevlo STAILQ_INIT(&sc->sc_rx_inactive); 870289066Skevlo 871289066Skevlo for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 872289066Skevlo STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 873289066Skevlo 874289066Skevlo return (0); 875289066Skevlo} 876289066Skevlo 877289066Skevlostatic int 878289066Skevlourtwn_alloc_tx_list(struct urtwn_softc *sc) 879289066Skevlo{ 880289066Skevlo int error, i; 881289066Skevlo 882289066Skevlo error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 883289066Skevlo URTWN_TXBUFSZ); 884289066Skevlo if (error != 0) 885289066Skevlo return (error); 886289066Skevlo 887289066Skevlo STAILQ_INIT(&sc->sc_tx_active); 888289066Skevlo STAILQ_INIT(&sc->sc_tx_inactive); 889289066Skevlo STAILQ_INIT(&sc->sc_tx_pending); 890289066Skevlo 891289066Skevlo for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 892289066Skevlo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 893289066Skevlo 894289066Skevlo return (0); 895289066Skevlo} 896289066Skevlo 897251538Srpaulostatic void 898289066Skevlourtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 899289066Skevlo{ 900289066Skevlo int i; 901289066Skevlo 902289066Skevlo for (i = 0; i < ndata; i++) { 903289066Skevlo struct urtwn_data *dp = &data[i]; 904289066Skevlo 905289066Skevlo if (dp->buf != NULL) { 906289066Skevlo free(dp->buf, M_USBDEV); 907289066Skevlo dp->buf = NULL; 908289066Skevlo } 909289066Skevlo if (dp->ni != NULL) { 910289066Skevlo ieee80211_free_node(dp->ni); 911289066Skevlo dp->ni = NULL; 912289066Skevlo } 913289066Skevlo } 914289066Skevlo} 915289066Skevlo 916289066Skevlostatic void 917289066Skevlourtwn_free_rx_list(struct urtwn_softc *sc) 918289066Skevlo{ 919289066Skevlo urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 920289066Skevlo} 921289066Skevlo 922289066Skevlostatic void 923289066Skevlourtwn_free_tx_list(struct urtwn_softc *sc) 924289066Skevlo{ 925289066Skevlo urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 926289066Skevlo} 927289066Skevlo 928289066Skevlostatic void 929251538Srpaulourtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 930251538Srpaulo{ 931251538Srpaulo struct urtwn_softc *sc = usbd_xfer_softc(xfer); 932251538Srpaulo struct urtwn_data *data; 933251538Srpaulo 934251538Srpaulo URTWN_ASSERT_LOCKED(sc); 935251538Srpaulo 936251538Srpaulo switch (USB_GET_STATE(xfer)){ 937251538Srpaulo case USB_ST_TRANSFERRED: 938251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_active); 939251538Srpaulo if (data == NULL) 940251538Srpaulo goto tr_setup; 941251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 942251538Srpaulo urtwn_txeof(xfer, data); 943251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 944251538Srpaulo /* FALLTHROUGH */ 945251538Srpaulo case USB_ST_SETUP: 946251538Srpaulotr_setup: 947251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_pending); 948251538Srpaulo if (data == NULL) { 949251538Srpaulo DPRINTF("%s: empty pending queue\n", __func__); 950288353Sadrian goto finish; 951251538Srpaulo } 952251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 953251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 954251538Srpaulo usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 955251538Srpaulo usbd_transfer_submit(xfer); 956251538Srpaulo break; 957251538Srpaulo default: 958251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_active); 959251538Srpaulo if (data == NULL) 960251538Srpaulo goto tr_setup; 961251538Srpaulo if (data->ni != NULL) { 962287197Sglebius if_inc_counter(data->ni->ni_vap->iv_ifp, 963287197Sglebius IFCOUNTER_OERRORS, 1); 964251538Srpaulo ieee80211_free_node(data->ni); 965251538Srpaulo data->ni = NULL; 966251538Srpaulo } 967251538Srpaulo if (error != USB_ERR_CANCELLED) { 968251538Srpaulo usbd_xfer_set_stall(xfer); 969251538Srpaulo goto tr_setup; 970251538Srpaulo } 971251538Srpaulo break; 972251538Srpaulo } 973288353Sadrianfinish: 974288353Sadrian /* Kick-start more transmit */ 975288353Sadrian urtwn_start(sc); 976251538Srpaulo} 977251538Srpaulo 978251538Srpaulostatic struct urtwn_data * 979251538Srpaulo_urtwn_getbuf(struct urtwn_softc *sc) 980251538Srpaulo{ 981251538Srpaulo struct urtwn_data *bf; 982251538Srpaulo 983251538Srpaulo bf = STAILQ_FIRST(&sc->sc_tx_inactive); 984251538Srpaulo if (bf != NULL) 985251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 986251538Srpaulo else 987251538Srpaulo bf = NULL; 988251538Srpaulo if (bf == NULL) 989251538Srpaulo DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 990251538Srpaulo return (bf); 991251538Srpaulo} 992251538Srpaulo 993251538Srpaulostatic struct urtwn_data * 994251538Srpaulourtwn_getbuf(struct urtwn_softc *sc) 995251538Srpaulo{ 996251538Srpaulo struct urtwn_data *bf; 997251538Srpaulo 998251538Srpaulo URTWN_ASSERT_LOCKED(sc); 999251538Srpaulo 1000251538Srpaulo bf = _urtwn_getbuf(sc); 1001287197Sglebius if (bf == NULL) 1002251538Srpaulo DPRINTF("%s: stop queue\n", __func__); 1003251538Srpaulo return (bf); 1004251538Srpaulo} 1005251538Srpaulo 1006251538Srpaulostatic int 1007251538Srpaulourtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1008251538Srpaulo int len) 1009251538Srpaulo{ 1010251538Srpaulo usb_device_request_t req; 1011251538Srpaulo 1012251538Srpaulo req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1013251538Srpaulo req.bRequest = R92C_REQ_REGS; 1014251538Srpaulo USETW(req.wValue, addr); 1015251538Srpaulo USETW(req.wIndex, 0); 1016251538Srpaulo USETW(req.wLength, len); 1017251538Srpaulo return (urtwn_do_request(sc, &req, buf)); 1018251538Srpaulo} 1019251538Srpaulo 1020251538Srpaulostatic void 1021251538Srpaulourtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1022251538Srpaulo{ 1023251538Srpaulo urtwn_write_region_1(sc, addr, &val, 1); 1024251538Srpaulo} 1025251538Srpaulo 1026251538Srpaulo 1027251538Srpaulostatic void 1028251538Srpaulourtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1029251538Srpaulo{ 1030251538Srpaulo val = htole16(val); 1031251538Srpaulo urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 1032251538Srpaulo} 1033251538Srpaulo 1034251538Srpaulostatic void 1035251538Srpaulourtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1036251538Srpaulo{ 1037251538Srpaulo val = htole32(val); 1038251538Srpaulo urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 1039251538Srpaulo} 1040251538Srpaulo 1041251538Srpaulostatic int 1042251538Srpaulourtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1043251538Srpaulo int len) 1044251538Srpaulo{ 1045251538Srpaulo usb_device_request_t req; 1046251538Srpaulo 1047251538Srpaulo req.bmRequestType = UT_READ_VENDOR_DEVICE; 1048251538Srpaulo req.bRequest = R92C_REQ_REGS; 1049251538Srpaulo USETW(req.wValue, addr); 1050251538Srpaulo USETW(req.wIndex, 0); 1051251538Srpaulo USETW(req.wLength, len); 1052251538Srpaulo return (urtwn_do_request(sc, &req, buf)); 1053251538Srpaulo} 1054251538Srpaulo 1055251538Srpaulostatic uint8_t 1056251538Srpaulourtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1057251538Srpaulo{ 1058251538Srpaulo uint8_t val; 1059251538Srpaulo 1060251538Srpaulo if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1061251538Srpaulo return (0xff); 1062251538Srpaulo return (val); 1063251538Srpaulo} 1064251538Srpaulo 1065251538Srpaulostatic uint16_t 1066251538Srpaulourtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1067251538Srpaulo{ 1068251538Srpaulo uint16_t val; 1069251538Srpaulo 1070251538Srpaulo if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1071251538Srpaulo return (0xffff); 1072251538Srpaulo return (le16toh(val)); 1073251538Srpaulo} 1074251538Srpaulo 1075251538Srpaulostatic uint32_t 1076251538Srpaulourtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1077251538Srpaulo{ 1078251538Srpaulo uint32_t val; 1079251538Srpaulo 1080251538Srpaulo if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1081251538Srpaulo return (0xffffffff); 1082251538Srpaulo return (le32toh(val)); 1083251538Srpaulo} 1084251538Srpaulo 1085251538Srpaulostatic int 1086251538Srpaulourtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1087251538Srpaulo{ 1088251538Srpaulo struct r92c_fw_cmd cmd; 1089251538Srpaulo int ntries; 1090251538Srpaulo 1091251538Srpaulo /* Wait for current FW box to be empty. */ 1092251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 1093251538Srpaulo if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1094251538Srpaulo break; 1095266472Shselasky urtwn_ms_delay(sc); 1096251538Srpaulo } 1097251538Srpaulo if (ntries == 100) { 1098251538Srpaulo device_printf(sc->sc_dev, 1099251538Srpaulo "could not send firmware command\n"); 1100251538Srpaulo return (ETIMEDOUT); 1101251538Srpaulo } 1102251538Srpaulo memset(&cmd, 0, sizeof(cmd)); 1103251538Srpaulo cmd.id = id; 1104251538Srpaulo if (len > 3) 1105251538Srpaulo cmd.id |= R92C_CMD_FLAG_EXT; 1106251538Srpaulo KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1107251538Srpaulo memcpy(cmd.msg, buf, len); 1108251538Srpaulo 1109251538Srpaulo /* Write the first word last since that will trigger the FW. */ 1110251538Srpaulo urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1111251538Srpaulo (uint8_t *)&cmd + 4, 2); 1112251538Srpaulo urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1113251538Srpaulo (uint8_t *)&cmd + 0, 4); 1114251538Srpaulo 1115251538Srpaulo sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1116251538Srpaulo return (0); 1117251538Srpaulo} 1118251538Srpaulo 1119264912Skevlostatic __inline void 1120251538Srpaulourtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1121251538Srpaulo{ 1122264912Skevlo 1123264912Skevlo sc->sc_rf_write(sc, chain, addr, val); 1124264912Skevlo} 1125264912Skevlo 1126264912Skevlostatic void 1127264912Skevlourtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1128264912Skevlo uint32_t val) 1129264912Skevlo{ 1130251538Srpaulo urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1131251538Srpaulo SM(R92C_LSSI_PARAM_ADDR, addr) | 1132251538Srpaulo SM(R92C_LSSI_PARAM_DATA, val)); 1133251538Srpaulo} 1134251538Srpaulo 1135264912Skevlostatic void 1136264912Skevlourtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1137264912Skevlouint32_t val) 1138264912Skevlo{ 1139264912Skevlo urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1140264912Skevlo SM(R88E_LSSI_PARAM_ADDR, addr) | 1141264912Skevlo SM(R92C_LSSI_PARAM_DATA, val)); 1142264912Skevlo} 1143264912Skevlo 1144251538Srpaulostatic uint32_t 1145251538Srpaulourtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1146251538Srpaulo{ 1147251538Srpaulo uint32_t reg[R92C_MAX_CHAINS], val; 1148251538Srpaulo 1149251538Srpaulo reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1150251538Srpaulo if (chain != 0) 1151251538Srpaulo reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1152251538Srpaulo 1153251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1154251538Srpaulo reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1155266472Shselasky urtwn_ms_delay(sc); 1156251538Srpaulo 1157251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1158251538Srpaulo RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1159251538Srpaulo R92C_HSSI_PARAM2_READ_EDGE); 1160266472Shselasky urtwn_ms_delay(sc); 1161251538Srpaulo 1162251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1163251538Srpaulo reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1164266472Shselasky urtwn_ms_delay(sc); 1165251538Srpaulo 1166251538Srpaulo if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1167251538Srpaulo val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1168251538Srpaulo else 1169251538Srpaulo val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1170251538Srpaulo return (MS(val, R92C_LSSI_READBACK_DATA)); 1171251538Srpaulo} 1172251538Srpaulo 1173251538Srpaulostatic int 1174251538Srpaulourtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1175251538Srpaulo{ 1176251538Srpaulo int ntries; 1177251538Srpaulo 1178251538Srpaulo urtwn_write_4(sc, R92C_LLT_INIT, 1179251538Srpaulo SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1180251538Srpaulo SM(R92C_LLT_INIT_ADDR, addr) | 1181251538Srpaulo SM(R92C_LLT_INIT_DATA, data)); 1182251538Srpaulo /* Wait for write operation to complete. */ 1183251538Srpaulo for (ntries = 0; ntries < 20; ntries++) { 1184251538Srpaulo if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1185251538Srpaulo R92C_LLT_INIT_OP_NO_ACTIVE) 1186251538Srpaulo return (0); 1187266472Shselasky urtwn_ms_delay(sc); 1188251538Srpaulo } 1189251538Srpaulo return (ETIMEDOUT); 1190251538Srpaulo} 1191251538Srpaulo 1192251538Srpaulostatic uint8_t 1193251538Srpaulourtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1194251538Srpaulo{ 1195251538Srpaulo uint32_t reg; 1196251538Srpaulo int ntries; 1197251538Srpaulo 1198251538Srpaulo reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1199251538Srpaulo reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1200251538Srpaulo reg &= ~R92C_EFUSE_CTRL_VALID; 1201251538Srpaulo urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1202251538Srpaulo /* Wait for read operation to complete. */ 1203251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 1204251538Srpaulo reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1205251538Srpaulo if (reg & R92C_EFUSE_CTRL_VALID) 1206251538Srpaulo return (MS(reg, R92C_EFUSE_CTRL_DATA)); 1207266472Shselasky urtwn_ms_delay(sc); 1208251538Srpaulo } 1209281069Srpaulo device_printf(sc->sc_dev, 1210251538Srpaulo "could not read efuse byte at address 0x%x\n", addr); 1211251538Srpaulo return (0xff); 1212251538Srpaulo} 1213251538Srpaulo 1214251538Srpaulostatic void 1215251538Srpaulourtwn_efuse_read(struct urtwn_softc *sc) 1216251538Srpaulo{ 1217251538Srpaulo uint8_t *rom = (uint8_t *)&sc->rom; 1218251538Srpaulo uint16_t addr = 0; 1219251538Srpaulo uint32_t reg; 1220282623Skevlo uint8_t off, msk; 1221251538Srpaulo int i; 1222251538Srpaulo 1223264912Skevlo urtwn_efuse_switch_power(sc); 1224264912Skevlo 1225251538Srpaulo memset(&sc->rom, 0xff, sizeof(sc->rom)); 1226251538Srpaulo while (addr < 512) { 1227251538Srpaulo reg = urtwn_efuse_read_1(sc, addr); 1228251538Srpaulo if (reg == 0xff) 1229251538Srpaulo break; 1230251538Srpaulo addr++; 1231251538Srpaulo off = reg >> 4; 1232251538Srpaulo msk = reg & 0xf; 1233251538Srpaulo for (i = 0; i < 4; i++) { 1234251538Srpaulo if (msk & (1 << i)) 1235251538Srpaulo continue; 1236251538Srpaulo rom[off * 8 + i * 2 + 0] = 1237251538Srpaulo urtwn_efuse_read_1(sc, addr); 1238251538Srpaulo addr++; 1239251538Srpaulo rom[off * 8 + i * 2 + 1] = 1240251538Srpaulo urtwn_efuse_read_1(sc, addr); 1241251538Srpaulo addr++; 1242251538Srpaulo } 1243251538Srpaulo } 1244251538Srpaulo#ifdef URTWN_DEBUG 1245251538Srpaulo if (urtwn_debug >= 2) { 1246251538Srpaulo /* Dump ROM content. */ 1247251538Srpaulo printf("\n"); 1248251538Srpaulo for (i = 0; i < sizeof(sc->rom); i++) 1249251538Srpaulo printf("%02x:", rom[i]); 1250251538Srpaulo printf("\n"); 1251251538Srpaulo } 1252251538Srpaulo#endif 1253282623Skevlo urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1254282623Skevlo} 1255281592Skevlo 1256264912Skevlostatic void 1257264912Skevlourtwn_efuse_switch_power(struct urtwn_softc *sc) 1258264912Skevlo{ 1259264912Skevlo uint32_t reg; 1260251538Srpaulo 1261282623Skevlo urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1262281918Skevlo 1263264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1264264912Skevlo if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1265264912Skevlo urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1266264912Skevlo reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1267264912Skevlo } 1268264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1269264912Skevlo if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1270264912Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1271264912Skevlo reg | R92C_SYS_FUNC_EN_ELDR); 1272264912Skevlo } 1273264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1274264912Skevlo if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1275264912Skevlo (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1276264912Skevlo urtwn_write_2(sc, R92C_SYS_CLKR, 1277264912Skevlo reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1278264912Skevlo } 1279264912Skevlo} 1280264912Skevlo 1281251538Srpaulostatic int 1282251538Srpaulourtwn_read_chipid(struct urtwn_softc *sc) 1283251538Srpaulo{ 1284251538Srpaulo uint32_t reg; 1285251538Srpaulo 1286264912Skevlo if (sc->chip & URTWN_CHIP_88E) 1287264912Skevlo return (0); 1288264912Skevlo 1289251538Srpaulo reg = urtwn_read_4(sc, R92C_SYS_CFG); 1290251538Srpaulo if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1291251538Srpaulo return (EIO); 1292251538Srpaulo 1293251538Srpaulo if (reg & R92C_SYS_CFG_TYPE_92C) { 1294251538Srpaulo sc->chip |= URTWN_CHIP_92C; 1295251538Srpaulo /* Check if it is a castrated 8192C. */ 1296251538Srpaulo if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1297251538Srpaulo R92C_HPON_FSM_CHIP_BONDING_ID) == 1298251538Srpaulo R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1299251538Srpaulo sc->chip |= URTWN_CHIP_92C_1T2R; 1300251538Srpaulo } 1301251538Srpaulo if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1302251538Srpaulo sc->chip |= URTWN_CHIP_UMC; 1303251538Srpaulo if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1304251538Srpaulo sc->chip |= URTWN_CHIP_UMC_A_CUT; 1305251538Srpaulo } 1306251538Srpaulo return (0); 1307251538Srpaulo} 1308251538Srpaulo 1309251538Srpaulostatic void 1310251538Srpaulourtwn_read_rom(struct urtwn_softc *sc) 1311251538Srpaulo{ 1312251538Srpaulo struct r92c_rom *rom = &sc->rom; 1313251538Srpaulo 1314251538Srpaulo /* Read full ROM image. */ 1315251538Srpaulo urtwn_efuse_read(sc); 1316251538Srpaulo 1317251538Srpaulo /* XXX Weird but this is what the vendor driver does. */ 1318251538Srpaulo sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1319251538Srpaulo DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1320251538Srpaulo 1321251538Srpaulo sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1322251538Srpaulo 1323251538Srpaulo sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1324251538Srpaulo DPRINTF("regulatory type=%d\n", sc->regulatory); 1325287197Sglebius IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1326251538Srpaulo 1327264912Skevlo sc->sc_rf_write = urtwn_r92c_rf_write; 1328264912Skevlo sc->sc_power_on = urtwn_r92c_power_on; 1329264912Skevlo sc->sc_dma_init = urtwn_r92c_dma_init; 1330251538Srpaulo} 1331251538Srpaulo 1332264912Skevlostatic void 1333264912Skevlourtwn_r88e_read_rom(struct urtwn_softc *sc) 1334264912Skevlo{ 1335264912Skevlo uint8_t *rom = sc->r88e_rom; 1336264912Skevlo uint16_t addr = 0; 1337264912Skevlo uint32_t reg; 1338264912Skevlo uint8_t off, msk, tmp; 1339264912Skevlo int i; 1340264912Skevlo 1341264982Sandreast off = 0; 1342264912Skevlo urtwn_efuse_switch_power(sc); 1343264912Skevlo 1344264912Skevlo /* Read full ROM image. */ 1345264912Skevlo memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1346281918Skevlo while (addr < 512) { 1347264912Skevlo reg = urtwn_efuse_read_1(sc, addr); 1348264912Skevlo if (reg == 0xff) 1349264912Skevlo break; 1350264912Skevlo addr++; 1351264912Skevlo if ((reg & 0x1f) == 0x0f) { 1352264912Skevlo tmp = (reg & 0xe0) >> 5; 1353264912Skevlo reg = urtwn_efuse_read_1(sc, addr); 1354264912Skevlo if ((reg & 0x0f) != 0x0f) 1355264912Skevlo off = ((reg & 0xf0) >> 1) | tmp; 1356264912Skevlo addr++; 1357264912Skevlo } else 1358264912Skevlo off = reg >> 4; 1359264912Skevlo msk = reg & 0xf; 1360264912Skevlo for (i = 0; i < 4; i++) { 1361264912Skevlo if (msk & (1 << i)) 1362264912Skevlo continue; 1363264912Skevlo rom[off * 8 + i * 2 + 0] = 1364264912Skevlo urtwn_efuse_read_1(sc, addr); 1365264912Skevlo addr++; 1366264912Skevlo rom[off * 8 + i * 2 + 1] = 1367264912Skevlo urtwn_efuse_read_1(sc, addr); 1368264912Skevlo addr++; 1369264912Skevlo } 1370264912Skevlo } 1371264912Skevlo 1372281918Skevlo urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1373281918Skevlo 1374264912Skevlo addr = 0x10; 1375264912Skevlo for (i = 0; i < 6; i++) 1376264912Skevlo sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1377264912Skevlo for (i = 0; i < 5; i++) 1378264912Skevlo sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1379264912Skevlo sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1380264912Skevlo if (sc->bw20_tx_pwr_diff & 0x08) 1381264912Skevlo sc->bw20_tx_pwr_diff |= 0xf0; 1382264912Skevlo sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1383264912Skevlo if (sc->ofdm_tx_pwr_diff & 0x08) 1384264912Skevlo sc->ofdm_tx_pwr_diff |= 0xf0; 1385264912Skevlo sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1386287197Sglebius IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, &sc->r88e_rom[0xd7]); 1387264912Skevlo 1388264912Skevlo sc->sc_rf_write = urtwn_r88e_rf_write; 1389264912Skevlo sc->sc_power_on = urtwn_r88e_power_on; 1390264912Skevlo sc->sc_dma_init = urtwn_r88e_dma_init; 1391264912Skevlo} 1392264912Skevlo 1393251538Srpaulo/* 1394251538Srpaulo * Initialize rate adaptation in firmware. 1395251538Srpaulo */ 1396251538Srpaulostatic int 1397251538Srpaulourtwn_ra_init(struct urtwn_softc *sc) 1398251538Srpaulo{ 1399287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 1400251538Srpaulo struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1401251538Srpaulo struct ieee80211_node *ni; 1402251538Srpaulo struct ieee80211_rateset *rs; 1403251538Srpaulo struct r92c_fw_cmd_macid_cfg cmd; 1404251538Srpaulo uint32_t rates, basicrates; 1405251538Srpaulo uint8_t mode; 1406251538Srpaulo int maxrate, maxbasicrate, error, i, j; 1407251538Srpaulo 1408251538Srpaulo ni = ieee80211_ref_node(vap->iv_bss); 1409251538Srpaulo rs = &ni->ni_rates; 1410251538Srpaulo 1411251538Srpaulo /* Get normal and basic rates mask. */ 1412251538Srpaulo rates = basicrates = 0; 1413251538Srpaulo maxrate = maxbasicrate = 0; 1414251538Srpaulo for (i = 0; i < rs->rs_nrates; i++) { 1415251538Srpaulo /* Convert 802.11 rate to HW rate index. */ 1416289758Savos for (j = 0; j < nitems(ridx2rate); j++) 1417289758Savos if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == 1418289758Savos ridx2rate[j]) 1419251538Srpaulo break; 1420289758Savos if (j == nitems(ridx2rate)) /* Unknown rate, skip. */ 1421251538Srpaulo continue; 1422251538Srpaulo rates |= 1 << j; 1423251538Srpaulo if (j > maxrate) 1424251538Srpaulo maxrate = j; 1425251538Srpaulo if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1426251538Srpaulo basicrates |= 1 << j; 1427251538Srpaulo if (j > maxbasicrate) 1428251538Srpaulo maxbasicrate = j; 1429251538Srpaulo } 1430251538Srpaulo } 1431251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1432251538Srpaulo mode = R92C_RAID_11B; 1433251538Srpaulo else 1434251538Srpaulo mode = R92C_RAID_11BG; 1435251538Srpaulo DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1436251538Srpaulo mode, rates, basicrates); 1437251538Srpaulo 1438251538Srpaulo /* Set rates mask for group addressed frames. */ 1439251538Srpaulo cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1440251538Srpaulo cmd.mask = htole32(mode << 28 | basicrates); 1441251538Srpaulo error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1442251538Srpaulo if (error != 0) { 1443252401Srpaulo ieee80211_free_node(ni); 1444251538Srpaulo device_printf(sc->sc_dev, 1445251538Srpaulo "could not add broadcast station\n"); 1446251538Srpaulo return (error); 1447251538Srpaulo } 1448251538Srpaulo /* Set initial MRR rate. */ 1449251538Srpaulo DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1450251538Srpaulo urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1451251538Srpaulo maxbasicrate); 1452251538Srpaulo 1453251538Srpaulo /* Set rates mask for unicast frames. */ 1454251538Srpaulo cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1455251538Srpaulo cmd.mask = htole32(mode << 28 | rates); 1456251538Srpaulo error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1457251538Srpaulo if (error != 0) { 1458252401Srpaulo ieee80211_free_node(ni); 1459251538Srpaulo device_printf(sc->sc_dev, "could not add BSS station\n"); 1460251538Srpaulo return (error); 1461251538Srpaulo } 1462251538Srpaulo /* Set initial MRR rate. */ 1463251538Srpaulo DPRINTF("maxrate=%d\n", maxrate); 1464251538Srpaulo urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1465251538Srpaulo maxrate); 1466251538Srpaulo 1467251538Srpaulo /* Indicate highest supported rate. */ 1468252403Srpaulo ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1469252401Srpaulo ieee80211_free_node(ni); 1470252401Srpaulo 1471251538Srpaulo return (0); 1472251538Srpaulo} 1473251538Srpaulo 1474251538Srpaulovoid 1475251538Srpaulourtwn_tsf_sync_enable(struct urtwn_softc *sc) 1476251538Srpaulo{ 1477287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 1478251538Srpaulo struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1479251538Srpaulo struct ieee80211_node *ni = vap->iv_bss; 1480251538Srpaulo 1481251538Srpaulo uint64_t tsf; 1482251538Srpaulo 1483251538Srpaulo /* Enable TSF synchronization. */ 1484251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1485251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1486251538Srpaulo 1487251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1488251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1489251538Srpaulo 1490251538Srpaulo /* Set initial TSF. */ 1491251538Srpaulo memcpy(&tsf, ni->ni_tstamp.data, 8); 1492251538Srpaulo tsf = le64toh(tsf); 1493251538Srpaulo tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU)); 1494251538Srpaulo tsf -= IEEE80211_DUR_TU; 1495251538Srpaulo urtwn_write_4(sc, R92C_TSFTR + 0, tsf); 1496251538Srpaulo urtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32); 1497251538Srpaulo 1498251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1499251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1500251538Srpaulo} 1501251538Srpaulo 1502251538Srpaulostatic void 1503251538Srpaulourtwn_set_led(struct urtwn_softc *sc, int led, int on) 1504251538Srpaulo{ 1505251538Srpaulo uint8_t reg; 1506281069Srpaulo 1507251538Srpaulo if (led == URTWN_LED_LINK) { 1508264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 1509264912Skevlo reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1510264912Skevlo urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1511264912Skevlo if (!on) { 1512264912Skevlo reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1513264912Skevlo urtwn_write_1(sc, R92C_LEDCFG2, 1514264912Skevlo reg | R92C_LEDCFG0_DIS); 1515264912Skevlo urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1516264912Skevlo urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 1517264912Skevlo 0xfe); 1518264912Skevlo } 1519264912Skevlo } else { 1520264912Skevlo reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1521264912Skevlo if (!on) 1522264912Skevlo reg |= R92C_LEDCFG0_DIS; 1523264912Skevlo urtwn_write_1(sc, R92C_LEDCFG0, reg); 1524264912Skevlo } 1525264912Skevlo sc->ledlink = on; /* Save LED state. */ 1526251538Srpaulo } 1527251538Srpaulo} 1528251538Srpaulo 1529251538Srpaulostatic int 1530251538Srpaulourtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1531251538Srpaulo{ 1532251538Srpaulo struct urtwn_vap *uvp = URTWN_VAP(vap); 1533251538Srpaulo struct ieee80211com *ic = vap->iv_ic; 1534286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 1535251538Srpaulo struct ieee80211_node *ni; 1536251538Srpaulo enum ieee80211_state ostate; 1537251538Srpaulo uint32_t reg; 1538251538Srpaulo 1539251538Srpaulo ostate = vap->iv_state; 1540251538Srpaulo DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 1541251538Srpaulo ieee80211_state_name[nstate]); 1542251538Srpaulo 1543251538Srpaulo IEEE80211_UNLOCK(ic); 1544251538Srpaulo URTWN_LOCK(sc); 1545251538Srpaulo callout_stop(&sc->sc_watchdog_ch); 1546251538Srpaulo 1547251538Srpaulo if (ostate == IEEE80211_S_RUN) { 1548251538Srpaulo /* Turn link LED off. */ 1549251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 0); 1550251538Srpaulo 1551251538Srpaulo /* Set media status to 'No Link'. */ 1552251538Srpaulo reg = urtwn_read_4(sc, R92C_CR); 1553251538Srpaulo reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK); 1554251538Srpaulo urtwn_write_4(sc, R92C_CR, reg); 1555251538Srpaulo 1556251538Srpaulo /* Stop Rx of data frames. */ 1557251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1558251538Srpaulo 1559251538Srpaulo /* Rest TSF. */ 1560251538Srpaulo urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1561251538Srpaulo 1562251538Srpaulo /* Disable TSF synchronization. */ 1563251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1564251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) | 1565251538Srpaulo R92C_BCN_CTRL_DIS_TSF_UDT0); 1566251538Srpaulo 1567251538Srpaulo /* Reset EDCA parameters. */ 1568251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1569251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1570251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1571251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1572251538Srpaulo } 1573251538Srpaulo 1574251538Srpaulo switch (nstate) { 1575251538Srpaulo case IEEE80211_S_INIT: 1576251538Srpaulo /* Turn link LED off. */ 1577251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 0); 1578251538Srpaulo break; 1579251538Srpaulo case IEEE80211_S_SCAN: 1580251538Srpaulo if (ostate != IEEE80211_S_SCAN) { 1581251538Srpaulo /* Allow Rx from any BSSID. */ 1582251538Srpaulo urtwn_write_4(sc, R92C_RCR, 1583251538Srpaulo urtwn_read_4(sc, R92C_RCR) & 1584251538Srpaulo ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1585251538Srpaulo 1586251538Srpaulo /* Set gain for scanning. */ 1587251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1588251538Srpaulo reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1589251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1590251538Srpaulo 1591264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 1592264912Skevlo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1593264912Skevlo reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1594264912Skevlo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1595264912Skevlo } 1596251538Srpaulo } 1597251538Srpaulo /* Pause AC Tx queues. */ 1598251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 1599251538Srpaulo urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1600251538Srpaulo break; 1601251538Srpaulo case IEEE80211_S_AUTH: 1602251538Srpaulo /* Set initial gain under link. */ 1603251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1604251538Srpaulo reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1605251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1606251538Srpaulo 1607264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 1608264912Skevlo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1609264912Skevlo reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1610264912Skevlo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1611264912Skevlo } 1612251538Srpaulo urtwn_set_chan(sc, ic->ic_curchan, NULL); 1613251538Srpaulo break; 1614251538Srpaulo case IEEE80211_S_RUN: 1615251538Srpaulo if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1616251538Srpaulo /* Enable Rx of data frames. */ 1617251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1618251538Srpaulo 1619289173Skevlo /* Enable Rx of ctrl frames. */ 1620289173Skevlo urtwn_write_2(sc, R92C_RXFLTMAP1, 0xffff); 1621289173Skevlo 1622289173Skevlo /* 1623289173Skevlo * Accept data/control/management frames 1624289173Skevlo * from any BSSID. 1625289173Skevlo */ 1626289173Skevlo urtwn_write_4(sc, R92C_RCR, 1627289173Skevlo (urtwn_read_4(sc, R92C_RCR) & ~(R92C_RCR_APM | 1628289173Skevlo R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)) | 1629289173Skevlo R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF | 1630289173Skevlo R92C_RCR_AAP); 1631289173Skevlo 1632251538Srpaulo /* Turn link LED on. */ 1633251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 1); 1634251538Srpaulo break; 1635251538Srpaulo } 1636251538Srpaulo 1637251538Srpaulo ni = ieee80211_ref_node(vap->iv_bss); 1638251538Srpaulo /* Set media status to 'Associated'. */ 1639251538Srpaulo reg = urtwn_read_4(sc, R92C_CR); 1640251538Srpaulo reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 1641251538Srpaulo urtwn_write_4(sc, R92C_CR, reg); 1642251538Srpaulo 1643251538Srpaulo /* Set BSSID. */ 1644251538Srpaulo urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1645251538Srpaulo urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1646251538Srpaulo 1647251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1648251538Srpaulo urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1649251538Srpaulo else /* 802.11b/g */ 1650251538Srpaulo urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1651251538Srpaulo 1652251538Srpaulo /* Enable Rx of data frames. */ 1653251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1654251538Srpaulo 1655251538Srpaulo /* Flush all AC queues. */ 1656251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0); 1657251538Srpaulo 1658251538Srpaulo /* Set beacon interval. */ 1659251538Srpaulo urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1660251538Srpaulo 1661251538Srpaulo /* Allow Rx from our BSSID only. */ 1662251538Srpaulo urtwn_write_4(sc, R92C_RCR, 1663251538Srpaulo urtwn_read_4(sc, R92C_RCR) | 1664251538Srpaulo R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1665251538Srpaulo 1666251538Srpaulo /* Enable TSF synchronization. */ 1667251538Srpaulo urtwn_tsf_sync_enable(sc); 1668251538Srpaulo 1669251538Srpaulo urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1670251538Srpaulo urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1671251538Srpaulo urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1672251538Srpaulo urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1673251538Srpaulo urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1674251538Srpaulo urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1675251538Srpaulo 1676251538Srpaulo /* Intialize rate adaptation. */ 1677264912Skevlo if (sc->chip & URTWN_CHIP_88E) 1678264912Skevlo ni->ni_txrate = 1679264912Skevlo ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1]; 1680281069Srpaulo else 1681264912Skevlo urtwn_ra_init(sc); 1682251538Srpaulo /* Turn link LED on. */ 1683251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 1); 1684251538Srpaulo 1685251538Srpaulo sc->avg_pwdb = -1; /* Reset average RSSI. */ 1686251538Srpaulo /* Reset temperature calibration state machine. */ 1687251538Srpaulo sc->thcal_state = 0; 1688251538Srpaulo sc->thcal_lctemp = 0; 1689251538Srpaulo ieee80211_free_node(ni); 1690251538Srpaulo break; 1691251538Srpaulo default: 1692251538Srpaulo break; 1693251538Srpaulo } 1694251538Srpaulo URTWN_UNLOCK(sc); 1695251538Srpaulo IEEE80211_LOCK(ic); 1696251538Srpaulo return(uvp->newstate(vap, nstate, arg)); 1697251538Srpaulo} 1698251538Srpaulo 1699251538Srpaulostatic void 1700251538Srpaulourtwn_watchdog(void *arg) 1701251538Srpaulo{ 1702251538Srpaulo struct urtwn_softc *sc = arg; 1703251538Srpaulo 1704251538Srpaulo if (sc->sc_txtimer > 0) { 1705251538Srpaulo if (--sc->sc_txtimer == 0) { 1706251538Srpaulo device_printf(sc->sc_dev, "device timeout\n"); 1707287197Sglebius counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1708251538Srpaulo return; 1709251538Srpaulo } 1710251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1711251538Srpaulo } 1712251538Srpaulo} 1713251538Srpaulo 1714251538Srpaulostatic void 1715251538Srpaulourtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1716251538Srpaulo{ 1717251538Srpaulo int pwdb; 1718251538Srpaulo 1719251538Srpaulo /* Convert antenna signal to percentage. */ 1720251538Srpaulo if (rssi <= -100 || rssi >= 20) 1721251538Srpaulo pwdb = 0; 1722251538Srpaulo else if (rssi >= 0) 1723251538Srpaulo pwdb = 100; 1724251538Srpaulo else 1725251538Srpaulo pwdb = 100 + rssi; 1726264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 1727289758Savos if (rate <= URTWN_RIDX_CCK11) { 1728264912Skevlo /* CCK gain is smaller than OFDM/MCS gain. */ 1729264912Skevlo pwdb += 6; 1730264912Skevlo if (pwdb > 100) 1731264912Skevlo pwdb = 100; 1732264912Skevlo if (pwdb <= 14) 1733264912Skevlo pwdb -= 4; 1734264912Skevlo else if (pwdb <= 26) 1735264912Skevlo pwdb -= 8; 1736264912Skevlo else if (pwdb <= 34) 1737264912Skevlo pwdb -= 6; 1738264912Skevlo else if (pwdb <= 42) 1739264912Skevlo pwdb -= 2; 1740264912Skevlo } 1741251538Srpaulo } 1742251538Srpaulo if (sc->avg_pwdb == -1) /* Init. */ 1743251538Srpaulo sc->avg_pwdb = pwdb; 1744251538Srpaulo else if (sc->avg_pwdb < pwdb) 1745251538Srpaulo sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1746251538Srpaulo else 1747251538Srpaulo sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1748251538Srpaulo DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 1749251538Srpaulo} 1750251538Srpaulo 1751251538Srpaulostatic int8_t 1752251538Srpaulourtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1753251538Srpaulo{ 1754251538Srpaulo static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1755251538Srpaulo struct r92c_rx_phystat *phy; 1756251538Srpaulo struct r92c_rx_cck *cck; 1757251538Srpaulo uint8_t rpt; 1758251538Srpaulo int8_t rssi; 1759251538Srpaulo 1760289758Savos if (rate <= URTWN_RIDX_CCK11) { 1761251538Srpaulo cck = (struct r92c_rx_cck *)physt; 1762251538Srpaulo if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 1763251538Srpaulo rpt = (cck->agc_rpt >> 5) & 0x3; 1764251538Srpaulo rssi = (cck->agc_rpt & 0x1f) << 1; 1765251538Srpaulo } else { 1766251538Srpaulo rpt = (cck->agc_rpt >> 6) & 0x3; 1767251538Srpaulo rssi = cck->agc_rpt & 0x3e; 1768251538Srpaulo } 1769251538Srpaulo rssi = cckoff[rpt] - rssi; 1770251538Srpaulo } else { /* OFDM/HT. */ 1771251538Srpaulo phy = (struct r92c_rx_phystat *)physt; 1772251538Srpaulo rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1773251538Srpaulo } 1774251538Srpaulo return (rssi); 1775251538Srpaulo} 1776251538Srpaulo 1777264912Skevlostatic int8_t 1778264912Skevlourtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1779264912Skevlo{ 1780264912Skevlo struct r92c_rx_phystat *phy; 1781264912Skevlo struct r88e_rx_cck *cck; 1782264912Skevlo uint8_t cck_agc_rpt, lna_idx, vga_idx; 1783264912Skevlo int8_t rssi; 1784264912Skevlo 1785264972Skevlo rssi = 0; 1786289758Savos if (rate <= URTWN_RIDX_CCK11) { 1787264912Skevlo cck = (struct r88e_rx_cck *)physt; 1788264912Skevlo cck_agc_rpt = cck->agc_rpt; 1789264912Skevlo lna_idx = (cck_agc_rpt & 0xe0) >> 5; 1790281069Srpaulo vga_idx = cck_agc_rpt & 0x1f; 1791264912Skevlo switch (lna_idx) { 1792264912Skevlo case 7: 1793264912Skevlo if (vga_idx <= 27) 1794264912Skevlo rssi = -100 + 2* (27 - vga_idx); 1795264912Skevlo else 1796264912Skevlo rssi = -100; 1797264912Skevlo break; 1798264912Skevlo case 6: 1799264912Skevlo rssi = -48 + 2 * (2 - vga_idx); 1800264912Skevlo break; 1801264912Skevlo case 5: 1802264912Skevlo rssi = -42 + 2 * (7 - vga_idx); 1803264912Skevlo break; 1804264912Skevlo case 4: 1805264912Skevlo rssi = -36 + 2 * (7 - vga_idx); 1806264912Skevlo break; 1807264912Skevlo case 3: 1808264912Skevlo rssi = -24 + 2 * (7 - vga_idx); 1809264912Skevlo break; 1810264912Skevlo case 2: 1811264912Skevlo rssi = -12 + 2 * (5 - vga_idx); 1812264912Skevlo break; 1813264912Skevlo case 1: 1814264912Skevlo rssi = 8 - (2 * vga_idx); 1815264912Skevlo break; 1816264912Skevlo case 0: 1817264912Skevlo rssi = 14 - (2 * vga_idx); 1818264912Skevlo break; 1819264912Skevlo } 1820264912Skevlo rssi += 6; 1821264912Skevlo } else { /* OFDM/HT. */ 1822264912Skevlo phy = (struct r92c_rx_phystat *)physt; 1823264912Skevlo rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1824264912Skevlo } 1825264912Skevlo return (rssi); 1826264912Skevlo} 1827264912Skevlo 1828251538Srpaulostatic int 1829281069Srpaulourtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni, 1830251538Srpaulo struct mbuf *m0, struct urtwn_data *data) 1831251538Srpaulo{ 1832251538Srpaulo struct ieee80211_frame *wh; 1833251538Srpaulo struct ieee80211_key *k; 1834287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 1835251538Srpaulo struct ieee80211vap *vap = ni->ni_vap; 1836251538Srpaulo struct usb_xfer *xfer; 1837251538Srpaulo struct r92c_tx_desc *txd; 1838251538Srpaulo uint8_t raid, type; 1839251538Srpaulo uint16_t sum; 1840288534Sadrian int i, xferlen; 1841251538Srpaulo struct usb_xfer *urtwn_pipes[4] = { 1842251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_BE], 1843251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_BK], 1844251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_VI], 1845251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_VO] 1846251538Srpaulo }; 1847251538Srpaulo 1848251538Srpaulo URTWN_ASSERT_LOCKED(sc); 1849251538Srpaulo 1850251538Srpaulo /* 1851251538Srpaulo * Software crypto. 1852251538Srpaulo */ 1853251538Srpaulo wh = mtod(m0, struct ieee80211_frame *); 1854264912Skevlo type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1855264912Skevlo 1856260444Skevlo if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1857251538Srpaulo k = ieee80211_crypto_encap(ni, m0); 1858251538Srpaulo if (k == NULL) { 1859251538Srpaulo device_printf(sc->sc_dev, 1860251538Srpaulo "ieee80211_crypto_encap returns NULL.\n"); 1861251538Srpaulo /* XXX we don't expect the fragmented frames */ 1862251538Srpaulo return (ENOBUFS); 1863251538Srpaulo } 1864251538Srpaulo 1865251538Srpaulo /* in case packet header moved, reset pointer */ 1866251538Srpaulo wh = mtod(m0, struct ieee80211_frame *); 1867251538Srpaulo } 1868281069Srpaulo 1869264912Skevlo switch (type) { 1870251538Srpaulo case IEEE80211_FC0_TYPE_CTL: 1871251538Srpaulo case IEEE80211_FC0_TYPE_MGT: 1872251538Srpaulo xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 1873251538Srpaulo break; 1874251538Srpaulo default: 1875251538Srpaulo KASSERT(M_WME_GETAC(m0) < 4, 1876251538Srpaulo ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1877251538Srpaulo xfer = urtwn_pipes[M_WME_GETAC(m0)]; 1878251538Srpaulo break; 1879251538Srpaulo } 1880281069Srpaulo 1881251538Srpaulo /* Fill Tx descriptor. */ 1882251538Srpaulo txd = (struct r92c_tx_desc *)data->buf; 1883251538Srpaulo memset(txd, 0, sizeof(*txd)); 1884251538Srpaulo 1885251538Srpaulo txd->txdw0 |= htole32( 1886251538Srpaulo SM(R92C_TXDW0_PKTLEN, m0->m_pkthdr.len) | 1887251538Srpaulo SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1888251538Srpaulo R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1889251538Srpaulo if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1890251538Srpaulo txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1891251538Srpaulo if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1892251538Srpaulo type == IEEE80211_FC0_TYPE_DATA) { 1893251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1894251538Srpaulo raid = R92C_RAID_11B; 1895251538Srpaulo else 1896251538Srpaulo raid = R92C_RAID_11BG; 1897264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 1898264912Skevlo txd->txdw1 |= htole32( 1899264912Skevlo SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) | 1900264912Skevlo SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1901264912Skevlo SM(R92C_TXDW1_RAID, raid)); 1902264912Skevlo txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1903264912Skevlo } else { 1904264912Skevlo txd->txdw1 |= htole32( 1905264912Skevlo SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 1906264912Skevlo SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1907264912Skevlo SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1908264912Skevlo } 1909251538Srpaulo if (ic->ic_flags & IEEE80211_F_USEPROT) { 1910251538Srpaulo if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1911251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1912251538Srpaulo R92C_TXDW4_HWRTSEN); 1913251538Srpaulo } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1914251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1915251538Srpaulo R92C_TXDW4_HWRTSEN); 1916251538Srpaulo } 1917251538Srpaulo } 1918251538Srpaulo /* Send RTS at OFDM24. */ 1919289758Savos txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 1920289758Savos URTWN_RIDX_OFDM24)); 1921251538Srpaulo txd->txdw5 |= htole32(0x0001ff00); 1922251538Srpaulo /* Send data at OFDM54. */ 1923289758Savos txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 1924289758Savos URTWN_RIDX_OFDM54)); 1925251538Srpaulo } else { 1926251538Srpaulo txd->txdw1 |= htole32( 1927251538Srpaulo SM(R92C_TXDW1_MACID, 0) | 1928251538Srpaulo SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1929251538Srpaulo SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1930251538Srpaulo 1931251538Srpaulo /* Force CCK1. */ 1932251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1933289758Savos txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 1934289758Savos URTWN_RIDX_CCK1)); 1935251538Srpaulo } 1936251538Srpaulo /* Set sequence number (already little endian). */ 1937251538Srpaulo txd->txdseq |= *(uint16_t *)wh->i_seq; 1938251538Srpaulo 1939288534Sadrian if (!IEEE80211_QOS_HAS_SEQ(wh)) { 1940251538Srpaulo /* Use HW sequence numbering for non-QoS frames. */ 1941251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1942251538Srpaulo txd->txdseq |= htole16(0x8000); 1943251538Srpaulo } else 1944251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1945251538Srpaulo 1946251538Srpaulo /* Compute Tx descriptor checksum. */ 1947251538Srpaulo sum = 0; 1948251538Srpaulo for (i = 0; i < sizeof(*txd) / 2; i++) 1949251538Srpaulo sum ^= ((uint16_t *)txd)[i]; 1950251538Srpaulo txd->txdsum = sum; /* NB: already little endian. */ 1951251538Srpaulo 1952251538Srpaulo if (ieee80211_radiotap_active_vap(vap)) { 1953251538Srpaulo struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1954251538Srpaulo 1955251538Srpaulo tap->wt_flags = 0; 1956251538Srpaulo tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1957251538Srpaulo tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1958251538Srpaulo ieee80211_radiotap_tx(vap, m0); 1959251538Srpaulo } 1960251538Srpaulo 1961251538Srpaulo xferlen = sizeof(*txd) + m0->m_pkthdr.len; 1962251538Srpaulo m_copydata(m0, 0, m0->m_pkthdr.len, (caddr_t)&txd[1]); 1963251538Srpaulo 1964251538Srpaulo data->buflen = xferlen; 1965251538Srpaulo data->ni = ni; 1966251538Srpaulo data->m = m0; 1967251538Srpaulo 1968251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1969251538Srpaulo usbd_transfer_start(xfer); 1970251538Srpaulo return (0); 1971251538Srpaulo} 1972251538Srpaulo 1973287197Sglebiusstatic int 1974287197Sglebiusurtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 1975251538Srpaulo{ 1976287197Sglebius struct urtwn_softc *sc = ic->ic_softc; 1977287197Sglebius int error; 1978261863Srpaulo 1979261863Srpaulo URTWN_LOCK(sc); 1980287197Sglebius if ((sc->sc_flags & URTWN_RUNNING) == 0) { 1981287197Sglebius URTWN_UNLOCK(sc); 1982287197Sglebius return (ENXIO); 1983287197Sglebius } 1984287197Sglebius error = mbufq_enqueue(&sc->sc_snd, m); 1985287197Sglebius if (error) { 1986287197Sglebius URTWN_UNLOCK(sc); 1987287197Sglebius return (error); 1988287197Sglebius } 1989287197Sglebius urtwn_start(sc); 1990261863Srpaulo URTWN_UNLOCK(sc); 1991287197Sglebius 1992287197Sglebius return (0); 1993261863Srpaulo} 1994261863Srpaulo 1995261863Srpaulostatic void 1996287197Sglebiusurtwn_start(struct urtwn_softc *sc) 1997261863Srpaulo{ 1998251538Srpaulo struct ieee80211_node *ni; 1999251538Srpaulo struct mbuf *m; 2000251538Srpaulo struct urtwn_data *bf; 2001251538Srpaulo 2002261863Srpaulo URTWN_ASSERT_LOCKED(sc); 2003287197Sglebius while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 2004251538Srpaulo bf = urtwn_getbuf(sc); 2005251538Srpaulo if (bf == NULL) { 2006287197Sglebius mbufq_prepend(&sc->sc_snd, m); 2007251538Srpaulo break; 2008251538Srpaulo } 2009251538Srpaulo ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 2010251538Srpaulo m->m_pkthdr.rcvif = NULL; 2011251538Srpaulo if (urtwn_tx_start(sc, ni, m, bf) != 0) { 2012287197Sglebius if_inc_counter(ni->ni_vap->iv_ifp, 2013287197Sglebius IFCOUNTER_OERRORS, 1); 2014251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 2015288353Sadrian m_freem(m); 2016251538Srpaulo ieee80211_free_node(ni); 2017251538Srpaulo break; 2018251538Srpaulo } 2019251538Srpaulo sc->sc_txtimer = 5; 2020251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2021251538Srpaulo } 2022251538Srpaulo} 2023251538Srpaulo 2024287197Sglebiusstatic void 2025287197Sglebiusurtwn_parent(struct ieee80211com *ic) 2026251538Srpaulo{ 2027286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 2028287197Sglebius int startall = 0; 2029251538Srpaulo 2030263153Skevlo URTWN_LOCK(sc); 2031287197Sglebius if (sc->sc_flags & URTWN_DETACHED) { 2032287197Sglebius URTWN_UNLOCK(sc); 2033287197Sglebius return; 2034287197Sglebius } 2035287197Sglebius if (ic->ic_nrunning > 0) { 2036287197Sglebius if ((sc->sc_flags & URTWN_RUNNING) == 0) { 2037287197Sglebius urtwn_init(sc); 2038287197Sglebius startall = 1; 2039287197Sglebius } 2040287197Sglebius } else if (sc->sc_flags & URTWN_RUNNING) 2041287197Sglebius urtwn_stop(sc); 2042263153Skevlo URTWN_UNLOCK(sc); 2043263153Skevlo 2044287197Sglebius if (startall) 2045287197Sglebius ieee80211_start_all(ic); 2046251538Srpaulo} 2047251538Srpaulo 2048264912Skevlostatic __inline int 2049251538Srpaulourtwn_power_on(struct urtwn_softc *sc) 2050251538Srpaulo{ 2051264912Skevlo 2052264912Skevlo return sc->sc_power_on(sc); 2053264912Skevlo} 2054264912Skevlo 2055264912Skevlostatic int 2056264912Skevlourtwn_r92c_power_on(struct urtwn_softc *sc) 2057264912Skevlo{ 2058251538Srpaulo uint32_t reg; 2059251538Srpaulo int ntries; 2060251538Srpaulo 2061251538Srpaulo /* Wait for autoload done bit. */ 2062251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2063251538Srpaulo if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2064251538Srpaulo break; 2065266472Shselasky urtwn_ms_delay(sc); 2066251538Srpaulo } 2067251538Srpaulo if (ntries == 1000) { 2068251538Srpaulo device_printf(sc->sc_dev, 2069251538Srpaulo "timeout waiting for chip autoload\n"); 2070251538Srpaulo return (ETIMEDOUT); 2071251538Srpaulo } 2072251538Srpaulo 2073251538Srpaulo /* Unlock ISO/CLK/Power control register. */ 2074251538Srpaulo urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2075251538Srpaulo /* Move SPS into PWM mode. */ 2076251538Srpaulo urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2077266472Shselasky urtwn_ms_delay(sc); 2078251538Srpaulo 2079251538Srpaulo reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2080251538Srpaulo if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2081251538Srpaulo urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2082251538Srpaulo reg | R92C_LDOV12D_CTRL_LDV12_EN); 2083266472Shselasky urtwn_ms_delay(sc); 2084251538Srpaulo urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2085251538Srpaulo urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2086251538Srpaulo ~R92C_SYS_ISO_CTRL_MD2PP); 2087251538Srpaulo } 2088251538Srpaulo 2089251538Srpaulo /* Auto enable WLAN. */ 2090251538Srpaulo urtwn_write_2(sc, R92C_APS_FSMCO, 2091251538Srpaulo urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2092251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2093262822Skevlo if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2094262822Skevlo R92C_APS_FSMCO_APFM_ONMAC)) 2095251538Srpaulo break; 2096266472Shselasky urtwn_ms_delay(sc); 2097251538Srpaulo } 2098251538Srpaulo if (ntries == 1000) { 2099251538Srpaulo device_printf(sc->sc_dev, 2100251538Srpaulo "timeout waiting for MAC auto ON\n"); 2101251538Srpaulo return (ETIMEDOUT); 2102251538Srpaulo } 2103251538Srpaulo 2104251538Srpaulo /* Enable radio, GPIO and LED functions. */ 2105251538Srpaulo urtwn_write_2(sc, R92C_APS_FSMCO, 2106251538Srpaulo R92C_APS_FSMCO_AFSM_HSUS | 2107251538Srpaulo R92C_APS_FSMCO_PDN_EN | 2108251538Srpaulo R92C_APS_FSMCO_PFM_ALDN); 2109251538Srpaulo /* Release RF digital isolation. */ 2110251538Srpaulo urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2111251538Srpaulo urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2112251538Srpaulo 2113251538Srpaulo /* Initialize MAC. */ 2114251538Srpaulo urtwn_write_1(sc, R92C_APSD_CTRL, 2115251538Srpaulo urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2116251538Srpaulo for (ntries = 0; ntries < 200; ntries++) { 2117251538Srpaulo if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2118251538Srpaulo R92C_APSD_CTRL_OFF_STATUS)) 2119251538Srpaulo break; 2120266472Shselasky urtwn_ms_delay(sc); 2121251538Srpaulo } 2122251538Srpaulo if (ntries == 200) { 2123251538Srpaulo device_printf(sc->sc_dev, 2124251538Srpaulo "timeout waiting for MAC initialization\n"); 2125251538Srpaulo return (ETIMEDOUT); 2126251538Srpaulo } 2127251538Srpaulo 2128251538Srpaulo /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2129251538Srpaulo reg = urtwn_read_2(sc, R92C_CR); 2130251538Srpaulo reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2131251538Srpaulo R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2132251538Srpaulo R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2133251538Srpaulo R92C_CR_ENSEC; 2134251538Srpaulo urtwn_write_2(sc, R92C_CR, reg); 2135251538Srpaulo 2136251538Srpaulo urtwn_write_1(sc, 0xfe10, 0x19); 2137251538Srpaulo return (0); 2138251538Srpaulo} 2139251538Srpaulo 2140251538Srpaulostatic int 2141264912Skevlourtwn_r88e_power_on(struct urtwn_softc *sc) 2142264912Skevlo{ 2143264912Skevlo uint32_t reg; 2144264912Skevlo int ntries; 2145264912Skevlo 2146264912Skevlo /* Wait for power ready bit. */ 2147264912Skevlo for (ntries = 0; ntries < 5000; ntries++) { 2148281918Skevlo if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 2149264912Skevlo break; 2150266472Shselasky urtwn_ms_delay(sc); 2151264912Skevlo } 2152264912Skevlo if (ntries == 5000) { 2153264912Skevlo device_printf(sc->sc_dev, 2154264912Skevlo "timeout waiting for chip power up\n"); 2155264912Skevlo return (ETIMEDOUT); 2156264912Skevlo } 2157264912Skevlo 2158264912Skevlo /* Reset BB. */ 2159264912Skevlo urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2160264912Skevlo urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2161264912Skevlo R92C_SYS_FUNC_EN_BB_GLB_RST)); 2162264912Skevlo 2163281918Skevlo urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 2164281918Skevlo urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 2165264912Skevlo 2166264912Skevlo /* Disable HWPDN. */ 2167281918Skevlo urtwn_write_2(sc, R92C_APS_FSMCO, 2168281918Skevlo urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 2169264912Skevlo 2170264912Skevlo /* Disable WL suspend. */ 2171281918Skevlo urtwn_write_2(sc, R92C_APS_FSMCO, 2172281918Skevlo urtwn_read_2(sc, R92C_APS_FSMCO) & 2173281918Skevlo ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 2174264912Skevlo 2175281918Skevlo urtwn_write_2(sc, R92C_APS_FSMCO, 2176281918Skevlo urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2177264912Skevlo for (ntries = 0; ntries < 5000; ntries++) { 2178281918Skevlo if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2179281918Skevlo R92C_APS_FSMCO_APFM_ONMAC)) 2180264912Skevlo break; 2181266472Shselasky urtwn_ms_delay(sc); 2182264912Skevlo } 2183264912Skevlo if (ntries == 5000) 2184264912Skevlo return (ETIMEDOUT); 2185264912Skevlo 2186264912Skevlo /* Enable LDO normal mode. */ 2187281918Skevlo urtwn_write_1(sc, R92C_LPLDO_CTRL, 2188281918Skevlo urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 2189264912Skevlo 2190264912Skevlo /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2191264912Skevlo urtwn_write_2(sc, R92C_CR, 0); 2192264912Skevlo reg = urtwn_read_2(sc, R92C_CR); 2193264912Skevlo reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2194264912Skevlo R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2195264912Skevlo R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2196264912Skevlo urtwn_write_2(sc, R92C_CR, reg); 2197264912Skevlo 2198264912Skevlo return (0); 2199264912Skevlo} 2200264912Skevlo 2201264912Skevlostatic int 2202251538Srpaulourtwn_llt_init(struct urtwn_softc *sc) 2203251538Srpaulo{ 2204264912Skevlo int i, error, page_count, pktbuf_count; 2205251538Srpaulo 2206264912Skevlo page_count = (sc->chip & URTWN_CHIP_88E) ? 2207264912Skevlo R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 2208264912Skevlo pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 2209264912Skevlo R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2210264912Skevlo 2211264912Skevlo /* Reserve pages [0; page_count]. */ 2212264912Skevlo for (i = 0; i < page_count; i++) { 2213251538Srpaulo if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2214251538Srpaulo return (error); 2215251538Srpaulo } 2216251538Srpaulo /* NB: 0xff indicates end-of-list. */ 2217251538Srpaulo if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2218251538Srpaulo return (error); 2219251538Srpaulo /* 2220264912Skevlo * Use pages [page_count + 1; pktbuf_count - 1] 2221251538Srpaulo * as ring buffer. 2222251538Srpaulo */ 2223264912Skevlo for (++i; i < pktbuf_count - 1; i++) { 2224251538Srpaulo if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2225251538Srpaulo return (error); 2226251538Srpaulo } 2227251538Srpaulo /* Make the last page point to the beginning of the ring buffer. */ 2228264912Skevlo error = urtwn_llt_write(sc, i, page_count + 1); 2229251538Srpaulo return (error); 2230251538Srpaulo} 2231251538Srpaulo 2232251538Srpaulostatic void 2233251538Srpaulourtwn_fw_reset(struct urtwn_softc *sc) 2234251538Srpaulo{ 2235251538Srpaulo uint16_t reg; 2236251538Srpaulo int ntries; 2237251538Srpaulo 2238251538Srpaulo /* Tell 8051 to reset itself. */ 2239251538Srpaulo urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2240251538Srpaulo 2241251538Srpaulo /* Wait until 8051 resets by itself. */ 2242251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 2243251538Srpaulo reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2244251538Srpaulo if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2245251538Srpaulo return; 2246266472Shselasky urtwn_ms_delay(sc); 2247251538Srpaulo } 2248251538Srpaulo /* Force 8051 reset. */ 2249251538Srpaulo urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2250251538Srpaulo} 2251251538Srpaulo 2252264912Skevlostatic void 2253264912Skevlourtwn_r88e_fw_reset(struct urtwn_softc *sc) 2254264912Skevlo{ 2255264912Skevlo uint16_t reg; 2256264912Skevlo 2257264912Skevlo reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2258264912Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2259264912Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 2260264912Skevlo} 2261264912Skevlo 2262251538Srpaulostatic int 2263251538Srpaulourtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 2264251538Srpaulo{ 2265251538Srpaulo uint32_t reg; 2266251538Srpaulo int off, mlen, error = 0; 2267251538Srpaulo 2268251538Srpaulo reg = urtwn_read_4(sc, R92C_MCUFWDL); 2269251538Srpaulo reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2270251538Srpaulo urtwn_write_4(sc, R92C_MCUFWDL, reg); 2271251538Srpaulo 2272251538Srpaulo off = R92C_FW_START_ADDR; 2273251538Srpaulo while (len > 0) { 2274251538Srpaulo if (len > 196) 2275251538Srpaulo mlen = 196; 2276251538Srpaulo else if (len > 4) 2277251538Srpaulo mlen = 4; 2278251538Srpaulo else 2279251538Srpaulo mlen = 1; 2280251538Srpaulo /* XXX fix this deconst */ 2281281069Srpaulo error = urtwn_write_region_1(sc, off, 2282251538Srpaulo __DECONST(uint8_t *, buf), mlen); 2283251538Srpaulo if (error != 0) 2284251538Srpaulo break; 2285251538Srpaulo off += mlen; 2286251538Srpaulo buf += mlen; 2287251538Srpaulo len -= mlen; 2288251538Srpaulo } 2289251538Srpaulo return (error); 2290251538Srpaulo} 2291251538Srpaulo 2292251538Srpaulostatic int 2293251538Srpaulourtwn_load_firmware(struct urtwn_softc *sc) 2294251538Srpaulo{ 2295251538Srpaulo const struct firmware *fw; 2296251538Srpaulo const struct r92c_fw_hdr *hdr; 2297251538Srpaulo const char *imagename; 2298251538Srpaulo const u_char *ptr; 2299251538Srpaulo size_t len; 2300251538Srpaulo uint32_t reg; 2301251538Srpaulo int mlen, ntries, page, error; 2302251538Srpaulo 2303264864Skevlo URTWN_UNLOCK(sc); 2304251538Srpaulo /* Read firmware image from the filesystem. */ 2305264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2306264912Skevlo imagename = "urtwn-rtl8188eufw"; 2307264912Skevlo else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2308264912Skevlo URTWN_CHIP_UMC_A_CUT) 2309251538Srpaulo imagename = "urtwn-rtl8192cfwU"; 2310251538Srpaulo else 2311251538Srpaulo imagename = "urtwn-rtl8192cfwT"; 2312251538Srpaulo 2313251538Srpaulo fw = firmware_get(imagename); 2314264864Skevlo URTWN_LOCK(sc); 2315251538Srpaulo if (fw == NULL) { 2316251538Srpaulo device_printf(sc->sc_dev, 2317251538Srpaulo "failed loadfirmware of file %s\n", imagename); 2318251538Srpaulo return (ENOENT); 2319251538Srpaulo } 2320251538Srpaulo 2321251538Srpaulo len = fw->datasize; 2322251538Srpaulo 2323251538Srpaulo if (len < sizeof(*hdr)) { 2324251538Srpaulo device_printf(sc->sc_dev, "firmware too short\n"); 2325251538Srpaulo error = EINVAL; 2326251538Srpaulo goto fail; 2327251538Srpaulo } 2328251538Srpaulo ptr = fw->data; 2329251538Srpaulo hdr = (const struct r92c_fw_hdr *)ptr; 2330251538Srpaulo /* Check if there is a valid FW header and skip it. */ 2331251538Srpaulo if ((le16toh(hdr->signature) >> 4) == 0x88c || 2332264912Skevlo (le16toh(hdr->signature) >> 4) == 0x88e || 2333251538Srpaulo (le16toh(hdr->signature) >> 4) == 0x92c) { 2334251538Srpaulo DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 2335251538Srpaulo le16toh(hdr->version), le16toh(hdr->subversion), 2336251538Srpaulo hdr->month, hdr->date, hdr->hour, hdr->minute); 2337251538Srpaulo ptr += sizeof(*hdr); 2338251538Srpaulo len -= sizeof(*hdr); 2339251538Srpaulo } 2340251538Srpaulo 2341264912Skevlo if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 2342264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2343264912Skevlo urtwn_r88e_fw_reset(sc); 2344264912Skevlo else 2345264912Skevlo urtwn_fw_reset(sc); 2346251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 0); 2347251538Srpaulo } 2348264912Skevlo 2349268487Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 2350268487Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2351268487Skevlo urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2352268487Skevlo R92C_SYS_FUNC_EN_CPUEN); 2353268487Skevlo } 2354251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 2355251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2356251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL + 2, 2357251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2358251538Srpaulo 2359263154Skevlo /* Reset the FWDL checksum. */ 2360263154Skevlo urtwn_write_1(sc, R92C_MCUFWDL, 2361263154Skevlo urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2362263154Skevlo 2363251538Srpaulo for (page = 0; len > 0; page++) { 2364251538Srpaulo mlen = min(len, R92C_FW_PAGE_SIZE); 2365251538Srpaulo error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2366251538Srpaulo if (error != 0) { 2367251538Srpaulo device_printf(sc->sc_dev, 2368251538Srpaulo "could not load firmware page\n"); 2369251538Srpaulo goto fail; 2370251538Srpaulo } 2371251538Srpaulo ptr += mlen; 2372251538Srpaulo len -= mlen; 2373251538Srpaulo } 2374251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 2375251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2376251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2377251538Srpaulo 2378251538Srpaulo /* Wait for checksum report. */ 2379251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2380251538Srpaulo if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2381251538Srpaulo break; 2382266472Shselasky urtwn_ms_delay(sc); 2383251538Srpaulo } 2384251538Srpaulo if (ntries == 1000) { 2385251538Srpaulo device_printf(sc->sc_dev, 2386251538Srpaulo "timeout waiting for checksum report\n"); 2387251538Srpaulo error = ETIMEDOUT; 2388251538Srpaulo goto fail; 2389251538Srpaulo } 2390251538Srpaulo 2391251538Srpaulo reg = urtwn_read_4(sc, R92C_MCUFWDL); 2392251538Srpaulo reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2393251538Srpaulo urtwn_write_4(sc, R92C_MCUFWDL, reg); 2394264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2395264912Skevlo urtwn_r88e_fw_reset(sc); 2396251538Srpaulo /* Wait for firmware readiness. */ 2397251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2398251538Srpaulo if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2399251538Srpaulo break; 2400266472Shselasky urtwn_ms_delay(sc); 2401251538Srpaulo } 2402251538Srpaulo if (ntries == 1000) { 2403251538Srpaulo device_printf(sc->sc_dev, 2404251538Srpaulo "timeout waiting for firmware readiness\n"); 2405251538Srpaulo error = ETIMEDOUT; 2406251538Srpaulo goto fail; 2407251538Srpaulo } 2408251538Srpaulofail: 2409251538Srpaulo firmware_put(fw, FIRMWARE_UNLOAD); 2410251538Srpaulo return (error); 2411251538Srpaulo} 2412251538Srpaulo 2413264912Skevlostatic __inline int 2414251538Srpaulourtwn_dma_init(struct urtwn_softc *sc) 2415251538Srpaulo{ 2416281069Srpaulo 2417264912Skevlo return sc->sc_dma_init(sc); 2418264912Skevlo} 2419264912Skevlo 2420264912Skevlostatic int 2421264912Skevlourtwn_r92c_dma_init(struct urtwn_softc *sc) 2422264912Skevlo{ 2423251538Srpaulo int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2424251538Srpaulo uint32_t reg; 2425251538Srpaulo int error; 2426251538Srpaulo 2427251538Srpaulo /* Initialize LLT table. */ 2428251538Srpaulo error = urtwn_llt_init(sc); 2429251538Srpaulo if (error != 0) 2430251538Srpaulo return (error); 2431251538Srpaulo 2432251538Srpaulo /* Get Tx queues to USB endpoints mapping. */ 2433251538Srpaulo hashq = hasnq = haslq = 0; 2434251538Srpaulo reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2435251538Srpaulo DPRINTFN(2, "USB endpoints mapping 0x%x\n", reg); 2436251538Srpaulo if (MS(reg, R92C_USB_EP_HQ) != 0) 2437251538Srpaulo hashq = 1; 2438251538Srpaulo if (MS(reg, R92C_USB_EP_NQ) != 0) 2439251538Srpaulo hasnq = 1; 2440251538Srpaulo if (MS(reg, R92C_USB_EP_LQ) != 0) 2441251538Srpaulo haslq = 1; 2442251538Srpaulo nqueues = hashq + hasnq + haslq; 2443251538Srpaulo if (nqueues == 0) 2444251538Srpaulo return (EIO); 2445251538Srpaulo /* Get the number of pages for each queue. */ 2446251538Srpaulo nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2447251538Srpaulo /* The remaining pages are assigned to the high priority queue. */ 2448251538Srpaulo nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2449251538Srpaulo 2450251538Srpaulo /* Set number of pages for normal priority queue. */ 2451251538Srpaulo urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2452251538Srpaulo urtwn_write_4(sc, R92C_RQPN, 2453251538Srpaulo /* Set number of pages for public queue. */ 2454251538Srpaulo SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2455251538Srpaulo /* Set number of pages for high priority queue. */ 2456251538Srpaulo SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2457251538Srpaulo /* Set number of pages for low priority queue. */ 2458251538Srpaulo SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2459251538Srpaulo /* Load values. */ 2460251538Srpaulo R92C_RQPN_LD); 2461251538Srpaulo 2462251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2463251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2464251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2465251538Srpaulo urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2466251538Srpaulo urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2467251538Srpaulo 2468251538Srpaulo /* Set queue to USB pipe mapping. */ 2469251538Srpaulo reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2470251538Srpaulo reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2471251538Srpaulo if (nqueues == 1) { 2472251538Srpaulo if (hashq) 2473251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2474251538Srpaulo else if (hasnq) 2475251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2476251538Srpaulo else 2477251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2478251538Srpaulo } else if (nqueues == 2) { 2479251538Srpaulo /* All 2-endpoints configs have a high priority queue. */ 2480251538Srpaulo if (!hashq) 2481251538Srpaulo return (EIO); 2482251538Srpaulo if (hasnq) 2483251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2484251538Srpaulo else 2485251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2486251538Srpaulo } else 2487251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2488251538Srpaulo urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2489251538Srpaulo 2490251538Srpaulo /* Set Tx/Rx transfer page boundary. */ 2491251538Srpaulo urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2492251538Srpaulo 2493251538Srpaulo /* Set Tx/Rx transfer page size. */ 2494251538Srpaulo urtwn_write_1(sc, R92C_PBP, 2495251538Srpaulo SM(R92C_PBP_PSRX, R92C_PBP_128) | 2496251538Srpaulo SM(R92C_PBP_PSTX, R92C_PBP_128)); 2497251538Srpaulo return (0); 2498251538Srpaulo} 2499251538Srpaulo 2500264912Skevlostatic int 2501264912Skevlourtwn_r88e_dma_init(struct urtwn_softc *sc) 2502264912Skevlo{ 2503264912Skevlo struct usb_interface *iface; 2504264912Skevlo uint32_t reg; 2505264912Skevlo int nqueues; 2506264912Skevlo int error; 2507264912Skevlo 2508264912Skevlo /* Initialize LLT table. */ 2509264912Skevlo error = urtwn_llt_init(sc); 2510264912Skevlo if (error != 0) 2511264912Skevlo return (error); 2512264912Skevlo 2513264912Skevlo /* Get Tx queues to USB endpoints mapping. */ 2514264912Skevlo iface = usbd_get_iface(sc->sc_udev, 0); 2515264912Skevlo nqueues = iface->idesc->bNumEndpoints - 1; 2516264912Skevlo if (nqueues == 0) 2517264912Skevlo return (EIO); 2518264912Skevlo 2519264912Skevlo /* Set number of pages for normal priority queue. */ 2520264912Skevlo urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 2521264912Skevlo urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 2522264912Skevlo 2523264912Skevlo urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2524264912Skevlo urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2525264912Skevlo urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 2526264912Skevlo urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 2527264912Skevlo urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 2528264912Skevlo 2529264912Skevlo /* Set queue to USB pipe mapping. */ 2530264912Skevlo reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2531264912Skevlo reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2532264912Skevlo if (nqueues == 1) 2533264912Skevlo reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2534264912Skevlo else if (nqueues == 2) 2535264912Skevlo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2536264912Skevlo else 2537264912Skevlo reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2538264912Skevlo urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2539264912Skevlo 2540264912Skevlo /* Set Tx/Rx transfer page boundary. */ 2541264912Skevlo urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 2542264912Skevlo 2543264912Skevlo /* Set Tx/Rx transfer page size. */ 2544264912Skevlo urtwn_write_1(sc, R92C_PBP, 2545264912Skevlo SM(R92C_PBP_PSRX, R92C_PBP_128) | 2546264912Skevlo SM(R92C_PBP_PSTX, R92C_PBP_128)); 2547264912Skevlo 2548264912Skevlo return (0); 2549264912Skevlo} 2550264912Skevlo 2551251538Srpaulostatic void 2552251538Srpaulourtwn_mac_init(struct urtwn_softc *sc) 2553251538Srpaulo{ 2554251538Srpaulo int i; 2555251538Srpaulo 2556251538Srpaulo /* Write MAC initialization values. */ 2557264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 2558264912Skevlo for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2559264912Skevlo urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2560264912Skevlo rtl8188eu_mac[i].val); 2561264912Skevlo } 2562264912Skevlo urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2563264912Skevlo } else { 2564264912Skevlo for (i = 0; i < nitems(rtl8192cu_mac); i++) 2565264912Skevlo urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2566264912Skevlo rtl8192cu_mac[i].val); 2567264912Skevlo } 2568251538Srpaulo} 2569251538Srpaulo 2570251538Srpaulostatic void 2571251538Srpaulourtwn_bb_init(struct urtwn_softc *sc) 2572251538Srpaulo{ 2573251538Srpaulo const struct urtwn_bb_prog *prog; 2574251538Srpaulo uint32_t reg; 2575264912Skevlo uint8_t crystalcap; 2576251538Srpaulo int i; 2577251538Srpaulo 2578251538Srpaulo /* Enable BB and RF. */ 2579251538Srpaulo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2580251538Srpaulo urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2581251538Srpaulo R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2582251538Srpaulo R92C_SYS_FUNC_EN_DIO_RF); 2583251538Srpaulo 2584264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) 2585264912Skevlo urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2586251538Srpaulo 2587251538Srpaulo urtwn_write_1(sc, R92C_RF_CTRL, 2588251538Srpaulo R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2589251538Srpaulo urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2590251538Srpaulo R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2591251538Srpaulo R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2592251538Srpaulo 2593264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 2594264912Skevlo urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2595264912Skevlo urtwn_write_1(sc, 0x15, 0xe9); 2596264912Skevlo urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2597264912Skevlo } 2598251538Srpaulo 2599251538Srpaulo /* Select BB programming based on board type. */ 2600264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2601264912Skevlo prog = &rtl8188eu_bb_prog; 2602264912Skevlo else if (!(sc->chip & URTWN_CHIP_92C)) { 2603251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2604251538Srpaulo prog = &rtl8188ce_bb_prog; 2605251538Srpaulo else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2606251538Srpaulo prog = &rtl8188ru_bb_prog; 2607251538Srpaulo else 2608251538Srpaulo prog = &rtl8188cu_bb_prog; 2609251538Srpaulo } else { 2610251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2611251538Srpaulo prog = &rtl8192ce_bb_prog; 2612251538Srpaulo else 2613251538Srpaulo prog = &rtl8192cu_bb_prog; 2614251538Srpaulo } 2615251538Srpaulo /* Write BB initialization values. */ 2616251538Srpaulo for (i = 0; i < prog->count; i++) { 2617251538Srpaulo urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2618266472Shselasky urtwn_ms_delay(sc); 2619251538Srpaulo } 2620251538Srpaulo 2621251538Srpaulo if (sc->chip & URTWN_CHIP_92C_1T2R) { 2622251538Srpaulo /* 8192C 1T only configuration. */ 2623251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2624251538Srpaulo reg = (reg & ~0x00000003) | 0x2; 2625251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2626251538Srpaulo 2627251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2628251538Srpaulo reg = (reg & ~0x00300033) | 0x00200022; 2629251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2630251538Srpaulo 2631251538Srpaulo reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2632251538Srpaulo reg = (reg & ~0xff000000) | 0x45 << 24; 2633251538Srpaulo urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2634251538Srpaulo 2635251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2636251538Srpaulo reg = (reg & ~0x000000ff) | 0x23; 2637251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2638251538Srpaulo 2639251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2640251538Srpaulo reg = (reg & ~0x00000030) | 1 << 4; 2641251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2642251538Srpaulo 2643251538Srpaulo reg = urtwn_bb_read(sc, 0xe74); 2644251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2645251538Srpaulo urtwn_bb_write(sc, 0xe74, reg); 2646251538Srpaulo reg = urtwn_bb_read(sc, 0xe78); 2647251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2648251538Srpaulo urtwn_bb_write(sc, 0xe78, reg); 2649251538Srpaulo reg = urtwn_bb_read(sc, 0xe7c); 2650251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2651251538Srpaulo urtwn_bb_write(sc, 0xe7c, reg); 2652251538Srpaulo reg = urtwn_bb_read(sc, 0xe80); 2653251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2654251538Srpaulo urtwn_bb_write(sc, 0xe80, reg); 2655251538Srpaulo reg = urtwn_bb_read(sc, 0xe88); 2656251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2657251538Srpaulo urtwn_bb_write(sc, 0xe88, reg); 2658251538Srpaulo } 2659251538Srpaulo 2660251538Srpaulo /* Write AGC values. */ 2661251538Srpaulo for (i = 0; i < prog->agccount; i++) { 2662251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2663251538Srpaulo prog->agcvals[i]); 2664266472Shselasky urtwn_ms_delay(sc); 2665251538Srpaulo } 2666251538Srpaulo 2667264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 2668264912Skevlo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 2669266472Shselasky urtwn_ms_delay(sc); 2670264912Skevlo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 2671266472Shselasky urtwn_ms_delay(sc); 2672264912Skevlo 2673264912Skevlo crystalcap = sc->r88e_rom[0xb9]; 2674264912Skevlo if (crystalcap == 0xff) 2675264912Skevlo crystalcap = 0x20; 2676264912Skevlo crystalcap &= 0x3f; 2677264912Skevlo reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 2678264912Skevlo urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 2679264912Skevlo RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 2680264912Skevlo crystalcap | crystalcap << 6)); 2681264912Skevlo } else { 2682264912Skevlo if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2683264912Skevlo R92C_HSSI_PARAM2_CCK_HIPWR) 2684264912Skevlo sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 2685264912Skevlo } 2686251538Srpaulo} 2687251538Srpaulo 2688289066Skevlostatic void 2689251538Srpaulourtwn_rf_init(struct urtwn_softc *sc) 2690251538Srpaulo{ 2691251538Srpaulo const struct urtwn_rf_prog *prog; 2692251538Srpaulo uint32_t reg, type; 2693251538Srpaulo int i, j, idx, off; 2694251538Srpaulo 2695251538Srpaulo /* Select RF programming based on board type. */ 2696264912Skevlo if (sc->chip & URTWN_CHIP_88E) 2697264912Skevlo prog = rtl8188eu_rf_prog; 2698264912Skevlo else if (!(sc->chip & URTWN_CHIP_92C)) { 2699251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2700251538Srpaulo prog = rtl8188ce_rf_prog; 2701251538Srpaulo else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2702251538Srpaulo prog = rtl8188ru_rf_prog; 2703251538Srpaulo else 2704251538Srpaulo prog = rtl8188cu_rf_prog; 2705251538Srpaulo } else 2706251538Srpaulo prog = rtl8192ce_rf_prog; 2707251538Srpaulo 2708251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 2709251538Srpaulo /* Save RF_ENV control type. */ 2710251538Srpaulo idx = i / 2; 2711251538Srpaulo off = (i % 2) * 16; 2712251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2713251538Srpaulo type = (reg >> off) & 0x10; 2714251538Srpaulo 2715251538Srpaulo /* Set RF_ENV enable. */ 2716251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2717251538Srpaulo reg |= 0x100000; 2718251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2719266472Shselasky urtwn_ms_delay(sc); 2720251538Srpaulo /* Set RF_ENV output high. */ 2721251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2722251538Srpaulo reg |= 0x10; 2723251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2724266472Shselasky urtwn_ms_delay(sc); 2725251538Srpaulo /* Set address and data lengths of RF registers. */ 2726251538Srpaulo reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2727251538Srpaulo reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2728251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2729266472Shselasky urtwn_ms_delay(sc); 2730251538Srpaulo reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2731251538Srpaulo reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2732251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2733266472Shselasky urtwn_ms_delay(sc); 2734251538Srpaulo 2735251538Srpaulo /* Write RF initialization values for this chain. */ 2736251538Srpaulo for (j = 0; j < prog[i].count; j++) { 2737251538Srpaulo if (prog[i].regs[j] >= 0xf9 && 2738251538Srpaulo prog[i].regs[j] <= 0xfe) { 2739251538Srpaulo /* 2740251538Srpaulo * These are fake RF registers offsets that 2741251538Srpaulo * indicate a delay is required. 2742251538Srpaulo */ 2743266472Shselasky usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 2744251538Srpaulo continue; 2745251538Srpaulo } 2746251538Srpaulo urtwn_rf_write(sc, i, prog[i].regs[j], 2747251538Srpaulo prog[i].vals[j]); 2748266472Shselasky urtwn_ms_delay(sc); 2749251538Srpaulo } 2750251538Srpaulo 2751251538Srpaulo /* Restore RF_ENV control type. */ 2752251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2753251538Srpaulo reg &= ~(0x10 << off) | (type << off); 2754251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2755251538Srpaulo 2756251538Srpaulo /* Cache RF register CHNLBW. */ 2757251538Srpaulo sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2758251538Srpaulo } 2759251538Srpaulo 2760251538Srpaulo if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2761251538Srpaulo URTWN_CHIP_UMC_A_CUT) { 2762251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2763251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2764251538Srpaulo } 2765251538Srpaulo} 2766251538Srpaulo 2767251538Srpaulostatic void 2768251538Srpaulourtwn_cam_init(struct urtwn_softc *sc) 2769251538Srpaulo{ 2770251538Srpaulo /* Invalidate all CAM entries. */ 2771251538Srpaulo urtwn_write_4(sc, R92C_CAMCMD, 2772251538Srpaulo R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2773251538Srpaulo} 2774251538Srpaulo 2775251538Srpaulostatic void 2776251538Srpaulourtwn_pa_bias_init(struct urtwn_softc *sc) 2777251538Srpaulo{ 2778251538Srpaulo uint8_t reg; 2779251538Srpaulo int i; 2780251538Srpaulo 2781251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 2782251538Srpaulo if (sc->pa_setting & (1 << i)) 2783251538Srpaulo continue; 2784251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2785251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2786251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2787251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2788251538Srpaulo } 2789251538Srpaulo if (!(sc->pa_setting & 0x10)) { 2790251538Srpaulo reg = urtwn_read_1(sc, 0x16); 2791251538Srpaulo reg = (reg & ~0xf0) | 0x90; 2792251538Srpaulo urtwn_write_1(sc, 0x16, reg); 2793251538Srpaulo } 2794251538Srpaulo} 2795251538Srpaulo 2796251538Srpaulostatic void 2797251538Srpaulourtwn_rxfilter_init(struct urtwn_softc *sc) 2798251538Srpaulo{ 2799251538Srpaulo /* Initialize Rx filter. */ 2800251538Srpaulo /* TODO: use better filter for monitor mode. */ 2801251538Srpaulo urtwn_write_4(sc, R92C_RCR, 2802251538Srpaulo R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2803251538Srpaulo R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2804251538Srpaulo R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2805251538Srpaulo /* Accept all multicast frames. */ 2806251538Srpaulo urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2807251538Srpaulo urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2808251538Srpaulo /* Accept all management frames. */ 2809251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2810251538Srpaulo /* Reject all control frames. */ 2811251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2812251538Srpaulo /* Accept all data frames. */ 2813251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2814251538Srpaulo} 2815251538Srpaulo 2816251538Srpaulostatic void 2817251538Srpaulourtwn_edca_init(struct urtwn_softc *sc) 2818251538Srpaulo{ 2819251538Srpaulo urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 2820251538Srpaulo urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 2821251538Srpaulo urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 2822251538Srpaulo urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 2823251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2824251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2825251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 2826251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 2827251538Srpaulo} 2828251538Srpaulo 2829289066Skevlostatic void 2830251538Srpaulourtwn_write_txpower(struct urtwn_softc *sc, int chain, 2831251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]) 2832251538Srpaulo{ 2833251538Srpaulo uint32_t reg; 2834251538Srpaulo 2835251538Srpaulo /* Write per-CCK rate Tx power. */ 2836251538Srpaulo if (chain == 0) { 2837251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2838251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2839251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2840251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2841251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2842251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2843251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2844251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2845251538Srpaulo } else { 2846251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2847251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2848251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2849251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2850251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2851251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2852251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2853251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2854251538Srpaulo } 2855251538Srpaulo /* Write per-OFDM rate Tx power. */ 2856251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2857251538Srpaulo SM(R92C_TXAGC_RATE06, power[ 4]) | 2858251538Srpaulo SM(R92C_TXAGC_RATE09, power[ 5]) | 2859251538Srpaulo SM(R92C_TXAGC_RATE12, power[ 6]) | 2860251538Srpaulo SM(R92C_TXAGC_RATE18, power[ 7])); 2861251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2862251538Srpaulo SM(R92C_TXAGC_RATE24, power[ 8]) | 2863251538Srpaulo SM(R92C_TXAGC_RATE36, power[ 9]) | 2864251538Srpaulo SM(R92C_TXAGC_RATE48, power[10]) | 2865251538Srpaulo SM(R92C_TXAGC_RATE54, power[11])); 2866251538Srpaulo /* Write per-MCS Tx power. */ 2867251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2868251538Srpaulo SM(R92C_TXAGC_MCS00, power[12]) | 2869251538Srpaulo SM(R92C_TXAGC_MCS01, power[13]) | 2870251538Srpaulo SM(R92C_TXAGC_MCS02, power[14]) | 2871251538Srpaulo SM(R92C_TXAGC_MCS03, power[15])); 2872251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2873251538Srpaulo SM(R92C_TXAGC_MCS04, power[16]) | 2874251538Srpaulo SM(R92C_TXAGC_MCS05, power[17]) | 2875251538Srpaulo SM(R92C_TXAGC_MCS06, power[18]) | 2876251538Srpaulo SM(R92C_TXAGC_MCS07, power[19])); 2877251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2878251538Srpaulo SM(R92C_TXAGC_MCS08, power[20]) | 2879261506Skevlo SM(R92C_TXAGC_MCS09, power[21]) | 2880251538Srpaulo SM(R92C_TXAGC_MCS10, power[22]) | 2881251538Srpaulo SM(R92C_TXAGC_MCS11, power[23])); 2882251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2883251538Srpaulo SM(R92C_TXAGC_MCS12, power[24]) | 2884251538Srpaulo SM(R92C_TXAGC_MCS13, power[25]) | 2885251538Srpaulo SM(R92C_TXAGC_MCS14, power[26]) | 2886251538Srpaulo SM(R92C_TXAGC_MCS15, power[27])); 2887251538Srpaulo} 2888251538Srpaulo 2889289066Skevlostatic void 2890251538Srpaulourtwn_get_txpower(struct urtwn_softc *sc, int chain, 2891251538Srpaulo struct ieee80211_channel *c, struct ieee80211_channel *extc, 2892251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]) 2893251538Srpaulo{ 2894287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 2895251538Srpaulo struct r92c_rom *rom = &sc->rom; 2896251538Srpaulo uint16_t cckpow, ofdmpow, htpow, diff, max; 2897251538Srpaulo const struct urtwn_txpwr *base; 2898251538Srpaulo int ridx, chan, group; 2899251538Srpaulo 2900251538Srpaulo /* Determine channel group. */ 2901251538Srpaulo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2902251538Srpaulo if (chan <= 3) 2903251538Srpaulo group = 0; 2904251538Srpaulo else if (chan <= 9) 2905251538Srpaulo group = 1; 2906251538Srpaulo else 2907251538Srpaulo group = 2; 2908251538Srpaulo 2909251538Srpaulo /* Get original Tx power based on board type and RF chain. */ 2910251538Srpaulo if (!(sc->chip & URTWN_CHIP_92C)) { 2911251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2912251538Srpaulo base = &rtl8188ru_txagc[chain]; 2913251538Srpaulo else 2914251538Srpaulo base = &rtl8192cu_txagc[chain]; 2915251538Srpaulo } else 2916251538Srpaulo base = &rtl8192cu_txagc[chain]; 2917251538Srpaulo 2918251538Srpaulo memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 2919251538Srpaulo if (sc->regulatory == 0) { 2920289758Savos for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 2921251538Srpaulo power[ridx] = base->pwr[0][ridx]; 2922251538Srpaulo } 2923289758Savos for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 2924251538Srpaulo if (sc->regulatory == 3) { 2925251538Srpaulo power[ridx] = base->pwr[0][ridx]; 2926251538Srpaulo /* Apply vendor limits. */ 2927251538Srpaulo if (extc != NULL) 2928251538Srpaulo max = rom->ht40_max_pwr[group]; 2929251538Srpaulo else 2930251538Srpaulo max = rom->ht20_max_pwr[group]; 2931251538Srpaulo max = (max >> (chain * 4)) & 0xf; 2932251538Srpaulo if (power[ridx] > max) 2933251538Srpaulo power[ridx] = max; 2934251538Srpaulo } else if (sc->regulatory == 1) { 2935251538Srpaulo if (extc == NULL) 2936251538Srpaulo power[ridx] = base->pwr[group][ridx]; 2937251538Srpaulo } else if (sc->regulatory != 2) 2938251538Srpaulo power[ridx] = base->pwr[0][ridx]; 2939251538Srpaulo } 2940251538Srpaulo 2941251538Srpaulo /* Compute per-CCK rate Tx power. */ 2942251538Srpaulo cckpow = rom->cck_tx_pwr[chain][group]; 2943289758Savos for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 2944251538Srpaulo power[ridx] += cckpow; 2945251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 2946251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 2947251538Srpaulo } 2948251538Srpaulo 2949251538Srpaulo htpow = rom->ht40_1s_tx_pwr[chain][group]; 2950251538Srpaulo if (sc->ntxchains > 1) { 2951251538Srpaulo /* Apply reduction for 2 spatial streams. */ 2952251538Srpaulo diff = rom->ht40_2s_tx_pwr_diff[group]; 2953251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 2954251538Srpaulo htpow = (htpow > diff) ? htpow - diff : 0; 2955251538Srpaulo } 2956251538Srpaulo 2957251538Srpaulo /* Compute per-OFDM rate Tx power. */ 2958251538Srpaulo diff = rom->ofdm_tx_pwr_diff[group]; 2959251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 2960251538Srpaulo ofdmpow = htpow + diff; /* HT->OFDM correction. */ 2961289758Savos for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 2962251538Srpaulo power[ridx] += ofdmpow; 2963251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 2964251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 2965251538Srpaulo } 2966251538Srpaulo 2967251538Srpaulo /* Compute per-MCS Tx power. */ 2968251538Srpaulo if (extc == NULL) { 2969251538Srpaulo diff = rom->ht20_tx_pwr_diff[group]; 2970251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 2971251538Srpaulo htpow += diff; /* HT40->HT20 correction. */ 2972251538Srpaulo } 2973251538Srpaulo for (ridx = 12; ridx <= 27; ridx++) { 2974251538Srpaulo power[ridx] += htpow; 2975251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 2976251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 2977251538Srpaulo } 2978251538Srpaulo#ifdef URTWN_DEBUG 2979251538Srpaulo if (urtwn_debug >= 4) { 2980251538Srpaulo /* Dump per-rate Tx power values. */ 2981251538Srpaulo printf("Tx power for chain %d:\n", chain); 2982289758Savos for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++) 2983251538Srpaulo printf("Rate %d = %u\n", ridx, power[ridx]); 2984251538Srpaulo } 2985251538Srpaulo#endif 2986251538Srpaulo} 2987251538Srpaulo 2988289066Skevlostatic void 2989264912Skevlourtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 2990264912Skevlo struct ieee80211_channel *c, struct ieee80211_channel *extc, 2991264912Skevlo uint16_t power[URTWN_RIDX_COUNT]) 2992264912Skevlo{ 2993287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 2994264912Skevlo uint16_t cckpow, ofdmpow, bw20pow, htpow; 2995264912Skevlo const struct urtwn_r88e_txpwr *base; 2996264912Skevlo int ridx, chan, group; 2997264912Skevlo 2998264912Skevlo /* Determine channel group. */ 2999264912Skevlo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3000264912Skevlo if (chan <= 2) 3001264912Skevlo group = 0; 3002264912Skevlo else if (chan <= 5) 3003264912Skevlo group = 1; 3004264912Skevlo else if (chan <= 8) 3005264912Skevlo group = 2; 3006264912Skevlo else if (chan <= 11) 3007264912Skevlo group = 3; 3008264912Skevlo else if (chan <= 13) 3009264912Skevlo group = 4; 3010264912Skevlo else 3011264912Skevlo group = 5; 3012264912Skevlo 3013264912Skevlo /* Get original Tx power based on board type and RF chain. */ 3014264912Skevlo base = &rtl8188eu_txagc[chain]; 3015264912Skevlo 3016264912Skevlo memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3017264912Skevlo if (sc->regulatory == 0) { 3018289758Savos for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 3019264912Skevlo power[ridx] = base->pwr[0][ridx]; 3020264912Skevlo } 3021289758Savos for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 3022264912Skevlo if (sc->regulatory == 3) 3023264912Skevlo power[ridx] = base->pwr[0][ridx]; 3024264912Skevlo else if (sc->regulatory == 1) { 3025264912Skevlo if (extc == NULL) 3026264912Skevlo power[ridx] = base->pwr[group][ridx]; 3027264912Skevlo } else if (sc->regulatory != 2) 3028264912Skevlo power[ridx] = base->pwr[0][ridx]; 3029264912Skevlo } 3030264912Skevlo 3031264912Skevlo /* Compute per-CCK rate Tx power. */ 3032264912Skevlo cckpow = sc->cck_tx_pwr[group]; 3033289758Savos for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 3034264912Skevlo power[ridx] += cckpow; 3035264912Skevlo if (power[ridx] > R92C_MAX_TX_PWR) 3036264912Skevlo power[ridx] = R92C_MAX_TX_PWR; 3037264912Skevlo } 3038264912Skevlo 3039264912Skevlo htpow = sc->ht40_tx_pwr[group]; 3040264912Skevlo 3041264912Skevlo /* Compute per-OFDM rate Tx power. */ 3042264912Skevlo ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3043289758Savos for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 3044264912Skevlo power[ridx] += ofdmpow; 3045264912Skevlo if (power[ridx] > R92C_MAX_TX_PWR) 3046264912Skevlo power[ridx] = R92C_MAX_TX_PWR; 3047264912Skevlo } 3048264912Skevlo 3049264912Skevlo bw20pow = htpow + sc->bw20_tx_pwr_diff; 3050264912Skevlo for (ridx = 12; ridx <= 27; ridx++) { 3051264912Skevlo power[ridx] += bw20pow; 3052264912Skevlo if (power[ridx] > R92C_MAX_TX_PWR) 3053264912Skevlo power[ridx] = R92C_MAX_TX_PWR; 3054264912Skevlo } 3055264912Skevlo} 3056264912Skevlo 3057289066Skevlostatic void 3058251538Srpaulourtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 3059251538Srpaulo struct ieee80211_channel *extc) 3060251538Srpaulo{ 3061251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]; 3062251538Srpaulo int i; 3063251538Srpaulo 3064251538Srpaulo for (i = 0; i < sc->ntxchains; i++) { 3065251538Srpaulo /* Compute per-rate Tx power values. */ 3066264912Skevlo if (sc->chip & URTWN_CHIP_88E) 3067264912Skevlo urtwn_r88e_get_txpower(sc, i, c, extc, power); 3068264912Skevlo else 3069264912Skevlo urtwn_get_txpower(sc, i, c, extc, power); 3070251538Srpaulo /* Write per-rate Tx power values to hardware. */ 3071251538Srpaulo urtwn_write_txpower(sc, i, power); 3072251538Srpaulo } 3073251538Srpaulo} 3074251538Srpaulo 3075251538Srpaulostatic void 3076251538Srpaulourtwn_scan_start(struct ieee80211com *ic) 3077251538Srpaulo{ 3078251538Srpaulo /* XXX do nothing? */ 3079251538Srpaulo} 3080251538Srpaulo 3081251538Srpaulostatic void 3082251538Srpaulourtwn_scan_end(struct ieee80211com *ic) 3083251538Srpaulo{ 3084251538Srpaulo /* XXX do nothing? */ 3085251538Srpaulo} 3086251538Srpaulo 3087251538Srpaulostatic void 3088251538Srpaulourtwn_set_channel(struct ieee80211com *ic) 3089251538Srpaulo{ 3090286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 3091281070Srpaulo struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3092251538Srpaulo 3093251538Srpaulo URTWN_LOCK(sc); 3094281070Srpaulo if (vap->iv_state == IEEE80211_S_SCAN) { 3095281070Srpaulo /* Make link LED blink during scan. */ 3096281070Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 3097281070Srpaulo } 3098251538Srpaulo urtwn_set_chan(sc, ic->ic_curchan, NULL); 3099251538Srpaulo URTWN_UNLOCK(sc); 3100251538Srpaulo} 3101251538Srpaulo 3102251538Srpaulostatic void 3103283540Sglebiusurtwn_update_mcast(struct ieee80211com *ic) 3104251538Srpaulo{ 3105251538Srpaulo /* XXX do nothing? */ 3106251538Srpaulo} 3107251538Srpaulo 3108251538Srpaulostatic void 3109251538Srpaulourtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 3110251538Srpaulo struct ieee80211_channel *extc) 3111251538Srpaulo{ 3112287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 3113251538Srpaulo uint32_t reg; 3114251538Srpaulo u_int chan; 3115251538Srpaulo int i; 3116251538Srpaulo 3117251538Srpaulo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3118251538Srpaulo if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 3119251538Srpaulo device_printf(sc->sc_dev, 3120251538Srpaulo "%s: invalid channel %x\n", __func__, chan); 3121251538Srpaulo return; 3122251538Srpaulo } 3123251538Srpaulo 3124251538Srpaulo /* Set Tx power for this new channel. */ 3125251538Srpaulo urtwn_set_txpower(sc, c, extc); 3126251538Srpaulo 3127251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 3128251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3129251538Srpaulo RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3130251538Srpaulo } 3131251538Srpaulo#ifndef IEEE80211_NO_HT 3132251538Srpaulo if (extc != NULL) { 3133251538Srpaulo /* Is secondary channel below or above primary? */ 3134251538Srpaulo int prichlo = c->ic_freq < extc->ic_freq; 3135251538Srpaulo 3136251538Srpaulo urtwn_write_1(sc, R92C_BWOPMODE, 3137251538Srpaulo urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3138251538Srpaulo 3139251538Srpaulo reg = urtwn_read_1(sc, R92C_RRSR + 2); 3140251538Srpaulo reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3141251538Srpaulo urtwn_write_1(sc, R92C_RRSR + 2, reg); 3142251538Srpaulo 3143251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3144251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3145251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3146251538Srpaulo urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3147251538Srpaulo 3148251538Srpaulo /* Set CCK side band. */ 3149251538Srpaulo reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3150251538Srpaulo reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3151251538Srpaulo urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3152251538Srpaulo 3153251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3154251538Srpaulo reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3155251538Srpaulo urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3156251538Srpaulo 3157251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3158251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3159251538Srpaulo ~R92C_FPGA0_ANAPARAM2_CBW20); 3160251538Srpaulo 3161251538Srpaulo reg = urtwn_bb_read(sc, 0x818); 3162251538Srpaulo reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3163251538Srpaulo urtwn_bb_write(sc, 0x818, reg); 3164251538Srpaulo 3165251538Srpaulo /* Select 40MHz bandwidth. */ 3166251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3167251538Srpaulo (sc->rf_chnlbw[0] & ~0xfff) | chan); 3168251538Srpaulo } else 3169251538Srpaulo#endif 3170251538Srpaulo { 3171251538Srpaulo urtwn_write_1(sc, R92C_BWOPMODE, 3172251538Srpaulo urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3173251538Srpaulo 3174251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3175251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3176251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3177251538Srpaulo urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3178251538Srpaulo 3179264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3180264912Skevlo urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3181264912Skevlo urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3182264912Skevlo R92C_FPGA0_ANAPARAM2_CBW20); 3183264912Skevlo } 3184281069Srpaulo 3185251538Srpaulo /* Select 20MHz bandwidth. */ 3186251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3187281069Srpaulo (sc->rf_chnlbw[0] & ~0xfff) | chan | 3188264912Skevlo ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 3189264912Skevlo R92C_RF_CHNLBW_BW20)); 3190251538Srpaulo } 3191251538Srpaulo} 3192251538Srpaulo 3193251538Srpaulostatic void 3194251538Srpaulourtwn_iq_calib(struct urtwn_softc *sc) 3195251538Srpaulo{ 3196251538Srpaulo /* TODO */ 3197251538Srpaulo} 3198251538Srpaulo 3199251538Srpaulostatic void 3200251538Srpaulourtwn_lc_calib(struct urtwn_softc *sc) 3201251538Srpaulo{ 3202251538Srpaulo uint32_t rf_ac[2]; 3203251538Srpaulo uint8_t txmode; 3204251538Srpaulo int i; 3205251538Srpaulo 3206251538Srpaulo txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3207251538Srpaulo if ((txmode & 0x70) != 0) { 3208251538Srpaulo /* Disable all continuous Tx. */ 3209251538Srpaulo urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3210251538Srpaulo 3211251538Srpaulo /* Set RF mode to standby mode. */ 3212251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 3213251538Srpaulo rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3214251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_AC, 3215251538Srpaulo RW(rf_ac[i], R92C_RF_AC_MODE, 3216251538Srpaulo R92C_RF_AC_MODE_STANDBY)); 3217251538Srpaulo } 3218251538Srpaulo } else { 3219251538Srpaulo /* Block all Tx queues. */ 3220251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3221251538Srpaulo } 3222251538Srpaulo /* Start calibration. */ 3223251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3224251538Srpaulo urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3225251538Srpaulo 3226251538Srpaulo /* Give calibration the time to complete. */ 3227266472Shselasky usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 3228251538Srpaulo 3229251538Srpaulo /* Restore configuration. */ 3230251538Srpaulo if ((txmode & 0x70) != 0) { 3231251538Srpaulo /* Restore Tx mode. */ 3232251538Srpaulo urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3233251538Srpaulo /* Restore RF mode. */ 3234251538Srpaulo for (i = 0; i < sc->nrxchains; i++) 3235251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3236251538Srpaulo } else { 3237251538Srpaulo /* Unblock all Tx queues. */ 3238251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3239251538Srpaulo } 3240251538Srpaulo} 3241251538Srpaulo 3242251538Srpaulostatic void 3243287197Sglebiusurtwn_init(struct urtwn_softc *sc) 3244251538Srpaulo{ 3245287197Sglebius struct ieee80211com *ic = &sc->sc_ic; 3246287197Sglebius struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3247287197Sglebius uint8_t macaddr[IEEE80211_ADDR_LEN]; 3248251538Srpaulo uint32_t reg; 3249251538Srpaulo int error; 3250251538Srpaulo 3251264864Skevlo URTWN_ASSERT_LOCKED(sc); 3252264864Skevlo 3253287197Sglebius if (sc->sc_flags & URTWN_RUNNING) 3254287197Sglebius urtwn_stop(sc); 3255251538Srpaulo 3256251538Srpaulo /* Init firmware commands ring. */ 3257251538Srpaulo sc->fwcur = 0; 3258251538Srpaulo 3259251538Srpaulo /* Allocate Tx/Rx buffers. */ 3260251538Srpaulo error = urtwn_alloc_rx_list(sc); 3261251538Srpaulo if (error != 0) 3262251538Srpaulo goto fail; 3263281069Srpaulo 3264251538Srpaulo error = urtwn_alloc_tx_list(sc); 3265251538Srpaulo if (error != 0) 3266251538Srpaulo goto fail; 3267251538Srpaulo 3268251538Srpaulo /* Power on adapter. */ 3269251538Srpaulo error = urtwn_power_on(sc); 3270251538Srpaulo if (error != 0) 3271251538Srpaulo goto fail; 3272251538Srpaulo 3273251538Srpaulo /* Initialize DMA. */ 3274251538Srpaulo error = urtwn_dma_init(sc); 3275251538Srpaulo if (error != 0) 3276251538Srpaulo goto fail; 3277251538Srpaulo 3278251538Srpaulo /* Set info size in Rx descriptors (in 64-bit words). */ 3279251538Srpaulo urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3280251538Srpaulo 3281251538Srpaulo /* Init interrupts. */ 3282264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 3283264912Skevlo urtwn_write_4(sc, R88E_HISR, 0xffffffff); 3284264912Skevlo urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 3285264912Skevlo R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 3286264912Skevlo urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 3287264912Skevlo R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 3288264912Skevlo urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3289264912Skevlo urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3290264912Skevlo R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 3291264912Skevlo } else { 3292264912Skevlo urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3293264912Skevlo urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3294264912Skevlo } 3295251538Srpaulo 3296251538Srpaulo /* Set MAC address. */ 3297287197Sglebius IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 3298287197Sglebius urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 3299251538Srpaulo 3300251538Srpaulo /* Set initial network type. */ 3301251538Srpaulo reg = urtwn_read_4(sc, R92C_CR); 3302251538Srpaulo reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 3303251538Srpaulo urtwn_write_4(sc, R92C_CR, reg); 3304251538Srpaulo 3305251538Srpaulo urtwn_rxfilter_init(sc); 3306251538Srpaulo 3307282623Skevlo /* Set response rate. */ 3308251538Srpaulo reg = urtwn_read_4(sc, R92C_RRSR); 3309251538Srpaulo reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3310251538Srpaulo urtwn_write_4(sc, R92C_RRSR, reg); 3311251538Srpaulo 3312251538Srpaulo /* Set short/long retry limits. */ 3313251538Srpaulo urtwn_write_2(sc, R92C_RL, 3314251538Srpaulo SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3315251538Srpaulo 3316251538Srpaulo /* Initialize EDCA parameters. */ 3317251538Srpaulo urtwn_edca_init(sc); 3318251538Srpaulo 3319251538Srpaulo /* Setup rate fallback. */ 3320264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3321264912Skevlo urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3322264912Skevlo urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3323264912Skevlo urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3324264912Skevlo urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3325264912Skevlo } 3326251538Srpaulo 3327251538Srpaulo urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3328251538Srpaulo urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3329251538Srpaulo R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3330251538Srpaulo /* Set ACK timeout. */ 3331251538Srpaulo urtwn_write_1(sc, R92C_ACKTO, 0x40); 3332251538Srpaulo 3333251538Srpaulo /* Setup USB aggregation. */ 3334251538Srpaulo reg = urtwn_read_4(sc, R92C_TDECTRL); 3335251538Srpaulo reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3336251538Srpaulo urtwn_write_4(sc, R92C_TDECTRL, reg); 3337251538Srpaulo urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3338251538Srpaulo urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3339251538Srpaulo R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3340251538Srpaulo urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3341264912Skevlo if (sc->chip & URTWN_CHIP_88E) 3342264912Skevlo urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 3343282266Skevlo else { 3344264912Skevlo urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3345282266Skevlo urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3346282266Skevlo urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3347282266Skevlo R92C_USB_SPECIAL_OPTION_AGG_EN); 3348282266Skevlo urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 3349282266Skevlo urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 3350282266Skevlo } 3351251538Srpaulo 3352251538Srpaulo /* Initialize beacon parameters. */ 3353264912Skevlo urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 3354251538Srpaulo urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3355251538Srpaulo urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3356251538Srpaulo urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3357251538Srpaulo urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3358251538Srpaulo 3359264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3360264912Skevlo /* Setup AMPDU aggregation. */ 3361264912Skevlo urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3362264912Skevlo urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3363264912Skevlo urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 3364251538Srpaulo 3365264912Skevlo urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3366264912Skevlo } 3367251538Srpaulo 3368251538Srpaulo /* Load 8051 microcode. */ 3369251538Srpaulo error = urtwn_load_firmware(sc); 3370251538Srpaulo if (error != 0) 3371251538Srpaulo goto fail; 3372251538Srpaulo 3373251538Srpaulo /* Initialize MAC/BB/RF blocks. */ 3374251538Srpaulo urtwn_mac_init(sc); 3375251538Srpaulo urtwn_bb_init(sc); 3376251538Srpaulo urtwn_rf_init(sc); 3377251538Srpaulo 3378264912Skevlo if (sc->chip & URTWN_CHIP_88E) { 3379264912Skevlo urtwn_write_2(sc, R92C_CR, 3380264912Skevlo urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 3381264912Skevlo R92C_CR_MACRXEN); 3382264912Skevlo } 3383264912Skevlo 3384251538Srpaulo /* Turn CCK and OFDM blocks on. */ 3385251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3386251538Srpaulo reg |= R92C_RFMOD_CCK_EN; 3387251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3388251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3389251538Srpaulo reg |= R92C_RFMOD_OFDM_EN; 3390251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3391251538Srpaulo 3392251538Srpaulo /* Clear per-station keys table. */ 3393251538Srpaulo urtwn_cam_init(sc); 3394251538Srpaulo 3395251538Srpaulo /* Enable hardware sequence numbering. */ 3396251538Srpaulo urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3397251538Srpaulo 3398251538Srpaulo /* Perform LO and IQ calibrations. */ 3399251538Srpaulo urtwn_iq_calib(sc); 3400251538Srpaulo /* Perform LC calibration. */ 3401251538Srpaulo urtwn_lc_calib(sc); 3402251538Srpaulo 3403251538Srpaulo /* Fix USB interference issue. */ 3404264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 3405264912Skevlo urtwn_write_1(sc, 0xfe40, 0xe0); 3406264912Skevlo urtwn_write_1(sc, 0xfe41, 0x8d); 3407264912Skevlo urtwn_write_1(sc, 0xfe42, 0x80); 3408251538Srpaulo 3409264912Skevlo urtwn_pa_bias_init(sc); 3410264912Skevlo } 3411251538Srpaulo 3412251538Srpaulo /* Initialize GPIO setting. */ 3413251538Srpaulo urtwn_write_1(sc, R92C_GPIO_MUXCFG, 3414251538Srpaulo urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3415251538Srpaulo 3416251538Srpaulo /* Fix for lower temperature. */ 3417264912Skevlo if (!(sc->chip & URTWN_CHIP_88E)) 3418264912Skevlo urtwn_write_1(sc, 0x15, 0xe9); 3419251538Srpaulo 3420251538Srpaulo usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 3421251538Srpaulo 3422287197Sglebius sc->sc_flags |= URTWN_RUNNING; 3423251538Srpaulo 3424251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3425251538Srpaulofail: 3426251538Srpaulo return; 3427251538Srpaulo} 3428251538Srpaulo 3429251538Srpaulostatic void 3430287197Sglebiusurtwn_stop(struct urtwn_softc *sc) 3431251538Srpaulo{ 3432251538Srpaulo 3433264864Skevlo URTWN_ASSERT_LOCKED(sc); 3434287197Sglebius sc->sc_flags &= ~URTWN_RUNNING; 3435251538Srpaulo callout_stop(&sc->sc_watchdog_ch); 3436251538Srpaulo urtwn_abort_xfers(sc); 3437288353Sadrian 3438288353Sadrian urtwn_drain_mbufq(sc); 3439251538Srpaulo} 3440251538Srpaulo 3441251538Srpaulostatic void 3442251538Srpaulourtwn_abort_xfers(struct urtwn_softc *sc) 3443251538Srpaulo{ 3444251538Srpaulo int i; 3445251538Srpaulo 3446251538Srpaulo URTWN_ASSERT_LOCKED(sc); 3447251538Srpaulo 3448251538Srpaulo /* abort any pending transfers */ 3449251538Srpaulo for (i = 0; i < URTWN_N_TRANSFER; i++) 3450251538Srpaulo usbd_transfer_stop(sc->sc_xfer[i]); 3451251538Srpaulo} 3452251538Srpaulo 3453251538Srpaulostatic int 3454251538Srpaulourtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3455251538Srpaulo const struct ieee80211_bpf_params *params) 3456251538Srpaulo{ 3457251538Srpaulo struct ieee80211com *ic = ni->ni_ic; 3458286949Sadrian struct urtwn_softc *sc = ic->ic_softc; 3459251538Srpaulo struct urtwn_data *bf; 3460251538Srpaulo 3461251538Srpaulo /* prevent management frames from being sent if we're not ready */ 3462287197Sglebius if (!(sc->sc_flags & URTWN_RUNNING)) { 3463251538Srpaulo m_freem(m); 3464251538Srpaulo return (ENETDOWN); 3465251538Srpaulo } 3466251538Srpaulo URTWN_LOCK(sc); 3467251538Srpaulo bf = urtwn_getbuf(sc); 3468251538Srpaulo if (bf == NULL) { 3469251538Srpaulo m_freem(m); 3470251538Srpaulo URTWN_UNLOCK(sc); 3471251538Srpaulo return (ENOBUFS); 3472251538Srpaulo } 3473251538Srpaulo 3474251538Srpaulo if (urtwn_tx_start(sc, ni, m, bf) != 0) { 3475288353Sadrian m_freem(m); 3476251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3477251538Srpaulo URTWN_UNLOCK(sc); 3478251538Srpaulo return (EIO); 3479251538Srpaulo } 3480288353Sadrian sc->sc_txtimer = 5; 3481251538Srpaulo URTWN_UNLOCK(sc); 3482251538Srpaulo 3483251538Srpaulo return (0); 3484251538Srpaulo} 3485251538Srpaulo 3486266472Shselaskystatic void 3487266472Shselaskyurtwn_ms_delay(struct urtwn_softc *sc) 3488266472Shselasky{ 3489266472Shselasky usb_pause_mtx(&sc->sc_mtx, hz / 1000); 3490266472Shselasky} 3491266472Shselasky 3492251538Srpaulostatic device_method_t urtwn_methods[] = { 3493251538Srpaulo /* Device interface */ 3494251538Srpaulo DEVMETHOD(device_probe, urtwn_match), 3495251538Srpaulo DEVMETHOD(device_attach, urtwn_attach), 3496251538Srpaulo DEVMETHOD(device_detach, urtwn_detach), 3497251538Srpaulo 3498264912Skevlo DEVMETHOD_END 3499251538Srpaulo}; 3500251538Srpaulo 3501251538Srpaulostatic driver_t urtwn_driver = { 3502251538Srpaulo "urtwn", 3503251538Srpaulo urtwn_methods, 3504251538Srpaulo sizeof(struct urtwn_softc) 3505251538Srpaulo}; 3506251538Srpaulo 3507251538Srpaulostatic devclass_t urtwn_devclass; 3508251538Srpaulo 3509251538SrpauloDRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 3510251538SrpauloMODULE_DEPEND(urtwn, usb, 1, 1, 1); 3511251538SrpauloMODULE_DEPEND(urtwn, wlan, 1, 1, 1); 3512251538SrpauloMODULE_DEPEND(urtwn, firmware, 1, 1, 1); 3513251538SrpauloMODULE_VERSION(urtwn, 1); 3514