if_urtwn.c revision 289758
1/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20#include <sys/cdefs.h> 21__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 289758 2015-10-22 15:42:53Z avos $"); 22 23/* 24 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 25 */ 26 27#include "opt_wlan.h" 28 29#include <sys/param.h> 30#include <sys/sockio.h> 31#include <sys/sysctl.h> 32#include <sys/lock.h> 33#include <sys/mutex.h> 34#include <sys/mbuf.h> 35#include <sys/kernel.h> 36#include <sys/socket.h> 37#include <sys/systm.h> 38#include <sys/malloc.h> 39#include <sys/module.h> 40#include <sys/bus.h> 41#include <sys/endian.h> 42#include <sys/linker.h> 43#include <sys/firmware.h> 44#include <sys/kdb.h> 45 46#include <machine/bus.h> 47#include <machine/resource.h> 48#include <sys/rman.h> 49 50#include <net/bpf.h> 51#include <net/if.h> 52#include <net/if_var.h> 53#include <net/if_arp.h> 54#include <net/ethernet.h> 55#include <net/if_dl.h> 56#include <net/if_media.h> 57#include <net/if_types.h> 58 59#include <netinet/in.h> 60#include <netinet/in_systm.h> 61#include <netinet/in_var.h> 62#include <netinet/if_ether.h> 63#include <netinet/ip.h> 64 65#include <net80211/ieee80211_var.h> 66#include <net80211/ieee80211_input.h> 67#include <net80211/ieee80211_regdomain.h> 68#include <net80211/ieee80211_radiotap.h> 69#include <net80211/ieee80211_ratectl.h> 70 71#include <dev/usb/usb.h> 72#include <dev/usb/usbdi.h> 73#include "usbdevs.h" 74 75#define USB_DEBUG_VAR urtwn_debug 76#include <dev/usb/usb_debug.h> 77 78#include <dev/usb/wlan/if_urtwnreg.h> 79#include <dev/usb/wlan/if_urtwnvar.h> 80 81#ifdef USB_DEBUG 82static int urtwn_debug = 0; 83 84SYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 85SYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RWTUN, &urtwn_debug, 0, 86 "Debug level"); 87#endif 88 89#define URTWN_RSSI(r) (r) - 110 90#define IEEE80211_HAS_ADDR4(wh) IEEE80211_IS_DSTODS(wh) 91 92/* various supported device vendors/products */ 93static const STRUCT_USB_HOST_ID urtwn_devs[] = { 94#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 95#define URTWN_RTL8188E_DEV(v,p) \ 96 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 97#define URTWN_RTL8188E 1 98 URTWN_DEV(ABOCOM, RTL8188CU_1), 99 URTWN_DEV(ABOCOM, RTL8188CU_2), 100 URTWN_DEV(ABOCOM, RTL8192CU), 101 URTWN_DEV(ASUS, RTL8192CU), 102 URTWN_DEV(ASUS, USBN10NANO), 103 URTWN_DEV(AZUREWAVE, RTL8188CE_1), 104 URTWN_DEV(AZUREWAVE, RTL8188CE_2), 105 URTWN_DEV(AZUREWAVE, RTL8188CU), 106 URTWN_DEV(BELKIN, F7D2102), 107 URTWN_DEV(BELKIN, RTL8188CU), 108 URTWN_DEV(BELKIN, RTL8192CU), 109 URTWN_DEV(CHICONY, RTL8188CUS_1), 110 URTWN_DEV(CHICONY, RTL8188CUS_2), 111 URTWN_DEV(CHICONY, RTL8188CUS_3), 112 URTWN_DEV(CHICONY, RTL8188CUS_4), 113 URTWN_DEV(CHICONY, RTL8188CUS_5), 114 URTWN_DEV(COREGA, RTL8192CU), 115 URTWN_DEV(DLINK, RTL8188CU), 116 URTWN_DEV(DLINK, RTL8192CU_1), 117 URTWN_DEV(DLINK, RTL8192CU_2), 118 URTWN_DEV(DLINK, RTL8192CU_3), 119 URTWN_DEV(DLINK, DWA131B), 120 URTWN_DEV(EDIMAX, EW7811UN), 121 URTWN_DEV(EDIMAX, RTL8192CU), 122 URTWN_DEV(FEIXUN, RTL8188CU), 123 URTWN_DEV(FEIXUN, RTL8192CU), 124 URTWN_DEV(GUILLEMOT, HWNUP150), 125 URTWN_DEV(HAWKING, RTL8192CU), 126 URTWN_DEV(HP3, RTL8188CU), 127 URTWN_DEV(NETGEAR, WNA1000M), 128 URTWN_DEV(NETGEAR, RTL8192CU), 129 URTWN_DEV(NETGEAR4, RTL8188CU), 130 URTWN_DEV(NOVATECH, RTL8188CU), 131 URTWN_DEV(PLANEX2, RTL8188CU_1), 132 URTWN_DEV(PLANEX2, RTL8188CU_2), 133 URTWN_DEV(PLANEX2, RTL8188CU_3), 134 URTWN_DEV(PLANEX2, RTL8188CU_4), 135 URTWN_DEV(PLANEX2, RTL8188CUS), 136 URTWN_DEV(PLANEX2, RTL8192CU), 137 URTWN_DEV(REALTEK, RTL8188CE_0), 138 URTWN_DEV(REALTEK, RTL8188CE_1), 139 URTWN_DEV(REALTEK, RTL8188CTV), 140 URTWN_DEV(REALTEK, RTL8188CU_0), 141 URTWN_DEV(REALTEK, RTL8188CU_1), 142 URTWN_DEV(REALTEK, RTL8188CU_2), 143 URTWN_DEV(REALTEK, RTL8188CU_3), 144 URTWN_DEV(REALTEK, RTL8188CU_COMBO), 145 URTWN_DEV(REALTEK, RTL8188CUS), 146 URTWN_DEV(REALTEK, RTL8188RU_1), 147 URTWN_DEV(REALTEK, RTL8188RU_2), 148 URTWN_DEV(REALTEK, RTL8188RU_3), 149 URTWN_DEV(REALTEK, RTL8191CU), 150 URTWN_DEV(REALTEK, RTL8192CE), 151 URTWN_DEV(REALTEK, RTL8192CU), 152 URTWN_DEV(SITECOMEU, RTL8188CU_1), 153 URTWN_DEV(SITECOMEU, RTL8188CU_2), 154 URTWN_DEV(SITECOMEU, RTL8192CU), 155 URTWN_DEV(TRENDNET, RTL8188CU), 156 URTWN_DEV(TRENDNET, RTL8192CU), 157 URTWN_DEV(ZYXEL, RTL8192CU), 158 /* URTWN_RTL8188E */ 159 URTWN_RTL8188E_DEV(DLINK, DWA123D1), 160 URTWN_RTL8188E_DEV(DLINK, DWA125D1), 161 URTWN_RTL8188E_DEV(ELECOM, WDC150SU2M), 162 URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 163 URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 164#undef URTWN_RTL8188E_DEV 165#undef URTWN_DEV 166}; 167 168static device_probe_t urtwn_match; 169static device_attach_t urtwn_attach; 170static device_detach_t urtwn_detach; 171 172static usb_callback_t urtwn_bulk_tx_callback; 173static usb_callback_t urtwn_bulk_rx_callback; 174 175static void urtwn_drain_mbufq(struct urtwn_softc *sc); 176static usb_error_t urtwn_do_request(struct urtwn_softc *, 177 struct usb_device_request *, void *); 178static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 179 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 180 const uint8_t [IEEE80211_ADDR_LEN], 181 const uint8_t [IEEE80211_ADDR_LEN]); 182static void urtwn_vap_delete(struct ieee80211vap *); 183static struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 184 int *); 185static struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *, 186 int *, int8_t *); 187static void urtwn_txeof(struct usb_xfer *, struct urtwn_data *); 188static int urtwn_alloc_list(struct urtwn_softc *, 189 struct urtwn_data[], int, int); 190static int urtwn_alloc_rx_list(struct urtwn_softc *); 191static int urtwn_alloc_tx_list(struct urtwn_softc *); 192static void urtwn_free_list(struct urtwn_softc *, 193 struct urtwn_data data[], int); 194static void urtwn_free_rx_list(struct urtwn_softc *); 195static void urtwn_free_tx_list(struct urtwn_softc *); 196static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 197static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 198static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, 199 uint8_t *, int); 200static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 201static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 202static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 203static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, 204 uint8_t *, int); 205static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 206static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 207static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 208static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 209 const void *, int); 210static void urtwn_r92c_rf_write(struct urtwn_softc *, int, 211 uint8_t, uint32_t); 212static void urtwn_r88e_rf_write(struct urtwn_softc *, int, 213 uint8_t, uint32_t); 214static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 215static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 216 uint32_t); 217static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 218static void urtwn_efuse_read(struct urtwn_softc *); 219static void urtwn_efuse_switch_power(struct urtwn_softc *); 220static int urtwn_read_chipid(struct urtwn_softc *); 221static void urtwn_read_rom(struct urtwn_softc *); 222static void urtwn_r88e_read_rom(struct urtwn_softc *); 223static int urtwn_ra_init(struct urtwn_softc *); 224static void urtwn_tsf_sync_enable(struct urtwn_softc *); 225static void urtwn_set_led(struct urtwn_softc *, int, int); 226static int urtwn_newstate(struct ieee80211vap *, 227 enum ieee80211_state, int); 228static void urtwn_watchdog(void *); 229static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 230static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 231static int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 232static int urtwn_tx_start(struct urtwn_softc *, 233 struct ieee80211_node *, struct mbuf *, 234 struct urtwn_data *); 235static int urtwn_transmit(struct ieee80211com *, struct mbuf *); 236static void urtwn_start(struct urtwn_softc *); 237static void urtwn_parent(struct ieee80211com *); 238static int urtwn_r92c_power_on(struct urtwn_softc *); 239static int urtwn_r88e_power_on(struct urtwn_softc *); 240static int urtwn_llt_init(struct urtwn_softc *); 241static void urtwn_fw_reset(struct urtwn_softc *); 242static void urtwn_r88e_fw_reset(struct urtwn_softc *); 243static int urtwn_fw_loadpage(struct urtwn_softc *, int, 244 const uint8_t *, int); 245static int urtwn_load_firmware(struct urtwn_softc *); 246static int urtwn_r92c_dma_init(struct urtwn_softc *); 247static int urtwn_r88e_dma_init(struct urtwn_softc *); 248static void urtwn_mac_init(struct urtwn_softc *); 249static void urtwn_bb_init(struct urtwn_softc *); 250static void urtwn_rf_init(struct urtwn_softc *); 251static void urtwn_cam_init(struct urtwn_softc *); 252static void urtwn_pa_bias_init(struct urtwn_softc *); 253static void urtwn_rxfilter_init(struct urtwn_softc *); 254static void urtwn_edca_init(struct urtwn_softc *); 255static void urtwn_write_txpower(struct urtwn_softc *, int, 256 uint16_t[]); 257static void urtwn_get_txpower(struct urtwn_softc *, int, 258 struct ieee80211_channel *, 259 struct ieee80211_channel *, uint16_t[]); 260static void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 261 struct ieee80211_channel *, 262 struct ieee80211_channel *, uint16_t[]); 263static void urtwn_set_txpower(struct urtwn_softc *, 264 struct ieee80211_channel *, 265 struct ieee80211_channel *); 266static void urtwn_scan_start(struct ieee80211com *); 267static void urtwn_scan_end(struct ieee80211com *); 268static void urtwn_set_channel(struct ieee80211com *); 269static void urtwn_update_mcast(struct ieee80211com *); 270static void urtwn_set_chan(struct urtwn_softc *, 271 struct ieee80211_channel *, 272 struct ieee80211_channel *); 273static void urtwn_iq_calib(struct urtwn_softc *); 274static void urtwn_lc_calib(struct urtwn_softc *); 275static void urtwn_init(struct urtwn_softc *); 276static void urtwn_stop(struct urtwn_softc *); 277static void urtwn_abort_xfers(struct urtwn_softc *); 278static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 279 const struct ieee80211_bpf_params *); 280static void urtwn_ms_delay(struct urtwn_softc *); 281 282/* Aliases. */ 283#define urtwn_bb_write urtwn_write_4 284#define urtwn_bb_read urtwn_read_4 285 286static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 287 [URTWN_BULK_RX] = { 288 .type = UE_BULK, 289 .endpoint = UE_ADDR_ANY, 290 .direction = UE_DIR_IN, 291 .bufsize = URTWN_RXBUFSZ, 292 .flags = { 293 .pipe_bof = 1, 294 .short_xfer_ok = 1 295 }, 296 .callback = urtwn_bulk_rx_callback, 297 }, 298 [URTWN_BULK_TX_BE] = { 299 .type = UE_BULK, 300 .endpoint = 0x03, 301 .direction = UE_DIR_OUT, 302 .bufsize = URTWN_TXBUFSZ, 303 .flags = { 304 .ext_buffer = 1, 305 .pipe_bof = 1, 306 .force_short_xfer = 1 307 }, 308 .callback = urtwn_bulk_tx_callback, 309 .timeout = URTWN_TX_TIMEOUT, /* ms */ 310 }, 311 [URTWN_BULK_TX_BK] = { 312 .type = UE_BULK, 313 .endpoint = 0x03, 314 .direction = UE_DIR_OUT, 315 .bufsize = URTWN_TXBUFSZ, 316 .flags = { 317 .ext_buffer = 1, 318 .pipe_bof = 1, 319 .force_short_xfer = 1, 320 }, 321 .callback = urtwn_bulk_tx_callback, 322 .timeout = URTWN_TX_TIMEOUT, /* ms */ 323 }, 324 [URTWN_BULK_TX_VI] = { 325 .type = UE_BULK, 326 .endpoint = 0x02, 327 .direction = UE_DIR_OUT, 328 .bufsize = URTWN_TXBUFSZ, 329 .flags = { 330 .ext_buffer = 1, 331 .pipe_bof = 1, 332 .force_short_xfer = 1 333 }, 334 .callback = urtwn_bulk_tx_callback, 335 .timeout = URTWN_TX_TIMEOUT, /* ms */ 336 }, 337 [URTWN_BULK_TX_VO] = { 338 .type = UE_BULK, 339 .endpoint = 0x02, 340 .direction = UE_DIR_OUT, 341 .bufsize = URTWN_TXBUFSZ, 342 .flags = { 343 .ext_buffer = 1, 344 .pipe_bof = 1, 345 .force_short_xfer = 1 346 }, 347 .callback = urtwn_bulk_tx_callback, 348 .timeout = URTWN_TX_TIMEOUT, /* ms */ 349 }, 350}; 351 352static int 353urtwn_match(device_t self) 354{ 355 struct usb_attach_arg *uaa = device_get_ivars(self); 356 357 if (uaa->usb_mode != USB_MODE_HOST) 358 return (ENXIO); 359 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 360 return (ENXIO); 361 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 362 return (ENXIO); 363 364 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 365} 366 367static int 368urtwn_attach(device_t self) 369{ 370 struct usb_attach_arg *uaa = device_get_ivars(self); 371 struct urtwn_softc *sc = device_get_softc(self); 372 struct ieee80211com *ic = &sc->sc_ic; 373 uint8_t iface_index, bands; 374 int error; 375 376 device_set_usb_desc(self); 377 sc->sc_udev = uaa->device; 378 sc->sc_dev = self; 379 if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 380 sc->chip |= URTWN_CHIP_88E; 381 382 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 383 MTX_NETWORK_LOCK, MTX_DEF); 384 callout_init(&sc->sc_watchdog_ch, 0); 385 mbufq_init(&sc->sc_snd, ifqmaxlen); 386 387 iface_index = URTWN_IFACE_INDEX; 388 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 389 urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 390 if (error) { 391 device_printf(self, "could not allocate USB transfers, " 392 "err=%s\n", usbd_errstr(error)); 393 goto detach; 394 } 395 396 URTWN_LOCK(sc); 397 398 error = urtwn_read_chipid(sc); 399 if (error) { 400 device_printf(sc->sc_dev, "unsupported test chip\n"); 401 URTWN_UNLOCK(sc); 402 goto detach; 403 } 404 405 /* Determine number of Tx/Rx chains. */ 406 if (sc->chip & URTWN_CHIP_92C) { 407 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 408 sc->nrxchains = 2; 409 } else { 410 sc->ntxchains = 1; 411 sc->nrxchains = 1; 412 } 413 414 if (sc->chip & URTWN_CHIP_88E) 415 urtwn_r88e_read_rom(sc); 416 else 417 urtwn_read_rom(sc); 418 419 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 420 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 421 (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 422 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 423 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 424 "8188CUS", sc->ntxchains, sc->nrxchains); 425 426 URTWN_UNLOCK(sc); 427 428 ic->ic_softc = sc; 429 ic->ic_name = device_get_nameunit(self); 430 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 431 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 432 433 /* set device capabilities */ 434 ic->ic_caps = 435 IEEE80211_C_STA /* station mode */ 436 | IEEE80211_C_MONITOR /* monitor mode */ 437 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 438 | IEEE80211_C_SHSLOT /* short slot time supported */ 439 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 440 | IEEE80211_C_WPA /* 802.11i */ 441 ; 442 443 bands = 0; 444 setbit(&bands, IEEE80211_MODE_11B); 445 setbit(&bands, IEEE80211_MODE_11G); 446 ieee80211_init_channels(ic, NULL, &bands); 447 448 ieee80211_ifattach(ic); 449 ic->ic_raw_xmit = urtwn_raw_xmit; 450 ic->ic_scan_start = urtwn_scan_start; 451 ic->ic_scan_end = urtwn_scan_end; 452 ic->ic_set_channel = urtwn_set_channel; 453 ic->ic_transmit = urtwn_transmit; 454 ic->ic_parent = urtwn_parent; 455 ic->ic_vap_create = urtwn_vap_create; 456 ic->ic_vap_delete = urtwn_vap_delete; 457 ic->ic_update_mcast = urtwn_update_mcast; 458 459 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 460 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 461 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 462 URTWN_RX_RADIOTAP_PRESENT); 463 464 if (bootverbose) 465 ieee80211_announce(ic); 466 467 return (0); 468 469detach: 470 urtwn_detach(self); 471 return (ENXIO); /* failure */ 472} 473 474static int 475urtwn_detach(device_t self) 476{ 477 struct urtwn_softc *sc = device_get_softc(self); 478 struct ieee80211com *ic = &sc->sc_ic; 479 unsigned int x; 480 481 /* Prevent further ioctls. */ 482 URTWN_LOCK(sc); 483 sc->sc_flags |= URTWN_DETACHED; 484 urtwn_stop(sc); 485 URTWN_UNLOCK(sc); 486 487 callout_drain(&sc->sc_watchdog_ch); 488 489 /* stop all USB transfers */ 490 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 491 492 /* Prevent further allocations from RX/TX data lists. */ 493 URTWN_LOCK(sc); 494 STAILQ_INIT(&sc->sc_tx_active); 495 STAILQ_INIT(&sc->sc_tx_inactive); 496 STAILQ_INIT(&sc->sc_tx_pending); 497 498 STAILQ_INIT(&sc->sc_rx_active); 499 STAILQ_INIT(&sc->sc_rx_inactive); 500 URTWN_UNLOCK(sc); 501 502 /* drain USB transfers */ 503 for (x = 0; x != URTWN_N_TRANSFER; x++) 504 usbd_transfer_drain(sc->sc_xfer[x]); 505 506 /* Free data buffers. */ 507 URTWN_LOCK(sc); 508 urtwn_free_tx_list(sc); 509 urtwn_free_rx_list(sc); 510 URTWN_UNLOCK(sc); 511 512 ieee80211_ifdetach(ic); 513 mtx_destroy(&sc->sc_mtx); 514 515 return (0); 516} 517 518static void 519urtwn_drain_mbufq(struct urtwn_softc *sc) 520{ 521 struct mbuf *m; 522 struct ieee80211_node *ni; 523 URTWN_ASSERT_LOCKED(sc); 524 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 525 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 526 m->m_pkthdr.rcvif = NULL; 527 ieee80211_free_node(ni); 528 m_freem(m); 529 } 530} 531 532static usb_error_t 533urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 534 void *data) 535{ 536 usb_error_t err; 537 int ntries = 10; 538 539 URTWN_ASSERT_LOCKED(sc); 540 541 while (ntries--) { 542 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 543 req, data, 0, NULL, 250 /* ms */); 544 if (err == 0) 545 break; 546 547 DPRINTFN(1, "Control request failed, %s (retrying)\n", 548 usbd_errstr(err)); 549 usb_pause_mtx(&sc->sc_mtx, hz / 100); 550 } 551 return (err); 552} 553 554static struct ieee80211vap * 555urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 556 enum ieee80211_opmode opmode, int flags, 557 const uint8_t bssid[IEEE80211_ADDR_LEN], 558 const uint8_t mac[IEEE80211_ADDR_LEN]) 559{ 560 struct urtwn_vap *uvp; 561 struct ieee80211vap *vap; 562 563 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 564 return (NULL); 565 566 uvp = malloc(sizeof(struct urtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 567 vap = &uvp->vap; 568 /* enable s/w bmiss handling for sta mode */ 569 570 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 571 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 572 /* out of memory */ 573 free(uvp, M_80211_VAP); 574 return (NULL); 575 } 576 577 /* override state transition machine */ 578 uvp->newstate = vap->iv_newstate; 579 vap->iv_newstate = urtwn_newstate; 580 581 /* complete setup */ 582 ieee80211_vap_attach(vap, ieee80211_media_change, 583 ieee80211_media_status, mac); 584 ic->ic_opmode = opmode; 585 return (vap); 586} 587 588static void 589urtwn_vap_delete(struct ieee80211vap *vap) 590{ 591 struct urtwn_vap *uvp = URTWN_VAP(vap); 592 593 ieee80211_vap_detach(vap); 594 free(uvp, M_80211_VAP); 595} 596 597static struct mbuf * 598urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 599{ 600 struct ieee80211com *ic = &sc->sc_ic; 601 struct ieee80211_frame *wh; 602 struct mbuf *m; 603 struct r92c_rx_stat *stat; 604 uint32_t rxdw0, rxdw3; 605 uint8_t rate; 606 int8_t rssi = 0; 607 int infosz; 608 609 /* 610 * don't pass packets to the ieee80211 framework if the driver isn't 611 * RUNNING. 612 */ 613 if (!(sc->sc_flags & URTWN_RUNNING)) 614 return (NULL); 615 616 stat = (struct r92c_rx_stat *)buf; 617 rxdw0 = le32toh(stat->rxdw0); 618 rxdw3 = le32toh(stat->rxdw3); 619 620 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 621 /* 622 * This should not happen since we setup our Rx filter 623 * to not receive these frames. 624 */ 625 counter_u64_add(ic->ic_ierrors, 1); 626 return (NULL); 627 } 628 if (pktlen < sizeof(*wh) || pktlen > MCLBYTES) { 629 counter_u64_add(ic->ic_ierrors, 1); 630 return (NULL); 631 } 632 633 rate = MS(rxdw3, R92C_RXDW3_RATE); 634 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 635 636 /* Get RSSI from PHY status descriptor if present. */ 637 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 638 if (sc->chip & URTWN_CHIP_88E) 639 rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 640 else 641 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 642 /* Update our average RSSI. */ 643 urtwn_update_avgrssi(sc, rate, rssi); 644 /* 645 * Convert the RSSI to a range that will be accepted 646 * by net80211. 647 */ 648 rssi = URTWN_RSSI(rssi); 649 } 650 651 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 652 if (m == NULL) { 653 device_printf(sc->sc_dev, "could not create RX mbuf\n"); 654 return (NULL); 655 } 656 657 /* Finalize mbuf. */ 658 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 659 memcpy(mtod(m, uint8_t *), wh, pktlen); 660 m->m_pkthdr.len = m->m_len = pktlen; 661 662 if (ieee80211_radiotap_active(ic)) { 663 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 664 665 tap->wr_flags = 0; 666 /* Map HW rate index to 802.11 rate. */ 667 if (!(rxdw3 & R92C_RXDW3_HT)) { 668 tap->wr_rate = ridx2rate[rate]; 669 } else if (rate >= 12) { /* MCS0~15. */ 670 /* Bit 7 set means HT MCS instead of rate. */ 671 tap->wr_rate = 0x80 | (rate - 12); 672 } 673 tap->wr_dbm_antsignal = rssi; 674 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 675 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 676 } 677 678 *rssi_p = rssi; 679 680 return (m); 681} 682 683static struct mbuf * 684urtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 685 int8_t *nf) 686{ 687 struct urtwn_softc *sc = data->sc; 688 struct ieee80211com *ic = &sc->sc_ic; 689 struct r92c_rx_stat *stat; 690 struct mbuf *m, *m0 = NULL, *prevm = NULL; 691 uint32_t rxdw0; 692 uint8_t *buf; 693 int len, totlen, pktlen, infosz, npkts; 694 695 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 696 697 if (len < sizeof(*stat)) { 698 counter_u64_add(ic->ic_ierrors, 1); 699 return (NULL); 700 } 701 702 buf = data->buf; 703 /* Get the number of encapsulated frames. */ 704 stat = (struct r92c_rx_stat *)buf; 705 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 706 DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 707 708 /* Process all of them. */ 709 while (npkts-- > 0) { 710 if (len < sizeof(*stat)) 711 break; 712 stat = (struct r92c_rx_stat *)buf; 713 rxdw0 = le32toh(stat->rxdw0); 714 715 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 716 if (pktlen == 0) 717 break; 718 719 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 720 721 /* Make sure everything fits in xfer. */ 722 totlen = sizeof(*stat) + infosz + pktlen; 723 if (totlen > len) 724 break; 725 726 m = urtwn_rx_frame(sc, buf, pktlen, rssi); 727 if (m0 == NULL) 728 m0 = m; 729 if (prevm == NULL) 730 prevm = m; 731 else { 732 prevm->m_next = m; 733 prevm = m; 734 } 735 736 /* Next chunk is 128-byte aligned. */ 737 totlen = (totlen + 127) & ~127; 738 buf += totlen; 739 len -= totlen; 740 } 741 742 return (m0); 743} 744 745static void 746urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 747{ 748 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 749 struct ieee80211com *ic = &sc->sc_ic; 750 struct ieee80211_frame *wh; 751 struct ieee80211_node *ni; 752 struct mbuf *m = NULL, *next; 753 struct urtwn_data *data; 754 int8_t nf; 755 int rssi = 1; 756 757 URTWN_ASSERT_LOCKED(sc); 758 759 switch (USB_GET_STATE(xfer)) { 760 case USB_ST_TRANSFERRED: 761 data = STAILQ_FIRST(&sc->sc_rx_active); 762 if (data == NULL) 763 goto tr_setup; 764 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 765 m = urtwn_rxeof(xfer, data, &rssi, &nf); 766 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 767 /* FALLTHROUGH */ 768 case USB_ST_SETUP: 769tr_setup: 770 data = STAILQ_FIRST(&sc->sc_rx_inactive); 771 if (data == NULL) { 772 KASSERT(m == NULL, ("mbuf isn't NULL")); 773 return; 774 } 775 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 776 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 777 usbd_xfer_set_frame_data(xfer, 0, data->buf, 778 usbd_xfer_max_len(xfer)); 779 usbd_transfer_submit(xfer); 780 781 /* 782 * To avoid LOR we should unlock our private mutex here to call 783 * ieee80211_input() because here is at the end of a USB 784 * callback and safe to unlock. 785 */ 786 URTWN_UNLOCK(sc); 787 while (m != NULL) { 788 next = m->m_next; 789 m->m_next = NULL; 790 wh = mtod(m, struct ieee80211_frame *); 791 ni = ieee80211_find_rxnode(ic, 792 (struct ieee80211_frame_min *)wh); 793 nf = URTWN_NOISE_FLOOR; 794 if (ni != NULL) { 795 (void)ieee80211_input(ni, m, rssi, nf); 796 ieee80211_free_node(ni); 797 } else 798 (void)ieee80211_input_all(ic, m, rssi, nf); 799 m = next; 800 } 801 URTWN_LOCK(sc); 802 break; 803 default: 804 /* needs it to the inactive queue due to a error. */ 805 data = STAILQ_FIRST(&sc->sc_rx_active); 806 if (data != NULL) { 807 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 808 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 809 } 810 if (error != USB_ERR_CANCELLED) { 811 usbd_xfer_set_stall(xfer); 812 counter_u64_add(ic->ic_ierrors, 1); 813 goto tr_setup; 814 } 815 break; 816 } 817} 818 819static void 820urtwn_txeof(struct usb_xfer *xfer, struct urtwn_data *data) 821{ 822 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 823 824 URTWN_ASSERT_LOCKED(sc); 825 /* XXX status? */ 826 ieee80211_tx_complete(data->ni, data->m, 0); 827 data->ni = NULL; 828 data->m = NULL; 829 sc->sc_txtimer = 0; 830} 831 832static int 833urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 834 int ndata, int maxsz) 835{ 836 int i, error; 837 838 for (i = 0; i < ndata; i++) { 839 struct urtwn_data *dp = &data[i]; 840 dp->sc = sc; 841 dp->m = NULL; 842 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 843 if (dp->buf == NULL) { 844 device_printf(sc->sc_dev, 845 "could not allocate buffer\n"); 846 error = ENOMEM; 847 goto fail; 848 } 849 dp->ni = NULL; 850 } 851 852 return (0); 853fail: 854 urtwn_free_list(sc, data, ndata); 855 return (error); 856} 857 858static int 859urtwn_alloc_rx_list(struct urtwn_softc *sc) 860{ 861 int error, i; 862 863 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 864 URTWN_RXBUFSZ); 865 if (error != 0) 866 return (error); 867 868 STAILQ_INIT(&sc->sc_rx_active); 869 STAILQ_INIT(&sc->sc_rx_inactive); 870 871 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 872 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 873 874 return (0); 875} 876 877static int 878urtwn_alloc_tx_list(struct urtwn_softc *sc) 879{ 880 int error, i; 881 882 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 883 URTWN_TXBUFSZ); 884 if (error != 0) 885 return (error); 886 887 STAILQ_INIT(&sc->sc_tx_active); 888 STAILQ_INIT(&sc->sc_tx_inactive); 889 STAILQ_INIT(&sc->sc_tx_pending); 890 891 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 892 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 893 894 return (0); 895} 896 897static void 898urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 899{ 900 int i; 901 902 for (i = 0; i < ndata; i++) { 903 struct urtwn_data *dp = &data[i]; 904 905 if (dp->buf != NULL) { 906 free(dp->buf, M_USBDEV); 907 dp->buf = NULL; 908 } 909 if (dp->ni != NULL) { 910 ieee80211_free_node(dp->ni); 911 dp->ni = NULL; 912 } 913 } 914} 915 916static void 917urtwn_free_rx_list(struct urtwn_softc *sc) 918{ 919 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 920} 921 922static void 923urtwn_free_tx_list(struct urtwn_softc *sc) 924{ 925 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 926} 927 928static void 929urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 930{ 931 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 932 struct urtwn_data *data; 933 934 URTWN_ASSERT_LOCKED(sc); 935 936 switch (USB_GET_STATE(xfer)){ 937 case USB_ST_TRANSFERRED: 938 data = STAILQ_FIRST(&sc->sc_tx_active); 939 if (data == NULL) 940 goto tr_setup; 941 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 942 urtwn_txeof(xfer, data); 943 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 944 /* FALLTHROUGH */ 945 case USB_ST_SETUP: 946tr_setup: 947 data = STAILQ_FIRST(&sc->sc_tx_pending); 948 if (data == NULL) { 949 DPRINTF("%s: empty pending queue\n", __func__); 950 goto finish; 951 } 952 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 953 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 954 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 955 usbd_transfer_submit(xfer); 956 break; 957 default: 958 data = STAILQ_FIRST(&sc->sc_tx_active); 959 if (data == NULL) 960 goto tr_setup; 961 if (data->ni != NULL) { 962 if_inc_counter(data->ni->ni_vap->iv_ifp, 963 IFCOUNTER_OERRORS, 1); 964 ieee80211_free_node(data->ni); 965 data->ni = NULL; 966 } 967 if (error != USB_ERR_CANCELLED) { 968 usbd_xfer_set_stall(xfer); 969 goto tr_setup; 970 } 971 break; 972 } 973finish: 974 /* Kick-start more transmit */ 975 urtwn_start(sc); 976} 977 978static struct urtwn_data * 979_urtwn_getbuf(struct urtwn_softc *sc) 980{ 981 struct urtwn_data *bf; 982 983 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 984 if (bf != NULL) 985 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 986 else 987 bf = NULL; 988 if (bf == NULL) 989 DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 990 return (bf); 991} 992 993static struct urtwn_data * 994urtwn_getbuf(struct urtwn_softc *sc) 995{ 996 struct urtwn_data *bf; 997 998 URTWN_ASSERT_LOCKED(sc); 999 1000 bf = _urtwn_getbuf(sc); 1001 if (bf == NULL) 1002 DPRINTF("%s: stop queue\n", __func__); 1003 return (bf); 1004} 1005 1006static int 1007urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1008 int len) 1009{ 1010 usb_device_request_t req; 1011 1012 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1013 req.bRequest = R92C_REQ_REGS; 1014 USETW(req.wValue, addr); 1015 USETW(req.wIndex, 0); 1016 USETW(req.wLength, len); 1017 return (urtwn_do_request(sc, &req, buf)); 1018} 1019 1020static void 1021urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 1022{ 1023 urtwn_write_region_1(sc, addr, &val, 1); 1024} 1025 1026 1027static void 1028urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1029{ 1030 val = htole16(val); 1031 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 1032} 1033 1034static void 1035urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1036{ 1037 val = htole32(val); 1038 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 1039} 1040 1041static int 1042urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1043 int len) 1044{ 1045 usb_device_request_t req; 1046 1047 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1048 req.bRequest = R92C_REQ_REGS; 1049 USETW(req.wValue, addr); 1050 USETW(req.wIndex, 0); 1051 USETW(req.wLength, len); 1052 return (urtwn_do_request(sc, &req, buf)); 1053} 1054 1055static uint8_t 1056urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1057{ 1058 uint8_t val; 1059 1060 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1061 return (0xff); 1062 return (val); 1063} 1064 1065static uint16_t 1066urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1067{ 1068 uint16_t val; 1069 1070 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1071 return (0xffff); 1072 return (le16toh(val)); 1073} 1074 1075static uint32_t 1076urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1077{ 1078 uint32_t val; 1079 1080 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1081 return (0xffffffff); 1082 return (le32toh(val)); 1083} 1084 1085static int 1086urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1087{ 1088 struct r92c_fw_cmd cmd; 1089 int ntries; 1090 1091 /* Wait for current FW box to be empty. */ 1092 for (ntries = 0; ntries < 100; ntries++) { 1093 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1094 break; 1095 urtwn_ms_delay(sc); 1096 } 1097 if (ntries == 100) { 1098 device_printf(sc->sc_dev, 1099 "could not send firmware command\n"); 1100 return (ETIMEDOUT); 1101 } 1102 memset(&cmd, 0, sizeof(cmd)); 1103 cmd.id = id; 1104 if (len > 3) 1105 cmd.id |= R92C_CMD_FLAG_EXT; 1106 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1107 memcpy(cmd.msg, buf, len); 1108 1109 /* Write the first word last since that will trigger the FW. */ 1110 urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1111 (uint8_t *)&cmd + 4, 2); 1112 urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1113 (uint8_t *)&cmd + 0, 4); 1114 1115 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1116 return (0); 1117} 1118 1119static __inline void 1120urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1121{ 1122 1123 sc->sc_rf_write(sc, chain, addr, val); 1124} 1125 1126static void 1127urtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1128 uint32_t val) 1129{ 1130 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1131 SM(R92C_LSSI_PARAM_ADDR, addr) | 1132 SM(R92C_LSSI_PARAM_DATA, val)); 1133} 1134 1135static void 1136urtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1137uint32_t val) 1138{ 1139 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1140 SM(R88E_LSSI_PARAM_ADDR, addr) | 1141 SM(R92C_LSSI_PARAM_DATA, val)); 1142} 1143 1144static uint32_t 1145urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1146{ 1147 uint32_t reg[R92C_MAX_CHAINS], val; 1148 1149 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1150 if (chain != 0) 1151 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1152 1153 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1154 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1155 urtwn_ms_delay(sc); 1156 1157 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1158 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1159 R92C_HSSI_PARAM2_READ_EDGE); 1160 urtwn_ms_delay(sc); 1161 1162 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1163 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1164 urtwn_ms_delay(sc); 1165 1166 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1167 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1168 else 1169 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1170 return (MS(val, R92C_LSSI_READBACK_DATA)); 1171} 1172 1173static int 1174urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1175{ 1176 int ntries; 1177 1178 urtwn_write_4(sc, R92C_LLT_INIT, 1179 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1180 SM(R92C_LLT_INIT_ADDR, addr) | 1181 SM(R92C_LLT_INIT_DATA, data)); 1182 /* Wait for write operation to complete. */ 1183 for (ntries = 0; ntries < 20; ntries++) { 1184 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1185 R92C_LLT_INIT_OP_NO_ACTIVE) 1186 return (0); 1187 urtwn_ms_delay(sc); 1188 } 1189 return (ETIMEDOUT); 1190} 1191 1192static uint8_t 1193urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1194{ 1195 uint32_t reg; 1196 int ntries; 1197 1198 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1199 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1200 reg &= ~R92C_EFUSE_CTRL_VALID; 1201 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1202 /* Wait for read operation to complete. */ 1203 for (ntries = 0; ntries < 100; ntries++) { 1204 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1205 if (reg & R92C_EFUSE_CTRL_VALID) 1206 return (MS(reg, R92C_EFUSE_CTRL_DATA)); 1207 urtwn_ms_delay(sc); 1208 } 1209 device_printf(sc->sc_dev, 1210 "could not read efuse byte at address 0x%x\n", addr); 1211 return (0xff); 1212} 1213 1214static void 1215urtwn_efuse_read(struct urtwn_softc *sc) 1216{ 1217 uint8_t *rom = (uint8_t *)&sc->rom; 1218 uint16_t addr = 0; 1219 uint32_t reg; 1220 uint8_t off, msk; 1221 int i; 1222 1223 urtwn_efuse_switch_power(sc); 1224 1225 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1226 while (addr < 512) { 1227 reg = urtwn_efuse_read_1(sc, addr); 1228 if (reg == 0xff) 1229 break; 1230 addr++; 1231 off = reg >> 4; 1232 msk = reg & 0xf; 1233 for (i = 0; i < 4; i++) { 1234 if (msk & (1 << i)) 1235 continue; 1236 rom[off * 8 + i * 2 + 0] = 1237 urtwn_efuse_read_1(sc, addr); 1238 addr++; 1239 rom[off * 8 + i * 2 + 1] = 1240 urtwn_efuse_read_1(sc, addr); 1241 addr++; 1242 } 1243 } 1244#ifdef URTWN_DEBUG 1245 if (urtwn_debug >= 2) { 1246 /* Dump ROM content. */ 1247 printf("\n"); 1248 for (i = 0; i < sizeof(sc->rom); i++) 1249 printf("%02x:", rom[i]); 1250 printf("\n"); 1251 } 1252#endif 1253 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1254} 1255 1256static void 1257urtwn_efuse_switch_power(struct urtwn_softc *sc) 1258{ 1259 uint32_t reg; 1260 1261 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1262 1263 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1264 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1265 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1266 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1267 } 1268 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1269 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1270 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1271 reg | R92C_SYS_FUNC_EN_ELDR); 1272 } 1273 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1274 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1275 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1276 urtwn_write_2(sc, R92C_SYS_CLKR, 1277 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1278 } 1279} 1280 1281static int 1282urtwn_read_chipid(struct urtwn_softc *sc) 1283{ 1284 uint32_t reg; 1285 1286 if (sc->chip & URTWN_CHIP_88E) 1287 return (0); 1288 1289 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1290 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1291 return (EIO); 1292 1293 if (reg & R92C_SYS_CFG_TYPE_92C) { 1294 sc->chip |= URTWN_CHIP_92C; 1295 /* Check if it is a castrated 8192C. */ 1296 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1297 R92C_HPON_FSM_CHIP_BONDING_ID) == 1298 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1299 sc->chip |= URTWN_CHIP_92C_1T2R; 1300 } 1301 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1302 sc->chip |= URTWN_CHIP_UMC; 1303 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1304 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1305 } 1306 return (0); 1307} 1308 1309static void 1310urtwn_read_rom(struct urtwn_softc *sc) 1311{ 1312 struct r92c_rom *rom = &sc->rom; 1313 1314 /* Read full ROM image. */ 1315 urtwn_efuse_read(sc); 1316 1317 /* XXX Weird but this is what the vendor driver does. */ 1318 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1319 DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1320 1321 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1322 1323 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1324 DPRINTF("regulatory type=%d\n", sc->regulatory); 1325 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1326 1327 sc->sc_rf_write = urtwn_r92c_rf_write; 1328 sc->sc_power_on = urtwn_r92c_power_on; 1329 sc->sc_dma_init = urtwn_r92c_dma_init; 1330} 1331 1332static void 1333urtwn_r88e_read_rom(struct urtwn_softc *sc) 1334{ 1335 uint8_t *rom = sc->r88e_rom; 1336 uint16_t addr = 0; 1337 uint32_t reg; 1338 uint8_t off, msk, tmp; 1339 int i; 1340 1341 off = 0; 1342 urtwn_efuse_switch_power(sc); 1343 1344 /* Read full ROM image. */ 1345 memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1346 while (addr < 512) { 1347 reg = urtwn_efuse_read_1(sc, addr); 1348 if (reg == 0xff) 1349 break; 1350 addr++; 1351 if ((reg & 0x1f) == 0x0f) { 1352 tmp = (reg & 0xe0) >> 5; 1353 reg = urtwn_efuse_read_1(sc, addr); 1354 if ((reg & 0x0f) != 0x0f) 1355 off = ((reg & 0xf0) >> 1) | tmp; 1356 addr++; 1357 } else 1358 off = reg >> 4; 1359 msk = reg & 0xf; 1360 for (i = 0; i < 4; i++) { 1361 if (msk & (1 << i)) 1362 continue; 1363 rom[off * 8 + i * 2 + 0] = 1364 urtwn_efuse_read_1(sc, addr); 1365 addr++; 1366 rom[off * 8 + i * 2 + 1] = 1367 urtwn_efuse_read_1(sc, addr); 1368 addr++; 1369 } 1370 } 1371 1372 urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1373 1374 addr = 0x10; 1375 for (i = 0; i < 6; i++) 1376 sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1377 for (i = 0; i < 5; i++) 1378 sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1379 sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1380 if (sc->bw20_tx_pwr_diff & 0x08) 1381 sc->bw20_tx_pwr_diff |= 0xf0; 1382 sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1383 if (sc->ofdm_tx_pwr_diff & 0x08) 1384 sc->ofdm_tx_pwr_diff |= 0xf0; 1385 sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1386 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, &sc->r88e_rom[0xd7]); 1387 1388 sc->sc_rf_write = urtwn_r88e_rf_write; 1389 sc->sc_power_on = urtwn_r88e_power_on; 1390 sc->sc_dma_init = urtwn_r88e_dma_init; 1391} 1392 1393/* 1394 * Initialize rate adaptation in firmware. 1395 */ 1396static int 1397urtwn_ra_init(struct urtwn_softc *sc) 1398{ 1399 struct ieee80211com *ic = &sc->sc_ic; 1400 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1401 struct ieee80211_node *ni; 1402 struct ieee80211_rateset *rs; 1403 struct r92c_fw_cmd_macid_cfg cmd; 1404 uint32_t rates, basicrates; 1405 uint8_t mode; 1406 int maxrate, maxbasicrate, error, i, j; 1407 1408 ni = ieee80211_ref_node(vap->iv_bss); 1409 rs = &ni->ni_rates; 1410 1411 /* Get normal and basic rates mask. */ 1412 rates = basicrates = 0; 1413 maxrate = maxbasicrate = 0; 1414 for (i = 0; i < rs->rs_nrates; i++) { 1415 /* Convert 802.11 rate to HW rate index. */ 1416 for (j = 0; j < nitems(ridx2rate); j++) 1417 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == 1418 ridx2rate[j]) 1419 break; 1420 if (j == nitems(ridx2rate)) /* Unknown rate, skip. */ 1421 continue; 1422 rates |= 1 << j; 1423 if (j > maxrate) 1424 maxrate = j; 1425 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1426 basicrates |= 1 << j; 1427 if (j > maxbasicrate) 1428 maxbasicrate = j; 1429 } 1430 } 1431 if (ic->ic_curmode == IEEE80211_MODE_11B) 1432 mode = R92C_RAID_11B; 1433 else 1434 mode = R92C_RAID_11BG; 1435 DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1436 mode, rates, basicrates); 1437 1438 /* Set rates mask for group addressed frames. */ 1439 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1440 cmd.mask = htole32(mode << 28 | basicrates); 1441 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1442 if (error != 0) { 1443 ieee80211_free_node(ni); 1444 device_printf(sc->sc_dev, 1445 "could not add broadcast station\n"); 1446 return (error); 1447 } 1448 /* Set initial MRR rate. */ 1449 DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1450 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1451 maxbasicrate); 1452 1453 /* Set rates mask for unicast frames. */ 1454 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1455 cmd.mask = htole32(mode << 28 | rates); 1456 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1457 if (error != 0) { 1458 ieee80211_free_node(ni); 1459 device_printf(sc->sc_dev, "could not add BSS station\n"); 1460 return (error); 1461 } 1462 /* Set initial MRR rate. */ 1463 DPRINTF("maxrate=%d\n", maxrate); 1464 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1465 maxrate); 1466 1467 /* Indicate highest supported rate. */ 1468 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1469 ieee80211_free_node(ni); 1470 1471 return (0); 1472} 1473 1474void 1475urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1476{ 1477 struct ieee80211com *ic = &sc->sc_ic; 1478 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1479 struct ieee80211_node *ni = vap->iv_bss; 1480 1481 uint64_t tsf; 1482 1483 /* Enable TSF synchronization. */ 1484 urtwn_write_1(sc, R92C_BCN_CTRL, 1485 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1486 1487 urtwn_write_1(sc, R92C_BCN_CTRL, 1488 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1489 1490 /* Set initial TSF. */ 1491 memcpy(&tsf, ni->ni_tstamp.data, 8); 1492 tsf = le64toh(tsf); 1493 tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU)); 1494 tsf -= IEEE80211_DUR_TU; 1495 urtwn_write_4(sc, R92C_TSFTR + 0, tsf); 1496 urtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32); 1497 1498 urtwn_write_1(sc, R92C_BCN_CTRL, 1499 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1500} 1501 1502static void 1503urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1504{ 1505 uint8_t reg; 1506 1507 if (led == URTWN_LED_LINK) { 1508 if (sc->chip & URTWN_CHIP_88E) { 1509 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1510 urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1511 if (!on) { 1512 reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1513 urtwn_write_1(sc, R92C_LEDCFG2, 1514 reg | R92C_LEDCFG0_DIS); 1515 urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1516 urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 1517 0xfe); 1518 } 1519 } else { 1520 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1521 if (!on) 1522 reg |= R92C_LEDCFG0_DIS; 1523 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1524 } 1525 sc->ledlink = on; /* Save LED state. */ 1526 } 1527} 1528 1529static int 1530urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1531{ 1532 struct urtwn_vap *uvp = URTWN_VAP(vap); 1533 struct ieee80211com *ic = vap->iv_ic; 1534 struct urtwn_softc *sc = ic->ic_softc; 1535 struct ieee80211_node *ni; 1536 enum ieee80211_state ostate; 1537 uint32_t reg; 1538 1539 ostate = vap->iv_state; 1540 DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 1541 ieee80211_state_name[nstate]); 1542 1543 IEEE80211_UNLOCK(ic); 1544 URTWN_LOCK(sc); 1545 callout_stop(&sc->sc_watchdog_ch); 1546 1547 if (ostate == IEEE80211_S_RUN) { 1548 /* Turn link LED off. */ 1549 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1550 1551 /* Set media status to 'No Link'. */ 1552 reg = urtwn_read_4(sc, R92C_CR); 1553 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK); 1554 urtwn_write_4(sc, R92C_CR, reg); 1555 1556 /* Stop Rx of data frames. */ 1557 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1558 1559 /* Rest TSF. */ 1560 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1561 1562 /* Disable TSF synchronization. */ 1563 urtwn_write_1(sc, R92C_BCN_CTRL, 1564 urtwn_read_1(sc, R92C_BCN_CTRL) | 1565 R92C_BCN_CTRL_DIS_TSF_UDT0); 1566 1567 /* Reset EDCA parameters. */ 1568 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1569 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1570 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1571 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1572 } 1573 1574 switch (nstate) { 1575 case IEEE80211_S_INIT: 1576 /* Turn link LED off. */ 1577 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1578 break; 1579 case IEEE80211_S_SCAN: 1580 if (ostate != IEEE80211_S_SCAN) { 1581 /* Allow Rx from any BSSID. */ 1582 urtwn_write_4(sc, R92C_RCR, 1583 urtwn_read_4(sc, R92C_RCR) & 1584 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1585 1586 /* Set gain for scanning. */ 1587 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1588 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1589 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1590 1591 if (!(sc->chip & URTWN_CHIP_88E)) { 1592 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1593 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1594 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1595 } 1596 } 1597 /* Pause AC Tx queues. */ 1598 urtwn_write_1(sc, R92C_TXPAUSE, 1599 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1600 break; 1601 case IEEE80211_S_AUTH: 1602 /* Set initial gain under link. */ 1603 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1604 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1605 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1606 1607 if (!(sc->chip & URTWN_CHIP_88E)) { 1608 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1609 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1610 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1611 } 1612 urtwn_set_chan(sc, ic->ic_curchan, NULL); 1613 break; 1614 case IEEE80211_S_RUN: 1615 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1616 /* Enable Rx of data frames. */ 1617 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1618 1619 /* Enable Rx of ctrl frames. */ 1620 urtwn_write_2(sc, R92C_RXFLTMAP1, 0xffff); 1621 1622 /* 1623 * Accept data/control/management frames 1624 * from any BSSID. 1625 */ 1626 urtwn_write_4(sc, R92C_RCR, 1627 (urtwn_read_4(sc, R92C_RCR) & ~(R92C_RCR_APM | 1628 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)) | 1629 R92C_RCR_ADF | R92C_RCR_ACF | R92C_RCR_AMF | 1630 R92C_RCR_AAP); 1631 1632 /* Turn link LED on. */ 1633 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1634 break; 1635 } 1636 1637 ni = ieee80211_ref_node(vap->iv_bss); 1638 /* Set media status to 'Associated'. */ 1639 reg = urtwn_read_4(sc, R92C_CR); 1640 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 1641 urtwn_write_4(sc, R92C_CR, reg); 1642 1643 /* Set BSSID. */ 1644 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1645 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1646 1647 if (ic->ic_curmode == IEEE80211_MODE_11B) 1648 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1649 else /* 802.11b/g */ 1650 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1651 1652 /* Enable Rx of data frames. */ 1653 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1654 1655 /* Flush all AC queues. */ 1656 urtwn_write_1(sc, R92C_TXPAUSE, 0); 1657 1658 /* Set beacon interval. */ 1659 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1660 1661 /* Allow Rx from our BSSID only. */ 1662 urtwn_write_4(sc, R92C_RCR, 1663 urtwn_read_4(sc, R92C_RCR) | 1664 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1665 1666 /* Enable TSF synchronization. */ 1667 urtwn_tsf_sync_enable(sc); 1668 1669 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1670 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1671 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1672 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1673 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1674 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1675 1676 /* Intialize rate adaptation. */ 1677 if (sc->chip & URTWN_CHIP_88E) 1678 ni->ni_txrate = 1679 ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1]; 1680 else 1681 urtwn_ra_init(sc); 1682 /* Turn link LED on. */ 1683 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1684 1685 sc->avg_pwdb = -1; /* Reset average RSSI. */ 1686 /* Reset temperature calibration state machine. */ 1687 sc->thcal_state = 0; 1688 sc->thcal_lctemp = 0; 1689 ieee80211_free_node(ni); 1690 break; 1691 default: 1692 break; 1693 } 1694 URTWN_UNLOCK(sc); 1695 IEEE80211_LOCK(ic); 1696 return(uvp->newstate(vap, nstate, arg)); 1697} 1698 1699static void 1700urtwn_watchdog(void *arg) 1701{ 1702 struct urtwn_softc *sc = arg; 1703 1704 if (sc->sc_txtimer > 0) { 1705 if (--sc->sc_txtimer == 0) { 1706 device_printf(sc->sc_dev, "device timeout\n"); 1707 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1708 return; 1709 } 1710 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1711 } 1712} 1713 1714static void 1715urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1716{ 1717 int pwdb; 1718 1719 /* Convert antenna signal to percentage. */ 1720 if (rssi <= -100 || rssi >= 20) 1721 pwdb = 0; 1722 else if (rssi >= 0) 1723 pwdb = 100; 1724 else 1725 pwdb = 100 + rssi; 1726 if (!(sc->chip & URTWN_CHIP_88E)) { 1727 if (rate <= URTWN_RIDX_CCK11) { 1728 /* CCK gain is smaller than OFDM/MCS gain. */ 1729 pwdb += 6; 1730 if (pwdb > 100) 1731 pwdb = 100; 1732 if (pwdb <= 14) 1733 pwdb -= 4; 1734 else if (pwdb <= 26) 1735 pwdb -= 8; 1736 else if (pwdb <= 34) 1737 pwdb -= 6; 1738 else if (pwdb <= 42) 1739 pwdb -= 2; 1740 } 1741 } 1742 if (sc->avg_pwdb == -1) /* Init. */ 1743 sc->avg_pwdb = pwdb; 1744 else if (sc->avg_pwdb < pwdb) 1745 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1746 else 1747 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1748 DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 1749} 1750 1751static int8_t 1752urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1753{ 1754 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1755 struct r92c_rx_phystat *phy; 1756 struct r92c_rx_cck *cck; 1757 uint8_t rpt; 1758 int8_t rssi; 1759 1760 if (rate <= URTWN_RIDX_CCK11) { 1761 cck = (struct r92c_rx_cck *)physt; 1762 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 1763 rpt = (cck->agc_rpt >> 5) & 0x3; 1764 rssi = (cck->agc_rpt & 0x1f) << 1; 1765 } else { 1766 rpt = (cck->agc_rpt >> 6) & 0x3; 1767 rssi = cck->agc_rpt & 0x3e; 1768 } 1769 rssi = cckoff[rpt] - rssi; 1770 } else { /* OFDM/HT. */ 1771 phy = (struct r92c_rx_phystat *)physt; 1772 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1773 } 1774 return (rssi); 1775} 1776 1777static int8_t 1778urtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1779{ 1780 struct r92c_rx_phystat *phy; 1781 struct r88e_rx_cck *cck; 1782 uint8_t cck_agc_rpt, lna_idx, vga_idx; 1783 int8_t rssi; 1784 1785 rssi = 0; 1786 if (rate <= URTWN_RIDX_CCK11) { 1787 cck = (struct r88e_rx_cck *)physt; 1788 cck_agc_rpt = cck->agc_rpt; 1789 lna_idx = (cck_agc_rpt & 0xe0) >> 5; 1790 vga_idx = cck_agc_rpt & 0x1f; 1791 switch (lna_idx) { 1792 case 7: 1793 if (vga_idx <= 27) 1794 rssi = -100 + 2* (27 - vga_idx); 1795 else 1796 rssi = -100; 1797 break; 1798 case 6: 1799 rssi = -48 + 2 * (2 - vga_idx); 1800 break; 1801 case 5: 1802 rssi = -42 + 2 * (7 - vga_idx); 1803 break; 1804 case 4: 1805 rssi = -36 + 2 * (7 - vga_idx); 1806 break; 1807 case 3: 1808 rssi = -24 + 2 * (7 - vga_idx); 1809 break; 1810 case 2: 1811 rssi = -12 + 2 * (5 - vga_idx); 1812 break; 1813 case 1: 1814 rssi = 8 - (2 * vga_idx); 1815 break; 1816 case 0: 1817 rssi = 14 - (2 * vga_idx); 1818 break; 1819 } 1820 rssi += 6; 1821 } else { /* OFDM/HT. */ 1822 phy = (struct r92c_rx_phystat *)physt; 1823 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1824 } 1825 return (rssi); 1826} 1827 1828static int 1829urtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni, 1830 struct mbuf *m0, struct urtwn_data *data) 1831{ 1832 struct ieee80211_frame *wh; 1833 struct ieee80211_key *k; 1834 struct ieee80211com *ic = &sc->sc_ic; 1835 struct ieee80211vap *vap = ni->ni_vap; 1836 struct usb_xfer *xfer; 1837 struct r92c_tx_desc *txd; 1838 uint8_t raid, type; 1839 uint16_t sum; 1840 int i, xferlen; 1841 struct usb_xfer *urtwn_pipes[4] = { 1842 sc->sc_xfer[URTWN_BULK_TX_BE], 1843 sc->sc_xfer[URTWN_BULK_TX_BK], 1844 sc->sc_xfer[URTWN_BULK_TX_VI], 1845 sc->sc_xfer[URTWN_BULK_TX_VO] 1846 }; 1847 1848 URTWN_ASSERT_LOCKED(sc); 1849 1850 /* 1851 * Software crypto. 1852 */ 1853 wh = mtod(m0, struct ieee80211_frame *); 1854 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1855 1856 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1857 k = ieee80211_crypto_encap(ni, m0); 1858 if (k == NULL) { 1859 device_printf(sc->sc_dev, 1860 "ieee80211_crypto_encap returns NULL.\n"); 1861 /* XXX we don't expect the fragmented frames */ 1862 return (ENOBUFS); 1863 } 1864 1865 /* in case packet header moved, reset pointer */ 1866 wh = mtod(m0, struct ieee80211_frame *); 1867 } 1868 1869 switch (type) { 1870 case IEEE80211_FC0_TYPE_CTL: 1871 case IEEE80211_FC0_TYPE_MGT: 1872 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 1873 break; 1874 default: 1875 KASSERT(M_WME_GETAC(m0) < 4, 1876 ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1877 xfer = urtwn_pipes[M_WME_GETAC(m0)]; 1878 break; 1879 } 1880 1881 /* Fill Tx descriptor. */ 1882 txd = (struct r92c_tx_desc *)data->buf; 1883 memset(txd, 0, sizeof(*txd)); 1884 1885 txd->txdw0 |= htole32( 1886 SM(R92C_TXDW0_PKTLEN, m0->m_pkthdr.len) | 1887 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1888 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1889 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1890 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1891 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1892 type == IEEE80211_FC0_TYPE_DATA) { 1893 if (ic->ic_curmode == IEEE80211_MODE_11B) 1894 raid = R92C_RAID_11B; 1895 else 1896 raid = R92C_RAID_11BG; 1897 if (sc->chip & URTWN_CHIP_88E) { 1898 txd->txdw1 |= htole32( 1899 SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) | 1900 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1901 SM(R92C_TXDW1_RAID, raid)); 1902 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1903 } else { 1904 txd->txdw1 |= htole32( 1905 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 1906 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1907 SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1908 } 1909 if (ic->ic_flags & IEEE80211_F_USEPROT) { 1910 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1911 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1912 R92C_TXDW4_HWRTSEN); 1913 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1914 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1915 R92C_TXDW4_HWRTSEN); 1916 } 1917 } 1918 /* Send RTS at OFDM24. */ 1919 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 1920 URTWN_RIDX_OFDM24)); 1921 txd->txdw5 |= htole32(0x0001ff00); 1922 /* Send data at OFDM54. */ 1923 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 1924 URTWN_RIDX_OFDM54)); 1925 } else { 1926 txd->txdw1 |= htole32( 1927 SM(R92C_TXDW1_MACID, 0) | 1928 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1929 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1930 1931 /* Force CCK1. */ 1932 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1933 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 1934 URTWN_RIDX_CCK1)); 1935 } 1936 /* Set sequence number (already little endian). */ 1937 txd->txdseq |= *(uint16_t *)wh->i_seq; 1938 1939 if (!IEEE80211_QOS_HAS_SEQ(wh)) { 1940 /* Use HW sequence numbering for non-QoS frames. */ 1941 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1942 txd->txdseq |= htole16(0x8000); 1943 } else 1944 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1945 1946 /* Compute Tx descriptor checksum. */ 1947 sum = 0; 1948 for (i = 0; i < sizeof(*txd) / 2; i++) 1949 sum ^= ((uint16_t *)txd)[i]; 1950 txd->txdsum = sum; /* NB: already little endian. */ 1951 1952 if (ieee80211_radiotap_active_vap(vap)) { 1953 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1954 1955 tap->wt_flags = 0; 1956 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1957 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1958 ieee80211_radiotap_tx(vap, m0); 1959 } 1960 1961 xferlen = sizeof(*txd) + m0->m_pkthdr.len; 1962 m_copydata(m0, 0, m0->m_pkthdr.len, (caddr_t)&txd[1]); 1963 1964 data->buflen = xferlen; 1965 data->ni = ni; 1966 data->m = m0; 1967 1968 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1969 usbd_transfer_start(xfer); 1970 return (0); 1971} 1972 1973static int 1974urtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 1975{ 1976 struct urtwn_softc *sc = ic->ic_softc; 1977 int error; 1978 1979 URTWN_LOCK(sc); 1980 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 1981 URTWN_UNLOCK(sc); 1982 return (ENXIO); 1983 } 1984 error = mbufq_enqueue(&sc->sc_snd, m); 1985 if (error) { 1986 URTWN_UNLOCK(sc); 1987 return (error); 1988 } 1989 urtwn_start(sc); 1990 URTWN_UNLOCK(sc); 1991 1992 return (0); 1993} 1994 1995static void 1996urtwn_start(struct urtwn_softc *sc) 1997{ 1998 struct ieee80211_node *ni; 1999 struct mbuf *m; 2000 struct urtwn_data *bf; 2001 2002 URTWN_ASSERT_LOCKED(sc); 2003 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 2004 bf = urtwn_getbuf(sc); 2005 if (bf == NULL) { 2006 mbufq_prepend(&sc->sc_snd, m); 2007 break; 2008 } 2009 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 2010 m->m_pkthdr.rcvif = NULL; 2011 if (urtwn_tx_start(sc, ni, m, bf) != 0) { 2012 if_inc_counter(ni->ni_vap->iv_ifp, 2013 IFCOUNTER_OERRORS, 1); 2014 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 2015 m_freem(m); 2016 ieee80211_free_node(ni); 2017 break; 2018 } 2019 sc->sc_txtimer = 5; 2020 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2021 } 2022} 2023 2024static void 2025urtwn_parent(struct ieee80211com *ic) 2026{ 2027 struct urtwn_softc *sc = ic->ic_softc; 2028 int startall = 0; 2029 2030 URTWN_LOCK(sc); 2031 if (sc->sc_flags & URTWN_DETACHED) { 2032 URTWN_UNLOCK(sc); 2033 return; 2034 } 2035 if (ic->ic_nrunning > 0) { 2036 if ((sc->sc_flags & URTWN_RUNNING) == 0) { 2037 urtwn_init(sc); 2038 startall = 1; 2039 } 2040 } else if (sc->sc_flags & URTWN_RUNNING) 2041 urtwn_stop(sc); 2042 URTWN_UNLOCK(sc); 2043 2044 if (startall) 2045 ieee80211_start_all(ic); 2046} 2047 2048static __inline int 2049urtwn_power_on(struct urtwn_softc *sc) 2050{ 2051 2052 return sc->sc_power_on(sc); 2053} 2054 2055static int 2056urtwn_r92c_power_on(struct urtwn_softc *sc) 2057{ 2058 uint32_t reg; 2059 int ntries; 2060 2061 /* Wait for autoload done bit. */ 2062 for (ntries = 0; ntries < 1000; ntries++) { 2063 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2064 break; 2065 urtwn_ms_delay(sc); 2066 } 2067 if (ntries == 1000) { 2068 device_printf(sc->sc_dev, 2069 "timeout waiting for chip autoload\n"); 2070 return (ETIMEDOUT); 2071 } 2072 2073 /* Unlock ISO/CLK/Power control register. */ 2074 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2075 /* Move SPS into PWM mode. */ 2076 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2077 urtwn_ms_delay(sc); 2078 2079 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2080 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2081 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2082 reg | R92C_LDOV12D_CTRL_LDV12_EN); 2083 urtwn_ms_delay(sc); 2084 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2085 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2086 ~R92C_SYS_ISO_CTRL_MD2PP); 2087 } 2088 2089 /* Auto enable WLAN. */ 2090 urtwn_write_2(sc, R92C_APS_FSMCO, 2091 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2092 for (ntries = 0; ntries < 1000; ntries++) { 2093 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2094 R92C_APS_FSMCO_APFM_ONMAC)) 2095 break; 2096 urtwn_ms_delay(sc); 2097 } 2098 if (ntries == 1000) { 2099 device_printf(sc->sc_dev, 2100 "timeout waiting for MAC auto ON\n"); 2101 return (ETIMEDOUT); 2102 } 2103 2104 /* Enable radio, GPIO and LED functions. */ 2105 urtwn_write_2(sc, R92C_APS_FSMCO, 2106 R92C_APS_FSMCO_AFSM_HSUS | 2107 R92C_APS_FSMCO_PDN_EN | 2108 R92C_APS_FSMCO_PFM_ALDN); 2109 /* Release RF digital isolation. */ 2110 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2111 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2112 2113 /* Initialize MAC. */ 2114 urtwn_write_1(sc, R92C_APSD_CTRL, 2115 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2116 for (ntries = 0; ntries < 200; ntries++) { 2117 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2118 R92C_APSD_CTRL_OFF_STATUS)) 2119 break; 2120 urtwn_ms_delay(sc); 2121 } 2122 if (ntries == 200) { 2123 device_printf(sc->sc_dev, 2124 "timeout waiting for MAC initialization\n"); 2125 return (ETIMEDOUT); 2126 } 2127 2128 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2129 reg = urtwn_read_2(sc, R92C_CR); 2130 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2131 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2132 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2133 R92C_CR_ENSEC; 2134 urtwn_write_2(sc, R92C_CR, reg); 2135 2136 urtwn_write_1(sc, 0xfe10, 0x19); 2137 return (0); 2138} 2139 2140static int 2141urtwn_r88e_power_on(struct urtwn_softc *sc) 2142{ 2143 uint32_t reg; 2144 int ntries; 2145 2146 /* Wait for power ready bit. */ 2147 for (ntries = 0; ntries < 5000; ntries++) { 2148 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 2149 break; 2150 urtwn_ms_delay(sc); 2151 } 2152 if (ntries == 5000) { 2153 device_printf(sc->sc_dev, 2154 "timeout waiting for chip power up\n"); 2155 return (ETIMEDOUT); 2156 } 2157 2158 /* Reset BB. */ 2159 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2160 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2161 R92C_SYS_FUNC_EN_BB_GLB_RST)); 2162 2163 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 2164 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 2165 2166 /* Disable HWPDN. */ 2167 urtwn_write_2(sc, R92C_APS_FSMCO, 2168 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 2169 2170 /* Disable WL suspend. */ 2171 urtwn_write_2(sc, R92C_APS_FSMCO, 2172 urtwn_read_2(sc, R92C_APS_FSMCO) & 2173 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 2174 2175 urtwn_write_2(sc, R92C_APS_FSMCO, 2176 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2177 for (ntries = 0; ntries < 5000; ntries++) { 2178 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2179 R92C_APS_FSMCO_APFM_ONMAC)) 2180 break; 2181 urtwn_ms_delay(sc); 2182 } 2183 if (ntries == 5000) 2184 return (ETIMEDOUT); 2185 2186 /* Enable LDO normal mode. */ 2187 urtwn_write_1(sc, R92C_LPLDO_CTRL, 2188 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 2189 2190 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2191 urtwn_write_2(sc, R92C_CR, 0); 2192 reg = urtwn_read_2(sc, R92C_CR); 2193 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2194 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2195 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2196 urtwn_write_2(sc, R92C_CR, reg); 2197 2198 return (0); 2199} 2200 2201static int 2202urtwn_llt_init(struct urtwn_softc *sc) 2203{ 2204 int i, error, page_count, pktbuf_count; 2205 2206 page_count = (sc->chip & URTWN_CHIP_88E) ? 2207 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 2208 pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 2209 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2210 2211 /* Reserve pages [0; page_count]. */ 2212 for (i = 0; i < page_count; i++) { 2213 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2214 return (error); 2215 } 2216 /* NB: 0xff indicates end-of-list. */ 2217 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2218 return (error); 2219 /* 2220 * Use pages [page_count + 1; pktbuf_count - 1] 2221 * as ring buffer. 2222 */ 2223 for (++i; i < pktbuf_count - 1; i++) { 2224 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2225 return (error); 2226 } 2227 /* Make the last page point to the beginning of the ring buffer. */ 2228 error = urtwn_llt_write(sc, i, page_count + 1); 2229 return (error); 2230} 2231 2232static void 2233urtwn_fw_reset(struct urtwn_softc *sc) 2234{ 2235 uint16_t reg; 2236 int ntries; 2237 2238 /* Tell 8051 to reset itself. */ 2239 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2240 2241 /* Wait until 8051 resets by itself. */ 2242 for (ntries = 0; ntries < 100; ntries++) { 2243 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2244 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2245 return; 2246 urtwn_ms_delay(sc); 2247 } 2248 /* Force 8051 reset. */ 2249 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2250} 2251 2252static void 2253urtwn_r88e_fw_reset(struct urtwn_softc *sc) 2254{ 2255 uint16_t reg; 2256 2257 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2258 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2259 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 2260} 2261 2262static int 2263urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 2264{ 2265 uint32_t reg; 2266 int off, mlen, error = 0; 2267 2268 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2269 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2270 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2271 2272 off = R92C_FW_START_ADDR; 2273 while (len > 0) { 2274 if (len > 196) 2275 mlen = 196; 2276 else if (len > 4) 2277 mlen = 4; 2278 else 2279 mlen = 1; 2280 /* XXX fix this deconst */ 2281 error = urtwn_write_region_1(sc, off, 2282 __DECONST(uint8_t *, buf), mlen); 2283 if (error != 0) 2284 break; 2285 off += mlen; 2286 buf += mlen; 2287 len -= mlen; 2288 } 2289 return (error); 2290} 2291 2292static int 2293urtwn_load_firmware(struct urtwn_softc *sc) 2294{ 2295 const struct firmware *fw; 2296 const struct r92c_fw_hdr *hdr; 2297 const char *imagename; 2298 const u_char *ptr; 2299 size_t len; 2300 uint32_t reg; 2301 int mlen, ntries, page, error; 2302 2303 URTWN_UNLOCK(sc); 2304 /* Read firmware image from the filesystem. */ 2305 if (sc->chip & URTWN_CHIP_88E) 2306 imagename = "urtwn-rtl8188eufw"; 2307 else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2308 URTWN_CHIP_UMC_A_CUT) 2309 imagename = "urtwn-rtl8192cfwU"; 2310 else 2311 imagename = "urtwn-rtl8192cfwT"; 2312 2313 fw = firmware_get(imagename); 2314 URTWN_LOCK(sc); 2315 if (fw == NULL) { 2316 device_printf(sc->sc_dev, 2317 "failed loadfirmware of file %s\n", imagename); 2318 return (ENOENT); 2319 } 2320 2321 len = fw->datasize; 2322 2323 if (len < sizeof(*hdr)) { 2324 device_printf(sc->sc_dev, "firmware too short\n"); 2325 error = EINVAL; 2326 goto fail; 2327 } 2328 ptr = fw->data; 2329 hdr = (const struct r92c_fw_hdr *)ptr; 2330 /* Check if there is a valid FW header and skip it. */ 2331 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2332 (le16toh(hdr->signature) >> 4) == 0x88e || 2333 (le16toh(hdr->signature) >> 4) == 0x92c) { 2334 DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 2335 le16toh(hdr->version), le16toh(hdr->subversion), 2336 hdr->month, hdr->date, hdr->hour, hdr->minute); 2337 ptr += sizeof(*hdr); 2338 len -= sizeof(*hdr); 2339 } 2340 2341 if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 2342 if (sc->chip & URTWN_CHIP_88E) 2343 urtwn_r88e_fw_reset(sc); 2344 else 2345 urtwn_fw_reset(sc); 2346 urtwn_write_1(sc, R92C_MCUFWDL, 0); 2347 } 2348 2349 if (!(sc->chip & URTWN_CHIP_88E)) { 2350 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2351 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2352 R92C_SYS_FUNC_EN_CPUEN); 2353 } 2354 urtwn_write_1(sc, R92C_MCUFWDL, 2355 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2356 urtwn_write_1(sc, R92C_MCUFWDL + 2, 2357 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2358 2359 /* Reset the FWDL checksum. */ 2360 urtwn_write_1(sc, R92C_MCUFWDL, 2361 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2362 2363 for (page = 0; len > 0; page++) { 2364 mlen = min(len, R92C_FW_PAGE_SIZE); 2365 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2366 if (error != 0) { 2367 device_printf(sc->sc_dev, 2368 "could not load firmware page\n"); 2369 goto fail; 2370 } 2371 ptr += mlen; 2372 len -= mlen; 2373 } 2374 urtwn_write_1(sc, R92C_MCUFWDL, 2375 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2376 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2377 2378 /* Wait for checksum report. */ 2379 for (ntries = 0; ntries < 1000; ntries++) { 2380 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2381 break; 2382 urtwn_ms_delay(sc); 2383 } 2384 if (ntries == 1000) { 2385 device_printf(sc->sc_dev, 2386 "timeout waiting for checksum report\n"); 2387 error = ETIMEDOUT; 2388 goto fail; 2389 } 2390 2391 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2392 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2393 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2394 if (sc->chip & URTWN_CHIP_88E) 2395 urtwn_r88e_fw_reset(sc); 2396 /* Wait for firmware readiness. */ 2397 for (ntries = 0; ntries < 1000; ntries++) { 2398 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2399 break; 2400 urtwn_ms_delay(sc); 2401 } 2402 if (ntries == 1000) { 2403 device_printf(sc->sc_dev, 2404 "timeout waiting for firmware readiness\n"); 2405 error = ETIMEDOUT; 2406 goto fail; 2407 } 2408fail: 2409 firmware_put(fw, FIRMWARE_UNLOAD); 2410 return (error); 2411} 2412 2413static __inline int 2414urtwn_dma_init(struct urtwn_softc *sc) 2415{ 2416 2417 return sc->sc_dma_init(sc); 2418} 2419 2420static int 2421urtwn_r92c_dma_init(struct urtwn_softc *sc) 2422{ 2423 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2424 uint32_t reg; 2425 int error; 2426 2427 /* Initialize LLT table. */ 2428 error = urtwn_llt_init(sc); 2429 if (error != 0) 2430 return (error); 2431 2432 /* Get Tx queues to USB endpoints mapping. */ 2433 hashq = hasnq = haslq = 0; 2434 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2435 DPRINTFN(2, "USB endpoints mapping 0x%x\n", reg); 2436 if (MS(reg, R92C_USB_EP_HQ) != 0) 2437 hashq = 1; 2438 if (MS(reg, R92C_USB_EP_NQ) != 0) 2439 hasnq = 1; 2440 if (MS(reg, R92C_USB_EP_LQ) != 0) 2441 haslq = 1; 2442 nqueues = hashq + hasnq + haslq; 2443 if (nqueues == 0) 2444 return (EIO); 2445 /* Get the number of pages for each queue. */ 2446 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2447 /* The remaining pages are assigned to the high priority queue. */ 2448 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2449 2450 /* Set number of pages for normal priority queue. */ 2451 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2452 urtwn_write_4(sc, R92C_RQPN, 2453 /* Set number of pages for public queue. */ 2454 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2455 /* Set number of pages for high priority queue. */ 2456 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2457 /* Set number of pages for low priority queue. */ 2458 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2459 /* Load values. */ 2460 R92C_RQPN_LD); 2461 2462 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2463 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2464 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2465 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2466 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2467 2468 /* Set queue to USB pipe mapping. */ 2469 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2470 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2471 if (nqueues == 1) { 2472 if (hashq) 2473 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2474 else if (hasnq) 2475 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2476 else 2477 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2478 } else if (nqueues == 2) { 2479 /* All 2-endpoints configs have a high priority queue. */ 2480 if (!hashq) 2481 return (EIO); 2482 if (hasnq) 2483 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2484 else 2485 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2486 } else 2487 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2488 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2489 2490 /* Set Tx/Rx transfer page boundary. */ 2491 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2492 2493 /* Set Tx/Rx transfer page size. */ 2494 urtwn_write_1(sc, R92C_PBP, 2495 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2496 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2497 return (0); 2498} 2499 2500static int 2501urtwn_r88e_dma_init(struct urtwn_softc *sc) 2502{ 2503 struct usb_interface *iface; 2504 uint32_t reg; 2505 int nqueues; 2506 int error; 2507 2508 /* Initialize LLT table. */ 2509 error = urtwn_llt_init(sc); 2510 if (error != 0) 2511 return (error); 2512 2513 /* Get Tx queues to USB endpoints mapping. */ 2514 iface = usbd_get_iface(sc->sc_udev, 0); 2515 nqueues = iface->idesc->bNumEndpoints - 1; 2516 if (nqueues == 0) 2517 return (EIO); 2518 2519 /* Set number of pages for normal priority queue. */ 2520 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 2521 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 2522 2523 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2524 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2525 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 2526 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 2527 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 2528 2529 /* Set queue to USB pipe mapping. */ 2530 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2531 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2532 if (nqueues == 1) 2533 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2534 else if (nqueues == 2) 2535 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2536 else 2537 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2538 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2539 2540 /* Set Tx/Rx transfer page boundary. */ 2541 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 2542 2543 /* Set Tx/Rx transfer page size. */ 2544 urtwn_write_1(sc, R92C_PBP, 2545 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2546 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2547 2548 return (0); 2549} 2550 2551static void 2552urtwn_mac_init(struct urtwn_softc *sc) 2553{ 2554 int i; 2555 2556 /* Write MAC initialization values. */ 2557 if (sc->chip & URTWN_CHIP_88E) { 2558 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2559 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2560 rtl8188eu_mac[i].val); 2561 } 2562 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2563 } else { 2564 for (i = 0; i < nitems(rtl8192cu_mac); i++) 2565 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2566 rtl8192cu_mac[i].val); 2567 } 2568} 2569 2570static void 2571urtwn_bb_init(struct urtwn_softc *sc) 2572{ 2573 const struct urtwn_bb_prog *prog; 2574 uint32_t reg; 2575 uint8_t crystalcap; 2576 int i; 2577 2578 /* Enable BB and RF. */ 2579 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2580 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2581 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2582 R92C_SYS_FUNC_EN_DIO_RF); 2583 2584 if (!(sc->chip & URTWN_CHIP_88E)) 2585 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2586 2587 urtwn_write_1(sc, R92C_RF_CTRL, 2588 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2589 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2590 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2591 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2592 2593 if (!(sc->chip & URTWN_CHIP_88E)) { 2594 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2595 urtwn_write_1(sc, 0x15, 0xe9); 2596 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2597 } 2598 2599 /* Select BB programming based on board type. */ 2600 if (sc->chip & URTWN_CHIP_88E) 2601 prog = &rtl8188eu_bb_prog; 2602 else if (!(sc->chip & URTWN_CHIP_92C)) { 2603 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2604 prog = &rtl8188ce_bb_prog; 2605 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2606 prog = &rtl8188ru_bb_prog; 2607 else 2608 prog = &rtl8188cu_bb_prog; 2609 } else { 2610 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2611 prog = &rtl8192ce_bb_prog; 2612 else 2613 prog = &rtl8192cu_bb_prog; 2614 } 2615 /* Write BB initialization values. */ 2616 for (i = 0; i < prog->count; i++) { 2617 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2618 urtwn_ms_delay(sc); 2619 } 2620 2621 if (sc->chip & URTWN_CHIP_92C_1T2R) { 2622 /* 8192C 1T only configuration. */ 2623 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2624 reg = (reg & ~0x00000003) | 0x2; 2625 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2626 2627 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2628 reg = (reg & ~0x00300033) | 0x00200022; 2629 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2630 2631 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2632 reg = (reg & ~0xff000000) | 0x45 << 24; 2633 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2634 2635 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2636 reg = (reg & ~0x000000ff) | 0x23; 2637 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2638 2639 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2640 reg = (reg & ~0x00000030) | 1 << 4; 2641 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2642 2643 reg = urtwn_bb_read(sc, 0xe74); 2644 reg = (reg & ~0x0c000000) | 2 << 26; 2645 urtwn_bb_write(sc, 0xe74, reg); 2646 reg = urtwn_bb_read(sc, 0xe78); 2647 reg = (reg & ~0x0c000000) | 2 << 26; 2648 urtwn_bb_write(sc, 0xe78, reg); 2649 reg = urtwn_bb_read(sc, 0xe7c); 2650 reg = (reg & ~0x0c000000) | 2 << 26; 2651 urtwn_bb_write(sc, 0xe7c, reg); 2652 reg = urtwn_bb_read(sc, 0xe80); 2653 reg = (reg & ~0x0c000000) | 2 << 26; 2654 urtwn_bb_write(sc, 0xe80, reg); 2655 reg = urtwn_bb_read(sc, 0xe88); 2656 reg = (reg & ~0x0c000000) | 2 << 26; 2657 urtwn_bb_write(sc, 0xe88, reg); 2658 } 2659 2660 /* Write AGC values. */ 2661 for (i = 0; i < prog->agccount; i++) { 2662 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2663 prog->agcvals[i]); 2664 urtwn_ms_delay(sc); 2665 } 2666 2667 if (sc->chip & URTWN_CHIP_88E) { 2668 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 2669 urtwn_ms_delay(sc); 2670 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 2671 urtwn_ms_delay(sc); 2672 2673 crystalcap = sc->r88e_rom[0xb9]; 2674 if (crystalcap == 0xff) 2675 crystalcap = 0x20; 2676 crystalcap &= 0x3f; 2677 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 2678 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 2679 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 2680 crystalcap | crystalcap << 6)); 2681 } else { 2682 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2683 R92C_HSSI_PARAM2_CCK_HIPWR) 2684 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 2685 } 2686} 2687 2688static void 2689urtwn_rf_init(struct urtwn_softc *sc) 2690{ 2691 const struct urtwn_rf_prog *prog; 2692 uint32_t reg, type; 2693 int i, j, idx, off; 2694 2695 /* Select RF programming based on board type. */ 2696 if (sc->chip & URTWN_CHIP_88E) 2697 prog = rtl8188eu_rf_prog; 2698 else if (!(sc->chip & URTWN_CHIP_92C)) { 2699 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2700 prog = rtl8188ce_rf_prog; 2701 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2702 prog = rtl8188ru_rf_prog; 2703 else 2704 prog = rtl8188cu_rf_prog; 2705 } else 2706 prog = rtl8192ce_rf_prog; 2707 2708 for (i = 0; i < sc->nrxchains; i++) { 2709 /* Save RF_ENV control type. */ 2710 idx = i / 2; 2711 off = (i % 2) * 16; 2712 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2713 type = (reg >> off) & 0x10; 2714 2715 /* Set RF_ENV enable. */ 2716 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2717 reg |= 0x100000; 2718 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2719 urtwn_ms_delay(sc); 2720 /* Set RF_ENV output high. */ 2721 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2722 reg |= 0x10; 2723 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2724 urtwn_ms_delay(sc); 2725 /* Set address and data lengths of RF registers. */ 2726 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2727 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2728 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2729 urtwn_ms_delay(sc); 2730 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2731 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2732 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2733 urtwn_ms_delay(sc); 2734 2735 /* Write RF initialization values for this chain. */ 2736 for (j = 0; j < prog[i].count; j++) { 2737 if (prog[i].regs[j] >= 0xf9 && 2738 prog[i].regs[j] <= 0xfe) { 2739 /* 2740 * These are fake RF registers offsets that 2741 * indicate a delay is required. 2742 */ 2743 usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 2744 continue; 2745 } 2746 urtwn_rf_write(sc, i, prog[i].regs[j], 2747 prog[i].vals[j]); 2748 urtwn_ms_delay(sc); 2749 } 2750 2751 /* Restore RF_ENV control type. */ 2752 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2753 reg &= ~(0x10 << off) | (type << off); 2754 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2755 2756 /* Cache RF register CHNLBW. */ 2757 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2758 } 2759 2760 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2761 URTWN_CHIP_UMC_A_CUT) { 2762 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2763 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2764 } 2765} 2766 2767static void 2768urtwn_cam_init(struct urtwn_softc *sc) 2769{ 2770 /* Invalidate all CAM entries. */ 2771 urtwn_write_4(sc, R92C_CAMCMD, 2772 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2773} 2774 2775static void 2776urtwn_pa_bias_init(struct urtwn_softc *sc) 2777{ 2778 uint8_t reg; 2779 int i; 2780 2781 for (i = 0; i < sc->nrxchains; i++) { 2782 if (sc->pa_setting & (1 << i)) 2783 continue; 2784 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2785 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2786 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2787 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2788 } 2789 if (!(sc->pa_setting & 0x10)) { 2790 reg = urtwn_read_1(sc, 0x16); 2791 reg = (reg & ~0xf0) | 0x90; 2792 urtwn_write_1(sc, 0x16, reg); 2793 } 2794} 2795 2796static void 2797urtwn_rxfilter_init(struct urtwn_softc *sc) 2798{ 2799 /* Initialize Rx filter. */ 2800 /* TODO: use better filter for monitor mode. */ 2801 urtwn_write_4(sc, R92C_RCR, 2802 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2803 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2804 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2805 /* Accept all multicast frames. */ 2806 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2807 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2808 /* Accept all management frames. */ 2809 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2810 /* Reject all control frames. */ 2811 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2812 /* Accept all data frames. */ 2813 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2814} 2815 2816static void 2817urtwn_edca_init(struct urtwn_softc *sc) 2818{ 2819 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 2820 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 2821 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 2822 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 2823 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2824 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2825 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 2826 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 2827} 2828 2829static void 2830urtwn_write_txpower(struct urtwn_softc *sc, int chain, 2831 uint16_t power[URTWN_RIDX_COUNT]) 2832{ 2833 uint32_t reg; 2834 2835 /* Write per-CCK rate Tx power. */ 2836 if (chain == 0) { 2837 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2838 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2839 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2840 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2841 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2842 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2843 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2844 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2845 } else { 2846 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2847 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2848 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2849 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2850 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2851 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2852 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2853 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2854 } 2855 /* Write per-OFDM rate Tx power. */ 2856 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2857 SM(R92C_TXAGC_RATE06, power[ 4]) | 2858 SM(R92C_TXAGC_RATE09, power[ 5]) | 2859 SM(R92C_TXAGC_RATE12, power[ 6]) | 2860 SM(R92C_TXAGC_RATE18, power[ 7])); 2861 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2862 SM(R92C_TXAGC_RATE24, power[ 8]) | 2863 SM(R92C_TXAGC_RATE36, power[ 9]) | 2864 SM(R92C_TXAGC_RATE48, power[10]) | 2865 SM(R92C_TXAGC_RATE54, power[11])); 2866 /* Write per-MCS Tx power. */ 2867 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2868 SM(R92C_TXAGC_MCS00, power[12]) | 2869 SM(R92C_TXAGC_MCS01, power[13]) | 2870 SM(R92C_TXAGC_MCS02, power[14]) | 2871 SM(R92C_TXAGC_MCS03, power[15])); 2872 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2873 SM(R92C_TXAGC_MCS04, power[16]) | 2874 SM(R92C_TXAGC_MCS05, power[17]) | 2875 SM(R92C_TXAGC_MCS06, power[18]) | 2876 SM(R92C_TXAGC_MCS07, power[19])); 2877 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2878 SM(R92C_TXAGC_MCS08, power[20]) | 2879 SM(R92C_TXAGC_MCS09, power[21]) | 2880 SM(R92C_TXAGC_MCS10, power[22]) | 2881 SM(R92C_TXAGC_MCS11, power[23])); 2882 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2883 SM(R92C_TXAGC_MCS12, power[24]) | 2884 SM(R92C_TXAGC_MCS13, power[25]) | 2885 SM(R92C_TXAGC_MCS14, power[26]) | 2886 SM(R92C_TXAGC_MCS15, power[27])); 2887} 2888 2889static void 2890urtwn_get_txpower(struct urtwn_softc *sc, int chain, 2891 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2892 uint16_t power[URTWN_RIDX_COUNT]) 2893{ 2894 struct ieee80211com *ic = &sc->sc_ic; 2895 struct r92c_rom *rom = &sc->rom; 2896 uint16_t cckpow, ofdmpow, htpow, diff, max; 2897 const struct urtwn_txpwr *base; 2898 int ridx, chan, group; 2899 2900 /* Determine channel group. */ 2901 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2902 if (chan <= 3) 2903 group = 0; 2904 else if (chan <= 9) 2905 group = 1; 2906 else 2907 group = 2; 2908 2909 /* Get original Tx power based on board type and RF chain. */ 2910 if (!(sc->chip & URTWN_CHIP_92C)) { 2911 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2912 base = &rtl8188ru_txagc[chain]; 2913 else 2914 base = &rtl8192cu_txagc[chain]; 2915 } else 2916 base = &rtl8192cu_txagc[chain]; 2917 2918 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 2919 if (sc->regulatory == 0) { 2920 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 2921 power[ridx] = base->pwr[0][ridx]; 2922 } 2923 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 2924 if (sc->regulatory == 3) { 2925 power[ridx] = base->pwr[0][ridx]; 2926 /* Apply vendor limits. */ 2927 if (extc != NULL) 2928 max = rom->ht40_max_pwr[group]; 2929 else 2930 max = rom->ht20_max_pwr[group]; 2931 max = (max >> (chain * 4)) & 0xf; 2932 if (power[ridx] > max) 2933 power[ridx] = max; 2934 } else if (sc->regulatory == 1) { 2935 if (extc == NULL) 2936 power[ridx] = base->pwr[group][ridx]; 2937 } else if (sc->regulatory != 2) 2938 power[ridx] = base->pwr[0][ridx]; 2939 } 2940 2941 /* Compute per-CCK rate Tx power. */ 2942 cckpow = rom->cck_tx_pwr[chain][group]; 2943 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 2944 power[ridx] += cckpow; 2945 if (power[ridx] > R92C_MAX_TX_PWR) 2946 power[ridx] = R92C_MAX_TX_PWR; 2947 } 2948 2949 htpow = rom->ht40_1s_tx_pwr[chain][group]; 2950 if (sc->ntxchains > 1) { 2951 /* Apply reduction for 2 spatial streams. */ 2952 diff = rom->ht40_2s_tx_pwr_diff[group]; 2953 diff = (diff >> (chain * 4)) & 0xf; 2954 htpow = (htpow > diff) ? htpow - diff : 0; 2955 } 2956 2957 /* Compute per-OFDM rate Tx power. */ 2958 diff = rom->ofdm_tx_pwr_diff[group]; 2959 diff = (diff >> (chain * 4)) & 0xf; 2960 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 2961 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 2962 power[ridx] += ofdmpow; 2963 if (power[ridx] > R92C_MAX_TX_PWR) 2964 power[ridx] = R92C_MAX_TX_PWR; 2965 } 2966 2967 /* Compute per-MCS Tx power. */ 2968 if (extc == NULL) { 2969 diff = rom->ht20_tx_pwr_diff[group]; 2970 diff = (diff >> (chain * 4)) & 0xf; 2971 htpow += diff; /* HT40->HT20 correction. */ 2972 } 2973 for (ridx = 12; ridx <= 27; ridx++) { 2974 power[ridx] += htpow; 2975 if (power[ridx] > R92C_MAX_TX_PWR) 2976 power[ridx] = R92C_MAX_TX_PWR; 2977 } 2978#ifdef URTWN_DEBUG 2979 if (urtwn_debug >= 4) { 2980 /* Dump per-rate Tx power values. */ 2981 printf("Tx power for chain %d:\n", chain); 2982 for (ridx = URTWN_RIDX_CCK1; ridx < URTWN_RIDX_COUNT; ridx++) 2983 printf("Rate %d = %u\n", ridx, power[ridx]); 2984 } 2985#endif 2986} 2987 2988static void 2989urtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 2990 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2991 uint16_t power[URTWN_RIDX_COUNT]) 2992{ 2993 struct ieee80211com *ic = &sc->sc_ic; 2994 uint16_t cckpow, ofdmpow, bw20pow, htpow; 2995 const struct urtwn_r88e_txpwr *base; 2996 int ridx, chan, group; 2997 2998 /* Determine channel group. */ 2999 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3000 if (chan <= 2) 3001 group = 0; 3002 else if (chan <= 5) 3003 group = 1; 3004 else if (chan <= 8) 3005 group = 2; 3006 else if (chan <= 11) 3007 group = 3; 3008 else if (chan <= 13) 3009 group = 4; 3010 else 3011 group = 5; 3012 3013 /* Get original Tx power based on board type and RF chain. */ 3014 base = &rtl8188eu_txagc[chain]; 3015 3016 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3017 if (sc->regulatory == 0) { 3018 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) 3019 power[ridx] = base->pwr[0][ridx]; 3020 } 3021 for (ridx = URTWN_RIDX_OFDM6; ridx < URTWN_RIDX_COUNT; ridx++) { 3022 if (sc->regulatory == 3) 3023 power[ridx] = base->pwr[0][ridx]; 3024 else if (sc->regulatory == 1) { 3025 if (extc == NULL) 3026 power[ridx] = base->pwr[group][ridx]; 3027 } else if (sc->regulatory != 2) 3028 power[ridx] = base->pwr[0][ridx]; 3029 } 3030 3031 /* Compute per-CCK rate Tx power. */ 3032 cckpow = sc->cck_tx_pwr[group]; 3033 for (ridx = URTWN_RIDX_CCK1; ridx <= URTWN_RIDX_CCK11; ridx++) { 3034 power[ridx] += cckpow; 3035 if (power[ridx] > R92C_MAX_TX_PWR) 3036 power[ridx] = R92C_MAX_TX_PWR; 3037 } 3038 3039 htpow = sc->ht40_tx_pwr[group]; 3040 3041 /* Compute per-OFDM rate Tx power. */ 3042 ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3043 for (ridx = URTWN_RIDX_OFDM6; ridx <= URTWN_RIDX_OFDM54; ridx++) { 3044 power[ridx] += ofdmpow; 3045 if (power[ridx] > R92C_MAX_TX_PWR) 3046 power[ridx] = R92C_MAX_TX_PWR; 3047 } 3048 3049 bw20pow = htpow + sc->bw20_tx_pwr_diff; 3050 for (ridx = 12; ridx <= 27; ridx++) { 3051 power[ridx] += bw20pow; 3052 if (power[ridx] > R92C_MAX_TX_PWR) 3053 power[ridx] = R92C_MAX_TX_PWR; 3054 } 3055} 3056 3057static void 3058urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 3059 struct ieee80211_channel *extc) 3060{ 3061 uint16_t power[URTWN_RIDX_COUNT]; 3062 int i; 3063 3064 for (i = 0; i < sc->ntxchains; i++) { 3065 /* Compute per-rate Tx power values. */ 3066 if (sc->chip & URTWN_CHIP_88E) 3067 urtwn_r88e_get_txpower(sc, i, c, extc, power); 3068 else 3069 urtwn_get_txpower(sc, i, c, extc, power); 3070 /* Write per-rate Tx power values to hardware. */ 3071 urtwn_write_txpower(sc, i, power); 3072 } 3073} 3074 3075static void 3076urtwn_scan_start(struct ieee80211com *ic) 3077{ 3078 /* XXX do nothing? */ 3079} 3080 3081static void 3082urtwn_scan_end(struct ieee80211com *ic) 3083{ 3084 /* XXX do nothing? */ 3085} 3086 3087static void 3088urtwn_set_channel(struct ieee80211com *ic) 3089{ 3090 struct urtwn_softc *sc = ic->ic_softc; 3091 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3092 3093 URTWN_LOCK(sc); 3094 if (vap->iv_state == IEEE80211_S_SCAN) { 3095 /* Make link LED blink during scan. */ 3096 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 3097 } 3098 urtwn_set_chan(sc, ic->ic_curchan, NULL); 3099 URTWN_UNLOCK(sc); 3100} 3101 3102static void 3103urtwn_update_mcast(struct ieee80211com *ic) 3104{ 3105 /* XXX do nothing? */ 3106} 3107 3108static void 3109urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 3110 struct ieee80211_channel *extc) 3111{ 3112 struct ieee80211com *ic = &sc->sc_ic; 3113 uint32_t reg; 3114 u_int chan; 3115 int i; 3116 3117 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3118 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 3119 device_printf(sc->sc_dev, 3120 "%s: invalid channel %x\n", __func__, chan); 3121 return; 3122 } 3123 3124 /* Set Tx power for this new channel. */ 3125 urtwn_set_txpower(sc, c, extc); 3126 3127 for (i = 0; i < sc->nrxchains; i++) { 3128 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3129 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3130 } 3131#ifndef IEEE80211_NO_HT 3132 if (extc != NULL) { 3133 /* Is secondary channel below or above primary? */ 3134 int prichlo = c->ic_freq < extc->ic_freq; 3135 3136 urtwn_write_1(sc, R92C_BWOPMODE, 3137 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3138 3139 reg = urtwn_read_1(sc, R92C_RRSR + 2); 3140 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3141 urtwn_write_1(sc, R92C_RRSR + 2, reg); 3142 3143 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3144 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3145 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3146 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3147 3148 /* Set CCK side band. */ 3149 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3150 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3151 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3152 3153 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3154 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3155 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3156 3157 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3158 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3159 ~R92C_FPGA0_ANAPARAM2_CBW20); 3160 3161 reg = urtwn_bb_read(sc, 0x818); 3162 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3163 urtwn_bb_write(sc, 0x818, reg); 3164 3165 /* Select 40MHz bandwidth. */ 3166 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3167 (sc->rf_chnlbw[0] & ~0xfff) | chan); 3168 } else 3169#endif 3170 { 3171 urtwn_write_1(sc, R92C_BWOPMODE, 3172 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3173 3174 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3175 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3176 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3177 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3178 3179 if (!(sc->chip & URTWN_CHIP_88E)) { 3180 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3181 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3182 R92C_FPGA0_ANAPARAM2_CBW20); 3183 } 3184 3185 /* Select 20MHz bandwidth. */ 3186 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3187 (sc->rf_chnlbw[0] & ~0xfff) | chan | 3188 ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 3189 R92C_RF_CHNLBW_BW20)); 3190 } 3191} 3192 3193static void 3194urtwn_iq_calib(struct urtwn_softc *sc) 3195{ 3196 /* TODO */ 3197} 3198 3199static void 3200urtwn_lc_calib(struct urtwn_softc *sc) 3201{ 3202 uint32_t rf_ac[2]; 3203 uint8_t txmode; 3204 int i; 3205 3206 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3207 if ((txmode & 0x70) != 0) { 3208 /* Disable all continuous Tx. */ 3209 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3210 3211 /* Set RF mode to standby mode. */ 3212 for (i = 0; i < sc->nrxchains; i++) { 3213 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3214 urtwn_rf_write(sc, i, R92C_RF_AC, 3215 RW(rf_ac[i], R92C_RF_AC_MODE, 3216 R92C_RF_AC_MODE_STANDBY)); 3217 } 3218 } else { 3219 /* Block all Tx queues. */ 3220 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3221 } 3222 /* Start calibration. */ 3223 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3224 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3225 3226 /* Give calibration the time to complete. */ 3227 usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 3228 3229 /* Restore configuration. */ 3230 if ((txmode & 0x70) != 0) { 3231 /* Restore Tx mode. */ 3232 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3233 /* Restore RF mode. */ 3234 for (i = 0; i < sc->nrxchains; i++) 3235 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3236 } else { 3237 /* Unblock all Tx queues. */ 3238 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3239 } 3240} 3241 3242static void 3243urtwn_init(struct urtwn_softc *sc) 3244{ 3245 struct ieee80211com *ic = &sc->sc_ic; 3246 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3247 uint8_t macaddr[IEEE80211_ADDR_LEN]; 3248 uint32_t reg; 3249 int error; 3250 3251 URTWN_ASSERT_LOCKED(sc); 3252 3253 if (sc->sc_flags & URTWN_RUNNING) 3254 urtwn_stop(sc); 3255 3256 /* Init firmware commands ring. */ 3257 sc->fwcur = 0; 3258 3259 /* Allocate Tx/Rx buffers. */ 3260 error = urtwn_alloc_rx_list(sc); 3261 if (error != 0) 3262 goto fail; 3263 3264 error = urtwn_alloc_tx_list(sc); 3265 if (error != 0) 3266 goto fail; 3267 3268 /* Power on adapter. */ 3269 error = urtwn_power_on(sc); 3270 if (error != 0) 3271 goto fail; 3272 3273 /* Initialize DMA. */ 3274 error = urtwn_dma_init(sc); 3275 if (error != 0) 3276 goto fail; 3277 3278 /* Set info size in Rx descriptors (in 64-bit words). */ 3279 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3280 3281 /* Init interrupts. */ 3282 if (sc->chip & URTWN_CHIP_88E) { 3283 urtwn_write_4(sc, R88E_HISR, 0xffffffff); 3284 urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 3285 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 3286 urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 3287 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 3288 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3289 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3290 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 3291 } else { 3292 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3293 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3294 } 3295 3296 /* Set MAC address. */ 3297 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 3298 urtwn_write_region_1(sc, R92C_MACID, macaddr, IEEE80211_ADDR_LEN); 3299 3300 /* Set initial network type. */ 3301 reg = urtwn_read_4(sc, R92C_CR); 3302 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 3303 urtwn_write_4(sc, R92C_CR, reg); 3304 3305 urtwn_rxfilter_init(sc); 3306 3307 /* Set response rate. */ 3308 reg = urtwn_read_4(sc, R92C_RRSR); 3309 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3310 urtwn_write_4(sc, R92C_RRSR, reg); 3311 3312 /* Set short/long retry limits. */ 3313 urtwn_write_2(sc, R92C_RL, 3314 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3315 3316 /* Initialize EDCA parameters. */ 3317 urtwn_edca_init(sc); 3318 3319 /* Setup rate fallback. */ 3320 if (!(sc->chip & URTWN_CHIP_88E)) { 3321 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3322 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3323 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3324 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3325 } 3326 3327 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3328 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3329 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3330 /* Set ACK timeout. */ 3331 urtwn_write_1(sc, R92C_ACKTO, 0x40); 3332 3333 /* Setup USB aggregation. */ 3334 reg = urtwn_read_4(sc, R92C_TDECTRL); 3335 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3336 urtwn_write_4(sc, R92C_TDECTRL, reg); 3337 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3338 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3339 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3340 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3341 if (sc->chip & URTWN_CHIP_88E) 3342 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 3343 else { 3344 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3345 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3346 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3347 R92C_USB_SPECIAL_OPTION_AGG_EN); 3348 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 3349 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 3350 } 3351 3352 /* Initialize beacon parameters. */ 3353 urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 3354 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3355 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3356 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3357 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3358 3359 if (!(sc->chip & URTWN_CHIP_88E)) { 3360 /* Setup AMPDU aggregation. */ 3361 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3362 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3363 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 3364 3365 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3366 } 3367 3368 /* Load 8051 microcode. */ 3369 error = urtwn_load_firmware(sc); 3370 if (error != 0) 3371 goto fail; 3372 3373 /* Initialize MAC/BB/RF blocks. */ 3374 urtwn_mac_init(sc); 3375 urtwn_bb_init(sc); 3376 urtwn_rf_init(sc); 3377 3378 if (sc->chip & URTWN_CHIP_88E) { 3379 urtwn_write_2(sc, R92C_CR, 3380 urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 3381 R92C_CR_MACRXEN); 3382 } 3383 3384 /* Turn CCK and OFDM blocks on. */ 3385 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3386 reg |= R92C_RFMOD_CCK_EN; 3387 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3388 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3389 reg |= R92C_RFMOD_OFDM_EN; 3390 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3391 3392 /* Clear per-station keys table. */ 3393 urtwn_cam_init(sc); 3394 3395 /* Enable hardware sequence numbering. */ 3396 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3397 3398 /* Perform LO and IQ calibrations. */ 3399 urtwn_iq_calib(sc); 3400 /* Perform LC calibration. */ 3401 urtwn_lc_calib(sc); 3402 3403 /* Fix USB interference issue. */ 3404 if (!(sc->chip & URTWN_CHIP_88E)) { 3405 urtwn_write_1(sc, 0xfe40, 0xe0); 3406 urtwn_write_1(sc, 0xfe41, 0x8d); 3407 urtwn_write_1(sc, 0xfe42, 0x80); 3408 3409 urtwn_pa_bias_init(sc); 3410 } 3411 3412 /* Initialize GPIO setting. */ 3413 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 3414 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3415 3416 /* Fix for lower temperature. */ 3417 if (!(sc->chip & URTWN_CHIP_88E)) 3418 urtwn_write_1(sc, 0x15, 0xe9); 3419 3420 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 3421 3422 sc->sc_flags |= URTWN_RUNNING; 3423 3424 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3425fail: 3426 return; 3427} 3428 3429static void 3430urtwn_stop(struct urtwn_softc *sc) 3431{ 3432 3433 URTWN_ASSERT_LOCKED(sc); 3434 sc->sc_flags &= ~URTWN_RUNNING; 3435 callout_stop(&sc->sc_watchdog_ch); 3436 urtwn_abort_xfers(sc); 3437 3438 urtwn_drain_mbufq(sc); 3439} 3440 3441static void 3442urtwn_abort_xfers(struct urtwn_softc *sc) 3443{ 3444 int i; 3445 3446 URTWN_ASSERT_LOCKED(sc); 3447 3448 /* abort any pending transfers */ 3449 for (i = 0; i < URTWN_N_TRANSFER; i++) 3450 usbd_transfer_stop(sc->sc_xfer[i]); 3451} 3452 3453static int 3454urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3455 const struct ieee80211_bpf_params *params) 3456{ 3457 struct ieee80211com *ic = ni->ni_ic; 3458 struct urtwn_softc *sc = ic->ic_softc; 3459 struct urtwn_data *bf; 3460 3461 /* prevent management frames from being sent if we're not ready */ 3462 if (!(sc->sc_flags & URTWN_RUNNING)) { 3463 m_freem(m); 3464 return (ENETDOWN); 3465 } 3466 URTWN_LOCK(sc); 3467 bf = urtwn_getbuf(sc); 3468 if (bf == NULL) { 3469 m_freem(m); 3470 URTWN_UNLOCK(sc); 3471 return (ENOBUFS); 3472 } 3473 3474 if (urtwn_tx_start(sc, ni, m, bf) != 0) { 3475 m_freem(m); 3476 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3477 URTWN_UNLOCK(sc); 3478 return (EIO); 3479 } 3480 sc->sc_txtimer = 5; 3481 URTWN_UNLOCK(sc); 3482 3483 return (0); 3484} 3485 3486static void 3487urtwn_ms_delay(struct urtwn_softc *sc) 3488{ 3489 usb_pause_mtx(&sc->sc_mtx, hz / 1000); 3490} 3491 3492static device_method_t urtwn_methods[] = { 3493 /* Device interface */ 3494 DEVMETHOD(device_probe, urtwn_match), 3495 DEVMETHOD(device_attach, urtwn_attach), 3496 DEVMETHOD(device_detach, urtwn_detach), 3497 3498 DEVMETHOD_END 3499}; 3500 3501static driver_t urtwn_driver = { 3502 "urtwn", 3503 urtwn_methods, 3504 sizeof(struct urtwn_softc) 3505}; 3506 3507static devclass_t urtwn_devclass; 3508 3509DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 3510MODULE_DEPEND(urtwn, usb, 1, 1, 1); 3511MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 3512MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 3513MODULE_VERSION(urtwn, 1); 3514