if_urtwn.c revision 264864
1251538Srpaulo/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2251538Srpaulo 3251538Srpaulo/*- 4251538Srpaulo * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5251538Srpaulo * 6251538Srpaulo * Permission to use, copy, modify, and distribute this software for any 7251538Srpaulo * purpose with or without fee is hereby granted, provided that the above 8251538Srpaulo * copyright notice and this permission notice appear in all copies. 9251538Srpaulo * 10251538Srpaulo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11251538Srpaulo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12251538Srpaulo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13251538Srpaulo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14251538Srpaulo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15251538Srpaulo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16251538Srpaulo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17251538Srpaulo */ 18251538Srpaulo 19251538Srpaulo#include <sys/cdefs.h> 20251538Srpaulo__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 264864 2014-04-24 03:16:47Z kevlo $"); 21251538Srpaulo 22251538Srpaulo/* 23251538Srpaulo * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188RU/RTL8192CU. 24251538Srpaulo */ 25251538Srpaulo 26251538Srpaulo#include <sys/param.h> 27251538Srpaulo#include <sys/sockio.h> 28251538Srpaulo#include <sys/sysctl.h> 29251538Srpaulo#include <sys/lock.h> 30251538Srpaulo#include <sys/mutex.h> 31251538Srpaulo#include <sys/mbuf.h> 32251538Srpaulo#include <sys/kernel.h> 33251538Srpaulo#include <sys/socket.h> 34251538Srpaulo#include <sys/systm.h> 35251538Srpaulo#include <sys/malloc.h> 36251538Srpaulo#include <sys/module.h> 37251538Srpaulo#include <sys/bus.h> 38251538Srpaulo#include <sys/endian.h> 39251538Srpaulo#include <sys/linker.h> 40251538Srpaulo#include <sys/firmware.h> 41251538Srpaulo#include <sys/kdb.h> 42251538Srpaulo 43251538Srpaulo#include <machine/bus.h> 44251538Srpaulo#include <machine/resource.h> 45251538Srpaulo#include <sys/rman.h> 46251538Srpaulo 47251538Srpaulo#include <net/bpf.h> 48251538Srpaulo#include <net/if.h> 49257176Sglebius#include <net/if_var.h> 50251538Srpaulo#include <net/if_arp.h> 51251538Srpaulo#include <net/ethernet.h> 52251538Srpaulo#include <net/if_dl.h> 53251538Srpaulo#include <net/if_media.h> 54251538Srpaulo#include <net/if_types.h> 55251538Srpaulo 56251538Srpaulo#include <netinet/in.h> 57251538Srpaulo#include <netinet/in_systm.h> 58251538Srpaulo#include <netinet/in_var.h> 59251538Srpaulo#include <netinet/if_ether.h> 60251538Srpaulo#include <netinet/ip.h> 61251538Srpaulo 62251538Srpaulo#include <net80211/ieee80211_var.h> 63251538Srpaulo#include <net80211/ieee80211_regdomain.h> 64251538Srpaulo#include <net80211/ieee80211_radiotap.h> 65251538Srpaulo#include <net80211/ieee80211_ratectl.h> 66251538Srpaulo 67251538Srpaulo#include <dev/usb/usb.h> 68251538Srpaulo#include <dev/usb/usbdi.h> 69251538Srpaulo#include "usbdevs.h" 70251538Srpaulo 71251538Srpaulo#define USB_DEBUG_VAR urtwn_debug 72251538Srpaulo#include <dev/usb/usb_debug.h> 73251538Srpaulo 74251538Srpaulo#include <dev/usb/wlan/if_urtwnreg.h> 75251538Srpaulo 76251538Srpaulo#ifdef USB_DEBUG 77251538Srpaulostatic int urtwn_debug = 0; 78251538Srpaulo 79251538SrpauloSYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 80251538SrpauloSYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RW, &urtwn_debug, 0, 81251538Srpaulo "Debug level"); 82251538Srpaulo#endif 83251538Srpaulo 84252406Srpaulo#define URTWN_RSSI(r) (r) - 110 85251538Srpaulo#define IEEE80211_HAS_ADDR4(wh) \ 86251538Srpaulo (((wh)->i_fc[1] & IEEE80211_FC1_DIR_MASK) == IEEE80211_FC1_DIR_DSTODS) 87251538Srpaulo 88251538Srpaulo/* various supported device vendors/products */ 89251596Srpaulostatic const STRUCT_USB_HOST_ID urtwn_devs[] = { 90251538Srpaulo#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 91251538Srpaulo URTWN_DEV(ABOCOM, RTL8188CU_1), 92251538Srpaulo URTWN_DEV(ABOCOM, RTL8188CU_2), 93251538Srpaulo URTWN_DEV(ABOCOM, RTL8192CU), 94251538Srpaulo URTWN_DEV(ASUS, RTL8192CU), 95264317Skevlo URTWN_DEV(ASUS, USBN10NANO), 96251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CE_1), 97251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CE_2), 98251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CU), 99251538Srpaulo URTWN_DEV(BELKIN, F7D2102), 100251538Srpaulo URTWN_DEV(BELKIN, RTL8188CU), 101251538Srpaulo URTWN_DEV(BELKIN, RTL8192CU), 102251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_1), 103251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_2), 104251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_3), 105251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_4), 106251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_5), 107251538Srpaulo URTWN_DEV(COREGA, RTL8192CU), 108251538Srpaulo URTWN_DEV(DLINK, RTL8188CU), 109251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_1), 110251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_2), 111251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_3), 112252196Skevlo URTWN_DEV(DLINK, DWA131B), 113251538Srpaulo URTWN_DEV(EDIMAX, EW7811UN), 114251538Srpaulo URTWN_DEV(EDIMAX, RTL8192CU), 115251538Srpaulo URTWN_DEV(FEIXUN, RTL8188CU), 116251538Srpaulo URTWN_DEV(FEIXUN, RTL8192CU), 117251538Srpaulo URTWN_DEV(GUILLEMOT, HWNUP150), 118251538Srpaulo URTWN_DEV(HAWKING, RTL8192CU), 119251538Srpaulo URTWN_DEV(HP3, RTL8188CU), 120251538Srpaulo URTWN_DEV(NETGEAR, WNA1000M), 121251538Srpaulo URTWN_DEV(NETGEAR, RTL8192CU), 122251538Srpaulo URTWN_DEV(NETGEAR4, RTL8188CU), 123251538Srpaulo URTWN_DEV(NOVATECH, RTL8188CU), 124251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_1), 125251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_2), 126251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_3), 127251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_4), 128251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CUS), 129251538Srpaulo URTWN_DEV(PLANEX2, RTL8192CU), 130251538Srpaulo URTWN_DEV(REALTEK, RTL8188CE_0), 131251538Srpaulo URTWN_DEV(REALTEK, RTL8188CE_1), 132251538Srpaulo URTWN_DEV(REALTEK, RTL8188CTV), 133251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_0), 134251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_1), 135251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_2), 136251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_COMBO), 137251538Srpaulo URTWN_DEV(REALTEK, RTL8188CUS), 138251538Srpaulo URTWN_DEV(REALTEK, RTL8188RU_1), 139251538Srpaulo URTWN_DEV(REALTEK, RTL8188RU_2), 140251538Srpaulo URTWN_DEV(REALTEK, RTL8191CU), 141251538Srpaulo URTWN_DEV(REALTEK, RTL8192CE), 142251538Srpaulo URTWN_DEV(REALTEK, RTL8192CU), 143257543Salfred URTWN_DEV(REALTEK, RTL8188CU_0), 144251538Srpaulo URTWN_DEV(SITECOMEU, RTL8188CU_1), 145251538Srpaulo URTWN_DEV(SITECOMEU, RTL8188CU_2), 146251538Srpaulo URTWN_DEV(SITECOMEU, RTL8192CU), 147251538Srpaulo URTWN_DEV(TRENDNET, RTL8188CU), 148251538Srpaulo URTWN_DEV(TRENDNET, RTL8192CU), 149251538Srpaulo URTWN_DEV(ZYXEL, RTL8192CU), 150251538Srpaulo#undef URTWN_DEV 151251538Srpaulo}; 152251538Srpaulo 153251538Srpaulostatic device_probe_t urtwn_match; 154251538Srpaulostatic device_attach_t urtwn_attach; 155251538Srpaulostatic device_detach_t urtwn_detach; 156251538Srpaulo 157251538Srpaulostatic usb_callback_t urtwn_bulk_tx_callback; 158251538Srpaulostatic usb_callback_t urtwn_bulk_rx_callback; 159251538Srpaulo 160251538Srpaulostatic usb_error_t urtwn_do_request(struct urtwn_softc *sc, 161251538Srpaulo struct usb_device_request *req, void *data); 162251538Srpaulostatic struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 163251538Srpaulo const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 164251538Srpaulo const uint8_t [IEEE80211_ADDR_LEN], 165251538Srpaulo const uint8_t [IEEE80211_ADDR_LEN]); 166251538Srpaulostatic void urtwn_vap_delete(struct ieee80211vap *); 167251538Srpaulostatic struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 168251538Srpaulo int *); 169251538Srpaulostatic struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *, 170251538Srpaulo int *, int8_t *); 171251538Srpaulostatic void urtwn_txeof(struct usb_xfer *, struct urtwn_data *); 172251538Srpaulostatic int urtwn_alloc_list(struct urtwn_softc *, 173251538Srpaulo struct urtwn_data[], int, int); 174251538Srpaulostatic int urtwn_alloc_rx_list(struct urtwn_softc *); 175251538Srpaulostatic int urtwn_alloc_tx_list(struct urtwn_softc *); 176251538Srpaulostatic void urtwn_free_tx_list(struct urtwn_softc *); 177251538Srpaulostatic void urtwn_free_rx_list(struct urtwn_softc *); 178251538Srpaulostatic void urtwn_free_list(struct urtwn_softc *, 179251538Srpaulo struct urtwn_data data[], int); 180251538Srpaulostatic struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 181251538Srpaulostatic struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 182251538Srpaulostatic int urtwn_write_region_1(struct urtwn_softc *, uint16_t, 183251538Srpaulo uint8_t *, int); 184251538Srpaulostatic void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 185251538Srpaulostatic void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 186251538Srpaulostatic void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 187251538Srpaulostatic int urtwn_read_region_1(struct urtwn_softc *, uint16_t, 188251538Srpaulo uint8_t *, int); 189251538Srpaulostatic uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 190251538Srpaulostatic uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 191251538Srpaulostatic uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 192251538Srpaulostatic int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 193251538Srpaulo const void *, int); 194251538Srpaulostatic void urtwn_rf_write(struct urtwn_softc *, int, uint8_t, 195251538Srpaulo uint32_t); 196251538Srpaulostatic uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 197251538Srpaulostatic int urtwn_llt_write(struct urtwn_softc *, uint32_t, 198251538Srpaulo uint32_t); 199251538Srpaulostatic uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 200251538Srpaulostatic void urtwn_efuse_read(struct urtwn_softc *); 201251538Srpaulostatic int urtwn_read_chipid(struct urtwn_softc *); 202251538Srpaulostatic void urtwn_read_rom(struct urtwn_softc *); 203251538Srpaulostatic int urtwn_ra_init(struct urtwn_softc *); 204251538Srpaulostatic void urtwn_tsf_sync_enable(struct urtwn_softc *); 205251538Srpaulostatic void urtwn_set_led(struct urtwn_softc *, int, int); 206251538Srpaulostatic int urtwn_newstate(struct ieee80211vap *, 207251538Srpaulo enum ieee80211_state, int); 208251538Srpaulostatic void urtwn_watchdog(void *); 209251538Srpaulostatic void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 210251538Srpaulostatic int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 211251538Srpaulostatic int urtwn_tx_start(struct urtwn_softc *, 212251538Srpaulo struct ieee80211_node *, struct mbuf *, 213251538Srpaulo struct urtwn_data *); 214251538Srpaulostatic void urtwn_start(struct ifnet *); 215261863Srpaulostatic void urtwn_start_locked(struct ifnet *, 216261863Srpaulo struct urtwn_softc *); 217251538Srpaulostatic int urtwn_ioctl(struct ifnet *, u_long, caddr_t); 218251538Srpaulostatic int urtwn_power_on(struct urtwn_softc *); 219251538Srpaulostatic int urtwn_llt_init(struct urtwn_softc *); 220251538Srpaulostatic void urtwn_fw_reset(struct urtwn_softc *); 221251538Srpaulostatic int urtwn_fw_loadpage(struct urtwn_softc *, int, 222251538Srpaulo const uint8_t *, int); 223251538Srpaulostatic int urtwn_load_firmware(struct urtwn_softc *); 224251538Srpaulostatic int urtwn_dma_init(struct urtwn_softc *); 225251538Srpaulostatic void urtwn_mac_init(struct urtwn_softc *); 226251538Srpaulostatic void urtwn_bb_init(struct urtwn_softc *); 227251538Srpaulostatic void urtwn_rf_init(struct urtwn_softc *); 228251538Srpaulostatic void urtwn_cam_init(struct urtwn_softc *); 229251538Srpaulostatic void urtwn_pa_bias_init(struct urtwn_softc *); 230251538Srpaulostatic void urtwn_rxfilter_init(struct urtwn_softc *); 231251538Srpaulostatic void urtwn_edca_init(struct urtwn_softc *); 232251538Srpaulostatic void urtwn_write_txpower(struct urtwn_softc *, int, 233251538Srpaulo uint16_t[]); 234251538Srpaulostatic void urtwn_get_txpower(struct urtwn_softc *, int, 235251538Srpaulo struct ieee80211_channel *, 236251538Srpaulo struct ieee80211_channel *, uint16_t[]); 237251538Srpaulostatic void urtwn_set_txpower(struct urtwn_softc *, 238251538Srpaulo struct ieee80211_channel *, 239251538Srpaulo struct ieee80211_channel *); 240251538Srpaulostatic void urtwn_scan_start(struct ieee80211com *); 241251538Srpaulostatic void urtwn_scan_end(struct ieee80211com *); 242251538Srpaulostatic void urtwn_set_channel(struct ieee80211com *); 243251538Srpaulostatic void urtwn_set_chan(struct urtwn_softc *, 244251538Srpaulo struct ieee80211_channel *, 245251538Srpaulo struct ieee80211_channel *); 246251538Srpaulostatic void urtwn_update_mcast(struct ifnet *); 247251538Srpaulostatic void urtwn_iq_calib(struct urtwn_softc *); 248251538Srpaulostatic void urtwn_lc_calib(struct urtwn_softc *); 249251538Srpaulostatic void urtwn_init(void *); 250251538Srpaulostatic void urtwn_init_locked(void *); 251263153Skevlostatic void urtwn_stop(struct ifnet *); 252263153Skevlostatic void urtwn_stop_locked(struct ifnet *); 253251538Srpaulostatic void urtwn_abort_xfers(struct urtwn_softc *); 254251538Srpaulostatic int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 255251538Srpaulo const struct ieee80211_bpf_params *); 256251538Srpaulo 257251538Srpaulo/* Aliases. */ 258251538Srpaulo#define urtwn_bb_write urtwn_write_4 259251538Srpaulo#define urtwn_bb_read urtwn_read_4 260251538Srpaulo 261251538Srpaulostatic const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 262251538Srpaulo [URTWN_BULK_RX] = { 263251538Srpaulo .type = UE_BULK, 264251538Srpaulo .endpoint = UE_ADDR_ANY, 265251538Srpaulo .direction = UE_DIR_IN, 266251538Srpaulo .bufsize = URTWN_RXBUFSZ, 267251538Srpaulo .flags = { 268251538Srpaulo .pipe_bof = 1, 269251538Srpaulo .short_xfer_ok = 1 270251538Srpaulo }, 271251538Srpaulo .callback = urtwn_bulk_rx_callback, 272251538Srpaulo }, 273251538Srpaulo [URTWN_BULK_TX_BE] = { 274251538Srpaulo .type = UE_BULK, 275251538Srpaulo .endpoint = 0x03, 276251538Srpaulo .direction = UE_DIR_OUT, 277251538Srpaulo .bufsize = URTWN_TXBUFSZ, 278251538Srpaulo .flags = { 279251538Srpaulo .ext_buffer = 1, 280251538Srpaulo .pipe_bof = 1, 281251538Srpaulo .force_short_xfer = 1 282251538Srpaulo }, 283251538Srpaulo .callback = urtwn_bulk_tx_callback, 284251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 285251538Srpaulo }, 286251538Srpaulo [URTWN_BULK_TX_BK] = { 287251538Srpaulo .type = UE_BULK, 288251538Srpaulo .endpoint = 0x03, 289251538Srpaulo .direction = UE_DIR_OUT, 290251538Srpaulo .bufsize = URTWN_TXBUFSZ, 291251538Srpaulo .flags = { 292251538Srpaulo .ext_buffer = 1, 293251538Srpaulo .pipe_bof = 1, 294251538Srpaulo .force_short_xfer = 1, 295251538Srpaulo }, 296251538Srpaulo .callback = urtwn_bulk_tx_callback, 297251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 298251538Srpaulo }, 299251538Srpaulo [URTWN_BULK_TX_VI] = { 300251538Srpaulo .type = UE_BULK, 301251538Srpaulo .endpoint = 0x02, 302251538Srpaulo .direction = UE_DIR_OUT, 303251538Srpaulo .bufsize = URTWN_TXBUFSZ, 304251538Srpaulo .flags = { 305251538Srpaulo .ext_buffer = 1, 306251538Srpaulo .pipe_bof = 1, 307251538Srpaulo .force_short_xfer = 1 308251538Srpaulo }, 309251538Srpaulo .callback = urtwn_bulk_tx_callback, 310251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 311251538Srpaulo }, 312251538Srpaulo [URTWN_BULK_TX_VO] = { 313251538Srpaulo .type = UE_BULK, 314251538Srpaulo .endpoint = 0x02, 315251538Srpaulo .direction = UE_DIR_OUT, 316251538Srpaulo .bufsize = URTWN_TXBUFSZ, 317251538Srpaulo .flags = { 318251538Srpaulo .ext_buffer = 1, 319251538Srpaulo .pipe_bof = 1, 320251538Srpaulo .force_short_xfer = 1 321251538Srpaulo }, 322251538Srpaulo .callback = urtwn_bulk_tx_callback, 323251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 324251538Srpaulo }, 325251538Srpaulo}; 326251538Srpaulo 327251538Srpaulostatic int 328251538Srpaulourtwn_match(device_t self) 329251538Srpaulo{ 330251538Srpaulo struct usb_attach_arg *uaa = device_get_ivars(self); 331251538Srpaulo 332251538Srpaulo if (uaa->usb_mode != USB_MODE_HOST) 333251538Srpaulo return (ENXIO); 334251538Srpaulo if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 335251538Srpaulo return (ENXIO); 336251538Srpaulo if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 337251538Srpaulo return (ENXIO); 338251538Srpaulo 339251538Srpaulo return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 340251538Srpaulo} 341251538Srpaulo 342251538Srpaulostatic int 343251538Srpaulourtwn_attach(device_t self) 344251538Srpaulo{ 345251538Srpaulo struct usb_attach_arg *uaa = device_get_ivars(self); 346251538Srpaulo struct urtwn_softc *sc = device_get_softc(self); 347251538Srpaulo struct ifnet *ifp; 348251538Srpaulo struct ieee80211com *ic; 349251538Srpaulo uint8_t iface_index, bands; 350251538Srpaulo int error; 351251538Srpaulo 352251538Srpaulo device_set_usb_desc(self); 353251538Srpaulo sc->sc_udev = uaa->device; 354251538Srpaulo sc->sc_dev = self; 355251538Srpaulo 356251538Srpaulo mtx_init(&sc->sc_mtx, device_get_nameunit(self), 357251538Srpaulo MTX_NETWORK_LOCK, MTX_DEF); 358251538Srpaulo callout_init(&sc->sc_watchdog_ch, 0); 359251538Srpaulo 360251538Srpaulo iface_index = URTWN_IFACE_INDEX; 361251538Srpaulo error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 362251538Srpaulo urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 363251538Srpaulo if (error) { 364251538Srpaulo device_printf(self, "could not allocate USB transfers, " 365251538Srpaulo "err=%s\n", usbd_errstr(error)); 366251538Srpaulo goto detach; 367251538Srpaulo } 368251538Srpaulo 369251538Srpaulo URTWN_LOCK(sc); 370251538Srpaulo 371251538Srpaulo error = urtwn_read_chipid(sc); 372251538Srpaulo if (error) { 373251538Srpaulo device_printf(sc->sc_dev, "unsupported test chip\n"); 374251538Srpaulo URTWN_UNLOCK(sc); 375251538Srpaulo goto detach; 376251538Srpaulo } 377251538Srpaulo 378251538Srpaulo /* Determine number of Tx/Rx chains. */ 379251538Srpaulo if (sc->chip & URTWN_CHIP_92C) { 380251538Srpaulo sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 381251538Srpaulo sc->nrxchains = 2; 382251538Srpaulo } else { 383251538Srpaulo sc->ntxchains = 1; 384251538Srpaulo sc->nrxchains = 1; 385251538Srpaulo } 386251538Srpaulo urtwn_read_rom(sc); 387251538Srpaulo 388251538Srpaulo device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 389251538Srpaulo (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 390251538Srpaulo (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 391251538Srpaulo (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 392251538Srpaulo "8188CUS", sc->ntxchains, sc->nrxchains); 393251538Srpaulo 394251538Srpaulo URTWN_UNLOCK(sc); 395251538Srpaulo 396251538Srpaulo ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 397251538Srpaulo if (ifp == NULL) { 398251538Srpaulo device_printf(sc->sc_dev, "can not if_alloc()\n"); 399251538Srpaulo goto detach; 400251538Srpaulo } 401251538Srpaulo ic = ifp->if_l2com; 402251538Srpaulo 403251538Srpaulo ifp->if_softc = sc; 404251538Srpaulo if_initname(ifp, "urtwn", device_get_unit(sc->sc_dev)); 405251538Srpaulo ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 406251538Srpaulo ifp->if_init = urtwn_init; 407251538Srpaulo ifp->if_ioctl = urtwn_ioctl; 408251538Srpaulo ifp->if_start = urtwn_start; 409251538Srpaulo IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 410251538Srpaulo ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 411251538Srpaulo IFQ_SET_READY(&ifp->if_snd); 412251538Srpaulo 413251538Srpaulo ic->ic_ifp = ifp; 414251538Srpaulo ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 415251538Srpaulo ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 416251538Srpaulo 417251538Srpaulo /* set device capabilities */ 418251538Srpaulo ic->ic_caps = 419251538Srpaulo IEEE80211_C_STA /* station mode */ 420251538Srpaulo | IEEE80211_C_MONITOR /* monitor mode */ 421251538Srpaulo | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 422251538Srpaulo | IEEE80211_C_SHSLOT /* short slot time supported */ 423251538Srpaulo | IEEE80211_C_BGSCAN /* capable of bg scanning */ 424251538Srpaulo | IEEE80211_C_WPA /* 802.11i */ 425251538Srpaulo ; 426251538Srpaulo 427251538Srpaulo bands = 0; 428251538Srpaulo setbit(&bands, IEEE80211_MODE_11B); 429251538Srpaulo setbit(&bands, IEEE80211_MODE_11G); 430251538Srpaulo ieee80211_init_channels(ic, NULL, &bands); 431251538Srpaulo 432251538Srpaulo ieee80211_ifattach(ic, sc->sc_bssid); 433251538Srpaulo ic->ic_raw_xmit = urtwn_raw_xmit; 434251538Srpaulo ic->ic_scan_start = urtwn_scan_start; 435251538Srpaulo ic->ic_scan_end = urtwn_scan_end; 436251538Srpaulo ic->ic_set_channel = urtwn_set_channel; 437251538Srpaulo 438251538Srpaulo ic->ic_vap_create = urtwn_vap_create; 439251538Srpaulo ic->ic_vap_delete = urtwn_vap_delete; 440251538Srpaulo ic->ic_update_mcast = urtwn_update_mcast; 441251538Srpaulo 442251538Srpaulo ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 443251538Srpaulo sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 444251538Srpaulo &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 445251538Srpaulo URTWN_RX_RADIOTAP_PRESENT); 446251538Srpaulo 447251538Srpaulo if (bootverbose) 448251538Srpaulo ieee80211_announce(ic); 449251538Srpaulo 450251538Srpaulo return (0); 451251538Srpaulo 452251538Srpaulodetach: 453251538Srpaulo urtwn_detach(self); 454251538Srpaulo return (ENXIO); /* failure */ 455251538Srpaulo} 456251538Srpaulo 457251538Srpaulostatic int 458251538Srpaulourtwn_detach(device_t self) 459251538Srpaulo{ 460251538Srpaulo struct urtwn_softc *sc = device_get_softc(self); 461251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 462251538Srpaulo struct ieee80211com *ic = ifp->if_l2com; 463263153Skevlo unsigned int x; 464251538Srpaulo 465263153Skevlo /* Prevent further ioctls. */ 466263153Skevlo URTWN_LOCK(sc); 467263153Skevlo sc->sc_flags |= URTWN_DETACHED; 468263153Skevlo URTWN_UNLOCK(sc); 469251538Srpaulo 470263153Skevlo urtwn_stop(ifp); 471251538Srpaulo 472251538Srpaulo callout_drain(&sc->sc_watchdog_ch); 473251538Srpaulo 474263153Skevlo /* Prevent further allocations from RX/TX data lists. */ 475263153Skevlo URTWN_LOCK(sc); 476263153Skevlo STAILQ_INIT(&sc->sc_tx_active); 477263153Skevlo STAILQ_INIT(&sc->sc_tx_inactive); 478263153Skevlo STAILQ_INIT(&sc->sc_tx_pending); 479263153Skevlo 480263153Skevlo STAILQ_INIT(&sc->sc_rx_active); 481263153Skevlo STAILQ_INIT(&sc->sc_rx_inactive); 482263153Skevlo URTWN_UNLOCK(sc); 483263153Skevlo 484263153Skevlo /* drain USB transfers */ 485263153Skevlo for (x = 0; x != URTWN_N_TRANSFER; x++) 486263153Skevlo usbd_transfer_drain(sc->sc_xfer[x]); 487263153Skevlo 488263153Skevlo /* Free data buffers. */ 489263153Skevlo URTWN_LOCK(sc); 490263153Skevlo urtwn_free_tx_list(sc); 491263153Skevlo urtwn_free_rx_list(sc); 492263153Skevlo URTWN_UNLOCK(sc); 493263153Skevlo 494251538Srpaulo /* stop all USB transfers */ 495251538Srpaulo usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 496251538Srpaulo ieee80211_ifdetach(ic); 497251538Srpaulo 498251538Srpaulo if_free(ifp); 499251538Srpaulo mtx_destroy(&sc->sc_mtx); 500251538Srpaulo 501251538Srpaulo return (0); 502251538Srpaulo} 503251538Srpaulo 504251538Srpaulostatic void 505251538Srpaulourtwn_free_tx_list(struct urtwn_softc *sc) 506251538Srpaulo{ 507251538Srpaulo urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 508251538Srpaulo} 509251538Srpaulo 510251538Srpaulostatic void 511251538Srpaulourtwn_free_rx_list(struct urtwn_softc *sc) 512251538Srpaulo{ 513251538Srpaulo urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 514251538Srpaulo} 515251538Srpaulo 516251538Srpaulostatic void 517251538Srpaulourtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 518251538Srpaulo{ 519251538Srpaulo int i; 520251538Srpaulo 521251538Srpaulo for (i = 0; i < ndata; i++) { 522251538Srpaulo struct urtwn_data *dp = &data[i]; 523251538Srpaulo 524251538Srpaulo if (dp->buf != NULL) { 525251538Srpaulo free(dp->buf, M_USBDEV); 526251538Srpaulo dp->buf = NULL; 527251538Srpaulo } 528251538Srpaulo if (dp->ni != NULL) { 529251538Srpaulo ieee80211_free_node(dp->ni); 530251538Srpaulo dp->ni = NULL; 531251538Srpaulo } 532251538Srpaulo } 533251538Srpaulo} 534251538Srpaulo 535251538Srpaulostatic usb_error_t 536251538Srpaulourtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 537251538Srpaulo void *data) 538251538Srpaulo{ 539251538Srpaulo usb_error_t err; 540251538Srpaulo int ntries = 10; 541251538Srpaulo 542251538Srpaulo URTWN_ASSERT_LOCKED(sc); 543251538Srpaulo 544251538Srpaulo while (ntries--) { 545251538Srpaulo err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 546251538Srpaulo req, data, 0, NULL, 250 /* ms */); 547251538Srpaulo if (err == 0) 548251538Srpaulo break; 549251538Srpaulo 550251538Srpaulo DPRINTFN(1, "Control request failed, %s (retrying)\n", 551251538Srpaulo usbd_errstr(err)); 552251538Srpaulo usb_pause_mtx(&sc->sc_mtx, hz / 100); 553251538Srpaulo } 554251538Srpaulo return (err); 555251538Srpaulo} 556251538Srpaulo 557251538Srpaulostatic struct ieee80211vap * 558251538Srpaulourtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 559251538Srpaulo enum ieee80211_opmode opmode, int flags, 560251538Srpaulo const uint8_t bssid[IEEE80211_ADDR_LEN], 561251538Srpaulo const uint8_t mac[IEEE80211_ADDR_LEN]) 562251538Srpaulo{ 563251538Srpaulo struct urtwn_vap *uvp; 564251538Srpaulo struct ieee80211vap *vap; 565251538Srpaulo 566251538Srpaulo if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 567251538Srpaulo return (NULL); 568251538Srpaulo 569251538Srpaulo uvp = (struct urtwn_vap *) malloc(sizeof(struct urtwn_vap), 570251538Srpaulo M_80211_VAP, M_NOWAIT | M_ZERO); 571251538Srpaulo if (uvp == NULL) 572251538Srpaulo return (NULL); 573251538Srpaulo vap = &uvp->vap; 574251538Srpaulo /* enable s/w bmiss handling for sta mode */ 575251538Srpaulo 576257743Shselasky if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 577257743Shselasky flags | IEEE80211_CLONE_NOBEACONS, bssid, mac) != 0) { 578257743Shselasky /* out of memory */ 579257743Shselasky free(uvp, M_80211_VAP); 580257743Shselasky return (NULL); 581257743Shselasky } 582257743Shselasky 583251538Srpaulo /* override state transition machine */ 584251538Srpaulo uvp->newstate = vap->iv_newstate; 585251538Srpaulo vap->iv_newstate = urtwn_newstate; 586251538Srpaulo 587251538Srpaulo /* complete setup */ 588251538Srpaulo ieee80211_vap_attach(vap, ieee80211_media_change, 589251538Srpaulo ieee80211_media_status); 590251538Srpaulo ic->ic_opmode = opmode; 591251538Srpaulo return (vap); 592251538Srpaulo} 593251538Srpaulo 594251538Srpaulostatic void 595251538Srpaulourtwn_vap_delete(struct ieee80211vap *vap) 596251538Srpaulo{ 597251538Srpaulo struct urtwn_vap *uvp = URTWN_VAP(vap); 598251538Srpaulo 599251538Srpaulo ieee80211_vap_detach(vap); 600251538Srpaulo free(uvp, M_80211_VAP); 601251538Srpaulo} 602251538Srpaulo 603251538Srpaulostatic struct mbuf * 604251538Srpaulourtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 605251538Srpaulo{ 606251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 607251538Srpaulo struct ieee80211com *ic = ifp->if_l2com; 608251538Srpaulo struct ieee80211_frame *wh; 609251538Srpaulo struct mbuf *m; 610251538Srpaulo struct r92c_rx_stat *stat; 611251538Srpaulo uint32_t rxdw0, rxdw3; 612251538Srpaulo uint8_t rate; 613251538Srpaulo int8_t rssi = 0; 614251538Srpaulo int infosz; 615251538Srpaulo 616251538Srpaulo /* 617251538Srpaulo * don't pass packets to the ieee80211 framework if the driver isn't 618251538Srpaulo * RUNNING. 619251538Srpaulo */ 620251538Srpaulo if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 621251538Srpaulo return (NULL); 622251538Srpaulo 623251538Srpaulo stat = (struct r92c_rx_stat *)buf; 624251538Srpaulo rxdw0 = le32toh(stat->rxdw0); 625251538Srpaulo rxdw3 = le32toh(stat->rxdw3); 626251538Srpaulo 627251538Srpaulo if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 628251538Srpaulo /* 629251538Srpaulo * This should not happen since we setup our Rx filter 630251538Srpaulo * to not receive these frames. 631251538Srpaulo */ 632251538Srpaulo ifp->if_ierrors++; 633251538Srpaulo return (NULL); 634251538Srpaulo } 635251538Srpaulo 636251538Srpaulo rate = MS(rxdw3, R92C_RXDW3_RATE); 637251538Srpaulo infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 638251538Srpaulo 639251538Srpaulo /* Get RSSI from PHY status descriptor if present. */ 640251538Srpaulo if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 641251538Srpaulo rssi = urtwn_get_rssi(sc, rate, &stat[1]); 642251538Srpaulo /* Update our average RSSI. */ 643251538Srpaulo urtwn_update_avgrssi(sc, rate, rssi); 644252405Srpaulo /* 645252405Srpaulo * Convert the RSSI to a range that will be accepted 646252405Srpaulo * by net80211. 647252405Srpaulo */ 648252405Srpaulo rssi = URTWN_RSSI(rssi); 649251538Srpaulo } 650251538Srpaulo 651260463Skevlo m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 652251538Srpaulo if (m == NULL) { 653251538Srpaulo device_printf(sc->sc_dev, "could not create RX mbuf\n"); 654251538Srpaulo return (NULL); 655251538Srpaulo } 656251538Srpaulo 657251538Srpaulo /* Finalize mbuf. */ 658251538Srpaulo m->m_pkthdr.rcvif = ifp; 659251538Srpaulo wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 660251538Srpaulo memcpy(mtod(m, uint8_t *), wh, pktlen); 661251538Srpaulo m->m_pkthdr.len = m->m_len = pktlen; 662251538Srpaulo 663251538Srpaulo if (ieee80211_radiotap_active(ic)) { 664251538Srpaulo struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 665251538Srpaulo 666251538Srpaulo tap->wr_flags = 0; 667251538Srpaulo /* Map HW rate index to 802.11 rate. */ 668251538Srpaulo if (!(rxdw3 & R92C_RXDW3_HT)) { 669251538Srpaulo switch (rate) { 670251538Srpaulo /* CCK. */ 671251538Srpaulo case 0: tap->wr_rate = 2; break; 672251538Srpaulo case 1: tap->wr_rate = 4; break; 673251538Srpaulo case 2: tap->wr_rate = 11; break; 674251538Srpaulo case 3: tap->wr_rate = 22; break; 675251538Srpaulo /* OFDM. */ 676251538Srpaulo case 4: tap->wr_rate = 12; break; 677251538Srpaulo case 5: tap->wr_rate = 18; break; 678251538Srpaulo case 6: tap->wr_rate = 24; break; 679251538Srpaulo case 7: tap->wr_rate = 36; break; 680251538Srpaulo case 8: tap->wr_rate = 48; break; 681251538Srpaulo case 9: tap->wr_rate = 72; break; 682251538Srpaulo case 10: tap->wr_rate = 96; break; 683251538Srpaulo case 11: tap->wr_rate = 108; break; 684251538Srpaulo } 685251538Srpaulo } else if (rate >= 12) { /* MCS0~15. */ 686251538Srpaulo /* Bit 7 set means HT MCS instead of rate. */ 687251538Srpaulo tap->wr_rate = 0x80 | (rate - 12); 688251538Srpaulo } 689251538Srpaulo tap->wr_dbm_antsignal = rssi; 690251538Srpaulo tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 691251538Srpaulo tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 692251538Srpaulo } 693251538Srpaulo 694251538Srpaulo *rssi_p = rssi; 695251538Srpaulo 696251538Srpaulo return (m); 697251538Srpaulo} 698251538Srpaulo 699251538Srpaulostatic struct mbuf * 700251538Srpaulourtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 701251538Srpaulo int8_t *nf) 702251538Srpaulo{ 703251538Srpaulo struct urtwn_softc *sc = data->sc; 704251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 705251538Srpaulo struct r92c_rx_stat *stat; 706251538Srpaulo struct mbuf *m, *m0 = NULL, *prevm = NULL; 707251538Srpaulo uint32_t rxdw0; 708251538Srpaulo uint8_t *buf; 709251538Srpaulo int len, totlen, pktlen, infosz, npkts; 710251538Srpaulo 711251538Srpaulo usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 712251538Srpaulo 713251538Srpaulo if (len < sizeof(*stat)) { 714251538Srpaulo ifp->if_ierrors++; 715251538Srpaulo return (NULL); 716251538Srpaulo } 717251538Srpaulo 718251538Srpaulo buf = data->buf; 719251538Srpaulo /* Get the number of encapsulated frames. */ 720251538Srpaulo stat = (struct r92c_rx_stat *)buf; 721251538Srpaulo npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 722251538Srpaulo DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 723251538Srpaulo 724251538Srpaulo /* Process all of them. */ 725251538Srpaulo while (npkts-- > 0) { 726251538Srpaulo if (len < sizeof(*stat)) 727251538Srpaulo break; 728251538Srpaulo stat = (struct r92c_rx_stat *)buf; 729251538Srpaulo rxdw0 = le32toh(stat->rxdw0); 730251538Srpaulo 731251538Srpaulo pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 732251538Srpaulo if (pktlen == 0) 733251538Srpaulo break; 734251538Srpaulo 735251538Srpaulo infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 736251538Srpaulo 737251538Srpaulo /* Make sure everything fits in xfer. */ 738251538Srpaulo totlen = sizeof(*stat) + infosz + pktlen; 739251538Srpaulo if (totlen > len) 740251538Srpaulo break; 741251538Srpaulo 742251538Srpaulo m = urtwn_rx_frame(sc, buf, pktlen, rssi); 743251538Srpaulo if (m0 == NULL) 744251538Srpaulo m0 = m; 745251538Srpaulo if (prevm == NULL) 746251538Srpaulo prevm = m; 747251538Srpaulo else { 748251538Srpaulo prevm->m_next = m; 749251538Srpaulo prevm = m; 750251538Srpaulo } 751251538Srpaulo 752251538Srpaulo /* Next chunk is 128-byte aligned. */ 753251538Srpaulo totlen = (totlen + 127) & ~127; 754251538Srpaulo buf += totlen; 755251538Srpaulo len -= totlen; 756251538Srpaulo } 757251538Srpaulo 758251538Srpaulo return (m0); 759251538Srpaulo} 760251538Srpaulo 761251538Srpaulostatic void 762251538Srpaulourtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 763251538Srpaulo{ 764251538Srpaulo struct urtwn_softc *sc = usbd_xfer_softc(xfer); 765251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 766251538Srpaulo struct ieee80211com *ic = ifp->if_l2com; 767251538Srpaulo struct ieee80211_frame *wh; 768251538Srpaulo struct ieee80211_node *ni; 769251538Srpaulo struct mbuf *m = NULL, *next; 770251538Srpaulo struct urtwn_data *data; 771251538Srpaulo int8_t nf; 772251538Srpaulo int rssi = 1; 773251538Srpaulo 774251538Srpaulo URTWN_ASSERT_LOCKED(sc); 775251538Srpaulo 776251538Srpaulo switch (USB_GET_STATE(xfer)) { 777251538Srpaulo case USB_ST_TRANSFERRED: 778251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_active); 779251538Srpaulo if (data == NULL) 780251538Srpaulo goto tr_setup; 781251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 782251538Srpaulo m = urtwn_rxeof(xfer, data, &rssi, &nf); 783251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 784251538Srpaulo /* FALLTHROUGH */ 785251538Srpaulo case USB_ST_SETUP: 786251538Srpaulotr_setup: 787251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_inactive); 788251538Srpaulo if (data == NULL) { 789251538Srpaulo KASSERT(m == NULL, ("mbuf isn't NULL")); 790251538Srpaulo return; 791251538Srpaulo } 792251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 793251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 794251538Srpaulo usbd_xfer_set_frame_data(xfer, 0, data->buf, 795251538Srpaulo usbd_xfer_max_len(xfer)); 796251538Srpaulo usbd_transfer_submit(xfer); 797251538Srpaulo 798251538Srpaulo /* 799251538Srpaulo * To avoid LOR we should unlock our private mutex here to call 800251538Srpaulo * ieee80211_input() because here is at the end of a USB 801251538Srpaulo * callback and safe to unlock. 802251538Srpaulo */ 803251538Srpaulo URTWN_UNLOCK(sc); 804251538Srpaulo while (m != NULL) { 805251538Srpaulo next = m->m_next; 806251538Srpaulo m->m_next = NULL; 807251538Srpaulo wh = mtod(m, struct ieee80211_frame *); 808251538Srpaulo ni = ieee80211_find_rxnode(ic, 809251538Srpaulo (struct ieee80211_frame_min *)wh); 810251538Srpaulo nf = URTWN_NOISE_FLOOR; 811251538Srpaulo if (ni != NULL) { 812251538Srpaulo (void)ieee80211_input(ni, m, rssi, nf); 813251538Srpaulo ieee80211_free_node(ni); 814251538Srpaulo } else 815251538Srpaulo (void)ieee80211_input_all(ic, m, rssi, nf); 816251538Srpaulo m = next; 817251538Srpaulo } 818251538Srpaulo URTWN_LOCK(sc); 819251538Srpaulo break; 820251538Srpaulo default: 821251538Srpaulo /* needs it to the inactive queue due to a error. */ 822251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_active); 823251538Srpaulo if (data != NULL) { 824251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 825251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 826251538Srpaulo } 827251538Srpaulo if (error != USB_ERR_CANCELLED) { 828251538Srpaulo usbd_xfer_set_stall(xfer); 829251538Srpaulo ifp->if_ierrors++; 830251538Srpaulo goto tr_setup; 831251538Srpaulo } 832251538Srpaulo break; 833251538Srpaulo } 834251538Srpaulo} 835251538Srpaulo 836251538Srpaulostatic void 837251538Srpaulourtwn_txeof(struct usb_xfer *xfer, struct urtwn_data *data) 838251538Srpaulo{ 839251538Srpaulo struct urtwn_softc *sc = usbd_xfer_softc(xfer); 840251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 841251538Srpaulo struct mbuf *m; 842251538Srpaulo 843251538Srpaulo URTWN_ASSERT_LOCKED(sc); 844251538Srpaulo 845251538Srpaulo /* 846251538Srpaulo * Do any tx complete callback. Note this must be done before releasing 847251538Srpaulo * the node reference. 848251538Srpaulo */ 849251538Srpaulo if (data->m) { 850251538Srpaulo m = data->m; 851251538Srpaulo if (m->m_flags & M_TXCB) { 852251538Srpaulo /* XXX status? */ 853251538Srpaulo ieee80211_process_callback(data->ni, m, 0); 854251538Srpaulo } 855251538Srpaulo m_freem(m); 856251538Srpaulo data->m = NULL; 857251538Srpaulo } 858251538Srpaulo if (data->ni) { 859251538Srpaulo ieee80211_free_node(data->ni); 860251538Srpaulo data->ni = NULL; 861251538Srpaulo } 862251538Srpaulo sc->sc_txtimer = 0; 863251538Srpaulo ifp->if_opackets++; 864251538Srpaulo ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 865251538Srpaulo} 866251538Srpaulo 867251538Srpaulostatic void 868251538Srpaulourtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 869251538Srpaulo{ 870251538Srpaulo struct urtwn_softc *sc = usbd_xfer_softc(xfer); 871251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 872251538Srpaulo struct urtwn_data *data; 873251538Srpaulo 874251538Srpaulo URTWN_ASSERT_LOCKED(sc); 875251538Srpaulo 876251538Srpaulo switch (USB_GET_STATE(xfer)){ 877251538Srpaulo case USB_ST_TRANSFERRED: 878251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_active); 879251538Srpaulo if (data == NULL) 880251538Srpaulo goto tr_setup; 881251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 882251538Srpaulo urtwn_txeof(xfer, data); 883251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 884251538Srpaulo /* FALLTHROUGH */ 885251538Srpaulo case USB_ST_SETUP: 886251538Srpaulotr_setup: 887251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_pending); 888251538Srpaulo if (data == NULL) { 889251538Srpaulo DPRINTF("%s: empty pending queue\n", __func__); 890251538Srpaulo return; 891251538Srpaulo } 892251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 893251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 894251538Srpaulo usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 895251538Srpaulo usbd_transfer_submit(xfer); 896261863Srpaulo urtwn_start_locked(ifp, sc); 897251538Srpaulo break; 898251538Srpaulo default: 899251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_active); 900251538Srpaulo if (data == NULL) 901251538Srpaulo goto tr_setup; 902251538Srpaulo if (data->ni != NULL) { 903251538Srpaulo ieee80211_free_node(data->ni); 904251538Srpaulo data->ni = NULL; 905251538Srpaulo ifp->if_oerrors++; 906251538Srpaulo } 907251538Srpaulo if (error != USB_ERR_CANCELLED) { 908251538Srpaulo usbd_xfer_set_stall(xfer); 909251538Srpaulo goto tr_setup; 910251538Srpaulo } 911251538Srpaulo break; 912251538Srpaulo } 913251538Srpaulo} 914251538Srpaulo 915251538Srpaulostatic struct urtwn_data * 916251538Srpaulo_urtwn_getbuf(struct urtwn_softc *sc) 917251538Srpaulo{ 918251538Srpaulo struct urtwn_data *bf; 919251538Srpaulo 920251538Srpaulo bf = STAILQ_FIRST(&sc->sc_tx_inactive); 921251538Srpaulo if (bf != NULL) 922251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 923251538Srpaulo else 924251538Srpaulo bf = NULL; 925251538Srpaulo if (bf == NULL) 926251538Srpaulo DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 927251538Srpaulo return (bf); 928251538Srpaulo} 929251538Srpaulo 930251538Srpaulostatic struct urtwn_data * 931251538Srpaulourtwn_getbuf(struct urtwn_softc *sc) 932251538Srpaulo{ 933251538Srpaulo struct urtwn_data *bf; 934251538Srpaulo 935251538Srpaulo URTWN_ASSERT_LOCKED(sc); 936251538Srpaulo 937251538Srpaulo bf = _urtwn_getbuf(sc); 938251538Srpaulo if (bf == NULL) { 939251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 940251538Srpaulo DPRINTF("%s: stop queue\n", __func__); 941251538Srpaulo ifp->if_drv_flags |= IFF_DRV_OACTIVE; 942251538Srpaulo } 943251538Srpaulo return (bf); 944251538Srpaulo} 945251538Srpaulo 946251538Srpaulostatic int 947251538Srpaulourtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 948251538Srpaulo int len) 949251538Srpaulo{ 950251538Srpaulo usb_device_request_t req; 951251538Srpaulo 952251538Srpaulo req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 953251538Srpaulo req.bRequest = R92C_REQ_REGS; 954251538Srpaulo USETW(req.wValue, addr); 955251538Srpaulo USETW(req.wIndex, 0); 956251538Srpaulo USETW(req.wLength, len); 957251538Srpaulo return (urtwn_do_request(sc, &req, buf)); 958251538Srpaulo} 959251538Srpaulo 960251538Srpaulostatic void 961251538Srpaulourtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 962251538Srpaulo{ 963251538Srpaulo urtwn_write_region_1(sc, addr, &val, 1); 964251538Srpaulo} 965251538Srpaulo 966251538Srpaulo 967251538Srpaulostatic void 968251538Srpaulourtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 969251538Srpaulo{ 970251538Srpaulo val = htole16(val); 971251538Srpaulo urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 972251538Srpaulo} 973251538Srpaulo 974251538Srpaulostatic void 975251538Srpaulourtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 976251538Srpaulo{ 977251538Srpaulo val = htole32(val); 978251538Srpaulo urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 979251538Srpaulo} 980251538Srpaulo 981251538Srpaulostatic int 982251538Srpaulourtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 983251538Srpaulo int len) 984251538Srpaulo{ 985251538Srpaulo usb_device_request_t req; 986251538Srpaulo 987251538Srpaulo req.bmRequestType = UT_READ_VENDOR_DEVICE; 988251538Srpaulo req.bRequest = R92C_REQ_REGS; 989251538Srpaulo USETW(req.wValue, addr); 990251538Srpaulo USETW(req.wIndex, 0); 991251538Srpaulo USETW(req.wLength, len); 992251538Srpaulo return (urtwn_do_request(sc, &req, buf)); 993251538Srpaulo} 994251538Srpaulo 995251538Srpaulostatic uint8_t 996251538Srpaulourtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 997251538Srpaulo{ 998251538Srpaulo uint8_t val; 999251538Srpaulo 1000251538Srpaulo if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1001251538Srpaulo return (0xff); 1002251538Srpaulo return (val); 1003251538Srpaulo} 1004251538Srpaulo 1005251538Srpaulostatic uint16_t 1006251538Srpaulourtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1007251538Srpaulo{ 1008251538Srpaulo uint16_t val; 1009251538Srpaulo 1010251538Srpaulo if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1011251538Srpaulo return (0xffff); 1012251538Srpaulo return (le16toh(val)); 1013251538Srpaulo} 1014251538Srpaulo 1015251538Srpaulostatic uint32_t 1016251538Srpaulourtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1017251538Srpaulo{ 1018251538Srpaulo uint32_t val; 1019251538Srpaulo 1020251538Srpaulo if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1021251538Srpaulo return (0xffffffff); 1022251538Srpaulo return (le32toh(val)); 1023251538Srpaulo} 1024251538Srpaulo 1025251538Srpaulostatic int 1026251538Srpaulourtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1027251538Srpaulo{ 1028251538Srpaulo struct r92c_fw_cmd cmd; 1029251538Srpaulo int ntries; 1030251538Srpaulo 1031251538Srpaulo /* Wait for current FW box to be empty. */ 1032251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 1033251538Srpaulo if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1034251538Srpaulo break; 1035251538Srpaulo DELAY(1); 1036251538Srpaulo } 1037251538Srpaulo if (ntries == 100) { 1038251538Srpaulo device_printf(sc->sc_dev, 1039251538Srpaulo "could not send firmware command\n"); 1040251538Srpaulo return (ETIMEDOUT); 1041251538Srpaulo } 1042251538Srpaulo memset(&cmd, 0, sizeof(cmd)); 1043251538Srpaulo cmd.id = id; 1044251538Srpaulo if (len > 3) 1045251538Srpaulo cmd.id |= R92C_CMD_FLAG_EXT; 1046251538Srpaulo KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1047251538Srpaulo memcpy(cmd.msg, buf, len); 1048251538Srpaulo 1049251538Srpaulo /* Write the first word last since that will trigger the FW. */ 1050251538Srpaulo urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1051251538Srpaulo (uint8_t *)&cmd + 4, 2); 1052251538Srpaulo urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1053251538Srpaulo (uint8_t *)&cmd + 0, 4); 1054251538Srpaulo 1055251538Srpaulo sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1056251538Srpaulo return (0); 1057251538Srpaulo} 1058251538Srpaulo 1059251538Srpaulostatic void 1060251538Srpaulourtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1061251538Srpaulo{ 1062251538Srpaulo urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1063251538Srpaulo SM(R92C_LSSI_PARAM_ADDR, addr) | 1064251538Srpaulo SM(R92C_LSSI_PARAM_DATA, val)); 1065251538Srpaulo} 1066251538Srpaulo 1067251538Srpaulostatic uint32_t 1068251538Srpaulourtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1069251538Srpaulo{ 1070251538Srpaulo uint32_t reg[R92C_MAX_CHAINS], val; 1071251538Srpaulo 1072251538Srpaulo reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1073251538Srpaulo if (chain != 0) 1074251538Srpaulo reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1075251538Srpaulo 1076251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1077251538Srpaulo reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1078251538Srpaulo DELAY(1000); 1079251538Srpaulo 1080251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1081251538Srpaulo RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1082251538Srpaulo R92C_HSSI_PARAM2_READ_EDGE); 1083251538Srpaulo DELAY(1000); 1084251538Srpaulo 1085251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1086251538Srpaulo reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1087251538Srpaulo DELAY(1000); 1088251538Srpaulo 1089251538Srpaulo if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1090251538Srpaulo val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1091251538Srpaulo else 1092251538Srpaulo val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1093251538Srpaulo return (MS(val, R92C_LSSI_READBACK_DATA)); 1094251538Srpaulo} 1095251538Srpaulo 1096251538Srpaulostatic int 1097251538Srpaulourtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1098251538Srpaulo{ 1099251538Srpaulo int ntries; 1100251538Srpaulo 1101251538Srpaulo urtwn_write_4(sc, R92C_LLT_INIT, 1102251538Srpaulo SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1103251538Srpaulo SM(R92C_LLT_INIT_ADDR, addr) | 1104251538Srpaulo SM(R92C_LLT_INIT_DATA, data)); 1105251538Srpaulo /* Wait for write operation to complete. */ 1106251538Srpaulo for (ntries = 0; ntries < 20; ntries++) { 1107251538Srpaulo if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1108251538Srpaulo R92C_LLT_INIT_OP_NO_ACTIVE) 1109251538Srpaulo return (0); 1110251538Srpaulo DELAY(5); 1111251538Srpaulo } 1112251538Srpaulo return (ETIMEDOUT); 1113251538Srpaulo} 1114251538Srpaulo 1115251538Srpaulostatic uint8_t 1116251538Srpaulourtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1117251538Srpaulo{ 1118251538Srpaulo uint32_t reg; 1119251538Srpaulo int ntries; 1120251538Srpaulo 1121251538Srpaulo reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1122251538Srpaulo reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1123251538Srpaulo reg &= ~R92C_EFUSE_CTRL_VALID; 1124251538Srpaulo urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1125251538Srpaulo /* Wait for read operation to complete. */ 1126251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 1127251538Srpaulo reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1128251538Srpaulo if (reg & R92C_EFUSE_CTRL_VALID) 1129251538Srpaulo return (MS(reg, R92C_EFUSE_CTRL_DATA)); 1130251538Srpaulo DELAY(5); 1131251538Srpaulo } 1132251538Srpaulo device_printf(sc->sc_dev, 1133251538Srpaulo "could not read efuse byte at address 0x%x\n", addr); 1134251538Srpaulo return (0xff); 1135251538Srpaulo} 1136251538Srpaulo 1137251538Srpaulostatic void 1138251538Srpaulourtwn_efuse_read(struct urtwn_softc *sc) 1139251538Srpaulo{ 1140251538Srpaulo uint8_t *rom = (uint8_t *)&sc->rom; 1141251538Srpaulo uint16_t addr = 0; 1142251538Srpaulo uint32_t reg; 1143251538Srpaulo uint8_t off, msk; 1144251538Srpaulo int i; 1145251538Srpaulo 1146251538Srpaulo reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1147251538Srpaulo if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1148251538Srpaulo urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1149251538Srpaulo reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1150251538Srpaulo } 1151251538Srpaulo reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1152251538Srpaulo if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1153251538Srpaulo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1154251538Srpaulo reg | R92C_SYS_FUNC_EN_ELDR); 1155251538Srpaulo } 1156251538Srpaulo reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1157251538Srpaulo if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1158251538Srpaulo (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1159251538Srpaulo urtwn_write_2(sc, R92C_SYS_CLKR, 1160251538Srpaulo reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1161251538Srpaulo } 1162251538Srpaulo memset(&sc->rom, 0xff, sizeof(sc->rom)); 1163251538Srpaulo while (addr < 512) { 1164251538Srpaulo reg = urtwn_efuse_read_1(sc, addr); 1165251538Srpaulo if (reg == 0xff) 1166251538Srpaulo break; 1167251538Srpaulo addr++; 1168251538Srpaulo off = reg >> 4; 1169251538Srpaulo msk = reg & 0xf; 1170251538Srpaulo for (i = 0; i < 4; i++) { 1171251538Srpaulo if (msk & (1 << i)) 1172251538Srpaulo continue; 1173251538Srpaulo rom[off * 8 + i * 2 + 0] = 1174251538Srpaulo urtwn_efuse_read_1(sc, addr); 1175251538Srpaulo addr++; 1176251538Srpaulo rom[off * 8 + i * 2 + 1] = 1177251538Srpaulo urtwn_efuse_read_1(sc, addr); 1178251538Srpaulo addr++; 1179251538Srpaulo } 1180251538Srpaulo } 1181251538Srpaulo#ifdef URTWN_DEBUG 1182251538Srpaulo if (urtwn_debug >= 2) { 1183251538Srpaulo /* Dump ROM content. */ 1184251538Srpaulo printf("\n"); 1185251538Srpaulo for (i = 0; i < sizeof(sc->rom); i++) 1186251538Srpaulo printf("%02x:", rom[i]); 1187251538Srpaulo printf("\n"); 1188251538Srpaulo } 1189251538Srpaulo#endif 1190251538Srpaulo} 1191251538Srpaulo 1192251538Srpaulostatic int 1193251538Srpaulourtwn_read_chipid(struct urtwn_softc *sc) 1194251538Srpaulo{ 1195251538Srpaulo uint32_t reg; 1196251538Srpaulo 1197251538Srpaulo reg = urtwn_read_4(sc, R92C_SYS_CFG); 1198251538Srpaulo if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1199251538Srpaulo return (EIO); 1200251538Srpaulo 1201251538Srpaulo if (reg & R92C_SYS_CFG_TYPE_92C) { 1202251538Srpaulo sc->chip |= URTWN_CHIP_92C; 1203251538Srpaulo /* Check if it is a castrated 8192C. */ 1204251538Srpaulo if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1205251538Srpaulo R92C_HPON_FSM_CHIP_BONDING_ID) == 1206251538Srpaulo R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1207251538Srpaulo sc->chip |= URTWN_CHIP_92C_1T2R; 1208251538Srpaulo } 1209251538Srpaulo if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1210251538Srpaulo sc->chip |= URTWN_CHIP_UMC; 1211251538Srpaulo if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1212251538Srpaulo sc->chip |= URTWN_CHIP_UMC_A_CUT; 1213251538Srpaulo } 1214251538Srpaulo return (0); 1215251538Srpaulo} 1216251538Srpaulo 1217251538Srpaulostatic void 1218251538Srpaulourtwn_read_rom(struct urtwn_softc *sc) 1219251538Srpaulo{ 1220251538Srpaulo struct r92c_rom *rom = &sc->rom; 1221251538Srpaulo 1222251538Srpaulo /* Read full ROM image. */ 1223251538Srpaulo urtwn_efuse_read(sc); 1224251538Srpaulo 1225251538Srpaulo /* XXX Weird but this is what the vendor driver does. */ 1226251538Srpaulo sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1227251538Srpaulo DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1228251538Srpaulo 1229251538Srpaulo sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1230251538Srpaulo 1231251538Srpaulo sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1232251538Srpaulo DPRINTF("regulatory type=%d\n", sc->regulatory); 1233251538Srpaulo 1234251538Srpaulo IEEE80211_ADDR_COPY(sc->sc_bssid, rom->macaddr); 1235251538Srpaulo} 1236251538Srpaulo 1237251538Srpaulo/* 1238251538Srpaulo * Initialize rate adaptation in firmware. 1239251538Srpaulo */ 1240251538Srpaulostatic int 1241251538Srpaulourtwn_ra_init(struct urtwn_softc *sc) 1242251538Srpaulo{ 1243251538Srpaulo static const uint8_t map[] = 1244251538Srpaulo { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 }; 1245251538Srpaulo struct ieee80211com *ic = sc->sc_ifp->if_l2com; 1246251538Srpaulo struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1247251538Srpaulo struct ieee80211_node *ni; 1248251538Srpaulo struct ieee80211_rateset *rs; 1249251538Srpaulo struct r92c_fw_cmd_macid_cfg cmd; 1250251538Srpaulo uint32_t rates, basicrates; 1251251538Srpaulo uint8_t mode; 1252251538Srpaulo int maxrate, maxbasicrate, error, i, j; 1253251538Srpaulo 1254251538Srpaulo ni = ieee80211_ref_node(vap->iv_bss); 1255251538Srpaulo rs = &ni->ni_rates; 1256251538Srpaulo 1257251538Srpaulo /* Get normal and basic rates mask. */ 1258251538Srpaulo rates = basicrates = 0; 1259251538Srpaulo maxrate = maxbasicrate = 0; 1260251538Srpaulo for (i = 0; i < rs->rs_nrates; i++) { 1261251538Srpaulo /* Convert 802.11 rate to HW rate index. */ 1262251538Srpaulo for (j = 0; j < nitems(map); j++) 1263251538Srpaulo if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 1264251538Srpaulo break; 1265251538Srpaulo if (j == nitems(map)) /* Unknown rate, skip. */ 1266251538Srpaulo continue; 1267251538Srpaulo rates |= 1 << j; 1268251538Srpaulo if (j > maxrate) 1269251538Srpaulo maxrate = j; 1270251538Srpaulo if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1271251538Srpaulo basicrates |= 1 << j; 1272251538Srpaulo if (j > maxbasicrate) 1273251538Srpaulo maxbasicrate = j; 1274251538Srpaulo } 1275251538Srpaulo } 1276251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1277251538Srpaulo mode = R92C_RAID_11B; 1278251538Srpaulo else 1279251538Srpaulo mode = R92C_RAID_11BG; 1280251538Srpaulo DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1281251538Srpaulo mode, rates, basicrates); 1282251538Srpaulo 1283251538Srpaulo /* Set rates mask for group addressed frames. */ 1284251538Srpaulo cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1285251538Srpaulo cmd.mask = htole32(mode << 28 | basicrates); 1286251538Srpaulo error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1287251538Srpaulo if (error != 0) { 1288252401Srpaulo ieee80211_free_node(ni); 1289251538Srpaulo device_printf(sc->sc_dev, 1290251538Srpaulo "could not add broadcast station\n"); 1291251538Srpaulo return (error); 1292251538Srpaulo } 1293251538Srpaulo /* Set initial MRR rate. */ 1294251538Srpaulo DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1295251538Srpaulo urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1296251538Srpaulo maxbasicrate); 1297251538Srpaulo 1298251538Srpaulo /* Set rates mask for unicast frames. */ 1299251538Srpaulo cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1300251538Srpaulo cmd.mask = htole32(mode << 28 | rates); 1301251538Srpaulo error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1302251538Srpaulo if (error != 0) { 1303252401Srpaulo ieee80211_free_node(ni); 1304251538Srpaulo device_printf(sc->sc_dev, "could not add BSS station\n"); 1305251538Srpaulo return (error); 1306251538Srpaulo } 1307251538Srpaulo /* Set initial MRR rate. */ 1308251538Srpaulo DPRINTF("maxrate=%d\n", maxrate); 1309251538Srpaulo urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1310251538Srpaulo maxrate); 1311251538Srpaulo 1312251538Srpaulo /* Indicate highest supported rate. */ 1313252403Srpaulo ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1314252401Srpaulo ieee80211_free_node(ni); 1315252401Srpaulo 1316251538Srpaulo return (0); 1317251538Srpaulo} 1318251538Srpaulo 1319251538Srpaulovoid 1320251538Srpaulourtwn_tsf_sync_enable(struct urtwn_softc *sc) 1321251538Srpaulo{ 1322251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 1323251538Srpaulo struct ieee80211com *ic = ifp->if_l2com; 1324251538Srpaulo struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1325251538Srpaulo struct ieee80211_node *ni = vap->iv_bss; 1326251538Srpaulo 1327251538Srpaulo uint64_t tsf; 1328251538Srpaulo 1329251538Srpaulo /* Enable TSF synchronization. */ 1330251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1331251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1332251538Srpaulo 1333251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1334251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1335251538Srpaulo 1336251538Srpaulo /* Set initial TSF. */ 1337251538Srpaulo memcpy(&tsf, ni->ni_tstamp.data, 8); 1338251538Srpaulo tsf = le64toh(tsf); 1339251538Srpaulo tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU)); 1340251538Srpaulo tsf -= IEEE80211_DUR_TU; 1341251538Srpaulo urtwn_write_4(sc, R92C_TSFTR + 0, tsf); 1342251538Srpaulo urtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32); 1343251538Srpaulo 1344251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1345251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1346251538Srpaulo} 1347251538Srpaulo 1348251538Srpaulostatic void 1349251538Srpaulourtwn_set_led(struct urtwn_softc *sc, int led, int on) 1350251538Srpaulo{ 1351251538Srpaulo uint8_t reg; 1352251538Srpaulo 1353251538Srpaulo if (led == URTWN_LED_LINK) { 1354251538Srpaulo reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1355251538Srpaulo if (!on) 1356251538Srpaulo reg |= R92C_LEDCFG0_DIS; 1357251538Srpaulo urtwn_write_1(sc, R92C_LEDCFG0, reg); 1358251538Srpaulo sc->ledlink = on; /* Save LED state. */ 1359251538Srpaulo } 1360251538Srpaulo} 1361251538Srpaulo 1362251538Srpaulostatic int 1363251538Srpaulourtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1364251538Srpaulo{ 1365251538Srpaulo struct urtwn_vap *uvp = URTWN_VAP(vap); 1366251538Srpaulo struct ieee80211com *ic = vap->iv_ic; 1367251538Srpaulo struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1368251538Srpaulo struct ieee80211_node *ni; 1369251538Srpaulo enum ieee80211_state ostate; 1370251538Srpaulo uint32_t reg; 1371251538Srpaulo 1372251538Srpaulo ostate = vap->iv_state; 1373251538Srpaulo DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 1374251538Srpaulo ieee80211_state_name[nstate]); 1375251538Srpaulo 1376251538Srpaulo IEEE80211_UNLOCK(ic); 1377251538Srpaulo URTWN_LOCK(sc); 1378251538Srpaulo callout_stop(&sc->sc_watchdog_ch); 1379251538Srpaulo 1380251538Srpaulo if (ostate == IEEE80211_S_RUN) { 1381251538Srpaulo /* Turn link LED off. */ 1382251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 0); 1383251538Srpaulo 1384251538Srpaulo /* Set media status to 'No Link'. */ 1385251538Srpaulo reg = urtwn_read_4(sc, R92C_CR); 1386251538Srpaulo reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK); 1387251538Srpaulo urtwn_write_4(sc, R92C_CR, reg); 1388251538Srpaulo 1389251538Srpaulo /* Stop Rx of data frames. */ 1390251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1391251538Srpaulo 1392251538Srpaulo /* Rest TSF. */ 1393251538Srpaulo urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1394251538Srpaulo 1395251538Srpaulo /* Disable TSF synchronization. */ 1396251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1397251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) | 1398251538Srpaulo R92C_BCN_CTRL_DIS_TSF_UDT0); 1399251538Srpaulo 1400251538Srpaulo /* Reset EDCA parameters. */ 1401251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1402251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1403251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1404251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1405251538Srpaulo } 1406251538Srpaulo 1407251538Srpaulo switch (nstate) { 1408251538Srpaulo case IEEE80211_S_INIT: 1409251538Srpaulo /* Turn link LED off. */ 1410251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 0); 1411251538Srpaulo break; 1412251538Srpaulo case IEEE80211_S_SCAN: 1413251538Srpaulo if (ostate != IEEE80211_S_SCAN) { 1414251538Srpaulo /* Allow Rx from any BSSID. */ 1415251538Srpaulo urtwn_write_4(sc, R92C_RCR, 1416251538Srpaulo urtwn_read_4(sc, R92C_RCR) & 1417251538Srpaulo ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1418251538Srpaulo 1419251538Srpaulo /* Set gain for scanning. */ 1420251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1421251538Srpaulo reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1422251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1423251538Srpaulo 1424251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1425251538Srpaulo reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1426251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1427251538Srpaulo } 1428251538Srpaulo 1429251538Srpaulo /* Make link LED blink during scan. */ 1430251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 1431251538Srpaulo 1432251538Srpaulo /* Pause AC Tx queues. */ 1433251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 1434251538Srpaulo urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1435251538Srpaulo 1436251538Srpaulo urtwn_set_chan(sc, ic->ic_curchan, NULL); 1437251538Srpaulo break; 1438251538Srpaulo case IEEE80211_S_AUTH: 1439251538Srpaulo /* Set initial gain under link. */ 1440251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1441251538Srpaulo reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1442251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1443251538Srpaulo 1444251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1445251538Srpaulo reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1446251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1447251538Srpaulo 1448251538Srpaulo urtwn_set_chan(sc, ic->ic_curchan, NULL); 1449251538Srpaulo break; 1450251538Srpaulo case IEEE80211_S_RUN: 1451251538Srpaulo if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1452251538Srpaulo /* Enable Rx of data frames. */ 1453251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1454251538Srpaulo 1455251538Srpaulo /* Turn link LED on. */ 1456251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 1); 1457251538Srpaulo break; 1458251538Srpaulo } 1459251538Srpaulo 1460251538Srpaulo ni = ieee80211_ref_node(vap->iv_bss); 1461251538Srpaulo /* Set media status to 'Associated'. */ 1462251538Srpaulo reg = urtwn_read_4(sc, R92C_CR); 1463251538Srpaulo reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 1464251538Srpaulo urtwn_write_4(sc, R92C_CR, reg); 1465251538Srpaulo 1466251538Srpaulo /* Set BSSID. */ 1467251538Srpaulo urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1468251538Srpaulo urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1469251538Srpaulo 1470251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1471251538Srpaulo urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1472251538Srpaulo else /* 802.11b/g */ 1473251538Srpaulo urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1474251538Srpaulo 1475251538Srpaulo /* Enable Rx of data frames. */ 1476251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1477251538Srpaulo 1478251538Srpaulo /* Flush all AC queues. */ 1479251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0); 1480251538Srpaulo 1481251538Srpaulo /* Set beacon interval. */ 1482251538Srpaulo urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1483251538Srpaulo 1484251538Srpaulo /* Allow Rx from our BSSID only. */ 1485251538Srpaulo urtwn_write_4(sc, R92C_RCR, 1486251538Srpaulo urtwn_read_4(sc, R92C_RCR) | 1487251538Srpaulo R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1488251538Srpaulo 1489251538Srpaulo /* Enable TSF synchronization. */ 1490251538Srpaulo urtwn_tsf_sync_enable(sc); 1491251538Srpaulo 1492251538Srpaulo urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1493251538Srpaulo urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1494251538Srpaulo urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1495251538Srpaulo urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1496251538Srpaulo urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1497251538Srpaulo urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1498251538Srpaulo 1499251538Srpaulo /* Intialize rate adaptation. */ 1500251538Srpaulo urtwn_ra_init(sc); 1501251538Srpaulo /* Turn link LED on. */ 1502251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 1); 1503251538Srpaulo 1504251538Srpaulo sc->avg_pwdb = -1; /* Reset average RSSI. */ 1505251538Srpaulo /* Reset temperature calibration state machine. */ 1506251538Srpaulo sc->thcal_state = 0; 1507251538Srpaulo sc->thcal_lctemp = 0; 1508251538Srpaulo ieee80211_free_node(ni); 1509251538Srpaulo break; 1510251538Srpaulo default: 1511251538Srpaulo break; 1512251538Srpaulo } 1513251538Srpaulo URTWN_UNLOCK(sc); 1514251538Srpaulo IEEE80211_LOCK(ic); 1515251538Srpaulo return(uvp->newstate(vap, nstate, arg)); 1516251538Srpaulo} 1517251538Srpaulo 1518251538Srpaulostatic void 1519251538Srpaulourtwn_watchdog(void *arg) 1520251538Srpaulo{ 1521251538Srpaulo struct urtwn_softc *sc = arg; 1522251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 1523251538Srpaulo 1524251538Srpaulo if (sc->sc_txtimer > 0) { 1525251538Srpaulo if (--sc->sc_txtimer == 0) { 1526251538Srpaulo device_printf(sc->sc_dev, "device timeout\n"); 1527251538Srpaulo ifp->if_oerrors++; 1528251538Srpaulo return; 1529251538Srpaulo } 1530251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1531251538Srpaulo } 1532251538Srpaulo} 1533251538Srpaulo 1534251538Srpaulostatic void 1535251538Srpaulourtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1536251538Srpaulo{ 1537251538Srpaulo int pwdb; 1538251538Srpaulo 1539251538Srpaulo /* Convert antenna signal to percentage. */ 1540251538Srpaulo if (rssi <= -100 || rssi >= 20) 1541251538Srpaulo pwdb = 0; 1542251538Srpaulo else if (rssi >= 0) 1543251538Srpaulo pwdb = 100; 1544251538Srpaulo else 1545251538Srpaulo pwdb = 100 + rssi; 1546251538Srpaulo if (rate <= 3) { 1547251538Srpaulo /* CCK gain is smaller than OFDM/MCS gain. */ 1548251538Srpaulo pwdb += 6; 1549251538Srpaulo if (pwdb > 100) 1550251538Srpaulo pwdb = 100; 1551251538Srpaulo if (pwdb <= 14) 1552251538Srpaulo pwdb -= 4; 1553251538Srpaulo else if (pwdb <= 26) 1554251538Srpaulo pwdb -= 8; 1555251538Srpaulo else if (pwdb <= 34) 1556251538Srpaulo pwdb -= 6; 1557251538Srpaulo else if (pwdb <= 42) 1558251538Srpaulo pwdb -= 2; 1559251538Srpaulo } 1560251538Srpaulo if (sc->avg_pwdb == -1) /* Init. */ 1561251538Srpaulo sc->avg_pwdb = pwdb; 1562251538Srpaulo else if (sc->avg_pwdb < pwdb) 1563251538Srpaulo sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1564251538Srpaulo else 1565251538Srpaulo sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1566251538Srpaulo DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 1567251538Srpaulo} 1568251538Srpaulo 1569251538Srpaulostatic int8_t 1570251538Srpaulourtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1571251538Srpaulo{ 1572251538Srpaulo static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1573251538Srpaulo struct r92c_rx_phystat *phy; 1574251538Srpaulo struct r92c_rx_cck *cck; 1575251538Srpaulo uint8_t rpt; 1576251538Srpaulo int8_t rssi; 1577251538Srpaulo 1578251538Srpaulo if (rate <= 3) { 1579251538Srpaulo cck = (struct r92c_rx_cck *)physt; 1580251538Srpaulo if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 1581251538Srpaulo rpt = (cck->agc_rpt >> 5) & 0x3; 1582251538Srpaulo rssi = (cck->agc_rpt & 0x1f) << 1; 1583251538Srpaulo } else { 1584251538Srpaulo rpt = (cck->agc_rpt >> 6) & 0x3; 1585251538Srpaulo rssi = cck->agc_rpt & 0x3e; 1586251538Srpaulo } 1587251538Srpaulo rssi = cckoff[rpt] - rssi; 1588251538Srpaulo } else { /* OFDM/HT. */ 1589251538Srpaulo phy = (struct r92c_rx_phystat *)physt; 1590251538Srpaulo rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1591251538Srpaulo } 1592251538Srpaulo return (rssi); 1593251538Srpaulo} 1594251538Srpaulo 1595251538Srpaulostatic int 1596251538Srpaulourtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni, 1597251538Srpaulo struct mbuf *m0, struct urtwn_data *data) 1598251538Srpaulo{ 1599251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 1600251538Srpaulo struct ieee80211_frame *wh; 1601251538Srpaulo struct ieee80211_key *k; 1602251538Srpaulo struct ieee80211com *ic = ifp->if_l2com; 1603251538Srpaulo struct ieee80211vap *vap = ni->ni_vap; 1604251538Srpaulo struct usb_xfer *xfer; 1605251538Srpaulo struct r92c_tx_desc *txd; 1606251538Srpaulo uint8_t raid, type; 1607251538Srpaulo uint16_t sum; 1608251538Srpaulo int i, hasqos, xferlen; 1609251538Srpaulo struct usb_xfer *urtwn_pipes[4] = { 1610251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_BE], 1611251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_BK], 1612251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_VI], 1613251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_VO] 1614251538Srpaulo }; 1615251538Srpaulo 1616251538Srpaulo URTWN_ASSERT_LOCKED(sc); 1617251538Srpaulo 1618251538Srpaulo /* 1619251538Srpaulo * Software crypto. 1620251538Srpaulo */ 1621251538Srpaulo wh = mtod(m0, struct ieee80211_frame *); 1622260444Skevlo if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1623251538Srpaulo k = ieee80211_crypto_encap(ni, m0); 1624251538Srpaulo if (k == NULL) { 1625251538Srpaulo device_printf(sc->sc_dev, 1626251538Srpaulo "ieee80211_crypto_encap returns NULL.\n"); 1627251538Srpaulo /* XXX we don't expect the fragmented frames */ 1628251538Srpaulo m_freem(m0); 1629251538Srpaulo return (ENOBUFS); 1630251538Srpaulo } 1631251538Srpaulo 1632251538Srpaulo /* in case packet header moved, reset pointer */ 1633251538Srpaulo wh = mtod(m0, struct ieee80211_frame *); 1634251538Srpaulo } 1635251538Srpaulo 1636251538Srpaulo switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 1637251538Srpaulo case IEEE80211_FC0_TYPE_CTL: 1638251538Srpaulo case IEEE80211_FC0_TYPE_MGT: 1639251538Srpaulo xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 1640251538Srpaulo break; 1641251538Srpaulo default: 1642251538Srpaulo KASSERT(M_WME_GETAC(m0) < 4, 1643251538Srpaulo ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1644251538Srpaulo xfer = urtwn_pipes[M_WME_GETAC(m0)]; 1645251538Srpaulo break; 1646251538Srpaulo } 1647251538Srpaulo 1648251538Srpaulo hasqos = 0; 1649251538Srpaulo 1650251538Srpaulo /* Fill Tx descriptor. */ 1651251538Srpaulo txd = (struct r92c_tx_desc *)data->buf; 1652251538Srpaulo memset(txd, 0, sizeof(*txd)); 1653251538Srpaulo 1654251538Srpaulo txd->txdw0 |= htole32( 1655251538Srpaulo SM(R92C_TXDW0_PKTLEN, m0->m_pkthdr.len) | 1656251538Srpaulo SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1657251538Srpaulo R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1658251538Srpaulo if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1659251538Srpaulo txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1660251538Srpaulo 1661251538Srpaulo type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1662251538Srpaulo if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1663251538Srpaulo type == IEEE80211_FC0_TYPE_DATA) { 1664251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1665251538Srpaulo raid = R92C_RAID_11B; 1666251538Srpaulo else 1667251538Srpaulo raid = R92C_RAID_11BG; 1668251538Srpaulo txd->txdw1 |= htole32( 1669251538Srpaulo SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 1670251538Srpaulo SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1671251538Srpaulo SM(R92C_TXDW1_RAID, raid) | 1672251538Srpaulo R92C_TXDW1_AGGBK); 1673251538Srpaulo 1674251538Srpaulo if (ic->ic_flags & IEEE80211_F_USEPROT) { 1675251538Srpaulo if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1676251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1677251538Srpaulo R92C_TXDW4_HWRTSEN); 1678251538Srpaulo } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1679251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1680251538Srpaulo R92C_TXDW4_HWRTSEN); 1681251538Srpaulo } 1682251538Srpaulo } 1683251538Srpaulo /* Send RTS at OFDM24. */ 1684251538Srpaulo txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1685251538Srpaulo txd->txdw5 |= htole32(0x0001ff00); 1686251538Srpaulo /* Send data at OFDM54. */ 1687251538Srpaulo txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1688251538Srpaulo } else { 1689251538Srpaulo txd->txdw1 |= htole32( 1690251538Srpaulo SM(R92C_TXDW1_MACID, 0) | 1691251538Srpaulo SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1692251538Srpaulo SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1693251538Srpaulo 1694251538Srpaulo /* Force CCK1. */ 1695251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1696251538Srpaulo txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1697251538Srpaulo } 1698251538Srpaulo /* Set sequence number (already little endian). */ 1699251538Srpaulo txd->txdseq |= *(uint16_t *)wh->i_seq; 1700251538Srpaulo 1701251538Srpaulo if (!hasqos) { 1702251538Srpaulo /* Use HW sequence numbering for non-QoS frames. */ 1703251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1704251538Srpaulo txd->txdseq |= htole16(0x8000); 1705251538Srpaulo } else 1706251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1707251538Srpaulo 1708251538Srpaulo /* Compute Tx descriptor checksum. */ 1709251538Srpaulo sum = 0; 1710251538Srpaulo for (i = 0; i < sizeof(*txd) / 2; i++) 1711251538Srpaulo sum ^= ((uint16_t *)txd)[i]; 1712251538Srpaulo txd->txdsum = sum; /* NB: already little endian. */ 1713251538Srpaulo 1714251538Srpaulo if (ieee80211_radiotap_active_vap(vap)) { 1715251538Srpaulo struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1716251538Srpaulo 1717251538Srpaulo tap->wt_flags = 0; 1718251538Srpaulo tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1719251538Srpaulo tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1720251538Srpaulo ieee80211_radiotap_tx(vap, m0); 1721251538Srpaulo } 1722251538Srpaulo 1723251538Srpaulo xferlen = sizeof(*txd) + m0->m_pkthdr.len; 1724251538Srpaulo m_copydata(m0, 0, m0->m_pkthdr.len, (caddr_t)&txd[1]); 1725251538Srpaulo 1726251538Srpaulo data->buflen = xferlen; 1727251538Srpaulo data->ni = ni; 1728251538Srpaulo data->m = m0; 1729251538Srpaulo 1730251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1731251538Srpaulo usbd_transfer_start(xfer); 1732251538Srpaulo return (0); 1733251538Srpaulo} 1734251538Srpaulo 1735251538Srpaulostatic void 1736251538Srpaulourtwn_start(struct ifnet *ifp) 1737251538Srpaulo{ 1738251538Srpaulo struct urtwn_softc *sc = ifp->if_softc; 1739261863Srpaulo 1740261863Srpaulo if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1741261863Srpaulo return; 1742261863Srpaulo URTWN_LOCK(sc); 1743261863Srpaulo urtwn_start_locked(ifp, sc); 1744261863Srpaulo URTWN_UNLOCK(sc); 1745261863Srpaulo} 1746261863Srpaulo 1747261863Srpaulostatic void 1748261863Srpaulourtwn_start_locked(struct ifnet *ifp, struct urtwn_softc *sc) 1749261863Srpaulo{ 1750251538Srpaulo struct ieee80211_node *ni; 1751251538Srpaulo struct mbuf *m; 1752251538Srpaulo struct urtwn_data *bf; 1753251538Srpaulo 1754261863Srpaulo URTWN_ASSERT_LOCKED(sc); 1755251538Srpaulo for (;;) { 1756251538Srpaulo IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1757251538Srpaulo if (m == NULL) 1758251538Srpaulo break; 1759251538Srpaulo bf = urtwn_getbuf(sc); 1760251538Srpaulo if (bf == NULL) { 1761251538Srpaulo IFQ_DRV_PREPEND(&ifp->if_snd, m); 1762251538Srpaulo break; 1763251538Srpaulo } 1764251538Srpaulo ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1765251538Srpaulo m->m_pkthdr.rcvif = NULL; 1766251538Srpaulo 1767251538Srpaulo if (urtwn_tx_start(sc, ni, m, bf) != 0) { 1768251538Srpaulo ifp->if_oerrors++; 1769251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1770251538Srpaulo ieee80211_free_node(ni); 1771251538Srpaulo break; 1772251538Srpaulo } 1773251538Srpaulo 1774251538Srpaulo sc->sc_txtimer = 5; 1775251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1776251538Srpaulo } 1777251538Srpaulo} 1778251538Srpaulo 1779251538Srpaulostatic int 1780251538Srpaulourtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1781251538Srpaulo{ 1782263153Skevlo struct urtwn_softc *sc = ifp->if_softc; 1783251538Srpaulo struct ieee80211com *ic = ifp->if_l2com; 1784251538Srpaulo struct ifreq *ifr = (struct ifreq *) data; 1785251538Srpaulo int error = 0, startall = 0; 1786251538Srpaulo 1787263153Skevlo URTWN_LOCK(sc); 1788263153Skevlo error = (sc->sc_flags & URTWN_DETACHED) ? ENXIO : 0; 1789263153Skevlo URTWN_UNLOCK(sc); 1790263153Skevlo if (error != 0) 1791263153Skevlo return (error); 1792263153Skevlo 1793251538Srpaulo switch (cmd) { 1794251538Srpaulo case SIOCSIFFLAGS: 1795251538Srpaulo if (ifp->if_flags & IFF_UP) { 1796251538Srpaulo if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1797251538Srpaulo urtwn_init(ifp->if_softc); 1798251538Srpaulo startall = 1; 1799251538Srpaulo } 1800251538Srpaulo } else { 1801251538Srpaulo if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1802263153Skevlo urtwn_stop(ifp); 1803251538Srpaulo } 1804251538Srpaulo if (startall) 1805251538Srpaulo ieee80211_start_all(ic); 1806251538Srpaulo break; 1807251538Srpaulo case SIOCGIFMEDIA: 1808251538Srpaulo error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1809251538Srpaulo break; 1810251538Srpaulo case SIOCGIFADDR: 1811251538Srpaulo error = ether_ioctl(ifp, cmd, data); 1812251538Srpaulo break; 1813251538Srpaulo default: 1814251538Srpaulo error = EINVAL; 1815251538Srpaulo break; 1816251538Srpaulo } 1817251538Srpaulo return (error); 1818251538Srpaulo} 1819251538Srpaulo 1820251538Srpaulostatic int 1821251538Srpaulourtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 1822251538Srpaulo int ndata, int maxsz) 1823251538Srpaulo{ 1824251538Srpaulo int i, error; 1825251538Srpaulo 1826251538Srpaulo for (i = 0; i < ndata; i++) { 1827251538Srpaulo struct urtwn_data *dp = &data[i]; 1828251538Srpaulo dp->sc = sc; 1829251538Srpaulo dp->m = NULL; 1830251538Srpaulo dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 1831251538Srpaulo if (dp->buf == NULL) { 1832251538Srpaulo device_printf(sc->sc_dev, 1833251538Srpaulo "could not allocate buffer\n"); 1834251538Srpaulo error = ENOMEM; 1835251538Srpaulo goto fail; 1836251538Srpaulo } 1837251538Srpaulo dp->ni = NULL; 1838251538Srpaulo } 1839251538Srpaulo 1840251538Srpaulo return (0); 1841251538Srpaulofail: 1842251538Srpaulo urtwn_free_list(sc, data, ndata); 1843251538Srpaulo return (error); 1844251538Srpaulo} 1845251538Srpaulo 1846251538Srpaulostatic int 1847251538Srpaulourtwn_alloc_rx_list(struct urtwn_softc *sc) 1848251538Srpaulo{ 1849251538Srpaulo int error, i; 1850251538Srpaulo 1851251538Srpaulo error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 1852251538Srpaulo URTWN_RXBUFSZ); 1853251538Srpaulo if (error != 0) 1854251538Srpaulo return (error); 1855251538Srpaulo 1856251538Srpaulo STAILQ_INIT(&sc->sc_rx_active); 1857251538Srpaulo STAILQ_INIT(&sc->sc_rx_inactive); 1858251538Srpaulo 1859251538Srpaulo for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 1860251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1861251538Srpaulo 1862251538Srpaulo return (0); 1863251538Srpaulo} 1864251538Srpaulo 1865251538Srpaulostatic int 1866251538Srpaulourtwn_alloc_tx_list(struct urtwn_softc *sc) 1867251538Srpaulo{ 1868251538Srpaulo int error, i; 1869251538Srpaulo 1870251538Srpaulo error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 1871251538Srpaulo URTWN_TXBUFSZ); 1872251538Srpaulo if (error != 0) 1873251538Srpaulo return (error); 1874251538Srpaulo 1875251538Srpaulo STAILQ_INIT(&sc->sc_tx_active); 1876251538Srpaulo STAILQ_INIT(&sc->sc_tx_inactive); 1877251538Srpaulo STAILQ_INIT(&sc->sc_tx_pending); 1878251538Srpaulo 1879251538Srpaulo for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 1880251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 1881251538Srpaulo 1882251538Srpaulo return (0); 1883251538Srpaulo} 1884251538Srpaulo 1885251538Srpaulostatic int 1886251538Srpaulourtwn_power_on(struct urtwn_softc *sc) 1887251538Srpaulo{ 1888251538Srpaulo uint32_t reg; 1889251538Srpaulo int ntries; 1890251538Srpaulo 1891251538Srpaulo /* Wait for autoload done bit. */ 1892251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 1893251538Srpaulo if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 1894251538Srpaulo break; 1895251538Srpaulo DELAY(5); 1896251538Srpaulo } 1897251538Srpaulo if (ntries == 1000) { 1898251538Srpaulo device_printf(sc->sc_dev, 1899251538Srpaulo "timeout waiting for chip autoload\n"); 1900251538Srpaulo return (ETIMEDOUT); 1901251538Srpaulo } 1902251538Srpaulo 1903251538Srpaulo /* Unlock ISO/CLK/Power control register. */ 1904251538Srpaulo urtwn_write_1(sc, R92C_RSV_CTRL, 0); 1905251538Srpaulo /* Move SPS into PWM mode. */ 1906251538Srpaulo urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 1907251538Srpaulo DELAY(100); 1908251538Srpaulo 1909251538Srpaulo reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 1910251538Srpaulo if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 1911251538Srpaulo urtwn_write_1(sc, R92C_LDOV12D_CTRL, 1912251538Srpaulo reg | R92C_LDOV12D_CTRL_LDV12_EN); 1913251538Srpaulo DELAY(100); 1914251538Srpaulo urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 1915251538Srpaulo urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 1916251538Srpaulo ~R92C_SYS_ISO_CTRL_MD2PP); 1917251538Srpaulo } 1918251538Srpaulo 1919251538Srpaulo /* Auto enable WLAN. */ 1920251538Srpaulo urtwn_write_2(sc, R92C_APS_FSMCO, 1921251538Srpaulo urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1922251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 1923262822Skevlo if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1924262822Skevlo R92C_APS_FSMCO_APFM_ONMAC)) 1925251538Srpaulo break; 1926251538Srpaulo DELAY(5); 1927251538Srpaulo } 1928251538Srpaulo if (ntries == 1000) { 1929251538Srpaulo device_printf(sc->sc_dev, 1930251538Srpaulo "timeout waiting for MAC auto ON\n"); 1931251538Srpaulo return (ETIMEDOUT); 1932251538Srpaulo } 1933251538Srpaulo 1934251538Srpaulo /* Enable radio, GPIO and LED functions. */ 1935251538Srpaulo urtwn_write_2(sc, R92C_APS_FSMCO, 1936251538Srpaulo R92C_APS_FSMCO_AFSM_HSUS | 1937251538Srpaulo R92C_APS_FSMCO_PDN_EN | 1938251538Srpaulo R92C_APS_FSMCO_PFM_ALDN); 1939251538Srpaulo /* Release RF digital isolation. */ 1940251538Srpaulo urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1941251538Srpaulo urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 1942251538Srpaulo 1943251538Srpaulo /* Initialize MAC. */ 1944251538Srpaulo urtwn_write_1(sc, R92C_APSD_CTRL, 1945251538Srpaulo urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 1946251538Srpaulo for (ntries = 0; ntries < 200; ntries++) { 1947251538Srpaulo if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 1948251538Srpaulo R92C_APSD_CTRL_OFF_STATUS)) 1949251538Srpaulo break; 1950251538Srpaulo DELAY(5); 1951251538Srpaulo } 1952251538Srpaulo if (ntries == 200) { 1953251538Srpaulo device_printf(sc->sc_dev, 1954251538Srpaulo "timeout waiting for MAC initialization\n"); 1955251538Srpaulo return (ETIMEDOUT); 1956251538Srpaulo } 1957251538Srpaulo 1958251538Srpaulo /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1959251538Srpaulo reg = urtwn_read_2(sc, R92C_CR); 1960251538Srpaulo reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1961251538Srpaulo R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1962251538Srpaulo R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 1963251538Srpaulo R92C_CR_ENSEC; 1964251538Srpaulo urtwn_write_2(sc, R92C_CR, reg); 1965251538Srpaulo 1966251538Srpaulo urtwn_write_1(sc, 0xfe10, 0x19); 1967251538Srpaulo return (0); 1968251538Srpaulo} 1969251538Srpaulo 1970251538Srpaulostatic int 1971251538Srpaulourtwn_llt_init(struct urtwn_softc *sc) 1972251538Srpaulo{ 1973251538Srpaulo int i, error; 1974251538Srpaulo 1975251538Srpaulo /* Reserve pages [0; R92C_TX_PAGE_COUNT]. */ 1976251538Srpaulo for (i = 0; i < R92C_TX_PAGE_COUNT; i++) { 1977251538Srpaulo if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 1978251538Srpaulo return (error); 1979251538Srpaulo } 1980251538Srpaulo /* NB: 0xff indicates end-of-list. */ 1981251538Srpaulo if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 1982251538Srpaulo return (error); 1983251538Srpaulo /* 1984251538Srpaulo * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1] 1985251538Srpaulo * as ring buffer. 1986251538Srpaulo */ 1987251538Srpaulo for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) { 1988251538Srpaulo if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 1989251538Srpaulo return (error); 1990251538Srpaulo } 1991251538Srpaulo /* Make the last page point to the beginning of the ring buffer. */ 1992251538Srpaulo error = urtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1); 1993251538Srpaulo return (error); 1994251538Srpaulo} 1995251538Srpaulo 1996251538Srpaulostatic void 1997251538Srpaulourtwn_fw_reset(struct urtwn_softc *sc) 1998251538Srpaulo{ 1999251538Srpaulo uint16_t reg; 2000251538Srpaulo int ntries; 2001251538Srpaulo 2002251538Srpaulo /* Tell 8051 to reset itself. */ 2003251538Srpaulo urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2004251538Srpaulo 2005251538Srpaulo /* Wait until 8051 resets by itself. */ 2006251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 2007251538Srpaulo reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2008251538Srpaulo if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2009251538Srpaulo return; 2010251538Srpaulo DELAY(50); 2011251538Srpaulo } 2012251538Srpaulo /* Force 8051 reset. */ 2013251538Srpaulo urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2014251538Srpaulo} 2015251538Srpaulo 2016251538Srpaulostatic int 2017251538Srpaulourtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 2018251538Srpaulo{ 2019251538Srpaulo uint32_t reg; 2020251538Srpaulo int off, mlen, error = 0; 2021251538Srpaulo 2022251538Srpaulo reg = urtwn_read_4(sc, R92C_MCUFWDL); 2023251538Srpaulo reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2024251538Srpaulo urtwn_write_4(sc, R92C_MCUFWDL, reg); 2025251538Srpaulo 2026251538Srpaulo off = R92C_FW_START_ADDR; 2027251538Srpaulo while (len > 0) { 2028251538Srpaulo if (len > 196) 2029251538Srpaulo mlen = 196; 2030251538Srpaulo else if (len > 4) 2031251538Srpaulo mlen = 4; 2032251538Srpaulo else 2033251538Srpaulo mlen = 1; 2034251538Srpaulo /* XXX fix this deconst */ 2035251538Srpaulo error = urtwn_write_region_1(sc, off, 2036251538Srpaulo __DECONST(uint8_t *, buf), mlen); 2037251538Srpaulo if (error != 0) 2038251538Srpaulo break; 2039251538Srpaulo off += mlen; 2040251538Srpaulo buf += mlen; 2041251538Srpaulo len -= mlen; 2042251538Srpaulo } 2043251538Srpaulo return (error); 2044251538Srpaulo} 2045251538Srpaulo 2046251538Srpaulostatic int 2047251538Srpaulourtwn_load_firmware(struct urtwn_softc *sc) 2048251538Srpaulo{ 2049251538Srpaulo const struct firmware *fw; 2050251538Srpaulo const struct r92c_fw_hdr *hdr; 2051251538Srpaulo const char *imagename; 2052251538Srpaulo const u_char *ptr; 2053251538Srpaulo size_t len; 2054251538Srpaulo uint32_t reg; 2055251538Srpaulo int mlen, ntries, page, error; 2056251538Srpaulo 2057264864Skevlo URTWN_UNLOCK(sc); 2058251538Srpaulo /* Read firmware image from the filesystem. */ 2059251538Srpaulo if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2060251538Srpaulo URTWN_CHIP_UMC_A_CUT) 2061251538Srpaulo imagename = "urtwn-rtl8192cfwU"; 2062251538Srpaulo else 2063251538Srpaulo imagename = "urtwn-rtl8192cfwT"; 2064251538Srpaulo 2065251538Srpaulo fw = firmware_get(imagename); 2066264864Skevlo URTWN_LOCK(sc); 2067251538Srpaulo if (fw == NULL) { 2068251538Srpaulo device_printf(sc->sc_dev, 2069251538Srpaulo "failed loadfirmware of file %s\n", imagename); 2070251538Srpaulo return (ENOENT); 2071251538Srpaulo } 2072251538Srpaulo 2073251538Srpaulo len = fw->datasize; 2074251538Srpaulo 2075251538Srpaulo if (len < sizeof(*hdr)) { 2076251538Srpaulo device_printf(sc->sc_dev, "firmware too short\n"); 2077251538Srpaulo error = EINVAL; 2078251538Srpaulo goto fail; 2079251538Srpaulo } 2080251538Srpaulo ptr = fw->data; 2081251538Srpaulo hdr = (const struct r92c_fw_hdr *)ptr; 2082251538Srpaulo /* Check if there is a valid FW header and skip it. */ 2083251538Srpaulo if ((le16toh(hdr->signature) >> 4) == 0x88c || 2084251538Srpaulo (le16toh(hdr->signature) >> 4) == 0x92c) { 2085251538Srpaulo DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 2086251538Srpaulo le16toh(hdr->version), le16toh(hdr->subversion), 2087251538Srpaulo hdr->month, hdr->date, hdr->hour, hdr->minute); 2088251538Srpaulo ptr += sizeof(*hdr); 2089251538Srpaulo len -= sizeof(*hdr); 2090251538Srpaulo } 2091251538Srpaulo 2092251538Srpaulo if (urtwn_read_1(sc, R92C_MCUFWDL) & 0x80) { 2093251538Srpaulo urtwn_fw_reset(sc); 2094251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 0); 2095251538Srpaulo } 2096251538Srpaulo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2097251538Srpaulo urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2098251538Srpaulo R92C_SYS_FUNC_EN_CPUEN); 2099251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 2100251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2101251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL + 2, 2102251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2103251538Srpaulo 2104263154Skevlo /* Reset the FWDL checksum. */ 2105263154Skevlo urtwn_write_1(sc, R92C_MCUFWDL, 2106263154Skevlo urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2107263154Skevlo 2108251538Srpaulo for (page = 0; len > 0; page++) { 2109251538Srpaulo mlen = min(len, R92C_FW_PAGE_SIZE); 2110251538Srpaulo error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2111251538Srpaulo if (error != 0) { 2112251538Srpaulo device_printf(sc->sc_dev, 2113251538Srpaulo "could not load firmware page\n"); 2114251538Srpaulo goto fail; 2115251538Srpaulo } 2116251538Srpaulo ptr += mlen; 2117251538Srpaulo len -= mlen; 2118251538Srpaulo } 2119251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 2120251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2121251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2122251538Srpaulo 2123251538Srpaulo /* Wait for checksum report. */ 2124251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2125251538Srpaulo if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2126251538Srpaulo break; 2127251538Srpaulo DELAY(5); 2128251538Srpaulo } 2129251538Srpaulo if (ntries == 1000) { 2130251538Srpaulo device_printf(sc->sc_dev, 2131251538Srpaulo "timeout waiting for checksum report\n"); 2132251538Srpaulo error = ETIMEDOUT; 2133251538Srpaulo goto fail; 2134251538Srpaulo } 2135251538Srpaulo 2136251538Srpaulo reg = urtwn_read_4(sc, R92C_MCUFWDL); 2137251538Srpaulo reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2138251538Srpaulo urtwn_write_4(sc, R92C_MCUFWDL, reg); 2139251538Srpaulo /* Wait for firmware readiness. */ 2140251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2141251538Srpaulo if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2142251538Srpaulo break; 2143251538Srpaulo DELAY(5); 2144251538Srpaulo } 2145251538Srpaulo if (ntries == 1000) { 2146251538Srpaulo device_printf(sc->sc_dev, 2147251538Srpaulo "timeout waiting for firmware readiness\n"); 2148251538Srpaulo error = ETIMEDOUT; 2149251538Srpaulo goto fail; 2150251538Srpaulo } 2151251538Srpaulofail: 2152251538Srpaulo firmware_put(fw, FIRMWARE_UNLOAD); 2153251538Srpaulo return (error); 2154251538Srpaulo} 2155251538Srpaulo 2156251538Srpaulostatic int 2157251538Srpaulourtwn_dma_init(struct urtwn_softc *sc) 2158251538Srpaulo{ 2159251538Srpaulo int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2160251538Srpaulo uint32_t reg; 2161251538Srpaulo int error; 2162251538Srpaulo 2163251538Srpaulo /* Initialize LLT table. */ 2164251538Srpaulo error = urtwn_llt_init(sc); 2165251538Srpaulo if (error != 0) 2166251538Srpaulo return (error); 2167251538Srpaulo 2168251538Srpaulo /* Get Tx queues to USB endpoints mapping. */ 2169251538Srpaulo hashq = hasnq = haslq = 0; 2170251538Srpaulo reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2171251538Srpaulo DPRINTFN(2, "USB endpoints mapping 0x%x\n", reg); 2172251538Srpaulo if (MS(reg, R92C_USB_EP_HQ) != 0) 2173251538Srpaulo hashq = 1; 2174251538Srpaulo if (MS(reg, R92C_USB_EP_NQ) != 0) 2175251538Srpaulo hasnq = 1; 2176251538Srpaulo if (MS(reg, R92C_USB_EP_LQ) != 0) 2177251538Srpaulo haslq = 1; 2178251538Srpaulo nqueues = hashq + hasnq + haslq; 2179251538Srpaulo if (nqueues == 0) 2180251538Srpaulo return (EIO); 2181251538Srpaulo /* Get the number of pages for each queue. */ 2182251538Srpaulo nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2183251538Srpaulo /* The remaining pages are assigned to the high priority queue. */ 2184251538Srpaulo nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2185251538Srpaulo 2186251538Srpaulo /* Set number of pages for normal priority queue. */ 2187251538Srpaulo urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2188251538Srpaulo urtwn_write_4(sc, R92C_RQPN, 2189251538Srpaulo /* Set number of pages for public queue. */ 2190251538Srpaulo SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2191251538Srpaulo /* Set number of pages for high priority queue. */ 2192251538Srpaulo SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2193251538Srpaulo /* Set number of pages for low priority queue. */ 2194251538Srpaulo SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2195251538Srpaulo /* Load values. */ 2196251538Srpaulo R92C_RQPN_LD); 2197251538Srpaulo 2198251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2199251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2200251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2201251538Srpaulo urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2202251538Srpaulo urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2203251538Srpaulo 2204251538Srpaulo /* Set queue to USB pipe mapping. */ 2205251538Srpaulo reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2206251538Srpaulo reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2207251538Srpaulo if (nqueues == 1) { 2208251538Srpaulo if (hashq) 2209251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2210251538Srpaulo else if (hasnq) 2211251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2212251538Srpaulo else 2213251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2214251538Srpaulo } else if (nqueues == 2) { 2215251538Srpaulo /* All 2-endpoints configs have a high priority queue. */ 2216251538Srpaulo if (!hashq) 2217251538Srpaulo return (EIO); 2218251538Srpaulo if (hasnq) 2219251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2220251538Srpaulo else 2221251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2222251538Srpaulo } else 2223251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2224251538Srpaulo urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2225251538Srpaulo 2226251538Srpaulo /* Set Tx/Rx transfer page boundary. */ 2227251538Srpaulo urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2228251538Srpaulo 2229251538Srpaulo /* Set Tx/Rx transfer page size. */ 2230251538Srpaulo urtwn_write_1(sc, R92C_PBP, 2231251538Srpaulo SM(R92C_PBP_PSRX, R92C_PBP_128) | 2232251538Srpaulo SM(R92C_PBP_PSTX, R92C_PBP_128)); 2233251538Srpaulo return (0); 2234251538Srpaulo} 2235251538Srpaulo 2236251538Srpaulostatic void 2237251538Srpaulourtwn_mac_init(struct urtwn_softc *sc) 2238251538Srpaulo{ 2239251538Srpaulo int i; 2240251538Srpaulo 2241251538Srpaulo /* Write MAC initialization values. */ 2242251538Srpaulo for (i = 0; i < nitems(rtl8192cu_mac); i++) 2243251538Srpaulo urtwn_write_1(sc, rtl8192cu_mac[i].reg, rtl8192cu_mac[i].val); 2244251538Srpaulo} 2245251538Srpaulo 2246251538Srpaulostatic void 2247251538Srpaulourtwn_bb_init(struct urtwn_softc *sc) 2248251538Srpaulo{ 2249251538Srpaulo const struct urtwn_bb_prog *prog; 2250251538Srpaulo uint32_t reg; 2251251538Srpaulo int i; 2252251538Srpaulo 2253251538Srpaulo /* Enable BB and RF. */ 2254251538Srpaulo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2255251538Srpaulo urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2256251538Srpaulo R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2257251538Srpaulo R92C_SYS_FUNC_EN_DIO_RF); 2258251538Srpaulo 2259251538Srpaulo urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2260251538Srpaulo 2261251538Srpaulo urtwn_write_1(sc, R92C_RF_CTRL, 2262251538Srpaulo R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2263251538Srpaulo urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2264251538Srpaulo R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2265251538Srpaulo R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2266251538Srpaulo 2267251538Srpaulo urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2268251538Srpaulo urtwn_write_1(sc, 0x15, 0xe9); 2269251538Srpaulo urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2270251538Srpaulo 2271251538Srpaulo /* Select BB programming based on board type. */ 2272251538Srpaulo if (!(sc->chip & URTWN_CHIP_92C)) { 2273251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2274251538Srpaulo prog = &rtl8188ce_bb_prog; 2275251538Srpaulo else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2276251538Srpaulo prog = &rtl8188ru_bb_prog; 2277251538Srpaulo else 2278251538Srpaulo prog = &rtl8188cu_bb_prog; 2279251538Srpaulo } else { 2280251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2281251538Srpaulo prog = &rtl8192ce_bb_prog; 2282251538Srpaulo else 2283251538Srpaulo prog = &rtl8192cu_bb_prog; 2284251538Srpaulo } 2285251538Srpaulo /* Write BB initialization values. */ 2286251538Srpaulo for (i = 0; i < prog->count; i++) { 2287251538Srpaulo urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2288251538Srpaulo DELAY(1); 2289251538Srpaulo } 2290251538Srpaulo 2291251538Srpaulo if (sc->chip & URTWN_CHIP_92C_1T2R) { 2292251538Srpaulo /* 8192C 1T only configuration. */ 2293251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2294251538Srpaulo reg = (reg & ~0x00000003) | 0x2; 2295251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2296251538Srpaulo 2297251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2298251538Srpaulo reg = (reg & ~0x00300033) | 0x00200022; 2299251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2300251538Srpaulo 2301251538Srpaulo reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2302251538Srpaulo reg = (reg & ~0xff000000) | 0x45 << 24; 2303251538Srpaulo urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2304251538Srpaulo 2305251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2306251538Srpaulo reg = (reg & ~0x000000ff) | 0x23; 2307251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2308251538Srpaulo 2309251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2310251538Srpaulo reg = (reg & ~0x00000030) | 1 << 4; 2311251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2312251538Srpaulo 2313251538Srpaulo reg = urtwn_bb_read(sc, 0xe74); 2314251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2315251538Srpaulo urtwn_bb_write(sc, 0xe74, reg); 2316251538Srpaulo reg = urtwn_bb_read(sc, 0xe78); 2317251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2318251538Srpaulo urtwn_bb_write(sc, 0xe78, reg); 2319251538Srpaulo reg = urtwn_bb_read(sc, 0xe7c); 2320251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2321251538Srpaulo urtwn_bb_write(sc, 0xe7c, reg); 2322251538Srpaulo reg = urtwn_bb_read(sc, 0xe80); 2323251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2324251538Srpaulo urtwn_bb_write(sc, 0xe80, reg); 2325251538Srpaulo reg = urtwn_bb_read(sc, 0xe88); 2326251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2327251538Srpaulo urtwn_bb_write(sc, 0xe88, reg); 2328251538Srpaulo } 2329251538Srpaulo 2330251538Srpaulo /* Write AGC values. */ 2331251538Srpaulo for (i = 0; i < prog->agccount; i++) { 2332251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2333251538Srpaulo prog->agcvals[i]); 2334251538Srpaulo DELAY(1); 2335251538Srpaulo } 2336251538Srpaulo 2337251538Srpaulo if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2338251538Srpaulo R92C_HSSI_PARAM2_CCK_HIPWR) 2339251538Srpaulo sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 2340251538Srpaulo} 2341251538Srpaulo 2342251538Srpaulovoid 2343251538Srpaulourtwn_rf_init(struct urtwn_softc *sc) 2344251538Srpaulo{ 2345251538Srpaulo const struct urtwn_rf_prog *prog; 2346251538Srpaulo uint32_t reg, type; 2347251538Srpaulo int i, j, idx, off; 2348251538Srpaulo 2349251538Srpaulo /* Select RF programming based on board type. */ 2350251538Srpaulo if (!(sc->chip & URTWN_CHIP_92C)) { 2351251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2352251538Srpaulo prog = rtl8188ce_rf_prog; 2353251538Srpaulo else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2354251538Srpaulo prog = rtl8188ru_rf_prog; 2355251538Srpaulo else 2356251538Srpaulo prog = rtl8188cu_rf_prog; 2357251538Srpaulo } else 2358251538Srpaulo prog = rtl8192ce_rf_prog; 2359251538Srpaulo 2360251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 2361251538Srpaulo /* Save RF_ENV control type. */ 2362251538Srpaulo idx = i / 2; 2363251538Srpaulo off = (i % 2) * 16; 2364251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2365251538Srpaulo type = (reg >> off) & 0x10; 2366251538Srpaulo 2367251538Srpaulo /* Set RF_ENV enable. */ 2368251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2369251538Srpaulo reg |= 0x100000; 2370251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2371251538Srpaulo DELAY(1); 2372251538Srpaulo /* Set RF_ENV output high. */ 2373251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2374251538Srpaulo reg |= 0x10; 2375251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2376251538Srpaulo DELAY(1); 2377251538Srpaulo /* Set address and data lengths of RF registers. */ 2378251538Srpaulo reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2379251538Srpaulo reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2380251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2381251538Srpaulo DELAY(1); 2382251538Srpaulo reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2383251538Srpaulo reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2384251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2385251538Srpaulo DELAY(1); 2386251538Srpaulo 2387251538Srpaulo /* Write RF initialization values for this chain. */ 2388251538Srpaulo for (j = 0; j < prog[i].count; j++) { 2389251538Srpaulo if (prog[i].regs[j] >= 0xf9 && 2390251538Srpaulo prog[i].regs[j] <= 0xfe) { 2391251538Srpaulo /* 2392251538Srpaulo * These are fake RF registers offsets that 2393251538Srpaulo * indicate a delay is required. 2394251538Srpaulo */ 2395251538Srpaulo usb_pause_mtx(&sc->sc_mtx, 50); 2396251538Srpaulo continue; 2397251538Srpaulo } 2398251538Srpaulo urtwn_rf_write(sc, i, prog[i].regs[j], 2399251538Srpaulo prog[i].vals[j]); 2400251538Srpaulo DELAY(1); 2401251538Srpaulo } 2402251538Srpaulo 2403251538Srpaulo /* Restore RF_ENV control type. */ 2404251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2405251538Srpaulo reg &= ~(0x10 << off) | (type << off); 2406251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2407251538Srpaulo 2408251538Srpaulo /* Cache RF register CHNLBW. */ 2409251538Srpaulo sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2410251538Srpaulo } 2411251538Srpaulo 2412251538Srpaulo if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2413251538Srpaulo URTWN_CHIP_UMC_A_CUT) { 2414251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2415251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2416251538Srpaulo } 2417251538Srpaulo} 2418251538Srpaulo 2419251538Srpaulostatic void 2420251538Srpaulourtwn_cam_init(struct urtwn_softc *sc) 2421251538Srpaulo{ 2422251538Srpaulo /* Invalidate all CAM entries. */ 2423251538Srpaulo urtwn_write_4(sc, R92C_CAMCMD, 2424251538Srpaulo R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2425251538Srpaulo} 2426251538Srpaulo 2427251538Srpaulostatic void 2428251538Srpaulourtwn_pa_bias_init(struct urtwn_softc *sc) 2429251538Srpaulo{ 2430251538Srpaulo uint8_t reg; 2431251538Srpaulo int i; 2432251538Srpaulo 2433251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 2434251538Srpaulo if (sc->pa_setting & (1 << i)) 2435251538Srpaulo continue; 2436251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2437251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2438251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2439251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2440251538Srpaulo } 2441251538Srpaulo if (!(sc->pa_setting & 0x10)) { 2442251538Srpaulo reg = urtwn_read_1(sc, 0x16); 2443251538Srpaulo reg = (reg & ~0xf0) | 0x90; 2444251538Srpaulo urtwn_write_1(sc, 0x16, reg); 2445251538Srpaulo } 2446251538Srpaulo} 2447251538Srpaulo 2448251538Srpaulostatic void 2449251538Srpaulourtwn_rxfilter_init(struct urtwn_softc *sc) 2450251538Srpaulo{ 2451251538Srpaulo /* Initialize Rx filter. */ 2452251538Srpaulo /* TODO: use better filter for monitor mode. */ 2453251538Srpaulo urtwn_write_4(sc, R92C_RCR, 2454251538Srpaulo R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2455251538Srpaulo R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2456251538Srpaulo R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2457251538Srpaulo /* Accept all multicast frames. */ 2458251538Srpaulo urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2459251538Srpaulo urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2460251538Srpaulo /* Accept all management frames. */ 2461251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2462251538Srpaulo /* Reject all control frames. */ 2463251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2464251538Srpaulo /* Accept all data frames. */ 2465251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2466251538Srpaulo} 2467251538Srpaulo 2468251538Srpaulostatic void 2469251538Srpaulourtwn_edca_init(struct urtwn_softc *sc) 2470251538Srpaulo{ 2471251538Srpaulo urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 2472251538Srpaulo urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 2473251538Srpaulo urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 2474251538Srpaulo urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 2475251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2476251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2477251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 2478251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 2479251538Srpaulo} 2480251538Srpaulo 2481251538Srpaulovoid 2482251538Srpaulourtwn_write_txpower(struct urtwn_softc *sc, int chain, 2483251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]) 2484251538Srpaulo{ 2485251538Srpaulo uint32_t reg; 2486251538Srpaulo 2487251538Srpaulo /* Write per-CCK rate Tx power. */ 2488251538Srpaulo if (chain == 0) { 2489251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2490251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2491251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2492251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2493251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2494251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2495251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2496251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2497251538Srpaulo } else { 2498251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2499251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2500251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2501251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2502251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2503251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2504251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2505251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2506251538Srpaulo } 2507251538Srpaulo /* Write per-OFDM rate Tx power. */ 2508251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2509251538Srpaulo SM(R92C_TXAGC_RATE06, power[ 4]) | 2510251538Srpaulo SM(R92C_TXAGC_RATE09, power[ 5]) | 2511251538Srpaulo SM(R92C_TXAGC_RATE12, power[ 6]) | 2512251538Srpaulo SM(R92C_TXAGC_RATE18, power[ 7])); 2513251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2514251538Srpaulo SM(R92C_TXAGC_RATE24, power[ 8]) | 2515251538Srpaulo SM(R92C_TXAGC_RATE36, power[ 9]) | 2516251538Srpaulo SM(R92C_TXAGC_RATE48, power[10]) | 2517251538Srpaulo SM(R92C_TXAGC_RATE54, power[11])); 2518251538Srpaulo /* Write per-MCS Tx power. */ 2519251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2520251538Srpaulo SM(R92C_TXAGC_MCS00, power[12]) | 2521251538Srpaulo SM(R92C_TXAGC_MCS01, power[13]) | 2522251538Srpaulo SM(R92C_TXAGC_MCS02, power[14]) | 2523251538Srpaulo SM(R92C_TXAGC_MCS03, power[15])); 2524251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2525251538Srpaulo SM(R92C_TXAGC_MCS04, power[16]) | 2526251538Srpaulo SM(R92C_TXAGC_MCS05, power[17]) | 2527251538Srpaulo SM(R92C_TXAGC_MCS06, power[18]) | 2528251538Srpaulo SM(R92C_TXAGC_MCS07, power[19])); 2529251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2530251538Srpaulo SM(R92C_TXAGC_MCS08, power[20]) | 2531261506Skevlo SM(R92C_TXAGC_MCS09, power[21]) | 2532251538Srpaulo SM(R92C_TXAGC_MCS10, power[22]) | 2533251538Srpaulo SM(R92C_TXAGC_MCS11, power[23])); 2534251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2535251538Srpaulo SM(R92C_TXAGC_MCS12, power[24]) | 2536251538Srpaulo SM(R92C_TXAGC_MCS13, power[25]) | 2537251538Srpaulo SM(R92C_TXAGC_MCS14, power[26]) | 2538251538Srpaulo SM(R92C_TXAGC_MCS15, power[27])); 2539251538Srpaulo} 2540251538Srpaulo 2541251538Srpaulovoid 2542251538Srpaulourtwn_get_txpower(struct urtwn_softc *sc, int chain, 2543251538Srpaulo struct ieee80211_channel *c, struct ieee80211_channel *extc, 2544251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]) 2545251538Srpaulo{ 2546251538Srpaulo struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2547251538Srpaulo struct r92c_rom *rom = &sc->rom; 2548251538Srpaulo uint16_t cckpow, ofdmpow, htpow, diff, max; 2549251538Srpaulo const struct urtwn_txpwr *base; 2550251538Srpaulo int ridx, chan, group; 2551251538Srpaulo 2552251538Srpaulo /* Determine channel group. */ 2553251538Srpaulo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2554251538Srpaulo if (chan <= 3) 2555251538Srpaulo group = 0; 2556251538Srpaulo else if (chan <= 9) 2557251538Srpaulo group = 1; 2558251538Srpaulo else 2559251538Srpaulo group = 2; 2560251538Srpaulo 2561251538Srpaulo /* Get original Tx power based on board type and RF chain. */ 2562251538Srpaulo if (!(sc->chip & URTWN_CHIP_92C)) { 2563251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2564251538Srpaulo base = &rtl8188ru_txagc[chain]; 2565251538Srpaulo else 2566251538Srpaulo base = &rtl8192cu_txagc[chain]; 2567251538Srpaulo } else 2568251538Srpaulo base = &rtl8192cu_txagc[chain]; 2569251538Srpaulo 2570251538Srpaulo memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 2571251538Srpaulo if (sc->regulatory == 0) { 2572251538Srpaulo for (ridx = 0; ridx <= 3; ridx++) 2573251538Srpaulo power[ridx] = base->pwr[0][ridx]; 2574251538Srpaulo } 2575251538Srpaulo for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 2576251538Srpaulo if (sc->regulatory == 3) { 2577251538Srpaulo power[ridx] = base->pwr[0][ridx]; 2578251538Srpaulo /* Apply vendor limits. */ 2579251538Srpaulo if (extc != NULL) 2580251538Srpaulo max = rom->ht40_max_pwr[group]; 2581251538Srpaulo else 2582251538Srpaulo max = rom->ht20_max_pwr[group]; 2583251538Srpaulo max = (max >> (chain * 4)) & 0xf; 2584251538Srpaulo if (power[ridx] > max) 2585251538Srpaulo power[ridx] = max; 2586251538Srpaulo } else if (sc->regulatory == 1) { 2587251538Srpaulo if (extc == NULL) 2588251538Srpaulo power[ridx] = base->pwr[group][ridx]; 2589251538Srpaulo } else if (sc->regulatory != 2) 2590251538Srpaulo power[ridx] = base->pwr[0][ridx]; 2591251538Srpaulo } 2592251538Srpaulo 2593251538Srpaulo /* Compute per-CCK rate Tx power. */ 2594251538Srpaulo cckpow = rom->cck_tx_pwr[chain][group]; 2595251538Srpaulo for (ridx = 0; ridx <= 3; ridx++) { 2596251538Srpaulo power[ridx] += cckpow; 2597251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 2598251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 2599251538Srpaulo } 2600251538Srpaulo 2601251538Srpaulo htpow = rom->ht40_1s_tx_pwr[chain][group]; 2602251538Srpaulo if (sc->ntxchains > 1) { 2603251538Srpaulo /* Apply reduction for 2 spatial streams. */ 2604251538Srpaulo diff = rom->ht40_2s_tx_pwr_diff[group]; 2605251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 2606251538Srpaulo htpow = (htpow > diff) ? htpow - diff : 0; 2607251538Srpaulo } 2608251538Srpaulo 2609251538Srpaulo /* Compute per-OFDM rate Tx power. */ 2610251538Srpaulo diff = rom->ofdm_tx_pwr_diff[group]; 2611251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 2612251538Srpaulo ofdmpow = htpow + diff; /* HT->OFDM correction. */ 2613251538Srpaulo for (ridx = 4; ridx <= 11; ridx++) { 2614251538Srpaulo power[ridx] += ofdmpow; 2615251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 2616251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 2617251538Srpaulo } 2618251538Srpaulo 2619251538Srpaulo /* Compute per-MCS Tx power. */ 2620251538Srpaulo if (extc == NULL) { 2621251538Srpaulo diff = rom->ht20_tx_pwr_diff[group]; 2622251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 2623251538Srpaulo htpow += diff; /* HT40->HT20 correction. */ 2624251538Srpaulo } 2625251538Srpaulo for (ridx = 12; ridx <= 27; ridx++) { 2626251538Srpaulo power[ridx] += htpow; 2627251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 2628251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 2629251538Srpaulo } 2630251538Srpaulo#ifdef URTWN_DEBUG 2631251538Srpaulo if (urtwn_debug >= 4) { 2632251538Srpaulo /* Dump per-rate Tx power values. */ 2633251538Srpaulo printf("Tx power for chain %d:\n", chain); 2634251538Srpaulo for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) 2635251538Srpaulo printf("Rate %d = %u\n", ridx, power[ridx]); 2636251538Srpaulo } 2637251538Srpaulo#endif 2638251538Srpaulo} 2639251538Srpaulo 2640251538Srpaulovoid 2641251538Srpaulourtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 2642251538Srpaulo struct ieee80211_channel *extc) 2643251538Srpaulo{ 2644251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]; 2645251538Srpaulo int i; 2646251538Srpaulo 2647251538Srpaulo for (i = 0; i < sc->ntxchains; i++) { 2648251538Srpaulo /* Compute per-rate Tx power values. */ 2649251538Srpaulo urtwn_get_txpower(sc, i, c, extc, power); 2650251538Srpaulo /* Write per-rate Tx power values to hardware. */ 2651251538Srpaulo urtwn_write_txpower(sc, i, power); 2652251538Srpaulo } 2653251538Srpaulo} 2654251538Srpaulo 2655251538Srpaulostatic void 2656251538Srpaulourtwn_scan_start(struct ieee80211com *ic) 2657251538Srpaulo{ 2658251538Srpaulo /* XXX do nothing? */ 2659251538Srpaulo} 2660251538Srpaulo 2661251538Srpaulostatic void 2662251538Srpaulourtwn_scan_end(struct ieee80211com *ic) 2663251538Srpaulo{ 2664251538Srpaulo /* XXX do nothing? */ 2665251538Srpaulo} 2666251538Srpaulo 2667251538Srpaulostatic void 2668251538Srpaulourtwn_set_channel(struct ieee80211com *ic) 2669251538Srpaulo{ 2670251538Srpaulo struct urtwn_softc *sc = ic->ic_ifp->if_softc; 2671251538Srpaulo 2672251538Srpaulo URTWN_LOCK(sc); 2673251538Srpaulo urtwn_set_chan(sc, ic->ic_curchan, NULL); 2674251538Srpaulo URTWN_UNLOCK(sc); 2675251538Srpaulo} 2676251538Srpaulo 2677251538Srpaulostatic void 2678251538Srpaulourtwn_update_mcast(struct ifnet *ifp) 2679251538Srpaulo{ 2680251538Srpaulo /* XXX do nothing? */ 2681251538Srpaulo} 2682251538Srpaulo 2683251538Srpaulostatic void 2684251538Srpaulourtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 2685251538Srpaulo struct ieee80211_channel *extc) 2686251538Srpaulo{ 2687251538Srpaulo struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2688251538Srpaulo uint32_t reg; 2689251538Srpaulo u_int chan; 2690251538Srpaulo int i; 2691251538Srpaulo 2692251538Srpaulo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2693251538Srpaulo if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 2694251538Srpaulo device_printf(sc->sc_dev, 2695251538Srpaulo "%s: invalid channel %x\n", __func__, chan); 2696251538Srpaulo return; 2697251538Srpaulo } 2698251538Srpaulo 2699251538Srpaulo /* Set Tx power for this new channel. */ 2700251538Srpaulo urtwn_set_txpower(sc, c, extc); 2701251538Srpaulo 2702251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 2703251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 2704251538Srpaulo RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 2705251538Srpaulo } 2706251538Srpaulo#ifndef IEEE80211_NO_HT 2707251538Srpaulo if (extc != NULL) { 2708251538Srpaulo /* Is secondary channel below or above primary? */ 2709251538Srpaulo int prichlo = c->ic_freq < extc->ic_freq; 2710251538Srpaulo 2711251538Srpaulo urtwn_write_1(sc, R92C_BWOPMODE, 2712251538Srpaulo urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 2713251538Srpaulo 2714251538Srpaulo reg = urtwn_read_1(sc, R92C_RRSR + 2); 2715251538Srpaulo reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 2716251538Srpaulo urtwn_write_1(sc, R92C_RRSR + 2, reg); 2717251538Srpaulo 2718251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 2719251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 2720251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 2721251538Srpaulo urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 2722251538Srpaulo 2723251538Srpaulo /* Set CCK side band. */ 2724251538Srpaulo reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 2725251538Srpaulo reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 2726251538Srpaulo urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 2727251538Srpaulo 2728251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 2729251538Srpaulo reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 2730251538Srpaulo urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 2731251538Srpaulo 2732251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 2733251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 2734251538Srpaulo ~R92C_FPGA0_ANAPARAM2_CBW20); 2735251538Srpaulo 2736251538Srpaulo reg = urtwn_bb_read(sc, 0x818); 2737251538Srpaulo reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 2738251538Srpaulo urtwn_bb_write(sc, 0x818, reg); 2739251538Srpaulo 2740251538Srpaulo /* Select 40MHz bandwidth. */ 2741251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 2742251538Srpaulo (sc->rf_chnlbw[0] & ~0xfff) | chan); 2743251538Srpaulo } else 2744251538Srpaulo#endif 2745251538Srpaulo { 2746251538Srpaulo urtwn_write_1(sc, R92C_BWOPMODE, 2747251538Srpaulo urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 2748251538Srpaulo 2749251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 2750251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 2751251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 2752251538Srpaulo urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 2753251538Srpaulo 2754251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 2755251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 2756251538Srpaulo R92C_FPGA0_ANAPARAM2_CBW20); 2757251538Srpaulo 2758251538Srpaulo /* Select 20MHz bandwidth. */ 2759251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 2760251538Srpaulo (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan); 2761251538Srpaulo } 2762251538Srpaulo} 2763251538Srpaulo 2764251538Srpaulostatic void 2765251538Srpaulourtwn_iq_calib(struct urtwn_softc *sc) 2766251538Srpaulo{ 2767251538Srpaulo /* TODO */ 2768251538Srpaulo} 2769251538Srpaulo 2770251538Srpaulostatic void 2771251538Srpaulourtwn_lc_calib(struct urtwn_softc *sc) 2772251538Srpaulo{ 2773251538Srpaulo uint32_t rf_ac[2]; 2774251538Srpaulo uint8_t txmode; 2775251538Srpaulo int i; 2776251538Srpaulo 2777251538Srpaulo txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 2778251538Srpaulo if ((txmode & 0x70) != 0) { 2779251538Srpaulo /* Disable all continuous Tx. */ 2780251538Srpaulo urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 2781251538Srpaulo 2782251538Srpaulo /* Set RF mode to standby mode. */ 2783251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 2784251538Srpaulo rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 2785251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_AC, 2786251538Srpaulo RW(rf_ac[i], R92C_RF_AC_MODE, 2787251538Srpaulo R92C_RF_AC_MODE_STANDBY)); 2788251538Srpaulo } 2789251538Srpaulo } else { 2790251538Srpaulo /* Block all Tx queues. */ 2791251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 2792251538Srpaulo } 2793251538Srpaulo /* Start calibration. */ 2794251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 2795251538Srpaulo urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 2796251538Srpaulo 2797251538Srpaulo /* Give calibration the time to complete. */ 2798251538Srpaulo usb_pause_mtx(&sc->sc_mtx, 100); 2799251538Srpaulo 2800251538Srpaulo /* Restore configuration. */ 2801251538Srpaulo if ((txmode & 0x70) != 0) { 2802251538Srpaulo /* Restore Tx mode. */ 2803251538Srpaulo urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 2804251538Srpaulo /* Restore RF mode. */ 2805251538Srpaulo for (i = 0; i < sc->nrxchains; i++) 2806251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 2807251538Srpaulo } else { 2808251538Srpaulo /* Unblock all Tx queues. */ 2809251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 2810251538Srpaulo } 2811251538Srpaulo} 2812251538Srpaulo 2813251538Srpaulostatic void 2814251538Srpaulourtwn_init_locked(void *arg) 2815251538Srpaulo{ 2816251538Srpaulo struct urtwn_softc *sc = arg; 2817251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 2818251538Srpaulo uint32_t reg; 2819251538Srpaulo int error; 2820251538Srpaulo 2821264864Skevlo URTWN_ASSERT_LOCKED(sc); 2822264864Skevlo 2823251538Srpaulo if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2824263153Skevlo urtwn_stop_locked(ifp); 2825251538Srpaulo 2826251538Srpaulo /* Init firmware commands ring. */ 2827251538Srpaulo sc->fwcur = 0; 2828251538Srpaulo 2829251538Srpaulo /* Allocate Tx/Rx buffers. */ 2830251538Srpaulo error = urtwn_alloc_rx_list(sc); 2831251538Srpaulo if (error != 0) 2832251538Srpaulo goto fail; 2833251538Srpaulo 2834251538Srpaulo error = urtwn_alloc_tx_list(sc); 2835251538Srpaulo if (error != 0) 2836251538Srpaulo goto fail; 2837251538Srpaulo 2838251538Srpaulo /* Power on adapter. */ 2839251538Srpaulo error = urtwn_power_on(sc); 2840251538Srpaulo if (error != 0) 2841251538Srpaulo goto fail; 2842251538Srpaulo 2843251538Srpaulo /* Initialize DMA. */ 2844251538Srpaulo error = urtwn_dma_init(sc); 2845251538Srpaulo if (error != 0) 2846251538Srpaulo goto fail; 2847251538Srpaulo 2848251538Srpaulo /* Set info size in Rx descriptors (in 64-bit words). */ 2849251538Srpaulo urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 2850251538Srpaulo 2851251538Srpaulo /* Init interrupts. */ 2852251538Srpaulo urtwn_write_4(sc, R92C_HISR, 0xffffffff); 2853251538Srpaulo urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 2854251538Srpaulo 2855251538Srpaulo /* Set MAC address. */ 2856251538Srpaulo urtwn_write_region_1(sc, R92C_MACID, IF_LLADDR(ifp), 2857251538Srpaulo IEEE80211_ADDR_LEN); 2858251538Srpaulo 2859251538Srpaulo /* Set initial network type. */ 2860251538Srpaulo reg = urtwn_read_4(sc, R92C_CR); 2861251538Srpaulo reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 2862251538Srpaulo urtwn_write_4(sc, R92C_CR, reg); 2863251538Srpaulo 2864251538Srpaulo urtwn_rxfilter_init(sc); 2865251538Srpaulo 2866251538Srpaulo reg = urtwn_read_4(sc, R92C_RRSR); 2867251538Srpaulo reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 2868251538Srpaulo urtwn_write_4(sc, R92C_RRSR, reg); 2869251538Srpaulo 2870251538Srpaulo /* Set short/long retry limits. */ 2871251538Srpaulo urtwn_write_2(sc, R92C_RL, 2872251538Srpaulo SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 2873251538Srpaulo 2874251538Srpaulo /* Initialize EDCA parameters. */ 2875251538Srpaulo urtwn_edca_init(sc); 2876251538Srpaulo 2877251538Srpaulo /* Setup rate fallback. */ 2878251538Srpaulo urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 2879251538Srpaulo urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 2880251538Srpaulo urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 2881251538Srpaulo urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 2882251538Srpaulo 2883251538Srpaulo urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 2884251538Srpaulo urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 2885251538Srpaulo R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 2886251538Srpaulo /* Set ACK timeout. */ 2887251538Srpaulo urtwn_write_1(sc, R92C_ACKTO, 0x40); 2888251538Srpaulo 2889251538Srpaulo /* Setup USB aggregation. */ 2890251538Srpaulo reg = urtwn_read_4(sc, R92C_TDECTRL); 2891251538Srpaulo reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 2892251538Srpaulo urtwn_write_4(sc, R92C_TDECTRL, reg); 2893251538Srpaulo urtwn_write_1(sc, R92C_TRXDMA_CTRL, 2894251538Srpaulo urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 2895251538Srpaulo R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 2896251538Srpaulo urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 2897251538Srpaulo urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 2898251538Srpaulo R92C_USB_SPECIAL_OPTION_AGG_EN); 2899251538Srpaulo urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 2900251538Srpaulo urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 2901251538Srpaulo urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 2902251538Srpaulo urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 2903251538Srpaulo 2904251538Srpaulo /* Initialize beacon parameters. */ 2905251538Srpaulo urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 2906251538Srpaulo urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 2907251538Srpaulo urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 2908251538Srpaulo urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 2909251538Srpaulo 2910251538Srpaulo /* Setup AMPDU aggregation. */ 2911251538Srpaulo urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 2912251538Srpaulo urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 2913251538Srpaulo urtwn_write_2(sc, 0x4ca, 0x0708); 2914251538Srpaulo 2915251538Srpaulo urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 2916251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 2917251538Srpaulo 2918251538Srpaulo /* Load 8051 microcode. */ 2919251538Srpaulo error = urtwn_load_firmware(sc); 2920251538Srpaulo if (error != 0) 2921251538Srpaulo goto fail; 2922251538Srpaulo 2923251538Srpaulo /* Initialize MAC/BB/RF blocks. */ 2924251538Srpaulo urtwn_mac_init(sc); 2925251538Srpaulo urtwn_bb_init(sc); 2926251538Srpaulo urtwn_rf_init(sc); 2927251538Srpaulo 2928251538Srpaulo /* Turn CCK and OFDM blocks on. */ 2929251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 2930251538Srpaulo reg |= R92C_RFMOD_CCK_EN; 2931251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 2932251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 2933251538Srpaulo reg |= R92C_RFMOD_OFDM_EN; 2934251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 2935251538Srpaulo 2936251538Srpaulo /* Clear per-station keys table. */ 2937251538Srpaulo urtwn_cam_init(sc); 2938251538Srpaulo 2939251538Srpaulo /* Enable hardware sequence numbering. */ 2940251538Srpaulo urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 2941251538Srpaulo 2942251538Srpaulo /* Perform LO and IQ calibrations. */ 2943251538Srpaulo urtwn_iq_calib(sc); 2944251538Srpaulo /* Perform LC calibration. */ 2945251538Srpaulo urtwn_lc_calib(sc); 2946251538Srpaulo 2947251538Srpaulo /* Fix USB interference issue. */ 2948251538Srpaulo urtwn_write_1(sc, 0xfe40, 0xe0); 2949251538Srpaulo urtwn_write_1(sc, 0xfe41, 0x8d); 2950251538Srpaulo urtwn_write_1(sc, 0xfe42, 0x80); 2951251538Srpaulo 2952251538Srpaulo urtwn_pa_bias_init(sc); 2953251538Srpaulo 2954251538Srpaulo /* Initialize GPIO setting. */ 2955251538Srpaulo urtwn_write_1(sc, R92C_GPIO_MUXCFG, 2956251538Srpaulo urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 2957251538Srpaulo 2958251538Srpaulo /* Fix for lower temperature. */ 2959251538Srpaulo urtwn_write_1(sc, 0x15, 0xe9); 2960251538Srpaulo 2961251538Srpaulo usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 2962251538Srpaulo 2963251538Srpaulo ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2964251538Srpaulo ifp->if_drv_flags |= IFF_DRV_RUNNING; 2965251538Srpaulo 2966251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2967251538Srpaulofail: 2968251538Srpaulo return; 2969251538Srpaulo} 2970251538Srpaulo 2971251538Srpaulostatic void 2972251538Srpaulourtwn_init(void *arg) 2973251538Srpaulo{ 2974251538Srpaulo struct urtwn_softc *sc = arg; 2975251538Srpaulo 2976251538Srpaulo URTWN_LOCK(sc); 2977251538Srpaulo urtwn_init_locked(arg); 2978251538Srpaulo URTWN_UNLOCK(sc); 2979251538Srpaulo} 2980251538Srpaulo 2981251538Srpaulostatic void 2982263153Skevlourtwn_stop_locked(struct ifnet *ifp) 2983251538Srpaulo{ 2984251538Srpaulo struct urtwn_softc *sc = ifp->if_softc; 2985251538Srpaulo 2986264864Skevlo URTWN_ASSERT_LOCKED(sc); 2987264864Skevlo 2988251538Srpaulo ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2989251538Srpaulo 2990251538Srpaulo callout_stop(&sc->sc_watchdog_ch); 2991251538Srpaulo urtwn_abort_xfers(sc); 2992251538Srpaulo} 2993251538Srpaulo 2994251538Srpaulostatic void 2995263153Skevlourtwn_stop(struct ifnet *ifp) 2996251538Srpaulo{ 2997251538Srpaulo struct urtwn_softc *sc = ifp->if_softc; 2998251538Srpaulo 2999251538Srpaulo URTWN_LOCK(sc); 3000263153Skevlo urtwn_stop_locked(ifp); 3001251538Srpaulo URTWN_UNLOCK(sc); 3002251538Srpaulo} 3003251538Srpaulo 3004251538Srpaulostatic void 3005251538Srpaulourtwn_abort_xfers(struct urtwn_softc *sc) 3006251538Srpaulo{ 3007251538Srpaulo int i; 3008251538Srpaulo 3009251538Srpaulo URTWN_ASSERT_LOCKED(sc); 3010251538Srpaulo 3011251538Srpaulo /* abort any pending transfers */ 3012251538Srpaulo for (i = 0; i < URTWN_N_TRANSFER; i++) 3013251538Srpaulo usbd_transfer_stop(sc->sc_xfer[i]); 3014251538Srpaulo} 3015251538Srpaulo 3016251538Srpaulostatic int 3017251538Srpaulourtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3018251538Srpaulo const struct ieee80211_bpf_params *params) 3019251538Srpaulo{ 3020251538Srpaulo struct ieee80211com *ic = ni->ni_ic; 3021251538Srpaulo struct ifnet *ifp = ic->ic_ifp; 3022251538Srpaulo struct urtwn_softc *sc = ifp->if_softc; 3023251538Srpaulo struct urtwn_data *bf; 3024251538Srpaulo 3025251538Srpaulo /* prevent management frames from being sent if we're not ready */ 3026251538Srpaulo if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3027251538Srpaulo m_freem(m); 3028251538Srpaulo ieee80211_free_node(ni); 3029251538Srpaulo return (ENETDOWN); 3030251538Srpaulo } 3031251538Srpaulo URTWN_LOCK(sc); 3032251538Srpaulo bf = urtwn_getbuf(sc); 3033251538Srpaulo if (bf == NULL) { 3034251538Srpaulo ieee80211_free_node(ni); 3035251538Srpaulo m_freem(m); 3036251538Srpaulo URTWN_UNLOCK(sc); 3037251538Srpaulo return (ENOBUFS); 3038251538Srpaulo } 3039251538Srpaulo 3040251538Srpaulo ifp->if_opackets++; 3041251538Srpaulo if (urtwn_tx_start(sc, ni, m, bf) != 0) { 3042251538Srpaulo ieee80211_free_node(ni); 3043251538Srpaulo ifp->if_oerrors++; 3044251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3045251538Srpaulo URTWN_UNLOCK(sc); 3046251538Srpaulo return (EIO); 3047251538Srpaulo } 3048251538Srpaulo URTWN_UNLOCK(sc); 3049251538Srpaulo 3050251538Srpaulo sc->sc_txtimer = 5; 3051251538Srpaulo return (0); 3052251538Srpaulo} 3053251538Srpaulo 3054251538Srpaulostatic device_method_t urtwn_methods[] = { 3055251538Srpaulo /* Device interface */ 3056251538Srpaulo DEVMETHOD(device_probe, urtwn_match), 3057251538Srpaulo DEVMETHOD(device_attach, urtwn_attach), 3058251538Srpaulo DEVMETHOD(device_detach, urtwn_detach), 3059251538Srpaulo 3060251538Srpaulo { 0, 0 } 3061251538Srpaulo}; 3062251538Srpaulo 3063251538Srpaulostatic driver_t urtwn_driver = { 3064251538Srpaulo "urtwn", 3065251538Srpaulo urtwn_methods, 3066251538Srpaulo sizeof(struct urtwn_softc) 3067251538Srpaulo}; 3068251538Srpaulo 3069251538Srpaulostatic devclass_t urtwn_devclass; 3070251538Srpaulo 3071251538SrpauloDRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 3072251538SrpauloMODULE_DEPEND(urtwn, usb, 1, 1, 1); 3073251538SrpauloMODULE_DEPEND(urtwn, wlan, 1, 1, 1); 3074251538SrpauloMODULE_DEPEND(urtwn, firmware, 1, 1, 1); 3075251538SrpauloMODULE_VERSION(urtwn, 1); 3076