if_urtwn.c revision 264864
1341825Sdim/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2317685Sdim 3353358Sdim/*- 4353358Sdim * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5353358Sdim * 6317685Sdim * Permission to use, copy, modify, and distribute this software for any 7317685Sdim * purpose with or without fee is hereby granted, provided that the above 8317685Sdim * copyright notice and this permission notice appear in all copies. 9317685Sdim * 10317685Sdim * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11317685Sdim * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12317685Sdim * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13317685Sdim * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14317685Sdim * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15317685Sdim * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16317685Sdim * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17344779Sdim */ 18317685Sdim 19317685Sdim#include <sys/cdefs.h> 20317685Sdim__FBSDID("$FreeBSD: head/sys/dev/usb/wlan/if_urtwn.c 264864 2014-04-24 03:16:47Z kevlo $"); 21360784Sdim 22341825Sdim/* 23317685Sdim * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188RU/RTL8192CU. 24317685Sdim */ 25317685Sdim 26317685Sdim#include <sys/param.h> 27317685Sdim#include <sys/sockio.h> 28317685Sdim#include <sys/sysctl.h> 29317685Sdim#include <sys/lock.h> 30317685Sdim#include <sys/mutex.h> 31317685Sdim#include <sys/mbuf.h> 32317685Sdim#include <sys/kernel.h> 33341825Sdim#include <sys/socket.h> 34341825Sdim#include <sys/systm.h> 35341825Sdim#include <sys/malloc.h> 36341825Sdim#include <sys/module.h> 37341825Sdim#include <sys/bus.h> 38341825Sdim#include <sys/endian.h> 39341825Sdim#include <sys/linker.h> 40341825Sdim#include <sys/firmware.h> 41317685Sdim#include <sys/kdb.h> 42317685Sdim 43317685Sdim#include <machine/bus.h> 44317685Sdim#include <machine/resource.h> 45360784Sdim#include <sys/rman.h> 46360784Sdim 47360784Sdim#include <net/bpf.h> 48317685Sdim#include <net/if.h> 49360784Sdim#include <net/if_var.h> 50360784Sdim#include <net/if_arp.h> 51360784Sdim#include <net/ethernet.h> 52317685Sdim#include <net/if_dl.h> 53317685Sdim#include <net/if_media.h> 54317685Sdim#include <net/if_types.h> 55317685Sdim 56317685Sdim#include <netinet/in.h> 57341825Sdim#include <netinet/in_systm.h> 58341825Sdim#include <netinet/in_var.h> 59317685Sdim#include <netinet/if_ether.h> 60317685Sdim#include <netinet/ip.h> 61317685Sdim 62317685Sdim#include <net80211/ieee80211_var.h> 63317685Sdim#include <net80211/ieee80211_regdomain.h> 64317685Sdim#include <net80211/ieee80211_radiotap.h> 65317685Sdim#include <net80211/ieee80211_ratectl.h> 66317685Sdim 67317685Sdim#include <dev/usb/usb.h> 68317685Sdim#include <dev/usb/usbdi.h> 69317685Sdim#include "usbdevs.h" 70341825Sdim 71317685Sdim#define USB_DEBUG_VAR urtwn_debug 72317685Sdim#include <dev/usb/usb_debug.h> 73317685Sdim 74317685Sdim#include <dev/usb/wlan/if_urtwnreg.h> 75341825Sdim 76320572Sdim#ifdef USB_DEBUG 77320572Sdimstatic int urtwn_debug = 0; 78317685Sdim 79341825SdimSYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 80341825SdimSYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RW, &urtwn_debug, 0, 81317685Sdim "Debug level"); 82317685Sdim#endif 83317685Sdim 84317685Sdim#define URTWN_RSSI(r) (r) - 110 85317685Sdim#define IEEE80211_HAS_ADDR4(wh) \ 86317685Sdim (((wh)->i_fc[1] & IEEE80211_FC1_DIR_MASK) == IEEE80211_FC1_DIR_DSTODS) 87341825Sdim 88341825Sdim/* various supported device vendors/products */ 89341825Sdimstatic const STRUCT_USB_HOST_ID urtwn_devs[] = { 90360784Sdim#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 91341825Sdim URTWN_DEV(ABOCOM, RTL8188CU_1), 92317685Sdim URTWN_DEV(ABOCOM, RTL8188CU_2), 93317685Sdim URTWN_DEV(ABOCOM, RTL8192CU), 94341825Sdim URTWN_DEV(ASUS, RTL8192CU), 95341825Sdim URTWN_DEV(ASUS, USBN10NANO), 96341825Sdim URTWN_DEV(AZUREWAVE, RTL8188CE_1), 97360784Sdim URTWN_DEV(AZUREWAVE, RTL8188CE_2), 98341825Sdim URTWN_DEV(AZUREWAVE, RTL8188CU), 99317685Sdim URTWN_DEV(BELKIN, F7D2102), 100317685Sdim URTWN_DEV(BELKIN, RTL8188CU), 101317685Sdim URTWN_DEV(BELKIN, RTL8192CU), 102317685Sdim URTWN_DEV(CHICONY, RTL8188CUS_1), 103317685Sdim URTWN_DEV(CHICONY, RTL8188CUS_2), 104317685Sdim URTWN_DEV(CHICONY, RTL8188CUS_3), 105317685Sdim URTWN_DEV(CHICONY, RTL8188CUS_4), 106317685Sdim URTWN_DEV(CHICONY, RTL8188CUS_5), 107317685Sdim URTWN_DEV(COREGA, RTL8192CU), 108317685Sdim URTWN_DEV(DLINK, RTL8188CU), 109317685Sdim URTWN_DEV(DLINK, RTL8192CU_1), 110317685Sdim URTWN_DEV(DLINK, RTL8192CU_2), 111317685Sdim URTWN_DEV(DLINK, RTL8192CU_3), 112317685Sdim URTWN_DEV(DLINK, DWA131B), 113353358Sdim URTWN_DEV(EDIMAX, EW7811UN), 114353358Sdim URTWN_DEV(EDIMAX, RTL8192CU), 115353358Sdim URTWN_DEV(FEIXUN, RTL8188CU), 116353358Sdim URTWN_DEV(FEIXUN, RTL8192CU), 117317685Sdim URTWN_DEV(GUILLEMOT, HWNUP150), 118317685Sdim URTWN_DEV(HAWKING, RTL8192CU), 119317685Sdim URTWN_DEV(HP3, RTL8188CU), 120344779Sdim URTWN_DEV(NETGEAR, WNA1000M), 121344779Sdim URTWN_DEV(NETGEAR, RTL8192CU), 122317685Sdim URTWN_DEV(NETGEAR4, RTL8188CU), 123344779Sdim URTWN_DEV(NOVATECH, RTL8188CU), 124344779Sdim URTWN_DEV(PLANEX2, RTL8188CU_1), 125344779Sdim URTWN_DEV(PLANEX2, RTL8188CU_2), 126344779Sdim URTWN_DEV(PLANEX2, RTL8188CU_3), 127344779Sdim URTWN_DEV(PLANEX2, RTL8188CU_4), 128344779Sdim URTWN_DEV(PLANEX2, RTL8188CUS), 129344779Sdim URTWN_DEV(PLANEX2, RTL8192CU), 130344779Sdim URTWN_DEV(REALTEK, RTL8188CE_0), 131344779Sdim URTWN_DEV(REALTEK, RTL8188CE_1), 132344779Sdim URTWN_DEV(REALTEK, RTL8188CTV), 133317685Sdim URTWN_DEV(REALTEK, RTL8188CU_0), 134341825Sdim URTWN_DEV(REALTEK, RTL8188CU_1), 135317685Sdim URTWN_DEV(REALTEK, RTL8188CU_2), 136317685Sdim URTWN_DEV(REALTEK, RTL8188CU_COMBO), 137317685Sdim URTWN_DEV(REALTEK, RTL8188CUS), 138 URTWN_DEV(REALTEK, RTL8188RU_1), 139 URTWN_DEV(REALTEK, RTL8188RU_2), 140 URTWN_DEV(REALTEK, RTL8191CU), 141 URTWN_DEV(REALTEK, RTL8192CE), 142 URTWN_DEV(REALTEK, RTL8192CU), 143 URTWN_DEV(REALTEK, RTL8188CU_0), 144 URTWN_DEV(SITECOMEU, RTL8188CU_1), 145 URTWN_DEV(SITECOMEU, RTL8188CU_2), 146 URTWN_DEV(SITECOMEU, RTL8192CU), 147 URTWN_DEV(TRENDNET, RTL8188CU), 148 URTWN_DEV(TRENDNET, RTL8192CU), 149 URTWN_DEV(ZYXEL, RTL8192CU), 150#undef URTWN_DEV 151}; 152 153static device_probe_t urtwn_match; 154static device_attach_t urtwn_attach; 155static device_detach_t urtwn_detach; 156 157static usb_callback_t urtwn_bulk_tx_callback; 158static usb_callback_t urtwn_bulk_rx_callback; 159 160static usb_error_t urtwn_do_request(struct urtwn_softc *sc, 161 struct usb_device_request *req, void *data); 162static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 163 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 164 const uint8_t [IEEE80211_ADDR_LEN], 165 const uint8_t [IEEE80211_ADDR_LEN]); 166static void urtwn_vap_delete(struct ieee80211vap *); 167static struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 168 int *); 169static struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *, 170 int *, int8_t *); 171static void urtwn_txeof(struct usb_xfer *, struct urtwn_data *); 172static int urtwn_alloc_list(struct urtwn_softc *, 173 struct urtwn_data[], int, int); 174static int urtwn_alloc_rx_list(struct urtwn_softc *); 175static int urtwn_alloc_tx_list(struct urtwn_softc *); 176static void urtwn_free_tx_list(struct urtwn_softc *); 177static void urtwn_free_rx_list(struct urtwn_softc *); 178static void urtwn_free_list(struct urtwn_softc *, 179 struct urtwn_data data[], int); 180static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 181static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 182static int urtwn_write_region_1(struct urtwn_softc *, uint16_t, 183 uint8_t *, int); 184static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 185static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 186static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 187static int urtwn_read_region_1(struct urtwn_softc *, uint16_t, 188 uint8_t *, int); 189static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 190static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 191static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 192static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 193 const void *, int); 194static void urtwn_rf_write(struct urtwn_softc *, int, uint8_t, 195 uint32_t); 196static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 197static int urtwn_llt_write(struct urtwn_softc *, uint32_t, 198 uint32_t); 199static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 200static void urtwn_efuse_read(struct urtwn_softc *); 201static int urtwn_read_chipid(struct urtwn_softc *); 202static void urtwn_read_rom(struct urtwn_softc *); 203static int urtwn_ra_init(struct urtwn_softc *); 204static void urtwn_tsf_sync_enable(struct urtwn_softc *); 205static void urtwn_set_led(struct urtwn_softc *, int, int); 206static int urtwn_newstate(struct ieee80211vap *, 207 enum ieee80211_state, int); 208static void urtwn_watchdog(void *); 209static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 210static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 211static int urtwn_tx_start(struct urtwn_softc *, 212 struct ieee80211_node *, struct mbuf *, 213 struct urtwn_data *); 214static void urtwn_start(struct ifnet *); 215static void urtwn_start_locked(struct ifnet *, 216 struct urtwn_softc *); 217static int urtwn_ioctl(struct ifnet *, u_long, caddr_t); 218static int urtwn_power_on(struct urtwn_softc *); 219static int urtwn_llt_init(struct urtwn_softc *); 220static void urtwn_fw_reset(struct urtwn_softc *); 221static int urtwn_fw_loadpage(struct urtwn_softc *, int, 222 const uint8_t *, int); 223static int urtwn_load_firmware(struct urtwn_softc *); 224static int urtwn_dma_init(struct urtwn_softc *); 225static void urtwn_mac_init(struct urtwn_softc *); 226static void urtwn_bb_init(struct urtwn_softc *); 227static void urtwn_rf_init(struct urtwn_softc *); 228static void urtwn_cam_init(struct urtwn_softc *); 229static void urtwn_pa_bias_init(struct urtwn_softc *); 230static void urtwn_rxfilter_init(struct urtwn_softc *); 231static void urtwn_edca_init(struct urtwn_softc *); 232static void urtwn_write_txpower(struct urtwn_softc *, int, 233 uint16_t[]); 234static void urtwn_get_txpower(struct urtwn_softc *, int, 235 struct ieee80211_channel *, 236 struct ieee80211_channel *, uint16_t[]); 237static void urtwn_set_txpower(struct urtwn_softc *, 238 struct ieee80211_channel *, 239 struct ieee80211_channel *); 240static void urtwn_scan_start(struct ieee80211com *); 241static void urtwn_scan_end(struct ieee80211com *); 242static void urtwn_set_channel(struct ieee80211com *); 243static void urtwn_set_chan(struct urtwn_softc *, 244 struct ieee80211_channel *, 245 struct ieee80211_channel *); 246static void urtwn_update_mcast(struct ifnet *); 247static void urtwn_iq_calib(struct urtwn_softc *); 248static void urtwn_lc_calib(struct urtwn_softc *); 249static void urtwn_init(void *); 250static void urtwn_init_locked(void *); 251static void urtwn_stop(struct ifnet *); 252static void urtwn_stop_locked(struct ifnet *); 253static void urtwn_abort_xfers(struct urtwn_softc *); 254static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 255 const struct ieee80211_bpf_params *); 256 257/* Aliases. */ 258#define urtwn_bb_write urtwn_write_4 259#define urtwn_bb_read urtwn_read_4 260 261static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 262 [URTWN_BULK_RX] = { 263 .type = UE_BULK, 264 .endpoint = UE_ADDR_ANY, 265 .direction = UE_DIR_IN, 266 .bufsize = URTWN_RXBUFSZ, 267 .flags = { 268 .pipe_bof = 1, 269 .short_xfer_ok = 1 270 }, 271 .callback = urtwn_bulk_rx_callback, 272 }, 273 [URTWN_BULK_TX_BE] = { 274 .type = UE_BULK, 275 .endpoint = 0x03, 276 .direction = UE_DIR_OUT, 277 .bufsize = URTWN_TXBUFSZ, 278 .flags = { 279 .ext_buffer = 1, 280 .pipe_bof = 1, 281 .force_short_xfer = 1 282 }, 283 .callback = urtwn_bulk_tx_callback, 284 .timeout = URTWN_TX_TIMEOUT, /* ms */ 285 }, 286 [URTWN_BULK_TX_BK] = { 287 .type = UE_BULK, 288 .endpoint = 0x03, 289 .direction = UE_DIR_OUT, 290 .bufsize = URTWN_TXBUFSZ, 291 .flags = { 292 .ext_buffer = 1, 293 .pipe_bof = 1, 294 .force_short_xfer = 1, 295 }, 296 .callback = urtwn_bulk_tx_callback, 297 .timeout = URTWN_TX_TIMEOUT, /* ms */ 298 }, 299 [URTWN_BULK_TX_VI] = { 300 .type = UE_BULK, 301 .endpoint = 0x02, 302 .direction = UE_DIR_OUT, 303 .bufsize = URTWN_TXBUFSZ, 304 .flags = { 305 .ext_buffer = 1, 306 .pipe_bof = 1, 307 .force_short_xfer = 1 308 }, 309 .callback = urtwn_bulk_tx_callback, 310 .timeout = URTWN_TX_TIMEOUT, /* ms */ 311 }, 312 [URTWN_BULK_TX_VO] = { 313 .type = UE_BULK, 314 .endpoint = 0x02, 315 .direction = UE_DIR_OUT, 316 .bufsize = URTWN_TXBUFSZ, 317 .flags = { 318 .ext_buffer = 1, 319 .pipe_bof = 1, 320 .force_short_xfer = 1 321 }, 322 .callback = urtwn_bulk_tx_callback, 323 .timeout = URTWN_TX_TIMEOUT, /* ms */ 324 }, 325}; 326 327static int 328urtwn_match(device_t self) 329{ 330 struct usb_attach_arg *uaa = device_get_ivars(self); 331 332 if (uaa->usb_mode != USB_MODE_HOST) 333 return (ENXIO); 334 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 335 return (ENXIO); 336 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 337 return (ENXIO); 338 339 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 340} 341 342static int 343urtwn_attach(device_t self) 344{ 345 struct usb_attach_arg *uaa = device_get_ivars(self); 346 struct urtwn_softc *sc = device_get_softc(self); 347 struct ifnet *ifp; 348 struct ieee80211com *ic; 349 uint8_t iface_index, bands; 350 int error; 351 352 device_set_usb_desc(self); 353 sc->sc_udev = uaa->device; 354 sc->sc_dev = self; 355 356 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 357 MTX_NETWORK_LOCK, MTX_DEF); 358 callout_init(&sc->sc_watchdog_ch, 0); 359 360 iface_index = URTWN_IFACE_INDEX; 361 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 362 urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 363 if (error) { 364 device_printf(self, "could not allocate USB transfers, " 365 "err=%s\n", usbd_errstr(error)); 366 goto detach; 367 } 368 369 URTWN_LOCK(sc); 370 371 error = urtwn_read_chipid(sc); 372 if (error) { 373 device_printf(sc->sc_dev, "unsupported test chip\n"); 374 URTWN_UNLOCK(sc); 375 goto detach; 376 } 377 378 /* Determine number of Tx/Rx chains. */ 379 if (sc->chip & URTWN_CHIP_92C) { 380 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 381 sc->nrxchains = 2; 382 } else { 383 sc->ntxchains = 1; 384 sc->nrxchains = 1; 385 } 386 urtwn_read_rom(sc); 387 388 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 389 (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 390 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 391 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 392 "8188CUS", sc->ntxchains, sc->nrxchains); 393 394 URTWN_UNLOCK(sc); 395 396 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 397 if (ifp == NULL) { 398 device_printf(sc->sc_dev, "can not if_alloc()\n"); 399 goto detach; 400 } 401 ic = ifp->if_l2com; 402 403 ifp->if_softc = sc; 404 if_initname(ifp, "urtwn", device_get_unit(sc->sc_dev)); 405 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 406 ifp->if_init = urtwn_init; 407 ifp->if_ioctl = urtwn_ioctl; 408 ifp->if_start = urtwn_start; 409 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 410 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 411 IFQ_SET_READY(&ifp->if_snd); 412 413 ic->ic_ifp = ifp; 414 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 415 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 416 417 /* set device capabilities */ 418 ic->ic_caps = 419 IEEE80211_C_STA /* station mode */ 420 | IEEE80211_C_MONITOR /* monitor mode */ 421 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 422 | IEEE80211_C_SHSLOT /* short slot time supported */ 423 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 424 | IEEE80211_C_WPA /* 802.11i */ 425 ; 426 427 bands = 0; 428 setbit(&bands, IEEE80211_MODE_11B); 429 setbit(&bands, IEEE80211_MODE_11G); 430 ieee80211_init_channels(ic, NULL, &bands); 431 432 ieee80211_ifattach(ic, sc->sc_bssid); 433 ic->ic_raw_xmit = urtwn_raw_xmit; 434 ic->ic_scan_start = urtwn_scan_start; 435 ic->ic_scan_end = urtwn_scan_end; 436 ic->ic_set_channel = urtwn_set_channel; 437 438 ic->ic_vap_create = urtwn_vap_create; 439 ic->ic_vap_delete = urtwn_vap_delete; 440 ic->ic_update_mcast = urtwn_update_mcast; 441 442 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 443 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 444 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 445 URTWN_RX_RADIOTAP_PRESENT); 446 447 if (bootverbose) 448 ieee80211_announce(ic); 449 450 return (0); 451 452detach: 453 urtwn_detach(self); 454 return (ENXIO); /* failure */ 455} 456 457static int 458urtwn_detach(device_t self) 459{ 460 struct urtwn_softc *sc = device_get_softc(self); 461 struct ifnet *ifp = sc->sc_ifp; 462 struct ieee80211com *ic = ifp->if_l2com; 463 unsigned int x; 464 465 /* Prevent further ioctls. */ 466 URTWN_LOCK(sc); 467 sc->sc_flags |= URTWN_DETACHED; 468 URTWN_UNLOCK(sc); 469 470 urtwn_stop(ifp); 471 472 callout_drain(&sc->sc_watchdog_ch); 473 474 /* Prevent further allocations from RX/TX data lists. */ 475 URTWN_LOCK(sc); 476 STAILQ_INIT(&sc->sc_tx_active); 477 STAILQ_INIT(&sc->sc_tx_inactive); 478 STAILQ_INIT(&sc->sc_tx_pending); 479 480 STAILQ_INIT(&sc->sc_rx_active); 481 STAILQ_INIT(&sc->sc_rx_inactive); 482 URTWN_UNLOCK(sc); 483 484 /* drain USB transfers */ 485 for (x = 0; x != URTWN_N_TRANSFER; x++) 486 usbd_transfer_drain(sc->sc_xfer[x]); 487 488 /* Free data buffers. */ 489 URTWN_LOCK(sc); 490 urtwn_free_tx_list(sc); 491 urtwn_free_rx_list(sc); 492 URTWN_UNLOCK(sc); 493 494 /* stop all USB transfers */ 495 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 496 ieee80211_ifdetach(ic); 497 498 if_free(ifp); 499 mtx_destroy(&sc->sc_mtx); 500 501 return (0); 502} 503 504static void 505urtwn_free_tx_list(struct urtwn_softc *sc) 506{ 507 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 508} 509 510static void 511urtwn_free_rx_list(struct urtwn_softc *sc) 512{ 513 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 514} 515 516static void 517urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 518{ 519 int i; 520 521 for (i = 0; i < ndata; i++) { 522 struct urtwn_data *dp = &data[i]; 523 524 if (dp->buf != NULL) { 525 free(dp->buf, M_USBDEV); 526 dp->buf = NULL; 527 } 528 if (dp->ni != NULL) { 529 ieee80211_free_node(dp->ni); 530 dp->ni = NULL; 531 } 532 } 533} 534 535static usb_error_t 536urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 537 void *data) 538{ 539 usb_error_t err; 540 int ntries = 10; 541 542 URTWN_ASSERT_LOCKED(sc); 543 544 while (ntries--) { 545 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 546 req, data, 0, NULL, 250 /* ms */); 547 if (err == 0) 548 break; 549 550 DPRINTFN(1, "Control request failed, %s (retrying)\n", 551 usbd_errstr(err)); 552 usb_pause_mtx(&sc->sc_mtx, hz / 100); 553 } 554 return (err); 555} 556 557static struct ieee80211vap * 558urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 559 enum ieee80211_opmode opmode, int flags, 560 const uint8_t bssid[IEEE80211_ADDR_LEN], 561 const uint8_t mac[IEEE80211_ADDR_LEN]) 562{ 563 struct urtwn_vap *uvp; 564 struct ieee80211vap *vap; 565 566 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 567 return (NULL); 568 569 uvp = (struct urtwn_vap *) malloc(sizeof(struct urtwn_vap), 570 M_80211_VAP, M_NOWAIT | M_ZERO); 571 if (uvp == NULL) 572 return (NULL); 573 vap = &uvp->vap; 574 /* enable s/w bmiss handling for sta mode */ 575 576 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 577 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac) != 0) { 578 /* out of memory */ 579 free(uvp, M_80211_VAP); 580 return (NULL); 581 } 582 583 /* override state transition machine */ 584 uvp->newstate = vap->iv_newstate; 585 vap->iv_newstate = urtwn_newstate; 586 587 /* complete setup */ 588 ieee80211_vap_attach(vap, ieee80211_media_change, 589 ieee80211_media_status); 590 ic->ic_opmode = opmode; 591 return (vap); 592} 593 594static void 595urtwn_vap_delete(struct ieee80211vap *vap) 596{ 597 struct urtwn_vap *uvp = URTWN_VAP(vap); 598 599 ieee80211_vap_detach(vap); 600 free(uvp, M_80211_VAP); 601} 602 603static struct mbuf * 604urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 605{ 606 struct ifnet *ifp = sc->sc_ifp; 607 struct ieee80211com *ic = ifp->if_l2com; 608 struct ieee80211_frame *wh; 609 struct mbuf *m; 610 struct r92c_rx_stat *stat; 611 uint32_t rxdw0, rxdw3; 612 uint8_t rate; 613 int8_t rssi = 0; 614 int infosz; 615 616 /* 617 * don't pass packets to the ieee80211 framework if the driver isn't 618 * RUNNING. 619 */ 620 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 621 return (NULL); 622 623 stat = (struct r92c_rx_stat *)buf; 624 rxdw0 = le32toh(stat->rxdw0); 625 rxdw3 = le32toh(stat->rxdw3); 626 627 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 628 /* 629 * This should not happen since we setup our Rx filter 630 * to not receive these frames. 631 */ 632 ifp->if_ierrors++; 633 return (NULL); 634 } 635 636 rate = MS(rxdw3, R92C_RXDW3_RATE); 637 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 638 639 /* Get RSSI from PHY status descriptor if present. */ 640 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 641 rssi = urtwn_get_rssi(sc, rate, &stat[1]); 642 /* Update our average RSSI. */ 643 urtwn_update_avgrssi(sc, rate, rssi); 644 /* 645 * Convert the RSSI to a range that will be accepted 646 * by net80211. 647 */ 648 rssi = URTWN_RSSI(rssi); 649 } 650 651 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 652 if (m == NULL) { 653 device_printf(sc->sc_dev, "could not create RX mbuf\n"); 654 return (NULL); 655 } 656 657 /* Finalize mbuf. */ 658 m->m_pkthdr.rcvif = ifp; 659 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 660 memcpy(mtod(m, uint8_t *), wh, pktlen); 661 m->m_pkthdr.len = m->m_len = pktlen; 662 663 if (ieee80211_radiotap_active(ic)) { 664 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 665 666 tap->wr_flags = 0; 667 /* Map HW rate index to 802.11 rate. */ 668 if (!(rxdw3 & R92C_RXDW3_HT)) { 669 switch (rate) { 670 /* CCK. */ 671 case 0: tap->wr_rate = 2; break; 672 case 1: tap->wr_rate = 4; break; 673 case 2: tap->wr_rate = 11; break; 674 case 3: tap->wr_rate = 22; break; 675 /* OFDM. */ 676 case 4: tap->wr_rate = 12; break; 677 case 5: tap->wr_rate = 18; break; 678 case 6: tap->wr_rate = 24; break; 679 case 7: tap->wr_rate = 36; break; 680 case 8: tap->wr_rate = 48; break; 681 case 9: tap->wr_rate = 72; break; 682 case 10: tap->wr_rate = 96; break; 683 case 11: tap->wr_rate = 108; break; 684 } 685 } else if (rate >= 12) { /* MCS0~15. */ 686 /* Bit 7 set means HT MCS instead of rate. */ 687 tap->wr_rate = 0x80 | (rate - 12); 688 } 689 tap->wr_dbm_antsignal = rssi; 690 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 691 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 692 } 693 694 *rssi_p = rssi; 695 696 return (m); 697} 698 699static struct mbuf * 700urtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 701 int8_t *nf) 702{ 703 struct urtwn_softc *sc = data->sc; 704 struct ifnet *ifp = sc->sc_ifp; 705 struct r92c_rx_stat *stat; 706 struct mbuf *m, *m0 = NULL, *prevm = NULL; 707 uint32_t rxdw0; 708 uint8_t *buf; 709 int len, totlen, pktlen, infosz, npkts; 710 711 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 712 713 if (len < sizeof(*stat)) { 714 ifp->if_ierrors++; 715 return (NULL); 716 } 717 718 buf = data->buf; 719 /* Get the number of encapsulated frames. */ 720 stat = (struct r92c_rx_stat *)buf; 721 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 722 DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 723 724 /* Process all of them. */ 725 while (npkts-- > 0) { 726 if (len < sizeof(*stat)) 727 break; 728 stat = (struct r92c_rx_stat *)buf; 729 rxdw0 = le32toh(stat->rxdw0); 730 731 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 732 if (pktlen == 0) 733 break; 734 735 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 736 737 /* Make sure everything fits in xfer. */ 738 totlen = sizeof(*stat) + infosz + pktlen; 739 if (totlen > len) 740 break; 741 742 m = urtwn_rx_frame(sc, buf, pktlen, rssi); 743 if (m0 == NULL) 744 m0 = m; 745 if (prevm == NULL) 746 prevm = m; 747 else { 748 prevm->m_next = m; 749 prevm = m; 750 } 751 752 /* Next chunk is 128-byte aligned. */ 753 totlen = (totlen + 127) & ~127; 754 buf += totlen; 755 len -= totlen; 756 } 757 758 return (m0); 759} 760 761static void 762urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 763{ 764 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 765 struct ifnet *ifp = sc->sc_ifp; 766 struct ieee80211com *ic = ifp->if_l2com; 767 struct ieee80211_frame *wh; 768 struct ieee80211_node *ni; 769 struct mbuf *m = NULL, *next; 770 struct urtwn_data *data; 771 int8_t nf; 772 int rssi = 1; 773 774 URTWN_ASSERT_LOCKED(sc); 775 776 switch (USB_GET_STATE(xfer)) { 777 case USB_ST_TRANSFERRED: 778 data = STAILQ_FIRST(&sc->sc_rx_active); 779 if (data == NULL) 780 goto tr_setup; 781 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 782 m = urtwn_rxeof(xfer, data, &rssi, &nf); 783 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 784 /* FALLTHROUGH */ 785 case USB_ST_SETUP: 786tr_setup: 787 data = STAILQ_FIRST(&sc->sc_rx_inactive); 788 if (data == NULL) { 789 KASSERT(m == NULL, ("mbuf isn't NULL")); 790 return; 791 } 792 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 793 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 794 usbd_xfer_set_frame_data(xfer, 0, data->buf, 795 usbd_xfer_max_len(xfer)); 796 usbd_transfer_submit(xfer); 797 798 /* 799 * To avoid LOR we should unlock our private mutex here to call 800 * ieee80211_input() because here is at the end of a USB 801 * callback and safe to unlock. 802 */ 803 URTWN_UNLOCK(sc); 804 while (m != NULL) { 805 next = m->m_next; 806 m->m_next = NULL; 807 wh = mtod(m, struct ieee80211_frame *); 808 ni = ieee80211_find_rxnode(ic, 809 (struct ieee80211_frame_min *)wh); 810 nf = URTWN_NOISE_FLOOR; 811 if (ni != NULL) { 812 (void)ieee80211_input(ni, m, rssi, nf); 813 ieee80211_free_node(ni); 814 } else 815 (void)ieee80211_input_all(ic, m, rssi, nf); 816 m = next; 817 } 818 URTWN_LOCK(sc); 819 break; 820 default: 821 /* needs it to the inactive queue due to a error. */ 822 data = STAILQ_FIRST(&sc->sc_rx_active); 823 if (data != NULL) { 824 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 825 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 826 } 827 if (error != USB_ERR_CANCELLED) { 828 usbd_xfer_set_stall(xfer); 829 ifp->if_ierrors++; 830 goto tr_setup; 831 } 832 break; 833 } 834} 835 836static void 837urtwn_txeof(struct usb_xfer *xfer, struct urtwn_data *data) 838{ 839 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 840 struct ifnet *ifp = sc->sc_ifp; 841 struct mbuf *m; 842 843 URTWN_ASSERT_LOCKED(sc); 844 845 /* 846 * Do any tx complete callback. Note this must be done before releasing 847 * the node reference. 848 */ 849 if (data->m) { 850 m = data->m; 851 if (m->m_flags & M_TXCB) { 852 /* XXX status? */ 853 ieee80211_process_callback(data->ni, m, 0); 854 } 855 m_freem(m); 856 data->m = NULL; 857 } 858 if (data->ni) { 859 ieee80211_free_node(data->ni); 860 data->ni = NULL; 861 } 862 sc->sc_txtimer = 0; 863 ifp->if_opackets++; 864 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 865} 866 867static void 868urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 869{ 870 struct urtwn_softc *sc = usbd_xfer_softc(xfer); 871 struct ifnet *ifp = sc->sc_ifp; 872 struct urtwn_data *data; 873 874 URTWN_ASSERT_LOCKED(sc); 875 876 switch (USB_GET_STATE(xfer)){ 877 case USB_ST_TRANSFERRED: 878 data = STAILQ_FIRST(&sc->sc_tx_active); 879 if (data == NULL) 880 goto tr_setup; 881 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 882 urtwn_txeof(xfer, data); 883 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 884 /* FALLTHROUGH */ 885 case USB_ST_SETUP: 886tr_setup: 887 data = STAILQ_FIRST(&sc->sc_tx_pending); 888 if (data == NULL) { 889 DPRINTF("%s: empty pending queue\n", __func__); 890 return; 891 } 892 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 893 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 894 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 895 usbd_transfer_submit(xfer); 896 urtwn_start_locked(ifp, sc); 897 break; 898 default: 899 data = STAILQ_FIRST(&sc->sc_tx_active); 900 if (data == NULL) 901 goto tr_setup; 902 if (data->ni != NULL) { 903 ieee80211_free_node(data->ni); 904 data->ni = NULL; 905 ifp->if_oerrors++; 906 } 907 if (error != USB_ERR_CANCELLED) { 908 usbd_xfer_set_stall(xfer); 909 goto tr_setup; 910 } 911 break; 912 } 913} 914 915static struct urtwn_data * 916_urtwn_getbuf(struct urtwn_softc *sc) 917{ 918 struct urtwn_data *bf; 919 920 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 921 if (bf != NULL) 922 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 923 else 924 bf = NULL; 925 if (bf == NULL) 926 DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 927 return (bf); 928} 929 930static struct urtwn_data * 931urtwn_getbuf(struct urtwn_softc *sc) 932{ 933 struct urtwn_data *bf; 934 935 URTWN_ASSERT_LOCKED(sc); 936 937 bf = _urtwn_getbuf(sc); 938 if (bf == NULL) { 939 struct ifnet *ifp = sc->sc_ifp; 940 DPRINTF("%s: stop queue\n", __func__); 941 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 942 } 943 return (bf); 944} 945 946static int 947urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 948 int len) 949{ 950 usb_device_request_t req; 951 952 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 953 req.bRequest = R92C_REQ_REGS; 954 USETW(req.wValue, addr); 955 USETW(req.wIndex, 0); 956 USETW(req.wLength, len); 957 return (urtwn_do_request(sc, &req, buf)); 958} 959 960static void 961urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 962{ 963 urtwn_write_region_1(sc, addr, &val, 1); 964} 965 966 967static void 968urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 969{ 970 val = htole16(val); 971 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 972} 973 974static void 975urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 976{ 977 val = htole32(val); 978 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 979} 980 981static int 982urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 983 int len) 984{ 985 usb_device_request_t req; 986 987 req.bmRequestType = UT_READ_VENDOR_DEVICE; 988 req.bRequest = R92C_REQ_REGS; 989 USETW(req.wValue, addr); 990 USETW(req.wIndex, 0); 991 USETW(req.wLength, len); 992 return (urtwn_do_request(sc, &req, buf)); 993} 994 995static uint8_t 996urtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 997{ 998 uint8_t val; 999 1000 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1001 return (0xff); 1002 return (val); 1003} 1004 1005static uint16_t 1006urtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1007{ 1008 uint16_t val; 1009 1010 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1011 return (0xffff); 1012 return (le16toh(val)); 1013} 1014 1015static uint32_t 1016urtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1017{ 1018 uint32_t val; 1019 1020 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1021 return (0xffffffff); 1022 return (le32toh(val)); 1023} 1024 1025static int 1026urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1027{ 1028 struct r92c_fw_cmd cmd; 1029 int ntries; 1030 1031 /* Wait for current FW box to be empty. */ 1032 for (ntries = 0; ntries < 100; ntries++) { 1033 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1034 break; 1035 DELAY(1); 1036 } 1037 if (ntries == 100) { 1038 device_printf(sc->sc_dev, 1039 "could not send firmware command\n"); 1040 return (ETIMEDOUT); 1041 } 1042 memset(&cmd, 0, sizeof(cmd)); 1043 cmd.id = id; 1044 if (len > 3) 1045 cmd.id |= R92C_CMD_FLAG_EXT; 1046 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1047 memcpy(cmd.msg, buf, len); 1048 1049 /* Write the first word last since that will trigger the FW. */ 1050 urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1051 (uint8_t *)&cmd + 4, 2); 1052 urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1053 (uint8_t *)&cmd + 0, 4); 1054 1055 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1056 return (0); 1057} 1058 1059static void 1060urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1061{ 1062 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1063 SM(R92C_LSSI_PARAM_ADDR, addr) | 1064 SM(R92C_LSSI_PARAM_DATA, val)); 1065} 1066 1067static uint32_t 1068urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1069{ 1070 uint32_t reg[R92C_MAX_CHAINS], val; 1071 1072 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1073 if (chain != 0) 1074 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1075 1076 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1077 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1078 DELAY(1000); 1079 1080 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1081 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1082 R92C_HSSI_PARAM2_READ_EDGE); 1083 DELAY(1000); 1084 1085 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1086 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1087 DELAY(1000); 1088 1089 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1090 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1091 else 1092 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1093 return (MS(val, R92C_LSSI_READBACK_DATA)); 1094} 1095 1096static int 1097urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1098{ 1099 int ntries; 1100 1101 urtwn_write_4(sc, R92C_LLT_INIT, 1102 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1103 SM(R92C_LLT_INIT_ADDR, addr) | 1104 SM(R92C_LLT_INIT_DATA, data)); 1105 /* Wait for write operation to complete. */ 1106 for (ntries = 0; ntries < 20; ntries++) { 1107 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1108 R92C_LLT_INIT_OP_NO_ACTIVE) 1109 return (0); 1110 DELAY(5); 1111 } 1112 return (ETIMEDOUT); 1113} 1114 1115static uint8_t 1116urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1117{ 1118 uint32_t reg; 1119 int ntries; 1120 1121 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1122 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1123 reg &= ~R92C_EFUSE_CTRL_VALID; 1124 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1125 /* Wait for read operation to complete. */ 1126 for (ntries = 0; ntries < 100; ntries++) { 1127 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1128 if (reg & R92C_EFUSE_CTRL_VALID) 1129 return (MS(reg, R92C_EFUSE_CTRL_DATA)); 1130 DELAY(5); 1131 } 1132 device_printf(sc->sc_dev, 1133 "could not read efuse byte at address 0x%x\n", addr); 1134 return (0xff); 1135} 1136 1137static void 1138urtwn_efuse_read(struct urtwn_softc *sc) 1139{ 1140 uint8_t *rom = (uint8_t *)&sc->rom; 1141 uint16_t addr = 0; 1142 uint32_t reg; 1143 uint8_t off, msk; 1144 int i; 1145 1146 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1147 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1148 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1149 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1150 } 1151 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1152 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1153 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1154 reg | R92C_SYS_FUNC_EN_ELDR); 1155 } 1156 reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1157 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1158 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1159 urtwn_write_2(sc, R92C_SYS_CLKR, 1160 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1161 } 1162 memset(&sc->rom, 0xff, sizeof(sc->rom)); 1163 while (addr < 512) { 1164 reg = urtwn_efuse_read_1(sc, addr); 1165 if (reg == 0xff) 1166 break; 1167 addr++; 1168 off = reg >> 4; 1169 msk = reg & 0xf; 1170 for (i = 0; i < 4; i++) { 1171 if (msk & (1 << i)) 1172 continue; 1173 rom[off * 8 + i * 2 + 0] = 1174 urtwn_efuse_read_1(sc, addr); 1175 addr++; 1176 rom[off * 8 + i * 2 + 1] = 1177 urtwn_efuse_read_1(sc, addr); 1178 addr++; 1179 } 1180 } 1181#ifdef URTWN_DEBUG 1182 if (urtwn_debug >= 2) { 1183 /* Dump ROM content. */ 1184 printf("\n"); 1185 for (i = 0; i < sizeof(sc->rom); i++) 1186 printf("%02x:", rom[i]); 1187 printf("\n"); 1188 } 1189#endif 1190} 1191 1192static int 1193urtwn_read_chipid(struct urtwn_softc *sc) 1194{ 1195 uint32_t reg; 1196 1197 reg = urtwn_read_4(sc, R92C_SYS_CFG); 1198 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1199 return (EIO); 1200 1201 if (reg & R92C_SYS_CFG_TYPE_92C) { 1202 sc->chip |= URTWN_CHIP_92C; 1203 /* Check if it is a castrated 8192C. */ 1204 if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1205 R92C_HPON_FSM_CHIP_BONDING_ID) == 1206 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1207 sc->chip |= URTWN_CHIP_92C_1T2R; 1208 } 1209 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1210 sc->chip |= URTWN_CHIP_UMC; 1211 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1212 sc->chip |= URTWN_CHIP_UMC_A_CUT; 1213 } 1214 return (0); 1215} 1216 1217static void 1218urtwn_read_rom(struct urtwn_softc *sc) 1219{ 1220 struct r92c_rom *rom = &sc->rom; 1221 1222 /* Read full ROM image. */ 1223 urtwn_efuse_read(sc); 1224 1225 /* XXX Weird but this is what the vendor driver does. */ 1226 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1227 DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1228 1229 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1230 1231 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1232 DPRINTF("regulatory type=%d\n", sc->regulatory); 1233 1234 IEEE80211_ADDR_COPY(sc->sc_bssid, rom->macaddr); 1235} 1236 1237/* 1238 * Initialize rate adaptation in firmware. 1239 */ 1240static int 1241urtwn_ra_init(struct urtwn_softc *sc) 1242{ 1243 static const uint8_t map[] = 1244 { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 }; 1245 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 1246 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1247 struct ieee80211_node *ni; 1248 struct ieee80211_rateset *rs; 1249 struct r92c_fw_cmd_macid_cfg cmd; 1250 uint32_t rates, basicrates; 1251 uint8_t mode; 1252 int maxrate, maxbasicrate, error, i, j; 1253 1254 ni = ieee80211_ref_node(vap->iv_bss); 1255 rs = &ni->ni_rates; 1256 1257 /* Get normal and basic rates mask. */ 1258 rates = basicrates = 0; 1259 maxrate = maxbasicrate = 0; 1260 for (i = 0; i < rs->rs_nrates; i++) { 1261 /* Convert 802.11 rate to HW rate index. */ 1262 for (j = 0; j < nitems(map); j++) 1263 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 1264 break; 1265 if (j == nitems(map)) /* Unknown rate, skip. */ 1266 continue; 1267 rates |= 1 << j; 1268 if (j > maxrate) 1269 maxrate = j; 1270 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1271 basicrates |= 1 << j; 1272 if (j > maxbasicrate) 1273 maxbasicrate = j; 1274 } 1275 } 1276 if (ic->ic_curmode == IEEE80211_MODE_11B) 1277 mode = R92C_RAID_11B; 1278 else 1279 mode = R92C_RAID_11BG; 1280 DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1281 mode, rates, basicrates); 1282 1283 /* Set rates mask for group addressed frames. */ 1284 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1285 cmd.mask = htole32(mode << 28 | basicrates); 1286 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1287 if (error != 0) { 1288 ieee80211_free_node(ni); 1289 device_printf(sc->sc_dev, 1290 "could not add broadcast station\n"); 1291 return (error); 1292 } 1293 /* Set initial MRR rate. */ 1294 DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1295 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1296 maxbasicrate); 1297 1298 /* Set rates mask for unicast frames. */ 1299 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1300 cmd.mask = htole32(mode << 28 | rates); 1301 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1302 if (error != 0) { 1303 ieee80211_free_node(ni); 1304 device_printf(sc->sc_dev, "could not add BSS station\n"); 1305 return (error); 1306 } 1307 /* Set initial MRR rate. */ 1308 DPRINTF("maxrate=%d\n", maxrate); 1309 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1310 maxrate); 1311 1312 /* Indicate highest supported rate. */ 1313 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1314 ieee80211_free_node(ni); 1315 1316 return (0); 1317} 1318 1319void 1320urtwn_tsf_sync_enable(struct urtwn_softc *sc) 1321{ 1322 struct ifnet *ifp = sc->sc_ifp; 1323 struct ieee80211com *ic = ifp->if_l2com; 1324 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1325 struct ieee80211_node *ni = vap->iv_bss; 1326 1327 uint64_t tsf; 1328 1329 /* Enable TSF synchronization. */ 1330 urtwn_write_1(sc, R92C_BCN_CTRL, 1331 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1332 1333 urtwn_write_1(sc, R92C_BCN_CTRL, 1334 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1335 1336 /* Set initial TSF. */ 1337 memcpy(&tsf, ni->ni_tstamp.data, 8); 1338 tsf = le64toh(tsf); 1339 tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU)); 1340 tsf -= IEEE80211_DUR_TU; 1341 urtwn_write_4(sc, R92C_TSFTR + 0, tsf); 1342 urtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32); 1343 1344 urtwn_write_1(sc, R92C_BCN_CTRL, 1345 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1346} 1347 1348static void 1349urtwn_set_led(struct urtwn_softc *sc, int led, int on) 1350{ 1351 uint8_t reg; 1352 1353 if (led == URTWN_LED_LINK) { 1354 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1355 if (!on) 1356 reg |= R92C_LEDCFG0_DIS; 1357 urtwn_write_1(sc, R92C_LEDCFG0, reg); 1358 sc->ledlink = on; /* Save LED state. */ 1359 } 1360} 1361 1362static int 1363urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1364{ 1365 struct urtwn_vap *uvp = URTWN_VAP(vap); 1366 struct ieee80211com *ic = vap->iv_ic; 1367 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1368 struct ieee80211_node *ni; 1369 enum ieee80211_state ostate; 1370 uint32_t reg; 1371 1372 ostate = vap->iv_state; 1373 DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 1374 ieee80211_state_name[nstate]); 1375 1376 IEEE80211_UNLOCK(ic); 1377 URTWN_LOCK(sc); 1378 callout_stop(&sc->sc_watchdog_ch); 1379 1380 if (ostate == IEEE80211_S_RUN) { 1381 /* Turn link LED off. */ 1382 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1383 1384 /* Set media status to 'No Link'. */ 1385 reg = urtwn_read_4(sc, R92C_CR); 1386 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK); 1387 urtwn_write_4(sc, R92C_CR, reg); 1388 1389 /* Stop Rx of data frames. */ 1390 urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1391 1392 /* Rest TSF. */ 1393 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1394 1395 /* Disable TSF synchronization. */ 1396 urtwn_write_1(sc, R92C_BCN_CTRL, 1397 urtwn_read_1(sc, R92C_BCN_CTRL) | 1398 R92C_BCN_CTRL_DIS_TSF_UDT0); 1399 1400 /* Reset EDCA parameters. */ 1401 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1402 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1403 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1404 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1405 } 1406 1407 switch (nstate) { 1408 case IEEE80211_S_INIT: 1409 /* Turn link LED off. */ 1410 urtwn_set_led(sc, URTWN_LED_LINK, 0); 1411 break; 1412 case IEEE80211_S_SCAN: 1413 if (ostate != IEEE80211_S_SCAN) { 1414 /* Allow Rx from any BSSID. */ 1415 urtwn_write_4(sc, R92C_RCR, 1416 urtwn_read_4(sc, R92C_RCR) & 1417 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1418 1419 /* Set gain for scanning. */ 1420 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1421 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1422 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1423 1424 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1425 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1426 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1427 } 1428 1429 /* Make link LED blink during scan. */ 1430 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 1431 1432 /* Pause AC Tx queues. */ 1433 urtwn_write_1(sc, R92C_TXPAUSE, 1434 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1435 1436 urtwn_set_chan(sc, ic->ic_curchan, NULL); 1437 break; 1438 case IEEE80211_S_AUTH: 1439 /* Set initial gain under link. */ 1440 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1441 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1442 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1443 1444 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1445 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1446 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1447 1448 urtwn_set_chan(sc, ic->ic_curchan, NULL); 1449 break; 1450 case IEEE80211_S_RUN: 1451 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1452 /* Enable Rx of data frames. */ 1453 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1454 1455 /* Turn link LED on. */ 1456 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1457 break; 1458 } 1459 1460 ni = ieee80211_ref_node(vap->iv_bss); 1461 /* Set media status to 'Associated'. */ 1462 reg = urtwn_read_4(sc, R92C_CR); 1463 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 1464 urtwn_write_4(sc, R92C_CR, reg); 1465 1466 /* Set BSSID. */ 1467 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1468 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1469 1470 if (ic->ic_curmode == IEEE80211_MODE_11B) 1471 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1472 else /* 802.11b/g */ 1473 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1474 1475 /* Enable Rx of data frames. */ 1476 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1477 1478 /* Flush all AC queues. */ 1479 urtwn_write_1(sc, R92C_TXPAUSE, 0); 1480 1481 /* Set beacon interval. */ 1482 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1483 1484 /* Allow Rx from our BSSID only. */ 1485 urtwn_write_4(sc, R92C_RCR, 1486 urtwn_read_4(sc, R92C_RCR) | 1487 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1488 1489 /* Enable TSF synchronization. */ 1490 urtwn_tsf_sync_enable(sc); 1491 1492 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1493 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1494 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1495 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1496 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1497 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1498 1499 /* Intialize rate adaptation. */ 1500 urtwn_ra_init(sc); 1501 /* Turn link LED on. */ 1502 urtwn_set_led(sc, URTWN_LED_LINK, 1); 1503 1504 sc->avg_pwdb = -1; /* Reset average RSSI. */ 1505 /* Reset temperature calibration state machine. */ 1506 sc->thcal_state = 0; 1507 sc->thcal_lctemp = 0; 1508 ieee80211_free_node(ni); 1509 break; 1510 default: 1511 break; 1512 } 1513 URTWN_UNLOCK(sc); 1514 IEEE80211_LOCK(ic); 1515 return(uvp->newstate(vap, nstate, arg)); 1516} 1517 1518static void 1519urtwn_watchdog(void *arg) 1520{ 1521 struct urtwn_softc *sc = arg; 1522 struct ifnet *ifp = sc->sc_ifp; 1523 1524 if (sc->sc_txtimer > 0) { 1525 if (--sc->sc_txtimer == 0) { 1526 device_printf(sc->sc_dev, "device timeout\n"); 1527 ifp->if_oerrors++; 1528 return; 1529 } 1530 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1531 } 1532} 1533 1534static void 1535urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1536{ 1537 int pwdb; 1538 1539 /* Convert antenna signal to percentage. */ 1540 if (rssi <= -100 || rssi >= 20) 1541 pwdb = 0; 1542 else if (rssi >= 0) 1543 pwdb = 100; 1544 else 1545 pwdb = 100 + rssi; 1546 if (rate <= 3) { 1547 /* CCK gain is smaller than OFDM/MCS gain. */ 1548 pwdb += 6; 1549 if (pwdb > 100) 1550 pwdb = 100; 1551 if (pwdb <= 14) 1552 pwdb -= 4; 1553 else if (pwdb <= 26) 1554 pwdb -= 8; 1555 else if (pwdb <= 34) 1556 pwdb -= 6; 1557 else if (pwdb <= 42) 1558 pwdb -= 2; 1559 } 1560 if (sc->avg_pwdb == -1) /* Init. */ 1561 sc->avg_pwdb = pwdb; 1562 else if (sc->avg_pwdb < pwdb) 1563 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1564 else 1565 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1566 DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 1567} 1568 1569static int8_t 1570urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1571{ 1572 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1573 struct r92c_rx_phystat *phy; 1574 struct r92c_rx_cck *cck; 1575 uint8_t rpt; 1576 int8_t rssi; 1577 1578 if (rate <= 3) { 1579 cck = (struct r92c_rx_cck *)physt; 1580 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 1581 rpt = (cck->agc_rpt >> 5) & 0x3; 1582 rssi = (cck->agc_rpt & 0x1f) << 1; 1583 } else { 1584 rpt = (cck->agc_rpt >> 6) & 0x3; 1585 rssi = cck->agc_rpt & 0x3e; 1586 } 1587 rssi = cckoff[rpt] - rssi; 1588 } else { /* OFDM/HT. */ 1589 phy = (struct r92c_rx_phystat *)physt; 1590 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1591 } 1592 return (rssi); 1593} 1594 1595static int 1596urtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni, 1597 struct mbuf *m0, struct urtwn_data *data) 1598{ 1599 struct ifnet *ifp = sc->sc_ifp; 1600 struct ieee80211_frame *wh; 1601 struct ieee80211_key *k; 1602 struct ieee80211com *ic = ifp->if_l2com; 1603 struct ieee80211vap *vap = ni->ni_vap; 1604 struct usb_xfer *xfer; 1605 struct r92c_tx_desc *txd; 1606 uint8_t raid, type; 1607 uint16_t sum; 1608 int i, hasqos, xferlen; 1609 struct usb_xfer *urtwn_pipes[4] = { 1610 sc->sc_xfer[URTWN_BULK_TX_BE], 1611 sc->sc_xfer[URTWN_BULK_TX_BK], 1612 sc->sc_xfer[URTWN_BULK_TX_VI], 1613 sc->sc_xfer[URTWN_BULK_TX_VO] 1614 }; 1615 1616 URTWN_ASSERT_LOCKED(sc); 1617 1618 /* 1619 * Software crypto. 1620 */ 1621 wh = mtod(m0, struct ieee80211_frame *); 1622 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1623 k = ieee80211_crypto_encap(ni, m0); 1624 if (k == NULL) { 1625 device_printf(sc->sc_dev, 1626 "ieee80211_crypto_encap returns NULL.\n"); 1627 /* XXX we don't expect the fragmented frames */ 1628 m_freem(m0); 1629 return (ENOBUFS); 1630 } 1631 1632 /* in case packet header moved, reset pointer */ 1633 wh = mtod(m0, struct ieee80211_frame *); 1634 } 1635 1636 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 1637 case IEEE80211_FC0_TYPE_CTL: 1638 case IEEE80211_FC0_TYPE_MGT: 1639 xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 1640 break; 1641 default: 1642 KASSERT(M_WME_GETAC(m0) < 4, 1643 ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1644 xfer = urtwn_pipes[M_WME_GETAC(m0)]; 1645 break; 1646 } 1647 1648 hasqos = 0; 1649 1650 /* Fill Tx descriptor. */ 1651 txd = (struct r92c_tx_desc *)data->buf; 1652 memset(txd, 0, sizeof(*txd)); 1653 1654 txd->txdw0 |= htole32( 1655 SM(R92C_TXDW0_PKTLEN, m0->m_pkthdr.len) | 1656 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1657 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1658 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1659 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1660 1661 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1662 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1663 type == IEEE80211_FC0_TYPE_DATA) { 1664 if (ic->ic_curmode == IEEE80211_MODE_11B) 1665 raid = R92C_RAID_11B; 1666 else 1667 raid = R92C_RAID_11BG; 1668 txd->txdw1 |= htole32( 1669 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 1670 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1671 SM(R92C_TXDW1_RAID, raid) | 1672 R92C_TXDW1_AGGBK); 1673 1674 if (ic->ic_flags & IEEE80211_F_USEPROT) { 1675 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1676 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1677 R92C_TXDW4_HWRTSEN); 1678 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1679 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1680 R92C_TXDW4_HWRTSEN); 1681 } 1682 } 1683 /* Send RTS at OFDM24. */ 1684 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1685 txd->txdw5 |= htole32(0x0001ff00); 1686 /* Send data at OFDM54. */ 1687 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1688 } else { 1689 txd->txdw1 |= htole32( 1690 SM(R92C_TXDW1_MACID, 0) | 1691 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1692 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1693 1694 /* Force CCK1. */ 1695 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1696 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1697 } 1698 /* Set sequence number (already little endian). */ 1699 txd->txdseq |= *(uint16_t *)wh->i_seq; 1700 1701 if (!hasqos) { 1702 /* Use HW sequence numbering for non-QoS frames. */ 1703 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1704 txd->txdseq |= htole16(0x8000); 1705 } else 1706 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1707 1708 /* Compute Tx descriptor checksum. */ 1709 sum = 0; 1710 for (i = 0; i < sizeof(*txd) / 2; i++) 1711 sum ^= ((uint16_t *)txd)[i]; 1712 txd->txdsum = sum; /* NB: already little endian. */ 1713 1714 if (ieee80211_radiotap_active_vap(vap)) { 1715 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1716 1717 tap->wt_flags = 0; 1718 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1719 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1720 ieee80211_radiotap_tx(vap, m0); 1721 } 1722 1723 xferlen = sizeof(*txd) + m0->m_pkthdr.len; 1724 m_copydata(m0, 0, m0->m_pkthdr.len, (caddr_t)&txd[1]); 1725 1726 data->buflen = xferlen; 1727 data->ni = ni; 1728 data->m = m0; 1729 1730 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1731 usbd_transfer_start(xfer); 1732 return (0); 1733} 1734 1735static void 1736urtwn_start(struct ifnet *ifp) 1737{ 1738 struct urtwn_softc *sc = ifp->if_softc; 1739 1740 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1741 return; 1742 URTWN_LOCK(sc); 1743 urtwn_start_locked(ifp, sc); 1744 URTWN_UNLOCK(sc); 1745} 1746 1747static void 1748urtwn_start_locked(struct ifnet *ifp, struct urtwn_softc *sc) 1749{ 1750 struct ieee80211_node *ni; 1751 struct mbuf *m; 1752 struct urtwn_data *bf; 1753 1754 URTWN_ASSERT_LOCKED(sc); 1755 for (;;) { 1756 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1757 if (m == NULL) 1758 break; 1759 bf = urtwn_getbuf(sc); 1760 if (bf == NULL) { 1761 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1762 break; 1763 } 1764 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1765 m->m_pkthdr.rcvif = NULL; 1766 1767 if (urtwn_tx_start(sc, ni, m, bf) != 0) { 1768 ifp->if_oerrors++; 1769 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1770 ieee80211_free_node(ni); 1771 break; 1772 } 1773 1774 sc->sc_txtimer = 5; 1775 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1776 } 1777} 1778 1779static int 1780urtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1781{ 1782 struct urtwn_softc *sc = ifp->if_softc; 1783 struct ieee80211com *ic = ifp->if_l2com; 1784 struct ifreq *ifr = (struct ifreq *) data; 1785 int error = 0, startall = 0; 1786 1787 URTWN_LOCK(sc); 1788 error = (sc->sc_flags & URTWN_DETACHED) ? ENXIO : 0; 1789 URTWN_UNLOCK(sc); 1790 if (error != 0) 1791 return (error); 1792 1793 switch (cmd) { 1794 case SIOCSIFFLAGS: 1795 if (ifp->if_flags & IFF_UP) { 1796 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1797 urtwn_init(ifp->if_softc); 1798 startall = 1; 1799 } 1800 } else { 1801 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1802 urtwn_stop(ifp); 1803 } 1804 if (startall) 1805 ieee80211_start_all(ic); 1806 break; 1807 case SIOCGIFMEDIA: 1808 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1809 break; 1810 case SIOCGIFADDR: 1811 error = ether_ioctl(ifp, cmd, data); 1812 break; 1813 default: 1814 error = EINVAL; 1815 break; 1816 } 1817 return (error); 1818} 1819 1820static int 1821urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 1822 int ndata, int maxsz) 1823{ 1824 int i, error; 1825 1826 for (i = 0; i < ndata; i++) { 1827 struct urtwn_data *dp = &data[i]; 1828 dp->sc = sc; 1829 dp->m = NULL; 1830 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 1831 if (dp->buf == NULL) { 1832 device_printf(sc->sc_dev, 1833 "could not allocate buffer\n"); 1834 error = ENOMEM; 1835 goto fail; 1836 } 1837 dp->ni = NULL; 1838 } 1839 1840 return (0); 1841fail: 1842 urtwn_free_list(sc, data, ndata); 1843 return (error); 1844} 1845 1846static int 1847urtwn_alloc_rx_list(struct urtwn_softc *sc) 1848{ 1849 int error, i; 1850 1851 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 1852 URTWN_RXBUFSZ); 1853 if (error != 0) 1854 return (error); 1855 1856 STAILQ_INIT(&sc->sc_rx_active); 1857 STAILQ_INIT(&sc->sc_rx_inactive); 1858 1859 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 1860 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1861 1862 return (0); 1863} 1864 1865static int 1866urtwn_alloc_tx_list(struct urtwn_softc *sc) 1867{ 1868 int error, i; 1869 1870 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 1871 URTWN_TXBUFSZ); 1872 if (error != 0) 1873 return (error); 1874 1875 STAILQ_INIT(&sc->sc_tx_active); 1876 STAILQ_INIT(&sc->sc_tx_inactive); 1877 STAILQ_INIT(&sc->sc_tx_pending); 1878 1879 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 1880 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 1881 1882 return (0); 1883} 1884 1885static int 1886urtwn_power_on(struct urtwn_softc *sc) 1887{ 1888 uint32_t reg; 1889 int ntries; 1890 1891 /* Wait for autoload done bit. */ 1892 for (ntries = 0; ntries < 1000; ntries++) { 1893 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 1894 break; 1895 DELAY(5); 1896 } 1897 if (ntries == 1000) { 1898 device_printf(sc->sc_dev, 1899 "timeout waiting for chip autoload\n"); 1900 return (ETIMEDOUT); 1901 } 1902 1903 /* Unlock ISO/CLK/Power control register. */ 1904 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 1905 /* Move SPS into PWM mode. */ 1906 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 1907 DELAY(100); 1908 1909 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 1910 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 1911 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 1912 reg | R92C_LDOV12D_CTRL_LDV12_EN); 1913 DELAY(100); 1914 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 1915 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 1916 ~R92C_SYS_ISO_CTRL_MD2PP); 1917 } 1918 1919 /* Auto enable WLAN. */ 1920 urtwn_write_2(sc, R92C_APS_FSMCO, 1921 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1922 for (ntries = 0; ntries < 1000; ntries++) { 1923 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1924 R92C_APS_FSMCO_APFM_ONMAC)) 1925 break; 1926 DELAY(5); 1927 } 1928 if (ntries == 1000) { 1929 device_printf(sc->sc_dev, 1930 "timeout waiting for MAC auto ON\n"); 1931 return (ETIMEDOUT); 1932 } 1933 1934 /* Enable radio, GPIO and LED functions. */ 1935 urtwn_write_2(sc, R92C_APS_FSMCO, 1936 R92C_APS_FSMCO_AFSM_HSUS | 1937 R92C_APS_FSMCO_PDN_EN | 1938 R92C_APS_FSMCO_PFM_ALDN); 1939 /* Release RF digital isolation. */ 1940 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1941 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 1942 1943 /* Initialize MAC. */ 1944 urtwn_write_1(sc, R92C_APSD_CTRL, 1945 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 1946 for (ntries = 0; ntries < 200; ntries++) { 1947 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 1948 R92C_APSD_CTRL_OFF_STATUS)) 1949 break; 1950 DELAY(5); 1951 } 1952 if (ntries == 200) { 1953 device_printf(sc->sc_dev, 1954 "timeout waiting for MAC initialization\n"); 1955 return (ETIMEDOUT); 1956 } 1957 1958 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1959 reg = urtwn_read_2(sc, R92C_CR); 1960 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1961 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1962 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 1963 R92C_CR_ENSEC; 1964 urtwn_write_2(sc, R92C_CR, reg); 1965 1966 urtwn_write_1(sc, 0xfe10, 0x19); 1967 return (0); 1968} 1969 1970static int 1971urtwn_llt_init(struct urtwn_softc *sc) 1972{ 1973 int i, error; 1974 1975 /* Reserve pages [0; R92C_TX_PAGE_COUNT]. */ 1976 for (i = 0; i < R92C_TX_PAGE_COUNT; i++) { 1977 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 1978 return (error); 1979 } 1980 /* NB: 0xff indicates end-of-list. */ 1981 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 1982 return (error); 1983 /* 1984 * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1] 1985 * as ring buffer. 1986 */ 1987 for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) { 1988 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 1989 return (error); 1990 } 1991 /* Make the last page point to the beginning of the ring buffer. */ 1992 error = urtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1); 1993 return (error); 1994} 1995 1996static void 1997urtwn_fw_reset(struct urtwn_softc *sc) 1998{ 1999 uint16_t reg; 2000 int ntries; 2001 2002 /* Tell 8051 to reset itself. */ 2003 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2004 2005 /* Wait until 8051 resets by itself. */ 2006 for (ntries = 0; ntries < 100; ntries++) { 2007 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2008 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2009 return; 2010 DELAY(50); 2011 } 2012 /* Force 8051 reset. */ 2013 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2014} 2015 2016static int 2017urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 2018{ 2019 uint32_t reg; 2020 int off, mlen, error = 0; 2021 2022 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2023 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2024 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2025 2026 off = R92C_FW_START_ADDR; 2027 while (len > 0) { 2028 if (len > 196) 2029 mlen = 196; 2030 else if (len > 4) 2031 mlen = 4; 2032 else 2033 mlen = 1; 2034 /* XXX fix this deconst */ 2035 error = urtwn_write_region_1(sc, off, 2036 __DECONST(uint8_t *, buf), mlen); 2037 if (error != 0) 2038 break; 2039 off += mlen; 2040 buf += mlen; 2041 len -= mlen; 2042 } 2043 return (error); 2044} 2045 2046static int 2047urtwn_load_firmware(struct urtwn_softc *sc) 2048{ 2049 const struct firmware *fw; 2050 const struct r92c_fw_hdr *hdr; 2051 const char *imagename; 2052 const u_char *ptr; 2053 size_t len; 2054 uint32_t reg; 2055 int mlen, ntries, page, error; 2056 2057 URTWN_UNLOCK(sc); 2058 /* Read firmware image from the filesystem. */ 2059 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2060 URTWN_CHIP_UMC_A_CUT) 2061 imagename = "urtwn-rtl8192cfwU"; 2062 else 2063 imagename = "urtwn-rtl8192cfwT"; 2064 2065 fw = firmware_get(imagename); 2066 URTWN_LOCK(sc); 2067 if (fw == NULL) { 2068 device_printf(sc->sc_dev, 2069 "failed loadfirmware of file %s\n", imagename); 2070 return (ENOENT); 2071 } 2072 2073 len = fw->datasize; 2074 2075 if (len < sizeof(*hdr)) { 2076 device_printf(sc->sc_dev, "firmware too short\n"); 2077 error = EINVAL; 2078 goto fail; 2079 } 2080 ptr = fw->data; 2081 hdr = (const struct r92c_fw_hdr *)ptr; 2082 /* Check if there is a valid FW header and skip it. */ 2083 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2084 (le16toh(hdr->signature) >> 4) == 0x92c) { 2085 DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 2086 le16toh(hdr->version), le16toh(hdr->subversion), 2087 hdr->month, hdr->date, hdr->hour, hdr->minute); 2088 ptr += sizeof(*hdr); 2089 len -= sizeof(*hdr); 2090 } 2091 2092 if (urtwn_read_1(sc, R92C_MCUFWDL) & 0x80) { 2093 urtwn_fw_reset(sc); 2094 urtwn_write_1(sc, R92C_MCUFWDL, 0); 2095 } 2096 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2097 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2098 R92C_SYS_FUNC_EN_CPUEN); 2099 urtwn_write_1(sc, R92C_MCUFWDL, 2100 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2101 urtwn_write_1(sc, R92C_MCUFWDL + 2, 2102 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2103 2104 /* Reset the FWDL checksum. */ 2105 urtwn_write_1(sc, R92C_MCUFWDL, 2106 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2107 2108 for (page = 0; len > 0; page++) { 2109 mlen = min(len, R92C_FW_PAGE_SIZE); 2110 error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2111 if (error != 0) { 2112 device_printf(sc->sc_dev, 2113 "could not load firmware page\n"); 2114 goto fail; 2115 } 2116 ptr += mlen; 2117 len -= mlen; 2118 } 2119 urtwn_write_1(sc, R92C_MCUFWDL, 2120 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2121 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2122 2123 /* Wait for checksum report. */ 2124 for (ntries = 0; ntries < 1000; ntries++) { 2125 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2126 break; 2127 DELAY(5); 2128 } 2129 if (ntries == 1000) { 2130 device_printf(sc->sc_dev, 2131 "timeout waiting for checksum report\n"); 2132 error = ETIMEDOUT; 2133 goto fail; 2134 } 2135 2136 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2137 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2138 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2139 /* Wait for firmware readiness. */ 2140 for (ntries = 0; ntries < 1000; ntries++) { 2141 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2142 break; 2143 DELAY(5); 2144 } 2145 if (ntries == 1000) { 2146 device_printf(sc->sc_dev, 2147 "timeout waiting for firmware readiness\n"); 2148 error = ETIMEDOUT; 2149 goto fail; 2150 } 2151fail: 2152 firmware_put(fw, FIRMWARE_UNLOAD); 2153 return (error); 2154} 2155 2156static int 2157urtwn_dma_init(struct urtwn_softc *sc) 2158{ 2159 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2160 uint32_t reg; 2161 int error; 2162 2163 /* Initialize LLT table. */ 2164 error = urtwn_llt_init(sc); 2165 if (error != 0) 2166 return (error); 2167 2168 /* Get Tx queues to USB endpoints mapping. */ 2169 hashq = hasnq = haslq = 0; 2170 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2171 DPRINTFN(2, "USB endpoints mapping 0x%x\n", reg); 2172 if (MS(reg, R92C_USB_EP_HQ) != 0) 2173 hashq = 1; 2174 if (MS(reg, R92C_USB_EP_NQ) != 0) 2175 hasnq = 1; 2176 if (MS(reg, R92C_USB_EP_LQ) != 0) 2177 haslq = 1; 2178 nqueues = hashq + hasnq + haslq; 2179 if (nqueues == 0) 2180 return (EIO); 2181 /* Get the number of pages for each queue. */ 2182 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2183 /* The remaining pages are assigned to the high priority queue. */ 2184 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2185 2186 /* Set number of pages for normal priority queue. */ 2187 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2188 urtwn_write_4(sc, R92C_RQPN, 2189 /* Set number of pages for public queue. */ 2190 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2191 /* Set number of pages for high priority queue. */ 2192 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2193 /* Set number of pages for low priority queue. */ 2194 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2195 /* Load values. */ 2196 R92C_RQPN_LD); 2197 2198 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2199 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2200 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2201 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2202 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2203 2204 /* Set queue to USB pipe mapping. */ 2205 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2206 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2207 if (nqueues == 1) { 2208 if (hashq) 2209 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2210 else if (hasnq) 2211 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2212 else 2213 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2214 } else if (nqueues == 2) { 2215 /* All 2-endpoints configs have a high priority queue. */ 2216 if (!hashq) 2217 return (EIO); 2218 if (hasnq) 2219 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2220 else 2221 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2222 } else 2223 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2224 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2225 2226 /* Set Tx/Rx transfer page boundary. */ 2227 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2228 2229 /* Set Tx/Rx transfer page size. */ 2230 urtwn_write_1(sc, R92C_PBP, 2231 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2232 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2233 return (0); 2234} 2235 2236static void 2237urtwn_mac_init(struct urtwn_softc *sc) 2238{ 2239 int i; 2240 2241 /* Write MAC initialization values. */ 2242 for (i = 0; i < nitems(rtl8192cu_mac); i++) 2243 urtwn_write_1(sc, rtl8192cu_mac[i].reg, rtl8192cu_mac[i].val); 2244} 2245 2246static void 2247urtwn_bb_init(struct urtwn_softc *sc) 2248{ 2249 const struct urtwn_bb_prog *prog; 2250 uint32_t reg; 2251 int i; 2252 2253 /* Enable BB and RF. */ 2254 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2255 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2256 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2257 R92C_SYS_FUNC_EN_DIO_RF); 2258 2259 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2260 2261 urtwn_write_1(sc, R92C_RF_CTRL, 2262 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2263 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2264 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2265 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2266 2267 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2268 urtwn_write_1(sc, 0x15, 0xe9); 2269 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2270 2271 /* Select BB programming based on board type. */ 2272 if (!(sc->chip & URTWN_CHIP_92C)) { 2273 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2274 prog = &rtl8188ce_bb_prog; 2275 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2276 prog = &rtl8188ru_bb_prog; 2277 else 2278 prog = &rtl8188cu_bb_prog; 2279 } else { 2280 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2281 prog = &rtl8192ce_bb_prog; 2282 else 2283 prog = &rtl8192cu_bb_prog; 2284 } 2285 /* Write BB initialization values. */ 2286 for (i = 0; i < prog->count; i++) { 2287 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2288 DELAY(1); 2289 } 2290 2291 if (sc->chip & URTWN_CHIP_92C_1T2R) { 2292 /* 8192C 1T only configuration. */ 2293 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2294 reg = (reg & ~0x00000003) | 0x2; 2295 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2296 2297 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2298 reg = (reg & ~0x00300033) | 0x00200022; 2299 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2300 2301 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2302 reg = (reg & ~0xff000000) | 0x45 << 24; 2303 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2304 2305 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2306 reg = (reg & ~0x000000ff) | 0x23; 2307 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2308 2309 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2310 reg = (reg & ~0x00000030) | 1 << 4; 2311 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2312 2313 reg = urtwn_bb_read(sc, 0xe74); 2314 reg = (reg & ~0x0c000000) | 2 << 26; 2315 urtwn_bb_write(sc, 0xe74, reg); 2316 reg = urtwn_bb_read(sc, 0xe78); 2317 reg = (reg & ~0x0c000000) | 2 << 26; 2318 urtwn_bb_write(sc, 0xe78, reg); 2319 reg = urtwn_bb_read(sc, 0xe7c); 2320 reg = (reg & ~0x0c000000) | 2 << 26; 2321 urtwn_bb_write(sc, 0xe7c, reg); 2322 reg = urtwn_bb_read(sc, 0xe80); 2323 reg = (reg & ~0x0c000000) | 2 << 26; 2324 urtwn_bb_write(sc, 0xe80, reg); 2325 reg = urtwn_bb_read(sc, 0xe88); 2326 reg = (reg & ~0x0c000000) | 2 << 26; 2327 urtwn_bb_write(sc, 0xe88, reg); 2328 } 2329 2330 /* Write AGC values. */ 2331 for (i = 0; i < prog->agccount; i++) { 2332 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2333 prog->agcvals[i]); 2334 DELAY(1); 2335 } 2336 2337 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2338 R92C_HSSI_PARAM2_CCK_HIPWR) 2339 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 2340} 2341 2342void 2343urtwn_rf_init(struct urtwn_softc *sc) 2344{ 2345 const struct urtwn_rf_prog *prog; 2346 uint32_t reg, type; 2347 int i, j, idx, off; 2348 2349 /* Select RF programming based on board type. */ 2350 if (!(sc->chip & URTWN_CHIP_92C)) { 2351 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2352 prog = rtl8188ce_rf_prog; 2353 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2354 prog = rtl8188ru_rf_prog; 2355 else 2356 prog = rtl8188cu_rf_prog; 2357 } else 2358 prog = rtl8192ce_rf_prog; 2359 2360 for (i = 0; i < sc->nrxchains; i++) { 2361 /* Save RF_ENV control type. */ 2362 idx = i / 2; 2363 off = (i % 2) * 16; 2364 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2365 type = (reg >> off) & 0x10; 2366 2367 /* Set RF_ENV enable. */ 2368 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2369 reg |= 0x100000; 2370 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2371 DELAY(1); 2372 /* Set RF_ENV output high. */ 2373 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2374 reg |= 0x10; 2375 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2376 DELAY(1); 2377 /* Set address and data lengths of RF registers. */ 2378 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2379 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2380 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2381 DELAY(1); 2382 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2383 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2384 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2385 DELAY(1); 2386 2387 /* Write RF initialization values for this chain. */ 2388 for (j = 0; j < prog[i].count; j++) { 2389 if (prog[i].regs[j] >= 0xf9 && 2390 prog[i].regs[j] <= 0xfe) { 2391 /* 2392 * These are fake RF registers offsets that 2393 * indicate a delay is required. 2394 */ 2395 usb_pause_mtx(&sc->sc_mtx, 50); 2396 continue; 2397 } 2398 urtwn_rf_write(sc, i, prog[i].regs[j], 2399 prog[i].vals[j]); 2400 DELAY(1); 2401 } 2402 2403 /* Restore RF_ENV control type. */ 2404 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2405 reg &= ~(0x10 << off) | (type << off); 2406 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2407 2408 /* Cache RF register CHNLBW. */ 2409 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2410 } 2411 2412 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2413 URTWN_CHIP_UMC_A_CUT) { 2414 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2415 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2416 } 2417} 2418 2419static void 2420urtwn_cam_init(struct urtwn_softc *sc) 2421{ 2422 /* Invalidate all CAM entries. */ 2423 urtwn_write_4(sc, R92C_CAMCMD, 2424 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2425} 2426 2427static void 2428urtwn_pa_bias_init(struct urtwn_softc *sc) 2429{ 2430 uint8_t reg; 2431 int i; 2432 2433 for (i = 0; i < sc->nrxchains; i++) { 2434 if (sc->pa_setting & (1 << i)) 2435 continue; 2436 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2437 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2438 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2439 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2440 } 2441 if (!(sc->pa_setting & 0x10)) { 2442 reg = urtwn_read_1(sc, 0x16); 2443 reg = (reg & ~0xf0) | 0x90; 2444 urtwn_write_1(sc, 0x16, reg); 2445 } 2446} 2447 2448static void 2449urtwn_rxfilter_init(struct urtwn_softc *sc) 2450{ 2451 /* Initialize Rx filter. */ 2452 /* TODO: use better filter for monitor mode. */ 2453 urtwn_write_4(sc, R92C_RCR, 2454 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2455 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2456 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2457 /* Accept all multicast frames. */ 2458 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2459 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2460 /* Accept all management frames. */ 2461 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2462 /* Reject all control frames. */ 2463 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2464 /* Accept all data frames. */ 2465 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2466} 2467 2468static void 2469urtwn_edca_init(struct urtwn_softc *sc) 2470{ 2471 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 2472 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 2473 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 2474 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 2475 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2476 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2477 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 2478 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 2479} 2480 2481void 2482urtwn_write_txpower(struct urtwn_softc *sc, int chain, 2483 uint16_t power[URTWN_RIDX_COUNT]) 2484{ 2485 uint32_t reg; 2486 2487 /* Write per-CCK rate Tx power. */ 2488 if (chain == 0) { 2489 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2490 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2491 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2492 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2493 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2494 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2495 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2496 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2497 } else { 2498 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2499 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2500 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2501 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2502 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2503 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2504 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2505 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2506 } 2507 /* Write per-OFDM rate Tx power. */ 2508 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2509 SM(R92C_TXAGC_RATE06, power[ 4]) | 2510 SM(R92C_TXAGC_RATE09, power[ 5]) | 2511 SM(R92C_TXAGC_RATE12, power[ 6]) | 2512 SM(R92C_TXAGC_RATE18, power[ 7])); 2513 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2514 SM(R92C_TXAGC_RATE24, power[ 8]) | 2515 SM(R92C_TXAGC_RATE36, power[ 9]) | 2516 SM(R92C_TXAGC_RATE48, power[10]) | 2517 SM(R92C_TXAGC_RATE54, power[11])); 2518 /* Write per-MCS Tx power. */ 2519 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2520 SM(R92C_TXAGC_MCS00, power[12]) | 2521 SM(R92C_TXAGC_MCS01, power[13]) | 2522 SM(R92C_TXAGC_MCS02, power[14]) | 2523 SM(R92C_TXAGC_MCS03, power[15])); 2524 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2525 SM(R92C_TXAGC_MCS04, power[16]) | 2526 SM(R92C_TXAGC_MCS05, power[17]) | 2527 SM(R92C_TXAGC_MCS06, power[18]) | 2528 SM(R92C_TXAGC_MCS07, power[19])); 2529 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2530 SM(R92C_TXAGC_MCS08, power[20]) | 2531 SM(R92C_TXAGC_MCS09, power[21]) | 2532 SM(R92C_TXAGC_MCS10, power[22]) | 2533 SM(R92C_TXAGC_MCS11, power[23])); 2534 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2535 SM(R92C_TXAGC_MCS12, power[24]) | 2536 SM(R92C_TXAGC_MCS13, power[25]) | 2537 SM(R92C_TXAGC_MCS14, power[26]) | 2538 SM(R92C_TXAGC_MCS15, power[27])); 2539} 2540 2541void 2542urtwn_get_txpower(struct urtwn_softc *sc, int chain, 2543 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2544 uint16_t power[URTWN_RIDX_COUNT]) 2545{ 2546 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2547 struct r92c_rom *rom = &sc->rom; 2548 uint16_t cckpow, ofdmpow, htpow, diff, max; 2549 const struct urtwn_txpwr *base; 2550 int ridx, chan, group; 2551 2552 /* Determine channel group. */ 2553 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2554 if (chan <= 3) 2555 group = 0; 2556 else if (chan <= 9) 2557 group = 1; 2558 else 2559 group = 2; 2560 2561 /* Get original Tx power based on board type and RF chain. */ 2562 if (!(sc->chip & URTWN_CHIP_92C)) { 2563 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2564 base = &rtl8188ru_txagc[chain]; 2565 else 2566 base = &rtl8192cu_txagc[chain]; 2567 } else 2568 base = &rtl8192cu_txagc[chain]; 2569 2570 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 2571 if (sc->regulatory == 0) { 2572 for (ridx = 0; ridx <= 3; ridx++) 2573 power[ridx] = base->pwr[0][ridx]; 2574 } 2575 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 2576 if (sc->regulatory == 3) { 2577 power[ridx] = base->pwr[0][ridx]; 2578 /* Apply vendor limits. */ 2579 if (extc != NULL) 2580 max = rom->ht40_max_pwr[group]; 2581 else 2582 max = rom->ht20_max_pwr[group]; 2583 max = (max >> (chain * 4)) & 0xf; 2584 if (power[ridx] > max) 2585 power[ridx] = max; 2586 } else if (sc->regulatory == 1) { 2587 if (extc == NULL) 2588 power[ridx] = base->pwr[group][ridx]; 2589 } else if (sc->regulatory != 2) 2590 power[ridx] = base->pwr[0][ridx]; 2591 } 2592 2593 /* Compute per-CCK rate Tx power. */ 2594 cckpow = rom->cck_tx_pwr[chain][group]; 2595 for (ridx = 0; ridx <= 3; ridx++) { 2596 power[ridx] += cckpow; 2597 if (power[ridx] > R92C_MAX_TX_PWR) 2598 power[ridx] = R92C_MAX_TX_PWR; 2599 } 2600 2601 htpow = rom->ht40_1s_tx_pwr[chain][group]; 2602 if (sc->ntxchains > 1) { 2603 /* Apply reduction for 2 spatial streams. */ 2604 diff = rom->ht40_2s_tx_pwr_diff[group]; 2605 diff = (diff >> (chain * 4)) & 0xf; 2606 htpow = (htpow > diff) ? htpow - diff : 0; 2607 } 2608 2609 /* Compute per-OFDM rate Tx power. */ 2610 diff = rom->ofdm_tx_pwr_diff[group]; 2611 diff = (diff >> (chain * 4)) & 0xf; 2612 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 2613 for (ridx = 4; ridx <= 11; ridx++) { 2614 power[ridx] += ofdmpow; 2615 if (power[ridx] > R92C_MAX_TX_PWR) 2616 power[ridx] = R92C_MAX_TX_PWR; 2617 } 2618 2619 /* Compute per-MCS Tx power. */ 2620 if (extc == NULL) { 2621 diff = rom->ht20_tx_pwr_diff[group]; 2622 diff = (diff >> (chain * 4)) & 0xf; 2623 htpow += diff; /* HT40->HT20 correction. */ 2624 } 2625 for (ridx = 12; ridx <= 27; ridx++) { 2626 power[ridx] += htpow; 2627 if (power[ridx] > R92C_MAX_TX_PWR) 2628 power[ridx] = R92C_MAX_TX_PWR; 2629 } 2630#ifdef URTWN_DEBUG 2631 if (urtwn_debug >= 4) { 2632 /* Dump per-rate Tx power values. */ 2633 printf("Tx power for chain %d:\n", chain); 2634 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) 2635 printf("Rate %d = %u\n", ridx, power[ridx]); 2636 } 2637#endif 2638} 2639 2640void 2641urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 2642 struct ieee80211_channel *extc) 2643{ 2644 uint16_t power[URTWN_RIDX_COUNT]; 2645 int i; 2646 2647 for (i = 0; i < sc->ntxchains; i++) { 2648 /* Compute per-rate Tx power values. */ 2649 urtwn_get_txpower(sc, i, c, extc, power); 2650 /* Write per-rate Tx power values to hardware. */ 2651 urtwn_write_txpower(sc, i, power); 2652 } 2653} 2654 2655static void 2656urtwn_scan_start(struct ieee80211com *ic) 2657{ 2658 /* XXX do nothing? */ 2659} 2660 2661static void 2662urtwn_scan_end(struct ieee80211com *ic) 2663{ 2664 /* XXX do nothing? */ 2665} 2666 2667static void 2668urtwn_set_channel(struct ieee80211com *ic) 2669{ 2670 struct urtwn_softc *sc = ic->ic_ifp->if_softc; 2671 2672 URTWN_LOCK(sc); 2673 urtwn_set_chan(sc, ic->ic_curchan, NULL); 2674 URTWN_UNLOCK(sc); 2675} 2676 2677static void 2678urtwn_update_mcast(struct ifnet *ifp) 2679{ 2680 /* XXX do nothing? */ 2681} 2682 2683static void 2684urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 2685 struct ieee80211_channel *extc) 2686{ 2687 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2688 uint32_t reg; 2689 u_int chan; 2690 int i; 2691 2692 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2693 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 2694 device_printf(sc->sc_dev, 2695 "%s: invalid channel %x\n", __func__, chan); 2696 return; 2697 } 2698 2699 /* Set Tx power for this new channel. */ 2700 urtwn_set_txpower(sc, c, extc); 2701 2702 for (i = 0; i < sc->nrxchains; i++) { 2703 urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 2704 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 2705 } 2706#ifndef IEEE80211_NO_HT 2707 if (extc != NULL) { 2708 /* Is secondary channel below or above primary? */ 2709 int prichlo = c->ic_freq < extc->ic_freq; 2710 2711 urtwn_write_1(sc, R92C_BWOPMODE, 2712 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 2713 2714 reg = urtwn_read_1(sc, R92C_RRSR + 2); 2715 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 2716 urtwn_write_1(sc, R92C_RRSR + 2, reg); 2717 2718 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 2719 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 2720 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 2721 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 2722 2723 /* Set CCK side band. */ 2724 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 2725 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 2726 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 2727 2728 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 2729 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 2730 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 2731 2732 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 2733 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 2734 ~R92C_FPGA0_ANAPARAM2_CBW20); 2735 2736 reg = urtwn_bb_read(sc, 0x818); 2737 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 2738 urtwn_bb_write(sc, 0x818, reg); 2739 2740 /* Select 40MHz bandwidth. */ 2741 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 2742 (sc->rf_chnlbw[0] & ~0xfff) | chan); 2743 } else 2744#endif 2745 { 2746 urtwn_write_1(sc, R92C_BWOPMODE, 2747 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 2748 2749 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 2750 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 2751 urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 2752 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 2753 2754 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 2755 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 2756 R92C_FPGA0_ANAPARAM2_CBW20); 2757 2758 /* Select 20MHz bandwidth. */ 2759 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 2760 (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan); 2761 } 2762} 2763 2764static void 2765urtwn_iq_calib(struct urtwn_softc *sc) 2766{ 2767 /* TODO */ 2768} 2769 2770static void 2771urtwn_lc_calib(struct urtwn_softc *sc) 2772{ 2773 uint32_t rf_ac[2]; 2774 uint8_t txmode; 2775 int i; 2776 2777 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 2778 if ((txmode & 0x70) != 0) { 2779 /* Disable all continuous Tx. */ 2780 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 2781 2782 /* Set RF mode to standby mode. */ 2783 for (i = 0; i < sc->nrxchains; i++) { 2784 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 2785 urtwn_rf_write(sc, i, R92C_RF_AC, 2786 RW(rf_ac[i], R92C_RF_AC_MODE, 2787 R92C_RF_AC_MODE_STANDBY)); 2788 } 2789 } else { 2790 /* Block all Tx queues. */ 2791 urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 2792 } 2793 /* Start calibration. */ 2794 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 2795 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 2796 2797 /* Give calibration the time to complete. */ 2798 usb_pause_mtx(&sc->sc_mtx, 100); 2799 2800 /* Restore configuration. */ 2801 if ((txmode & 0x70) != 0) { 2802 /* Restore Tx mode. */ 2803 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 2804 /* Restore RF mode. */ 2805 for (i = 0; i < sc->nrxchains; i++) 2806 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 2807 } else { 2808 /* Unblock all Tx queues. */ 2809 urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 2810 } 2811} 2812 2813static void 2814urtwn_init_locked(void *arg) 2815{ 2816 struct urtwn_softc *sc = arg; 2817 struct ifnet *ifp = sc->sc_ifp; 2818 uint32_t reg; 2819 int error; 2820 2821 URTWN_ASSERT_LOCKED(sc); 2822 2823 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2824 urtwn_stop_locked(ifp); 2825 2826 /* Init firmware commands ring. */ 2827 sc->fwcur = 0; 2828 2829 /* Allocate Tx/Rx buffers. */ 2830 error = urtwn_alloc_rx_list(sc); 2831 if (error != 0) 2832 goto fail; 2833 2834 error = urtwn_alloc_tx_list(sc); 2835 if (error != 0) 2836 goto fail; 2837 2838 /* Power on adapter. */ 2839 error = urtwn_power_on(sc); 2840 if (error != 0) 2841 goto fail; 2842 2843 /* Initialize DMA. */ 2844 error = urtwn_dma_init(sc); 2845 if (error != 0) 2846 goto fail; 2847 2848 /* Set info size in Rx descriptors (in 64-bit words). */ 2849 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 2850 2851 /* Init interrupts. */ 2852 urtwn_write_4(sc, R92C_HISR, 0xffffffff); 2853 urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 2854 2855 /* Set MAC address. */ 2856 urtwn_write_region_1(sc, R92C_MACID, IF_LLADDR(ifp), 2857 IEEE80211_ADDR_LEN); 2858 2859 /* Set initial network type. */ 2860 reg = urtwn_read_4(sc, R92C_CR); 2861 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 2862 urtwn_write_4(sc, R92C_CR, reg); 2863 2864 urtwn_rxfilter_init(sc); 2865 2866 reg = urtwn_read_4(sc, R92C_RRSR); 2867 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 2868 urtwn_write_4(sc, R92C_RRSR, reg); 2869 2870 /* Set short/long retry limits. */ 2871 urtwn_write_2(sc, R92C_RL, 2872 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 2873 2874 /* Initialize EDCA parameters. */ 2875 urtwn_edca_init(sc); 2876 2877 /* Setup rate fallback. */ 2878 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 2879 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 2880 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 2881 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 2882 2883 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 2884 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 2885 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 2886 /* Set ACK timeout. */ 2887 urtwn_write_1(sc, R92C_ACKTO, 0x40); 2888 2889 /* Setup USB aggregation. */ 2890 reg = urtwn_read_4(sc, R92C_TDECTRL); 2891 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 2892 urtwn_write_4(sc, R92C_TDECTRL, reg); 2893 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 2894 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 2895 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 2896 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 2897 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 2898 R92C_USB_SPECIAL_OPTION_AGG_EN); 2899 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 2900 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 2901 urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 2902 urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 2903 2904 /* Initialize beacon parameters. */ 2905 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 2906 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 2907 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 2908 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 2909 2910 /* Setup AMPDU aggregation. */ 2911 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 2912 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 2913 urtwn_write_2(sc, 0x4ca, 0x0708); 2914 2915 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 2916 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 2917 2918 /* Load 8051 microcode. */ 2919 error = urtwn_load_firmware(sc); 2920 if (error != 0) 2921 goto fail; 2922 2923 /* Initialize MAC/BB/RF blocks. */ 2924 urtwn_mac_init(sc); 2925 urtwn_bb_init(sc); 2926 urtwn_rf_init(sc); 2927 2928 /* Turn CCK and OFDM blocks on. */ 2929 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 2930 reg |= R92C_RFMOD_CCK_EN; 2931 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 2932 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 2933 reg |= R92C_RFMOD_OFDM_EN; 2934 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 2935 2936 /* Clear per-station keys table. */ 2937 urtwn_cam_init(sc); 2938 2939 /* Enable hardware sequence numbering. */ 2940 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 2941 2942 /* Perform LO and IQ calibrations. */ 2943 urtwn_iq_calib(sc); 2944 /* Perform LC calibration. */ 2945 urtwn_lc_calib(sc); 2946 2947 /* Fix USB interference issue. */ 2948 urtwn_write_1(sc, 0xfe40, 0xe0); 2949 urtwn_write_1(sc, 0xfe41, 0x8d); 2950 urtwn_write_1(sc, 0xfe42, 0x80); 2951 2952 urtwn_pa_bias_init(sc); 2953 2954 /* Initialize GPIO setting. */ 2955 urtwn_write_1(sc, R92C_GPIO_MUXCFG, 2956 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 2957 2958 /* Fix for lower temperature. */ 2959 urtwn_write_1(sc, 0x15, 0xe9); 2960 2961 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 2962 2963 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2964 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2965 2966 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 2967fail: 2968 return; 2969} 2970 2971static void 2972urtwn_init(void *arg) 2973{ 2974 struct urtwn_softc *sc = arg; 2975 2976 URTWN_LOCK(sc); 2977 urtwn_init_locked(arg); 2978 URTWN_UNLOCK(sc); 2979} 2980 2981static void 2982urtwn_stop_locked(struct ifnet *ifp) 2983{ 2984 struct urtwn_softc *sc = ifp->if_softc; 2985 2986 URTWN_ASSERT_LOCKED(sc); 2987 2988 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2989 2990 callout_stop(&sc->sc_watchdog_ch); 2991 urtwn_abort_xfers(sc); 2992} 2993 2994static void 2995urtwn_stop(struct ifnet *ifp) 2996{ 2997 struct urtwn_softc *sc = ifp->if_softc; 2998 2999 URTWN_LOCK(sc); 3000 urtwn_stop_locked(ifp); 3001 URTWN_UNLOCK(sc); 3002} 3003 3004static void 3005urtwn_abort_xfers(struct urtwn_softc *sc) 3006{ 3007 int i; 3008 3009 URTWN_ASSERT_LOCKED(sc); 3010 3011 /* abort any pending transfers */ 3012 for (i = 0; i < URTWN_N_TRANSFER; i++) 3013 usbd_transfer_stop(sc->sc_xfer[i]); 3014} 3015 3016static int 3017urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3018 const struct ieee80211_bpf_params *params) 3019{ 3020 struct ieee80211com *ic = ni->ni_ic; 3021 struct ifnet *ifp = ic->ic_ifp; 3022 struct urtwn_softc *sc = ifp->if_softc; 3023 struct urtwn_data *bf; 3024 3025 /* prevent management frames from being sent if we're not ready */ 3026 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3027 m_freem(m); 3028 ieee80211_free_node(ni); 3029 return (ENETDOWN); 3030 } 3031 URTWN_LOCK(sc); 3032 bf = urtwn_getbuf(sc); 3033 if (bf == NULL) { 3034 ieee80211_free_node(ni); 3035 m_freem(m); 3036 URTWN_UNLOCK(sc); 3037 return (ENOBUFS); 3038 } 3039 3040 ifp->if_opackets++; 3041 if (urtwn_tx_start(sc, ni, m, bf) != 0) { 3042 ieee80211_free_node(ni); 3043 ifp->if_oerrors++; 3044 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3045 URTWN_UNLOCK(sc); 3046 return (EIO); 3047 } 3048 URTWN_UNLOCK(sc); 3049 3050 sc->sc_txtimer = 5; 3051 return (0); 3052} 3053 3054static device_method_t urtwn_methods[] = { 3055 /* Device interface */ 3056 DEVMETHOD(device_probe, urtwn_match), 3057 DEVMETHOD(device_attach, urtwn_attach), 3058 DEVMETHOD(device_detach, urtwn_detach), 3059 3060 { 0, 0 } 3061}; 3062 3063static driver_t urtwn_driver = { 3064 "urtwn", 3065 urtwn_methods, 3066 sizeof(struct urtwn_softc) 3067}; 3068 3069static devclass_t urtwn_devclass; 3070 3071DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 3072MODULE_DEPEND(urtwn, usb, 1, 1, 1); 3073MODULE_DEPEND(urtwn, wlan, 1, 1, 1); 3074MODULE_DEPEND(urtwn, firmware, 1, 1, 1); 3075MODULE_VERSION(urtwn, 1); 3076